Re: [PATCH v1 3/4] aarch64/versal: Port JFFS2 GQSPI NOR Driver from Zynqmp
I agree with all of what you have said. I think it's best to leave this out for
the moment and wait for the generic JFFS2 driver. If a need arises for it we
can come back to it.
--- Original Message ---
On Friday, October 20th, 2023 at 12:43 AM, Kinsey Moore
wrote:
> It looks like this is an older version of the JFFS2 XQspiPsu adapter. The
> only real difference other than this being dated is the IRQ used. I'd rather
> that be factored out and make the existing code shared. Beyond that, both
> this and the ZynqMP version it was pulled from would be obviated by a generic
> JFFS2 NOR flashdev driver which I can go ahead and post. I was hoping to make
> it NAND compatible before posting, but I just haven't had the time.
> Alternatively, I can send it to you for testing if you'd prefer.
>
> On Thu, Oct 19, 2023 at 12:43 AM wrote:
>
>> From: Aaron Nyholm
>>
>> ---
>> .../include/bsp/jffs2_xqspipsu.h | 62 ++
>> bsps/aarch64/xilinx-versal/jffs2_xqspipsu.c | 190 ++
>> spec/build/bsps/aarch64/xilinx-versal/grp.yml | 4 +
>> .../aarch64/xilinx-versal/objjffs2qspinor.yml | 20 ++
>> .../aarch64/xilinx-versal/objxqspiflash.yml | 2 -
>> 5 files changed, 276 insertions(+), 2 deletions(-)
>> create mode 100644 bsps/aarch64/xilinx-versal/include/bsp/jffs2_xqspipsu.h
>> create mode 100644 bsps/aarch64/xilinx-versal/jffs2_xqspipsu.c
>> create mode 100644 spec/build/bsps/aarch64/xilinx-versal/objjffs2qspinor.yml
>>
>> diff --git a/bsps/aarch64/xilinx-versal/include/bsp/jffs2_xqspipsu.h
>> b/bsps/aarch64/xilinx-versal/include/bsp/jffs2_xqspipsu.h
>> new file mode 100644
>> index 00..4a1cdac7a6
>> --- /dev/null
>> +++ b/bsps/aarch64/xilinx-versal/include/bsp/jffs2_xqspipsu.h
>> @@ -0,0 +1,62 @@
>> +/* SPDX-License-Identifier: BSD-2-Clause */
>> +
>> +/**
>> + * @file
>> + *
>> + * @ingroup RTEMSBSPsAArch64XilinxVersal
>> + *
>> + * @brief Xilinx Versal QSPI JFFS2 flash driver definitions
>> + */
>> +
>> +/*
>> + * Copyright (C) 2023 Aaron Nyholm
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions
>> + * are met:
>> + * 1. Redistributions of source code must retain the above copyright
>> + * notice, this list of conditions and the following disclaimer.
>> + * 2. Redistributions in binary form must reproduce the above copyright
>> + * notice, this list of conditions and the following disclaimer in the
>> + * documentation and/or other materials provided with the distribution.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
>> IS"
>> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>> PURPOSE
>> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
>> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
>> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
>> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
>> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
>> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
>> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
>> THE
>> + * POSSIBILITY OF SUCH DAMAGE.
>> + */
>> +
>> +#ifndef LIBBSP_XILINX_VERSAL_JFFS2_XQSPIPSU_H
>> +#define LIBBSP_XILINX_VERSAL_JFFS2_XQSPIPSU_H
>> +
>> +#include
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif /* __cplusplus */
>> +
>> +/**
>> + * @brief Mount jffs2 filesystem.
>> + *
>> + * @param[in] mount_dir The directory to mount the filesystem at.
>> + * @param[in] qspipsu_ptr A pointer to an initialized QSPI instance.
>> + *
>> + * @retval 0 Successful operation. Negative number otherwise.
>> + */
>> +int xilinx_versal_nor_jffs2_initialize(
>> + const char *mount_dir,
>> + XQspiPsu *qspipsu_ptr
>> +);
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif /* __cplusplus */
>> +
>> +#endif /* LIBBSP_XILINX_VERSAL_JFFS2_XQSPIPSU_H */
>> diff --git a/bsps/aarch64/xilinx-versal/jffs2_xqspipsu.c
>> b/bsps/aarch64/xilinx-versal/jffs2_xqspipsu.c
>> new file mode 100644
>> index 00..c84280b420
>> --- /dev/null
>> +++ b/bsps/aarch64/xilinx-versal/jffs2_xqspipsu.c
>> @@ -0,0 +1,190 @@
>> +/* SPDX-License-Identifier: BSD-2-Clause */
>> +
>> +/*
>> + * Copyright (C) 2023 Aaron Nyholm
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions
>> + * are met:
>> + * 1. Redistributions of source code must retain the above copyright
>> + * notice, this list of conditions and the following disclaimer.
>> + * 2. Redistributions in binary form must reproduce the above copyright
>> + * notice, this list of conditions and the following disclaimer in the
>> + * documentation and/or other materials provided with the d
Re: [PATCH] fixed warning related to spstdc17
that didn't work but i'm thinking of defining a char array that is equal
to the size of the processor lock and the isr lock? i figured that the
processor lock is 64 bits and isr lock is a one bit?
I'm confused on how to make an api define do you have a file i can look at?
On Tue, 24 Oct 2023 at 08:31, Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 24.10.23 14:02, zack leung wrote:
> > hi! sabestian did you mean the size of the structure?
>
> Yes, one option to get rid of the empty structures is to just provide
> typedefs, for example:
>
> #if defined(RTEMS_SMP)
> typedef struct Scheduler_Context {
> ...
> } Scheduler_Context;
> #else
> typedef struct Scheduler_Context Scheduler_Context;
> #endif
>
> Then you have to make sure that #if !defined(RTEMS_SMP) no objects of
> this type are used.
>
> For the ISR locks we can do something similar. However, in this case
> this affects also the API, so we probably need an API define for this as
> well. Suggestion: RTEMS_HAVE_INTERRUPT_LOCK_OBJECTS.
>
> The user can then do something like this:
>
> struct app {
>...
> #if defined(RTEMS_HAVE_INTERRUPT_LOCK_OBJECTS)
>rtems_interrupt_lock lock;
> #endif
>...
> }
>
> --
> embedded brains GmbH
> Herr Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> phone: +49-89-18 94 741 - 16
> fax: +49-89-18 94 741 - 08
>
> Registergericht: Amtsgericht München
> Registernummer: HRB 157899
> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> Unsere Datenschutzerklärung finden Sie hier:
> https://embedded-brains.de/datenschutzerklaerung/
>
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[PATCH v3 1/2] bsps/clock: Import Xilinx TTC hardware definitions
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
---
bsps/include/dev/clock/VERSION | 24
bsps/include/dev/clock/xttcps_hw.h | 207 +
2 files changed, 231 insertions(+)
create mode 100644 bsps/include/dev/clock/VERSION
create mode 100644 bsps/include/dev/clock/xttcps_hw.h
diff --git a/bsps/include/dev/clock/VERSION b/bsps/include/dev/clock/VERSION
new file mode 100644
index 00..1ccbe7c216
--- /dev/null
+++ b/bsps/include/dev/clock/VERSION
@@ -0,0 +1,24 @@
+The information in this file describes the source of
+bsps/include/dev/clock/xttcps_hw.h.
+
+Import from:
+
+https://github.com/Xilinx/embeddedsw.git
+
+commit 5330a64c8efd14f0eef09befdbb8d3d738c33ec2
+Refs:
+Author: Nicole Baze
+AuthorDate: Mon Oct 3 13:27:19 2022 -0700
+Commit: Siva Addepalli
+CommitDate: Fri Oct 7 10:26:16 2022 +0530
+
+xilpm: versal: server: Fix bug in AIE2 zeroization
+
+There is a bug in AIE2 zeriozation function when polling for memory
+zeroization complete. Currently the entire memory register is being
+checked against zero but instead we need to check the bits specific
+to the memory tiles. This patch updates the zeroization check by
+adding a mask so that only the desired bits are checked for zero.
+
+Signed-off-by: Nicole Baze
+Acked-by: Jesus De Haro
diff --git a/bsps/include/dev/clock/xttcps_hw.h
b/bsps/include/dev/clock/xttcps_hw.h
new file mode 100644
index 00..0559c4a00c
--- /dev/null
+++ b/bsps/include/dev/clock/xttcps_hw.h
@@ -0,0 +1,207 @@
+/**
+* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+
+/*/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_15
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver WhoDate Changes
+* - -- -
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 srm10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+* mask 16 bit values for zynq and 32 bit values for
+* zynq ultrascale+mpsoc "
+*
+*
+**/
+
+#ifndef XTTCPS_HW_H/* prevent circular inclusions */
+#define XTTCPS_HW_H/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include Files */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/** Constant Definitions */
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET0xU /**< Clock Control
Register */
+#define XTTCPS_CNT_CNTRL_OFFSET0x000CU /**< Counter
Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET 0x0018U /**< Current Counter Value
*/
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x0024U /**< Interval Count Value
*/
+#define XTTCPS_MATCH_0_OFFSET 0x0030U /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET 0x003CU /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET 0x0048U /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET 0x0054U /**< Interrupt
Status Register */
+#define XTTCPS_IER_OFFSET 0x0060U /**< Interrupt
Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK0x0001U /**< Prescale
enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x001EU /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale
shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE16U /**<
Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK 0x0020U /**< Clock source
*/
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x0040U /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK 0x0001U /**< Disable the
counter */
+#
[PATCH v3 2/2] bsps/arm: Add BSP for ZynqMP RPU
From: Philip Kirkpatrick --- .../console/console-config.c | 129 ++ bsps/arm/xilinx-zynqmp-rpu/include/bsp.h | 96 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h | 65 + bsps/arm/xilinx-zynqmp-rpu/include/tm27.h | 54 + bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c | 43 bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c | 48 .../xilinx-zynqmp-rpu/start/bspstarthooks.c | 66 + .../arm/xilinx-zynqmp-rpu/start/bspstartmpu.c | 143 +++ bsps/include/dev/clock/xttcps_hw.h| 3 + bsps/include/peripheral_maps/xilinx_zynqmp.h | 118 + bsps/shared/dev/clock/xil-ttc.c | 229 ++ spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml | 21 ++ .../arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml | 96 .../bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml | 46 .../arm/xilinx-zynqmp-rpu/optclkfastidle.yml | 21 ++ .../bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml | 17 ++ .../bsps/arm/xilinx-zynqmp-rpu/optconirq.yml | 16 ++ .../bsps/arm/xilinx-zynqmp-rpu/optint0len.yml | 18 ++ .../bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml | 18 ++ .../bsps/arm/xilinx-zynqmp-rpu/optint1len.yml | 18 ++ .../bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml | 18 ++ .../arm/xilinx-zynqmp-rpu/optnocachelen.yml | 19 ++ .../arm/xilinx-zynqmp-rpu/optprocunitrpu.yml | 17 ++ .../bsps/arm/xilinx-zynqmp-rpu/optramlen.yml | 21 ++ .../bsps/arm/xilinx-zynqmp-rpu/optramori.yml | 19 ++ .../arm/xilinx-zynqmp-rpu/optresetvec.yml | 16 ++ spec/build/bsps/objxilinxsupportr5.yml| 3 +- spec/build/bsps/optxilsupportpath.yml | 3 +- 28 files changed, 1379 insertions(+), 2 deletions(-) create mode 100644 bsps/arm/xilinx-zynqmp-rpu/console/console-config.c create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/tm27.h create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c create mode 100644 bsps/include/peripheral_maps/xilinx_zynqmp.h create mode 100644 bsps/shared/dev/clock/xil-ttc.c create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c new file mode 100644 index 00..f52e008f2b --- /dev/null +++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c @@ -0,0 +1,129 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013, 2017 embedded brains GmbH + * + * Copyright (C) 2019 DornerWorks + * + * Written by Jeff Kubascik + *and Josh Whitehead + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTI
[PATCH v3 0/2] Add BSP for Cortex-R5 RPU
Changes from v2: * Fixed platform map installation * Fixed warnings in bspstartmpu.c * Fixed BSP internal function prototype name * Base Xilinx support contained in first two patches is now upstream ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP
Great! I'll get those integrated and post a v3.
Thanks,
Kinsey
On Tue, Oct 24, 2023 at 9:10 AM Philip Kirkpatrick <
p.kirkpatr...@reflexaerospace.com> wrote:
> Kinsey,
>
> I looked this over and built and tested it on actual hardware. I made the
> minor changes below, but afterwards it worked as expected. The change to
> `bspmercuryxu5.yml` was required to allow my application to find
> `peripheral_maps/xilinx_zynqmp.h`. The other changes were not required,
> but cleaned up some warnings.
>
> ---
> bsps/arm/xilinx-zynqmp-rpu/include/bsp.h| 2 +-
> bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c | 6 +++---
> spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml | 4 +++-
> 3 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> index db3997677f..e386bd4b26 100644
> --- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> +++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> @@ -81,7 +81,7 @@ extern "C" {
> *
> * Provide in the application to override the defaults in the BSP.
> */
> -BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
> +BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
>
> void zynqmp_debug_console_flush(void);
>
> diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> index 7c927058f7..8c591890bf 100644
> --- a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> +++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> @@ -123,19 +123,19 @@ static BSP_START_TEXT_SECTION void
> zynqmp_configure_mpu_sections(void)
>Xil_SetMPURegion(addr, size, attrib);
>
>// Add RO region for RO section
> - addr = bsp_section_rodata_begin;
> + addr = (u32)bsp_section_rodata_begin;
>size = bsp_section_rodata_end - bsp_section_rodata_begin;
>attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;
>Xil_SetMPURegion(addr, size, attrib);
>
>// Add no cache region for no cache section
> - addr = bsp_section_nocache_begin;
> + addr = (u32)bsp_section_nocache_begin;
>size = bsp_section_nocache_end - bsp_section_nocache_begin;
>attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
>Xil_SetMPURegion(addr, size, attrib);
>
>// Add no cache region for no cache no load section
> - addr = bsp_section_nocachenoload_begin;
> + addr = (u32)bsp_section_nocachenoload_begin;
>size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
>attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
>Xil_SetMPURegion(addr, size, attrib);
> diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> index 342cfdea57..595c1ad507 100644
> --- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> @@ -16,10 +16,12 @@ install:
>source:
>- bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
>- bsps/include/dev/clock/xttcps_hw.h
> - - bsps/include/peripheral_maps/xilinx_zynqmp.h
> - destination: ${BSP_INCLUDEDIR}/bsp
>source:
>- bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
> +- destination: ${BSP_INCLUDEDIR}/peripheral_maps
> + source:
> + - bsps/include/peripheral_maps/xilinx_zynqmp.h
> links:
> - role: build-dependency
>uid: ../grp
> --
>
>
> On Fri, Oct 20, 2023 at 7:03 PM Kinsey Moore
> wrote:
>
>> Philip,
>> When you get a chance, could you verify that this refactoring meets your
>> expectations as far as functionality? I'm especially interested in whether
>> the timer interrupts behave as you expect them to on hardware. I don't mind
>> getting the Xilinx support code updates committed, but I'd like some
>> feedback on the BSP itself.
>>
>> Kinsey
>>
>> On Thu, Oct 12, 2023 at 12:02 PM Kinsey Moore
>> wrote:
>>
>>> Changes from v1 (originally submitted by Philip Kirkpatrick):
>>> Refactoring:
>>> * import Xilinx code before modification
>>> * better use the existing Xilinx support code
>>> Other:
>>> * An additional patch to add cache support (also from Philip) has been
>>> integrated and refactored
>>>
>>> This has been tested on Xilinx's QEMU with Xilinx's device tree
>>> definitions using the following command line options to QEMU:
>>> -no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \
>>> -device loader,file=,cpu-num=4 \
>>> -device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \
>>> -device loader,addr=0xff9a,data=0x8218,data-len=4 \
>>> -hw-dtb /LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \
>>> -m 4096 -display none
>>>
>>> hello.exe and ts-validation-cache.exe operated as expected. Ticker
>>> produced output, but the timing and content was incorrect on QEMU.
>>>
>>>
>>> ___
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>>> devel@rtems.org
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Re: [PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP
Kinsey,
I looked this over and built and tested it on actual hardware. I made the
minor changes below, but afterwards it worked as expected. The change to
`bspmercuryxu5.yml` was required to allow my application to find
`peripheral_maps/xilinx_zynqmp.h`. The other changes were not required,
but cleaned up some warnings.
---
bsps/arm/xilinx-zynqmp-rpu/include/bsp.h| 2 +-
bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c | 6 +++---
spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml | 4 +++-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index db3997677f..e386bd4b26 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -81,7 +81,7 @@ extern "C" {
*
* Provide in the application to override the defaults in the BSP.
*/
-BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
+BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
void zynqmp_debug_console_flush(void);
diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
index 7c927058f7..8c591890bf 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
@@ -123,19 +123,19 @@ static BSP_START_TEXT_SECTION void
zynqmp_configure_mpu_sections(void)
Xil_SetMPURegion(addr, size, attrib);
// Add RO region for RO section
- addr = bsp_section_rodata_begin;
+ addr = (u32)bsp_section_rodata_begin;
size = bsp_section_rodata_end - bsp_section_rodata_begin;
attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;
Xil_SetMPURegion(addr, size, attrib);
// Add no cache region for no cache section
- addr = bsp_section_nocache_begin;
+ addr = (u32)bsp_section_nocache_begin;
size = bsp_section_nocache_end - bsp_section_nocache_begin;
attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
Xil_SetMPURegion(addr, size, attrib);
// Add no cache region for no cache no load section
- addr = bsp_section_nocachenoload_begin;
+ addr = (u32)bsp_section_nocachenoload_begin;
size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
Xil_SetMPURegion(addr, size, attrib);
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
index 342cfdea57..595c1ad507 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
@@ -16,10 +16,12 @@ install:
source:
- bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
- bsps/include/dev/clock/xttcps_hw.h
- - bsps/include/peripheral_maps/xilinx_zynqmp.h
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
+- destination: ${BSP_INCLUDEDIR}/peripheral_maps
+ source:
+ - bsps/include/peripheral_maps/xilinx_zynqmp.h
links:
- role: build-dependency
uid: ../grp
--
On Fri, Oct 20, 2023 at 7:03 PM Kinsey Moore
wrote:
> Philip,
> When you get a chance, could you verify that this refactoring meets your
> expectations as far as functionality? I'm especially interested in whether
> the timer interrupts behave as you expect them to on hardware. I don't mind
> getting the Xilinx support code updates committed, but I'd like some
> feedback on the BSP itself.
>
> Kinsey
>
> On Thu, Oct 12, 2023 at 12:02 PM Kinsey Moore
> wrote:
>
>> Changes from v1 (originally submitted by Philip Kirkpatrick):
>> Refactoring:
>> * import Xilinx code before modification
>> * better use the existing Xilinx support code
>> Other:
>> * An additional patch to add cache support (also from Philip) has been
>> integrated and refactored
>>
>> This has been tested on Xilinx's QEMU with Xilinx's device tree
>> definitions using the following command line options to QEMU:
>> -no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \
>> -device loader,file=,cpu-num=4 \
>> -device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \
>> -device loader,addr=0xff9a,data=0x8218,data-len=4 \
>> -hw-dtb /LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \
>> -m 4096 -display none
>>
>> hello.exe and ts-validation-cache.exe operated as expected. Ticker
>> produced output, but the timing and content was incorrect on QEMU.
>>
>>
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>>
>
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[PATCH] microblaze: Move interrupt context save to BSP
From: Sam Price The interrupt context save is now done in the BSP. This avoids an issue where a register is modified by the interrupt handler before it is saved. Specifically, the MSR register was modified by the `addi` instruction in the interrupt handler before the MSR was saved. This caused the MSR to be saved with the wrong value. Closes #4962 --- .../start/_interrupt_handler.S| 21 +++ cpukit/score/cpu/microblaze/cpu_asm.S | 17 --- 2 files changed, 17 insertions(+), 21 deletions(-) diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S index c24807c3e0..cf95eaee2f 100644 --- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -45,11 +45,24 @@ /* Subtract stack frame */ addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) - swi r5, r1, 8 + /* Save stack frame */ + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + mfs r3, rmsr + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR /* Indicate unknown interrupt source */ - addi r5, r0, 0xFF - braid _ISR_Handler - nop + addik r5, r0, 0xFF #endif /* __rtems__ */ diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S index 0a2c5d8fff..b0bb2b1fa1 100644 --- a/cpukit/score/cpu/microblaze/cpu_asm.S +++ b/cpukit/score/cpu/microblaze/cpu_asm.S @@ -41,28 +41,11 @@ .align 2 _ISR_Handler: - /* Save stack frame */ - swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 - swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 - swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 - swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 - swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 - swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 - swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 - swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 - swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 - swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 - swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 - mfs r3, rmsr - swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR - /* Disable dispatching */ lwi r3, r0, _Per_CPU_Information + 16 addik r3, r3, 1 swi r3, r0, _Per_CPU_Information + 16 - swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 - /* Is SP < INTERRUPT_STACK_LOW? */ lwi r4, r0, _Per_CPU_Information rsubk r3, r4, r1 -- 2.34.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] fixed warning related to spstdc17
On 24.10.23 14:02, zack leung wrote:
hi! sabestian did you mean the size of the structure?
Yes, one option to get rid of the empty structures is to just provide
typedefs, for example:
#if defined(RTEMS_SMP)
typedef struct Scheduler_Context {
...
} Scheduler_Context;
#else
typedef struct Scheduler_Context Scheduler_Context;
#endif
Then you have to make sure that #if !defined(RTEMS_SMP) no objects of
this type are used.
For the ISR locks we can do something similar. However, in this case
this affects also the API, so we probably need an API define for this as
well. Suggestion: RTEMS_HAVE_INTERRUPT_LOCK_OBJECTS.
The user can then do something like this:
struct app {
...
#if defined(RTEMS_HAVE_INTERRUPT_LOCK_OBJECTS)
rtems_interrupt_lock lock;
#endif
...
}
--
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Re: [PATCH] fixed warning related to spstdc17
hi! sabestian did you mean the size of the structure? On Mon, 23 Oct 2023 at 10:20, Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello Zack, > > there is a bit more work to do to fix this warning. The warning fix > should not result in a size increase of the uniprocessor RTEMS > configuration. > > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
