Re: [PATCH 5/5] bsps: Add xilinx_zynqmp_lp64_a53 BSP variant
On 22.03.24 16:48, Kinsey Moore wrote: This patch looks good. I would suggest dropping the a53 from the BSP name since all AArch64 ZynqMP BSPs will run on the A53 cores. We should keep this name. Maybe Xilinx provides a Zynq variant with other cores in the future and for the Cortex-A53 we have to enable some errata workarounds: https://devel.rtems.org/ticket/5003 -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 5/5] bsps: Add xilinx_zynqmp_lp64_a53 BSP variant
On 22.03.24 20:57, Gedare Bloom wrote: In some other architectures we have had "generic" BSP targets. It would be good to have something following the lp64 part. I'm not quite clear on what the purpose of this generic BSP target is here. For this platform, there is no need for having specific BSPs. The customization can be done through BSP options and a device tree. The only thing we need are the right compiler options. -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR
On 22.03.24 16:10, Kinsey Moore wrote: Putting these UART addresses in BSP options suggests that they're user-configurable when they aren't. ZynqMP can use the ZYNQMP_UART0/1 from bsps/include/peripheral_maps/xilinx_zynqmp.h, but Zynq would need its own peripheral map to reference. This UART support is used by four BSP families. Currently a lot of copy and past is involved. Defining the two UART base addresses though a BSP option was the easiest approach I found to do this. I would remove the xilinx_zynqmp.h header file since normally you use the xparameters.h for your application depending on the system configuration. -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
