subject:"\[PATCH\] bsps\/aarch64\: Use MMU pages appropriately"

Re: [PATCH] bsps/aarch64: Use MMU pages appropriately

2022-07-05 Thread Chris Johns

On 6/7/2022 5:38 am, Joel Sherrill wrote:
> I'm ok with this. But Chris should speak up about the Versal.

OK to push.

Tested on Versal hardware and it boots as before. I have not returned to see if
I can get access to at least 4G of memory in the lower 32bits of the address
space. That is in the queue.

Thanks
Chris
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH] bsps/aarch64: Use MMU pages appropriately

2022-07-05 Thread Joel Sherrill

I'm ok with this. But Chris should speak up about the Versal.

On Tue, Jul 5, 2022 at 2:36 PM Kinsey Moore 
wrote:

> There were two bugs with MMU page use that were partially hiding each
> other. The linker script page table section was 4x the size it needed to
> be and the page table allocation routine was allocating pages PTRSIZE
> times larger than it needed to. On ILP32, this resulted in incorrect but
> functional allocation. On LP64, this resulted in allocation failures
> earlier than expected.
> ---
>  bsps/aarch64/include/bsp/aarch64-mmu.h   | 4 ++--
>  spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml | 6 +++---
>  spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml  | 6 +++---
>  spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml | 6 +++---
>  spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml  | 6 +++---
>  5 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
> b/bsps/aarch64/include/bsp/aarch64-mmu.h
> index 6e589cd6cd..bca7e0ce8d 100644
> --- a/bsps/aarch64/include/bsp/aarch64-mmu.h
> +++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
> @@ -145,8 +145,8 @@ BSP_START_TEXT_SECTION static inline rtems_status_code
>  aarch64_mmu_page_table_alloc( uint64_t **page_table )
>  {
>/* First page table is already in use as TTB0 */
> -  static uintptr_t *current_page_table =
> -(uintptr_t *) bsp_translation_table_base;
> +  static uintptr_t current_page_table =
> +(uintptr_t) bsp_translation_table_base;
>
>current_page_table += MMU_PAGE_SIZE;
>*page_table = (uint64_t *) current_page_table;
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> index 3030fd0ae9..2d7a922495 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> @@ -29,9 +29,9 @@ content: |
> */
>
>MEMORY {
> -RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> -NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> -RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
> +RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> +NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> +RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
>}
>
>REGION_ALIAS ("REGION_START",  RAM);
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> index bd5d1f791b..76c0220f0e 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> @@ -29,9 +29,9 @@ content: |
> */
>
>MEMORY {
> -RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> -NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> -RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
> +RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> +NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
>

[PATCH] bsps/aarch64: Use MMU pages appropriately

2022-07-05 Thread Kinsey Moore

There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
---
 bsps/aarch64/include/bsp/aarch64-mmu.h   | 4 ++--
 spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml | 6 +++---
 spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml  | 6 +++---
 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml | 6 +++---
 spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml  | 6 +++---
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h 
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index 6e589cd6cd..bca7e0ce8d 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -145,8 +145,8 @@ BSP_START_TEXT_SECTION static inline rtems_status_code
 aarch64_mmu_page_table_alloc( uint64_t **page_table )
 {
   /* First page table is already in use as TTB0 */
-  static uintptr_t *current_page_table =
-(uintptr_t *) bsp_translation_table_base;
+  static uintptr_t current_page_table =
+(uintptr_t) bsp_translation_table_base;
 
   current_page_table += MMU_PAGE_SIZE;
   *page_table = (uint64_t *) current_page_table;
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
index 3030fd0ae9..2d7a922495 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
@@ -29,9 +29,9 @@ content: |
*/
 
   MEMORY {
-RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - 
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - 
(0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, 
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - 
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - 
(0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, 
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",  RAM);
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml 
b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
index bd5d1f791b..76c0220f0e 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
@@ -29,9 +29,9 @@ content: |
*/
 
   MEMORY {
-RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - 
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - 
(0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, 
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+RAM   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - 
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - 
(0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, 
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + 
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * 
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",

Re: [PATCH] bsps/aarch64: Use MMU pages appropriately

Re: [PATCH] bsps/aarch64: Use MMU pages appropriately

[PATCH] bsps/aarch64: Use MMU pages appropriately

3 matches

Site Navigation

Mail list logo

Footer information