[PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
- properly use the cpu <-> apic maps for IPIs --- bsps/i386/pc386/start/smp-imps.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c index 0985b8f08f..763ac0afc7 100644 --- a/bsps/i386/pc386/start/smp-imps.c +++ b/bsps/i386/pc386/start/smp-imps.c @@ -226,9 +226,11 @@ get_checksum(unsigned start, int length) int send_ipi(unsigned int dst, unsigned int v) { - int to, send_status; + int to, send_status, apicid; - IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24)); + apicid = imps_cpu_apic_map[dst]; + + IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (apicid << 24)); IMPS_LAPIC_WRITE(LAPIC_ICR, v); /* Wait for send to finish */ @@ -251,9 +253,11 @@ static int boot_cpu(imps_processor *proc) { int apicid = proc->apic_id, success = 1; + int cpuid; unsigned bootaddr; unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR); + cpuid = imps_apic_cpu_map[apicid]; /* * Copy boot code for secondary CPUs here. Find it in between * "patch_code_start" and "patch_code_end" symbols. The other CPUs @@ -276,7 +280,7 @@ boot_cpu(imps_processor *proc) /* Pass start function, stack region and gdtdescr to AP * see startAP.S for location */ reset[1] = (uint32_t)secondary_cpu_initialize; - reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high; + reset[2] = (uint32_t)_Per_CPU_Get_by_index(cpuid)->interrupt_stack_high; memcpy( (char*) &reset[3], &gdtdesc, @@ -295,13 +299,13 @@ boot_cpu(imps_processor *proc) /* assert INIT IPI */ send_ipi( -apicid, +cpuid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT ); UDELAY(1); /* de-assert INIT IPI */ - send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); + send_ipi(cpuid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); UDELAY(1); @@ -312,7 +316,7 @@ boot_cpu(imps_processor *proc) if (proc->apic_ver >= APIC_VER_NEW) { int i; for (i = 1; i <= 2; i++) { - send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); + send_ipi(cpuid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); UDELAY(1000); } } -- 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
Hello, Could someone please push this patch to the branches 5 and master? Or do I need a ticket for the 5 branch first? Cheers, Jan > -Original Message- > From: Sommer, Jan > Sent: Friday, July 3, 2020 2:32 PM > To: devel@rtems.org > Cc: Sommer, Jan > Subject: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs > > - properly use the cpu <-> apic maps for IPIs > --- > bsps/i386/pc386/start/smp-imps.c | 16 ++-- > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp- > imps.c > index 0985b8f08f..763ac0afc7 100644 > --- a/bsps/i386/pc386/start/smp-imps.c > +++ b/bsps/i386/pc386/start/smp-imps.c > @@ -226,9 +226,11 @@ get_checksum(unsigned start, int length) > int > send_ipi(unsigned int dst, unsigned int v) > { > - int to, send_status; > + int to, send_status, apicid; > > - IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24)); > + apicid = imps_cpu_apic_map[dst]; > + > + IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (apicid << 24)); >IMPS_LAPIC_WRITE(LAPIC_ICR, v); > >/* Wait for send to finish */ > @@ -251,9 +253,11 @@ static int > boot_cpu(imps_processor *proc) > { >int apicid = proc->apic_id, success = 1; > + int cpuid; >unsigned bootaddr; >unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR); > > + cpuid = imps_apic_cpu_map[apicid]; >/* > * Copy boot code for secondary CPUs here. Find it in between > * "patch_code_start" and "patch_code_end" symbols. The other CPUs > @@ -276,7 +280,7 @@ boot_cpu(imps_processor *proc) >/* Pass start function, stack region and gdtdescr to AP > * see startAP.S for location */ >reset[1] = (uint32_t)secondary_cpu_initialize; > - reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)- > >interrupt_stack_high; > + reset[2] = (uint32_t)_Per_CPU_Get_by_index(cpuid)- > >interrupt_stack_high; >memcpy( > (char*) &reset[3], > &gdtdesc, > @@ -295,13 +299,13 @@ boot_cpu(imps_processor *proc) > >/* assert INIT IPI */ >send_ipi( > -apicid, > +cpuid, > LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT >); >UDELAY(1); > >/* de-assert INIT IPI */ > - send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); > + send_ipi(cpuid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); > >UDELAY(1); > > @@ -312,7 +316,7 @@ boot_cpu(imps_processor *proc) >if (proc->apic_ver >= APIC_VER_NEW) { > int i; > for (i = 1; i <= 2; i++) { > - send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); > + send_ipi(cpuid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); >UDELAY(1000); > } >} > -- > 2.17.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
On 08/07/2020 08:55, jan.som...@dlr.de wrote: Could someone please push this patch to the branches 5 and master? Or do I need a ticket for the 5 branch first? If it is a bug fix, then the official procedure would be to add tickets for RTEMS 5 and 6. Since we had no working SMP support before I am not sure if it is worth the trouble. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
On 15/7/20 7:54 pm, Sebastian Huber wrote: > On 08/07/2020 08:55, jan.som...@dlr.de wrote: >> Could someone please push this patch to the branches 5 and master? >> Or do I need a ticket for the 5 branch first? > > If it is a bug fix, then the official procedure would be to add tickets for > RTEMS 5 and 6. Yes a ticket please. > Since we had no working SMP support before I am not sure if it is > worth the trouble. I think it is worth the trouble, the PC is important. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs
> -Original Message- > From: Chris Johns [mailto:chr...@rtems.org] > Sent: Thursday, July 16, 2020 3:21 AM > To: Sebastian Huber; Sommer, Jan; devel@rtems.org > Subject: Re: [PATCH v1 1/1] bsps/pc386: Fix IPI for non-consecutive APICIDs > > On 15/7/20 7:54 pm, Sebastian Huber wrote: > > On 08/07/2020 08:55, jan.som...@dlr.de wrote: > >> Could someone please push this patch to the branches 5 and master? > >> Or do I need a ticket for the 5 branch first? > > > > If it is a bug fix, then the official procedure would be to add tickets for > > RTEMS 5 and 6. > > Yes a ticket please. > Alright, I created a ticket for RTEMS 5: https://devel.rtems.org/ticket/4028 And RTEMS 6: https://devel.rtems.org/ticket/4029 I tried to attach the patch file to the tickets as well, but I get a "IndexError: pop from empty list" error when I try to upload a file. Best regards, Jan > > Since we had no working SMP support before I am not sure if it is > > worth the trouble. > > I think it is worth the trouble, the PC is important. > > Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel