Re: [PATCH v2 06/11] ARM: tegra: Move out nyan-generic parts out from the nyan-big DT
On 15 January 2015 at 18:28, Stephen Warren swar...@wwwdotorg.org wrote: On 01/15/2015 09:12 AM, Tomeu Vizoso wrote: In preparation for adding the DT for the nyan-blaze board. git format-patch -C might help here; hopefully it'd highlight that arch/arm/boot/dts/tegra124-nyan.dtsi was a copy from arch/arm/boot/dts/tegra124-nyan-big.dts, with just a few small diffs? It doesn't, because we keep the pinmux config in the leaf files. Regards, Tomeu -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 1/2] Documentation: DT: Add bindings for Spreadtrum SoC Platform
Adds Spreadtrum's prefix sprd to vendor-prefixes file. Adds the devicetree binding documentations for Spreadtrum's sc9836-uart and SC9836 SoC based on the Sharkl64 Platform which is a 64-bit SoC Platform of Spreadtrum. Signed-off-by: Chunyan Zhang chunyan.zh...@spreadtrum.com --- Documentation/devicetree/bindings/arm/sprd.txt | 11 +++ .../devicetree/bindings/serial/sprd-uart.txt |7 +++ .../devicetree/bindings/vendor-prefixes.txt|1 + 3 files changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sprd.txt create mode 100644 Documentation/devicetree/bindings/serial/sprd-uart.txt diff --git a/Documentation/devicetree/bindings/arm/sprd.txt b/Documentation/devicetree/bindings/arm/sprd.txt new file mode 100644 index 000..31a629d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sprd.txt @@ -0,0 +1,11 @@ +Spreadtrum SoC Platforms Device Tree Bindings + + +Sharkl64 is a Spreadtrum's SoC Platform which is based +on ARM 64-bit processor. + +SC9836 openphone board with SC9836 SoC based on the +Sharkl64 Platform shall have the following properties. + +Required root node properties: +- compatible = sprd,sc9836-openphone, sprd,sc9836; diff --git a/Documentation/devicetree/bindings/serial/sprd-uart.txt b/Documentation/devicetree/bindings/serial/sprd-uart.txt new file mode 100644 index 000..2aff0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sprd-uart.txt @@ -0,0 +1,7 @@ +* Spreadtrum serial UART + +Required properties: +- compatible: must be sprd,sc9836-uart +- reg: offset and length of the register set for the device +- interrupts: exactly one interrupt specifier +- clocks: phandles to input clocks. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b1df0ad..0a8384f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -153,6 +153,7 @@ snpsSynopsys, Inc. solidrun SolidRun sony Sony Corporation spansion Spansion Inc. +sprd Spreadtrum Communications Inc. st STMicroelectronics steST-Ericsson stericsson ST-Ericsson -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] DT: leds: Add led-sources property
Add a property for defining device outputs the LED
represented by the DT child node is connected to.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Bryan Wu coolo...@gmail.com
Cc: Richard Purdie rpur...@rpsys.net
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/leds/common.txt | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/leds/common.txt
b/Documentation/devicetree/bindings/leds/common.txt
index a2c3f7a..34811c5 100644
--- a/Documentation/devicetree/bindings/leds/common.txt
+++ b/Documentation/devicetree/bindings/leds/common.txt
@@ -1,6 +1,19 @@
Common leds properties.
+LED and flash LED devices provide the same basic functionality as current
+regulators, but extended with LED and flash LED specific features like
+blinking patterns, flash timeout, flash faults and external flash strobe mode.
+
+Many LED devices expose more than one current output that can be connected
+to one or more discrete LED component. Since the arrangement of connections
+can influence the way of the LED device initialization, the LED components
+have to be tightly coupled with the LED device binding. They are represented
+by child nodes of the parent LED device binding.
+
Optional properties for child nodes:
+- led-sources : List of device current outputs the LED is connected to. The
+ outputs are identified by the numbers that must be defined
+ in the LED device binding documentation.
- label : The label for this LED. If omitted, the label is
taken from the node name (excluding the unit address).
@@ -33,7 +46,8 @@ system-status {
camera-flash {
label = Flash;
+ led-sources = 0, 1;
max-microamp = 5;
flash-max-microamp = 32;
flash-timeout-us = 50;
-}
+};
--
1.7.9.5
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[PATCH v7 0/2] Add Spreadtrum Sharkl64 Platform support
This patch-set split the last version, and addressed the review comments from last version on serial driver code. Changes from v6: - Setted stdout-path with serial1:115200n8 Changes from v5: - Added maintenance interrupt for gic - Removed reg property from 'soc' and 'apb' nodes Zhizhou Zhang (2): arm64: dts: Add support for Spreadtrum SC9836 SoC in dts and Makefile arm64: Add support for Spreadtrum's Sharkl64 Platform in Kconfig and defconfig arch/arm64/Kconfig|5 ++ arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/sprd/Makefile |5 ++ arch/arm64/boot/dts/sprd/sc9836-openphone.dts | 49 arch/arm64/boot/dts/sprd/sc9836.dtsi | 74 + arch/arm64/boot/dts/sprd/sharkl64.dtsi| 65 ++ arch/arm64/configs/defconfig |1 + 7 files changed, 200 insertions(+) create mode 100644 arch/arm64/boot/dts/sprd/Makefile create mode 100644 arch/arm64/boot/dts/sprd/sc9836-openphone.dts create mode 100644 arch/arm64/boot/dts/sprd/sc9836.dtsi create mode 100644 arch/arm64/boot/dts/sprd/sharkl64.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv6 0/2] Driver for TI tlc591xx 8/16 Channel i2c LED driver
This patchset is a driver for the TI tlc59116 16 Channel i2c LED driver and tlc59108 8 Channel i2c LED driver. This driver is used on the Belkin WRT1900AC access point and the C code is derived from code Belkin contributed to OpenWRT. However it has been extensively re-written, and a device tree binding added to replace platform data. Cc: matthew.fathe...@belkin.com Since v5: Hard code number of LEDs, rather than #define Moved common fields from led into priv Moved reg_ledout into priv, removed helper functions Cache brightness to avoid race conditions tlc591xx_led_set - tlc591xx_set_brightness Be paranoid with of_match_device() and client-dev.of_node Since v4: Fix Oops on module unload reported by Vignesh R Since v3: Generalized and added support for tlc59108 brightness == 0 and brightness == LED_FULL disable PWM and used fixed OFF/ON mode Since v2: Remove incorrect /* Mode register ? */ comment Parenthesis around the macro arguments Converted many signed variables into unsigned Saved an initialization Since v1: s/uint8_t/u8/g Remove empty line Removed #gpio-cells Added select REGMAP_I2C Sorted #includes into alphabetic order Added missing MODULE_DEVICE_TABLE(of, ...) Check return value of regmap_write() Simplified tlc59116_set_mode() Andrew Lunn (2): leds: tlc59116: Document binding for the TI 16 Channel i2c LED driver leds: tlc59116: Driver for the TI 16 Channel i2c LED driver .../devicetree/bindings/leds/leds-tlc59116.txt | 41 drivers/leds/Kconfig | 7 + drivers/leds/Makefile | 1 + drivers/leds/leds-tlc59116.c | 253 + 4 files changed, 302 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc59116.txt create mode 100644 drivers/leds/leds-tlc59116.c -- 2.1.3 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv6 2/2] leds: tlc591xx: Driver for the TI 8/16 Channel i2c LED driver
The TLC59116 is an I2C bus controlled 16-channel LED driver. The
TLC59108 is an I2C bus controlled 8-channel LED driver, which is very
similar to the TLC59116. Each LED output has its own 8-bit
fixed-frequency PWM controller to control the brightness of the LED.
The LEDs can also be fixed off and on, making them suitable for use as
GPOs.
This is based on a driver from Belkin, but has been extensively
rewritten and extended to support both 08 and 16 versions.
Signed-off-by: Andrew Lunn and...@lunn.ch
Cc: matthew.fathe...@belkin.com
---
drivers/leds/Kconfig | 8 ++
drivers/leds/Makefile| 1 +
drivers/leds/leds-tlc591xx.c | 300 +++
3 files changed, 309 insertions(+)
create mode 100644 drivers/leds/leds-tlc591xx.c
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index a6c3d2f153f3..67cba2032543 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -457,6 +457,14 @@ config LEDS_TCA6507
LED driver chips accessed via the I2C bus.
Driver support brightness control and hardware-assisted blinking.
+config LEDS_TLC591XX
+ tristate LED driver for TLC59108 and TLC59116 controllers
+ depends on LEDS_CLASS I2C
+ select REGMAP_I2C
+ help
+ This option enables support for Texas Instruments TLC59108
+ and TLC59116 LED controllers.
+
config LEDS_MAX8997
tristate LED support for MAX8997 PMIC
depends on LEDS_CLASS MFD_MAX8997
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 1c65a191d907..0558117a9407 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_LEDS_LP8501) += leds-lp8501.o
obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o
obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o
obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o
+obj-$(CONFIG_LEDS_TLC591XX)+= leds-tlc591xx.o
obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o
obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
diff --git a/drivers/leds/leds-tlc591xx.c b/drivers/leds/leds-tlc591xx.c
new file mode 100644
index ..de16c29d7895
--- /dev/null
+++ b/drivers/leds/leds-tlc591xx.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2014 Belkin Inc.
+ * Copyright 2015 Andrew Lunn and...@lunn.ch
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include linux/i2c.h
+#include linux/leds.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/regmap.h
+#include linux/slab.h
+#include linux/workqueue.h
+
+#define TLC591XX_MAX_LEDS 16
+
+#define TLC591XX_REG_MODE1 0x00
+#define MODE1_RESPON_ADDR_MASK 0xF0
+#define MODE1_NORMAL_MODE (0 4)
+#define MODE1_SPEED_MODE (1 4)
+
+#define TLC591XX_REG_MODE2 0x01
+#define MODE2_DIM (0 5)
+#define MODE2_BLINK(1 5)
+#define MODE2_OCH_STOP (0 3)
+#define MODE2_OCH_ACK (1 3)
+
+#define TLC591XX_REG_PWM(x)(0x02 + (x))
+
+#define TLC591XX_REG_GRPPWM0x12
+#define TLC591XX_REG_GRPFREQ 0x13
+
+/* LED Driver Output State, determine the source that drives LED outputs */
+#define LEDOUT_OFF 0x0 /* Output LOW */
+#define LEDOUT_ON 0x1 /* Output HI-Z */
+#define LEDOUT_DIM 0x2 /* Dimming */
+#define LEDOUT_BLINK 0x3 /* Blinking */
+#define LEDOUT_MASK0x3
+
+#define ldev_to_led(c) container_of(c, struct tlc591xx_led, ldev)
+#define work_to_led(work) container_of(work, struct tlc591xx_led, work)
+
+struct tlc591xx_led {
+ bool active;
+ unsigned int led_no;
+ struct led_classdev ldev;
+ struct work_struct work;
+ struct tlc591xx_priv *priv;
+};
+
+struct tlc591xx_priv {
+ struct tlc591xx_led leds[TLC591XX_MAX_LEDS];
+ struct regmap *regmap;
+ unsigned int reg_ledout_offset;
+};
+
+struct tlc591xx {
+ unsigned int max_leds;
+ unsigned int reg_ledout_offset;
+};
+
+static const struct tlc591xx tlc59116 = {
+ .max_leds = 16,
+ .reg_ledout_offset = 0x14,
+};
+
+static const struct tlc591xx tlc59108 = {
+ .max_leds = 8,
+ .reg_ledout_offset = 0x0c,
+};
+
+static int
+tlc591xx_set_mode(struct regmap *regmap, u8 mode)
+{
+ int err;
+ u8 val;
+
+ err = regmap_write(regmap, TLC591XX_REG_MODE1, MODE1_NORMAL_MODE);
+ if (err)
+ return err;
+
+ val = MODE2_OCH_STOP | mode;
+
+ return regmap_write(regmap, TLC591XX_REG_MODE2, val);
+}
+
+static int
+tlc591xx_set_ledout(struct tlc591xx_priv *priv, struct tlc591xx_led *led,
+ u8 val)
+{
+ unsigned int i = (led-led_no % 4) * 2;
+ unsigned int mask =
[PATCH_V2 3/3] usb: ohci: jz4740: prepare the clock before enabling it
From: Paul Burton paul.bur...@imgtec.com The clock must have been prepared before enabling it. Signed-off-by: Paul Burton paul.bur...@imgtec.com -- V2 changes. Add disable_unprepare as well --- drivers/usb/host/ohci-jz4740.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c index bb69733..129f6b9 100644 --- a/drivers/usb/host/ohci-jz4740.c +++ b/drivers/usb/host/ohci-jz4740.c @@ -189,7 +189,7 @@ static int jz4740_ohci_probe(struct platform_device *pdev) clk_set_rate(jz4740_ohci-clk, 4800); - clk_enable(jz4740_ohci-clk); + clk_prepare_enable(jz4740_ohci-clk); if (jz4740_ohci-vbus) ohci_jz4740_set_vbus_power(jz4740_ohci, true); @@ -209,7 +209,7 @@ static int jz4740_ohci_probe(struct platform_device *pdev) err_disable: if (jz4740_ohci-vbus) regulator_disable(jz4740_ohci-vbus); - clk_disable(jz4740_ohci-clk); + clk_disable_unprepare(jz4740_ohci-clk); err_free: usb_put_hcd(hcd); @@ -227,7 +227,7 @@ static int jz4740_ohci_remove(struct platform_device *pdev) if (jz4740_ohci-vbus) regulator_disable(jz4740_ohci-vbus); - clk_disable(jz4740_ohci-clk); + clk_disable_unprepare(jz4740_ohci-clk); usb_put_hcd(hcd); -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
On Mon, Jan 26, 2015 at 4:57 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
As discussed with Sascha Hauer it is ambigous to use pins for
a numerical value indicating both a mux setting and a pin. Sascha
suggests using pinmux and adding this as a secondary generic
binding for this type of pin controllers that use numbers and #defines
to set up bindings.
We should still move these parsing functions to the core.
I tried that for the last few days and failed.
Part of the problem is that the core lacks the data structures to put
the information in. There is
struct pinctrl_map_mux {
const char *group;
const char *function;
};
but its meaning is SoC specific. Some SoCs combine the pins found in a
dt subnode to one group (i.MX, rockchip, at91) while others make an
individual group from each single pin (Tegra, others?). Also the
function string is SoC specific. Some SoCs just define functions like
alt1..altn which are valid for all groups, others define different
function names for each group.
Another thing is that the binding gives us numbers, but struct
pinctrl_map_mux expects strings, so the numbers would have to be
converted to strings. This is crude since the contents of struct
pinctrl_map_mux are converted from strings back to numbers later from
the pinctrl core with the help of the driver. So we would have to
translate the numbers from the bindings to strings just to convert them
back to numbers before passing them to the driver later.
So can we use a union?
struct pinctrl_map_mux {
union group {
const char *groupstr;
u16 groupno;
};
union function {
const char *functionstr;
u16 funcno;
};
};
The augment the code to reference foo-group.groupstr or
foo-group.groupno etc depending on runpath.
Yours,
Linus Walleij
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[PATCH 0/3] usb: ohci: jz4740: Add DT support and a fix
Hi, Here are a few simple patches for the jz4740. First adds a simple DT binding. Seconds adds DT support. Third is a minor fix in clock enabling. Patches are based on 3.19-rc6. Quite disjoint and stay within jz4740 so should apply easily on other trees. If you would like to have them rebased to a different tree, please tell. Thank-you ZubairLK Paul Burton (3): dt: usb: jz4740: Add DT binding document for OHCI usb: ohci: jz4740: add DT support usb: ohci: jz4740: prepare the clock before enabling it .../bindings/usb/ingenic,jz47xx-ohci.txt | 28 ++ drivers/usb/host/ohci-jz4740.c | 11 - 2 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] dt: usb: jz4740: Add DT binding document for OHCI
From: Paul Burton paul.bur...@imgtec.com
Add the binding documentation for the JZ47xx OHCI controller.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Signed-off-by: Zubair Lutfullah Kakakhel zubair.kakak...@imgtec.com
---
The jz4740 is platform only at the moment.
But DT support is being added
See http://patchwork.linux-mips.org/bundle/paulburton/ci20-v3.20/
jz47xx is used because jz4780 will also use this driver
---
.../bindings/usb/ingenic,jz47xx-ohci.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
b/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
new file mode 100644
index 000..2fada8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
@@ -0,0 +1,28 @@
+Ingenic JZ47XX SoC OHCI controller binding
+
+The Ingenic JZ47XX SoC includes an OHCI compliant USB host controller
+interface for use with USB 1.1 devices.
+
+Required properties:
+ - compatible: Should be ingenic,jz4740-ohci
+ - reg: Should contain the address size of the OHCI controller registers.
+ - interrupt-parent: Should be the phandle of the interrupt controller that
+ delivers interrupts to the OHCI block.
+ - interrupts: Should specify the interrupt provided by interrupt-parent.
+ - clocks: Should contain a single clock specifier for the SoC UHC clock.
+
+Example SoC include file for jz4780:
+
+/ {
+ ohci: jz4780-ohci@0x134a {
+ compatible = ingenic,jz4780-ohci;
+ reg = 0x134a 0x1;
+
+ interrupt-parent = intc;
+ interrupts = 5;
+
+ clocks = cgu JZ4780_CLK_UHC;
+ clock-names = uhc;
+ };
+};
+
--
1.9.1
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[PATCH 2/3] usb: ohci: jz4740: add DT support
From: Paul Burton paul.bur...@imgtec.com
This is a simple matter of providing a match table, the probe code needs
no modification.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
---
drivers/usb/host/ohci-jz4740.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c
index 8ddd8f5..bb69733 100644
--- a/drivers/usb/host/ohci-jz4740.c
+++ b/drivers/usb/host/ohci-jz4740.c
@@ -234,11 +234,20 @@ static int jz4740_ohci_remove(struct platform_device
*pdev)
return 0;
}
+#ifdef CONFIG_OF
+static struct of_device_id jz4740_ohci_of_match[] = {
+ { .compatible = ingenic,jz4740-ohci, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, jz4740_ohci_of_match);
+#endif
+
static struct platform_driver ohci_hcd_jz4740_driver = {
.probe = jz4740_ohci_probe,
.remove = jz4740_ohci_remove,
.driver = {
.name = jz4740-ohci,
+ .of_match_table = of_match_ptr(jz4740_ohci_of_match),
.owner = THIS_MODULE,
},
};
--
1.9.1
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[PATCH 3/3] usb: ohci: jz4740: prepare the clock before enabling it
From: Paul Burton paul.bur...@imgtec.com The clock must have been prepared before enabling it. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- drivers/usb/host/ohci-jz4740.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c index bb69733..1455a8b 100644 --- a/drivers/usb/host/ohci-jz4740.c +++ b/drivers/usb/host/ohci-jz4740.c @@ -189,7 +189,7 @@ static int jz4740_ohci_probe(struct platform_device *pdev) clk_set_rate(jz4740_ohci-clk, 4800); - clk_enable(jz4740_ohci-clk); + clk_prepare_enable(jz4740_ohci-clk); if (jz4740_ohci-vbus) ohci_jz4740_set_vbus_power(jz4740_ohci, true); -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] pinctrl: Qualcomm msm8916 pinctrl driver
On Tue, Jan 20, 2015 at 10:17 AM, Stanimir Varbanov svarba...@mm-sol.com wrote: This series adds a pinctrl driver for Snapdragon 410 (msm8916) SoC. The first patch increase the register address variable size, next adds a binding document and the last patch adds the pinctrl driver Comments are welcome! Stephen, Björn seems to be unavailable to review this patch set right now, can you have a look at it so it doesn't stall? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv6 1/2] leds: tlc591xx: Document binding for the TI 8/16 Channel i2c LED driver
Document the binding for the TLC591xx LED driver.
Signed-off-by: Andrew Lunn and...@lunn.ch
Cc: matthew.fathe...@belkin.com
---
.../devicetree/bindings/leds/leds-tlc591xx.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc591xx.txt
diff --git a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt
b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt
new file mode 100644
index ..3bbbf7024411
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt
@@ -0,0 +1,40 @@
+LEDs connected to tlc59116 or tlc59108
+
+Required properties
+- compatible: should be ti,tlc59116 or ti,tlc59108
+- #address-cells: must be 1
+- #size-cells: must be 0
+- reg: typically 0x68
+
+Each led is represented as a sub-node of the ti,tlc59116.
+See Documentation/devicetree/bindings/leds/common.txt
+
+LED sub-node properties:
+- reg: number of LED line, 0 to 15 or 0 to 7
+- label: (optional) name of LED
+- linux,default-trigger : (optional)
+
+Examples:
+
+tlc59116@68 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = ti,tlc59116;
+ reg = 0x68;
+
+ wan@0 {
+ label = wrt1900ac:amber:wan;
+ reg = 0x0;
+ };
+
+ 2g@2 {
+ label = wrt1900ac:white:2g;
+ reg = 0x2;
+ };
+
+ alive@9 {
+ label = wrt1900ac:green:alive;
+ reg = 0x9;
+ linux,default_trigger = heartbeat;
+ };
+};
--
2.1.4
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[PATCH_V2 0/3] usb: ohci: jz4740: Add DT support and a fix
Hi, Here are a few simple patches for the jz4740. First adds a simple DT binding. Seconds adds DT support. Third is a minor fix in clock enabling. Patches are based on 3.19-rc6. Quite disjoint and stay within jz4740 so should apply easily on other trees. If you would like to have them rebased to a different tree, please tell. Thank-you V2 changes Removed an interrupt parent binding. Forgot a binding Unprepared clock when disabling ZubairLK Paul Burton (3): dt: usb: jz4740: Add DT binding document for OHCI usb: ohci: jz4740: add DT support usb: ohci: jz4740: prepare the clock before enabling it .../bindings/usb/ingenic,jz47xx-ohci.txt | 26 ++ drivers/usb/host/ohci-jz4740.c | 15 ++--- 2 files changed, 38 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH_V2 1/3] dt: usb: jz4740: Add DT binding document for OHCI
From: Paul Burton paul.bur...@imgtec.com
Add the binding documentation for the JZ47xx OHCI controller.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Signed-off-by: Zubair Lutfullah Kakakhel zubair.kakak...@imgtec.com
---
The jz4740 is platform only at the moment.
But DT support is being added
See http://patchwork.linux-mips.org/bundle/paulburton/ci20-v3.20/
jz47xx is used because jz4780 will also use this driver
V2 Changes: Removed interrupt parent binding as that can be inherited.
Forgot a binding for clock-names
---
.../bindings/usb/ingenic,jz47xx-ohci.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
b/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
new file mode 100644
index 000..2e5dce5
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ingenic,jz47xx-ohci.txt
@@ -0,0 +1,26 @@
+Ingenic JZ47XX SoC OHCI controller binding
+
+The Ingenic JZ47XX SoC includes an OHCI compliant USB host controller
+interface for use with USB 1.1 devices.
+
+Required properties:
+ - compatible: Should be ingenic,jz4740-ohci
+ - reg: Should contain the address size of the OHCI controller registers.
+ - interrupts: Should specify the interrupt line number
+ - clocks: Should contain a single clock specifier for the SoC UHC clock.
+ - clock-names: Must be uhc
+
+Example for jz4780:
+
+/ {
+ ohci: jz4780-ohci@0x134a {
+ compatible = ingenic,jz4780-ohci;
+ reg = 0x134a 0x1;
+
+ interrupts = 5;
+
+ clocks = cgu JZ4780_CLK_UHC;
+ clock-names = uhc;
+ };
+};
+
--
1.9.1
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[PATCH_V2 2/3] usb: ohci: jz4740: add DT support
From: Paul Burton paul.bur...@imgtec.com
This is a simple matter of providing a match table, the probe code needs
no modification.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
---
drivers/usb/host/ohci-jz4740.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c
index 8ddd8f5..bb69733 100644
--- a/drivers/usb/host/ohci-jz4740.c
+++ b/drivers/usb/host/ohci-jz4740.c
@@ -234,11 +234,20 @@ static int jz4740_ohci_remove(struct platform_device
*pdev)
return 0;
}
+#ifdef CONFIG_OF
+static struct of_device_id jz4740_ohci_of_match[] = {
+ { .compatible = ingenic,jz4740-ohci, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, jz4740_ohci_of_match);
+#endif
+
static struct platform_driver ohci_hcd_jz4740_driver = {
.probe = jz4740_ohci_probe,
.remove = jz4740_ohci_remove,
.driver = {
.name = jz4740-ohci,
+ .of_match_table = of_match_ptr(jz4740_ohci_of_match),
.owner = THIS_MODULE,
},
};
--
1.9.1
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Re: [PATCHv2] mvebu: add Linksys WRT1900AC (Mamba) support
Hi Andrew, On Mon, 26 Jan 2015 19:44:36 +0100, Andrew Lunn and...@lunn.ch wrote: + model = Linksys WRT1900AC (Mamba); + compatible = linksys,mamba, marvell,armadaxp-mv78230, +marvell,armadaxp, marvell,armada-370-xp; Hi Imre So the consensus seems to be model = Linksys WRT1900AC; compatible = linksys,mamba, ...; with leds using mamba. Okie. Please name the file armada-xp-linksys-mamba.dts. Will do, thanks everyone for the help. Imre -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] net: allwinner: sun4i-emac: fix emac SRAM mapping
Hi,
On Mon, Jan 26, 2015 at 03:34:49PM +0100, Jens Kuske wrote:
Hi,
On 25/01/15 17:25, Maxime Ripard wrote:
Hi Jens,
On Sun, Jan 25, 2015 at 04:49:19PM +0100, Jens Kuske wrote:
The EMAC needs SRAM block A3_A4 being mapped to EMAC peripheral to
work. This is done by the bootloader most of the time, but U-Boot
Falcon Mode, for example, skips emac initialization and SRAM would
stay mapped to the CPU.
Thanks for reviving this.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
drivers/net/ethernet/allwinner/Kconfig | 1 +
drivers/net/ethernet/allwinner/sun4i-emac.c | 18 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/net/ethernet/allwinner/Kconfig
b/drivers/net/ethernet/allwinner/Kconfig
index d8d95d4..508a288 100644
--- a/drivers/net/ethernet/allwinner/Kconfig
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -28,6 +28,7 @@ config SUN4I_EMAC
select MII
select PHYLIB
select MDIO_SUN4I
+ select MFD_SYSCON
---help---
Support for Allwinner A10 EMAC ethernet driver.
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c
b/drivers/net/ethernet/allwinner/sun4i-emac.c
index 1fcd556..86c891d 100644
--- a/drivers/net/ethernet/allwinner/sun4i-emac.c
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
@@ -18,6 +18,8 @@
#include linux/gpio.h
#include linux/interrupt.h
#include linux/irq.h
+#include linux/mfd/syscon.h
+#include linux/mfd/syscon/sun4i-sc.h
#include linux/mii.h
#include linux/module.h
#include linux/netdevice.h
@@ -28,6 +30,7 @@
#include linux/of_platform.h
#include linux/platform_device.h
#include linux/phy.h
+#include linux/regmap.h
#include sun4i-emac.h
@@ -78,6 +81,7 @@ struct emac_board_info {
struct phy_device *phy_dev;
struct device_node *phy_node;
+ struct regmap *sc;
unsigned intlink;
unsigned intspeed;
unsigned intduplex;
@@ -862,6 +866,18 @@ static int emac_probe(struct platform_device *pdev)
goto out;
}
+ /* Map SRAM_A3_A4 to EMAC */
+ db-sc = syscon_regmap_lookup_by_compatible(
+ allwinner,sun4i-a10-syscon);
+ if (IS_ERR(db-sc)) {
+ dev_err(pdev-dev, failed to find syscon regmap\n);
+ ret = PTR_ERR(db-sc);
+ goto out;
+ }
+
+ regmap_update_bits(db-sc, SUN4I_SC1, SUN4I_SC1_SRAM_A3_A4_MAP_MASK,
+ SUN4I_SC1_SRAM_A3_A4_MAP_EMAC);
+
I don't think that using a syscon is the right solution here.
All this SRAM mapping thing is mutually exclusive, and will possibly
impact other drivers as well.
Each single SRAM area can only be mapped to a single peripheral, so as long
as the driver only changes bits related to his own area nothing can go wrong
I believe.
Which is exactly my point. This kind of assumption is very
fragile. Such mistakes might be made, will slip in under any review
and might get un-noticed for a very long time.
While adding a simple driver at least would make this obvious when two
drivers will contend for the same SRAM mapping.
SRAM_C2 looks like it can be mapped do different devices (AE, CE, ACE), but
as far as I understand this, they are all related to the ACE device, sharing
a common register space, and would have to be handled by a single driver
anyway (if that will ever happen without docs)
https://linux-sunxi.org/ACE_Register_guide
I think this is a more a case for a small driver in drivers/soc that
would take care of this, and make sure that client drivers don't step
on each other's toe.
I'm not convinced this is necessary, but what would this driver do different
than a basic regmap? Check if the area is already mapped by any driver and
deny mapping it again by a different driver? Which different driver, each
area is only interesting for a single device/driver? Except maybe mapping it
to CPU as general purpose sram, but that would need some direct agreement
with the driver to steal its memory anyway.
Off the top of my head:
- Make sure no one step on each other's toe, including the CPU that
might require a SRAM for several things (suspend, cpuidle, PSCI,
etc.)
- Provide a comprehensive status of the various SRAM and what they
are mapped to in debugfs
- Provide an abstraction to the SRAM mapping IP. You make the
assumption that the client drivers will always use on an A10 or an
SoC that has the same SRAMs, and the same IP to control which
device they are mapped to. This might not be true for other
drivers, and other SoCs.
- Make any adjustment to these registers that wouldn't fit in any
client drivers.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH v3] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
On Tue, Jan 27, 2015 at 06:27:45PM +, Adam Sampson wrote: Add support for the LinkSprite pcDuino 3 Nano board. This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Changes in v3: - rename LEDs to pcduino3-nano:green:usr[12] - remove optional features on Arduino headers (i2c2, spi0, uart2) Signed-off-by: Adam Sampson a...@offog.org Applied, thanks. Note that it will probably only show up in 3.21. The pull requests for 3.20 have been sent this week end, and unless something major and unexpected shows up, I won't send others. Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH 3/7] spi: spi-fsl-dspi: Remove usage of devm_kzalloc
On 01/27/2015 03:57 AM, Bhuvanchandra DV wrote: devm_* API was supposed to be used only in probe function call. Memory is allocated at 'probe' and free automatically at 'remove'. Usage of devm_* functions outside probe sometimes leads to memory leak. Avoid using devm_kzalloc in dspi_setup_transfer and use kzalloc instead. Also add the dspi_cleanup function to free the controller data upon cleanup. [1.027945] fsl-dspi 4002d000.dspi1: registered master spi1 [1.028664] spi spi1.0: setup mode 0, 8 bits/w, 5000 Hz max -- 0 [1.028877] [ cut here ] [1.036953] WARNING: CPU: 0 PID: 1 at drivers/base/dd.c:286 driver_probe_device+0x1d8/0x244() [1.052136] Modules linked in: [1.058525] CPU: 0 PID: 1 Comm: swapper Not tainted 3.19.0-rc1-104479-g702bebc #202 [1.072777] Backtrace: [1.078437] [80011a04] (dump_backtrace) from [80011ce0] (show_stack+0x18/0x1c) [1.092393] r6:011e r5:0009 r4: r3: [1.101639] [80011cc8] (show_stack) from [805a2d18] (dump_stack+0x24/0x28) [1.115701] [805a2cf4] (dump_stack) from [80021564] (warn_slowpath_common+0x74/0x8c) [1.130905] [800214f0] (warn_slowpath_common) from [80021620] (warn_slowpath_null+0x24/0x2c) [1.147289] r8: r7:807d5dd0 r6:802e2f54 r5:8ea1a200 r4:808444d4 [1.158272] [800215fc] (warn_slowpath_null) from [802e2ee8] (driver_probe_device+0x1d8/0x244) [1.175532] [802e2d10] (driver_probe_device) from [802e2f9c] (__device_attach+0x48/0x4c) [1.192583] r8: r7:8ea4 r6:802e2f54 r5:8ea1a200 r4:807d5dd0 r3:8035a150 [1.209718] [802e2f54] (__device_attach) from [802e14ac] (bus_for_each_drv+0x60/0x94) [1.227619] r5:8ea1a200 r4: [1.236097] [802e144c] (bus_for_each_drv) from [802e2cd4] (device_attach+0x7c/0x90) [1.253809] r6:807d5cc0 r5:8ea1a234 r4:8ea1a200 [1.263442] [802e2c58] (device_attach) from [802e2338] (bus_probe_device+0x8c/0xb0) [1.281269] r6:807d5cc0 r5:8ea1a200 r4:8ea1a208 r3:8e881cc0 [1.292124] [802e22ac] (bus_probe_device) from [802e06c8] (device_add+0x448/0x528) [1.309972] r6:8ea1a200 r5: r4:8ea1a208 r3:0001 [1.320830] [802e0280] (device_add) from [8035a8c8] (spi_add_device+0x9c/0x15c) [1.338382] r9:8e8ab210 r8: r7:8e8ab210 r6: r5:8ea4 r4:8ea1a200 [1.356236] [8035a82c] (spi_add_device) from [8035c0a8] (spi_register_master+0x4d8/0x73c) [1.374695] r7:8ea1a368 r6:8ea1a200 r5:8fde7f7c r4:8ea4 [1.385537] [8035bbd0] (spi_register_master) from [8035d930] (spi_bitbang_start+0x9c/0x108) [1.404100] r10:8088 r9:8e816f80 r8:8fde7c50 r7:8e8ab210 r6:8e8ab200 r5:8ea4 [1.421967] r4:8ea4 [1.429305] [8035d894] (spi_bitbang_start) from [8035e334] (dspi_probe+0x1d4/0x2bc) [1.446821] r4:8ea40210 r3:80845a10 [1.455241] [8035e160] (dspi_probe) from [802e4854] (platform_drv_probe+0x4c/0xac) [1.472666] r10: r9:8ea1c2c0 r8: r7:807d5e20 r6:807d5e20 r5:fdfb [1.490365] r4:8e8ab210 [1.497638] [802e4808] (platform_drv_probe) from [802e2e20] (driver_probe_device+0x110/0x244) [1.516021] r7:807d5e20 r6: r5:8e8ab210 r4:808444d4 [1.526612] [802e2d10] (driver_probe_device) from [802e3034] (__driver_attach+0x94/0x98) [1.544556] r8:807735e8 r7: r6:8e8ab244 r5:807d5e20 r4:8e8ab210 r3: [1.562013] [802e2fa0] (__driver_attach) from [802e13f4] (bus_for_each_dev+0x68/0x9c) [1.579714] r6:802e2fa0 r5:807d5e20 r4: r3:8e8ad03c [1.590310] [802e138c] (bus_for_each_dev) from [802e2914] (driver_attach+0x24/0x28) [1.607804] r6:807ca840 r5:8ea25700 r4:807d5e20 [1.617252] [802e28f0] (driver_attach) from [802e25bc] (bus_add_driver+0x150/0x1f8) [1.634584] [802e246c] (bus_add_driver) from [802e3670] (driver_register+0x80/0x100) [1.652292] r7:8e842038 r6:8078e0f8 r5:807b3460 r4:807d5e20 [1.662953] [802e35f0] (driver_register) from [802e4798] (__platform_driver_register+0x5c/0x64) [1.681772] r5:807b3460 r4:807b3460 [1.690234] [802e473c] (__platform_driver_register) from [8078e114] (fsl_dspi_driver_init+0x1c/0x20) [1.709306] [8078e0f8] (fsl_dspi_driver_init) from [80008770] (do_one_initcall+0x94/0x1d4) [1.727791] [800086dc] (do_one_initcall) from [80773e38] (kernel_init_freeable+0x130/0x1d0) [1.746412] r10:8079eef0 r9:8079eee4 r8:807735e8 r7:807f1c80 r6:807f1c80 r5:0006 [1.764399] r4:807a7bc8 [1.771813] [80773d08] (kernel_init_freeable) from [8059f864] (kernel_init+0x10/0xf0) [1.789660] r10: r9: r8: r7: r6: r5:8059f854 [1.807381] r4: [1.814668] [8059f854] (kernel_init) from [8000e638] (ret_from_fork+0x14/0x3c) [1.831772] r4: r3:8e842000 [1.840212] ---[ end trace f7f1c89f62e53de9 ]--- Acked-by: Stefan Agner ste...@agner.ch Signed-off-by: Bhuvanchandra DV bhuvanchandra...@toradex.com ---
[PATCH v3 07/10] ARM: dts: sunxi: Add usb3_vbus regulator to common regulators dtsi
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add a common VBUS regulator for the last host controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index e02baa66b33c..97fe8d73c4f7 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -130,6 +130,16 @@
status = disabled;
};
+ reg_usb3_vbus: usb3-vbus {
+ compatible = regulator-fixed;
+ pinctrl-names = default;
+ regulator-name = usb3-vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ enable-active-high;
+ status = disabled;
+ };
+
reg_vcc3v0: vcc3v0 {
compatible = regulator-fixed;
regulator-name = vcc3v0;
--
2.1.4
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[PATCH v3 06/10] ARM: dts: sun9i: Add USB host controller nodes to a80 dtsi
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d7ebd9390b01..9483b15bfda7 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -355,6 +355,28 @@
*/
ranges = 0 0 0 0x2000;
+ ehci0: usb@00a0 {
+ compatible = allwinner,sun9i-a80-ehci, generic-ehci;
+ reg = 0x00a0 0x100;
+ interrupts = GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 1;
+ resets = usb_mod_clk 17;
+ phys = usbphy1;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ ohci0: usb@00a00400 {
+ compatible = allwinner,sun9i-a80-ohci, generic-ohci;
+ reg = 0x00a00400 0x100;
+ interrupts = GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 1, usb_mod_clk 2;
+ resets = usb_mod_clk 17;
+ phys = usbphy1;
+ phy-names = usb;
+ status = disabled;
+ };
+
usbphy1: phy@00a00800 {
compatible = allwinner,sun9i-a80-usb-phy;
reg = 0x00a00800 0x4;
@@ -366,6 +388,32 @@
#phy-cells = 0;
};
+ ehci1: usb@00a01000 {
+ compatible = allwinner,sun9i-a80-ehci, generic-ehci;
+ reg = 0x00a01000 0x100;
+ interrupts = GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 3;
+ resets = usb_mod_clk 18;
+ phys = usbphy2;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ /*
+* Even though ohci1 exists, it is never used as
+* usb1 only has HSIC pins routed externally
+*/
+ ohci1: usb@00a01400 {
+ compatible = allwinner,sun9i-a80-ohci, generic-ohci;
+ reg = 0x00a01400 0x100;
+ interrupts = GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 3, usb_mod_clk 4;
+ resets = usb_mod_clk 18;
+ phys = usbphy2;
+ phy-names = usb;
+ status = disabled;
+ };
+
usbphy2: phy@00a01800 {
compatible = allwinner,sun9i-a80-usb-phy;
reg = 0x00a01800 0x4;
@@ -380,6 +428,28 @@
phy_type = hsic;
};
+ ehci2: usb@00a02000 {
+ compatible = allwinner,sun9i-a80-ehci, generic-ehci;
+ reg = 0x00a02000 0x100;
+ interrupts = GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 5;
+ resets = usb_mod_clk 19;
+ phys = usbphy3;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ ohci2: usb@00a02400 {
+ compatible = allwinner,sun9i-a80-ohci, generic-ohci;
+ reg = 0x00a02400 0x100;
+ interrupts = GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH;
+ clocks = usb_mod_clk 5, usb_mod_clk 6;
+ resets = usb_mod_clk 19;
+ phys = usbphy3;
+ phy-names = usb;
+ status = disabled;
+ };
+
usbphy3: phy@00a02800 {
compatible = allwinner,sun9i-a80-usb-phy;
reg = 0x00a02800 0x4;
--
2.1.4
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[PATCH v3 09/10] ARM: sunxi_defconfig: Enable CONFIG_PHY_SUN9I_USB
On sun9i we have a new PHY driver for USB. Signed-off-by: Chen-Yu Tsai w...@csie.org --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 38840a812924..6b271645eb43 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -106,6 +106,7 @@ CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUNXI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN9I_USB=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 02/10] clk: sunxi: Add support for sun9i A80 USB clocks and resets
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.
Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++
drivers/clk/sunxi/clk-usb.c | 43 +++
2 files changed, 45 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 60b44285250d..3f1dcd879af7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -66,6 +66,8 @@ Required properties:
allwinner,sun4i-a10-usb-clk - for usb gates + resets on A10 / A20
allwinner,sun5i-a13-usb-clk - for usb gates + resets on A13
allwinner,sun6i-a31-usb-clk - for usb gates + resets on A31
+ allwinner,sun9i-a80-usb-mod-clk - for usb gates + resets on A80
+ allwinner,sun9i-a80-usb-phy-clk - for usb phy gates + resets on A80
Required properties for all clocks:
- reg : shall be the control register address for the clock.
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
index f1dcc8fb5a7d..a86ed2f8d7af 100644
--- a/drivers/clk/sunxi/clk-usb.c
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -29,6 +29,7 @@
struct usb_reset_data {
void __iomem*reg;
spinlock_t *lock;
+ struct clk *clk;
struct reset_controller_dev rcdev;
};
@@ -41,12 +42,14 @@ static int sunxi_usb_reset_assert(struct
reset_controller_dev *rcdev,
unsigned long flags;
u32 reg;
+ clk_prepare_enable(data-clk);
spin_lock_irqsave(data-lock, flags);
reg = readl(data-reg);
writel(reg ~BIT(id), data-reg);
spin_unlock_irqrestore(data-lock, flags);
+ clk_disable_unprepare(data-clk);
return 0;
}
@@ -60,12 +63,14 @@ static int sunxi_usb_reset_deassert(struct
reset_controller_dev *rcdev,
unsigned long flags;
u32 reg;
+ clk_prepare_enable(data-clk);
spin_lock_irqsave(data-lock, flags);
reg = readl(data-reg);
writel(reg | BIT(id), data-reg);
spin_unlock_irqrestore(data-lock, flags);
+ clk_disable_unprepare(data-clk);
return 0;
}
@@ -84,6 +89,7 @@ static struct reset_control_ops sunxi_usb_reset_ops = {
struct usb_clk_data {
u32 clk_mask;
u32 reset_mask;
+ bool reset_needs_clk;
};
static void __init sunxi_usb_clk_setup(struct device_node *node,
@@ -146,6 +152,15 @@ static void __init sunxi_usb_clk_setup(struct device_node
*node,
if (!reset_data)
return;
+ if (data-reset_needs_clk) {
+ reset_data-clk = of_clk_get(node, 0);
+ if (IS_ERR(reset_data-clk)) {
+ pr_err(Could not get clock for reset controls\n);
+ kfree(reset_data);
+ return;
+ }
+ }
+
reset_data-reg = reg;
reset_data-lock = lock;
reset_data-rcdev.nr_resets = __fls(data-reset_mask) + 1;
@@ -188,3 +203,31 @@ static void __init sun6i_a31_usb_setup(struct device_node
*node)
sunxi_usb_clk_setup(node, sun6i_a31_usb_clk_data, sun4i_a10_usb_lock);
}
CLK_OF_DECLARE(sun6i_a31_usb, allwinner,sun6i-a31-usb-clk,
sun6i_a31_usb_setup);
+
+static const struct usb_clk_data sun9i_a80_usb_mod_data __initconst = {
+ .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
+ .reset_mask = BIT(19) | BIT(18) | BIT(17),
+ .reset_needs_clk = 1,
+};
+
+static DEFINE_SPINLOCK(a80_usb_mod_lock);
+
+static void __init sun9i_a80_usb_mod_setup(struct device_node *node)
+{
+ sunxi_usb_clk_setup(node, sun9i_a80_usb_mod_data, a80_usb_mod_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_usb_mod, allwinner,sun9i-a80-usb-mod-clk,
sun9i_a80_usb_mod_setup);
+
+static const struct usb_clk_data sun9i_a80_usb_phy_data __initconst = {
+ .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
+ .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
+ .reset_needs_clk = 1,
+};
+
+static DEFINE_SPINLOCK(a80_usb_phy_lock);
+
+static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
+{
+ sunxi_usb_clk_setup(node, sun9i_a80_usb_phy_data, a80_usb_phy_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_usb_phy, allwinner,sun9i-a80-usb-phy-clk,
sun9i_a80_usb_phy_setup);
--
2.1.4
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[PATCH v3 08/10] ARM: dts: sun9i: Enable USB support on A80 Optimus board
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c4de9cb9a5f6..16d30bb3a872 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -83,6 +83,18 @@
};
};
+ehci0 {
+ status = okay;
+};
+
+ehci1 {
+ status = okay;
+};
+
+ehci2 {
+ status = okay;
+};
+
i2c3 {
pinctrl-names = default;
pinctrl-0 = i2c3_pins_a;
@@ -94,6 +106,14 @@
allwinner,pull = SUN4I_PINCTRL_PULL_UP;
};
+ohci0 {
+ status = okay;
+};
+
+ohci2 {
+ status = okay;
+};
+
pio {
led_pins_optimus: led-pins@0 {
allwinner,pins = PH0, PH1;
@@ -108,6 +128,20 @@
allwinner,drive = SUN4I_PINCTRL_10_MA;
allwinner,pull = SUN4I_PINCTRL_PULL_UP;
};
+
+ usb1_vbus_pin_optimus: usb1_vbus_pin@1 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_out;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_NO_PULL;
+ };
+
+ usb3_vbus_pin_optimus: usb3_vbus_pin@1 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_out;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_NO_PULL;
+ };
};
mmc0 {
@@ -129,6 +163,18 @@
status = okay;
};
+reg_usb1_vbus {
+ pinctrl-0 = usb1_vbus_pin_optimus;
+ gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ status = okay;
+};
+
+reg_usb3_vbus {
+ pinctrl-0 = usb3_vbus_pin_optimus;
+ gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ status = okay;
+};
+
uart0 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_a;
@@ -145,3 +191,17 @@
/* Enable internal pull-up */
allwinner,pull = SUN4I_PINCTRL_PULL_UP;
};
+
+usbphy1 {
+ vbus-supply = reg_usb1_vbus;
+ status = okay;
+};
+
+usbphy2 {
+ status = okay;
+};
+
+usbphy3 {
+ vbus-supply = reg_usb3_vbus;
+ status = okay;
+};
--
2.1.4
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Re: [PATCH v1 1/2] mmc: host: arasan: Add addition of-arasan quirks and IOMMU support for arasan SDHCI driver.
On Tuesday 27 January 2015 22:50:59 Suman Tripathi wrote:
@@ -174,6 +176,13 @@ static int sdhci_arasan_probe(struct platform_device
*pdev)
pltfm_host-priv = sdhci_arasan;
pltfm_host-clk = clk_xin;
+ ret = xgene_ahbc_iommu_attach_device(pdev-dev);
+ if (ret 0 IS_ENABLED(CONFIG_XGENE_AHBC_IOMMU)) {
+ dev_err(pdev-dev,
+ unable to attach device to iommu %x\n, ret);
+ goto clk_disable_all;
+ }
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(pdev-dev, platform register failed (%u)\n, ret);
This looks wrong: the iommu should be automatically configured for devices
that need it, without any interaction from the driver.
Arnd
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Re: [PATCH v4 4/6] of/pci: add of_pci_dma_configure() update dma configuration
On 01/26/2015 06:59 PM, Bjorn Helgaas wrote:
On Mon, Jan 26, 2015 at 5:25 PM, Murali Karicherim-kariche...@ti.com wrote:
On 01/23/2015 06:41 PM, Bjorn Helgaas wrote:
On Fri, Jan 23, 2015 at 05:32:37PM -0500, Murali Karicheri wrote:
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device.
-- Cut ---
Signed-off-by: Murali Karicherim-kariche...@ti.com
---
drivers/of/of_pci.c| 39 +++
include/linux/of_pci.h | 12
2 files changed, 51 insertions(+)
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 88471d3..34878c9 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -2,6 +2,7 @@
#includelinux/export.h
#includelinux/of.h
#includelinux/of_address.h
+#includelinux/of_device.h
#includelinux/of_pci.h
#includelinux/slab.h
@@ -229,6 +230,44 @@ parse_failed:
return err;
}
EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+
+/**
+ * of_get_pci_root_bridge_parent - get the OF node of the root bridge's
parent
+ * @dev: ptr to pci_dev struct of the pci device
+ *
+ * This function will traverse the bus up to the root bus starting with
+ * the child and return the OF node ptr to root bridge device's parent
device.
+ */
+struct device_node *of_get_pci_root_bridge_parent(struct pci_dev *dev)
I'm not an OF person, but this interface seems like it might be too
special-purpose. Maybe it would be enough to add
of_get_pci_root_bridge(), and the caller could do this:
struct device *bridge = of_get_pci_root_bridge(dev);
struct device_node *parent_np = bridge-parent-of_node;
Also, the name of_get_... suggests that it increments a refcount, as
of_get_parent() does. But you aren't doing anything with the refcount.
But I guess an of_get_pci_root_bridge() isn't doing anything OF-related,
so maybe we should just add a pci_get_host_bridge(struct pci_dev *)
to PCI instead.
Bjorn,
Thanks for the comment.
I think adding pci_get_host_bridge() is a good idea. There is already
similar function in host-bridge.c. I have added this function re-using
existing function find_pci_root_bus(). See the incremental diff below after
this change. Does this look good?
I like the implementation, but I think either we need to take a
reference on the host bridge, or change the name to something like
pci_find_host_bridge(), because using _get_ is conventional for
functions that acquire a reference.
Since host bridges are hot-pluggable, at least in theory, I vote for
taking a reference. Then of course, you'd have to add code to drop
the reference when you're finished with it.
Bjorn,
Thanks. I agree with your suggestion even though the convention is not
followed fully :) of_pci_get_devfn(), of_get_pci_domain_nr(),
of_pci_get_host_bridge_resources() are some of those functions not
following the convention. I plan to change the function as below. Also
want to name functions as pci_get/put_host_bridge_device() as existing
function find_pci_host_bridge() is actually returning ptr to struct
pci_host_bridge vs the new function returning ptr to device. Here are
the new functions and how they will be used. Please review and respond
so that I can avoid a re-spin.
in linux/include/pci.h add the prototypes of
pci_get/put_host_bridge_device().
in drivers/pci/host-bridge.c add two new functions.
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_get(bridge-kobj);
return bridge;
}
void pci_put_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_put(bridge-kobj);
}
drivers/of/of_pci.c
void of_pci_dma_configure(struct pci_dev *pci_dev)
{
struct device *dev = pci_dev-dev;
struct device *bridge = pci_get_host_bridge_device(pci_dev);
of_dma_configure(dev, bridge-parent-of_node);
pci_put_host_bridge_device(pci_dev);
}
Murali
Bjorn
--
Murali Karicheri
Linux Kernel, Texas Instruments
--
Murali Karicheri
Linux Kernel, Texas Instruments
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Re: [PATCH v4 3/5] drivers: bus: Add Simple Power-Managed Bus DT Bindings
On Mon, Jan 26, 2015 at 04:16:15PM +, Geert Uytterhoeven wrote: Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be Tested-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com --- v4: - Replace simple-bus by simple-pm-bus, - Remove the renesas,bsc bindings. They will be specified in a separate document. v3: - Add Tested-by, - Document required properties inherited from simple-bus, - Document required reg property for renesas,bsc, - Move ranges before reg in the example, v2: - New. --- .../devicetree/bindings/bus/simple-pm-bus.txt | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/simple-pm-bus.txt diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt new file mode 100644 index ..0415e93a816c5ac0 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt @@ -0,0 +1,41 @@ +Simple Power-Managed Bus + + +A Simple Power-Managed Bus is a transparent bus that doesn't need a real +driver, as it's typically initialized by the boot loader. + +However, its bus controller is part of a PM domain, or under the control of a +functional clock. Hence, the bus controller's PM domain and/or clock must be +enabled for child devices connected to the bus (either on-SoC or externally) +to function. + +The bindings for the Simple Power-Managed Bus extend the bindings for +simple-bus, as specified in ePAPR. I would note that simple-pm-bus follows the simple-bus set of properties, but is not an extension of simple-bus. For the reasons I mentioned previously, I don't think that any simple-pm-bus should be simple-bus compatible (and I believe we should document that requirement below). + + +Required properties: + - compatible: Must contain at least simple-pm-bus. + It's recommended to let this be preceded by one or more + vendor-specific compatible values. + - #address-cells, #size-cells, ranges: Must describe the mapping between + parent address and child address spaces. + +Optional platform-specific properties for clock or PM domain control (at least +one of them is required): + - clocks: Must contain a reference to the functional clock(s), I'm a little worried about the clocks. What are the expectations on their configuration? I don't see how we can generally rely on the clock configuration being correct unless the input clocks only have on/off controls, and the OS doesn't see any of the parent clock tree it could potentially change the configuration of (beyond on/off). Otherwise we're relying on implicit behaviour elsewhere in Linux (which _will_ break over time), and this ends up not being usable by anything else. I'm coming to the opinion that while we might be able to have common driver in Linux, we can't have a common simple-pm-bus binding because it implicitly assumes too much about the OS behaviour. Thanks, Mark. -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH v4 1/3] ASoC: samsung: Add machine driver for Trats2
On Tue, Jan 27, 2015 at 06:09:39PM +0100, Sylwester Nawrocki wrote:
On 23/01/15 06:03, Inha Song wrote:
+ priv-clk_mclk = of_clk_get_by_name(codec_node, MCLK1);
+ if (IS_ERR(priv-clk_mclk)) {
+ dev_err(pdev-dev, Failed to get mclk clock\n);
+ of_node_put(codec_node);
+ return PTR_ERR(priv-clk_mclk);
+ }
Wouldn't it also work if we added clock handling into the wm8994 codec
driver instead? Not sure if it is correct to retrieve the codec's clock
in the machine driver like this. Or perhaps the MCLK1 (SoC CLKOUT) clock
should be added to the sound DT node and handled only by the machine
driver, together with the other (MCLK2) clock?
That's definitely where we should end up but there are practical issues
with that approach since it involves coordination with all the machine
drivers using the device.
signature.asc
Description: Digital signature
Re: [PATCH 2/2] watchdog: jz4740: Add DT support
On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
};
+#ifdef CONFIG_OF
+static const struct of_device_id jz4740_of_matches[] = {
+ { .compatible = ingenic,jz4740-watchdog, },
+ { /* sentinel */ }
+};
+#endif
+
static int jz4740_wdt_probe(struct platform_device *pdev)
{
struct jz4740_wdt_drvdata *drvdata;
@@ -211,6 +219,7 @@ static struct platform_driver jz4740_wdt_driver = {
.remove = jz4740_wdt_remove,
.driver = {
.name = jz4740-wdt,
+ .of_match_table = of_match_ptr(jz4740_of_matches),
},
Why the #ifdef? Presumably we want to move over jz4740 to DT-only in the
long run, so you could just remove the #ifdef and the of_match_ptr()
wrapper.
Also, you should add a MODULE_DEVICE_TABLE() entry.
Arnd
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Re: [PATCH] ahci_xgene: Fix the dma state machine lockup for the ATA_CMD_SMART PIO mode command.
On Tue, Jan 27, 2015 at 11:26:11PM +0530, Suman Tripathi wrote: This patch addresses the issue with ATA_CMD_SMART pio mode command for enumeration and device detection with ATA devices.It is the same issue as in patch www.spinics.net/lists/linux-ide/msg49092.html The link is broken. Can you please include at least a brief explanation of the problem and preferably link to something more permanant (commit ID, http://lkml.kernel.org/g/MSG_ID)? Thanks. -- tejun -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/6] of: fix size when dma-range is not used
On 01/27/2015 06:27 AM, Robin Murphy wrote:
Hi Murali,
On 23/01/15 22:32, Murali Karicheri wrote:
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev-coherent_dma_mask + 1 instead of dev-coherent_dma_mask. To detect
overflow when mask is set to max of u64, add a check, log error and
return.
Some platform use mask format for size in DTS. So add a work around to
catch this and fix.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/of/device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 2de320d..0a5ff54 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -105,12 +105,24 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
ret = of_dma_get_range(np, dma_addr, paddr, size);
if (ret 0) {
dma_addr = offset = 0;
- size = dev-coherent_dma_mask;
+ size = dev-coherent_dma_mask + 1;
} else {
offset = PFN_DOWN(paddr - dma_addr);
+ /*
+ * Add a work around to treat the size as mask + 1 in case
+ * it is defined in DT as a mask.
+ */
+ if (size 1)
+ size = size + 1;
dev_dbg(dev, dma_pfn_offset(%#08lx)\n, offset);
}
+ /* if size is 0, we have an overflow of u64 */
+ if (!size) {
+ dev_err(dev, invalid size\n);
+ return;
+ }
+
This seems potentially fragile to dodgy DTs given that we might also be
using size to make a mask later. Would it make sense to double-up a
sanity check as mask-format detection? Something like:
if is_power_of_2(size)
// use size
else if is_power_of_2(size + 1)
// use size + 1
else
// cry
Robin,
How about having the logic like this?
ret = of_dma_get_range(np, dma_addr, paddr, size);
if (ret 0) {
dma_addr = offset = 0;
size = dev-coherent_dma_mask + 1;
} else {
offset = PFN_DOWN(paddr - dma_addr);
dev_dbg(dev, dma_pfn_offset(%#08lx)\n, offset);
}
if (is_power_of_2(size + 1))
size = size + 1;
else if (!is_power_of_2(size))
{
dev_err(dev, invalid size\n);
return;
}
Murali
Robin.
dev-dma_pfn_offset = offset;
coherent = of_dma_is_coherent(np);
--
Murali Karicheri
Linux Kernel, Texas Instruments
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Re: [PATCH] usb: phy-generic: Don't fail on missing gpio reset
On Tue, Jan 27, 2015 at 11:13:08AM -0800, Sören Brinkmann wrote:
On Tue, 2015-01-27 at 09:20AM -0600, Felipe Balbi wrote:
On Mon, Jan 26, 2015 at 05:45:29PM -0800, Soren Brinkmann wrote:
A reset through a GPIO is optional. Don't fail probing when it is
missing.
Reported-by: Andreas Färber afaer...@suse.de
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
Hi Andreas,
does this do the trick?
Thanks,
Sören
drivers/usb/phy/phy-generic.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c
index dd05254241fb..a73d4c738f0b 100644
--- a/drivers/usb/phy/phy-generic.c
+++ b/drivers/usb/phy/phy-generic.c
@@ -241,10 +241,8 @@ int usb_phy_gen_create_phy(struct device *dev,
struct usb_phy_generic *nop,
if (err == -EPROBE_DEFER)
return -EPROBE_DEFER;
- if (err) {
- dev_err(dev, Error requesting RESET GPIO\n);
- return err;
- }
+ if (err)
+ nop-gpiod_reset = NULL;
there's a better patch to use gpiod_get_optional(), instead.
Great, apparently that wasn't in linux-next yesterday. I'll give it a
shot once it arrives there.
It's still under discussion ;-)
--
balbi
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Description: Digital signature
[PATCH 0/7 RESEND] ASoC: pcm512x: Clock master modes
From: Peter Rosin p...@axentia.se Hi! [ Note that the dt change is in patch 5/7, for those only interested in that particular bit. ] This series implements BCLK master modes for the pcm512x driver. It has only been tested with the pcm5142 chip, but they are from the same family and should be compatible. I have mainly used the spec for the newer pcm5242 chip (also from the same family) as it fills in a lot of blanks in the pcm512x/pcm514x specs. The code has also seen most of its testing in a 3.10 environment, so there might be some forward-porting warts. But it is able to play sound in 3.18 as well, and most of the changes have little to do with anything but the clocking in the chip itself. This is technically not a clean resend, since I'm now sending the whole series to all parties, hopefully using the correct email addesses this time. I have also augmented the commit message of patch 1/7 according to the review comments by Lars-Peter Clausen. Cheers, Peter Peter Rosin (7): ALSA: pcm: Add snd_interval_ranges() and snd_pcm_hw_constraint_ranges() ASoC: pcm512x: Fix spelling of register field names. ASoC: pcm512x: Change register default to match actual content after reset ASoC: pcm512x: Support mastering BCLK/LRCLK without using the PLL ASoC: pcm512x: Support mastering BCLK/LRCLK using the PLL ASoC: pcm512x: Avoid the PLL for the DAC clock, if possible ASoC: pcm512x: Support SND_SOC_DAIFMT_CBM_CFS .../devicetree/bindings/sound/pcm512x.txt | 25 +- include/sound/pcm.h| 12 + sound/core/pcm_lib.c | 85 ++ sound/soc/codecs/pcm512x.c | 955 +++- sound/soc/codecs/pcm512x.h | 109 ++- 5 files changed, 1161 insertions(+), 25 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/6] of/pci: add of_pci_dma_configure() update dma configuration
On 01/27/2015 01:42 PM, Bjorn Helgaas wrote:
On Tue, Jan 27, 2015 at 12:14 PM, Murali Karicherim-kariche...@ti.com wrote:
On 01/26/2015 06:59 PM, Bjorn Helgaas wrote:
On Mon, Jan 26, 2015 at 5:25 PM, Murali Karicherim-kariche...@ti.com
wrote:
On 01/23/2015 06:41 PM, Bjorn Helgaas wrote:
On Fri, Jan 23, 2015 at 05:32:37PM -0500, Murali Karicheri wrote:
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device.
-- Cut ---
Signed-off-by: Murali Karicherim-kariche...@ti.com
---
drivers/of/of_pci.c| 39
+++
include/linux/of_pci.h | 12
2 files changed, 51 insertions(+)
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 88471d3..34878c9 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -2,6 +2,7 @@
#includelinux/export.h
#includelinux/of.h
#includelinux/of_address.h
+#includelinux/of_device.h
#includelinux/of_pci.h
#includelinux/slab.h
@@ -229,6 +230,44 @@ parse_failed:
return err;
}
EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+
+/**
+ * of_get_pci_root_bridge_parent - get the OF node of the root
bridge's
parent
+ * @dev: ptr to pci_dev struct of the pci device
+ *
+ * This function will traverse the bus up to the root bus starting
with
+ * the child and return the OF node ptr to root bridge device's parent
device.
+ */
+struct device_node *of_get_pci_root_bridge_parent(struct pci_dev *dev)
I'm not an OF person, but this interface seems like it might be too
special-purpose. Maybe it would be enough to add
of_get_pci_root_bridge(), and the caller could do this:
struct device *bridge = of_get_pci_root_bridge(dev);
struct device_node *parent_np = bridge-parent-of_node;
Also, the name of_get_... suggests that it increments a refcount, as
of_get_parent() does. But you aren't doing anything with the refcount.
But I guess an of_get_pci_root_bridge() isn't doing anything
OF-related,
so maybe we should just add a pci_get_host_bridge(struct pci_dev *)
to PCI instead.
Bjorn,
Thanks for the comment.
I think adding pci_get_host_bridge() is a good idea. There is already
similar function in host-bridge.c. I have added this function re-using
existing function find_pci_root_bus(). See the incremental diff below
after
this change. Does this look good?
I like the implementation, but I think either we need to take a
reference on the host bridge, or change the name to something like
pci_find_host_bridge(), because using _get_ is conventional for
functions that acquire a reference.
Since host bridges are hot-pluggable, at least in theory, I vote for
taking a reference. Then of course, you'd have to add code to drop
the reference when you're finished with it.
Bjorn,
Thanks. I agree with your suggestion even though the convention is not
followed fully :) of_pci_get_devfn(), of_get_pci_domain_nr(),
of_pci_get_host_bridge_resources() are some of those functions not following
the convention. I plan to change the function as below. Also want to name
functions as pci_get/put_host_bridge_device() as existing function
find_pci_host_bridge() is actually returning ptr to struct pci_host_bridge
vs the new function returning ptr to device. Here are the new functions and
how they will be used. Please review and respond so that I can avoid a
re-spin.
in linux/include/pci.h add the prototypes of
pci_get/put_host_bridge_device().
in drivers/pci/host-bridge.c add two new functions.
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_get(bridge-kobj);
return bridge;
}
Looks good to me.
void pci_put_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_put(bridge-kobj);
}
I think I would pass in the struct device * here so we don't have to
call find_pci_root_bus() again.
drivers/of/of_pci.c
void of_pci_dma_configure(struct pci_dev *pci_dev)
{
struct device *dev =pci_dev-dev;
struct device *bridge = pci_get_host_bridge_device(pci_dev);
of_dma_configure(dev, bridge-parent-of_node);
pci_put_host_bridge_device(pci_dev);
Then this would become pci_put_host_bridge_device(bridge)
Agree with both. Will become part of my v5 of the series. I am adding
this as a separate commit.
Murali
}
Murali
Bjorn
--
Murali Karicheri
Linux Kernel, Texas Instruments
--
Murali Karicheri
Linux Kernel, Texas Instruments
--
Murali Karicheri
Linux Kernel, Texas Instruments
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Re: [PATCH] usb: phy-generic: Don't fail on missing gpio reset
On Tue, 2015-01-27 at 09:20AM -0600, Felipe Balbi wrote:
On Mon, Jan 26, 2015 at 05:45:29PM -0800, Soren Brinkmann wrote:
A reset through a GPIO is optional. Don't fail probing when it is
missing.
Reported-by: Andreas Färber afaer...@suse.de
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
Hi Andreas,
does this do the trick?
Thanks,
Sören
drivers/usb/phy/phy-generic.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c
index dd05254241fb..a73d4c738f0b 100644
--- a/drivers/usb/phy/phy-generic.c
+++ b/drivers/usb/phy/phy-generic.c
@@ -241,10 +241,8 @@ int usb_phy_gen_create_phy(struct device *dev, struct
usb_phy_generic *nop,
if (err == -EPROBE_DEFER)
return -EPROBE_DEFER;
- if (err) {
- dev_err(dev, Error requesting RESET GPIO\n);
- return err;
- }
+ if (err)
+ nop-gpiod_reset = NULL;
there's a better patch to use gpiod_get_optional(), instead.
Great, apparently that wasn't in linux-next yesterday. I'll give it a
shot once it arrives there.
Sören
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Re: [PATCH RFC 2/3] power: mxs_power: add driver for mxs power subsystem
On Tue, Jan 27, 2015 at 07:35:09PM +0100, Stefan Wahren wrote:
Mark Brown broo...@kernel.org hat am 27. Januar 2015 um 01:16 geschrieben:
okay i understand. But doesn't it need a extra driver to set the switching
frequency because of the new compatible string?
I don't understand this bit at all, sorry.
Sebastian suggested a new sub-node in the devicetree:
powerpll {
compatible = fsl,imx28-power-pll
#clock-cells = 0;
clock-frequency = 12345;
}
and i think that the new compatible string needs a separate driver to take
care
of the switching frequency.
I can see that this has been suggested, what I can't understand is why
we would wish to do this but I am missing some context here which may
make it all perfectly clear.
Or is it okay to leave the handling of the switching frequency in the
mxs-power
driver?
Unless the clock is exposed externally to the regulator either as an
input or an output I'm not sure I see any benefit but I'm possibly
missing something here. It does sound like there might be a separate
clock IP or something?
Btw if we add a new node to set switching frequency, i think it would be
better
to describe the dc-dc convertor and not the pll:
dcdc {
compatible = fsl,imx28-dcdc
frequency = 12345;
}
What do you think?
Yes, just adding a new property on the regulator node with all the other
properties seems sensible (we've just gained some helpers which make it
fairly straightforward to do this).
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Description: Digital signature
[PATCH v3 01/10] clk: sunxi: Move USB clocks to separate file
The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without affecting gates clocks, and also facilitate the
migration of gates clocks to a generic solution.
This also cleans up the USB clocks code slightly, such as adding
newlines, getting rid of the unused clkdev call, using a simple
u32 instead of BITMAP for the clock masks, using BIT() macro to
declare the clock bitmasks, and using of_io_request_and_map() to
get the I/O address.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
This patch does quite a few cleanups in addition to the code movement.
I'm not sure if it's acceptable.
---
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-sunxi.c | 88 ---
drivers/clk/sunxi/clk-usb.c | 190 ++
3 files changed, 191 insertions(+), 88 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-usb.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3a5292e3fcf8..058f273d6154 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-mod0.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
+obj-y += clk-usb.o
obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 24c7cc12e9e1..af23be24d736 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -835,59 +835,6 @@ static void __init sunxi_divider_clk_setup(struct
device_node *node,
/**
- * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
- */
-
-struct gates_reset_data {
- void __iomem*reg;
- spinlock_t *lock;
- struct reset_controller_dev rcdev;
-};
-
-static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct gates_reset_data *data = container_of(rcdev,
-struct gates_reset_data,
-rcdev);
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(data-lock, flags);
-
- reg = readl(data-reg);
- writel(reg ~BIT(id), data-reg);
-
- spin_unlock_irqrestore(data-lock, flags);
-
- return 0;
-}
-
-static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct gates_reset_data *data = container_of(rcdev,
-struct gates_reset_data,
-rcdev);
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(data-lock, flags);
-
- reg = readl(data-reg);
- writel(reg | BIT(id), data-reg);
-
- spin_unlock_irqrestore(data-lock, flags);
-
- return 0;
-}
-
-static struct reset_control_ops sunxi_gates_reset_ops = {
- .assert = sunxi_gates_reset_assert,
- .deassert = sunxi_gates_reset_deassert,
-};
-
-/**
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
*/
@@ -895,7 +842,6 @@ static struct reset_control_ops sunxi_gates_reset_ops = {
struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
- u32 reset_mask;
};
static const struct gates_data sun4i_axi_gates_data __initconst = {
@@ -994,26 +940,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data
__initconst = {
.mask = {0x1F0007},
};
-static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
- .mask = {0x1C0},
- .reset_mask = 0x07,
-};
-
-static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
- .mask = {0x140},
- .reset_mask = 0x03,
-};
-
-static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
- .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
- .reset_mask = BIT(2) | BIT(1) | BIT(0),
-};
-
static void __init sunxi_gates_clk_setup(struct device_node *node,
struct gates_data *data)
{
struct clk_onecell_data *clk_data;
- struct gates_reset_data *reset_data;
const char *clk_parent;
const char *clk_name;
void __iomem *reg;
@@ -1054,21 +984,6 @@ static void __init sunxi_gates_clk_setup(struct
device_node *node,
clk_data-clk_num = i;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- /* Register a reset controler for gates with reset bits */
- if (data-reset_mask == 0)
- return;
-
- reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
- if (!reset_data)
- return;
-
-
[PATCH v3 10/10] ARM: multi_v7_defconfig: Enable CONFIG_PHY_SUN9I_USB
On sun9i we have a new PHY driver for USB. Signed-off-by: Chen-Yu Tsai w...@csie.org --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index eec304487e6d..63fcc5522393 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -462,6 +462,7 @@ CONFIG_TI_PIPE3=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_STIH41X_USB=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN9I_USB=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 03/10] ARM: dts: sun9i: Add usb clock nodes to a80 dtsi
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 9e28ffc6dd90..679cf2878800 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -147,6 +147,28 @@
clock-output-names = osc32k;
};
+ usb_mod_clk: clk@00a08000 {
+ #clock-cells = 1;
+ #reset-cells = 1;
+ compatible = allwinner,sun9i-a80-usb-mod-clk;
+ reg = 0x00a08000 0x4;
+ clocks = ahb1_gates 1;
+ clock-output-names = usb0_ahb, usb_ohci0,
+usb1_ahb, usb_ohci1,
+usb2_ahb, usb_ohci2;
+ };
+
+ usb_phy_clk: clk@00a08004 {
+ #clock-cells = 1;
+ #reset-cells = 1;
+ compatible = allwinner,sun9i-a80-usb-phy-clk;
+ reg = 0x00a08004 0x4;
+ clocks = ahb1_gates 1;
+ clock-output-names = usb_phy0, usb_hsic1_480M,
+usb_phy1, usb_hsic2_480M,
+usb_phy2, usb_hsic_12M;
+ };
+
pll4: clk@060c {
#clock-cells = 0;
compatible = allwinner,sun9i-a80-pll4-clk;
--
2.1.4
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[PATCH v3 00/10] ARM: sun9i: Add USB host controller support for A80
Hi everyone, This is v3 of the sun9i A80 USB host support series. This series adds USB host controller (EHCI/OHCI) support for the Allwinner A80 SoC. The A80 has 3 pairs of host controllers and USB PHYs. The PHYs, unlike in previous SoCs, do not have low level control registers anymore. As such, this series forgoes the original phy-sun4i-usb driver, and adds a new, simpler driver for the USB PHYs. It may be possible to merge the two, but given that work is being done on the OTG front for the earlier SoCs, it may be better to merge them after support is complete. EHCI/OHCI0 corresponds to USB1 DP/DM pins; EHCI1 only has HSIC support; EHCI2/OHCI/2 is USB2 DP/DM externally. External pins labeled USB0 are for the USB 3.0 OTG controller. Changes since v2: - Split out current USB clock/reset code with a separate patch. Changes since v1: - Rework usb clock/reset driver to only enable ahb gate when child clock gates are enabled. - Add AHB_INCR16_BURST flag and HSIC specific bits to phy driver. - Renumber USB PHYs according to sunxi tradition, usbphy0 for OTG, usbphy1 and later for xHCI. - Add VBUS regulator for usb3 to sunxi common regulators. - Use common regulators for usb vbus regulators. - Adapt to label references in board dts file. - Use gpio and pinctrl macros in dts. Patch 1 moves the usb gate clocks and resets driver to a separate file. Patch 2 adds a80 specific support for usb-related clocks and resets. Patch 3 adds the device tree nodes for the usb clocks. Patch 4 adds a new generic phy driver for a80 usb phys. This has some code that is the same as the original phy-sun4i-usb driver, but is simpler. Patch 5 adds the 3 USB PHY nodes to the a80 dtsi. Patch 6 adds the USB host controller nodes to the a80 dtsi. Patch 7 adds a VBUS regulator for usb3 to sunxi common regulators. Patch 8 enables USB on the A80 Optimus board. Patch 9 enables sun9i USB PHY in sunxi_defconfig. Patch 10 enables sun9i USB PHY in multi_v7_defconfig. Regards, ChenYu Chen-Yu Tsai (10): clk: sunxi: Move USB clocks to separate file clk: sunxi: Add support for sun9i A80 USB clocks and resets ARM: dts: sun9i: Add usb clock nodes to a80 dtsi phy: Add driver to support individual USB PHYs on sun9i ARM: dts: sun9i: Add usb phy nodes to a80 dtsi ARM: dts: sun9i: Add USB host controller nodes to a80 dtsi ARM: dts: sunxi: Add usb3_vbus regulator to common regulators dtsi ARM: dts: sun9i: Enable USB support on A80 Optimus board ARM: sunxi_defconfig: Enable CONFIG_PHY_SUN9I_USB ARM: multi_v7_defconfig: Enable CONFIG_PHY_SUN9I_USB Documentation/devicetree/bindings/clock/sunxi.txt | 2 + .../devicetree/bindings/phy/sun9i-usb-phy.txt | 34 +++ arch/arm/boot/dts/sun9i-a80-optimus.dts| 60 ++ arch/arm/boot/dts/sun9i-a80.dtsi | 129 +++ arch/arm/boot/dts/sunxi-common-regulators.dtsi | 10 + arch/arm/configs/multi_v7_defconfig| 1 + arch/arm/configs/sunxi_defconfig | 1 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-sunxi.c | 88 drivers/clk/sunxi/clk-usb.c| 233 drivers/phy/Kconfig| 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-sun9i-usb.c| 238 + 13 files changed, 722 insertions(+), 88 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt create mode 100644 drivers/clk/sunxi/clk-usb.c create mode 100644 drivers/phy/phy-sun9i-usb.c -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 05/10] ARM: dts: sun9i: Add usb phy nodes to a80 dtsi
On sun9i, there are 3 independent usb phys for EHCI/OHCI.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 679cf2878800..d7ebd9390b01 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -355,6 +355,43 @@
*/
ranges = 0 0 0 0x2000;
+ usbphy1: phy@00a00800 {
+ compatible = allwinner,sun9i-a80-usb-phy;
+ reg = 0x00a00800 0x4;
+ clocks = usb_phy_clk 1;
+ clock-names = phy;
+ resets = usb_phy_clk 17;
+ reset-names = phy;
+ status = disabled;
+ #phy-cells = 0;
+ };
+
+ usbphy2: phy@00a01800 {
+ compatible = allwinner,sun9i-a80-usb-phy;
+ reg = 0x00a01800 0x4;
+ clocks = usb_phy_clk 2, usb_phy_clk 10,
+usb_phy_clk 3;
+ clock-names = hsic_480M, hsic_12M, phy;
+ resets = usb_phy_clk 18, usb_phy_clk 19;
+ reset-names = hsic, phy;
+ status = disabled;
+ #phy-cells = 0;
+ /* usb1 is always used with HSIC */
+ phy_type = hsic;
+ };
+
+ usbphy3: phy@00a02800 {
+ compatible = allwinner,sun9i-a80-usb-phy;
+ reg = 0x00a02800 0x4;
+ clocks = usb_phy_clk 4, usb_phy_clk 10,
+usb_phy_clk 5;
+ clock-names = hsic_480M, hsic_12M, phy;
+ resets = usb_phy_clk 20, usb_phy_clk 21;
+ reset-names = hsic, phy;
+ status = disabled;
+ #phy-cells = 0;
+ };
+
mmc0: mmc@01c0f000 {
compatible = allwinner,sun5i-a13-mmc;
reg = 0x01c0f000 0x1000;
--
2.1.4
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[PATCH v3] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
Add support for the LinkSprite pcDuino 3 Nano board. This is a low-cost
Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM,
4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and
another for power in, HDMI, SATA, 5V power for SATA devices, gigabit
Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector.
For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano
Changes in v3:
- rename LEDs to pcduino3-nano:green:usr[12]
- remove optional features on Arduino headers (i2c2, spi0, uart2)
Signed-off-by: Adam Sampson a...@offog.org
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 191 ++
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7df26a2..c025724 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -479,7 +479,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-micro.dtb \
- sun7i-a20-pcduino3.dtb
+ sun7i-a20-pcduino3.dtb \
+ sun7i-a20-pcduino3-nano.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
new file mode 100644
index 000..632b8a9
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2015 Adam Sampson a...@offog.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun7i-a20.dtsi
+#include sunxi-common-regulators.dtsi
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+/ {
+ model = LinkSprite pcDuino3 Nano;
+ compatible = linksprite,pcduino3-nano, allwinner,sun7i-a20;
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_pcduino3_nano;
+
+ /* Marked LED3 on the PCB. */
+ usr1 {
+ label = pcduino3-nano:green:usr1;
+ gpios = pio 7 16 GPIO_ACTIVE_LOW; /* PH16 */
+ };
+
+ /* Marked LED4 on the PCB. */
+ usr2 {
+ label = pcduino3-nano:green:usr2;
+ gpios = pio 7 15 GPIO_ACTIVE_LOW; /* PH15 */
+ };
+ };
+};
+
+ahci {
+ target-supply = reg_ahci_5v;
+ status = okay;
+};
+
+ehci0 {
+ status = okay;
+};
+
+ehci1 {
+ status = okay;
+};
+
+gmac {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_rgmii_a;
+
Re: [PATCH RFC 2/3] power: mxs_power: add driver for mxs power subsystem
Hi Mark,
Mark Brown broo...@kernel.org hat am 27. Januar 2015 um 01:16 geschrieben:
On Mon, Jan 26, 2015 at 08:46:45PM +0100, Stefan Wahren wrote:
Does a common property name exists for the switching frequency or would
it be vendor specific?
As far as I know most regulators have fixed switching frequencies,
so there is no common property name so far. I added regulator
framework people, since this property should be regulator specific.
No, it's pretty common for there to be a couple of options - there's
normally a performance tradeoff (power for regulation accuracy and/or
cost) which can be selected. IIRC it's selected at design time as it
affect the choice of passives on the board.
okay i understand. But doesn't it need a extra driver to set the switching
frequency because of the new compatible string?
I don't understand this bit at all, sorry.
Sebastian suggested a new sub-node in the devicetree:
powerpll {
compatible = fsl,imx28-power-pll
#clock-cells = 0;
clock-frequency = 12345;
}
and i think that the new compatible string needs a separate driver to take care
of the switching frequency.
Or is it okay to leave the handling of the switching frequency in the mxs-power
driver?
Btw if we add a new node to set switching frequency, i think it would be better
to describe the dc-dc convertor and not the pll:
dcdc {
compatible = fsl,imx28-dcdc
frequency = 12345;
}
What do you think?
Best regards
Stefan
At this point i think about moving this feature into the bootloader.
@Fabio, @Marek:
What's your opinion about that?
-- Sebastian
Stefan
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Re: [PATCH v4 4/6] of/pci: add of_pci_dma_configure() update dma configuration
On Tue, Jan 27, 2015 at 12:14 PM, Murali Karicheri m-kariche...@ti.com wrote:
On 01/26/2015 06:59 PM, Bjorn Helgaas wrote:
On Mon, Jan 26, 2015 at 5:25 PM, Murali Karicherim-kariche...@ti.com
wrote:
On 01/23/2015 06:41 PM, Bjorn Helgaas wrote:
On Fri, Jan 23, 2015 at 05:32:37PM -0500, Murali Karicheri wrote:
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device.
-- Cut ---
Signed-off-by: Murali Karicherim-kariche...@ti.com
---
drivers/of/of_pci.c| 39
+++
include/linux/of_pci.h | 12
2 files changed, 51 insertions(+)
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 88471d3..34878c9 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -2,6 +2,7 @@
#includelinux/export.h
#includelinux/of.h
#includelinux/of_address.h
+#includelinux/of_device.h
#includelinux/of_pci.h
#includelinux/slab.h
@@ -229,6 +230,44 @@ parse_failed:
return err;
}
EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+
+/**
+ * of_get_pci_root_bridge_parent - get the OF node of the root
bridge's
parent
+ * @dev: ptr to pci_dev struct of the pci device
+ *
+ * This function will traverse the bus up to the root bus starting
with
+ * the child and return the OF node ptr to root bridge device's parent
device.
+ */
+struct device_node *of_get_pci_root_bridge_parent(struct pci_dev *dev)
I'm not an OF person, but this interface seems like it might be too
special-purpose. Maybe it would be enough to add
of_get_pci_root_bridge(), and the caller could do this:
struct device *bridge = of_get_pci_root_bridge(dev);
struct device_node *parent_np = bridge-parent-of_node;
Also, the name of_get_... suggests that it increments a refcount, as
of_get_parent() does. But you aren't doing anything with the refcount.
But I guess an of_get_pci_root_bridge() isn't doing anything
OF-related,
so maybe we should just add a pci_get_host_bridge(struct pci_dev *)
to PCI instead.
Bjorn,
Thanks for the comment.
I think adding pci_get_host_bridge() is a good idea. There is already
similar function in host-bridge.c. I have added this function re-using
existing function find_pci_root_bus(). See the incremental diff below
after
this change. Does this look good?
I like the implementation, but I think either we need to take a
reference on the host bridge, or change the name to something like
pci_find_host_bridge(), because using _get_ is conventional for
functions that acquire a reference.
Since host bridges are hot-pluggable, at least in theory, I vote for
taking a reference. Then of course, you'd have to add code to drop
the reference when you're finished with it.
Bjorn,
Thanks. I agree with your suggestion even though the convention is not
followed fully :) of_pci_get_devfn(), of_get_pci_domain_nr(),
of_pci_get_host_bridge_resources() are some of those functions not following
the convention. I plan to change the function as below. Also want to name
functions as pci_get/put_host_bridge_device() as existing function
find_pci_host_bridge() is actually returning ptr to struct pci_host_bridge
vs the new function returning ptr to device. Here are the new functions and
how they will be used. Please review and respond so that I can avoid a
re-spin.
in linux/include/pci.h add the prototypes of
pci_get/put_host_bridge_device().
in drivers/pci/host-bridge.c add two new functions.
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_get(bridge-kobj);
return bridge;
}
Looks good to me.
void pci_put_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
struct device *bridge = root_bus-bridge;
kobject_put(bridge-kobj);
}
I think I would pass in the struct device * here so we don't have to
call find_pci_root_bus() again.
drivers/of/of_pci.c
void of_pci_dma_configure(struct pci_dev *pci_dev)
{
struct device *dev = pci_dev-dev;
struct device *bridge = pci_get_host_bridge_device(pci_dev);
of_dma_configure(dev, bridge-parent-of_node);
pci_put_host_bridge_device(pci_dev);
Then this would become pci_put_host_bridge_device(bridge)
}
Murali
Bjorn
--
Murali Karicheri
Linux Kernel, Texas Instruments
--
Murali Karicheri
Linux Kernel, Texas Instruments
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[PATCH 1/7 RESEND] ALSA: pcm: Add snd_interval_ranges() and snd_pcm_hw_constraint_ranges()
From: Peter Rosin p...@axentia.se
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
This is like snd_pcm_hw_constraint_list(), but for ranges instead of
points.
Signed-off-by: Peter Rosin p...@axentia.se
Reviewed-by: Lars-Peter Clausen l...@metafoo.de
---
include/sound/pcm.h | 12 +++
sound/core/pcm_lib.c | 85 ++
2 files changed, 97 insertions(+)
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 1e7f74acc2ec..04fc037e0555 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -275,6 +275,12 @@ struct snd_pcm_hw_constraint_list {
unsigned int mask;
};
+struct snd_pcm_hw_constraint_ranges {
+ unsigned int count;
+ const struct snd_interval *ranges;
+ unsigned int mask;
+};
+
struct snd_pcm_hwptr_log;
struct snd_pcm_runtime {
@@ -910,6 +916,8 @@ void snd_interval_mulkdiv(const struct snd_interval *a,
unsigned int k,
const struct snd_interval *b, struct snd_interval *c);
int snd_interval_list(struct snd_interval *i, unsigned int count,
const unsigned int *list, unsigned int mask);
+int snd_interval_ranges(struct snd_interval *i, unsigned int count,
+ const struct snd_interval *list, unsigned int mask);
int snd_interval_ratnum(struct snd_interval *i,
unsigned int rats_count, struct snd_ratnum *rats,
unsigned int *nump, unsigned int *denp);
@@ -934,6 +942,10 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime
*runtime,
unsigned int cond,
snd_pcm_hw_param_t var,
const struct snd_pcm_hw_constraint_list *l);
+int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime,
+unsigned int cond,
+snd_pcm_hw_param_t var,
+const struct snd_pcm_hw_constraint_ranges *r);
int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime,
unsigned int cond,
snd_pcm_hw_param_t var,
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index ec9e7866177f..446c00bd908b 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -1015,6 +1015,60 @@ int snd_interval_list(struct snd_interval *i, unsigned
int count,
EXPORT_SYMBOL(snd_interval_list);
+/**
+ * snd_interval_ranges - refine the interval value from the list of ranges
+ * @i: the interval value to refine
+ * @count: the number of elements in the list of ranges
+ * @ranges: the ranges list
+ * @mask: the bit-mask to evaluate
+ *
+ * Refines the interval value from the list of ranges.
+ * When mask is non-zero, only the elements corresponding to bit 1 are
+ * evaluated.
+ *
+ * Return: Positive if the value is changed, zero if it's not changed, or a
+ * negative error code.
+ */
+int snd_interval_ranges(struct snd_interval *i, unsigned int count,
+ const struct snd_interval *ranges, unsigned int mask)
+{
+ unsigned int k;
+ struct snd_interval range_union;
+ struct snd_interval range;
+
+ if (!count) {
+ snd_interval_none(i);
+ return -EINVAL;
+ }
+ snd_interval_any(range_union);
+ range_union.min = UINT_MAX;
+ range_union.max = 0;
+ for (k = 0; k count; k++) {
+ if (mask !(mask (1 k)))
+ continue;
+ snd_interval_copy(range, ranges[k]);
+ if (snd_interval_refine(range, i) 0)
+ continue;
+ if (snd_interval_empty(range))
+ continue;
+
+ if (range.min range_union.min) {
+ range_union.min = range.min;
+ range_union.openmin = 1;
+ }
+ if (range.min == range_union.min !range.openmin)
+ range_union.openmin = 0;
+ if (range.max range_union.max) {
+ range_union.max = range.max;
+ range_union.openmax = 1;
+ }
+ if (range.max == range_union.max !range.openmax)
+ range_union.openmax = 0;
+ }
+ return snd_interval_refine(i, range_union);
+}
+EXPORT_SYMBOL(snd_interval_ranges);
+
static int snd_interval_step(struct snd_interval *i, unsigned int step)
{
unsigned int n;
@@ -1221,6 +1275,37 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime
*runtime,
EXPORT_SYMBOL(snd_pcm_hw_constraint_list);
+static int snd_pcm_hw_rule_ranges(struct snd_pcm_hw_params *params,
+ struct snd_pcm_hw_rule *rule)
+{
+ struct
Re: [alsa-devel] [PATCH v4 2/3] ASoC: samsung: Document Trats2 audio subsystem bindings
On Fri, Jan 23, 2015 at 02:03:29PM +0900, Inha Song wrote: + - samsung,audio-routing : A list of the connections between audio + components. each entry is a pair of strings, the first being the + connection's sink, the second being the connection's source The list of valid components should be specified here - reference the CODEC bindings for anything on the CODEC but things on the board need to be enumerated. signature.asc Description: Digital signature
[PATCH 2/7 RESEND] ASoC: pcm512x: Fix spelling of register field names.
From: Peter Rosin p...@axentia.se Signed-off-by: Peter Rosin p...@axentia.se --- sound/soc/codecs/pcm512x.c |2 +- sound/soc/codecs/pcm512x.h |6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c index e5f2fb884bf3..874723c36d65 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -277,7 +277,7 @@ SOC_ENUM(Auto Mute Time Right, pcm512x_autom_r), SOC_SINGLE(Auto Mute Mono Switch, PCM512x_DIGITAL_MUTE_3, PCM512x_ACTL_SHIFT, 1, 0), SOC_DOUBLE(Auto Mute Switch, PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, - PCM512x_AMLR_SHIFT, 1, 0), + PCM512x_AMRE_SHIFT, 1, 0), SOC_ENUM(Volume Ramp Down Rate, pcm512x_vndf), SOC_ENUM(Volume Ramp Down Step, pcm512x_vnds), diff --git a/sound/soc/codecs/pcm512x.h b/sound/soc/codecs/pcm512x.h index 6ee76aaca09a..28b3dfd302bc 100644 --- a/sound/soc/codecs/pcm512x.h +++ b/sound/soc/codecs/pcm512x.h @@ -108,8 +108,8 @@ #define PCM512x_RQML_SHIFT 4 /* Page 0, Register 4 - PLL */ -#define PCM512x_PLCE (1 0) -#define PCM512x_RLCE_SHIFT 0 +#define PCM512x_PLLE (1 0) +#define PCM512x_PLLE_SHIFT 0 #define PCM512x_PLCK (1 4) #define PCM512x_PLCK_SHIFT 4 @@ -152,7 +152,7 @@ /* Page 0, Register 65 - Digital mute enables */ #define PCM512x_ACTL_SHIFT 2 #define PCM512x_AMLE_SHIFT 1 -#define PCM512x_AMLR_SHIFT 0 +#define PCM512x_AMRE_SHIFT 0 /* Page 1, Register 2 - analog volume control */ #define PCM512x_RAGN_SHIFT 0 -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/8] qcom audio clock control drivers
Quoting Ken Westfield (2015-01-22 13:41:22) On Mon, Jan 19, 2015 at 06:05:27PM -0800, Stephen Boyd wrote: This patchset adds support for the low power audio subsystem (LPASS) clock controller hardware. I split out the #define patch for IPQ so that it can go through the clock tree and the arm-soc tree in parallel if desired. Verified all supported bit clock frequencies for audio playback work on the ipq806x SOC with max98357a codec. Tested-by: Kenneth Westfield kwest...@codeaurora.org Applied to clk-next. Regards, Mike -- Kenneth Westfield Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/7 RESEND] ASoC: pcm512x: Support mastering BCLK/LRCLK without using the PLL
From: Peter Rosin p...@axentia.se
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 452 ++--
sound/soc/codecs/pcm512x.h | 57 +-
2 files changed, 492 insertions(+), 17 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 4c65eb9ab59b..ac9a0b25b863 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/codecs/pcm512x.c
@@ -23,6 +23,7 @@
#include linux/regulator/consumer.h
#include sound/soc.h
#include sound/soc-dapm.h
+#include sound/pcm_params.h
#include sound/tlv.h
#include pcm512x.h
@@ -39,6 +40,7 @@ struct pcm512x_priv {
struct clk *sclk;
struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
+ int fmt;
};
/*
@@ -69,6 +71,7 @@ static const struct reg_default pcm512x_reg_defaults[] = {
{ PCM512x_MUTE, 0x00 },
{ PCM512x_DSP, 0x00 },
{ PCM512x_PLL_REF, 0x00 },
+ { PCM512x_DAC_REF, 0x00 },
{ PCM512x_DAC_ROUTING, 0x11 },
{ PCM512x_DSP_PROGRAM, 0x01 },
{ PCM512x_CLKDET,0x00 },
@@ -87,6 +90,18 @@ static const struct reg_default pcm512x_reg_defaults[] = {
{ PCM512x_ANALOG_GAIN_BOOST, 0x00 },
{ PCM512x_VCOM_CTRL_1, 0x00 },
{ PCM512x_VCOM_CTRL_2, 0x01 },
+ { PCM512x_BCLK_LRCLK_CFG,0x00 },
+ { PCM512x_MASTER_MODE, 0x7c },
+ { PCM512x_SYNCHRONIZE, 0x10 },
+ { PCM512x_DSP_CLKDIV,0x00 },
+ { PCM512x_DAC_CLKDIV,0x00 },
+ { PCM512x_NCP_CLKDIV,0x00 },
+ { PCM512x_OSR_CLKDIV,0x00 },
+ { PCM512x_MASTER_CLKDIV_1, 0x00 },
+ { PCM512x_MASTER_CLKDIV_2, 0x00 },
+ { PCM512x_FS_SPEED_MODE, 0x00 },
+ { PCM512x_IDAC_1,0x01 },
+ { PCM512x_IDAC_2,0x00 },
};
static bool pcm512x_readable(struct device *dev, unsigned int reg)
@@ -103,6 +118,8 @@ static bool pcm512x_readable(struct device *dev, unsigned
int reg)
case PCM512x_DSP_GPIO_INPUT:
case PCM512x_MASTER_MODE:
case PCM512x_PLL_REF:
+ case PCM512x_DAC_REF:
+ case PCM512x_SYNCHRONIZE:
case PCM512x_PLL_COEFF_0:
case PCM512x_PLL_COEFF_1:
case PCM512x_PLL_COEFF_2:
@@ -303,6 +320,105 @@ static const struct snd_soc_dapm_route
pcm512x_dapm_routes[] = {
{ OUTR, NULL, DACR },
};
+static const u32 pcm512x_dai_rates[] = {
+ 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
+ 88200, 96000, 176400, 192000, 384000,
+};
+
+static const struct snd_pcm_hw_constraint_list constraints_slave = {
+ .count = ARRAY_SIZE(pcm512x_dai_rates),
+ .list = pcm512x_dai_rates,
+};
+
+static int pcm512x_params_to_frame_size(struct snd_pcm_hw_params *params)
+{
+ int sample_size;
+
+ sample_size = snd_pcm_format_physical_width(params_format(params));
+ if (sample_size 0)
+ return sample_size;
+
+ return snd_soc_calc_frame_size(sample_size, params_channels(params), 1);
+}
+
+static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai-codec;
+ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+ struct device *dev = dai-dev;
+ struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
+ struct snd_ratnum *rats_no_pll;
+
+ if (IS_ERR(pcm512x-sclk)) {
+ dev_err(dev, Need SCLK for master mode: %ld\n,
+ PTR_ERR(pcm512x-sclk));
+ return PTR_ERR(pcm512x-sclk);
+ }
+
+ constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
+ GFP_KERNEL);
+ if (!constraints_no_pll)
+ return -ENOMEM;
+ constraints_no_pll-nrats = 1;
+ rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
+ if (!rats_no_pll)
+ return -ENOMEM;
+ constraints_no_pll-rats = rats_no_pll;
+ rats_no_pll-num = clk_get_rate(pcm512x-sclk) / 64;
+ rats_no_pll-den_min = 1;
+ rats_no_pll-den_max = 128;
+ rats_no_pll-den_step = 1;
+
+ return snd_pcm_hw_constraint_ratnums(substream-runtime, 0,
+SNDRV_PCM_HW_PARAM_RATE,
+constraints_no_pll);
+}
+
+static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
+struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai-codec;
+ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+ struct device
Re: [PATCH v1 2/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
Here you don't provide an 'iommus' property, which means that the
device is unable to use the iommu.
Arnd
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Re: [PATCH] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
On Tue, Jan 27, 2015 at 06:00:35PM +0100, Maxime Ripard wrote: How about pcduino3-nano:green:usr-led3/4? Or ...:usr1/2, and a comment in the .dts explaining how they're labelled on the board? The latter looks better yes. tx and rx would do too, if you know what tx and what rx we're talking about here. I've changed it to usr1/2 with comments. (I don't know if they were intended to be TX/RX; the documentation doesn't suggest so.) They're multipurpose pins on Arduino-compatible headers: ... So should we [...] None of the above, if there's no hardware default, we won't enforce any default either. This is a case for the DT overlays. OK -- that simplifies it quite a bit, then. v3 of the patch incoming! Thanks very much, -- Adam Sampson a...@offog.org http://offog.org/ -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH v4 1/3] ASoC: samsung: Add machine driver for Trats2
On Fri, Jan 23, 2015 at 02:03:28PM +0900, Inha Song wrote: This patch add the sound machine driver for Trats2 board. The codec operate in master mode. This looks like (and mostly should be) a DTified copy of the littlemill driver. The major differences are the fact that this lacks jack detection, the management of the clock and the fact that instead of picking a fixed clock frequency this tries to adjust based on hw_params(). Ideally we'd be able to merge these drivers so we're keeping up with best practice. The reason we pick a fixed frequency for littlemill is that the device supports analogue bypass paths which would be broken otherwise which will apply here also I imagine. +config SND_SOC_SAMSUNG_TRATS2_WM1811 + tristate SoC I2S Audio support for WM1811 on Tizen Trats2 board + depends on SND_SOC_SAMSUNG + select SND_SAMSUNG_I2S + select MFD_WM8994 For things outside the audio subsystem it's more common to use a depends instead of a select - the selects are there because the drivers only work with a machine driver and if we go outside the subsystem then since selects aren't recursive we end up breaking elsewhere. For example here we'll end up not selecting MFD_CORE. signature.asc Description: Digital signature
Re: [PATCH 3/7] spi: spi-fsl-dspi: Remove usage of devm_kzalloc
On Tue, Jan 27, 2015 at 04:27:20PM +0530, Bhuvanchandra DV wrote: devm_* API was supposed to be used only in probe function call. Memory is allocated at 'probe' and free automatically at 'remove'. Applied, thanks. Please don't dump entire backtraces into your commit logs - they're far too big and not very helpful, they can obscure real content in the message. Explain in words what the problem is and if a backtrace helps illustrate that edit it down to only relevant portions rather than blindly including the entire thing. signature.asc Description: Digital signature
[PATCH 3/7 RESEND] ASoC: pcm512x: Change register default to match actual content after reset
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..4c65eb9ab59b 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/codecs/pcm512x.c
@@ -78,7 +78,7 @@ static const struct reg_default pcm512x_reg_defaults[] = {
{ PCM512x_DIGITAL_VOLUME_2, 0x30 },
{ PCM512x_DIGITAL_VOLUME_3, 0x30 },
{ PCM512x_DIGITAL_MUTE_1,0x22 },
- { PCM512x_DIGITAL_MUTE_2,0x00 },
+ { PCM512x_DIGITAL_MUTE_2,0x02 },
{ PCM512x_DIGITAL_MUTE_3,0x07 },
{ PCM512x_OUTPUT_AMPLITUDE, 0x00 },
{ PCM512x_ANALOG_GAIN_CTRL, 0x00 },
--
1.7.10.4
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Re: [PATCH 1/2] dt: watchdog: Add DT binding documentation for jz47xx watchdog timer
On Tuesday 27 January 2015 15:11:29 Zubair Lutfullah Kakakhel wrote:
+clocks: phandle to rtcclk
+clock-names: must be rtc
+
+Example:
+
+watchdog: jz47xx-watchdog@0x10002000 {
+ compatible = ingenic,jz4780-watchdog;
+ reg = 0x10002000 0x100;
+
+ clocks = rtclk;
+ clock-names = rtc;
+};
Why is the name rtc? are you sure you are not confusing the output
name of the clock controller with the input of the watchdog device?
It's suspicious that both have similar names.
Arnd
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[PATCH v8 0/2] Add Spreadtrum SoC bindings and serial driver support
This patch-set split the last version, and addressed the review comments from
last version on serial driver code.
Changes from v7:
* Addressed review comments from Peter:
- Initialized the stack local with zero in sprd_set_termios()
- Used dev_get_drvdata() to get sprd_uart_port
Changes from v6:
- Setted SPRD_TIMEOUT with 256 rather than 2048
- Used u32 instead of uint32_t
- Removed inline of handle_lsr_errors which is a single call site
function
- Removed unused parameter of sprd_tx sprd_rx
- Used spin_lock_irqsave in sprd_startup() instead of spin_lock
- Added a check for port-sysrq in sprd_console_write()
- Used a global counter as a condition of calling
uart_{un}register_driver
- Added pdev-id assignment in probe()
- Setted port-flags with UPF_BOOT_AUTOCONF instead of
ASYNC_BOOT_AUTOCONF
Changes from v5:
- Used Spreadtrum instead of SPRD in menus
- Changed TTY name to 'ttyS'
- Moved uart_register_driver() to probe()
- Added spinlock as needed
- Removed register states saving and restoring in suspend() and resume()
Chunyan Zhang (2):
Documentation: DT: Add bindings for Spreadtrum SoC Platform
tty/serial: Add Spreadtrum sc9836-uart driver support
Documentation/devicetree/bindings/arm/sprd.txt | 11 +
.../devicetree/bindings/serial/sprd-uart.txt |7 +
.../devicetree/bindings/vendor-prefixes.txt|1 +
drivers/tty/serial/Kconfig | 18 +
drivers/tty/serial/Makefile|1 +
drivers/tty/serial/sprd_serial.c | 797
include/uapi/linux/serial_core.h |3 +
7 files changed, 838 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/sprd.txt
create mode 100644 Documentation/devicetree/bindings/serial/sprd-uart.txt
create mode 100644 drivers/tty/serial/sprd_serial.c
--
1.7.9.5
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[PATCH v8 2/2] tty/serial: Add Spreadtrum sc9836-uart driver support
Add a full sc9836-uart driver for SC9836 SoC which is based on the spreadtrum sharkl64 platform. This driver also support earlycon. Originally-by: Lanqing Liu lanqing@spreadtrum.com Signed-off-by: Orson Zhai orson.z...@spreadtrum.com Signed-off-by: Chunyan Zhang chunyan.zh...@spreadtrum.com Acked-by: Arnd Bergmann a...@arndb.de --- drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile |1 + drivers/tty/serial/sprd_serial.c | 797 ++ include/uapi/linux/serial_core.h |3 + 4 files changed, 819 insertions(+) create mode 100644 drivers/tty/serial/sprd_serial.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index c79b43c..13211f7 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1577,6 +1577,24 @@ config SERIAL_MEN_Z135 This driver can also be build as a module. If so, the module will be called men_z135_uart.ko +config SERIAL_SPRD + tristate Support for Spreadtrum serial + depends on ARCH_SPRD + select SERIAL_CORE + help + This enables the driver for the Spreadtrum's serial. + +config SERIAL_SPRD_CONSOLE + bool Spreadtrum UART console support + depends on SERIAL_SPRD=y + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Support for early debug console using Spreadtrum's serial. This enables + the console before standard serial driver is probed. This is enabled + with earlycon on the kernel command line. The console is + enabled when early_param is processed. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 9a548ac..4801aca 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_SERIAL_ARC) += arc_uart.o obj-$(CONFIG_SERIAL_RP2) += rp2.o obj-$(CONFIG_SERIAL_FSL_LPUART)+= fsl_lpuart.o obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o +obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o diff --git a/drivers/tty/serial/sprd_serial.c b/drivers/tty/serial/sprd_serial.c new file mode 100644 index 000..bbd0447 --- /dev/null +++ b/drivers/tty/serial/sprd_serial.c @@ -0,0 +1,797 @@ +/* + * Copyright (C) 2012-2015 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/clk.h +#include linux/console.h +#include linux/delay.h +#include linux/io.h +#include linux/ioport.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/platform_device.h +#include linux/serial_core.h +#include linux/serial.h +#include linux/slab.h +#include linux/tty.h +#include linux/tty_flip.h + +/* device name */ +#define UART_NR_MAX8 +#define SPRD_TTY_NAME ttyS +#define SPRD_FIFO_SIZE 128 +#define SPRD_DEF_RATE 2600 +#define SPRD_BAUD_IO_LIMIT 300 +#define SPRD_TIMEOUT 256 + +/* the offset of serial registers and BITs for them */ +/* data registers */ +#define SPRD_TXD 0x +#define SPRD_RXD 0x0004 + +/* line status register and its BITs */ +#define SPRD_LSR 0x0008 +#define SPRD_LSR_OEBIT(4) +#define SPRD_LSR_FEBIT(3) +#define SPRD_LSR_PEBIT(2) +#define SPRD_LSR_BIBIT(7) +#define SPRD_LSR_TX_OVER BIT(15) + +/* data number in TX and RX fifo */ +#define SPRD_STS1 0x000C + +/* interrupt enable register and its BITs */ +#define SPRD_IEN 0x0010 +#define SPRD_IEN_RX_FULL BIT(0) +#define SPRD_IEN_TX_EMPTY BIT(1) +#define SPRD_IEN_BREAK_DETECT BIT(7) +#define SPRD_IEN_TIMEOUT BIT(13) + +/* interrupt clear register */ +#define SPRD_ICLR 0x0014 + +/* line control register */ +#define SPRD_LCR 0x0018 +#define SPRD_LCR_STOP_1BIT 0x10 +#define SPRD_LCR_STOP_2BIT 0x30 +#define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3)) +#define SPRD_LCR_DATA_LEN5 0x0 +#define SPRD_LCR_DATA_LEN6 0x4 +#define SPRD_LCR_DATA_LEN7 0x8 +#define SPRD_LCR_DATA_LEN8 0xc +#define SPRD_LCR_PARITY(BIT(0) | BIT(1)) +#define SPRD_LCR_PARITY_EN 0x2 +#define SPRD_LCR_EVEN_PAR 0x0 +#define SPRD_LCR_ODD_PAR 0x1 + +/* control register 1 */ +#define SPRD_CTL1 0x001C +#define RX_HW_FLOW_CTL_THLDBIT(6) +#define RX_HW_FLOW_CTL_EN
[PATCH 1/2] mmc: dw_mmc-exynos: add support for controlling emmc reset pin
There are boards (like Hardkernel's Odroid boards) on which eMMC card's
reset line is connected to SoC GPIO line instead of the hardware reset
logic. In case of such boards, before performing system reboot,
additional reset of eMMC card is required to boot again properly.
This patch adds code for handling such cases.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 6 +++
drivers/mmc/host/dw_mmc-exynos.c | 43 +-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index ee4fc0576c7d..fc53d335e7db 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -50,6 +50,12 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
phase shift clocks should be 0.
+Optional properties:
+
+* dw-mshc-reset-gpios: optional property specifying gpio for the eMMC nreset
+ line, it will be triggered on system reboot to properly reset eMMC card for
+ next system boot.
+
Required properties for a slot (Deprecated - Recommend to use one slot per
host):
* gpios: specifies a list of gpios used for command, clock and data bus. The
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 509365cb22c6..2add5a93859d 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -12,12 +12,14 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/clk.h
+#include linux/delay.h
#include linux/mmc/host.h
#include linux/mmc/dw_mmc.h
#include linux/mmc/mmc.h
#include linux/of.h
#include linux/of_gpio.h
#include linux/slab.h
+#include linux/reboot.h
#include dw_mmc.h
#include dw_mmc-pltfm.h
@@ -77,8 +79,23 @@ struct dw_mci_exynos_priv_data {
u32 sdr_timing;
u32 ddr_timing;
u32 cur_speed;
+ struct gpio_desc*reset_gpio;
+ struct notifier_block reset_nb;
};
+static int dw_mci_restart_handler(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ struct dw_mci_exynos_priv_data *data;
+ data = container_of(this, struct dw_mci_exynos_priv_data, reset_nb);
+
+ gpiod_direction_output(data-reset_gpio, 0);
+ mdelay(150);
+ gpiod_direction_output(data-reset_gpio, 1);
+
+ return NOTIFY_DONE;
+}
+
static struct dw_mci_exynos_compatible {
char*compatible;
enum dw_mci_exynos_type ctrl_type;
@@ -295,7 +312,20 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+
+ priv-reset_gpio = devm_gpiod_get_optional(host-dev,
+ samsung,dw-mshc-reset,
+ GPIOD_OUT_HIGH);
+ if (!IS_ERR_OR_NULL(priv-reset_gpio)) {
+ priv-reset_nb.notifier_call = dw_mci_restart_handler;
+ priv-reset_nb.priority = 255;
+ ret = register_restart_handler(priv-reset_nb);
+ if (ret)
+ dev_err(host-dev, cannot register restart handler\n);
+ }
+
host-priv = priv;
+
return 0;
}
@@ -490,6 +520,17 @@ static int dw_mci_exynos_probe(struct platform_device
*pdev)
return dw_mci_pltfm_register(pdev, drv_data);
}
+static int dw_mci_exynos_remove(struct platform_device *pdev)
+{
+ struct dw_mci *host = platform_get_drvdata(pdev);
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+
+ if (priv-reset_gpio)
+ unregister_restart_handler(priv-reset_nb);
+
+ return dw_mci_pltfm_remove(pdev);
+}
+
static const struct dev_pm_ops dw_mci_exynos_pmops = {
SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
.resume_noirq = dw_mci_exynos_resume_noirq,
@@ -499,7 +540,7 @@ static const struct dev_pm_ops dw_mci_exynos_pmops = {
static struct platform_driver dw_mci_exynos_pltfm_driver = {
.probe = dw_mci_exynos_probe,
- .remove = __exit_p(dw_mci_pltfm_remove),
+ .remove = dw_mci_exynos_remove,
.driver = {
.name = dwmmc_exynos,
.of_match_table = dw_mci_exynos_match,
--
1.9.2
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[PATCH 0/2] Fix reboot issue on Odroid boards with eMMC card
Hello, This patchset fixes reboot hang issue on Hardkernel's Odroid boards with eMMC card. Those boards are designed in such a way, that the eMMC nreset signal is routed to SoC GPIO line instead of the board reset logic. To properly restard system, one need to set this line to zero before performing reboot. The initial patches consisted of a complete reset/power off driver, but after further analysis, it turned out that only eMMC nreset line control logic is specific for those boards. Everything else can be done by generic Exynos code, so the code has been moved to Exynos DW MMC driver. Best regards Marek Szyprowski Samsung RD Institute Poland Changelog: initial version: http://thread.gmane.org/gmane.linux.power-management.general/51855/ Path summary: Marek Szyprowski (2): mmc: dw_mmc-exynos: add support for controlling emmc reset pin ARM: dts: exynos*-odroid*: add eMMC reset line .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 6 +++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 1 + arch/arm/boot/dts/exynos5422-odroidxu3.dts | 1 + drivers/mmc/host/dw_mmc-exynos.c | 43 +- 4 files changed, 50 insertions(+), 1 deletion(-) -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: dts: exynos*-odroid*: add eMMC reset line
This patch add samsung,dw-mshc-reset-gpios property to the eMMC slot, so Exynos DW MMC driver is able to properly reset eMMC card on system restart and thus fixes hang on software reboot. Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 + arch/arm/boot/dts/exynos5422-odroidxu3.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 74e89cbfb00c..97df0ef81d1a 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -69,6 +69,7 @@ samsung,dw-mshc-ciu-div = 3; samsung,dw-mshc-sdr-timing = 2 3; samsung,dw-mshc-ddr-timing = 1 2; + samsung,dw-mshc-reset-gpios = gpk1 2 1; bus-width = 8; cap-mmc-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index d829e220eedb..20064e36a5be 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -336,6 +336,7 @@ samsung,dw-mshc-ciu-div = 3; samsung,dw-mshc-sdr-timing = 0 4; samsung,dw-mshc-ddr-timing = 0 2; + samsung,dw-mshc-reset-gpios = gpd1 0 0; pinctrl-names = default; pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8; bus-width = 8; -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] Documentation: leds: Add description of LED Flash class extension
The documentation being added contains overall description of the LED Flash Class and the related sysfs attributes. Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com Cc: Bryan Wu coolo...@gmail.com Cc: Richard Purdie rpur...@rpsys.net --- Documentation/leds/leds-class-flash.txt | 59 +++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/leds/leds-class-flash.txt diff --git a/Documentation/leds/leds-class-flash.txt b/Documentation/leds/leds-class-flash.txt new file mode 100644 index 000..297401a --- /dev/null +++ b/Documentation/leds/leds-class-flash.txt @@ -0,0 +1,59 @@ + +Flash LED handling under Linux +== + +Some LED devices support two modes - torch and flash. In the LED subsystem +those modes are supported by LED class (see Documentation/leds/leds-class.txt) +and LED Flash class respectively. The torch mode related features are enabled +by default and the flash ones only if a driver declares it by setting +LED_DEV_CAP_FLASH flag. + +In order to enable support for flash LEDs CONFIG_LEDS_CLASS_FLASH symbol +must be defined in the kernel config. A flash LED driver must register +in the LED subsystem with led_classdev_flash_register function to gain flash +related capabilities. + +There are flash LED devices which can control more than one LED and allow for +strobing the sub-LEDs synchronously. A LED will be strobed synchronously with +the one whose identifier is written to the flash_sync_strobe sysfs attribute. +The list of available sub-LED identifiers can be read from the available_sync_leds +sysfs attribute. In order to enable the related settings the driver must set +LED_DEV_CAP_SYNC_STROBE flag. + +Following sysfs attributes are exposed for controlling flash LED devices: + + - flash_brightness - flash LED brightness in microamperes (RW) + - max_flash_brightness - maximum available flash LED brightness (RO) + - flash_timeout - flash strobe duration in microseconds (RW) + - max_flash_timeout - maximum available flash strobe duration (RO) + - flash_strobe - flash strobe state (RW) + - available_sync_leds - list of sub-LEDs available for flash strobe + synchronization (RO) + - flash_sync_strobe - identifier of the sub-LED to synchronize the flash + strobe with; 0 stands for no synchronization (RW) + - flash_fault - list of flash faults that may have occurred: + * led-over-voltage - flash controller voltage to the flash LED + has exceededthe limit specific to the flash controller + * flash-timeout-exceeded - the flash strobe was still on when + the timeout set by the user has expired; not all flash + controllers may set this in all such conditions + * controller-over-temperature - the flash controller has + overheated + * controller-short-circuit - the short circuit protection + of the flash controller has been triggered + * led-power-supply-over-current - current in the LED power + supply has exceeded the limit specific to the flash + controller + * indicator-led-fault - the flash controller has detected + a short or open circuit condition on the indicator LED + * led-under-voltage - flash controller voltage to the flash + LED has been below the minimum limit specific to + the flash + * controller-under-voltage - the input voltage of the flash + controller is below the limit under which strobing the + flash at full current will not be possible. The condition + persists until this flag is no longer set + * led-over-temperature - the temperature of the LED has exceeded + its allowed upper limit + + Flash faults are cleared, if possible, by reading the attribute. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] power: reset: add driver for Hardkernel's Odroid boards
Hello, On 2015-01-25 15:32, Sebastian Reichel wrote: On Fri, Jan 23, 2015 at 12:11:22PM +0100, Marek Szyprowski wrote: Frankly, I analyzed this case once again and I came to conclusion that there is no need to make a separate reset driver for Odroid boards. There is nothing special, specific to whole board about this gpio. It is rather a property of MMC host controller and eMMC card that is connected to it. When only gpio toggling code is moved to reset handler registered from mmc controller, the board properly performs reboot with a generic exynos4 code. OK, so I guess this will be fixed independently via mmc subsystem. I've posted an updated patch. The poweroff code in above driver is just a generic Exynos4 code, so again there is no need to duplicate it. OK. It seems there is a driver for that in arch/arm/mach-exynos. Otherwise I would have suggest to create something like syscon-reboot for shutdown. By moving the code to mmc driver, the same approach can be used for other Odroid boards (XU/XU3) and maybe even other boards which need manual resetting of eMMC cards to properly perform reboot procedure. I suggest to start a new thread for discussing this, which includes linux-mmc. It might be interesting to provide some more details about eMMC_nDET, since MMC already contain a reset signal (which seems to be used according to the odroid schematics I found). My fault. The documentation for this initial driver was incorrect. The reboot fix has noting to eMMC_nDET signal. It should be eMMC nreset, which is routed directly to SoC GPIO line with external pull-up resistor. I really have no idea why I wrote eMMC_nDET instead of nreset. Best regards -- Marek Szyprowski, PhD Samsung RD Institute Poland -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/2] arm64: Add support for Spreadtrum's Sharkl64 Platform in Kconfig and defconfig
From: Zhizhou Zhang zhizhou.zh...@spreadtrum.com Adds support for Spreadtrum's SoC Platform in the arm64 Kconfig and defconfig files. Signed-off-by: Zhizhou Zhang zhizhou.zh...@spreadtrum.com Signed-off-by: Orson Zhai orson.z...@spreadtrum.com Signed-off-by: Chunyan Zhang chunyan.zh...@spreadtrum.com --- arch/arm64/Kconfig |5 + arch/arm64/configs/defconfig |1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b1f9a20..885c1f4 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -153,6 +153,11 @@ config ARCH_SEATTLE help This enables support for AMD Seattle SOC Family +config ARCH_SPRD + bool Spreadtrum SoC platform + help + Support for Spreadtrum ARM based SoCs + config ARCH_THUNDER bool Cavium Inc. Thunder SoC Family help diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dd301be..2eb303a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_SPRD=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3 0/2] dmaengine: Support for IMG MDC
Hi Vinod, On Thu, Dec 11, 2014 at 10:59 PM, Andrew Bresticker abres...@chromium.org wrote: This series adds support for the IMG Multi-threaded DMA Controller (MDC) which is found on IMG SoCs. Currently this driver only supports the variant found on the MIPS-based Pistachio SoC. The MDC supports slave and memory-to-memory transfers on up to 32 channels. Requests from channels are handled by MDC threads. Thread assignments are per-channel and are specified in the device-tree. Tested on a platform based on the Pistachio SoC with additional patches. Support for Pistachio will be submitted later. Slave DMA was tested with the recently submitted IMG SPFI driver [1] and memory-to-memory DMA was tested with the dmatest module. Based on Vinod's slave-dma/topic/slave_caps_device_control_fix. Any more comments on this series? I'd like to get this in for 3.20 if possible. Thanks! Andrew -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Fix reboot issue on Odroid boards with eMMC card
On Tue, 2015-01-27 at 09:11 +0100, Marek Szyprowski wrote: Hello, This patchset fixes reboot hang issue on Hardkernel's Odroid boards with eMMC card. Those boards are designed in such a way, that the eMMC nreset signal is routed to SoC GPIO line instead of the board reset logic. To properly restard system, one need to set this line to zero before performing reboot. The initial patches consisted of a complete reset/power off driver, but after further analysis, it turned out that only eMMC nreset line control logic is specific for those boards. Everything else can be done by generic Exynos code, so the code has been moved to Exynos DW MMC driver. This seems a general board design quirk, rather then an exynos specific one. Potentially better to have this in the mmc core so it can be re-used by non-exynos boards? A very quick peek at the schematic for the hardkernel C1 (amlogic based), shows that for that board the eMMC reset line is hooked up to an SoC gpio line as well. (Although ofcourse, it may not need to be reset before a warm restart depending on what the amlogic rom code does). Random side-note, at least the samsung peach chromebooks are also hooked up this way. But don't run into this issue as they load their initial stages from flash rather then the eMMC. Best regards Marek Szyprowski Samsung RD Institute Poland Changelog: initial version: http://thread.gmane.org/gmane.linux.power-management.general/51855/ Path summary: Marek Szyprowski (2): mmc: dw_mmc-exynos: add support for controlling emmc reset pin ARM: dts: exynos*-odroid*: add eMMC reset line .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 6 +++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 1 + arch/arm/boot/dts/exynos5422-odroidxu3.dts | 1 + drivers/mmc/host/dw_mmc-exynos.c | 43 +- 4 files changed, 50 insertions(+), 1 deletion(-) smime.p7s Description: S/MIME cryptographic signature
Re: [PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene
On 01/27/2015 02:03 AM, Pranavkumar Sawargaonkar wrote: In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page size due to size alignment checking in vgic driver for VCPU Control and VCPU register. This patch corrects the sizes to be inline with the hardware spec. CC: linux-arm-ker...@lists.infradead.org CC: kvm...@lists.cs.columbia.edu CC: a...@arndb.de CC: marc.zyng...@arm.com CC: christoffer.d...@linaro.org CC: j...@redhat.com Signed-off-by: Pranavkumar Sawargaonkar psawargaon...@apm.com Signed-off-by: Tushar Jagad tja...@apm.com Signed-off-by: Feng Kan f...@apm.com --- arch/arm64/boot/dts/apm/apm-storm.dtsi |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index f1ad9c2..65f0e6d 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,10 +81,10 @@ compatible = arm,cortex-a15-gic; #interrupt-cells = 3; interrupt-controller; - reg = 0x0 0x7801 0x0 0x1000, /* GIC Dist */ - 0x0 0x7802 0x0 0x1000, /* GIC CPU */ - 0x0 0x7804 0x0 0x2000, /* GIC VCPU Control */ - 0x0 0x7806 0x0 0x2000; /* GIC VCPU */ + reg = 0x0 0x7801 0x0 0x1, /* GIC Dist */ + 0x0 0x7802 0x0 0x2, /* GIC CPU */ + 0x0 0x7804 0x0 0x1, /* GIC VCPU Control */ + 0x0 0x7806 0x0 0x2; /* GIC VCPU */ interrupts = 1 9 0xf04; /* GIC Maintenence IRQ */ }; Thanks. I confirm that we have tested this. Jon. -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] net: Linn Ethernet Packet Sniffer driver
On 26/01/15 19:39, Joe Perches wrote: This header file is the public API for the driver. Should it not live under the 'include' directory? Several other drivers seem to follow that convention. It depends on how public is public. If it's _really_ public, it should be in uapi. If it's kinda public, then _maybe_ it should be in include/linux, but how likely is it another driver will use it? It is intended for user space code that needs to use the driver as it defines the netlink messages and attributes that the driver understands. So I guess uapi/linux would be the place for it. Thanks, Stathis -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] mmc: dw_mmc-exynos: add support for controlling emmc reset pin
Hi, Marek.
your patch should be conflicted with
https://patchwork.kernel.org/patch/5698421/;
On 01/27/2015 05:11 PM, Marek Szyprowski wrote:
There are boards (like Hardkernel's Odroid boards) on which eMMC card's
reset line is connected to SoC GPIO line instead of the hardware reset
logic. In case of such boards, before performing system reboot,
additional reset of eMMC card is required to boot again properly.
This patch adds code for handling such cases.
mmc core supported to hw_reset function.
So i think we can use it. It's called at only initial time to clear the
previous status.
But i think it can be called at reboot time. (it needs to implement codes.)
how about?
Best Regards,
Jaehoon Chung
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 6 +++
drivers/mmc/host/dw_mmc-exynos.c | 43
+-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index ee4fc0576c7d..fc53d335e7db 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -50,6 +50,12 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
phase shift clocks should be 0.
+Optional properties:
+
+* dw-mshc-reset-gpios: optional property specifying gpio for the eMMC nreset
+ line, it will be triggered on system reboot to properly reset eMMC card for
+ next system boot.
+
Required properties for a slot (Deprecated - Recommend to use one slot per
host):
* gpios: specifies a list of gpios used for command, clock and data bus. The
diff --git a/drivers/mmc/host/dw_mmc-exynos.c
b/drivers/mmc/host/dw_mmc-exynos.c
index 509365cb22c6..2add5a93859d 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -12,12 +12,14 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/clk.h
+#include linux/delay.h
#include linux/mmc/host.h
#include linux/mmc/dw_mmc.h
#include linux/mmc/mmc.h
#include linux/of.h
#include linux/of_gpio.h
#include linux/slab.h
+#include linux/reboot.h
#include dw_mmc.h
#include dw_mmc-pltfm.h
@@ -77,8 +79,23 @@ struct dw_mci_exynos_priv_data {
u32 sdr_timing;
u32 ddr_timing;
u32 cur_speed;
+ struct gpio_desc*reset_gpio;
+ struct notifier_block reset_nb;
};
+static int dw_mci_restart_handler(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ struct dw_mci_exynos_priv_data *data;
+ data = container_of(this, struct dw_mci_exynos_priv_data, reset_nb);
+
+ gpiod_direction_output(data-reset_gpio, 0);
+ mdelay(150);
+ gpiod_direction_output(data-reset_gpio, 1);
+
+ return NOTIFY_DONE;
+}
+
static struct dw_mci_exynos_compatible {
char*compatible;
enum dw_mci_exynos_type ctrl_type;
@@ -295,7 +312,20 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+
+ priv-reset_gpio = devm_gpiod_get_optional(host-dev,
+samsung,dw-mshc-reset,
+GPIOD_OUT_HIGH);
+ if (!IS_ERR_OR_NULL(priv-reset_gpio)) {
+ priv-reset_nb.notifier_call = dw_mci_restart_handler;
+ priv-reset_nb.priority = 255;
+ ret = register_restart_handler(priv-reset_nb);
+ if (ret)
+ dev_err(host-dev, cannot register restart handler\n);
+ }
+
host-priv = priv;
+
return 0;
}
@@ -490,6 +520,17 @@ static int dw_mci_exynos_probe(struct platform_device
*pdev)
return dw_mci_pltfm_register(pdev, drv_data);
}
+static int dw_mci_exynos_remove(struct platform_device *pdev)
+{
+ struct dw_mci *host = platform_get_drvdata(pdev);
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+
+ if (priv-reset_gpio)
+ unregister_restart_handler(priv-reset_nb);
+
+ return dw_mci_pltfm_remove(pdev);
+}
+
static const struct dev_pm_ops dw_mci_exynos_pmops = {
SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
.resume_noirq = dw_mci_exynos_resume_noirq,
@@ -499,7 +540,7 @@ static const struct dev_pm_ops dw_mci_exynos_pmops = {
static struct platform_driver dw_mci_exynos_pltfm_driver = {
.probe = dw_mci_exynos_probe,
- .remove = __exit_p(dw_mci_pltfm_remove),
+ .remove = dw_mci_exynos_remove,
.driver
Re: [PATCH v5 2/4] ARM:sunxi:drivers:input Add support for A10/A20 PS2
Hi Vishnu,
On Sun, Jan 25, 2015 at 07:10:07PM +0530, Vishnu Patekar wrote:
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
drivers/input/serio/Kconfig | 11 ++
drivers/input/serio/Makefile|1 +
drivers/input/serio/sun4i-ps2.c | 347
+++
3 files changed, 359 insertions(+)
create mode 100644 drivers/input/serio/sun4i-ps2.c
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index bc2d474..964afc5 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -281,4 +281,15 @@ config HYPERV_KEYBOARD
To compile this driver as a module, choose M here: the module will
be called hyperv_keyboard.
+config SERIO_SUN4I_PS2
+ tristate Allwinner A10 PS/2 controller support
+ default n
+ depends on ARCH_SUNXI || COMPILE_TEST
+ help
+ This selects support for the PS/2 Host Controller on
+ Allwinner A10.
+
+ To compile this driver as a module, choose M here: the
+ module will be called sun4i-ps2.
+
endif
diff --git a/drivers/input/serio/Makefile b/drivers/input/serio/Makefile
index 815d874..c600089 100644
--- a/drivers/input/serio/Makefile
+++ b/drivers/input/serio/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_SERIO_ARC_PS2) += arc_ps2.o
obj-$(CONFIG_SERIO_APBPS2) += apbps2.o
obj-$(CONFIG_SERIO_OLPC_APSP)+= olpc_apsp.o
obj-$(CONFIG_HYPERV_KEYBOARD)+= hyperv-keyboard.o
+obj-$(CONFIG_SERIO_SUN4I_PS2)+= sun4i-ps2.o
diff --git a/drivers/input/serio/sun4i-ps2.c b/drivers/input/serio/sun4i-ps2.c
new file mode 100644
index 000..d3cf6bc
--- /dev/null
+++ b/drivers/input/serio/sun4i-ps2.c
@@ -0,0 +1,347 @@
+/*
+ * Driver for Allwinner A10 PS2 host controller
+ *
+ * Author: Vishnu Patekar vishnupatekar0...@gmail.com
+ * Aaron.maoye leafy.m...@newbietech.com
+ *
+ *
+ */
+
+#include linux/module.h
+#include linux/serio.h
+#include linux/interrupt.h
+#include linux/errno.h
+#include linux/slab.h
+#include linux/list.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/of_irq.h
+#include linux/of_platform.h
You do not really need all these of_* includes. Neither you need list.h.
+#include linux/clk.h
+#include linux/delay.h
+
+#define DRIVER_NAME sun4i-ps2
+
+/* register offset definitions */
+#define PS2_REG_GCTL 0x00/* PS2 Module Global Control Reg */
+#define PS2_REG_DATA 0x04/* PS2 Module Data Reg */
+#define PS2_REG_LCTL 0x08/* PS2 Module Line Control Reg */
+#define PS2_REG_LSTS 0x0C/* PS2 Module Line Status Reg */
+#define PS2_REG_FCTL 0x10/* PS2 Module FIFO Control Reg */
+#define PS2_REG_FSTS 0x14/* PS2 Module FIFO Status Reg */
+#define PS2_REG_CLKDR0x18/* PS2 Module Clock Divider
Reg*/
+
+/* PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
+#define PS2_GCTL_INTFLAG BIT(4)
+#define PS2_GCTL_INTEN BIT(3)
+#define PS2_GCTL_RESET BIT(2)
+#define PS2_GCTL_MASTER BIT(1)
+#define PS2_GCTL_BUSEN BIT(0)
+
+/* PS2 LINE CONTROL REGISTER */
+#define PS2_LCTL_NOACK BIT(18)
+#define PS2_LCTL_TXDTOEN BIT(8)
+#define PS2_LCTL_STOPERREN BIT(3)
+#define PS2_LCTL_ACKERRENBIT(2)
+#define PS2_LCTL_PARERRENBIT(1)
+#define PS2_LCTL_RXDTOEN BIT(0)
+
+/* PS2 LINE STATUS REGISTER */
+#define PS2_LSTS_TXTDO BIT(8)
+#define PS2_LSTS_STOPERR BIT(3)
+#define PS2_LSTS_ACKERR BIT(2)
+#define PS2_LSTS_PARERR BIT(1)
+#define PS2_LSTS_RXTDO BIT(0)
+
+#define PS2_LINE_ERROR_BIT \
+ (PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
+ PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
+
+/* PS2 FIFO CONTROL REGISTER */
+#define PS2_FCTL_TXRST BIT(17)
+#define PS2_FCTL_RXRST BIT(16)
+#define PS2_FCTL_TXUFIEN BIT(10)
+#define PS2_FCTL_TXOFIEN BIT(9)
+#define PS2_FCTL_TXRDYIENBIT(8)
+#define PS2_FCTL_RXUFIEN BIT(2)
+#define PS2_FCTL_RXOFIEN BIT(1)
+#define PS2_FCTL_RXRDYIENBIT(0)
+
+/* PS2 FIFO STATUS REGISTER */
+#define PS2_FSTS_TXUFBIT(10)
+#define PS2_FSTS_TXOFBIT(9)
+#define PS2_FSTS_TXRDY BIT(8)
+#define PS2_FSTS_RXUFBIT(2)
+#define PS2_FSTS_RXOFBIT(1)
+#define PS2_FSTS_RXRDY BIT(0)
+
+#define PS2_FIFO_ERROR_BIT \
+ (PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
+
+#define PS2_SAMPLE_CLK 100
+#define PS2_SCLK 125000
+
+struct sun4i_ps2data {
+ struct serio *serio;
+ struct device *dev;
+
+ /* IO mapping base */
+ void __iomem*reg_base;
+
+ /* clock management */
+ struct clk *clk;
+
+ /* irq */
[PATCH v5 2/8] of: move of_dma_configure() to device.c to help re-use
Move of_dma_configure() to device.c so that same function can be re-used
for PCI devices to obtain DMA configuration from DT. Also add a second
argument so that for PCI, DT node of root bus host bridge can be used to
obtain the DMA configuration for the slave PCI device.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Bjorn Helgaas bhelg...@google.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/of/device.c | 59 +
drivers/of/platform.c | 58 ++--
include/linux/of_device.h |2 ++
3 files changed, 63 insertions(+), 56 deletions(-)
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 46d6c75c..2de320d 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -2,6 +2,9 @@
#include linux/kernel.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_address.h
+#include linux/of_iommu.h
+#include linux/dma-mapping.h
#include linux/init.h
#include linux/module.h
#include linux/mod_devicetable.h
@@ -66,6 +69,62 @@ int of_device_add(struct platform_device *ofdev)
return device_add(ofdev-dev);
}
+/**
+ * of_dma_configure - Setup DMA configuration
+ * @dev: Device to apply DMA configuration
+ * @np:ptr to of node having dma configuration
+ *
+ * Try to get devices's DMA configuration from DT and update it
+ * accordingly.
+ *
+ * In case if platform code need to use own special DMA configuration,it
+ * can use Platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE event
+ * to fix up DMA configuration.
+ */
+void of_dma_configure(struct device *dev, struct device_node *np)
+{
+ u64 dma_addr, paddr, size;
+ int ret;
+ bool coherent;
+ unsigned long offset;
+ struct iommu_ops *iommu;
+
+ /*
+* Set default dma-mask to 32 bit. Drivers are expected to setup
+* the correct supported dma_mask.
+*/
+ dev-coherent_dma_mask = DMA_BIT_MASK(32);
+
+ /*
+* Set it to coherent_dma_mask by default if the architecture
+* code has not set it.
+*/
+ if (!dev-dma_mask)
+ dev-dma_mask = dev-coherent_dma_mask;
+
+ ret = of_dma_get_range(np, dma_addr, paddr, size);
+ if (ret 0) {
+ dma_addr = offset = 0;
+ size = dev-coherent_dma_mask;
+ } else {
+ offset = PFN_DOWN(paddr - dma_addr);
+ dev_dbg(dev, dma_pfn_offset(%#08lx)\n, offset);
+ }
+
+ dev-dma_pfn_offset = offset;
+
+ coherent = of_dma_is_coherent(np);
+ dev_dbg(dev, device is%sdma coherent\n,
+ coherent ? : not );
+
+ iommu = of_iommu_configure(dev, np);
+ dev_dbg(dev, device is%sbehind an iommu\n,
+ iommu ? : not );
+
+ arch_setup_dma_ops(dev, dma_addr, size, iommu, coherent);
+}
+EXPORT_SYMBOL_GPL(of_dma_configure);
+
int of_device_register(struct platform_device *pdev)
{
device_initialize(pdev-dev);
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index d3f3988..cbee18d 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -19,7 +19,6 @@
#include linux/slab.h
#include linux/of_address.h
#include linux/of_device.h
-#include linux/of_iommu.h
#include linux/of_irq.h
#include linux/of_platform.h
#include linux/platform_device.h
@@ -150,59 +149,6 @@ struct platform_device *of_device_alloc(struct device_node
*np,
}
EXPORT_SYMBOL(of_device_alloc);
-/**
- * of_dma_configure - Setup DMA configuration
- * @dev: Device to apply DMA configuration
- *
- * Try to get devices's DMA configuration from DT and update it
- * accordingly.
- *
- * In case if platform code need to use own special DMA configuration,it
- * can use Platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE event
- * to fix up DMA configuration.
- */
-static void of_dma_configure(struct device *dev)
-{
- u64 dma_addr, paddr, size;
- int ret;
- bool coherent;
- unsigned long offset;
- struct iommu_ops *iommu;
-
- /*
-* Set default dma-mask to 32 bit. Drivers are expected to setup
-* the correct supported dma_mask.
-*/
- dev-coherent_dma_mask = DMA_BIT_MASK(32);
-
- /*
-* Set it to coherent_dma_mask by default if the architecture
-* code has not set it.
-*/
- if (!dev-dma_mask)
- dev-dma_mask = dev-coherent_dma_mask;
-
- ret = of_dma_get_range(dev-of_node, dma_addr, paddr, size);
- if (ret 0) {
- dma_addr = offset = 0;
- size = dev-coherent_dma_mask;
- } else {
- offset = PFN_DOWN(paddr - dma_addr);
- dev_dbg(dev,
[PATCH 5/6] ARM: DT: msm8660: Add TCSR support
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi
b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd61..c162736 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -81,7 +81,7 @@
};
gsbi12: gsbi@19c0 {
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-msm8660;
reg = 0x19c0 0x100;
clocks = gcc GSBI12_H_CLK;
clock-names = iface;
@@ -89,6 +89,9 @@
#size-cells = 1;
ranges;
+ qcom,gsbi-num = 12;
+ syscon-tcsr = tcsr;
+
serial@19c4 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x19c4 0x1000,
@@ -196,6 +199,11 @@
vmmc-supply = vsdcc_fixed;
};
};
+
+ tcsr: syscon@1a40 {
+ compatible = qcom,tcsr-msm8660, syscon;
+ reg = 0x1a40 0x100;
+ };
};
};
--
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[PATCH 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 17 ++-
drivers/soc/qcom/Kconfig |1 +
drivers/soc/qcom/qcom_gsbi.c | 148 +++-
3 files changed, 158 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
index 4ce24d4..39eea8a 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
@@ -6,12 +6,18 @@ configuration settings. The mode setting will govern the
input/output mode of
the 4 GSBI IOs.
Required properties:
-- compatible: must contain qcom,gsbi-v1.0.0 for APQ8064/IPQ8064
+- compatible: Should contain:
+ qcom,gsbi-ipq8064 for IPQ8064
+ qcom,gsbi-apq8064 for APQ8064
+ qcom,gsbi-msm8960 for MSM8960
+ qcom,gsbi-msm8660 for MSM8660
- reg: Address range for GSBI registers
- clocks: required clock
- clock-names: must contain iface entry
- qcom,mode : indicates MUX value for configuration of the serial interface.
Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
+- qcom,gsbi-num: indicates GSBI instance number
+- syscon-tcsr: indicates phandle of TCSR syscon node
Optional properties:
- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
@@ -48,6 +54,9 @@ Example for APQ8064:
qcom,mode = GSBI_PROT_I2C_UART;
qcom,crci = GSBI_CRCI_QUP;
+ qcom,gsbi-num = 4;
+ syscon-tcsr = tcsr;
+
/* child nodes go under here */
i2c_qup4: i2c@1638 {
@@ -76,3 +85,9 @@ Example for APQ8064:
};
};
+ tcsr: syscon@1a40 {
+ compatible = qcom,apq8064-tcsr, syscon;
+ reg = 0x1a40 0x100;
+ };
+
+
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..32f20be 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
config QCOM_GSBI
tristate QCOM General Serial Bus Interface
depends on ARCH_QCOM
+ select MFD_SYSCON
help
Say y here to enable GSBI support. The GSBI provides control
functions for connecting the underlying serial UART, SPI, and I2C
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index 729425d..c7a22b5 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -18,22 +18,129 @@
#include linux/of.h
#include linux/of_platform.h
#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+#include dt-bindings/soc/qcom,gsbi.h
#define GSBI_CTRL_REG 0x
#define GSBI_PROTOCOL_SHIFT4
+#define MAX_GSBI 12
+
+#define TCSR_ADM_CRCI_BASE 0x70
+
+struct crci_config {
+ u32 num_rows;
+ const u32 *array;
+};
+
+static const u32 crci_ipq8064[][MAX_GSBI] = {
+ {
+ 0x03, 0x0c, 0x30, 0xc0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x03, 0x0c, 0x30, 0xc0
+ },
+ {
+ 0x03, 0x0c, 0x30, 0xc0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x03, 0x0c, 0x30, 0xc0
+ },
+};
+
+static const struct crci_config config_ipq8064 = {
+ .num_rows = ARRAY_SIZE(crci_ipq8064),
+ .array = crci_ipq8064[0],
+};
+
+static const unsigned int crci_apq8064[][MAX_GSBI] = {
+ {
+ 0x001800, 0x006000, 0x30, 0xc0,
+ 0x000300, 0x000400, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ },
+ {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x20, 0xc0, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ },
+};
+
+static const struct crci_config config_apq8064 = {
+ .num_rows = ARRAY_SIZE(crci_apq8064),
+ .array = crci_apq8064[0],
+};
+
+static const unsigned int crci_msm8960[][MAX_GSBI] = {
+ {
+ 0x03, 0x0c, 0x30, 0xc0,
+ 0x000300, 0x000400, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ },
+ {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x20, 0xc0, 0x000300,
+ 0x001800, 0x006000, 0x00, 0x00
+ },
+};
+
+static const struct crci_config config_msm8960 = {
+ .num_rows = ARRAY_SIZE(crci_msm8960),
+ .array =
[RFC/PATCH] pinctrl: sh-pfc: Accept standard function, pins and groups properties
The function, pins and groups pinmux and pinctrl properties have
been standardized. Support them in addition to the custom renesas,*
properties. New-style and old-style properties can't be mixed in DT.
Signed-off-by: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
---
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 20 +--
drivers/pinctrl/sh-pfc/pinctrl.c | 41 +-
2 files changed, 43 insertions(+), 18 deletions(-)
Hi Linus,
On Tuesday 27 January 2015 08:55:20 Linus Walleij wrote:
On Sun, Jan 18, 2015 at 1:20 PM, Niklas Söderlund n...@kth.se wrote:
Configure the pinmux on kzm9d to use the serial connector for uart1.
Signed-off-by: Niklas Söderlund n...@kth.se
Acked-by: Linus Walleij linus.wall...@linaro.org
+pfc {
+ uart1_pins: uart@e103 {
+ renesas,groups = uart1_ctrl, uart1_data;
+ renesas,function = uart1;
+ };
+};
Would be nice if the PFC driver could be augmented to also accept the
now standard bindings groups and function simply :) we're adding parse
functions for those to the core.
Something like this ?
Please note two differences between the Renesas PFC bindings and the standard
bindings:
- The standard bindings state that a pinctrl node must contain either a pins
property or a groups property, while the Renesas bindings allows for both
to coexist in the same node.
- The standard bindings don't allow a pinmux node to contain a pins property,
while the Renesas bindings do.
This patch implements the Renesas behaviour with the standard properties. The
difference in behaviour might not be desired. Please let me know what you
think.
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index bfe72ec055e3..60d191911e80 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -56,12 +56,12 @@ are parsed through phandles and processed purely based on
their content.
Pin Configuration Node Properties:
-- renesas,pins : An array of strings, each string containing the name of a pin.
-- renesas,groups : An array of strings, each string containing the name of a
pin
+- pins : An array of strings, each string containing the name of a pin.
+- groups : An array of strings, each string containing the name of a pin
group.
-- renesas,function: A string containing the name of the function to mux to the
- pin group(s) specified by the renesas,groups property
+- function: A string containing the name of the function to mux to the pin
+ group(s) specified by the groups property.
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
@@ -139,19 +139,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state
hog and pin control maps
mmcif_pins: mmcif {
mux {
- renesas,groups = mmc0_data8_0, mmc0_ctrl_0;
- renesas,function = mmc0;
+ groups = mmc0_data8_0, mmc0_ctrl_0;
+ function = mmc0;
};
cfg {
- renesas,groups = mmc0_data8_0;
- renesas,pins = PORT279;
+ groups = mmc0_data8_0;
+ pins = PORT279;
bias-pull-up;
};
};
scifa4_pins: scifa4 {
- renesas,groups = scifa4_data, scifa4_ctrl;
- renesas,function = scifa4;
+ groups = scifa4_data, scifa4_ctrl;
+ function = scifa4;
};
};
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 072e7c62cab7..522909e74b2e 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -40,6 +40,10 @@ struct sh_pfc_pinctrl {
struct pinctrl_pin_desc *pins;
struct sh_pfc_pin_config *configs;
+
+ const char *func_prop_name;
+ const char *groups_prop_name;
+ const char *pins_prop_name;
};
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
@@ -96,10 +100,13 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map,
return 0;
}
-static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
+static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps, unsigned int *index)
{
+ struct sh_pfc_pinctrl *pmx =
Re: [PATCH v5 3/6] iio: adc: fsl,imx25-gcq driver
On 24/01/15 14:01, Markus Pargmann wrote:
This is a conversion queue driver for the mx25 SoC. It uses the central
ADC which is used by two seperate independent queues. This driver
prepares different conversion configurations for each possible input.
For a conversion it creates a conversionqueue of one item with the
correct configuration for the chosen channel. It then executes the queue
once and disables the conversion queue afterwards.
The reference voltages are configurable through devicetree subnodes,
depending on the connections of the ADC inputs.
Signed-off-by: Markus Pargmann m...@pengutronix.de
Signed-off-by: Denis Carikli de...@eukrea.com
A couple of queries inline.
---
Notes:
Changes in v5:
- Fixed locking
- Removed module owner
.../devicetree/bindings/iio/adc/fsl,imx25-gcq.txt | 51 +++
drivers/iio/adc/Kconfig| 7 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/fsl-imx25-gcq.c| 369
+
include/dt-bindings/iio/adc/fsl-imx25-gcq.h| 11 +
5 files changed, 439 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
create mode 100644 drivers/iio/adc/fsl-imx25-gcq.c
create mode 100644 include/dt-bindings/iio/adc/fsl-imx25-gcq.h
diff --git a/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
b/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
new file mode 100644
index ..d55b6b751349
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
@@ -0,0 +1,51 @@
+Freescale i.MX25 ADC GCQ device
+
+This is a generic conversion queue device that can convert any of the
+analog inputs using the ADC unit of the i.MX25.
+
+Required properties:
+ - compatible: Should be fsl,imx25-gcq.
+ - reg: Should be the register range of the module.
+ - interrupts: Should be the interrupt number of the module.
+ Typically this is 1.
+ - interrupt-parent: phandle to the tsadc module of the i.MX25.
+ - #address-cells: Should be 1 (setting for the subnodes)
+ - #size-cells: Should be 0 (setting for the subnodes)
+
+Optional properties:
+ - vref-supply: The regulator supplying the ADC reference voltage.
+ Required when at least one subnode uses the external reference.
+
+Sub-nodes:
+Optionally you can define subnodes which define the reference voltage
+for the analog inputs.
+
+Required properties for subnodes:
+ - reg: Should be the number of the analog input.
+ 0: xp
+ 1: yp
+ 2: xn
+ 3: yn
+ 4: wiper
+ 5: inaux0
+ 6: inaux1
+ 7: inaux2
+ - fsl,adc-ref: specifies the reference input as defined in
+ dt-bindings/iio/adc/fsl-imx25-gcq.h
+ MX25_ADC_REF_INT and MX25_ADC_REF_EXT flags are supported.
+
+Example:
+
+ adc: adc@50030800 {
+ compatible = fsl,imx25-gcq;
+ reg = 0x50030800 0x60;
+ interrupt-parent = tscadc;
+ interrupts = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ inaux@5 {
+ reg = 5;
+ fsl,adc-ref = MX25_ADC_REF_INT;
+ };
+ };
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 0f79e4725763..fccbb4bf44cc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -143,6 +143,13 @@ config EXYNOS_ADC
of SoCs for drivers such as the touchscreen and hwmon to use to share
this resource.
+config FSL_MX25_ADC
+ tristate Freescale MX25 ADC driver
+ depends on MFD_MX25_TSADC
+ help
+ Generic Conversion Queue driver used for general purpose ADC in the
+ MX25. This driver supports single measurements using the MX25 ADC.
+
config LP8788_ADC
tristate LP8788 ADC driver
depends on MFD_LP8788
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 701fdb7c96aa..acab8d956371 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_AD799X) += ad799x.o
obj-$(CONFIG_AT91_ADC) += at91_adc.o
obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
+obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
diff --git a/drivers/iio/adc/fsl-imx25-gcq.c b/drivers/iio/adc/fsl-imx25-gcq.c
new file mode 100644
index ..c1ac5af41ec5
--- /dev/null
+++ b/drivers/iio/adc/fsl-imx25-gcq.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright 2014 Markus Pargmann, Pengutronix m...@pengutronix.de
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ *
Re: [RFC/PATCH] pinctrl: sh-pfc: Accept standard function, pins and groups properties
On Tue, Jan 27, 2015 at 9:31 PM, Laurent Pinchart
laurent.pinchart+rene...@ideasonboard.com wrote:
+ if (of_find_property(np, groups, NULL) ||
+ of_find_property(np, pins, NULL)) {
+ pmx-func_prop_name = function;
+ pmx-groups_prop_name = groups;
+ pmx-pins_prop_name = pins;
+ } else {
+ pmx-func_prop_name = renesas,function;
+ pmx-groups_prop_name = renesas,groups;
+ pmx-pins_prop_name = renesas,pins;
+ }
Do we want to be clever and save memory?
pmx-func_prop_name = renesas,function;
pmx-groups_prop_name = renesas,groups;
pmx-pins_prop_name = renesas,pins;
if (of_find_property(np, groups, NULL) ||
of_find_property(np, pins, NULL)) {
pmx-func_prop_name += strlen(renesas,);
pmx-groups_prop_name += strlen(renesas,);
pmx-pins_prop_name += strlen(renesas,);
}
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
-- Linus Torvalds
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Re: [PATCH 1/2] dt: watchdog: Add DT binding documentation for jz47xx watchdog timer
On Tuesday 27 January 2015 12:52:29 Guenter Roeck wrote: Driver does this (today): drvdata-rtc_clk = clk_get(pdev-dev, rtc); Isn't that the name to use ? Just wondering. Just because the driver uses it at the moment does not mean it's the name that the IP block uses. clk_get() has the unpleasant property of doing fuzzy matching on the name that is passed. It first tries to use the string as the name of the clock input of the device, but if that is not there, it falls back to looking for a global clk with a con_id. In DT, we only support the first kind, but if a driver currently uses the second, you get the wrong name. Looking at arch/mips/jz4740/clock.c now, this seems to be exactly what is going on here: there is no clkdev_add call to associate the device clocks, so it can only match a global clock entry. :( Arnd -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] dt: watchdog: Add DT binding documentation for jz47xx watchdog timer
On Tue, Jan 27, 2015 at 09:16:45PM +0100, Arnd Bergmann wrote:
On Tuesday 27 January 2015 15:11:29 Zubair Lutfullah Kakakhel wrote:
+clocks: phandle to rtcclk
+clock-names: must be rtc
+
+Example:
+
+watchdog: jz47xx-watchdog@0x10002000 {
+ compatible = ingenic,jz4780-watchdog;
+ reg = 0x10002000 0x100;
+
+ clocks = rtclk;
+ clock-names = rtc;
+};
Why is the name rtc? are you sure you are not confusing the output
name of the clock controller with the input of the watchdog device?
Driver does this (today):
drvdata-rtc_clk = clk_get(pdev-dev, rtc);
Isn't that the name to use ? Just wondering.
Thanks,
Guenter
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[PATCH v5 1/4] tpm/tpm_i2c_stm_st33: Replace access to io_lpcpd from struct st33zp24_platform_data to tpm_stm_dev
io_lpcpd is accessible from struct tpm_stm_dev.
struct st33zp24_platform_data is only valid when using static platform
configuration data, not when using dts.
Reviewed-by: Jason Gunthorpe jason.guntho...@obsidianresearch.com
Signed-off-by: Christophe Ricard christophe-h.ric...@st.com
---
drivers/char/tpm/tpm_i2c_stm_st33.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/char/tpm/tpm_i2c_stm_st33.c
b/drivers/char/tpm/tpm_i2c_stm_st33.c
index 612845b..882c60a 100644
--- a/drivers/char/tpm/tpm_i2c_stm_st33.c
+++ b/drivers/char/tpm/tpm_i2c_stm_st33.c
@@ -837,11 +837,14 @@ static int tpm_stm_i2c_remove(struct i2c_client *client)
*/
static int tpm_stm_i2c_pm_suspend(struct device *dev)
{
- struct st33zp24_platform_data *pin_infos = dev-platform_data;
+ struct tpm_chip *chip = dev_get_drvdata(dev);
+ struct tpm_stm_dev *tpm_dev;
int ret = 0;
- if (gpio_is_valid(pin_infos-io_lpcpd))
- gpio_set_value(pin_infos-io_lpcpd, 0);
+ tpm_dev = (struct tpm_stm_dev *)TPM_VPRIV(chip);
+
+ if (gpio_is_valid(tpm_dev-io_lpcpd))
+ gpio_set_value(tpm_dev-io_lpcpd, 0);
else
ret = tpm_pm_suspend(dev);
@@ -856,12 +859,13 @@ static int tpm_stm_i2c_pm_suspend(struct device *dev)
static int tpm_stm_i2c_pm_resume(struct device *dev)
{
struct tpm_chip *chip = dev_get_drvdata(dev);
- struct st33zp24_platform_data *pin_infos = dev-platform_data;
-
+ struct tpm_stm_dev *tpm_dev;
int ret = 0;
- if (gpio_is_valid(pin_infos-io_lpcpd)) {
- gpio_set_value(pin_infos-io_lpcpd, 1);
+ tpm_dev = (struct tpm_stm_dev *)TPM_VPRIV(chip);
+
+ if (gpio_is_valid(tpm_dev-io_lpcpd)) {
+ gpio_set_value(tpm_dev-io_lpcpd, 1);
ret = wait_for_stat(chip,
TPM_STS_VALID, chip-vendor.timeout_b,
chip-vendor.read_queue, false);
--
2.1.0
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[PATCH v5 2/4] tpm/tpm_i2c_stm_st33: Split tpm_i2c_tpm_st33 in 2 layers (core + phy)
tpm_i2c_stm_st33 is a TIS 1.2 TPM with a core interface which can be used by different phy such as i2c or spi. The core part is called st33zp24 which is also the main part reference. include/linux/platform_data/tpm_stm_st33.h is renamed consequently. The driver is also split into an i2c phy in charge of sending/receiving data as well as managing platform data or dts configuration. Reviewed-by: Jason Gunthorpe jason.guntho...@obsidianresearch.com Signed-off-by: Christophe Ricard christophe-h.ric...@st.com --- drivers/char/tpm/Kconfig | 11 +- drivers/char/tpm/Makefile | 2 +- drivers/char/tpm/st33zp24/Kconfig | 20 + drivers/char/tpm/st33zp24/Makefile | 9 + drivers/char/tpm/st33zp24/i2c.c| 278 + drivers/char/tpm/st33zp24/st33zp24.c | 688 ++ drivers/char/tpm/st33zp24/st33zp24.h | 34 ++ drivers/char/tpm/tpm_i2c_stm_st33.c| 915 - include/linux/platform_data/st33zp24.h | 28 + include/linux/platform_data/tpm_stm_st33.h | 39 -- 10 files changed, 1059 insertions(+), 965 deletions(-) create mode 100644 drivers/char/tpm/st33zp24/Kconfig create mode 100644 drivers/char/tpm/st33zp24/Makefile create mode 100644 drivers/char/tpm/st33zp24/i2c.c create mode 100644 drivers/char/tpm/st33zp24/st33zp24.c create mode 100644 drivers/char/tpm/st33zp24/st33zp24.h delete mode 100644 drivers/char/tpm/tpm_i2c_stm_st33.c create mode 100644 include/linux/platform_data/st33zp24.h delete mode 100644 include/linux/platform_data/tpm_stm_st33.h diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 9d4e375..2dc16d3 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -100,16 +100,6 @@ config TCG_IBMVTPM will be accessible from within Linux. To compile this driver as a module, choose M here; the module will be called tpm_ibmvtpm. -config TCG_TIS_I2C_ST33 - tristate TPM Interface Specification 1.2 Interface (I2C - STMicroelectronics) - depends on I2C - depends on GPIOLIB - ---help--- - If you have a TPM security chip from STMicroelectronics working with - an I2C bus say Yes and it will be accessible from within Linux. - To compile this driver as a module, choose M here; the module will be - called tpm_i2c_stm_st33. - config TCG_XEN tristate XEN TPM Interface depends on TCG_TPM XEN @@ -131,4 +121,5 @@ config TCG_CRB from within Linux. To compile this driver as a module, choose M here; the module will be called tpm_crb. +source drivers/char/tpm/st33zp24/Kconfig endif # TCG_TPM diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 990cf18..56e8f1f 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -20,6 +20,6 @@ obj-$(CONFIG_TCG_NSC) += tpm_nsc.o obj-$(CONFIG_TCG_ATMEL) += tpm_atmel.o obj-$(CONFIG_TCG_INFINEON) += tpm_infineon.o obj-$(CONFIG_TCG_IBMVTPM) += tpm_ibmvtpm.o -obj-$(CONFIG_TCG_TIS_I2C_ST33) += tpm_i2c_stm_st33.o +obj-$(CONFIG_TCG_TIS_ST33ZP24) += st33zp24/ obj-$(CONFIG_TCG_XEN) += xen-tpmfront.o obj-$(CONFIG_TCG_CRB) += tpm_crb.o diff --git a/drivers/char/tpm/st33zp24/Kconfig b/drivers/char/tpm/st33zp24/Kconfig new file mode 100644 index 000..51dcef5 --- /dev/null +++ b/drivers/char/tpm/st33zp24/Kconfig @@ -0,0 +1,20 @@ +config TCG_TIS_ST33ZP24 + tristate STMicroelectronics TPM Interface Specification 1.2 Interface + depends on GPIOLIB + ---help--- + STMicroelectronics ST33ZP24 core driver. It implements the core + TPM1.2 logic and hooks into the TPM kernel APIs. Physical layers will + register against it. + + To compile this driver as a module, choose m here. The module will be called + tpm_st33zp24. + +config TCG_TIS_ST33ZP24_I2C + tristate TPM 1.2 ST33ZP24 I2C support + depends on TCG_TIS_ST33ZP24 + depends on I2C + ---help--- + This module adds support for the STMicroelectronics TPM security chip + ST33ZP24 with i2c interface. + To compile this driver as a module, choose M here; the module will be + called tpm_st33zp24_i2c. diff --git a/drivers/char/tpm/st33zp24/Makefile b/drivers/char/tpm/st33zp24/Makefile new file mode 100644 index 000..414497f --- /dev/null +++ b/drivers/char/tpm/st33zp24/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for ST33ZP24 TPM 1.2 driver +# + +tpm_st33zp24-objs = st33zp24.o +obj-$(CONFIG_TCG_TIS_ST33ZP24) += tpm_st33zp24.o + +tpm_st33zp24_i2c-objs = i2c.o +obj-$(CONFIG_TCG_TIS_ST33ZP24_I2C) += tpm_st33zp24_i2c.o diff --git a/drivers/char/tpm/st33zp24/i2c.c b/drivers/char/tpm/st33zp24/i2c.c new file mode 100644 index 000..95e3091 --- /dev/null +++ b/drivers/char/tpm/st33zp24/i2c.c @@ -0,0 +1,278 @@ +/* + * STMicroelectronics TPM I2C Linux driver for TPM ST33ZP24 + * Copyright (C) 2009 - 2015 STMicroelectronics +
[PATCH v5 3/4] tpm/st33zp24/spi: Add st33zp24 spi phy
st33zp24 TIS 1.2 support also SPI. It is using a proprietary protocol to
transport TIS data.
Reviewed-by: Jason Gunthorpe jason.guntho...@obsidianresearch.com
Signed-off-by: Christophe Ricard christophe-h.ric...@st.com
---
drivers/char/tpm/st33zp24/Kconfig| 10 +
drivers/char/tpm/st33zp24/Makefile | 3 +
drivers/char/tpm/st33zp24/i2c.c | 2 -
drivers/char/tpm/st33zp24/spi.c | 386 +++
drivers/char/tpm/st33zp24/st33zp24.h | 3 +
5 files changed, 402 insertions(+), 2 deletions(-)
create mode 100644 drivers/char/tpm/st33zp24/spi.c
diff --git a/drivers/char/tpm/st33zp24/Kconfig
b/drivers/char/tpm/st33zp24/Kconfig
index 51dcef5..09cb7278 100644
--- a/drivers/char/tpm/st33zp24/Kconfig
+++ b/drivers/char/tpm/st33zp24/Kconfig
@@ -18,3 +18,13 @@ config TCG_TIS_ST33ZP24_I2C
ST33ZP24 with i2c interface.
To compile this driver as a module, choose M here; the module will be
called tpm_st33zp24_i2c.
+
+config TCG_TIS_ST33ZP24_SPI
+ tristate TPM 1.2 ST33ZP24 SPI support
+ depends on TCG_TIS_ST33ZP24
+ depends on SPI
+ ---help---
+ This module adds support for the STMicroelectronics TPM security chip
+ ST33ZP24 with spi interface.
+ To compile this driver as a module, choose M here; the module will be
+ called tpm_st33zp24_spi.
diff --git a/drivers/char/tpm/st33zp24/Makefile
b/drivers/char/tpm/st33zp24/Makefile
index 414497f..74a722e 100644
--- a/drivers/char/tpm/st33zp24/Makefile
+++ b/drivers/char/tpm/st33zp24/Makefile
@@ -7,3 +7,6 @@ obj-$(CONFIG_TCG_TIS_ST33ZP24) += tpm_st33zp24.o
tpm_st33zp24_i2c-objs = i2c.o
obj-$(CONFIG_TCG_TIS_ST33ZP24_I2C) += tpm_st33zp24_i2c.o
+
+tpm_st33zp24_spi-objs = spi.o
+obj-$(CONFIG_TCG_TIS_ST33ZP24_SPI) += tpm_st33zp24_spi.o
diff --git a/drivers/char/tpm/st33zp24/i2c.c b/drivers/char/tpm/st33zp24/i2c.c
index 95e3091..ad1ee18 100644
--- a/drivers/char/tpm/st33zp24/i2c.c
+++ b/drivers/char/tpm/st33zp24/i2c.c
@@ -27,8 +27,6 @@
#include st33zp24.h
#define TPM_DUMMY_BYTE 0xAA
-#define TPM_WRITE_DIRECTION0x80
-#define TPM_BUFSIZE2048
struct st33zp24_i2c_phy {
struct i2c_client *client;
diff --git a/drivers/char/tpm/st33zp24/spi.c b/drivers/char/tpm/st33zp24/spi.c
new file mode 100644
index 000..b9ef57c
--- /dev/null
+++ b/drivers/char/tpm/st33zp24/spi.c
@@ -0,0 +1,386 @@
+/*
+ * STMicroelectronics TPM SPI Linux driver for TPM ST33ZP24
+ * Copyright (C) 2009 - 2015 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/module.h
+#include linux/spi/spi.h
+#include linux/gpio.h
+#include linux/of_irq.h
+#include linux/of_gpio.h
+#include linux/tpm.h
+#include linux/platform_data/st33zp24.h
+
+#include st33zp24.h
+
+#define TPM_DATA_FIFO 0x24
+#define TPM_INTF_CAPABILITY 0x14
+
+#define TPM_DUMMY_BYTE 0x00
+
+#define MAX_SPI_LATENCY15
+#define LOCALITY0 0
+
+#define ST33ZP24_OK0x5A
+#define ST33ZP24_UNDEFINED_ERR 0x80
+#define ST33ZP24_BADLOCALITY 0x81
+#define ST33ZP24_TISREGISTER_UKNOWN0x82
+#define ST33ZP24_LOCALITY_NOT_ACTIVATED0x83
+#define ST33ZP24_HASH_END_BEFORE_HASH_START0x84
+#define ST33ZP24_BAD_COMMAND_ORDER 0x85
+#define ST33ZP24_INCORECT_RECEIVED_LENGTH 0x86
+#define ST33ZP24_TPM_FIFO_OVERFLOW 0x89
+#define ST33ZP24_UNEXPECTED_READ_FIFO 0x8A
+#define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B
+#define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END 0x90
+#define ST33ZP24_DUMMY_BYTES 0x00
+
+struct st33zp24_spi_phy {
+ struct spi_device *spi_device;
+ struct spi_transfer spi_xfer;
+ int io_lpcpd;
+ int latency;
+};
+
+static int st33zp24_status_to_errno(u8 code)
+{
+ switch (code) {
+ case ST33ZP24_OK:
+ return 0;
+ case ST33ZP24_UNDEFINED_ERR:
+ case ST33ZP24_BADLOCALITY:
+ case ST33ZP24_TISREGISTER_UKNOWN:
+ case ST33ZP24_LOCALITY_NOT_ACTIVATED:
+ case ST33ZP24_HASH_END_BEFORE_HASH_START:
+ case ST33ZP24_BAD_COMMAND_ORDER:
+ case
[PATCH v5 0/4] st33zp24 new architecture proposal and st33zp24 spi driver
Hi, The following patchset: - propose a new architecture allowing to share a core st33zp24 data management layer with different phy (i2c spi). For st33zp24 both phy have a proprietary transport protocol. Both are relying on the TCG TIS protocol. At the end, it simplifies the maintenance. - Add an spi phy allowing to support st33zp24 using with an SPI bus. The complete solution got tested in polling and interrupt mode successfully with i2c spi phy. This patchset applies on top of Peter's tree https://github.com/PeterHuewe/linux-tpmdd.git for-james branch on top of: d4989d9f693b9502f9288da5db279c2f8c2e50be tpm/tpm_tis: Add missing ifdef CONFIG_ACPI for pnp_acpi_device I confirm also Jarkko Sakkinen's changes are working with this product with both phy's. - v2 takes into account feedbacks from Jason Gunthorpe. - v3 is reduced to 4 patches as 6 out of 10 got accepted for 3.20. Also compare to v2: * Fix build issue with patch v2 04/10 Replace access to io_lpcpd from struct st33zp24_platform_data to tpm_stm_dev * Fix link issue with patch v2 08/10 Split tpm_i2c_tpm_st33 in 2 layers (core + phy) when building as a module. The symbols wasn't exported in st33zp24.c. * Add missing MODULE_LICENSE in patch v2 09/10 Add st33zp24 spi phy * Fix node example in dts spi documentation in patch v2 10/10 Add dts documentation for st33zp24 spi phy * Fix typo on Jason Gunthorpe first name. Sorry for that :(... * Change contact email address as tpmsupp...@st.com is no more valid - v4 adds missing module_license in st33zp24 - v5 includes as best as possible PeterHuewe comments. Best Regards Christophe Christophe Ricard (4): tpm/tpm_i2c_stm_st33: Replace access to io_lpcpd from struct st33zp24_platform_data to tpm_stm_dev tpm/tpm_i2c_stm_st33: Split tpm_i2c_tpm_st33 in 2 layers (core + phy) tpm/st33zp24/spi: Add st33zp24 spi phy tpm/st33zp24/dts/st33zp24-spi: Add dts documentation for st33zp24 spi phy .../bindings/security/tpm/st33zp24-spi.txt | 34 + drivers/char/tpm/Kconfig | 11 +- drivers/char/tpm/Makefile | 2 +- drivers/char/tpm/st33zp24/Kconfig | 30 + drivers/char/tpm/st33zp24/Makefile | 12 + drivers/char/tpm/st33zp24/i2c.c| 276 +++ drivers/char/tpm/st33zp24/spi.c| 386 + drivers/char/tpm/st33zp24/st33zp24.c | 688 drivers/char/tpm/st33zp24/st33zp24.h | 37 + drivers/char/tpm/tpm_i2c_stm_st33.c| 911 - include/linux/platform_data/st33zp24.h | 28 + include/linux/platform_data/tpm_stm_st33.h | 39 - 12 files changed, 1493 insertions(+), 961 deletions(-) create mode 100644 Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt create mode 100644 drivers/char/tpm/st33zp24/Kconfig create mode 100644 drivers/char/tpm/st33zp24/Makefile create mode 100644 drivers/char/tpm/st33zp24/i2c.c create mode 100644 drivers/char/tpm/st33zp24/spi.c create mode 100644 drivers/char/tpm/st33zp24/st33zp24.c create mode 100644 drivers/char/tpm/st33zp24/st33zp24.h delete mode 100644 drivers/char/tpm/tpm_i2c_stm_st33.c create mode 100644 include/linux/platform_data/st33zp24.h delete mode 100644 include/linux/platform_data/tpm_stm_st33.h -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 4/4] tpm/st33zp24/dts/st33zp24-spi: Add dts documentation for st33zp24 spi phy
Reviewed-by: Jason Gunthorpe jason.guntho...@obsidianresearch.com
Signed-off-by: Christophe Ricard christophe-h.ric...@st.com
---
.../bindings/security/tpm/st33zp24-spi.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt
diff --git a/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt
b/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt
new file mode 100644
index 000..158b016
--- /dev/null
+++ b/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt
@@ -0,0 +1,34 @@
+* STMicroelectronics SAS. ST33ZP24 TPM SoC
+
+Required properties:
+- compatible: Should be st,st33zp24-spi.
+- spi-max-frequency: Maximum SPI frequency (= 1000).
+
+Optional ST33ZP24 Properties:
+- interrupt-parent: phandle for the interrupt gpio controller
+- interrupts: GPIO interrupt to which the chip is connected
+- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
+If set, power must be present when the platform is going into sleep/hibernate
mode.
+
+Optional SoC Specific Properties:
+- pinctrl-names: Contains only one value - default.
+- pintctrl-0: Specifies the pin control groups used for this controller.
+
+Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
+
+mcspi4 {
+
+status = okay;
+
+st33zp24@0 {
+
+compatible = st,st33zp24-spi;
+
+spi-max-frequency = 1000;
+
+interrupt-parent = gpio5;
+interrupts = 7 IRQ_TYPE_LEVEL_HIGH;
+
+lpcpd-gpios = gpio5 15 GPIO_ACTIVE_HIGH;
+};
+};
--
2.1.0
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[PATCH 6/6] ARM: DT: msm8960: Add TCSR support
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5c..913a9f1 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -121,7 +121,7 @@
};
gsbi5: gsbi@1640 {
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-msm8960;
reg = 0x1640 0x100;
clocks = gcc GSBI5_H_CLK;
clock-names = iface;
@@ -129,6 +129,9 @@
#size-cells = 1;
ranges;
+ qcom,gsbi-num = 5;
+ syscon-tcsr = tcsr;
+
serial@1644 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x1644 0x1000,
@@ -238,5 +241,10 @@
vmmc-supply = vsdcc_fixed;
};
};
+
+ tcsr: syscon@1a40 {
+ compatible = qcom,tcsr-msm8960, syscon;
+ reg = 0x1a40 0x100;
+ };
};
};
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Re: [PATCH v2 4/4] ARM: shmobile: emev2-kzm9d: Add PFC information for uart1
Hi Niklas,
Thank you for the patch.
On Sunday 18 January 2015 13:20:04 Niklas Söderlund wrote:
Configure the pinmux on kzm9d to use the serial connector for uart1.
Signed-off-by: Niklas Söderlund n...@kth.se
Acked-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
arch/arm/boot/dts/emev2-kzm9d.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts
b/arch/arm/boot/dts/emev2-kzm9d.dts index 667d323..1944627 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -94,3 +94,16 @@
vdd33a-supply = reg_3p3v;
};
};
+
+pfc {
+ uart1_pins: uart@e103 {
+ renesas,groups = uart1_ctrl, uart1_data;
+ renesas,function = uart1;
+ };
+};
+
+uart1 {
+ pinctrl-0 = uart1_pins;
+ pinctrl-names = default;
+ status = okay;
+};
--
Regards,
Laurent Pinchart
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Re: [PATCH 2/2] watchdog: jz4740: Add DT support
On Tuesday 27 January 2015 12:54:30 Guenter Roeck wrote:
On Tue, Jan 27, 2015 at 09:15:37PM +0100, Arnd Bergmann wrote:
On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
};
+#ifdef CONFIG_OF
+static const struct of_device_id jz4740_of_matches[] = {
+ { .compatible = ingenic,jz4740-watchdog, },
+ { /* sentinel */ }
+};
+#endif
+
static int jz4740_wdt_probe(struct platform_device *pdev)
{
struct jz4740_wdt_drvdata *drvdata;
@@ -211,6 +219,7 @@ static struct platform_driver jz4740_wdt_driver = {
.remove = jz4740_wdt_remove,
.driver = {
.name = jz4740-wdt,
+ .of_match_table = of_match_ptr(jz4740_of_matches),
},
Why the #ifdef? Presumably we want to move over jz4740 to DT-only in the
long run, so you could just remove the #ifdef and the of_match_ptr()
wrapper.
Only if depends on OF is added to its Kconfig entry, or am I missing
something ?
I'm pretty sure you don't need that, it will still compile and link
fine, the only downside being a few wasted bytes to store the compatible
string and the array.
Arnd
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[PATCH 0/6] GSBI CRCI Autoconfiguration Support
This patch set adds support for automatic configuration of GSBI DMA CRCI values. DMA operations require that the ADM CRCI mux values be properly configured in the TCSR (Top Control and Status Register) block. During probing of a GSBI device, the client mode must be declared and this can be used to lookup the correct TCSR ADM CRCI MUX settings and then program them so that they are correct before any clients are populated. These patches add the TCSR as a syscon device and that allows the GSBI to access and manipulate the ADM CRCI MUX registers to correctly configure the values based on the GSBI port configuration. Andy Gross (6): soc: qcom: gsbi: Add support for ADM CRCI muxing mfd: qcom,tcsr: Add device tree binding for TCSR ARM: DT: apq8064: Add TCSR support ARM: DT: ipq8064: Add TCSR support ARM: DT: msm8660: Add TCSR support ARM: DT: msm8960: Add TCSR support .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++ .../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 17 ++- arch/arm/boot/dts/qcom-apq8064.dtsi| 20 ++- arch/arm/boot/dts/qcom-ipq8064.dtsi| 20 ++- arch/arm/boot/dts/qcom-msm8660.dtsi| 10 +- arch/arm/boot/dts/qcom-msm8960.dtsi| 10 +- drivers/soc/qcom/Kconfig |1 + drivers/soc/qcom/qcom_gsbi.c | 148 +++- 8 files changed, 232 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] ARM: DT: apq8064: Add TCSR support
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..f9a947c 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -165,7 +165,7 @@
gsbi1: gsbi@1244 {
status = disabled;
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-apq8064;
reg = 0x1244 0x100;
clocks = gcc GSBI1_H_CLK;
clock-names = iface;
@@ -173,6 +173,9 @@
#size-cells = 1;
ranges;
+ qcom,gsbi-num = 1;
+ syscon-tcsr = tcsr;
+
i2c1: i2c@1246 {
compatible = qcom,i2c-qup-v1.1.1;
reg = 0x1246 0x1000;
@@ -186,7 +189,7 @@
gsbi2: gsbi@1248 {
status = disabled;
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-apq8064;
reg = 0x1248 0x100;
clocks = gcc GSBI2_H_CLK;
clock-names = iface;
@@ -194,6 +197,9 @@
#size-cells = 1;
ranges;
+ qcom,gsbi-num = 2;
+ syscon-tcsr = tcsr;
+
i2c2: i2c@124a {
compatible = qcom,i2c-qup-v1.1.1;
reg = 0x124a 0x1000;
@@ -207,7 +213,7 @@
gsbi7: gsbi@1660 {
status = disabled;
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-apq8064;
reg = 0x1660 0x100;
clocks = gcc GSBI7_H_CLK;
clock-names = iface;
@@ -215,6 +221,9 @@
#size-cells = 1;
ranges;
+ qcom,gsbi-num = 7;
+ syscon-tcsr = tcsr;
+
serial@1664 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x1664 0x1000,
@@ -349,5 +358,10 @@
pinctrl-0 = sdc4_gpios;
};
};
+
+ tcsr: syscon@1a40 {
+ compatible = qcom,tcsr-apq8064, syscon;
+ reg = 0x1a40 0x100;
+ };
};
};
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Re: [PATCH 2/2] watchdog: jz4740: Add DT support
On Tue, Jan 27, 2015 at 09:15:37PM +0100, Arnd Bergmann wrote:
On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
};
+#ifdef CONFIG_OF
+static const struct of_device_id jz4740_of_matches[] = {
+ { .compatible = ingenic,jz4740-watchdog, },
+ { /* sentinel */ }
+};
+#endif
+
static int jz4740_wdt_probe(struct platform_device *pdev)
{
struct jz4740_wdt_drvdata *drvdata;
@@ -211,6 +219,7 @@ static struct platform_driver jz4740_wdt_driver = {
.remove = jz4740_wdt_remove,
.driver = {
.name = jz4740-wdt,
+ .of_match_table = of_match_ptr(jz4740_of_matches),
},
Why the #ifdef? Presumably we want to move over jz4740 to DT-only in the
long run, so you could just remove the #ifdef and the of_match_ptr()
wrapper.
Only if depends on OF is added to its Kconfig entry, or am I missing
something ?
Guenter
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[PATCH v5 1/8] of: iommu: add ptr to OF node arg to of_iommu_configure()
Function of_iommu_configure() is called from of_dma_configure() to
setup iommu ops using DT property. This API is currently used for
platform devices for which DMA configuration (including iommu ops)
may come from device's parent. To extend this functionality for PCI
devices, this API need to take a parent node ptr as an argument
instead of assuming device's parent. This is needed since for PCI, the
dma configuration may be defined in the DT node of the root bus bridge's
parent device. Currently only dma-range is used for PCI and iommu is not
supported. So return error if the device is PCI.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Bjorn Helgaas bhelg...@google.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/iommu/of_iommu.c | 10 --
drivers/of/platform.c|2 +-
include/linux/of_iommu.h |6 --
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index af1dc6a..439235b 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -133,19 +133,25 @@ struct iommu_ops *of_iommu_get_ops(struct device_node *np)
return ops;
}
-struct iommu_ops *of_iommu_configure(struct device *dev)
+struct iommu_ops *of_iommu_configure(struct device *dev,
+struct device_node *iommu_np)
{
struct of_phandle_args iommu_spec;
struct device_node *np;
struct iommu_ops *ops = NULL;
int idx = 0;
+ if (dev_is_pci(dev)) {
+ dev_err(dev, iommu is currently not supported for PCI\n);
+ return NULL;
+ }
+
/*
* We don't currently walk up the tree looking for a parent IOMMU.
* See the `Notes:' section of
* Documentation/devicetree/bindings/iommu/iommu.txt
*/
- while (!of_parse_phandle_with_args(dev-of_node, iommus,
+ while (!of_parse_phandle_with_args(iommu_np, iommus,
#iommu-cells, idx,
iommu_spec)) {
np = iommu_spec.np;
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index b0d50d7..d3f3988 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -196,7 +196,7 @@ static void of_dma_configure(struct device *dev)
dev_dbg(dev, device is%sdma coherent\n,
coherent ? : not );
- iommu = of_iommu_configure(dev);
+ iommu = of_iommu_configure(dev, dev-of_node);
dev_dbg(dev, device is%sbehind an iommu\n,
iommu ? : not );
diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h
index 16c7554..a97e5bd 100644
--- a/include/linux/of_iommu.h
+++ b/include/linux/of_iommu.h
@@ -12,7 +12,8 @@ extern int of_get_dma_window(struct device_node *dn, const
char *prefix,
size_t *size);
extern void of_iommu_init(void);
-extern struct iommu_ops *of_iommu_configure(struct device *dev);
+extern struct iommu_ops *of_iommu_configure(struct device *dev,
+ struct device_node *iommu_np);
#else
@@ -24,7 +25,8 @@ static inline int of_get_dma_window(struct device_node *dn,
const char *prefix,
}
static inline void of_iommu_init(void) { }
-static inline struct iommu_ops *of_iommu_configure(struct device *dev)
+static inline struct iommu_ops *of_iommu_configure(struct device *dev,
+struct device_node *iommu_np)
{
return NULL;
}
--
1.7.9.5
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[PATCH v5 0/8] PCI: get DMA configuration from parent device
PCI devices on Keystone doesn't have correct dma_pfn_offset set. This patch add capability to set the dma configuration such as dma-mask, dma_pfn_offset, and dma ops etc using the information from DT. The prior RFCs and discussions are available at [1] and [2] below. [2] : https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg790244.html [1] : http://www.gossamer-threads.com/lists/linux/kernel/2024591 Change history: v5 - moved the dma_mask update in device from ARM specific API to of_dma_configure to allow this across other architecture as well - improved sanity check for DT dma-range size in of_dma_configure() - moved API to get parent bridge device to PCI (host-bridge.c) v4 - moved size adjustments in of_iommu_configure() to a separate patch - consistent node name comment from Rob - patch 6 added for dma_mask adjustment and iommu mapping size limiting. v3 - addressed comments to re-use of_dma_configure() for PCI - To help re-use, change of_iommu_configure() function argument - Move of_dma_configure to of/device.c - Limit the of_iommu_configure to non pci devices v2 - update size to coherent_dma_mask + 1 if dma-range info is missing - also check the np for null. v1 - updates based on the comments against initial RFC. - Added a helper function to get the OF node of the parent - Added an API in of_pci.c to update DMA configuration of the pci device. Cc: Joerg Roedel j...@8bytes.org Cc: Grant Likely grant.lik...@linaro.org Cc: Rob Herring robh...@kernel.org Cc: Bjorn Helgaas bhelg...@google.com Cc: Will Deacon will.dea...@arm.com Cc: Russell King li...@arm.linux.org.uk Cc: Arnd Bergmann a...@arndb.de Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Acked-by: Bjorn Helgaas bhelg...@google.com Acked-by: Murali Karicheri m-kariche...@ti.com Murali Karicheri (8): of: iommu: add ptr to OF node arg to of_iommu_configure() of: move of_dma_configure() to device.c to help re-use of: fix size when dma-range is not used PCI: add helper functions pci_get[put]_host_bridge_device() of/pci: add of_pci_dma_configure() update dma configuration PCI: update dma configuration from DT arm: dma-mapping: limit iommu mapping size of: limit dma_mask of the device based on dma-range size arch/arm/mm/dma-mapping.c |7 + drivers/iommu/of_iommu.c | 10 +-- drivers/of/device.c | 69 + drivers/of/of_pci.c | 19 + drivers/of/platform.c | 58 ++--- drivers/pci/host-bridge.c | 14 + drivers/pci/probe.c |2 ++ include/linux/of_device.h |2 ++ include/linux/of_iommu.h |6 ++-- include/linux/of_pci.h|5 include/linux/pci.h |3 ++ 11 files changed, 135 insertions(+), 60 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 7/8] arm: dma-mapping: limit iommu mapping size
arm_iommu_create_mapping() has size parameter of size_t and
arm_setup_iommu_dma_ops() can take a value higher than that
when this is called from the of code. So limit the size to
SIZE_MAX.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/mm/dma-mapping.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7864797..496b2c3 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -2004,6 +2004,13 @@ static bool arm_setup_iommu_dma_ops(struct device *dev,
u64 dma_base, u64 size,
if (!iommu)
return false;
+ /*
+* currently arm_iommu_create_mapping() takes a max of size_t
+* for size param. So check this limit for now.
+*/
+ if (size SIZE_MAX)
+ return false;
+
mapping = arm_iommu_create_mapping(dev-bus, dma_base, size);
if (IS_ERR(mapping)) {
pr_warn(Failed to create %llu-byte IOMMU mapping for device
%s\n,
--
1.7.9.5
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[PATCH v5 4/8] PCI: add helper functions pci_get[put]_host_bridge_device()
Add a helper function to get/put the root bus's host bridge device.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Bjorn Helgaas bhelg...@google.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/pci/host-bridge.c | 14 ++
include/linux/pci.h |3 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index 0e5f3c9..f58e05b 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -23,6 +23,20 @@ static struct pci_host_bridge *find_pci_host_bridge(struct
pci_bus *bus)
return to_pci_host_bridge(root_bus-bridge);
}
+struct device *pci_get_host_bridge_device(struct pci_dev *dev)
+{
+ struct pci_bus *root_bus = find_pci_root_bus(dev-bus);
+ struct device *bridge = root_bus-bridge;
+
+ kobject_get(bridge-kobj);
+ return bridge;
+}
+
+void pci_put_host_bridge_device(struct device *dev)
+{
+ kobject_put(dev-kobj);
+}
+
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
void (*release_fn)(struct pci_host_bridge *),
void *release_data)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 9603094..d677c66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -513,6 +513,9 @@ static inline struct pci_dev *pci_upstream_bridge(struct
pci_dev *dev)
return dev-bus-self;
}
+struct device *pci_get_host_bridge_device(struct pci_dev *dev);
+void pci_put_host_bridge_device(struct device *dev);
+
#ifdef CONFIG_PCI_MSI
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
{
--
1.7.9.5
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[PATCH v5 3/8] of: fix size when dma-range is not used
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev-coherent_dma_mask + 1 instead of dev-coherent_dma_mask. Also add
code to check invalid values of size configured in DT and log error.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/of/device.c |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 2de320d..17504f4 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -105,12 +105,19 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
ret = of_dma_get_range(np, dma_addr, paddr, size);
if (ret 0) {
dma_addr = offset = 0;
- size = dev-coherent_dma_mask;
+ size = dev-coherent_dma_mask + 1;
} else {
offset = PFN_DOWN(paddr - dma_addr);
dev_dbg(dev, dma_pfn_offset(%#08lx)\n, offset);
}
+ if (is_power_of_2(size + 1))
+ size = size + 1;
+ else if (!is_power_of_2(size)) {
+ dev_err(dev, invalid size\n);
+ return;
+ }
+
dev-dma_pfn_offset = offset;
coherent = of_dma_is_coherent(np);
--
1.7.9.5
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[PATCH 2/6] mfd: qcom,tcsr: Add device tree binding for TCSR
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/mfd/qcom,tcsr.txt | 22
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 000..e90519d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and
status
+functions for their peripherals. This node is intended to allow access to
these
+registers via syscon.
+
+Required properties:
+- compatible: Should contain:
+ qcom,tcsr-ipq8064, syscon for IPQ8064
+ qcom,tcsr-apq8064, syscon for APQ8064
+ qcom,tcsr-msm8660, syscon for MSM8660
+ qcom,tcsr-msm8960, syscon for MSM8960
+ qcom,tcsr-msm8974, syscon for MSM8974
+ qcom,tcsr-apq8084, syscon for APQ8084
+ qcom,tcsr-msm8916, syscon for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+ tcsr: syscon@1a40 {
+ compatible = qcom,tcsr-msm8960, syscon;
+ reg = 0x1a40 0x100;
+ };
--
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[PATCH v5 6/8] PCI: update dma configuration from DT
If there is a DT node available for the root bridge's parent device, use the dma configuration from that device node. For example, keystone PCI devices would require dma_pfn_offset to be set correctly in the device structure of the pci device in order to have the correct dma mask. The DT node will have dma-ranges defined for this. Also support using the DT property dma-coherent to allow coherent DMA operation by the PCI device. This patch use the new helper function of_pci_dma_configure() to update the device dma configuration. Cc: Joerg Roedel j...@8bytes.org Cc: Grant Likely grant.lik...@linaro.org Cc: Rob Herring robh...@kernel.org Cc: Will Deacon will.dea...@arm.com Cc: Russell King li...@arm.linux.org.uk Cc: Arnd Bergmann a...@arndb.de Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Acked-by: Bjorn Helgaas bhelg...@google.com Signed-off-by: Murali Karicheri m-kariche...@ti.com --- drivers/pci/probe.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 23212f8..d7dcd6c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -6,6 +6,7 @@ #include linux/delay.h #include linux/init.h #include linux/pci.h +#include linux/of_pci.h #include linux/pci_hotplug.h #include linux/slab.h #include linux/module.h @@ -1520,6 +1521,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev-dev.dma_mask = dev-dma_mask; dev-dev.dma_parms = dev-dma_parms; dev-dev.coherent_dma_mask = 0xull; + of_pci_dma_configure(dev); pci_set_dma_max_seg_size(dev, 65536); pci_set_dma_seg_boundary(dev, 0x); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 8/8] of: limit dma_mask of the device based on dma-range size
limit the device dma_mask to the min of default dma_mask and mask calculate from the dma-range size. Cc: Joerg Roedel j...@8bytes.org Cc: Grant Likely grant.lik...@linaro.org Cc: Rob Herring robh...@kernel.org Cc: Bjorn Helgaas bhelg...@google.com Cc: Will Deacon will.dea...@arm.com Cc: Russell King li...@arm.linux.org.uk Cc: Arnd Bergmann a...@arndb.de Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Signed-off-by: Murali Karicheri m-kariche...@ti.com --- drivers/of/device.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/of/device.c b/drivers/of/device.c index 17504f4..bcb8a35 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -128,6 +128,9 @@ void of_dma_configure(struct device *dev, struct device_node *np) dev_dbg(dev, device is%sbehind an iommu\n, iommu ? : not ); + /* limit dma_mask to the lower of the two values */ + *dev-dma_mask = min((*dev-dma_mask), (dma_addr + size - 1)); + arch_setup_dma_ops(dev, dma_addr, size, iommu, coherent); } EXPORT_SYMBOL_GPL(of_dma_configure); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 5/8] of/pci: add of_pci_dma_configure() update dma configuration
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device. Use the newly added APIs
pci_get/put_host_bridge_device() for implementing this.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Bjorn Helgaas bhelg...@google.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/of/of_pci.c| 19 +++
include/linux/of_pci.h |5 +
2 files changed, 24 insertions(+)
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 88471d3..0f1dd0b 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -2,6 +2,7 @@
#include linux/export.h
#include linux/of.h
#include linux/of_address.h
+#include linux/of_device.h
#include linux/of_pci.h
#include linux/slab.h
@@ -229,6 +230,24 @@ parse_failed:
return err;
}
EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+
+/**
+ * of_pci_dma_configure - Setup DMA configuration
+ * @dev: ptr to pci_dev struct of the pci device
+ *
+ * Function to update PCI devices's DMA configuration using the same
+ * info from the OF node of root host bridge's parent.
+ */
+void of_pci_dma_configure(struct pci_dev *pci_dev)
+{
+ struct device *dev = pci_dev-dev;
+ struct device *bridge = pci_get_host_bridge_device(pci_dev);
+
+ of_dma_configure(dev, bridge-parent-of_node);
+ pci_put_host_bridge_device(bridge);
+}
+EXPORT_SYMBOL_GPL(of_pci_dma_configure);
+
#endif /* CONFIG_OF_ADDRESS */
#ifdef CONFIG_PCI_MSI
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index ce0e5ab..8f1741f 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -16,6 +16,7 @@ int of_pci_get_devfn(struct device_node *np);
int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin);
int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
int of_get_pci_domain_nr(struct device_node *node);
+void of_pci_dma_configure(struct pci_dev *pci_dev);
#else
static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct
of_phandle_args *out_irq)
{
@@ -50,6 +51,10 @@ of_get_pci_domain_nr(struct device_node *node)
{
return -1;
}
+
+static inline void of_pci_dma_configure(struct pci_dev *pci_dev)
+{
+}
#endif
#if defined(CONFIG_OF_ADDRESS)
--
1.7.9.5
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[PATCH 4/6] ARM: DT: ipq8064: Add TCSR support
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146..e47358d 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -119,7 +119,7 @@
};
gsbi2: gsbi@1248 {
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-ipq8064;
reg = 0x1248 0x100;
clocks = gcc GSBI2_H_CLK;
clock-names = iface;
@@ -128,6 +128,9 @@
ranges;
status = disabled;
+ qcom,gsbi-num = 2;
+ syscon-tcsr = tcsr;
+
serial@1249 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x1249 0x1000,
@@ -154,7 +157,7 @@
};
gsbi4: gsbi@1630 {
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-ipq8064;
reg = 0x1630 0x100;
clocks = gcc GSBI4_H_CLK;
clock-names = iface;
@@ -163,6 +166,9 @@
ranges;
status = disabled;
+ qcom,gsbi-num = 4;
+ syscon-tcsr = tcsr;
+
serial@1634 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x1634 0x1000,
@@ -188,7 +194,7 @@
};
gsbi5: gsbi@1a20 {
- compatible = qcom,gsbi-v1.0.0;
+ compatible = qcom,gsbi-ipq8064;
reg = 0x1a20 0x100;
clocks = gcc GSBI5_H_CLK;
clock-names = iface;
@@ -197,6 +203,9 @@
ranges;
status = disabled;
+ qcom,gsbi-num = 5;
+ syscon-tcsr = tcsr;
+
serial@1a24 {
compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
reg = 0x1a24 0x1000,
@@ -279,5 +288,10 @@
#clock-cells = 1;
#reset-cells = 1;
};
+
+ tcsr: syscon@1a40 {
+ compatible = qcom,tcsr-ipq8064, syscon;
+ reg = 0x1a40 0x100;
+ };
};
};
--
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