[PATCH v4 2/4] Documentation: dt-bindings: add dt binding info for hi6220
Signed-off-by: Zhangfei Gao
---
.../devicetree/bindings/usb/hi6220-usb.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..b3a7b5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,49 @@
+Hisilicon hi6220 SoC USB controller
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: "hisilicon,hi6220-usb"
+Refer to dwc2.txt for dwc2 usb properties
+
+
+PHY:
+-
+
+Required properties:
+- compatible: "hisilicon,hi6220-usb-phy"
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle and clock specifier of the PHY clock.
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,vbus-gpios: gpio of detecting vbus.
+- hisilicon,id-gpios: gpio of detecting id.
+
+Example:
+
+ sys_ctrl: syscon@f703 {
+ compatible = "hisilicon,sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x1000>;
+ };
+
+ usb_phy: usb-phy {
+ compatible = "hisilicon,hi6220-usb-phy";
+ vcc-supply = <&fixed_5v_hub>;
+ hisilicon,vbus-gpios = <&gpio2 6 0>;
+ hisilicon,id-gpios = <&gpio2 5 0>;
+ hisilicon,peripheral-syscon = <&sys_ctrl>;
+ clocks = <&clock_sys HI6220_USBOTG_HCLK>;
+ };
+
+ usb: usb@f72c {
+ compatible = "hisilicon,hi6220-usb";
+ reg = <0x0 0xf72c 0x0 0x4>;
+ phys = <&usb_phy>;
+ dr_mode = "otg";
+ g-use-dma;
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128>;
+ interrupts = <0 77 0x4>;
+ };
--
1.9.1
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[PATCH v4 3/4] usb: dwc2: platform: add hi6220 support
Signed-off-by: Zhangfei Gao
---
drivers/usb/dwc2/platform.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index ae095f0..f7c67db 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -50,6 +50,35 @@
static const char dwc2_driver_name[] = "dwc2";
+static const struct dwc2_core_params params_hi6220 = {
+ .otg_cap= 2,/* No HNP/SRP capable */
+ .otg_ver= 0,/* 1.3 */
+ .dma_enable = 1,
+ .dma_desc_enable= 0,
+ .speed = 0,/* High Speed */
+ .enable_dynamic_fifo= 1,
+ .en_multiple_tx_fifo= 1,
+ .host_rx_fifo_size = 512,
+ .host_nperio_tx_fifo_size = 512,
+ .host_perio_tx_fifo_size= 512,
+ .max_transfer_size = 65535,
+ .max_packet_count = 511,
+ .host_channels = 16,
+ .phy_type = 1,/* UTMI */
+ .phy_utmi_width = 8,
+ .phy_ulpi_ddr = 0,/* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0,
+ .host_support_fs_ls_low_power = 0,
+ .host_ls_low_power_phy_clk = 0,/* 48 MHz */
+ .ts_dline = 0,
+ .reload_ctl = 0,
+ .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ GAHBCFG_HBSTLEN_SHIFT,
+ .uframe_sched = 0,
+};
+
static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -129,6 +158,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
+ { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 },
{ .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
{ .compatible = "snps,dwc2", .data = NULL },
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
--
1.9.1
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[PATCH v4 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2
Add necessary dwc2 binding documentation for Hisilicon soc: hi6220 Signed-off-by: Zhangfei Gao --- Documentation/devicetree/bindings/usb/dwc2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index fd132cb..2213682 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller Required properties: - compatible : One of: - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. + - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 4/4] phy: add phy-hi6220-usb
Add usb phy controller for hi6220 platform
Signed-off-by: Zhangfei Gao
---
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-hi6220-usb.c | 306 +++
3 files changed, 316 insertions(+)
create mode 100644 drivers/phy/phy-hi6220-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..40a1ef1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -162,6 +162,15 @@ config PHY_HIX5HD2_SATA
help
Support for SATA PHY on Hisilicon hix5hd2 Soc.
+config PHY_HI6220_USB
+ tristate "hi6220 USB PHY support"
+ select USB_PHY
+ select MFD_SYSCON
+ help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver"
depends on ARCH_SUNXI && HAS_IOMEM && OF
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..ec43c2d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_TI_PIPE3)+=
phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
+obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o
obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
diff --git a/drivers/phy/phy-hi6220-usb.c b/drivers/phy/phy-hi6220-usb.c
new file mode 100644
index 000..0d9f5ac
--- /dev/null
+++ b/drivers/phy/phy-hi6220-usb.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ BIT(6)
+#define CTRL4_PICO_OGDISABLE BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL BIT(11)
+#define CTRL4_OTG_PHY_SEL BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL BIT(3)
+#define CTRL5_PICOPHY_ACAENB BIT(4)
+#define CTRL5_PICOPHY_BC_MODE BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB BIT(8)
+#define CTRL5_PICOPHY_DCDENB BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0 0x300
+#define SC_PERIPH_RSTDIS0 0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA 0x7053348c
+
+struct hi6220_priv {
+ struct usb_phy phy;
+ struct delayed_work work;
+ struct regmap *reg;
+ struct clk *clk;
+ struct regulator *vcc;
+ struct device *dev;
+ int gpio_vbus;
+ int gpio_id;
+ enum usb_otg_state state;
+};
+
+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+ struct usb_otg *otg = priv->phy.otg;
+
+ if (!otg->gadget)
+ return;
+
+ if (on)
+ usb_gadget_connect(otg->gadget);
+ else
+ usb_gadget_disconnect(otg->gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+ struct hi6220_priv *priv =
+ container_of(work, struct hi6220_priv, work.work);
+ int gpio_id, gpio_vbus;
+ enum usb_otg_state state;
+
+ if (!gpio_is_valid(priv->gpio_id) || !gpio_is_valid(priv->gpio_vbus))
+ return;
+
+ gpio_id = gpio_get_value_cansleep(priv->gpio_id);
+ gpio_vbus = gpio_get_value_cansleep(priv->gpio_vbus);
+
+ if (gpio_vbus == 0) {
+ if (gpio_id == 1)
+ state = OTG_STATE_B_PERIPHERAL;
+ else
+ state = OTG_STATE_A_HOST;
+ } else {
+ state = OTG_STATE_A_HOST;
+ }
+
+ if (priv->state != state) {
+ hi6220_start_peripheral(priv, state == OTG_STATE_B_PERIPHERAL);
+ priv->state = state;
+ }
+}
+
+static irqreturn_t hiusb_gpio_intr(int irq, void *data)
+{
+ struct hi6220_priv *priv = (struct hi6220_priv *)data;
+
+ /* add debounce time *
[PATCH v4 0/4] add usb support for hi6220
v4: Move drivers/usb/phy/phy-hi6220-usb.c to drivers/phy/phy-hi6220-usb.c, required by Balbi. Modify dt bindings per comments from Mark and Sergei v3: fix typo and add -EPROBE_DEFER of regulator, pointed by Peter v2: address comments from Sergei and Peter add hi6220_phy_setup(false) code v1: hi6220 usb controller is inherited from dwc2 add phy accordingly support otg gadget/host Zhangfei Gao (4): Documentation: dt-bindings: add dt binding info for hi6220 dwc2 Documentation: dt-bindings: add dt binding info for hi6220 usb: dwc2: platform: add hi6220 support phy: add phy-hi6220-usb Documentation/devicetree/bindings/usb/dwc2.txt | 1 + .../devicetree/bindings/usb/hi6220-usb.txt | 49 drivers/phy/Kconfig| 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-hi6220-usb.c | 306 + drivers/usb/dwc2/platform.c| 30 ++ 6 files changed, 396 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt create mode 100644 drivers/phy/phy-hi6220-usb.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/7] OPP: Introduce OPP bindings V2 and supporting code
On 12 February 2015 at 08:52, Stephen Boyd wrote: > Here's some feedback on how we can't use OPPs (and OPPs in DT) on > qcom platforms. > > On these platforms the OPPs are not always frequency voltage > pairs. Sometimes they're a frequency voltage voltage triplet, or So, making opp-microvolt an array of , values should fix this? Do we also need a opp-microvolt-names array as well? or can we reused similar ones from the CPU node where regulator are defined. > frequency voltage current triplet. I know that the OPP framework so we do need opp-milliamp here.. > in the kernel doesn't support more than frequency voltage pairs, > but that doesn't mean it can't in the future, and if it needs to > do so the DT bindings shouldn't need a v3 revision. Sure. > Furthermore, we have a large number of OPP sets that apply to > different speed bins and silicon characteristics of the SoC. In > our systems we read some efuses (an eeprom of sorts) that tell us > to use a certain set of OPPs because the silicon is so fast or > has these certain characteristics. The bootloader is *not* > reading these fuses and populating OPPs in DT. So right now we > just put all these custom OPPish tables in DT and then pick the > right one based on a node name match constructed from the bits we > read in the efuses. How can we express this in DT with these > bindings? What about keeping things as is in DT and disabling the OPPs which you don't support at boot? And only keep enabled the set of OPPs that you want to use based on these efuses ? > For example, on msm8974 we have a frequency voltage current > triplet and there are 18 different sets of these triplets, each > with 23 triplets per set. We could encode all of these tables as > a bunch of nodes with compatible = "operating-points-v2" but how > do we pick the right one to assign and populate for the CPU > devices? Do we need some sort of opp-fuse-map table that encodes > the information we want somewhere? Probably add all these groups in a single OPP descriptor and enable/disable them at runtime.. > qcom,opp-fuse-map = , > ... > > but where do we put it? In the cpus node? Or maybe we can keep > doing the node name matching? That would required dropping the > oppN convention. Probably this might not be required then ? > Or take msm8916 as another example. On this device the voltage > for a few frequencies comes from the efuses and then we > interpolate the rest of the frequency voltage pairs. The speed > bins are picked from another set of efuses so we can do the > interpolation. Unfortunately we don't encode the frequency in the > fuses, so we rely on a handful of tables being defined somewhere > so that we know speed bin 0 means this set of frequencies and > speed bin 1 means this set of frequencies. How do we encode this > in DT? Should we have the frequencies as OPPs and leave the > voltage part out, filling it in at runtime based on what we read Maybe yes. > out of the efuses? I assume it's desirable to have the frequency > tables in DT but we could also have them in the driver and if we > did that there wouldn't be any shared-opp property to set and > have the cpufreq-dt driver use to figure out clock sharing. Probably better keep them in DT. But for platforms with dynamic OPPs only, we will surely provide some API to make OPPs shared at runtime too.. > Also sometimes we need to correlate OPPs between each other. For > example on msm8960/apq8064 if the CPU is running at a frequency > and voltage, the L2 needs to be running at another frequency, > voltage, and voltage (triplet). The L2 is in two power domains > but it only has one clock. Can/should this be expressed in DT? It Not sure. > certainly seems that it's at least easier to add it on as a > feature because OPPs are nodes instead of an array. But we need It wouldn't be a great idea to make these nodes too large just to support some corner cases, and we better try to find the best way out. But if we need it this way, we need it this way :) > to make sure we can support multiple regulators somehow, either > through correlated OPPs and multiple OPPs for a single device or > by being able to say opp-0-microvolt, opp-1-microvolt. I would an array would be better. > guess something similar could happen if there were two clocks and > one regulator although I've never seen such a scenario in > practice. Isn't this common? A single regulator voltage supporting multiple clock rates? Or did I misunderstood it :) We can have separate OPP nodes in this case. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [Patch V4 00/10] ASoC: QCOM: Add support for ipq806x SOC
On 2/11/2015 6:53 PM, Mark Brown wrote: On Wed, Feb 11, 2015 at 05:05:52PM -0800, Kenneth Westfield wrote: Replacing DSP-based drivers with LPASS-based drivers would be something that should be handled by Kconfig selections. For the DT, the DSP-related No, it shouldn't be. We should have the ability to build a single kernel image which will run on many systems, including both your system with a DSP and other systems without. Is there expectation that DTB flashed onto the system would define nodes to bind with both LPASS-based driver and DSP-based driver? I hope not as we want to keep LPASS-based driver & DSP-based driver mutually exclusive. nodes and the LPASS-related nodes shouldn't overlap. There should be a DSP-based DT binding and a separate LPASS-based DT binding. Tying one or the other to the sound node (but not both), should work. The selection of DSP use sounds like something which isn't part of the description of the hardware but rather a runtime policy decision (at least in so far as non-DSP is ever an option). Put aside IPQ8064, I would say it is actually more of build time policy decision for QC SoCs with DSP. XPU is programmed by trust zone to allow certain LPASS registers to be accessed by the chosen processor. If ADSP and app processor would have to have access to audio interfaces and DMA, resources partition(i.e # of DMAs go to ADSP while rest of DMA go to app processor is decided after analyzing expected concurrency use case. For case of 8016, MDSP would simply expect it has access to all audio subsystem except digital core of CODEC. Thanks Patrick -- Patrick Lai Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/8] arm64: Add the support for new Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset is based on linux-samsung.git (branch: for-next).
Depends on:
- Exynos5433 clock controller patch-set[1][2] was merged by Sylwester Nawrocki,
(http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/,
branch:for-v3.20/clk/next)
- Exynos5433 UART patch[4] was merged by GregKH.
[1] [PATCH v5 00/13] clk: samsung: Add the support for exynos5433 clocks
- https://lkml.org/lkml/2015/2/2/368
[2] [PATCH v3 0/9] clk: samsung: Add clocks for remaining domains of Exynos5433
- https://lkml.org/lkml/2015/2/2/784
[3] [PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
[4] serial: samsung: Add the support for Exynos5433 SoC
-
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=31ec77aca72ee5920ed3ec3d047734dc0bc43342
Changelog:
Changes from v2:
(https://lkml.org/lkml/2014/12/2/134)
- Exynos5444 DTS modification
: Fix the range of GICC memory map (0x1000 -> 0x2000)
: Fix address space of 'range' property under 'soc' node
: Add ADMA / I2S dt node for sound playback/capture
- Select ARM_AMBA/ARM_GIC/HAVE_S3C_RTC for Exynos5433 in arch/arm64/Kconfig
- Send separate patch-set for Exynos5433 clock controller[1][2] and pinctrl[3]
Changes from v1:
(https://lkml.org/lkml/2014/11/27/92)
- Merge two patches (patch2, patch3) to solve incomplete description
- Exynos5433 Clock driver
: Fix wrong register and code clean by using space instead of tab
: Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system
control register
: Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain
- Exynos5433 SoC DTS
: Remove un-supported properties of arch_timer
: Remove 'clock-frequency' property from 'cpus' dt node
: Fix interrupt type from edge rising triggering to level high triggering
because Cortex-A53/A57 use level triggering.
: Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit
SoC
: Modify 'fin_pll' dt node to remove un-needed and ugly code
: Move 'chipid' dt node under 'soc'
: Use lowercase on all case in exynos5433.dtsi
: Add PSCI dt node for secondary cpu boot
: Add 'samsung,exynos5433' compatible to MCT dt node
- Divide pinctrl patch from this patchset
- Add new following patches:
: clocksource: exynos_mct: Add the support for Exynos 64bit SoC
: arm64: Enable Exynos5433 SoC in the defconfig
Chanwoo Choi (5):
arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
arm64: dts: exynos: Add PMU dt node for Exynos5433
arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC
Inha Song (2):
arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC
arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/arm/samsung/pmu.txt| 1 +
arch/arm64/Kconfig | 13 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 911 +
4 files changed, 1623 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
--
1.8.5.5
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[PATCH v3 5/8] arm64: dts: exynos: Add PMU dt node for Exynos5433
This patch adds PMU (Power Management Unit) dt node for Exynos5433 SoC and
set the source clock for CLKOUT register as xxti .
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
[ideal.song: Add the setting of CLKOUT register]
Signed-off-by: Inha Song
Acked-by: Inki Dae
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi| 8
2 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b2113..a87fc43 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+ - "samsung,exynos5433-pmu" - for Exynos5433 SoC.
- "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 5477630..0168786 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -844,6 +844,14 @@
status = "disabled";
};
+ pmu_system_controller: system-controller@105c {
+ compatible = "samsung,exynos5433-pmu", "syscon";
+ reg = <0x105c 0x5008>;
+ #clock-cells = <1>;
+ clock-names = "clkout16";
+ clocks = <&xxti>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff04>,
--
1.8.5.5
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[PATCH v3 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC
This patch adds RTC (Real Time Clock) dt node for Exynos5433 SoC and adds
ADC dt node for Exynos5433 SoC. The c1b501564c98a94b4(iio: adc: exynos_adc:
Add support for exynos7) commit supports the ADC for Exynos7. Exynos5433's ADC
IP is the same with Exynos7's ADC IP. Exynos5433 has a little different from
ADCv2 on ADC_CON2 register. Exynos5433 don't contain OSEL/ESEL /HIGHF of
ADC_CON2.
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0168786..8e9ca8d 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -852,6 +852,24 @@
clocks = <&xxti>;
};
+ rtc: rtc@1059 {
+ compatible = "samsung,exynos3250-rtc";
+ reg = <0x1059 0x100>;
+ interrupts = <0 385 0>, <0 386 0>;
+ status = "disabled";
+ };
+
+ adc: adc@14d1 {
+ compatible = "samsung,exynos7-adc";
+ reg = <0x14d1 0x100>;
+ interrupts = <0 438 0>;
+ clock-names = "adc";
+ clocks = <&cmu_peric CLK_PCLK_ADCIF>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff04>,
--
1.8.5.5
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[PATCH v3 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433
From: Jaehoon Chung
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Jaehoon Chung
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 2cc1375..a151584 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,9 @@
i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10;
i2c11 = &hsi2c_11;
+ mshc0 = &mshc_0;
+ mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
};
cpus {
@@ -683,6 +686,45 @@
status = "disabled";
};
+ mshc_0: mshc@1554 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 225 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1554 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC0>,
+<&cmu_fsys CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_1: mshc@1555 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 226 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1555 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC1>,
+<&cmu_fsys CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_2: mshc@1556 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 227 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1556 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC2>,
+<&cmu_fsys CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff04>,
--
1.8.5.5
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[PATCH v3 4/8] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a151584..5477630 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -55,6 +55,11 @@
mshc0 = &mshc_0;
mshc1 = &mshc_1;
mshc2 = &mshc_2;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ spi3 = &spi_3;
+ spi4 = &spi_4;
};
cpus {
@@ -430,6 +435,35 @@
interrupts = <1 9 0xf04>;
};
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma0: pdma@1561 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1561 0x1000>;
+ interrupts = <0 228 0>;
+ clocks = <&cmu_fsys CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@1560 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1560 0x1000>;
+ interrupts = <0 246 0>;
+ clocks = <&cmu_fsys CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
serial_0: serial@14c1 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c1 0x100>;
@@ -530,6 +564,91 @@
interrupts = <0 442 0>;
};
+ spi_0: spi@14d2 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d2 0x100>;
+ interrupts = <0 432 0>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI0>,
+<&cmu_top CLK_SCLK_SPI0_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
+
+ spi_1: spi@14d3 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d3 0x100>;
+ interrupts = <0 433 0>;
+ dmas = <&pdma0 11>, <&pdma0 10>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI1>,
+<&cmu_top CLK_SCLK_SPI1_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
+
+ spi_2: spi@14d4 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d4 0x100>;
+ interrupts = <0 434 0>;
+ dmas = <&pdma0 13>, <&pdma0 12>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI2>,
+<&cmu_top CLK_SCLK_SPI2_PERIC>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+
[PATCH v3 8/8] arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC
From: Inha Song
This patch adds I2S device tree node for Exynos5433 SoC.
In Exynos5433 SoC, I2S0 is used for audio interface.
Cc: Kukjin Kim
Signed-off-by: Inha Song
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 7bf4dcf..807ad8e 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -511,6 +511,23 @@
status = "disabled";
};
+ i2s0: i2s0@1144 {
+ compatible = "samsung,exynos7-i2s";
+ reg = <0x1144 0x100>;
+ dmas = <&adma 0 &adma 2>;
+ dma-names = "tx", "rx";
+ interrupts = <0 70 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
+<&cmu_aud CLK_SCLK_AUD_I2S>,
+<&cmu_aud CLK_SCLK_I2S_BCLK>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_bus>;
+ status = "disabled";
+ };
+
pinctrl_alive: pinctrl@1058 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x1058 0x1000>;
--
1.8.5.5
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[PATCH v3 7/8] arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC
From: Inha Song
This patch adds ADMA (Advanced DMA) device tree node for Exynos5433 SoC.
In Exynos5433 SoC, ADMA is used for I2S audio interface.
Cc: Kukjin Kim
Signed-off-by: Inha Song
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 8e9ca8d..7bf4dcf 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -462,6 +462,17 @@
#dma-channels = <8>;
#dma-requests = <32>;
};
+
+ adma: adma@1142 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1142 0x1000>;
+ interrupts = <0 73 0>;
+ clocks = <&cmu_aud CLK_ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
};
serial_0: serial@14c1 {
--
1.8.5.5
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[PATCH v3 2/8] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
This patch includes following dt node to support Exynos5433 SoC:
1. Octa core for big.LITTLE architecture
- Cortex-A53 LITTLE Quad-core
- Cortex-A57 big Quad-core
- Support PSCI v0.1
2. clock controller node:
- CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
- CMU_CPIF : clocks for LLI (Low Latency Interface)
- CMU_MIF : clocks for DRAM Memory Controller
- CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS
- CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC
- CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA
- CMU_G2D : clocks for G2D/MDMA
- CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER
- CMU_AUD : clocks for Cortex-A5/BUS/AUDIO
- CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses
- CMU_G3D : clocks for 3D Graphics Engine
- CMU_GSCL : clocks for GSCALER
- CMU_APOLLO: clocks for Cortex-A53 Quad-core processor.
- CMU_ATLAS : clocks for Cortex-A57 Quad-core processor,
CoreSight and L2 cache controller.
- CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- CMU_MFC : clocks for MFC (Multi-Format Codec) IP.
- CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP.
- CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
- CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.
3. pinctrl node for GPIO:
- alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad
4. HS (High-Speed) I2C device
5. Serial device
6. ARCH timer (arm,armv8-timer)
7. Interrupt controller (arm,gic-400)
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 696
2 files changed, 1394 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000..81fe925
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
+ "gpz0-4", "gpz0-5", "gpz0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
+ samsung,pin-function = <3>;
+
[PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Chanwoo Choi Acked-by: Inki Dae --- arch/arm64/Kconfig | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 15e8e74..4fc08d1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -153,6 +153,19 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool "ARMv8 based Samsung Exynos5433" + select ARCH_EXYNOS + select ARM_AMBA + select ARM_GIC + select COMMON_CLK_SAMSUNG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/4] usb: renesas_usbhs: fix spinlock recursion by usbhsf_dma_complete()
Hi Geert-san, > > Still, that would need some better protection, as local_irq_save() disables > > interrupts only on the CPU it's running on, not on other CPUs in a > > multiprocessor system. > > I see. I will investigate this issue more. I tried this issue on v3.19 with dmac enabled, it also caused an oops. However, the log is useful to investigate this issue. This issue is caused by tx_complete() and ncm_tx_tasklet() because the renesas_usbhs driver called usb_gadget_giveback_request with interrupts enabled. So, spin_lock_irqsave(&dev->req_lock, flags) in u_ether.c is held. So, I will submit a patch v2 as the followings. What do you think? -- Subject: [PATCH] usb: renesas_usbhs: fix spinlock suspected in a gadget complete function According to the gadget.h, a "complete" function will always be called with interrupts disabled. However, sometimes usbhsg_queue_pop() function is called with interrupts enabled. So, this function should calls local_irq_save() before this calls the usb_gadget_giveback_request(). Otherwise, there is possible to cause a spinlock suspected in a gadget complete function. Signed-off-by: Yoshihiro Shimoda --- drivers/usb/renesas_usbhs/mod_gadget.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c index e0384af..104bddf 100644 --- a/drivers/usb/renesas_usbhs/mod_gadget.c +++ b/drivers/usb/renesas_usbhs/mod_gadget.c @@ -126,11 +126,22 @@ static void usbhsg_queue_pop(struct usbhsg_uep *uep, struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep); struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep); struct device *dev = usbhsg_gpriv_to_dev(gpriv); + unsigned long flags; dev_dbg(dev, "pipe %d : queue pop\n", usbhs_pipe_number(pipe)); ureq->req.status = status; + /* +* According to the gadget.h, a "complete" function will always be +* called with interrupts disabled. However, sometimes this function +* is called with interrupts enabled. (e.g. complete a DMAC transfer or +* write data and done is set immediately when PIO.) So, this function +* should calls local_irq_save() before this calls the +* usb_gadget_giveback_request(). +*/ + local_irq_save(flags); usb_gadget_giveback_request(&uep->ep, &ureq->req); + local_irq_restore(flags); } static void usbhsg_queue_done(struct usbhs_priv *priv, struct usbhs_pkt *pkt) === oops log on v3.19 + dmac === BUG: spinlock lockup suspected on CPU#0, irq/102-e65a000/547 lock: 0xeea2dd5c, .magic: dead4ead, .owner: /-1, .owner_cpu: -1 CPU: 0 PID: 547 Comm: irq/102-e65a000 Tainted: GW 3.19.0-05634-g11371d7-dirty #55 Hardware name: Generic R8A7791 (Flattened Device Tree) Backtrace: [] (dump_backtrace) from [] (show_stack+0x18/0x1c) r6:00989680 r5:eea2dd5c r4: r3:00208040 [] (show_stack) from [] (dump_stack+0x7c/0x98) [] (dump_stack) from [] (spin_dump+0x80/0x94) r4: r3:c0671334 [] (spin_dump) from [] (do_raw_spin_lock+0x13c/0x190) r5: r4:00989680 [] (do_raw_spin_lock) from [] (_raw_spin_lock_irqsave+0x18/0x20) r9:eea2dd5c r8:eea2dd40 r7:eebaa034 r6: r5:000f r4:6113 [] (_raw_spin_lock_irqsave) from [] (eth_start_xmit+0xd0/0x37c [u_ether]) r4:eea2d800 r3: [] (eth_start_xmit [u_ether]) from [] (ncm_tx_tasklet+0x44/0x4c [usb_f_ncm]) r10:eeb87d00 r9:c06b6b00 r8: r7: r6:c0671274 r5: r4:ee0f8e00 [] (ncm_tx_tasklet [usb_f_ncm]) from [] (tasklet_action+0x94/0xf4) r5:ee0f8ee0 r4:ee0f8edc [] (tasklet_action) from [] (__do_softirq+0xec/0x220) r8:c0676098 r7:0100 r6:c0676088 r5:0030 r4:eeb86000 r3:4004 [] (__do_softirq) from [] (irq_exit+0x8c/0xfc) r10:0002 r9:6013 r8:0001 r7:ee806000 r6: r5:c0671ac8 r4: [] (irq_exit) from [] (__handle_domain_irq+0x94/0xb8) r4: r3:018e [] (__handle_domain_irq) from [] (gic_handle_irq+0x40/0x64) r8:eea2dd5c r7:eeb87de4 r6:c067c964 r5:eeb87db0 r4:f0002000 r3:eeb87db0 [] (gic_handle_irq) from [] (__irq_svc+0x40/0x54) Exception stack(0xeeb87db0 to 0xeeb87df8) 7da0: eea2dd5c aa05aa04 7dc0: eea2dd40 ee0be1c0 ee180e80 eea2dd5c eea2dd5c 6013 0002 eeb87e1c 7de0: eeb87e20 eeb87df8 c04751a4 c005586c 6013 r6: r5:6013 r4:c005586c r3:c04751a4 [] (do_raw_spin_lock) from [] (_raw_spin_lock+0x10/0x14) r9:6013 r8:ee1d3ab4 r7:eea2dd5c r6:ee180e80 r5:ee0be1c0 r4:eea2dd40 [] (_raw_spin_lock) from [] (tx_complete+0x70/0xd8 [u_ether]) [] (tx_complete [u_ether]) from [] (usb_gadget_giveback_request+0x14/0x18) r7:ee1d3a10 r6:eebaa86c r5: r4:ee0be1f4 [] (usb_gadget_giveback_request) from [] (usbhsg_queue_done+0x2c/0x30) [] (usbhsg_queue_done) from [] (usbhsf_pkt_handler+0xfc/0x114) [] (usbhsf_pkt_handler) from [] (usbhsf_dma_complete+0x20/0x58) r10: r9:0
Re: [PATCH v4 02/11] ARM: tegra: Move out nyan-generic parts out from the nyan-big DT
On 02/11/2015 06:26 PM, Andrew Bresticker wrote: > Hi Tomeu, > > On Wed, Feb 11, 2015 at 7:06 AM, Tomeu Vizoso > wrote: >> In preparation for adding the DT for the nyan-blaze board. >> >> Signed-off-by: Tomeu Vizoso > > Maybe it's worth pulling the common pinmux bits into nyan.dtsi as well? I decided to have them in the leaf DTSs so the whole output from tegra-pinmux-scripts can be stuck in there without any extra processing. I think this way we can be more certain that the pinmux in the kernel isn't diverging from what it should be. > Otherwise, > Acked-by: Andrew Bresticker Thanks, Tomeu -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v9 03/20] ARM: imx6q: clk: Add the video_27m clock
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2daef61..2b7beb8 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m",
"pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm",
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor("gpt_3m","osc",
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m",
"pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi",
"mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi",
"mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index b690cdb..25625bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS235
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_END238
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_END239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC v9 11/20] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
This patch adds Synopsys DesignWare MIPI DSI host controller driver support. Currently, the driver supports the burst with sync pulses mode only. Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository and adapt to bridge API change as the dw-hdmi driver did. * To address Philipp's comment, add a new required clock pclk and clean up clock-names. * Add driver copyright for 2015. v7->v8: * Fix the driver's Kconfig so that we may pass the allmodconfig for ARM. v6->v7: * None. v5->v6: * Make the checkpatch.pl script be happier. v4->v5: * Remove 'dsi->panel = NULL;' in dw_mipi_dsi_host_detach() to address Andrzej Hajda's comment. v3->v4: * Move the relevant dt-bindings to a separate patch to address Stefan Wahren's comment. v2->v3: * Newly introduced in v3 to address Andy Yan's comment. This is based on the i.MX MIPI DSI driver in v2. To make the Synopsys DesignWare MIPI DSI host controller driver less platform-dependant, this patch places it at the drm/bridge directory as a DRM bridge driver. drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1006 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1044 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f38bbcd..de151f2 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -3,6 +3,16 @@ config DRM_DW_HDMI depends on DRM select DRM_KMS_HELPER +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. + config DRM_PTN3460 tristate "PTN3460 DP/LVDS bridge" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d8a8cfd..5f8e9b3 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,3 +2,4 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_PTN3460) += ptn3460.o obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..0ff241e --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1006 @@ +/* + * Synopsys DesignWare(DW) MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_CFG0x0c +#define EN18_LOOSELY BIT(10) +#define COLORM_ACTIVE_LOW BIT(9) +#define SHUTD_ACTIVE_LOW BIT(8) +#define HSYNC_ACTIVE_LOW BIT(7) +#define VSYNC_ACTIVE_LOW BIT(6) +#define DATAEN_ACTIVE_LOW BIT(5) +#define DPI_COLOR_CODING_16BIT_1 (0x0 << 2) +#define DPI_COLOR_CODING_16BIT_2 (0x1 << 2) +#define DPI_COLOR_CODING_16BIT_3 (0x2 << 2) +#define DPI_COLOR_CODING_18BIT_1 (0x3 << 2) +#define DPI_COLOR_CODING_18BIT_2 (0x4 << 2) +#define DPI_COLOR_CODING_24BIT (0x5 << 2) +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DBI_CFG0x10 +#define DSI_DBIS_CMDSIZE 0x14 + +#define DSI_PCKHDL_CFG 0x18 +#define GEN_VID_RX(vid)(((vid) & 0x3) << 5) +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTN_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_VID_MODE_CFG 0x1c +#
[PATCH RFC v9 17/20] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Replace the bs[3:0]-gpios properties with the bs-gpios property.
This addresses Andrzej Hajda's comment.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* To address Thierry Reding's comments, remove several unnecessary
properties as they can be implied by the compatible string.
* Fix the compatible string.
* Remove the display-timings node from the panel node as it can be
implied by the compatible string as well.
* Remove the status property as it is unneeded.
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f1cd214..9ff4ba5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -480,6 +480,13 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
+
+ pinctrl_mipi_panel: mipipanelgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ >;
+ };
};
gpio_leds {
@@ -516,6 +523,19 @@
};
};
+&mipi_dsi {
+ status = "okay";
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi_panel>;
+ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ bs-gpios = <0>, <0>, <&gpio6 14 GPIO_ACTIVE_HIGH>, <0>;
+ };
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
--
2.1.0
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[PATCH RFC v9 07/20] ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the ipg clock's output. The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal . In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".
Signed-off-by: Liu Ying
---
v8->v9:
* Newly introduced in v9.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index cbdbe2a..909828d 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -419,6 +419,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1",
"ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx",
"hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg",
"video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg",
base + 0x74, 16, &share_count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index dbc828c..8780868 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -250,6 +250,7 @@
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_MIPI_CORE_CFG 239
-#define IMX6QDL_CLK_END240
+#define IMX6QDL_CLK_MIPI_IPG 240
+#define IMX6QDL_CLK_END241
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC v9 15/20] drm: panel: Add support for Himax HX8369A MIPI DSI panel
This patch adds support for Himax HX8369A MIPI DSI panel.
Reviewed-by: Andrzej Hajda
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* Add driver copyright for 2015.
v7->v8:
* Remove several unnecessary headers included in the driver.
v6->v7:
* Address Andrzej Hajda's following comments.
* Simplify the return logic in hx8369a_dcs_write().
* Replace the macro hx8369a_dsi_init_helper() with a function array to improve
the code quality.
* Handle error cases during getting gpios in probe().
* Add 'Reviewed-by: Andrzej Hajda '.
v5->v6:
* Make the checkpatch.pl script be happier.
* Do not set the dsi channel number to be zero in probe(), because the MIPI DSI
bus driver would set it.
v4->v5:
* Address Andrzej Hajda's comments.
* Get the bs-gpios property instead of the bs[3:0]-gpios properties.
* Implement error propagation for panel register configurations.
* Other minor changes to improve the code quality.
v3->v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2->v3:
* Sort the included header files alphabetically.
v1->v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and driver name.
* Move the driver's Makefile entry place to sort the entries alphabetically.
* Reuse several standard DCS functions instead of inventing wheels.
* Move the panel resetting and power logics to the driver probe/remove stages.
This may simplify panel prepare/unprepare hooks. The power consumption should
not change a lot at DPMS since the panel enters sleep mode at that time.
* Add the module author.
* Other minor changes, such as coding style issues.
drivers/gpu/drm/panel/Kconfig | 5 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-himax-hx8369a.c | 610
3 files changed, 616 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d845837..cd6fbb7 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes into a
low power state.
+config DRM_PANEL_HIMAX_HX8369A
+ tristate "Himax HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+
config DRM_PANEL_LD9040
tristate "LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d5dbe06 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HIMAX_HX8369A) += panel-himax-hx8369a.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8369a.c
b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
new file mode 100644
index 000..649e395
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
@@ -0,0 +1,610 @@
+/*
+ * Himax HX8369A panel driver.
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on Samsung s6e8aa0 panel driver.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define WRDISBV0x51
+#define WRCTRLD0x53
+#define WRCABC 0x55
+#define SETPOWER 0xb1
+#define SETDISP0xb2
+#define SETCYC 0xb4
+#define SETVCOM0xb6
+#define SETEXTC0xb9
+#define SETMIPI0xba
+#define SETPANEL 0xcc
+#define SETGIP 0xd5
+#define SETGAMMA 0xe0
+
+#define HX8369A_MIN_BRIGHTNESS 0x00
+#define HX8369A_MAX_BRIGHTNESS 0xff
+
+enum hx8369a_mpu_interface {
+ HX8369A_DBI_TYPE_A_8BIT,
+ HX8369A_DBI_TYPE_A_9BIT,
+ HX8369A_DBI_TYPE_A_16BIT,
+ HX8369A_DBI_TYPE_A_18BIT,
+ HX8369A_DBI_TYPE_B_8BIT,
+ HX8369A_DBI_TYPE_B_9BIT,
+ HX8369A_DBI_TYPE_B_16BIT,
+ HX8369A_DBI_TYPE_B_18BIT,
+ HX8369A_DSI_CMD_MODE,
+ HX8369A_DBI_TYPE_B_24BIT,
+ HX8369A_DSI_VIDEO_MODE,
+ HX8369A_MDDI,
+ HX8369A_DPI_DBI_TYPE_C_OPT1,
+ HX8369A_DPI_DBI_TYPE_C_OPT2,
+ HX8369A_DPI_DBI_TYPE_C_OPT3
+};
+
+enum hx8369a_resolution {
+ HX8369A_RES_480_864,
+ HX8369A_RES_480_854,
+ HX8369A_RES_480_800,
+ HX8369A_RES_480_640,
+ HX8369A_RES_36
[PATCH RFC v9 14/20] Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver
This patch adds device tree bindings for Himax HX8369A DRM panel driver.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Merge the bs[3:0]-gpios properties into one property - bs-gpios.
This addresses Andrzej Hajda's comment.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/panel/himax,hx8369a.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..3a44b70
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,39 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: should be a panel's compatible string
+ - reg: the virtual channel number of a DSI peripheral, as described in [1]
+ - reset-gpios: a GPIO spec for the reset pin, as described in [2]
+
+Optional properties:
+ - vdd1-supply: I/O and interface power supply
+ - vdd2-supply: analog power supply
+ - vdd3-supply: logic power supply
+ - dsi-vcc-supply: DSI and MDDI power supply
+ - vpp-supply: OTP programming voltage
+ - bs-gpios: a GPIO spec for the pins BS[3:0], as described in [2]
+
+[1] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[2] Documentation/devicetree/bindings/gpio/gpio.txt
+
+Example:
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi_panel>;
+ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ bs-gpios = <0>, <0>, <&gpio6 14 GPIO_ACTIVE_HIGH>, <0>;
+ };
--
2.1.0
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[PATCH RFC v9 13/20] drm: imx: Support Synopsys DesignWare MIPI DSI host controller
This patch adds support for Synopsys DesignWare MIPI DSI host controller
which is embedded in the i.MX6q/sdl SoCs.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* Add driver copyright for 2015.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Make the checkpatch.pl script be happier.
v4->v5:
* None.
v3->v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2->v3:
* To address Andy Yan's comments, move the common Synopsys DesignWare MIPI DSI
host controller logic into it's drm/bridge driver and leave the i.MX specific
logic only.
v1->v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node in the panel
node.
* Update the DT documentation to state that the nodes which represent the
possible
DRM CRTCs the controller may connect with should be placed in the node
"ports".
* Remove the flag 'enabled' from the struct imx_mipi_dsi.
* Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver.
* Improve the way we wait for check status for DPHY and command packet
transfer.
* Improve the DPMS support for the encoder.
* Split the functions of ->host_attach() and ->mode_valid() clearly as
suggested by
Thierry Reding.
* Improve the logics in imx_mipi_dsi_dcs_long_write().
* Enable/disable the pllref_clk and pllref_gate_clk at the component
binding/unbinding
stages to help remove the flag 'enabled'.
* Update the module license to be "GPL".
* Other minor changes, such as coding style issues and macro naming issues.
drivers/gpu/drm/imx/Kconfig | 7 ++
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 ++
3 files changed, 238 insertions(+)
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 33cdddf..7faeb49 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -53,3 +53,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX_MIPI_DSI
+ tristate "Freescale i.MX DRM MIPI DSI"
+ select DRM_DW_MIPI_DSI
+ depends on DRM_IMX
+ help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index f3ecd89..93919b4 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
obj-$(CONFIG_DRM_IMX_IPUV3)+= imx-ipuv3-crtc.o
obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_MIPI_DSI) += dw_mipi_dsi-imx.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
new file mode 100644
index 000..5e6f62d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
@@ -0,0 +1,230 @@
+/*
+ * i.MX drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "imx-drm.h"
+
+#define DRIVER_NAME"imx-mipi-dsi"
+
+struct imx_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+ regmap_update_bits(dsi->regmap, IOMUXC_GPR3,
+ IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+ ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+ .destroy = imx_drm_encoder_destroy,
+};
+
+static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void imx_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(en
[PATCH RFC v9 02/20] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field shift bits. Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7->v8: * None. v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c877cad..d16f4c8 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -207,6 +207,7 @@ #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v9 00/20] Add support for i.MX MIPI DSI DRM driver
Hi, This version mainly addresses the comments from Philipp Zabel on v8. The comments include a. A common compatible string "snps,dw-mipi-dsi" should be appended to all SoCs' MIPI DSI device tree documentations and nodes. b. Clean up the common clocks needed by the Synopsys DesignWare MIPI DSI host controller. This version also drops two documentation patches in v8 for adding Himax and Truly vendor prefixes since Rob Herring has taken them. The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a i.MX MIPI DSI specific DRM driver. Currently, the MIPI DSI drivers only support the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/20 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the imx-drm/next branch of Philipp Zabel's open git repository. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (20): clk: divider: Correct parent clk round rate if no bestdiv is normally found ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver drm: imx: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 39 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 30 +- arch/arm/configs/imx_v6_v7_defconfig | 23 +- arch/arm/mach-imx/clk-imx6q.c |8 +- drivers/clk/clk-divider.c |3 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1006 drivers/gpu/drm/imx/Kconfig|7 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 + drivers/gpu/drm/panel/Kconfig |5 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-himax-hx8369a.c| 610 include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/i
[PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
drivers/clk/clk-divider.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ MULT_ROUND_UP(rate, bestdiv));
}
return bestdiv;
--
2.1.0
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[PATCH RFC v9 04/20] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
clock's parent should be the video_27m clock. The i.MX6DL reference manual
has the same statement. This patch changes the hdmi_isfr clock's parent
from the pll3_pfd1_540m clock to the video_27m clock.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2b7beb8..0dbc79a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -401,7 +401,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core",
"gpu2d_core_podf", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core",
"gpu3d_core_podf", base + 0x6c, 26);
clk[IMX6QDL_CLK_HDMI_IAHB]= imx_clk_gate2("hdmi_iahb", "ahb",
base + 0x70, 0);
- clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2("hdmi_isfr",
"pll3_pfd1_540m",base + 0x70, 4);
+ clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2("hdmi_isfr",
"video_27m", base + 0x70, 4);
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1",
"ipg_per", base + 0x70, 6);
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2",
"ipg_per", base + 0x70, 8);
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3",
"ipg_per", base + 0x70, 10);
--
2.1.0
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[PATCH RFC v9 06/20] ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock. In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Add two spaces in the clock driver to eliminate two errors reported by
the checkpatch.pl script.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 049e922..cbdbe2a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -418,6 +418,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1",
"ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1",
"ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx",
"hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg",
"video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index 25625bf..dbc828c 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -249,6 +249,7 @@
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_VIDEO_27M 238
-#define IMX6QDL_CLK_END239
+#define IMX6QDL_CLK_MIPI_CORE_CFG 239
+#define IMX6QDL_CLK_END240
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC v9 05/20] ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a shared clock gate.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 0dbc79a..049e922 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
+static unsigned int share_count_mipi_core_cfg;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
@@ -416,7 +417,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0",
"ldb_di0_podf", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1",
"ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1",
"ipu2_di1_sel", base + 0x74, 10);
- clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx",
"hsi_tx_podf", base + 0x74, 16);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx",
"hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
--
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[PATCH RFC v9 16/20] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
"snps,dw-mipi-dsi" should be appended.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v3->v4:
* None.
v2->v3:
* As suggested by Phillip Zabel, change the clocks and the clock-names
properties to use the pllref and core_cfg clocks only.
v1->v2:
* None.
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 55aced8..0a4d7f7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1020,7 +1020,14 @@
mipi_dsi: mipi@021e {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi",
"snps,dw-mipi-dsi";
reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
status = "disabled";
ports {
--
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[PATCH RFC v9 20/20] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel
This patch adds support for Himax HX8369A panel. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the Himax HX8369A panel driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7->v8: * None. v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * Add the HIMAX prefix in the Kconfig name. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 9e650e8f..52d70a1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -197,6 +197,7 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_HIMAX_HX8369A=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v9 19/20] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the MIPI DSI host controller driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7->v8: * None. v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index ec4b255..9e650e8f 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -203,6 +203,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_MIPI_DSI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v9 08/20] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device. This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Acked-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Add Philipp's Ack.
v1->v2:
* Newly added, as suggested by Thierry Reding.
arch/arm/boot/dts/imx6q.dtsi | 20 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 23 ++-
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6..e152e6e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -292,19 +292,21 @@
};
&mipi_dsi {
- port@2 {
- reg = <2>;
+ ports {
+ port@2 {
+ reg = <2>;
- mipi_mux_2: endpoint {
- remote-endpoint = <&ipu2_di0_mipi>;
+ mipi_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_mipi>;
+ };
};
- };
- port@3 {
- reg = <3>;
+ port@3 {
+ reg = <3>;
- mipi_mux_3: endpoint {
- remote-endpoint = <&ipu2_di1_mipi>;
+ mipi_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_mipi>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2109d07..55aced8 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1023,19 +1023,24 @@
reg = <0x021e 0x4000>;
status = "disabled";
- port@0 {
- reg = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
- mipi_mux_0: endpoint {
- remote-endpoint =
<&ipu1_di0_mipi>;
+ mipi_mux_0: endpoint {
+ remote-endpoint =
<&ipu1_di0_mipi>;
+ };
};
- };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- mipi_mux_1: endpoint {
- remote-endpoint =
<&ipu1_di1_mipi>;
+ mipi_mux_1: endpoint {
+ remote-endpoint =
<&ipu1_di1_mipi>;
+ };
};
};
};
--
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[PATCH RFC v9 18/20] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging
The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository, so the patch content is different from v8. v7->v8: * None. v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 21 + 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 7c2075a..ec4b255 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -54,7 +54,6 @@ CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_BINFMT_MISC=m -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_NET=y @@ -163,13 +162,13 @@ CONFIG_SPI_IMX=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MC9S08DZ60=y CONFIG_GPIO_STMPE=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_IMX=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_IMX=y CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y @@ -198,7 +197,12 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -257,13 +261,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v9 12/20] Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver
This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI
driver.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
"snps,dw-mipi-dsi" should be appended.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless pllref_gate clock from the required clocks, clock-names
property.
v4->v5:
* None.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..4bd8451
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,81 @@
+i.MX specific Device-Tree bindings for Synopsys DesignWare MIPI DSI host
controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+The common device tree documentation for this controller can be found
+at [1].
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. And, a common compatible string "snps,dw-mipi-dsi"
+ should be appended.
+ - reg: Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: The controller's interrupt number to the CPU(s).
+ - gpr: Should be <&gpr>.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as described
+ in [2] and [3].
+
+Required sub-nodes:
+ - ports: This node may contain up to four port nodes with endpoint
+ definitions as defined in [4], corresponding to the four inputs to
+ the controller multiplexer.
+ - A node to represent a DSI peripheral as described in [5].
+
+[1] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt.
+[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[3] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[4] Documentation/devicetree/bindings/media/video-interfaces.txt
+[5] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
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[PATCH RFC v9 10/20] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
"snps,dw-mipi-dsi" should be appended for all SoCs.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless input-port properties from the example port@0 and port@1
nodes.
v4->v5:
* None.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..bb87466
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.1.0
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[PATCH RFC v9 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Signed-off-by: Liu Ying
---
v8->v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
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[Patch v4 1/2] dt/bindings: qcom_adm: Fix channel specifiers
This patch removes the crci information from the dma channel property. At least one client device requires using more than one CRCI value for a channel. This does not match the current binding and the crci information needs to be removed. Instead, the client device will provide this information via other means. Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt index 9bcab91..38d45f8 100644 --- a/Documentation/devicetree/bindings/dma/qcom_adm.txt +++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt @@ -4,8 +4,7 @@ Required properties: - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 - reg: Address range for DMA registers - interrupts: Should contain one interrupt shared by all channels -- #dma-cells: must be <2>. First cell denotes the channel number. Second cell - denotes CRCI (client rate control interface) flow control assignment. +- #dma-cells: must be <1>. First cell denotes the channel number. - clocks: Should contain the core clock and interface clock. - clock-names: Must contain "core" for the core clock and "iface" for the interface clock. @@ -22,7 +21,7 @@ Example: compatible = "qcom,adm"; reg = <0x1830 0x10>; interrupts = <0 170 0>; - #dma-cells = <2>; + #dma-cells = <1>; clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; clock-names = "core", "iface"; @@ -35,15 +34,12 @@ Example: qcom,ee = <0>; }; -DMA clients must use the format descripted in the dma.txt file, using a three +DMA clients must use the format descripted in the dma.txt file, using a two cell specifier for each channel. -Each dmas request consists of 3 cells: +Each dmas request consists of two cells: 1. phandle pointing to the DMA controller 2. channel number - 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. -The CRCI is used for flow control. It identifies the peripheral device that -is the source/destination for the transferred data. Example: @@ -56,7 +52,7 @@ Example: cs-gpios = <&qcom_pinmux 20 0>; - dmas = <&adm_dma 6 9>, - <&adm_dma 5 10>; + dmas = <&adm_dma 6>, + <&adm_dma 5>; dma-names = "rx", "tx"; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v4 0/2] Add Qualcomm ADM dmaengine driver
This patch set introduces the dmaengine driver for the Qualcomm Application Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064 devices. The initial version of this driver will only support slave DMA operations between system memory and peripherals. Flow control via the CRCI (client rate control interface) is supported and can be configured via device tree configuration. Flow control usage is required for some peripheral devices. Changes from v3: - Remove .owner field Changes from v2: - Removed extraneous achan variable from xlate function - Reworked crci check in slave_sg function - Added mux field to async_desc structure. - Reworked dma start function to use crci and mux values directly from structure. - Added disable of clocks in probe error paths. - Changed to use #define for fixed number of channels. Changes since v1: - Fixed various review comments - Fixed some descriptor programming issues. - Added single descriptors to support sub burst length transactions. Selection of single or box descriptors depends on the sg length and burst size. - Removed use of crci in the dmas property. CRCI is now designated via the slave_config structure and will be stored in slave_id. Andy Gross (2): dt/bindings: qcom_adm: Fix channel specifiers dmaengine: Add ADM driver Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 +- drivers/dma/Kconfig| 10 + drivers/dma/Makefile |1 + drivers/dma/qcom_adm.c | 901 4 files changed, 918 insertions(+), 10 deletions(-) create mode 100644 drivers/dma/qcom_adm.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v4 2/2] dmaengine: Add ADM driver
Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA controller found in the MSM8x60 and IPQ/APQ8064 platforms. The ADM supports both memory to memory transactions and memory to/from peripheral device transactions. The controller also provides flow control capabilities for transactions to/from peripheral devices. The initial release of this driver supports slave transfers to/from peripherals and also incorporates CRCI (client rate control interface) flow control. Signed-off-by: Andy Gross --- drivers/dma/Kconfig| 10 + drivers/dma/Makefile |1 + drivers/dma/qcom_adm.c | 901 3 files changed, 912 insertions(+) create mode 100644 drivers/dma/qcom_adm.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..69bc15e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -464,4 +464,14 @@ config QCOM_BAM_DMA Enable support for the QCOM BAM DMA controller. This controller provides DMA capabilities for a variety of on-chip devices. +config QCOM_ADM + tristate "Qualcomm ADM support" + depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + ---help--- + Enable support for the Qualcomm ADM DMA controller. This controller + provides DMA capabilities for both general purpose and on-chip + peripheral devices. + endif diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..3b7ead6 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o diff --git a/drivers/dma/qcom_adm.c b/drivers/dma/qcom_adm.c new file mode 100644 index 000..baea945 --- /dev/null +++ b/drivers/dma/qcom_adm.c @@ -0,0 +1,901 @@ +/* + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" +#include "virt-dma.h" + +/* ADM registers - calculated from channel number and security domain */ +#define HI_CH_CMD_PTR(chan, ee)(4*chan + 0x20800*ee) +#define HI_CH_RSLT(chan, ee) (0x40 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE0(chan, ee) (0x80 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE1(chan, ee) (0xc0 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE2(chan, ee) (0x100 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE3(chan, ee) (0x140 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE4(chan, ee) (0x180 + 4*chan + 0x20800*ee) +#define HI_CH_FLUSH_STATE5(chan, ee) (0x1c0 + 4*chan + 0x20800*ee) +#define HI_CH_STATUS_SD(chan, ee) (0x200 + 4*chan + 0x20800*ee) +#define HI_CH_CONF(chan) (0x240 + 4*chan) +#define HI_CH_RSLT_CONF(chan, ee) (0x300 + 4*chan + 0x20800*ee) +#define HI_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + 0x20800*ee) +#define HI_CI_CONF(ci) (0x390 + 4*ci) +#define HI_CRCI_CONF0 0x3d0 +#define HI_CRCI_CONF1 0x3d4 +#define HI_GP_CTL 0x3d8 +#define HI_CRCI_CTL(crci, ee) (0x400 + 0x4*crci + 0x20800*ee) + +/* channel status */ +#define CH_STATUS_VALIDBIT(1) + +/* channel result */ +#define CH_RSLT_VALID BIT(31) +#define CH_RSLT_ERRBIT(3) +#define CH_RSLT_FLUSH BIT(2) +#define CH_RSLT_TPDBIT(1) + +/* channel conf */ +#define CH_CONF_MPU_DISABLEBIT(11) +#define CH_CONF_PERM_MPU_CONF BIT(9) +#define CH_CONF_FLUSH_RSLT_EN BIT(8) +#define CH_CONF_FORCE_RSLT_EN BIT(7) +#define CH_CONF_IRQ_EN BIT(6) + +/* channel result conf */ +#define CH_RSLT_CONF_FLUSH_EN BIT(1) +#define CH_RSLT_CONF_IRQ_ENBIT(0) + +/* CRCI CTL */ +#define CRCI_CTL_MUX_SEL BIT(18) +#define CRCI_CTL_RST BIT(17) + +/* CI configuration */ +#define CI_RANGE_END(x)(x << 24) +#define CI_RANGE_START(x) (x << 16) +#define CI_BURST_4_WORDS 0x4 +#define CI_BURST_8_WORDS 0x8 + +/* GP CTL */ +#define GP_CTL_LP_EN BIT(12) +#define GP_CTL_LP_CNT(x) (x << 8) + +/* Command pointer list entry */ +#define CPLE_LPBIT(31) +#define CPLE_CMD_PTR_LIST BIT(29) + +/* Command list entry */ +#def
Re: [Patch v3 2/2] dmaengine: Add ADM driver
On Wed, Feb 11, 2015 at 05:28:14PM -0800, Stephen Boyd wrote:
> On 02/11, Andy Gross wrote:
> > +static struct platform_driver adm_dma_driver = {
> > + .probe = adm_dma_probe,
> > + .remove = adm_dma_remove,
> > + .driver = {
> > + .name = "adm-dma-engine",
> > + .owner = THIS_MODULE,
> > + .of_match_table = adm_of_match,
> > + },
> > +};
>
> The THIS_MODULE script will find you. Am I a script?
darn it. I skimmed right over that. I'll resend.
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[GIT PULL] DeviceTree changes for 3.20
Hi Linus,
Please pull DeviceTree changes for 3.20. Details below.
Rob
The following changes since commit 26bc420b59a38e4e6685a73345a0def461136dce:
Linux 3.19-rc6 (2015-01-25 20:04:41 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
tags/devicetree-for-3.20
for you to fetch changes up to 3c3c8e3618b018aee1dfd42343a74f3ab5ddf23c:
Merge remote-tracking branch 'grant/devicetree/next' into for-next
(2015-02-11 21:28:45 -0600)
DeviceTree changes for 3.20:
- DT unittests for I2C probing and overlays from Pantelis Antoniou
- Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha
- Add Tegra compatible strings missing for newer parts from Paul
Walmsley
- Various vendor prefix additions
Alan Tull (1):
doc: add bindings document for altera fpga manager
Andrew Lunn (1):
DT: Vendors: Add Everspin
Arnaud Ebalard (1):
dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt
Daniel Thompson (1):
of: Fix brace position for struct of_device_id definition
Fabio Estevam (2):
of: Use ovti for Omnivision
of: Add vendor prefix for OmniVision Technologies
Gaurav Minocha (1):
Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol
George G. Davis (1):
drivers: of: Export of_reserved_mem_device_{init,release}
Grant Likely (1):
of/unittest: Remove obsolete code
Ian Molton (1):
Add AD Holdings Plc. to vendor-prefixes.
Krzysztof Kozlowski (1):
dt-bindings: Add Silicon Mitus vendor prefix
Lad, Prabhakar (1):
of/fdt: fix sparse warning
Linus Walleij (1):
pinctrl: fix up device tree bindings
Liu Ying (2):
of: Add vendor prefix for Himax Technologies Inc.
of: Add vendor prefix for Truly Semiconductors Limited
Pantelis Antoniou (1):
of: unitest: Add I2C overlay unit tests.
Paul Walmsley (3):
Documentation: DT bindings: add more Tegra chip compatible strings
Documentation: DT bindings: add nvidia, tegra132-denver compatible string
Documentation: DT: document compatible string existence requirement
Rob Herring (2):
Merge tag 'v3.19-rc6' into HEAD
Merge remote-tracking branch 'grant/devicetree/next' into for-next
Sakari Ailus (1):
of: EXPORT_SYMBOL_GPL of_property_read_u64_array
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 5 +-
.../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 6 +-
.../devicetree/bindings/ata/tegra-sata.txt | 4 +-
.../bindings/fpga/altera-socfpga-fpga-mgr.txt | 17 +
.../bindings/fuse/nvidia,tegra20-fuse.txt | 10 +-
.../bindings/gpu/nvidia,tegra20-host1x.txt | 8 +-
.../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 10 +-
.../devicetree/bindings/media/atmel-isi.txt| 2 +-
.../devicetree/bindings/media/video-interfaces.txt | 2 +-
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 9 +-
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +-
.../bindings/pci/nvidia,tegra20-pcie.txt | 8 +-
.../bindings/pinctrl/nvidia,tegra124-pinmux.txt| 3 +-
.../pinctrl/nvidia,tegra124-xusb-padctl.txt| 4 +-
.../devicetree/bindings/pinctrl/ste,nomadik.txt| 35 +-
.../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 7 +-
.../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 4 +-
.../devicetree/bindings/serial/of-serial.txt | 5 +-
.../bindings/sound/nvidia,tegra30-ahub.txt | 5 +-
.../bindings/sound/nvidia,tegra30-hda.txt | 4 +-
.../bindings/sound/nvidia,tegra30-i2s.txt | 5 +-
.../bindings/spi/nvidia,tegra114-spi.txt | 4 +-
.../devicetree/bindings/submitting-patches.txt | 23 +
.../devicetree/bindings/thermal/tegra-soctherm.txt | 4 +-
.../bindings/timer/nvidia,tegra30-timer.txt| 4 +-
Documentation/devicetree/bindings/unittest.txt | 59 +-
.../bindings/usb/nvidia,tegra20-ehci.txt | 5 +-
.../bindings/usb/nvidia,tegra20-usb-phy.txt| 5 +-
.../devicetree/bindings/vendor-prefixes.txt| 9 +-
drivers/of/Kconfig | 1 -
drivers/of/base.c | 1 +
drivers/of/fdt.c | 2 +-
drivers/of/of_reserved_mem.c | 2 +
drivers/of/unittest-data/tests-overlay.dtsi| 94
drivers/of/unittest.c | 597 -
include/linux/mod_devicetable.h| 3 +-
37 files changed, 786 insertions(+), 187 deletions(-)
create mode 100644
Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt
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More
Re: [Patch V5 02/12] ASoC: max98357a: Document MAX98357A bindings
On Wed, Feb 11, 2015 at 06:10:05PM -0800, Kenneth Westfield wrote: > From: Kenneth Westfield > > Add documentation to the sound directory of the > device-tree bindings for the Maxim MAX98357A audio > DAC. This driver has already been applied. If there are any changes to current code please send incremental patches. signature.asc Description: Digital signature
Re: [alsa-devel] [Patch V4 00/10] ASoC: QCOM: Add support for ipq806x SOC
On Wed, Feb 11, 2015 at 05:05:52PM -0800, Kenneth Westfield wrote: > Replacing DSP-based drivers with LPASS-based drivers would be something that > should be handled by Kconfig selections. For the DT, the DSP-related No, it shouldn't be. We should have the ability to build a single kernel image which will run on many systems, including both your system with a DSP and other systems without. > nodes and the LPASS-related nodes shouldn't overlap. There should be a > DSP-based DT binding and a separate LPASS-based DT binding. Tying one > or the other to the sound node (but not both), should work. The selection of DSP use sounds like something which isn't part of the description of the hardware but rather a runtime policy decision (at least in so far as non-DSP is ever an option). signature.asc Description: Digital signature
RE: [PATCH 4/4] usb: renesas_usbhs: add support for USB-DMAC
Hi Geert-san,
> Hi Shimoda-san,
>
> On Mon, Feb 9, 2015 at 9:16 AM, Yoshihiro Shimoda
> wrote:
> > Some Renesas SoCs have the USB-DMAC. It is able to terminate transfers
> > when a short packet is received, even if less bytes than the transfer
> > counter size have been received. Also, it is able to send a short
> > packet even if the packet size is not multiples of 8bytes.
> >
> > Since the previous code has used the interruption of USBHS controller
> > when receiving packets even if this driver has used a dmac, a lot of
> > interruptions has happened. This patch will reduce such interruptions.
> >
> > This patch allows to use the USB-DMAC on R-Car H2 and M2.
> >
> > Signed-off-by: Yoshihiro Shimoda
>
> > --- a/drivers/usb/renesas_usbhs/common.c
> > +++ b/drivers/usb/renesas_usbhs/common.c
>
> > @@ -487,6 +497,15 @@ static struct renesas_usbhs_platform_info
> > *usbhs_parse_dt(struct device *dev)
> > if (gpio > 0)
> > dparam->enable_gpio = gpio;
> >
> > + switch (dparam->type) {
> > + case USBHS_TYPE_R8A7790:
> > + case USBHS_TYPE_R8A7791:
> > + dparam->has_usb_dmac = 1;
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > return info;
> > }
>
> > struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
> > diff --git a/drivers/usb/renesas_usbhs/fifo.c
> > b/drivers/usb/renesas_usbhs/fifo.c
> > index 3b77a1b..1e7dc6e 100644
> > --- a/drivers/usb/renesas_usbhs/fifo.c
> > +++ b/drivers/usb/renesas_usbhs/fifo.c
>
> > @@ -847,10 +849,13 @@ static int usbhsf_dma_prepare_push(struct usbhs_pkt
> > *pkt, int *is_done)
> > usbhs_pipe_is_dcp(pipe))
> > goto usbhsf_pio_prepare_push;
> >
> > - if (len & 0x7) /* 8byte alignment */
> > + /* default: 8byte alignment */
> > + if (!usbhs_get_dparam(priv, has_usb_dmac) && len & 0x7)
> > goto usbhsf_pio_prepare_push;
>
> So the has_usb_dmac flags indicates that DMA addresses are not limited to
> 8-byte alignment.
>
> Can't this be handled by looking at a dma_mask, as set by the DMAC?
Opps, the comment "8byte alignment" is wrong.
I will fix the comment.
The USB-DMAC can send a packet that it is not multiples of 8-bytes.
The USB-DMAC needs 32-bytes alignment by the following code.
- if ((uintptr_t)(pkt->buf + pkt->actual) & 0x7) /* 8byte alignment */
+ align_mask = usbhs_get_dparam(priv, has_usb_dmac) ?
+ USBHS_USB_DMAC_XFER_SIZE - 1 : 0x7;
+ if ((uintptr_t)(pkt->buf + pkt->actual) & align_mask)
The previous code will use a dmac if a packet size is multiples of 8-bytes and
it is 8-bytes alignment.
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
N�r��yb�X��ǧv�^�){.n�+���z��z��z)w* jg��� �ݢj/���z�ޖ��2�ޙ&�)ߡ�a���� �G���h��j:+v���w��٥
Re: [PATCH v2 1/2] mmc: dw_mmc: fix bug that cause 'Timeout sending command'
Hi Andrzej and Alim
On 2015/2/12 07:20, Alim Akhtar wrote:
> Hi Andrzej,
>
> On Wed, Feb 11, 2015 at 5:28 PM, Andrzej Hajda wrote:
>> Hi Alim,
>>
>> On 02/11/2015 03:57 AM, Addy wrote:
>>>
>>> On 2015/02/10 23:22, Alim Akhtar wrote:
Hi Addy,
On Mon, Feb 9, 2015 at 12:55 PM, Addy Ke wrote:
> Because of some uncertain factors, such as worse card or worse hardware,
> DAT[3:0](the data lines) may be pulled down by card, and mmc controller
> will be in busy state. This should not happend when mmc controller
> send command to update card clocks. If this happends, mci_send_cmd will
> be failed and we will get 'Timeout sending command', and then system will
> be blocked. To avoid this, we need reset mmc controller.
>
> Signed-off-by: Addy Ke
> ---
> drivers/mmc/host/dw_mmc.c | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 4d2e3c2..b0b57e3 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -100,6 +100,7 @@ struct idmac_desc {
> };
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> +static int dw_mci_card_busy(struct mmc_host *mmc);
> static bool dw_mci_reset(struct dw_mci *host);
> static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>
> @@ -888,6 +889,31 @@ static void mci_send_cmd(struct dw_mci_slot *slot,
> u32 cmd, u32 arg)
> cmd, arg, cmd_status);
> }
>
> +static void dw_mci_wait_busy(struct dw_mci_slot *slot)
> +{
> + struct dw_mci *host = slot->host;
> + unsigned long timeout = jiffies + msecs_to_jiffies(500);
> +
Why 500 msec?
>>> This timeout value is the same as mci_send_cmd:
>>> static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
>>> {
>>> struct dw_mci *host = slot->host;
>>> unsigned long timeout = jiffies + msecs_to_jiffies(500);
>>>
>>> }
>>>
>>> I have not clear that which is suitable.
>>> Do you have any suggestion on it?
> + do {
> + if (!dw_mci_card_busy(slot->mmc))
> + return;
> + cpu_relax();
> + } while (time_before(jiffies, timeout));
> +
> + dev_err(host->dev, "Data busy (status %#x)\n",
> + mci_readl(slot->host, STATUS));
> +
> + /*
> +* Data busy, this should not happend when mmc controller send
> command
> +* to update card clocks in non-volt-switch state. If it
> happends, we
> +* should reset controller to avoid getting "Timeout sending
> command".
> +*/
> + dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS);
> +
Why you need to reset all blocks? may be CTRL_RESET is good enough here.
>>> I have tested on rk3288, if only reset ctroller, data busy bit will not
>>> be cleaned,and we will still get
>>>
>>> "Timeout sending command".
>>>
> + /* Fail to reset controller or still data busy, WARN_ON! */
> + WARN_ON(dw_mci_card_busy(slot->mmc));
> +}
> +
> static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool
> force_clkinit)
> {
> struct dw_mci *host = slot->host;
> @@ -899,6 +925,8 @@ static void dw_mci_setup_bus(struct dw_mci_slot
> *slot, bool force_clkinit)
> /* We must continue to set bit 28 in CMD until the change is
> complete */
> if (host->state == STATE_WAITING_CMD11_DONE)
> sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
> + else
> + dw_mci_wait_busy(slot);
>
hmm...I would suggest you to call dw_mci_wait_busy() from inside
mci_send_cmd(), seems like dw_mmc hangs while sending update clock cmd
in multiple cases.see [1]
[1]: http://permalink.gmane.org/gmane.linux.kernel.mmc/31140
>>> I think this patch is more reasonable.
>>> So I will resend patches based on this patch.
>>> thank you!
>>
>> I have tested your patches instead [1] above and they do not solve my issue:
>> Board: odroid-xu3/exynos5422/dw_mmc_250a.
>> MMC card: absent, broken-cd quirk
>> SD card: present
>>
> I doubt $SUBJECT patch in current form can resolve you issue. I have
> already given comments on $subject patch.
>
> Can you try out below patch (I have not tested yet) on top of $SUBJECT patch?
>
> ===
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index b0b57e3..ea87844 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -101,6 +101,7 @@ struct idmac_desc {
> #endif /* CONFIG_MMC_DW_IDMAC */
>
> static int dw_mci_card_busy(struct mmc_host *mmc);
> +static void dw_mci_wait_busy(struct dw_mci_slot *slot);
> static bool dw_mci_reset(struct dw_mci *host);
> static bool dw_mci_ctrl_reset(struct
RE: [PATCH 1/4] usb: renesas_usbhs: fix spinlock recursion by usbhsf_dma_complete()
Hi Geert-san, Thank you for the reply! > Hi Shimoda-san, > > On Mon, Feb 9, 2015 at 9:16 AM, Yoshihiro Shimoda > wrote: > > The usbhsf_pkt_handler(pipe, USBHSF_PKT_DMA_DONE) in usbhsf_dma_complete() > > will call the complete function of a usb gadget driver finally. > > According to the gadget.h, "The function will always be called with > > interrupts disabled". > > > > So, this patch adds a local_irq_save/local_irq_restore in the > > usbhsf_dma_complete() because a dmaengine driver may call this > > callback function when interrupts enabled (e.g. in tasklet). > > > > Signed-off-by: Yoshihiro Shimoda > > --- > > drivers/usb/renesas_usbhs/fifo.c |3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/usb/renesas_usbhs/fifo.c > > b/drivers/usb/renesas_usbhs/fifo.c > > index d891bff..b1440d0 100644 > > --- a/drivers/usb/renesas_usbhs/fifo.c > > +++ b/drivers/usb/renesas_usbhs/fifo.c > > @@ -1165,11 +1165,14 @@ static void usbhsf_dma_complete(void *arg) > > struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); > > struct device *dev = usbhs_priv_to_dev(priv); > > int ret; > > + unsigned long flags; > > > > + local_irq_save(flags); > > Adding "local_irq_save()" without a spinlock is usually not correct. > I'm a bit confused here. usbhsf_pkt_handler() itself calls > > usbhs_lock(priv, flags); > > which is actually > > spin_lock_irqsave(usbhs_priv_to_lock(priv), flags) > > so it does disable interrupts internally? Yes, it does. But.. > Or is this about protecting the call to > > pkt->done(priv, pkt); > > at the end of usbhsf_pkt_handler(), which is done after releasing the > spinlock? yes, I would like to protect pkt->done(priv, pkt) because it will call usb_gadget_giveback_request() in mod_gadget.c. Otherwise, an oops happens if I enabled CONFIG_DEBUG_SPINLOCK and used g_ncm. I copied the oops log at the end of this email. (After I loocked the log again, I should have described a commit log that this issue is caused from a gadget driver.) Also, this driver cannot protect pkt->done(priv, pkt) using usbhs_lock() because a gadget driver may call usb_ep_queue() in the complete function from usb_gadget_giveback_request(). So, a spinlock recursion will happen. > Still, that would need some better protection, as local_irq_save() disables > interrupts only on the CPU it's running on, not on other CPUs in a > multiprocessor system. I see. I will investigate this issue more. === oops log === BUG: spinlock recursion on CPU#0, irq/102-e65a000/546 lock: 0xee1f5d5c, .magic: dead4ead, .owner: irq/102-e65a000/546, .owner_cpu: 0 CPU: 0 PID: 546 Comm: irq/102-e65a000 Tainted: GW 3.19.0-rc4-01754-gfd5b84e-dirty #181 Hardware name: Generic R8A7791 (Flattened Device Tree) Backtrace: [] (dump_backtrace) from [] (show_stack+0x18/0x1c) r6: r5:ee1f5d5c r4: r3:00208040 [] (show_stack) from [] (dump_stack+0x7c/0x98) [] (dump_stack) from [] (spin_dump+0x80/0x94) r4:ee967240 r3:c0653334 [] (spin_dump) from [] (spin_bug+0x2c/0x30) r5:c059b229 r4:ee1f5d5c [] (spin_bug) from [] (do_raw_spin_lock+0x50/0x190) r5:000f r4:6113 [] (do_raw_spin_lock) from [] (_raw_spin_lock_irqsave+0x18/0x20) r9:ee1f5d5c r8:ee1f5d40 r7:eeaea434 r6: r5:000f r4:6113 [] (_raw_spin_lock_irqsave) from [] (eth_start_xmit+0xd0/0x37c [u_ether]) r4:ee1f5800 r3: [] (eth_start_xmit [u_ether]) from [] (ncm_tx_tasklet+0x44/0x4c [usb_f_ncm]) r10:eea5fd38 r9:c06987c0 r8: r7: r6:c0653274 r5: r4:ee115600 [] (ncm_tx_tasklet [usb_f_ncm]) from [] (tasklet_action+0x94/0xf4) r5:ee1156e0 r4:ee1156dc [] (tasklet_action) from [] (__do_softirq+0xec/0x220) r8:c0658098 r7:0100 r6:c0658088 r5:0030 r4:eea5e000 r3:4004 [] (__do_softirq) from [] (irq_exit+0x8c/0xfc) r10:0002 r9:6013 r8:0001 r7:ee806000 r6: r5:c0653ac8 r4: [] (irq_exit) from [] (__handle_domain_irq+0x94/0xb8) r4: r3:00a2 [] (__handle_domain_irq) from [] (gic_handle_irq+0x40/0x64) r8:eea4f8b0 r7:eea5fe1c r6:c065e95c r5:eea5fde8 r4:f0002000 r3:eea5fde8 [] (gic_handle_irq) from [] (__irq_svc+0x40/0x54) Exception stack(0xeea5fde8 to 0xeea5fe30) fde0: ee1f5d5c ac4aac49 ee0b65e4 ee1f5d40 ee1f5d40 ee0b65c0 fe00: eeb5b280 ee1f5d5c eea4f8b0 6013 0002 eea5fe4c eea5fe20 eea5fe30 fe20: c0470254 bf0005b8 6013 r6: r5:6013 r4:bf0005b8 r3:c0470254 [] (tx_complete [u_ether]) from [] (usb_gadget_giveback_request+0x14/0x18) r7:eea4f810 r6:ee8e206c r5: r4:ee0b65f4 [] (usb_gadget_giveback_request) from [] (usbhsg_queue_done+0x2c/0x30) [] (usbhsg_queue_done) from [] (usbhsf_pkt_handler+0xfc/0x114) [] (usbhsf_pkt_handler) from [] (usbhsf_dma_complete+0x20/0x58) r10: r9:0001 r8:00200200 r7:00100100 r6:eeb118c8 r5:ee9a5a00 r4:ee8e206c [] (usbhsf_dma_complete) from [] (usb_dmac_isr_channel_thread+0x8c/0xcc) r5:eeb118
[Patch V5 05/12] ASoC: codec: Add MAX98357A codec driver
From: Kenneth Westfield
Add codec driver for the Maxim MAX98357A DAC.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
sound/soc/codecs/Kconfig | 4 ++
sound/soc/codecs/Makefile| 2 +
sound/soc/codecs/max98357a.c | 145 +++
3 files changed, 151 insertions(+)
create mode 100644 sound/soc/codecs/max98357a.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index
8349f982a586841a3ac9e7b0526af05699c7deaf..0500b3ed5fa5ac4d45663ad659da9db3003bc5a3
100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -69,6 +69,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_MAX98088 if I2C
select SND_SOC_MAX98090 if I2C
select SND_SOC_MAX98095 if I2C
+ select SND_SOC_MAX98357A if GPIOLIB
select SND_SOC_MAX9850 if I2C
select SND_SOC_MAX9768 if I2C
select SND_SOC_MAX9877 if I2C
@@ -456,6 +457,9 @@ config SND_SOC_MAX98090
config SND_SOC_MAX98095
tristate
+config SND_SOC_MAX98357A
+ tristate
+
config SND_SOC_MAX9850
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index
bbdfd1e1c182f9ee102f532f391f522e77a8922b..69b8666d187a0e8d1e2a532e68e2509acc95da7e
100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -64,6 +64,7 @@ snd-soc-max9768-objs := max9768.o
snd-soc-max98088-objs := max98088.o
snd-soc-max98090-objs := max98090.o
snd-soc-max98095-objs := max98095.o
+snd-soc-max98357a-objs := max98357a.o
snd-soc-max9850-objs := max9850.o
snd-soc-mc13783-objs := mc13783.o
snd-soc-ml26124-objs := ml26124.o
@@ -245,6 +246,7 @@ obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o
obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
obj-$(CONFIG_SND_SOC_MAX98090) += snd-soc-max98090.o
obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
+obj-$(CONFIG_SND_SOC_MAX98357A)+= snd-soc-max98357a.o
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
diff --git a/sound/soc/codecs/max98357a.c b/sound/soc/codecs/max98357a.c
new file mode 100644
index
..4ee23fbc4e1237268ae104319a9cfe4fc369934e
--- /dev/null
+++ b/sound/soc/codecs/max98357a.c
@@ -0,0 +1,145 @@
+/* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * max98357a.c -- MAX98357A ALSA SoC Codec driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int max98357a_daiops_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct gpio_desc *sdmode = snd_soc_dai_get_drvdata(dai);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ gpiod_set_value(sdmode, 1);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ gpiod_set_value(sdmode, 0);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget max98357a_dapm_widgets[] = {
+ SND_SOC_DAPM_DAC("SDMode", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_OUTPUT("Speaker"),
+};
+
+static const struct snd_soc_dapm_route max98357a_dapm_routes[] = {
+ {"Speaker", NULL, "SDMode"},
+};
+
+static int max98357a_codec_probe(struct snd_soc_codec *codec)
+{
+ struct gpio_desc *sdmode;
+
+ sdmode = devm_gpiod_get(codec->dev, "sdmode");
+ if (IS_ERR(sdmode)) {
+ dev_err(codec->dev, "%s() unable to get sdmode GPIO: %ld\n",
+ __func__, PTR_ERR(sdmode));
+ return PTR_ERR(sdmode);
+ }
+ gpiod_direction_output(sdmode, 0);
+ snd_soc_codec_set_drvdata(codec, sdmode);
+
+ return 0;
+}
+
+static struct snd_soc_codec_driver max98357a_codec_driver = {
+ .probe = max98357a_codec_probe,
+ .dapm_widgets = max98357a_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(max98357a_dapm_widgets),
+ .dapm_routes= max98357a_dapm_routes,
+ .num_dapm_routes= ARRAY_SIZE(max98357a_dapm_routes),
+};
+
+static struct snd_soc_dai_ops max98357a_dai_ops = {
+ .trigger= max98357a_daiops_trigger,
[Patch V5 07/12] ASoC: ipq806x: Add LPASS CPU DAI driver
From: Kenneth Westfield
Add the CPU DAI driver for the Qualcomm
Technologies low-power audio subsystem (LPASS).
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
sound/soc/qcom/lpass-cpu.c | 481 +
1 file changed, 481 insertions(+)
create mode 100644 sound/soc/qcom/lpass-cpu.c
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
new file mode 100644
index
..c178142989abce9c46565fccbaf3b140cb289b19
--- /dev/null
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "lpass-lpaif-ipq806x.h"
+#include "lpass.h"
+
+static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+ unsigned int freq, int dir)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = clk_set_rate(drvdata->mi2s_osr_clk, freq);
+ if (ret)
+ dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n",
+ __func__, freq, ret);
+
+ return ret;
+}
+
+static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = clk_prepare_enable(drvdata->mi2s_osr_clk);
+ if (ret) {
+ dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(drvdata->mi2s_bit_clk);
+ if (ret) {
+ dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n",
+ __func__, ret);
+ clk_disable_unprepare(drvdata->mi2s_osr_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+
+ clk_disable_unprepare(drvdata->mi2s_bit_clk);
+ clk_disable_unprepare(drvdata->mi2s_osr_clk);
+}
+
+static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ snd_pcm_format_t format = params_format(params);
+ unsigned int channels = params_channels(params);
+ unsigned int rate = params_rate(params);
+ unsigned int regval;
+ int bitwidth, ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(dai->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
+ LPAIF_I2SCTL_WSSRC_INTERNAL;
+
+ switch (bitwidth) {
+ case 16:
+ regval |= LPAIF_I2SCTL_BITWIDTH_16;
+ break;
+ case 24:
+ regval |= LPAIF_I2SCTL_BITWIDTH_24;
+ break;
+ case 32:
+ regval |= LPAIF_I2SCTL_BITWIDTH_32;
+ break;
+ default:
+ dev_err(dai->dev, "%s() invalid bitwidth given: %d\n",
+ __func__, bitwidth);
+ return -EINVAL;
+ }
+
+ switch (channels) {
+ case 1:
+ regval |= LPAIF_I2SCTL_SPKMODE_SD0;
+ regval |= LPAIF_I2SCTL_SPKMONO_MONO;
+ break;
+ case 2:
+ regval |= LPAIF_I2SCTL_SPKMODE_SD0;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 4:
+ regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 6:
+ regval |= LPAIF_I2SCTL_SPKMODE_6CH;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 8:
+ regval |= LPAIF_I2SCTL_SPKMODE_8CH;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+
[Patch V5 11/12] ASoC: Allow for building QCOM drivers
From: Kenneth Westfield Allow for the Qualcomm Technologies ASoC drivers to build. Signed-off-by: Kenneth Westfield Acked-by: Banajit Goswami --- sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + 2 files changed, 2 insertions(+) diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 7d5d6444a83737ffa3c01acbe1925de619e0390a..b98eebf0e30bba19ec24acc7f0e6ab155e5e602b 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig" source "sound/soc/intel/Kconfig" source "sound/soc/mxs/Kconfig" source "sound/soc/pxa/Kconfig" +source "sound/soc/qcom/Kconfig" source "sound/soc/rockchip/Kconfig" source "sound/soc/samsung/Kconfig" source "sound/soc/sh/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 865e090c80616024a552da5e33d2796b9be1dbbd..3d78a8d874dc98dd6219b33e3f2c100ef0334bfc 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/ obj-$(CONFIG_SND_SOC) += omap/ obj-$(CONFIG_SND_SOC) += kirkwood/ obj-$(CONFIG_SND_SOC) += pxa/ +obj-$(CONFIG_SND_SOC) += qcom/ obj-$(CONFIG_SND_SOC) += rockchip/ obj-$(CONFIG_SND_SOC) += samsung/ obj-$(CONFIG_SND_SOC) += sh/ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch V5 06/12] ASoC: ipq806x: add LPASS header files
From: Kenneth Westfield
Add the LPASS header files for ipq806x SOC. This
includes the register definitions for the ipq806x
LPAIF, and the structure definition for the driver
data.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
sound/soc/qcom/lpass-lpaif-ipq806x.h | 172 +++
sound/soc/qcom/lpass.h | 51 +++
2 files changed, 223 insertions(+)
create mode 100644 sound/soc/qcom/lpass-lpaif-ipq806x.h
create mode 100644 sound/soc/qcom/lpass.h
diff --git a/sound/soc/qcom/lpass-lpaif-ipq806x.h
b/sound/soc/qcom/lpass-lpaif-ipq806x.h
new file mode 100644
index
..dc423b425e60ebb11cd0ce78da2574ed27c2
--- /dev/null
+++ b/sound/soc/qcom/lpass-lpaif-ipq806x.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-lpaif-ipq806x.h -- Definitions for the QTi LPAIF in the ipq806x LPASS
+ */
+
+#ifndef __LPASS_LPAIF_H__
+#define __LPASS_LPAIF_H__
+
+#define LPAIF_BANK_OFFSET 0x1000
+
+/* LPAIF I2S */
+
+#define LPAIF_I2SCTL_REG_BASE 0x0010
+#define LPAIF_I2SCTL_REG_STRIDE0x4
+#define LPAIF_I2SCTL_REG_ADDR(addr, port) \
+ (LPAIF_I2SCTL_REG_BASE + (addr) + (LPAIF_I2SCTL_REG_STRIDE * (port)))
+
+enum lpaif_i2s_ports {
+ LPAIF_I2S_PORT_MIN = 0,
+
+ LPAIF_I2S_PORT_CODEC_SPK= 0,
+ LPAIF_I2S_PORT_CODEC_MIC= 1,
+ LPAIF_I2S_PORT_SEC_SPK = 2,
+ LPAIF_I2S_PORT_SEC_MIC = 3,
+ LPAIF_I2S_PORT_MI2S = 4,
+
+ LPAIF_I2S_PORT_MAX = 4,
+ LPAIF_I2S_PORT_NUM = 5,
+};
+
+#define LPAIF_I2SCTL_REG(port) LPAIF_I2SCTL_REG_ADDR(0x0, (port))
+
+#define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000
+#define LPAIF_I2SCTL_LOOPBACK_SHIFT15
+#define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
+#define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
+
+#define LPAIF_I2SCTL_SPKEN_MASK0x4000
+#define LPAIF_I2SCTL_SPKEN_SHIFT 14
+#define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT)
+#define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT)
+
+#define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00
+#define LPAIF_I2SCTL_SPKMODE_SHIFT 10
+#define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_QUAD01(5 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_QUAD23(6 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+
+#define LPAIF_I2SCTL_SPKMONO_MASK 0x0200
+#define LPAIF_I2SCTL_SPKMONO_SHIFT 9
+#define LPAIF_I2SCTL_SPKMONO_STEREO(0 << LPAIF_I2SCTL_SPKMONO_SHIFT)
+#define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT)
+
+#define LPAIF_I2SCTL_WSSRC_MASK0x0004
+#define LPAIF_I2SCTL_WSSRC_SHIFT 2
+#define LPAIF_I2SCTL_WSSRC_INTERNAL(0 << LPAIF_I2SCTL_WSSRC_SHIFT)
+#define LPAIF_I2SCTL_WSSRC_EXTERNAL(1 << LPAIF_I2SCTL_WSSRC_SHIFT)
+
+#define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003
+#define LPAIF_I2SCTL_BITWIDTH_SHIFT0
+#define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+#define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+#define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+
+/* LPAIF IRQ */
+
+#define LPAIF_IRQ_REG_BASE 0x3000
+#define LPAIF_IRQ_REG_STRIDE 0x1000
+#define LPAIF_IRQ_REG_ADDR(addr, port) \
+ (LPAIF_IRQ_REG_BASE + (addr) + (LPAIF_IRQ_REG_STRIDE * (port)))
+
+enum lpaif_irq_ports {
+ LPAIF_IRQ_PORT_MIN = 0,
+
+ LPAIF_IRQ_PORT_HOST = 0,
+ LPAIF_IRQ_PORT_ADSP = 1,
+
+ LPAIF_IRQ_PORT_MAX = 2,
+ LPAIF_IRQ_PORT_NUM = 3,
+};
+
+#define LPAIF_IRQEN_REG(port) LPAIF_IRQ_REG_ADDR(0x0, (port))
+#define LPAIF_IRQSTAT_REG(port)LPAIF_IRQ_REG_ADDR(0x4, (port))
+#define LPAIF_IRQCLEAR_REG(port) LPAIF_IRQ_REG_ADD
[Patch V5 04/12] ASoC: qcom: Document IPQ806X-MAX89357A bindings
From: Kenneth Westfield
Add documentation to the sound directory of the
device-tree bindings for the IPQ806x-MAX98357A
soundcard.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
.../bindings/sound/qcom,ipq806x-max98357a.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/qcom,ipq806x-max98357a.txt
diff --git a/Documentation/devicetree/bindings/sound/qcom,ipq806x-max98357a.txt
b/Documentation/devicetree/bindings/sound/qcom,ipq806x-max98357a.txt
new file mode 100644
index
..54c6211ce34ab8eb5c764df516c875694eeab3cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,ipq806x-max98357a.txt
@@ -0,0 +1,24 @@
+* Qualcomm Technologies IPQ806x-MAX98357A SoundCard
+
+This node models a soundcard for boards with the Qualcomm Technologies IPQ806x
+SOC connected to a MAX98357A DAC via I2S.
+
+Required properties:
+
+- compatible : "qcom,ipq806x-max98357a"
+- qcom,model : The user-visible name of this sound card.
+- cpu : Phandle of the CPU DAI
+- codec: Phandle of the codec DAI
+- codec-dai: Name of the codec DAI which must be selected from one of the
+ following entries:
+ * max98357a
+
+Example:
+
+sound {
+ compatible = "qcom,ipq806x-max98357a";
+ model = "ipq806x-max98357a";
+ cpu = <&lpass_cpu>;
+ codec = <&max98357a>;
+ codec-dai = "max98357a";
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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[Patch V5 02/12] ASoC: max98357a: Document MAX98357A bindings
From: Kenneth Westfield
Add documentation to the sound directory of the
device-tree bindings for the Maxim MAX98357A audio
DAC.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
Documentation/devicetree/bindings/sound/max98357a.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/max98357a.txt
diff --git a/Documentation/devicetree/bindings/sound/max98357a.txt
b/Documentation/devicetree/bindings/sound/max98357a.txt
new file mode 100644
index
..a7a149a236e55b8372b7cb3622cd6a6c664d4e2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/max98357a.txt
@@ -0,0 +1,14 @@
+Maxim MAX98357A audio DAC
+
+This node models the Maxim MAX98357A DAC.
+
+Required properties:
+- compatible : "maxim,max98357a"
+- sdmode-gpios : GPIO specifier for the GPIO -> DAC SDMODE pin
+
+Example:
+
+max98357a {
+ compatible = "maxim,max98357a";
+ sdmode-gpios = <&qcom_pinmux 25 0>;
+};
--
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a Linux Foundation Collaborative Project
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[Patch V5 01/12] MAINTAINERS: Add QCOM audio ASoC maintainer
From: Kenneth Westfield Add maintainers for the Qualcomm Technologies sound drivers. Signed-off-by: Kenneth Westfield Acked-by: Banajit Goswami --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d66a97dd3a12548e0f79c59154260724da11f282..9beda051e158156e2f7742485059ca299ed6a3d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5183,6 +5183,13 @@ F: drivers/char/ipmi/ F: include/linux/ipmi* F: include/uapi/linux/ipmi* +QCOM AUDIO (ASoC) DRIVERS +M: Patrick Lai +M: Banajit Goswami +L: alsa-de...@alsa-project.org (moderated for non-subscribers) +S: Supported +F: sound/soc/qcom/ + IPS SCSI RAID DRIVER M: Adaptec OEM Raid Solutions L: linux-s...@vger.kernel.org -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch V5 03/12] ASoC: qcom: Document LPASS CPU bindings
From: Kenneth Westfield
Add documentation to the sound directory of the
device-tree bindings for the IPQ806x LPASS CPU DAI
device.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
.../devicetree/bindings/sound/qcom,lpass-cpu.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
new file mode 100644
index
..621773d1c64af8f4f9eaceb2f7d2d7ec17c66aeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
@@ -0,0 +1,38 @@
+* Qualcomm Technologies LPASS CPU DAI
+
+This node models the Qualcomm Technologies Low-Power Audio SubSystem.
+
+Required properties:
+
+- compatible : "qcom,lpass-cpu"
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : A list which must include the following entries:
+ * "ahbix-clk"
+ * "mi2s-osr-clk"
+ * "mi2s-bit-clk"
+- interrupts : Must contain an entry for each entry in
+ interrupt-names.
+- interrupt-names : A list which must include the following entries:
+ * "lpass-irq-lpaif"
+- pinctrl-N: One property must exist for each entry in
+ pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
+ for details of the property values.
+- pinctrl-names: Must contain a "default" entry.
+- reg : Must contain an address for each entry in reg-names.
+- reg-names: A list which must include the following entries:
+ * "lpass-lpaif"
+
+Example:
+
+lpass@2810 {
+ compatible = "qcom,lpass-cpu";
+ clocks = <&lcc AHBIX_CLK>, <&lcc MI2S_OSR_CLK>, <&lcc MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk";
+ interrupts = <0 85 1>;
+ interrupt-names = "lpass-irq-lpaif";
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&mi2s_default>;
+ pinctrl-1 = <&mi2s_idle>;
+ reg = <0x2810 0x1>;
+ reg-names = "lpass-lpaif";
+};
--
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a Linux Foundation Collaborative Project
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[Patch V5 00/12] ASoC: QCOM: Add support for ipq806x SOC
From: Kenneth Westfield This patch series adds support for I2S audio playback on the Qualcomm Technologies ipq806x SOC. The ipq806x SOC has audio-related hardware blocks in its low-power audio subsystem (or LPASS). One of the relevant blocks in the LPASS is its low-power audio interface (or LPAIF). This contains an MI2S port, which is what these drivers are configured to use. The LPAIF also contains a DMA engine that is dedicated to moving audio samples into the transmit FIFO of the MI2S port. The development board being used for testing contains the ipq806x SOC and a Maxim max98357a DAC/amp. One bus from the MI2S port of the SOC is connected to the DAC/amp for stereo playback. This bus is configured so that the SOC is bus master and consists of DATA, LRCLK, and BCLK. The DAC/amp does not need MCLK to operate. In addition, a single GPIO pin from the SOC is connected to the same DAC/amp, which gives enable/disable control over the DAC/amp. The specific drivers added are: * a codec DAI driver for controlling the DAC/amp * a CPU DAI driver for controlling the MI2S port * a platform driver for controlling the LPAIF DMA engine * a machine driver that instantiates a dai-link for playback Corresponding additions to the device tree for the ipq806x SOC and its documentation has also been added. Also, as this is a new directory, the MAINTAINERS file has been updated as well. The LPASS also contains clocks that need to be controlled. Those drivers have been submitted as a separate patch series: [PATCH v3 0/8] qcom audio clock control drivers http://lkml.org/lkml/2015/1/19/656 = Changes since V4 [Patch V4 00/10] ASoC: QCOM: Add support for ipq806x SOC http://mailman.alsa-project.org/pipermail/alsa-devel/2015-February/087499.html * Replaced simple-card with a machine driver to resolve the system clock configuration, rather than having the CPU DAI driver do it. * Added header files to avoid indirect header dependencies and implicit forward declarations. * Tweaked the ISR to match the conventions of the surrounding code. * Removed the usage of the low-power memory as it is not needed. * Removed the use of the DRV_NAME constant. * Added explicit dependancy on gpiolib for the codec driver. * Moved the MODULE_DEVICE_TABLE macro inside the CONFIG_OF conditional. * Modified the documentation to reflect the changes. * General code cleanup. = Changes since V3 [Patch V3 00/10] ASoC: QCOM: Add support for ipq806x SOC http://mailman.alsa-project.org/pipermail/alsa-devel/2014-December/085694.html * Placed the content of the inline functions into the callbacks. * Replaced use of readl/writel register access functions with regmap access functions. Notable exception is the ISR, which uses ioread32/iowrite32. * Rearranged the sequencing of the hardware block enables to fit within the ASoC framework callbacks, while remaining functional. REQ 1: The hardware requires the enable sequence to be: LPAIF-DMA[enable],then LPAIF-MI2S[enable], then DAC-GPIO[enable] REQ 2: The hardware requires the disable sequence to be: DAC-GPIO[disable], then LPAIF-MI2S[disable] * Corrected the implementation of the pointer callback. * Utilize the LPM to buffer audio samples, rather than memory external to LPASS. * Corrected the interrupt clearing in the ISR. * Implemented a default system clock (defined by the simple-card DT node), and optional LPASS DT node modifiers that can alter the system clock in order to expand the range of available bit clock frequencies. * Addressed all of the remaining issues raised by Mark Brown. * General code cleanup. = Changes since V2 [Patch v2 00/11] ASoC: QCOM: Add support for ipq806x SOC http://mailman.alsa-project.org/pipermail/alsa-devel/2014-December/085186.html * Removed the PCM platform driver from the DTS platform and tied it to the CPU DAI driver. * Changed I2S pinctrl to use generic naming convention and moved control to CPU DAI driver. It should be controlled now by soc-core's pinctrl_pm_* functionality. * Added stub DAPM support in codec driver. As the DAC GPIO needs to be enabled last when starting playback, and disabled first when stopping playback, it seems as though the trigger function may be the place for this. Suggestions are welcome for a better place to put this. * Removed machine driver and tied DAI drivers to simple-audio-card. * Packaged the build files and Maxim codec files together in one change. * Removed QCOM as vendor from Maxim code and documentation. * Separated the SOC and board definitions into the correct DTS files. * Update device tree documentation to reflect changes. * General code cleanup. = Changes since V1 [PATCH 0/9] ASoC: QCOM: Add support for ipq806x SOC http://mailman.alsa-project.org/pipermail/alsa-devel/2014-November/084322.html * Remove the native LPAIF driver, and move its functionality to the CPU DAI
[Patch V5 09/12] ASoC: ipq806x: Add @max98357a machine driver
From: Kenneth Westfield
Add machine driver for the boards with the IPQ806X
SOC connected to the MAX98357A DAC.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
sound/soc/qcom/ipq806x-max98357a.c | 171 +
1 file changed, 171 insertions(+)
create mode 100644 sound/soc/qcom/ipq806x-max98357a.c
diff --git a/sound/soc/qcom/ipq806x-max98357a.c
b/sound/soc/qcom/ipq806x-max98357a.c
new file mode 100644
index
..af92e9ffa42104d6e29160b9e0ffedc820388c7c
--- /dev/null
+++ b/sound/soc/qcom/ipq806x-max98357a.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ipq806x-max98357a.c -- ALSA SoC machine driver for QTi ipq806x SOC with
+ *MAX98357a DAC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPQ806X_MAX98357A_SYSCLK_MULT 4
+
+static int ipq806x_max98357a_ops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct snd_soc_card *card = soc_runtime->card;
+ snd_pcm_format_t format = params_format(params);
+ unsigned int rate = params_rate(params);
+ unsigned int sysclk_freq;
+ int bitwidth, ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(card->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ /*
+* as the CPU DAI is the I2S bus master and no system clock is needed by
+* the MAX98357a DAC, simply set the system clock to be a constant
+* multiple of the bit clock for the clock divider
+*/
+ sysclk_freq = rate * bitwidth * 2 * IPQ806X_MAX98357A_SYSCLK_MULT;
+
+ ret = snd_soc_dai_set_sysclk(soc_runtime->cpu_dai, 0, sysclk_freq, 0);
+ if (ret) {
+ dev_err(card->dev, "%s() error setting sysclk to %u: %d\n",
+ __func__, sysclk_freq, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_ops ipq806x_max98357a_soc_ops = {
+ .hw_params = ipq806x_max98357a_ops_hw_params,
+};
+
+static struct snd_soc_dai_link ipq806x_max98357a_dai_link = {
+ .name = "IPQ806x Media1",
+ .stream_name= "MultiMedia1",
+ .ops= &ipq806x_max98357a_soc_ops,
+};
+
+static struct snd_soc_card ipq806x_max98357a_soc_card = {
+ .name = "ipq806x-max98357a",
+ .dev= NULL,
+};
+
+static int ipq806x_max98357a_parse_of(struct snd_soc_card *card)
+{
+ struct snd_soc_dai_link *dai_link = card->dai_link;
+ struct device_node *np = card->dev->of_node;
+ int ret;
+
+ dai_link->cpu_of_node = of_parse_phandle(np, "cpu", 0);
+ if (!dai_link->cpu_of_node) {
+ dev_err(card->dev, "%s() error getting cpu phandle\n",
+ __func__);
+ return -EINVAL;
+ }
+ dai_link->platform_of_node = dai_link->cpu_of_node;
+
+ dai_link->codec_of_node = of_parse_phandle(np, "codec", 0);
+ if (!dai_link->codec_of_node) {
+ dev_err(card->dev, "%s() error getting codec phandle\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ ret = of_property_read_string(np, "codec-dai",
+ &dai_link->codec_dai_name);
+ if (ret) {
+ dev_err(card->dev, "%s() error getting codec-dai: %d\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ipq806x_max98357a_platform_probe(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = &ipq806x_max98357a_soc_card;
+ int ret;
+
+ if (card->dev) {
+ dev_err(&pdev->dev, "%s() error, existing soundcard\n",
+ __func__);
+ return -ENODEV;
+ }
+ card->dev = &pdev->dev;
+ platform_set_drvdata(pdev, card);
+
+ ret = snd_soc_of_parse_card_name(card, "qcom,model");
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error parsing card name: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ card->dai_link = &ipq806x_max9
[Patch V5 10/12] ASoC: qcom: Add ability to build QCOM drivers
From: Kenneth Westfield Define the LPASS platform driver and the LPASS CPU DAI driver configuration, and how to build them. Signed-off-by: Kenneth Westfield Acked-by: Banajit Goswami --- sound/soc/qcom/Kconfig | 26 ++ sound/soc/qcom/Makefile | 11 +++ 2 files changed, 37 insertions(+) create mode 100644 sound/soc/qcom/Kconfig create mode 100644 sound/soc/qcom/Makefile diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig new file mode 100644 index ..803fc204d65ae1916f30477bdaf926b650320c8a --- /dev/null +++ b/sound/soc/qcom/Kconfig @@ -0,0 +1,26 @@ +config SND_SOC_QCOM + tristate "SoC Audio support for QCOM platforms" + help + Support for audio in Qualcomm Technologies SOC-based systems. + Say Y if you want to use audio devices such as I2S, PCM, + S/PDIF, etc. + +config SND_SOC_LPASS_CPU + tristate + depends on SND_SOC_QCOM + +config SND_SOC_IPQ806X_MAX98357A + tristate "SoC Audio support for IPQ806x based platforms" + depends on SND_SOC_QCOM || ARCH_QCOM || COMPILE_TEST + select SND_SOC_LPASS_CPU + select SND_SOC_LPASS_PLATFORM + select SND_SOC_MAX98357A + help + Support for Qualcomm Technologies LPASS audio block in + IPQ806X SOC-based systems. + Say Y if you want to use audio devices such as I2S, PCM, + S/PDIF, etc. + +config SND_SOC_LPASS_PLATFORM + tristate + depends on SND_SOC_QCOM diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile new file mode 100644 index ..b2811496b0df654a451c0dc231ab5bff84ca2850 --- /dev/null +++ b/sound/soc/qcom/Makefile @@ -0,0 +1,11 @@ +# Platform +snd-soc-lpass-cpu-objs := lpass-cpu.o +snd-soc-lpass-platform-objs := lpass-platform.o + +obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o +obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o + +# Machine +snd-soc-ipq806x-max98357a-objs := ipq806x-max98357a.o + +obj-$(CONFIG_SND_SOC_IPQ806X_MAX98357A) += snd-soc-ipq806x-max98357a.o -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch V5 08/12] ASoC: ipq806x: Add LPASS platform driver
From: Kenneth Westfield
Add platform driver for the Qualcomm Technologies
low-power audio subsystem (LPASS) ports.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
sound/soc/qcom/lpass-platform.c | 526
1 file changed, 526 insertions(+)
create mode 100644 sound/soc/qcom/lpass-platform.c
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
new file mode 100644
index
..2fa6280dfb234b213904ad73dfad91c7f575538c
--- /dev/null
+++ b/sound/soc/qcom/lpass-platform.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "lpass-lpaif-ipq806x.h"
+#include "lpass.h"
+
+#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
+#define LPASS_PLATFORM_PERIODS 2
+
+static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
+ .info = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+ .formats= SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 8,
+ .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
+ .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
+ LPASS_PLATFORM_PERIODS,
+ .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
+ LPASS_PLATFORM_PERIODS,
+ .periods_min= LPASS_PLATFORM_PERIODS,
+ .periods_max= LPASS_PLATFORM_PERIODS,
+ .fifo_size = 0,
+};
+
+static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ int ret;
+
+ snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
+
+ runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0) {
+ dev_err(soc_runtime->dev, "%s() setting constraints failed:
%d\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+ return 0;
+}
+
+static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ snd_pcm_format_t format = params_format(params);
+ unsigned int channels = params_channels(params);
+ unsigned int regval;
+ int bitwidth;
+ int ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ regval = LPAIF_RDMACTL_BURSTEN_INCR4 |
+ LPAIF_RDMACTL_AUDINTF_MI2S |
+ LPAIF_RDMACTL_FIFOWM_8;
+
+ switch (bitwidth) {
+ case 16:
+ switch (channels) {
+ case 1:
+ case 2:
+ regval |= LPAIF_RDMACTL_WPSCNT_ONE;
+ break;
+ case 4:
+ regval |= LPAIF_RDMACTL_WPSCNT_TWO;
+ break;
+ case 6:
+ regval |= LPAIF_RDMACTL
[Patch V5 12/12] ARM: dts: Model IPQ LPASS audio hardware
From: Kenneth Westfield
Model the Qualcomm Technologies LPASS hardware for
the ipq806x SOC.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index
63b2146f563b541e4994697af5ee1bbb41a4abd1..f9b1cf2737e61c5e428cfef19cfd013395138a52
100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
#include "skeleton.dtsi"
#include
+#include
#include
/ {
@@ -96,6 +97,21 @@
cpu-offset = <0x8>;
};
+ lpass@2810 {
+ compatible = "qcom,lpass-cpu";
+ status = "disabled";
+ clocks = <&lcc AHBIX_CLK>,
+ <&lcc MI2S_OSR_CLK>,
+ <&lcc MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk",
+ "mi2s-osr-clk",
+ "mi2s-bit-clk";
+ interrupts = <0 85 1>;
+ interrupt-names = "lpass-irq-lpaif";
+ reg = <0x2810 0x1>;
+ reg-names = "lpass-lpaif";
+ };
+
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -279,5 +295,12 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ lcc: clock-controller@2800 {
+ compatible = "qcom,lcc-ipq8064";
+ reg = <0x2800 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
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Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
On Wed, Feb 11, 2015 at 04:23:01PM +0100, Philipp Zabel wrote: > Am Mittwoch, den 11.02.2015, 22:09 +0800 schrieb Liu Ying: > > BTW, regarding the compatible string topic, shall I keep my implementation > > unchanged and don't append the additional "snps,dw-mipi-dsi" as I shared > > my concerns about it before? > > Leave the implementation unchanged. Still, I'd like to see > "snps,dw-mipi-dsi" appended to the mipi_dsi compatible property in > Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt > and in arch/arm/boot/dts/imx6qdl.dtsi. After all, Freescale's i.MX6 > specific implementation is register compatible to Synopsys' design, > isn't it? All right. Will do this in the next version. Regards, Liu Ying > > regards > Philipp > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 11 February 2015 at 13:27, Stephen Boyd wrote: > On 02/10, Ashwin Chaugule wrote: >> Hi Stephen, >> >> On 10 February 2015 at 20:05, Stephen Boyd wrote: >> > Scorpion supports a set of local performance monitor event >> > selection registers (LPM) sitting behind a cp15 based interface >> > that extend the architected PMU events to include Scorpion CPU >> > and Venum VFP specific events. To use these events the user is >> > expected to program the lpm register with the event code shifted >> > into the group they care about and then point the PMNx event at >> > that region+group combo by writing a LPMn_GROUPx event. Add >> > support for this hardware. >> > >> > Note: the raw event number is a pure software construct that >> > allows us to map the multi-dimensional number space of regions, >> > groups, and event codes into a flat event number space suitable >> > for use by the perf framework. >> > >> > This is based on code originally written by Ashwin Chaugule and >> > Neil Leeder [1] massed to become similar to the Krait PMU support >> > code. >> >> Thanks for taking this up! >> Overall this series looks good to me, but from what I faintly >> recollect, doesn't this (and the Krait pmu code) get affected by >> powercollapse issues anymore? >> e.g. >> https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/arch/arm/kernel/perf_event_msm.c?h=msm-3.4&id=b5ca687960f0fea2f4735e83ca5c9543474c19de >> > > Right now there isn't any power collapse support in mainline so > there's no immediate problem. Once we add power collapse support > (i.e. cpuidle) to the Scorpion and Krait platforms we'll need to > do something in the perf event code to properly maintain the > counts across idle. I imagine it would be done by registering for > cpu_pm notifications and then doing the save/restore on > CPU_PM_ENTER and CPU_PM_EXIT. At least, that's what you started > doing in this patch[1]. And then it seems the patch you mention > came after that and actually did the save/restore of the counts. > > [1] > https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/?h=msm-3.4&id=464983a7e991a484cac0bc0885cee4fee318d659 Right. Thats essential whenever the power collapse stuff goes in. Thanks, Ashwin. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Patch v3 2/2] dmaengine: Add ADM driver
On 02/11, Andy Gross wrote:
> +static struct platform_driver adm_dma_driver = {
> + .probe = adm_dma_probe,
> + .remove = adm_dma_remove,
> + .driver = {
> + .name = "adm-dma-engine",
> + .owner = THIS_MODULE,
> + .of_match_table = adm_of_match,
> + },
> +};
The THIS_MODULE script will find you. Am I a script?
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Re: [alsa-devel] [Patch V4 00/10] ASoC: QCOM: Add support for ipq806x SOC
On Tue, Feb 10, 2015 at 06:26:34PM -0800, Mark Brown wrote: > On Sun, Feb 08, 2015 at 10:45:11PM -0800, Kenneth Westfield wrote: > > On Sat, Feb 07, 2015 at 06:32:29AM +0800, Mark Brown wrote: > > > > I'd really like to see some discussion as to how this is all supposed > to > > > be handled - how will these direct hardware access drivers and device > > > trees work when someone does want to use the DSP (without causing > > > problems), and how will we transition from one to the other. This is > > > particularly pressing if there are use cases where people will want to > > > switch between the two modes at runtime. > > > > What I'm trying to avoid here is being in a situation where we have > > > existing stable DT bindings which we have to support but which > conflict > > > with the way that people want to use the systems. > > > The ipq806x SOC has no LPASS DSP. On SOCs with a DSP, these drivers > > would not be enabled. > > OK, but I'm guessing that they're using the same IP that is in other > SoCs which do have the DSP so even if you don't care for this device it > might still be an issue. > > > These drivers are prefixed with "lpass" to differentiate themselves from > > other drivers that would interact with a DSP, rather than the LPASS > > hardware directly. > > Right, it may be that all that's needed here is some indication as to > how to describe a system which *does* have a DSP. Perhaps require that > the devices be children of the DSP, that way if people want to access > the hardware directly they can load a dummy driver for the DSP that just > passes things through if they don't want to use the DSP? Replacing DSP-based drivers with LPASS-based drivers would be something that should be handled by Kconfig selections. For the DT, the DSP-related nodes and the LPASS-related nodes shouldn't overlap. There should be a DSP-based DT binding and a separate LPASS-based DT binding. Tying one or the other to the sound node (but not both), should work. -- Kenneth Westfield Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] ARM: dts: zynq: Split off Parallella Microserver device tree
The Microserver edition has neither HDMI nor USB.
Cc: Ola Jeppsson
Signed-off-by: Andreas Färber
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/zynq-parallella-microserver.dts | 19 +++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts/zynq-parallella-microserver.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..42c75eeba584 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -606,6 +606,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-parallella.dtb \
+ zynq-parallella-microserver.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
diff --git a/arch/arm/boot/dts/zynq-parallella-microserver.dts
b/arch/arm/boot/dts/zynq-parallella-microserver.dts
new file mode 100644
index ..1f3bd2d27a93
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-parallella-microserver.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ * Copyright (c) 2015 SUSE Linux GmbH
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include "zynq-parallella1.dtsi"
+
+/ {
+ model = "Adapteva Parallella Microserver Board";
+};
--
2.2.2
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[PATCH 2/5] ARM: dts: zynq: Add pinctrl to Parallella
Signed-off-by: Andreas Färber
---
arch/arm/boot/dts/zynq-parallella1.dtsi | 118
1 file changed, 118 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella1.dtsi
b/arch/arm/boot/dts/zynq-parallella1.dtsi
index 7c1206f928bc..e77a4968fe17 100644
--- a/arch/arm/boot/dts/zynq-parallella1.dtsi
+++ b/arch/arm/boot/dts/zynq-parallella1.dtsi
@@ -47,6 +47,8 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem0_default>;
ethernet_phy: ethernet-phy@0 {
/* Marvell 88E1318 */
@@ -58,6 +60,11 @@
};
};
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&i2c0 {
status = "okay";
@@ -85,10 +92,121 @@
};
};
+&pinctrl0 {
+ pinctrl_gem0_default: gem0-default {
+ mux {
+ function = "ethernet0";
+ groups = "ethernet0_0_grp";
+ };
+
+ conf {
+ groups = "ethernet0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26",
"MIO27";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20",
"MIO21";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio0";
+ groups = "mdio0_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio0_default: gpio0-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_7_grp";
+ };
+
+ conf {
+ groups = "gpio0_7_grp";
+ slew-rate = <0>;
+ io-standard = <3>;
+ };
+
+ conf-pull-up {
+ pins = "MIO7";
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ function = "sdio1";
+ groups = "sdio1_0_grp";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+
+ mux-cd {
+ function = "sdio1_cd";
+ groups = "gpio0_0_grp";
+ };
+
+ conf-cd {
+ groups = "gpio0_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <3>;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ function = "uart1";
+ groups = "uart1_0_grp";
+ };
+
+ conf {
+ groups = "uart1_0_grp";
+ slew-rate = <0>;
+ io-standard = <3>;
+ };
+
+ conf-rx {
+ pins = "MIO9";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO8";
+ bias-disable = <0>;
+ };
+ };
+};
+
&sdhci1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
--
2.2.2
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[PATCH 3/5] ARM: dts: zynq: Add LED for Parallella
This is the green LED CR10.
Signed-off-by: Andreas Färber
---
arch/arm/boot/dts/zynq-parallella1.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella1.dtsi
b/arch/arm/boot/dts/zynq-parallella1.dtsi
index e77a4968fe17..8b2895c06c8e 100644
--- a/arch/arm/boot/dts/zynq-parallella1.dtsi
+++ b/arch/arm/boot/dts/zynq-parallella1.dtsi
@@ -18,6 +18,7 @@
* GNU General Public License for more details.
*/
/include/ "zynq-7000.dtsi"
+#include
/ {
compatible = "adapteva,parallella", "xlnx,zynq-7000";
@@ -36,6 +37,16 @@
bootargs = "console=ttyPS0,115200 earlyprintk
root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
linux,stdout-path = "/amba/serial@e0001000";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ cr10 {
+ label = "parallella:cr10:usr";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
};
&clkc {
--
2.2.2
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[PATCH 5/5] ARM: dts: zynq: Add USB for Parallella
The Microserver edition does not feature USB - only the Kickstarter,
pre-order, Desktop and Embedded editions.
Signed-off-by: Andreas Färber
---
arch/arm/boot/dts/zynq-parallella.dts | 16 +++
arch/arm/boot/dts/zynq-parallella1.dtsi | 74 +
2 files changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index 99ee6551ae8d..b2eede1c708f 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -17,3 +17,19 @@
/ {
model = "Adapteva Parallella Board";
};
+
+&usb_phy0 {
+ status = "okay";
+};
+
+&usb_phy1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-parallella1.dtsi
b/arch/arm/boot/dts/zynq-parallella1.dtsi
index 8b2895c06c8e..1395aaadf3be 100644
--- a/arch/arm/boot/dts/zynq-parallella1.dtsi
+++ b/arch/arm/boot/dts/zynq-parallella1.dtsi
@@ -47,6 +47,18 @@
default-state = "on";
};
};
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb_phy1: phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
&clkc {
@@ -208,6 +220,54 @@
bias-disable = <0>;
};
};
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ function = "usb0";
+ groups = "usb0_0_grp";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ function = "usb1";
+ groups = "usb1_0_grp";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO41", "MIO43", "MIO48";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO40", "MIO42", "MIO44", "MIO45", "MIO46",
+ "MIO47", "MIO49", "MIO50", "MIO51";
+ bias-disable;
+ };
+ };
};
&sdhci1 {
@@ -221,3 +281,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
+
+&usb0 {
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ usb-phy = <&usb_phy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
+};
--
2.2.2
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[PATCH 1/5] ARM: dts: zynq: Split out common Parallella bits
This prepares for the USB-less Microserver edition as well as
headless vs. HDMI bitstreams.
Cc: Ola Jeppsson
Signed-off-by: Andreas Färber
---
arch/arm/boot/dts/zynq-parallella.dts | 80 +-
.../{zynq-parallella.dts => zynq-parallella1.dtsi} | 3 +-
2 files changed, 3 insertions(+), 80 deletions(-)
copy arch/arm/boot/dts/{zynq-parallella.dts => zynq-parallella1.dtsi} (97%)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index 0ebd2107022b..99ee6551ae8d 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -1,11 +1,6 @@
/*
* Copyright (c) 2014 SUSE LINUX Products GmbH
- *
- * Derived from zynq-zed.dts:
- *
- * Copyright (C) 2011 Xilinx
- * Copyright (C) 2012 National Instruments Corp.
- * Copyright (C) 2013 Xilinx
+ * Copyright (c) 2015 SUSE Linux GmbH
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -17,79 +12,8 @@
* GNU General Public License for more details.
*/
/dts-v1/;
-/include/ "zynq-7000.dtsi"
+#include "zynq-parallella1.dtsi"
/ {
model = "Adapteva Parallella Board";
- compatible = "adapteva,parallella", "xlnx,zynq-7000";
-
- aliases {
- ethernet0 = &gem0;
- serial0 = &uart1;
- };
-
- memory {
- device_type = "memory";
- reg = <0x0 0x4000>;
- };
-
- chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk
root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
- linux,stdout-path = "/amba/serial@e0001000";
- };
-};
-
-&clkc {
- fclk-enable = <0xf>;
- ps-clk-frequency = <>;
-};
-
-&gem0 {
- status = "okay";
- phy-mode = "rgmii-id";
- phy-handle = <ðernet_phy>;
-
- ethernet_phy: ethernet-phy@0 {
- /* Marvell 88E1318 */
- compatible = "ethernet-phy-id0141.0e90",
-"ethernet-phy-ieee802.3-c22";
- reg = <0>;
- marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
- <0x3 0x11 0xfff0 0xa>;
- };
-};
-
-&i2c0 {
- status = "okay";
-
- isl9305: isl9305@68 {
- compatible = "isil,isl9305";
- reg = <0x68>;
-
- regulators {
- dcd1 {
- regulator-name = "VDD_DSP";
- regulator-always-on;
- };
- dcd2 {
- regulator-name = "1P35V";
- regulator-always-on;
- };
- ldo1 {
- regulator-name = "VDD_ADJ";
- };
- ldo2 {
- regulator-name = "VDD_GPIO";
- regulator-always-on;
- };
- };
- };
-};
-
-&sdhci1 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella1.dtsi
similarity index 97%
copy from arch/arm/boot/dts/zynq-parallella.dts
copy to arch/arm/boot/dts/zynq-parallella1.dtsi
index 0ebd2107022b..7c1206f928bc 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella1.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014 SUSE LINUX Products GmbH
+ * Copyright (c) 2015 SUSE Linux GmbH
*
* Derived from zynq-zed.dts:
*
@@ -16,11 +17,9 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
- model = "Adapteva Parallella Board";
compatible = "adapteva,parallella", "xlnx,zynq-7000";
aliases {
--
2.2.2
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Re: [PATCH 0/7] OPP: Introduce OPP bindings V2 and supporting code
On 02/11, Viresh Kumar wrote: > Now that I have received an verbal Ack from Rob Herring (in a personal > conversation) about the bindings, I am showing how the code looks like with > these new bindings. > > Some part is still now done: > - Interface for adding new detailed OPPs from platform code instead of DT > - Providing cpufreq helpers for the next OPPs > - Providing regulator helpers for the target/min/max ranges > > Please provide feedback on how this looks like.. > Here's some feedback on how we can't use OPPs (and OPPs in DT) on qcom platforms. On these platforms the OPPs are not always frequency voltage pairs. Sometimes they're a frequency voltage voltage triplet, or frequency voltage current triplet. I know that the OPP framework in the kernel doesn't support more than frequency voltage pairs, but that doesn't mean it can't in the future, and if it needs to do so the DT bindings shouldn't need a v3 revision. Furthermore, we have a large number of OPP sets that apply to different speed bins and silicon characteristics of the SoC. In our systems we read some efuses (an eeprom of sorts) that tell us to use a certain set of OPPs because the silicon is so fast or has these certain characteristics. The bootloader is *not* reading these fuses and populating OPPs in DT. So right now we just put all these custom OPPish tables in DT and then pick the right one based on a node name match constructed from the bits we read in the efuses. How can we express this in DT with these bindings? For example, on msm8974 we have a frequency voltage current triplet and there are 18 different sets of these triplets, each with 23 triplets per set. We could encode all of these tables as a bunch of nodes with compatible = "operating-points-v2" but how do we pick the right one to assign and populate for the CPU devices? Do we need some sort of opp-fuse-map table that encodes the information we want somewhere? qcom,opp-fuse-map = , ... but where do we put it? In the cpus node? Or maybe we can keep doing the node name matching? That would required dropping the oppN convention. Or take msm8916 as another example. On this device the voltage for a few frequencies comes from the efuses and then we interpolate the rest of the frequency voltage pairs. The speed bins are picked from another set of efuses so we can do the interpolation. Unfortunately we don't encode the frequency in the fuses, so we rely on a handful of tables being defined somewhere so that we know speed bin 0 means this set of frequencies and speed bin 1 means this set of frequencies. How do we encode this in DT? Should we have the frequencies as OPPs and leave the voltage part out, filling it in at runtime based on what we read out of the efuses? I assume it's desirable to have the frequency tables in DT but we could also have them in the driver and if we did that there wouldn't be any shared-opp property to set and have the cpufreq-dt driver use to figure out clock sharing. Also sometimes we need to correlate OPPs between each other. For example on msm8960/apq8064 if the CPU is running at a frequency and voltage, the L2 needs to be running at another frequency, voltage, and voltage (triplet). The L2 is in two power domains but it only has one clock. Can/should this be expressed in DT? It certainly seems that it's at least easier to add it on as a feature because OPPs are nodes instead of an array. But we need to make sure we can support multiple regulators somehow, either through correlated OPPs and multiple OPPs for a single device or by being able to say opp-0-microvolt, opp-1-microvolt. I would guess something similar could happen if there were two clocks and one regulator although I've never seen such a scenario in practice. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 02/10, Stephen Boyd wrote:
> Scorpion supports a set of local performance monitor event
> selection registers (LPM) sitting behind a cp15 based interface
> that extend the architected PMU events to include Scorpion CPU
> and Venum VFP specific events. To use these events the user is
> expected to program the lpm register with the event code shifted
> into the group they care about and then point the PMNx event at
> that region+group combo by writing a LPMn_GROUPx event. Add
> support for this hardware.
>
> Note: the raw event number is a pure software construct that
> allows us to map the multi-dimensional number space of regions,
> groups, and event codes into a flat event number space suitable
> for use by the perf framework.
>
> This is based on code originally written by Ashwin Chaugule and
> Neil Leeder [1] massed to become similar to the Krait PMU support
> code.
>
> [1]
> https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
>
> Cc: Neil Leeder
> Cc: Ashwin Chaugule
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/pmu.txt | 2 +
> arch/arm/kernel/perf_event_cpu.c | 2 +
> arch/arm/kernel/perf_event_v7.c | 395
> ++
> 3 files changed, 399 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
> b/Documentation/devicetree/bindings/arm/pmu.txt
> index 75ef91d08f3b..6e54a9d88b7a 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.txt
> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
> @@ -18,6 +18,8 @@ Required properties:
> "arm,arm11mpcore-pmu"
> "arm,arm1176-pmu"
> "arm,arm1136-pmu"
> + "qcom,scorpion-pmu"
> + "qcom,scorpion-mp-pmu"
> "qcom,krait-pmu"
> - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a
> per-cpu
> interrupt (PPI) then 1 interrupt should be specified.
> diff --git a/arch/arm/kernel/perf_event_cpu.c
> b/arch/arm/kernel/perf_event_cpu.c
> index dd9acc95ebc0..010ffd241434 100644
> --- a/arch/arm/kernel/perf_event_cpu.c
> +++ b/arch/arm/kernel/perf_event_cpu.c
> @@ -242,6 +242,8 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
> {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
> {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
> {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
> + {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
> + {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_pmu_init},
> {.compatible = "qcom,krait-pmu",.data = krait_pmu_init},
> {},
> };
> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index 84a3ec3bc592..14bc8726f554 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -140,6 +140,23 @@ enum krait_perf_types {
> KRAIT_PERFCTR_L1_DTLB_ACCESS= 0x12210,
> };
>
> +/* ARMv7 Scorpion specific event types */
> +enum scorpion_perf_types {
> + SCORPION_LPM0_GROUP0= 0x4c,
> + SCORPION_LPM1_GROUP0= 0x50,
> + SCORPION_LPM2_GROUP0= 0x54,
> + SCORPION_L2LPM_GROUP0 = 0x58,
> + SCORPION_VLPM_GROUP0= 0x5c,
> +
> + SCORPION_ICACHE_ACCESS = 0x10053,
> + SCORPION_ICACHE_MISS= 0x10052,
> +
> + SCORPION_DTLB_ACCESS= 0x12013,
> + SCORPION_DTLB_MISS = 0x12012,
> +
> + SCORPION_ITLB_MISS = 0x12021,
> +};
> +
> /*
> * Cortex-A8 HW events mapping
> *
> @@ -482,6 +499,51 @@ static const unsigned
> krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> };
>
> /*
> + * Scorpion HW events mapping
> + */
> +static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
> + PERF_MAP_ALL_UNSUPPORTED,
> + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
> + [PERF_COUNT_HW_INSTRUCTIONS]= ARMV7_PERFCTR_INSTR_EXECUTED,
> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
> + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
> + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
> +};
> +
> +static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> + [PERF_COUNT_HW_CACHE_OP_MAX]
> + [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
> + PERF_CACHE_MAP_ALL_UNSUPPORTED,
> + /*
> + * The performance counters don't differentiate between read and write
> + * accesses/misses so this isn't strictly correct, but it's the best we
> + * can do. Writes and reads get combined.
> + */
> + [C(L1D)][C(OP_
Re: [PATCH v2 1/2] mmc: dw_mmc: fix bug that cause 'Timeout sending command'
Hi Andrzej,
On Wed, Feb 11, 2015 at 5:28 PM, Andrzej Hajda wrote:
> Hi Alim,
>
> On 02/11/2015 03:57 AM, Addy wrote:
>>
>> On 2015/02/10 23:22, Alim Akhtar wrote:
>>> Hi Addy,
>>>
>>> On Mon, Feb 9, 2015 at 12:55 PM, Addy Ke wrote:
Because of some uncertain factors, such as worse card or worse hardware,
DAT[3:0](the data lines) may be pulled down by card, and mmc controller
will be in busy state. This should not happend when mmc controller
send command to update card clocks. If this happends, mci_send_cmd will
be failed and we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 4d2e3c2..b0b57e3 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -100,6 +100,7 @@ struct idmac_desc {
};
#endif /* CONFIG_MMC_DW_IDMAC */
+static int dw_mci_card_busy(struct mmc_host *mmc);
static bool dw_mci_reset(struct dw_mci *host);
static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -888,6 +889,31 @@ static void mci_send_cmd(struct dw_mci_slot *slot,
u32 cmd, u32 arg)
cmd, arg, cmd_status);
}
+static void dw_mci_wait_busy(struct dw_mci_slot *slot)
+{
+ struct dw_mci *host = slot->host;
+ unsigned long timeout = jiffies + msecs_to_jiffies(500);
+
>>> Why 500 msec?
>> This timeout value is the same as mci_send_cmd:
>> static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
>> {
>> struct dw_mci *host = slot->host;
>> unsigned long timeout = jiffies + msecs_to_jiffies(500);
>>
>> }
>>
>> I have not clear that which is suitable.
>> Do you have any suggestion on it?
>>>
+ do {
+ if (!dw_mci_card_busy(slot->mmc))
+ return;
+ cpu_relax();
+ } while (time_before(jiffies, timeout));
+
+ dev_err(host->dev, "Data busy (status %#x)\n",
+ mci_readl(slot->host, STATUS));
+
+ /*
+* Data busy, this should not happend when mmc controller send
command
+* to update card clocks in non-volt-switch state. If it happends,
we
+* should reset controller to avoid getting "Timeout sending
command".
+*/
+ dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS);
+
>>> Why you need to reset all blocks? may be CTRL_RESET is good enough here.
>> I have tested on rk3288, if only reset ctroller, data busy bit will not
>> be cleaned,and we will still get
>>
>> "Timeout sending command".
>>
>>>
+ /* Fail to reset controller or still data busy, WARN_ON! */
+ WARN_ON(dw_mci_card_busy(slot->mmc));
+}
+
static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool
force_clkinit)
{
struct dw_mci *host = slot->host;
@@ -899,6 +925,8 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot,
bool force_clkinit)
/* We must continue to set bit 28 in CMD until the change is
complete */
if (host->state == STATE_WAITING_CMD11_DONE)
sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
+ else
+ dw_mci_wait_busy(slot);
>>> hmm...I would suggest you to call dw_mci_wait_busy() from inside
>>> mci_send_cmd(), seems like dw_mmc hangs while sending update clock cmd
>>> in multiple cases.see [1]
>>>
>>> [1]: http://permalink.gmane.org/gmane.linux.kernel.mmc/31140
>> I think this patch is more reasonable.
>> So I will resend patches based on this patch.
>> thank you!
>
> I have tested your patches instead [1] above and they do not solve my issue:
> Board: odroid-xu3/exynos5422/dw_mmc_250a.
> MMC card: absent, broken-cd quirk
> SD card: present
>
I doubt $SUBJECT patch in current form can resolve you issue. I have
already given comments on $subject patch.
Can you try out below patch (I have not tested yet) on top of $SUBJECT patch?
===
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b0b57e3..ea87844 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -101,6 +101,7 @@ struct idmac_desc {
#endif /* CONFIG_MMC_DW_IDMAC */
static int dw_mci_card_busy(struct mmc_host *mmc);
+static void dw_mci_wait_busy(struct dw_mci_slot *slot);
static bool dw_mci_reset(struct dw_mci *host);
static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -874,16 +875,22 @@ static void mci_send_cmd(struct dw_mci_slot
*slot, u32 cmd, u32 arg)
struct dw_mci *host = slot->host;
unsigned long timeout = jiffies + msecs_to_
[PATCH] ARM: shmobile: silk: add Ether DT support
Define the SILK board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original patch by Vladimir Barinov
.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20150211-v3.19' tag of Simon Horman's
'renesas.git' repo. It depends on just posted SILK board initial DT patch in
order to apply, on just posted R8A7794 PFC DT patch in order to compile, and
on R8A7794 PFC driver patch in order for the pins to be configured.
arch/arm/boot/dts/r8a7794-silk.dts | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7794-silk.dts
===
--- renesas.orig/arch/arm/boot/dts/r8a7794-silk.dts
+++ renesas/arch/arm/boot/dts/r8a7794-silk.dts
@@ -22,7 +22,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = &scif2;
};
@@ -41,6 +41,16 @@
renesas,groups = "scif2_data";
renesas,function = "scif2";
};
+
+ ether_pins: ether {
+ renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+ renesas,function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ renesas,groups = "intc_irq8";
+ renesas,function = "intc";
+ };
};
&scif2 {
@@ -49,3 +59,19 @@
status = "okay";
};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
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[PATCH v2] ARM: shmobile: silk: initial device tree
Add the initial device tree for the R8A7794 SoC based SILK low cost board.
SCIF2 serial port support is included, so that the serial console can work.
Based on the original patch by Vladimir Barinov
.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20150211-v3.19' tag of Simon Horman's
'renesas.git' repo. It requires just posted R8A7794 PFC DT patch in order to
compile, and R8A7794 PFC driver patch in order for the pins to be configured.
Changes in version 2:
- removed "console=" parameter from the kernel command line;
- added PFC node with SCIF2 pins subnode and referred it from the SCIF2 node;
- rebased the patch
- mentioned the origin of patch in the changelog.
arch/arm/boot/dts/Makefile |1
arch/arm/boot/dts/r8a7794-silk.dts | 51 +
2 files changed, 52 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -421,6 +421,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += eme
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7794-alt.dtb \
+ r8a7794-silk.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk.dtb \
Index: renesas/arch/arm/boot/dts/r8a7794-silk.dts
===
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7794-silk.dts
@@ -0,0 +1,51 @@
+/*
+ * Device Tree Source for the SILK board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014-2015 Renesas Solutions Corp.
+ * Copyright (C) 2014-2015 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+
+/ {
+ model = "SILK";
+ compatible = "renesas,silk", "renesas,r8a7794";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = &scif2;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x4000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <2000>;
+};
+
+&pfc {
+ scif2_pins: serial2 {
+ renesas,groups = "scif2_data";
+ renesas,function = "scif2";
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
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[PATCH] ARM: shmobile: r8a7794: add PFC DT support
Define the generic R8A7794 part of the PFC device node.
Based on original patch by Hisashi Nakamura .
Signed-off-by: Sergei Shtylyov
---
This patch is against 'renesas-devel-20150211-v3.19' tag of Simon Horman's
'renesas.git' repo. It needs the R8A7794 PFC driver patch in order to work.
arch/arm/boot/dts/r8a7794.dtsi |6 ++
1 file changed, 6 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7794.dtsi
===
--- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi
+++ renesas/arch/arm/boot/dts/r8a7794.dtsi
@@ -107,6 +107,12 @@
<0 17 IRQ_TYPE_LEVEL_HIGH>;
};
+ pfc: pin-controller@e606 {
+ compatible = "renesas,pfc-r8a7794";
+ reg = <0 0xe606 0 0x11c>;
+ #gpio-range-cells = <3>;
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,rcar-dmac";
reg = <0 0xe670 0 0x2>;
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Re: [PATCH v1] of: calculate masks of the device based on dma-range size
On Wed, Feb 11, 2015 at 12:53:35PM -0500, Murali Karicheri wrote:
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index 314c8a9..167ad2d 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -90,10 +90,11 @@ void of_dma_configure(struct device *dev, struct
> device_node *np)
> struct iommu_ops *iommu;
>
> /*
> - * Set default dma-mask to 32 bit. Drivers are expected to setup
> - * the correct supported dma_mask.
> + * Set default coherent_dma_mask to 32 bit. Drivers are expected to
> + * setup the correct supported mask.
>*/
> - dev->coherent_dma_mask = DMA_BIT_MASK(32);
> + if (!dev->coherent_dma_mask)
> + dev->coherent_dma_mask = DMA_BIT_MASK(32);
>
> /*
>* Set it to coherent_dma_mask by default if the architecture
> @@ -102,6 +103,11 @@ void of_dma_configure(struct device *dev, struct
> device_node *np)
> if (!dev->dma_mask)
> dev->dma_mask = &dev->coherent_dma_mask;
>
> + /*
> + * Use default size to cover 32 bit. Drivers need to set this in DT
> + * to override the same.
> + */
> + size = 1ULL << 32;
I'm not sure this is needed since on error path the original code would
set the size to coherent_dma_mask.
> ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
> if (ret < 0) {
> dma_addr = offset = 0;
Here we already have (not seen in the context):
size = dev->coherent_dma_mask + 1;
> @@ -128,6 +134,15 @@ void of_dma_configure(struct device *dev, struct
> device_node *np)
>
> dev->dma_pfn_offset = offset;
>
> + /*
> + * Limit coherent and dma mask based on size and default mask
> + * set by the driver.
> + */
> + dev->coherent_dma_mask = min(dev->coherent_dma_mask,
> + DMA_BIT_MASK(ilog2(dma_addr + size)));
> + *dev->dma_mask = min((*dev->dma_mask),
> + DMA_BIT_MASK(ilog2(dma_addr + size)));
> +
> coherent = of_dma_is_coherent(np);
> dev_dbg(dev, "device is%sdma coherent\n",
> coherent ? " " : " not ");
Otherwise it looks fine to me.
Reviewed-by: Catalin Marinas
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Re: [PATCH v2 1/2] Input: touchscreen-iproc: Add Broadcom iProc touchscreen driver
Pinging maintainers... Am I ok to go ahead with the current rotation
implementation? I haven't heard anything further. Any feedback on naming
conventions from DT people?
Thanks!
On 15-01-15 11:51 AM, Jonathan Richardson wrote:
> Hi Dmitry,
>
> On 15-01-14 10:07 PM, Dmitry Torokhov wrote:
>> On Wed, Jan 14, 2015 at 09:44:39PM -0800, Scott Branden wrote:
>>> On 15-01-14 05:02 PM, Dmitry Torokhov wrote:
Hi Jonathan,
On Fri, Dec 19, 2014 at 02:17:49PM -0800, Jonathan Richardson wrote:
> + if (of_property_read_u32(np, "scanning_period", &val) >= 0) {
> + if (val < 1 || val > 256) {
> + dev_err(dev, "scanning_period must be [1-256]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.scanning_period = val;
> + }
> +
> + if (of_property_read_u32(np, "debounce_timeout", &val) >= 0) {
> + if (val < 0 || val > 255) {
> + dev_err(dev, "debounce_timeout must be [0-255]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.debounce_timeout = val;
> + }
> +
> + if (of_property_read_u32(np, "settling_timeout", &val) >= 0) {
> + if (val < 0 || val > 11) {
> + dev_err(dev, "settling_timeout must be [0-11]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.settling_timeout = val;
> + }
> +
> + if (of_property_read_u32(np, "touch_timeout", &val) >= 0) {
> + if (val < 0 || val > 255) {
> + dev_err(dev, "touch_timeout must be [0-255]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.touch_timeout = val;
> + }
> +
> + if (of_property_read_u32(np, "average_data", &val) >= 0) {
> + if (val < 0 || val > 8) {
> + dev_err(dev, "average_data must be [0-8]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.average_data = val;
> + }
> +
> + if (of_property_read_u32(np, "fifo_threshold", &val) >= 0) {
> + if (val < 0 || val > 31) {
> + dev_err(dev, "fifo_threshold must be [0-31]\n");
> + return -EINVAL;
> + }
> + priv->cfg_params.fifo_threshold = val;
> + }
I think these are dveice specific and thus should have "brcm," prefix.
>>> I'm confused as to why we need the brcm prefix? Other device tree
>>> bindings we have for other drivers do not need such prefix.
>>
>> Properties that are not standard on the system (reg, interrupts,
>> clkocks, etc) or subsystem level customarily carry the vendor prefix so
>> that they do not clash with newly added global or subsystem properties.
>>
>>> Is this
>>> convention documented somewhere?
>>
>> Not sure. I glanced through Documentation/devicetree and do not see it
>> spelled out. Device tree overlords, what say you?
>
> Let me know. I haven't seen this before either. I will change the
> entries to use dashes though instead of underscores but will wait until
> these other issues are decided on before sending out another patch.
>
>>
> +
> + priv->ts_rotation = TS_ROTATION_0;
> + if (of_property_read_u32(np, "ts-rotation", &val) >= 0) {
> + priv->ts_rotation = val;
> + dev_dbg(dev, "ts rotation [%d] degrees\n",
> + 90 * priv->ts_rotation);
> + }
This I am not quite sure about - if we want rotation or swap+invert. You
are CCed on another email (tsc2007) that talks about need of generic
touchscreen transforms in input core/of bindings.
>>> Does such generic binding exist today? If not, I would like to go
>>> with this implementation and update to the new binding if/when it
>>> exists?
>>
>> Not yet but there several people interested. I think we have enough time
>> till 3.20 to hash it out properly.
>
> I think the rotation is simpler personally. Everyone would understand
> rotation refers to how it's oriented but I'm not sure everyone would
> immediately know how it is wired. Let me know what is decided and I'll
> make any changes required.
>
> Thanks,
> Jon
>
>
>>
>> Thanks.
>>
>
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Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 02/10, Ashwin Chaugule wrote: > Hi Stephen, > > On 10 February 2015 at 20:05, Stephen Boyd wrote: > > Scorpion supports a set of local performance monitor event > > selection registers (LPM) sitting behind a cp15 based interface > > that extend the architected PMU events to include Scorpion CPU > > and Venum VFP specific events. To use these events the user is > > expected to program the lpm register with the event code shifted > > into the group they care about and then point the PMNx event at > > that region+group combo by writing a LPMn_GROUPx event. Add > > support for this hardware. > > > > Note: the raw event number is a pure software construct that > > allows us to map the multi-dimensional number space of regions, > > groups, and event codes into a flat event number space suitable > > for use by the perf framework. > > > > This is based on code originally written by Ashwin Chaugule and > > Neil Leeder [1] massed to become similar to the Krait PMU support > > code. > > Thanks for taking this up! > Overall this series looks good to me, but from what I faintly > recollect, doesn't this (and the Krait pmu code) get affected by > powercollapse issues anymore? > e.g. > https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/arch/arm/kernel/perf_event_msm.c?h=msm-3.4&id=b5ca687960f0fea2f4735e83ca5c9543474c19de > Right now there isn't any power collapse support in mainline so there's no immediate problem. Once we add power collapse support (i.e. cpuidle) to the Scorpion and Krait platforms we'll need to do something in the perf event code to properly maintain the counts across idle. I imagine it would be done by registering for cpu_pm notifications and then doing the save/restore on CPU_PM_ENTER and CPU_PM_EXIT. At least, that's what you started doing in this patch[1]. And then it seems the patch you mention came after that and actually did the save/restore of the counts. [1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/?h=msm-3.4&id=464983a7e991a484cac0bc0885cee4fee318d659 -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: dts: zynq: Add linux, stdout-path and stdout-path
Am 11.02.2015 um 15:25 schrieb Michal Simek:
> On 02/11/2015 01:40 PM, Mark Rutland wrote:
>> On Wed, Feb 11, 2015 at 12:29:02PM +, Michal Simek wrote:
>>> parallella - Use reference instead of hardcoded path
>>> (linux,stdout-path)
>>>
>>> stdout-path is used by bootloader to identify console.
>>>
>>> Signed-off-by: Michal Simek
>>> ---
>>>
>>> U-Boot driver model requires stdout-path.
>>> ---
>>> arch/arm/boot/dts/zynq-parallella.dts | 3 ++-
>>> arch/arm/boot/dts/zynq-zc702.dts | 2 ++
>>> arch/arm/boot/dts/zynq-zc706.dts | 2 ++
>>> arch/arm/boot/dts/zynq-zed.dts| 2 ++
>>> arch/arm/boot/dts/zynq-zybo.dts | 2 ++
>>> 5 files changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/zynq-parallella.dts
>>> b/arch/arm/boot/dts/zynq-parallella.dts
>>> index 6a5f51daa708..45228a427006 100644
>>> --- a/arch/arm/boot/dts/zynq-parallella.dts
>>> +++ b/arch/arm/boot/dts/zynq-parallella.dts
>>> @@ -35,7 +35,8 @@
>>>
>>> chosen {
>>> bootargs = "console=ttyPS0,115200 earlyprintk
>>> root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>>> - linux,stdout-path = "/amba/serial@e0001000";
>>> + linux,stdout-path = &uart1;
>>> + stdout-path = &uart1;
>>
>> Given that you added aliases in the last patch, you can use that to
>> refer to the serial:
>>
>> stdout-path - "serial0:115200n8";
>>
>> With or without the alias you can encode the UART configuration here
>> too:
>>
>> stdout-path = "/amba/serial@e0001000:115200n8"
>
> let me check this configuration if it is supported by u-boot.
I would be surprised if either is supported - my Parallella ships:
U-Boot 2012.10-3-g792c31c (Jan 03 2014 - 12:24:08)
and upstream U-Boot still doesn't have support for the Parallella.
>> Which makes the expected configuration explicit without relying on the
>> Linux-specific bootargs.
>>
>> Is there any reason to keep linux,stdout-path?
>
> Agree when stdout-patch is defined there is no reason to use
> linux,stdout-patch.
It's not used, it was added on reviewers' request at the time. Feel free
to drop. But again, we are bound for patch conflict here.
Regards,
Andreas
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Re: [PATCH 0/2] GPIO joystick driver
On Wed, Feb 11, 2015 at 08:49:16AM +, Holmberg, Hans wrote: > > > > As far as I can tell, there is no way to specify values for ABS-"keys" > > > > in the device tree binding. > > > > > > It may not be present in device tree binding, but the driver does > > > support it, so I would rather extend the binding than have a brand new > > driver. > > > > All right, I find it a bit like whacking a round peg down a square hole, > > but I'll > > head down that path and see where it leads. > > > > This is what I've found: > > A digital joystick driver needs to report three states per axis: min, > max and neutral. The hardware only have two signals per axis(i.e. up > and down) however. See http://wiki.icomp.de/wiki/DB9-Joystick > > This makes gpio-keys pretty much impossible to use for joysticks - as > the driver only reports abs-events when a button/key is pressed, how > would the neutral state be reported? (as there is no signal for > "neutral") > > Even if through some hackery the driver would be modified to report a > special neutral event if all "buttons/keys" for that axis are not > pressed, what value should be reported? An average of the values for > that axis? Also, reporting such an implicit neutral event would > break the behavior of existing abs-reporting instances, right? You have 2 gpio per axis, and since you can't measure how "far" down the axis you have moved the driver should only report values -1, 0, 1 per axis. You start at neutral position, and move right. IRQ for right gpio is fired and you report EV_ABS/ABS_X/1. Then you start moving to the left, gpio IRQ fires (you want it to trigger on both edges) and you report EV_ABS/ABS_X/0. You continue moving to the left and IRQ for left gpio fires up and you report EV_ABS/ABS_X/-1. This assumes that you assign EV_ABS/ABS_X and value 1 for right gpio and EV_ABS/ABS_X and value -1 for left gpio. Thanks. -- Dmitry -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v1] of: calculate masks of the device based on dma-range size
This patch update of_dma_configure() API to calculate the
masks (dma_mask and coherent_dma_mask) based on the dma-range
values set in DT for the device. Also limit the mask to lower
of the default mask and mask calculated.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Bjorn Helgaas
Cc: Will Deacon
Cc: Russell King
Cc: Arnd Bergmann
Cc: Suravee Suthikulpanit
Signed-off-by: Murali Karicheri
---
- apply on top of the series "[PATCH v6 0/7] PCI: get DMA configuration
from parent device" at www.spinics.net/lists/linux-pci/msg38699.html
v1 - updated based on comments. Reverted to original
code for of_dma_get_range() within the of_dma_configure()
drivers/of/device.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 314c8a9..167ad2d 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -90,10 +90,11 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
struct iommu_ops *iommu;
/*
-* Set default dma-mask to 32 bit. Drivers are expected to setup
-* the correct supported dma_mask.
+* Set default coherent_dma_mask to 32 bit. Drivers are expected to
+* setup the correct supported mask.
*/
- dev->coherent_dma_mask = DMA_BIT_MASK(32);
+ if (!dev->coherent_dma_mask)
+ dev->coherent_dma_mask = DMA_BIT_MASK(32);
/*
* Set it to coherent_dma_mask by default if the architecture
@@ -102,6 +103,11 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
if (!dev->dma_mask)
dev->dma_mask = &dev->coherent_dma_mask;
+ /*
+* Use default size to cover 32 bit. Drivers need to set this in DT
+* to override the same.
+*/
+ size = 1ULL << 32;
ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
if (ret < 0) {
dma_addr = offset = 0;
@@ -128,6 +134,15 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
dev->dma_pfn_offset = offset;
+ /*
+* Limit coherent and dma mask based on size and default mask
+* set by the driver.
+*/
+ dev->coherent_dma_mask = min(dev->coherent_dma_mask,
+DMA_BIT_MASK(ilog2(dma_addr + size)));
+ *dev->dma_mask = min((*dev->dma_mask),
+DMA_BIT_MASK(ilog2(dma_addr + size)));
+
coherent = of_dma_is_coherent(np);
dev_dbg(dev, "device is%sdma coherent\n",
coherent ? " " : " not ");
--
1.7.9.5
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[PATCH 3/5] drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panel
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: Philipp Zabel
---
.../bindings/panel/ampire,am800480r3tmqwa1h.txt| 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 ++
2 files changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt
diff --git
a/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt
b/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt
new file mode 100644
index 000..83e2cae
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/ampire,am800480r3tmqwa1h.txt
@@ -0,0 +1,7 @@
+Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "ampire,am800480r3tmqwa1h"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 1d9cb6f..aac9dc1 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -327,6 +327,31 @@ static void panel_simple_shutdown(struct device *dev)
panel_simple_disable(&panel->base);
}
+static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
+ .clock = 3,
+ .hdisplay = 800,
+ .hsync_start = 800 + 0,
+ .hsync_end = 800 + 0 + 255,
+ .htotal = 800 + 0 + 255 + 0,
+ .vdisplay = 480,
+ .vsync_start = 480 + 2,
+ .vsync_end = 480 + 2 + 45,
+ .vtotal = 480 + 2 + 45 + 0,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+};
+
+static const struct panel_desc ampire_am800480r3tmqwa1h = {
+ .modes = &ire_am800480r3tmqwa1h_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 152,
+ .height = 91,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode auo_b101aw03_mode = {
.clock = 51450,
.hdisplay = 1024,
@@ -782,6 +807,9 @@ static const struct panel_desc samsung_ltn101nt05 = {
static const struct of_device_id platform_of_match[] = {
{
+ .compatible = "ampire,am800480r3tmqwa1h",
+ .data = &ire_am800480r3tmqwa1h,
+ }, {
.compatible = "auo,b101aw03",
.data = &auo_b101aw03,
}, {
--
2.1.4
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[PATCH 5/5] drm/panel: Add support for OrtusTech COM43H4M85ULC panel
This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: Philipp Zabel
---
.../bindings/panel/ortustech,com43h4m85ulc.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 27 ++
2 files changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt
diff --git
a/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt
b/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt
new file mode 100644
index 000..de19e93
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/ortustech,com43h4m85ulc.txt
@@ -0,0 +1,7 @@
+OrtusTech COM43H4M85ULC Blanview 3.7" TFT-LCD panel
+
+Required properties:
+- compatible: should be "ortustech,com43h4m85ulc"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index aac9dc1..da7c8ab 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -782,6 +782,30 @@ static const struct panel_desc lg_lp129qe = {
},
};
+static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
+ .clock = 25000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 10,
+ .hsync_end = 480 + 10 + 10,
+ .htotal = 480 + 10 + 10 + 15,
+ .vdisplay = 800,
+ .vsync_start = 800 + 3,
+ .vsync_end = 800 + 3 + 3,
+ .vtotal = 800 + 3 + 3 + 3,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc ortustech_com43h4m85ulc = {
+ .modes = &ortustech_com43h4m85ulc_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 56,
+ .height = 93,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+};
+
static const struct drm_display_mode samsung_ltn101nt05_mode = {
.clock = 54030,
.hdisplay = 1024,
@@ -867,6 +891,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "lg,lp129qe",
.data = &lg_lp129qe,
}, {
+ .compatible = "ortustech,com43h4m85ulc",
+ .data = &ortustech_com43h4m85ulc,
+ }, {
.compatible = "samsung,ltn101nt05",
.data = &samsung_ltn101nt05,
}, {
--
2.1.4
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[PATCH 4/5] of: Add vendor prefix for Ortus Technology Co., Ltd.
Add Ortus Technology Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ca9ea1..a698268 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -121,6 +121,7 @@ nvidia NVIDIA nxpNXP Semiconductors onnn ON Semiconductor Corp. opencores OpenCores.org +ortustech Ortus Technology Co., Ltd. panasonic Panasonic Corporation parade Parade Technologies Inc. pericomPericom Technology Inc. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] drm/panel: Add bus format for Giantplus GPG482739QS5 panel
From: Philipp Zabel
This patch adds the bus_format field to the GPG482739QS5 panel structure.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 39806c3..1d9cb6f 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -615,6 +615,7 @@ static const struct panel_desc giantplus_gpg482739qs5 = {
.width = 95,
.height = 54,
},
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
};
static const struct drm_display_mode hannstar_hsd070pww1_mode = {
--
2.1.4
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[PATCH 2/5] of: Add vendor prefix for Ampire Co., Ltd.
Add Ampire Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index c0333a9..1ca9ea1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -15,6 +15,7 @@ altr Altera Corp. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amdAdvanced Micro Devices (AMD), Inc. amlogicAmlogic, Inc. +ampire Ampire Co., Ltd. amsAMS AG amstaosAMS-Taos Inc. apmApplied Micro Circuits Corporation (APM) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] irqchip: Add DT binding doc for the virtual irq demuxer chip
On Wed, 11 Feb 2015 17:13:13 + Mark Rutland wrote: > On Wed, Feb 11, 2015 at 04:42:22PM +, Rafael J. Wysocki wrote: > > On Wednesday, February 11, 2015 05:15:15 PM Boris Brezillon wrote: > > > On Wed, 11 Feb 2015 15:57:20 + > > > Mark Rutland wrote: > > > > > > > [...] > > > > > > > > > > > > So for the flag at request time approach to work, all the > > > > > > > > drivers using > > > > > > > > the interrupt would have to flag they're safe in that context. > > > > > > > > > > > > > > Something like IRQF_"I can share the line with a timer" I guess? > > > > > > > That wouldn't > > > > > > > hurt and can be checked at request time even. > > > > > > > > > > > > I guess that would have to imply IRQF_SHARED, so we'd have something > > > > > > like: > > > > > > > > > > > > IRQF_SHARED_SUSPEND_OK - This handler is safe to call spuriously > > > > > > during > > > > > > suspend in the case the line is shared. The > > > > > > handler will not access unavailable hardware > > > > > > or kernel infrastructure during this period. > > > > > > > > > > > > #define __IRQF_SUSPEND_SPURIOUS 0x0004 > > > > > > #define IRQF_SHARED_SUSPEND_OK (IRQF_SHARED | > > > > > > __IRQF_SUSPEND_SPURIOUS) > > > > > > > > > > What about > > > > > > > > > > #define __IRQF_TIMER_SIBLING_OK 0x0004 > > > > > #define IRQF_SHARED_TIMER_OK(IRQF_SHARED | > > > > > __IRQF_TIMER_SIBLING_OK) > > > > > > > > > > The "suspend" part is kind of a distraction to me here, because that > > > > > really > > > > > only is about sharing an IRQ with a timer and the "your interrupt > > > > > handler > > > > > may be called when the device is suspended" part is just a > > > > > consequence of that. > > > > > > > > My rationale was that you didn't really care who else was using the IRQ > > > > (e.g. the timer); you're just stating that you can survive being called > > > > during suspend (which is what the driver may need to check for in the > > > > handler if the device happens to be powered down or whatever). > > > > > > > > So I guess I see it the other way around. This is essentially claiming > > > > we can handle sharing with IRQF_NO_SUSPEND rather than IRQF_TIMER. > > > > > > > > > So IMO it's better to have "TIMER" in the names to avoid encouraging > > > > > people to > > > > > abuse this for other purposes not related to timers. > > > > > > > > In the end a name is a name, and if you think IRQF_SHARED_TIMER_OK is > > > > better I shan't complain. > > > > > > > > The fundamental issue I'm concerned with is addressed by this approach. > > > > > > Okay then, is anyone taking care of submitting such a patch (Mark ?) ? > > > > Well, I guess I should take the responsibility for that. :-) > > > > I'll try to cut one later today or tomorrow unless someone else beats me to > > that. > > I had a go at the core part below. Does it look like what you had in > mind? > > I've given it a go on a hacked-up platform, but I don't have any at91 > stuff to test with, so I haven't bothered with the driver portions just > yet. > > Thanks, > Mark. > > >8 > From 2d9013517637bb567fbcde3e20797cb2fab1c4c5 Mon Sep 17 00:00:00 2001 > From: Mark Rutland > Date: Wed, 11 Feb 2015 16:44:06 + > Subject: [PATCH] genirq: allow safe sharing of irqs during suspend > > In some cases a physical IRQ line may be shared between devices from > which we expect interrupts during suspend (e.g. timers) and those we do > not (e.g. anything we cut the power to). Where a driver did not request > the interrupt with IRQF_NO_SUSPEND, it's unlikely that it can handle > being called during suspend, and where the IRQ PM code detects a > mismatch it produces a loud warning (via WARN_ON_ONCE). > > In a small set of cases the handlers for the devices other than timers > can tolerate being called during suspend time. In these cases the > warning is spurious, and masks other potentially unsafe mismatches as it > is only printed for the first mismatch detected. As the behaviour of the > handlers is an implementation detail, we cannot rely on external data to > decide when it is safe for a given interrupt line to be shared in this > manner. > > This patch adds a new flag, IRQF_SHARED_TIMER_OK, which drivers can use > when requesting an IRQ to state that they can cope if the interrupt is > shared with a timer driver (and hence may be raised during suspend). The > PM code is updated to only warn when a mismatch occurs and at least one > irqaction has neither asked to be called during suspend or has stated it > is safe to be called during suspend. > > This reduces the set of warnings to those cases where there is a real > problem. While it is possible that this flag may be abused, any such > abuses will be explicit in the kernel source and can be detected. > > Cc: Boris Brezillon > Cc: Jason Cooper > Cc: Nicolas Ferre > Cc: Peter Zijlstra > Cc: Raf
Re: [PATCH v4 02/11] ARM: tegra: Move out nyan-generic parts out from the nyan-big DT
Hi Tomeu, On Wed, Feb 11, 2015 at 7:06 AM, Tomeu Vizoso wrote: > In preparation for adding the DT for the nyan-blaze board. > > Signed-off-by: Tomeu Vizoso Maybe it's worth pulling the common pinmux bits into nyan.dtsi as well? Otherwise, Acked-by: Andrew Bresticker -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: zynq: Add missing alias node for zybo and parallella
Am 11.02.2015 um 13:29 schrieb Michal Simek:
> Add missing alias node.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/boot/dts/zynq-parallella.dts | 5 +
> arch/arm/boot/dts/zynq-zybo.dts | 5 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-parallella.dts
> b/arch/arm/boot/dts/zynq-parallella.dts
> index ab1dc0a56cdd..6a5f51daa708 100644
> --- a/arch/arm/boot/dts/zynq-parallella.dts
> +++ b/arch/arm/boot/dts/zynq-parallella.dts
> @@ -23,6 +23,11 @@
> model = "Adapteva Parallella Board";
> compatible = "adapteva,parallella", "xlnx,zynq-7000";
>
> + aliases {
> + ethernet0 = &gem0;
> + serial0 = &uart1;
> + };
> +
> memory {
> device_type = "memory";
> reg = <0x0 0x4000>;
[snip]
Reviewed-by: Andreas Färber
Please CC me next time, as I am refactoring this file into a .dtsi for
adding the USB nodes. I'll rebase on this one then.
Regards,
Andreas
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Re: [PATCH v4 09/11] ARM: tegra: add support for warm reset GPIO
Hi Tomeu, On Wed, Feb 11, 2015 at 7:06 AM, Tomeu Vizoso wrote: > From: Andrew Bresticker > > Allow for a warm reset GPIO to be passed to the PMC driver via DT > which will be used to reset the system instead of writing to PMC_CTRL. > The GPIO will be asserted at reset time and, if this fails to reset > the system, we'll fall back to using PMC_CTRL. > > Signed-off-by: Andrew Bresticker > [tomeu.viz...@collabora.com: Rebased] > Signed-off-by: Tomeu Vizoso There's actually gpio-restart driver now, which I think is what you want instead of this. See drivers/power/reset/gpio-restart.c. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] irqchip: Add DT binding doc for the virtual irq demuxer chip
On Wed, Feb 11, 2015 at 04:38:23PM +, Boris Brezillon wrote: > On Wed, 11 Feb 2015 16:32:31 + > Mark Rutland wrote: > > > On Wed, Feb 11, 2015 at 04:15:15PM +, Boris Brezillon wrote: > > > On Wed, 11 Feb 2015 15:57:20 + > > > Mark Rutland wrote: > > > > > > > [...] > > > > > > > > > > > > So for the flag at request time approach to work, all the > > > > > > > > drivers using > > > > > > > > the interrupt would have to flag they're safe in that context. > > > > > > > > > > > > > > Something like IRQF_"I can share the line with a timer" I guess? > > > > > > > That wouldn't > > > > > > > hurt and can be checked at request time even. > > > > > > > > > > > > I guess that would have to imply IRQF_SHARED, so we'd have something > > > > > > like: > > > > > > > > > > > > IRQF_SHARED_SUSPEND_OK - This handler is safe to call spuriously > > > > > > during > > > > > > suspend in the case the line is shared. The > > > > > > handler will not access unavailable hardware > > > > > > or kernel infrastructure during this period. > > > > > > > > > > > > #define __IRQF_SUSPEND_SPURIOUS 0x0004 > > > > > > #define IRQF_SHARED_SUSPEND_OK (IRQF_SHARED | > > > > > > __IRQF_SUSPEND_SPURIOUS) > > > > > > > > > > What about > > > > > > > > > > #define __IRQF_TIMER_SIBLING_OK 0x0004 > > > > > #define IRQF_SHARED_TIMER_OK(IRQF_SHARED | > > > > > __IRQF_TIMER_SIBLING_OK) > > > > > > > > > > The "suspend" part is kind of a distraction to me here, because that > > > > > really > > > > > only is about sharing an IRQ with a timer and the "your interrupt > > > > > handler > > > > > may be called when the device is suspended" part is just a > > > > > consequence of that. > > > > > > > > My rationale was that you didn't really care who else was using the IRQ > > > > (e.g. the timer); you're just stating that you can survive being called > > > > during suspend (which is what the driver may need to check for in the > > > > handler if the device happens to be powered down or whatever). > > > > > > > > So I guess I see it the other way around. This is essentially claiming > > > > we can handle sharing with IRQF_NO_SUSPEND rather than IRQF_TIMER. > > > > > > > > > So IMO it's better to have "TIMER" in the names to avoid encouraging > > > > > people to > > > > > abuse this for other purposes not related to timers. > > > > > > > > In the end a name is a name, and if you think IRQF_SHARED_TIMER_OK is > > > > better I shan't complain. > > > > > > > > The fundamental issue I'm concerned with is addressed by this approach. > > > > > > Okay then, is anyone taking care of submitting such a patch (Mark ?) ? > > > > I'll have the core patch shortly. > > > > I'll need to ask for your help tagging the relevant drivers and testing. > > For the list of impacted drivers, you can have a look at this series [1] > (patches 2 to 5), and I'll take care of the testing part once every one > has agreed on the solution ;-). > > [1]https://lkml.org/lkml/2014/12/15/552 Thanks for the link. I'll take a look at this once Rafael's given the core patch a once-over. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] irqchip: Add DT binding doc for the virtual irq demuxer chip
On Wed, Feb 11, 2015 at 04:42:22PM +, Rafael J. Wysocki wrote: > On Wednesday, February 11, 2015 05:15:15 PM Boris Brezillon wrote: > > On Wed, 11 Feb 2015 15:57:20 + > > Mark Rutland wrote: > > > > > [...] > > > > > > > > > > So for the flag at request time approach to work, all the drivers > > > > > > > using > > > > > > > the interrupt would have to flag they're safe in that context. > > > > > > > > > > > > Something like IRQF_"I can share the line with a timer" I guess? > > > > > > That wouldn't > > > > > > hurt and can be checked at request time even. > > > > > > > > > > I guess that would have to imply IRQF_SHARED, so we'd have something > > > > > like: > > > > > > > > > > IRQF_SHARED_SUSPEND_OK - This handler is safe to call spuriously > > > > > during > > > > >suspend in the case the line is shared. The > > > > >handler will not access unavailable hardware > > > > >or kernel infrastructure during this period. > > > > > > > > > > #define __IRQF_SUSPEND_SPURIOUS 0x0004 > > > > > #define IRQF_SHARED_SUSPEND_OK (IRQF_SHARED | > > > > > __IRQF_SUSPEND_SPURIOUS) > > > > > > > > What about > > > > > > > > #define __IRQF_TIMER_SIBLING_OK 0x0004 > > > > #define IRQF_SHARED_TIMER_OK(IRQF_SHARED | __IRQF_TIMER_SIBLING_OK) > > > > > > > > The "suspend" part is kind of a distraction to me here, because that > > > > really > > > > only is about sharing an IRQ with a timer and the "your interrupt > > > > handler > > > > may be called when the device is suspended" part is just a consequence > > > > of that. > > > > > > My rationale was that you didn't really care who else was using the IRQ > > > (e.g. the timer); you're just stating that you can survive being called > > > during suspend (which is what the driver may need to check for in the > > > handler if the device happens to be powered down or whatever). > > > > > > So I guess I see it the other way around. This is essentially claiming > > > we can handle sharing with IRQF_NO_SUSPEND rather than IRQF_TIMER. > > > > > > > So IMO it's better to have "TIMER" in the names to avoid encouraging > > > > people to > > > > abuse this for other purposes not related to timers. > > > > > > In the end a name is a name, and if you think IRQF_SHARED_TIMER_OK is > > > better I shan't complain. > > > > > > The fundamental issue I'm concerned with is addressed by this approach. > > > > Okay then, is anyone taking care of submitting such a patch (Mark ?) ? > > Well, I guess I should take the responsibility for that. :-) > > I'll try to cut one later today or tomorrow unless someone else beats me to > that. I had a go at the core part below. Does it look like what you had in mind? I've given it a go on a hacked-up platform, but I don't have any at91 stuff to test with, so I haven't bothered with the driver portions just yet. Thanks, Mark. >8 >From 2d9013517637bb567fbcde3e20797cb2fab1c4c5 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Wed, 11 Feb 2015 16:44:06 + Subject: [PATCH] genirq: allow safe sharing of irqs during suspend In some cases a physical IRQ line may be shared between devices from which we expect interrupts during suspend (e.g. timers) and those we do not (e.g. anything we cut the power to). Where a driver did not request the interrupt with IRQF_NO_SUSPEND, it's unlikely that it can handle being called during suspend, and where the IRQ PM code detects a mismatch it produces a loud warning (via WARN_ON_ONCE). In a small set of cases the handlers for the devices other than timers can tolerate being called during suspend time. In these cases the warning is spurious, and masks other potentially unsafe mismatches as it is only printed for the first mismatch detected. As the behaviour of the handlers is an implementation detail, we cannot rely on external data to decide when it is safe for a given interrupt line to be shared in this manner. This patch adds a new flag, IRQF_SHARED_TIMER_OK, which drivers can use when requesting an IRQ to state that they can cope if the interrupt is shared with a timer driver (and hence may be raised during suspend). The PM code is updated to only warn when a mismatch occurs and at least one irqaction has neither asked to be called during suspend or has stated it is safe to be called during suspend. This reduces the set of warnings to those cases where there is a real problem. While it is possible that this flag may be abused, any such abuses will be explicit in the kernel source and can be detected. Cc: Boris Brezillon Cc: Jason Cooper Cc: Nicolas Ferre Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Thomas Gleixner Signed-off-by: Mark Rutland --- include/linux/interrupt.h | 5 + kernel/irq/pm.c | 44 ++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/include/linux/interrupt.h b/include/linux
Re: [PATCH] of: calculate masks of the device based on dma-range size
On 02/09/2015 06:27 AM, Catalin Marinas wrote:
On Fri, Feb 06, 2015 at 03:15:20PM -0500, Murali Karicheri wrote:
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 314c8a9..44209fa 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -83,17 +83,18 @@ int of_device_add(struct platform_device *ofdev)
*/
void of_dma_configure(struct device *dev, struct device_node *np)
{
- u64 dma_addr, paddr, size;
+ u64 dma_addr = 0, paddr, size;
int ret;
bool coherent;
- unsigned long offset;
+ unsigned long offset = 0;
struct iommu_ops *iommu;
/*
* Set default dma-mask to 32 bit. Drivers are expected to setup
* the correct supported dma_mask.
*/
- dev->coherent_dma_mask = DMA_BIT_MASK(32);
+ if (!dev->coherent_dma_mask)
+ dev->coherent_dma_mask = DMA_BIT_MASK(32);
/*
* Set it to coherent_dma_mask by default if the architecture
@@ -102,11 +103,14 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
if (!dev->dma_mask)
dev->dma_mask =&dev->coherent_dma_mask;
+ /*
+* Set default size to cover the 32-bit. Drivers are expected to setup
+* the correct size and dma_mask.
+*/
Nitpick: drivers don't set up the size, just the mask. We read the size
from DT.
Not sure how this came, I will update this.
+ size = 1ULL<< 32;
+
ret = of_dma_get_range(np,&dma_addr,&paddr,&size);
- if (ret< 0) {
- dma_addr = offset = 0;
- size = dev->coherent_dma_mask + 1;
Do you assume that, on error, of_dma_get_range() does not touch any of
the dma_addr/paddr/size? It looks safer to me to leave it as the
original.
I think dma_addr and paddr is both modified on error. So this change
can't be done. I will revert the logic back to original.
- } else {
+ if (!ret) {
offset = PFN_DOWN(paddr - dma_addr);
/*
@@ -128,6 +132,15 @@ void of_dma_configure(struct device *dev, struct
device_node *np)
dev->dma_pfn_offset = offset;
+ /*
+* Limit coherent and dma mask based on size and default mask
+* set by the driver.
+*/
+ dev->coherent_dma_mask = min(dev->coherent_dma_mask,
+DMA_BIT_MASK(ilog2(dma_addr + size)));
Do we need to cover the case where size is incorrectly set to 0 in the
DT? At least some warning and leaving the mask unchanged.
The previous series already warn and return if the size is incorrect
(Patch v6 3/7) and leave the dma mask unchanged. So we don't have to do
anything in this patch. I will fix the above and re-send.
+ *dev->dma_mask = min((*dev->dma_mask),
+DMA_BIT_MASK(ilog2(dma_addr + size)));
+
coherent = of_dma_is_coherent(np);
dev_dbg(dev, "device is%sdma coherent\n",
coherent ? " " : " not ");
--
Murali Karicheri
Linux Kernel, Texas Instruments
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Re: [PATCH v6 0/7] PCI: get DMA configuration from parent device
On 02/11/2015 11:54 AM, Murali Karicheri wrote: On 02/06/2015 01:36 PM, Murali Karicheri wrote: On 02/06/2015 12:53 PM, Bjorn Helgaas wrote: On Fri, Feb 6, 2015 at 9:28 AM, Murali Karicheri wrote: On 02/06/2015 10:15 AM, Catalin Marinas wrote: On Thu, Feb 05, 2015 at 09:52:52PM +, Murali Karicheri wrote: This patch add an important capability to PCI driver on Keystone. I hope to have this merged to the upstream branch so that it is available for v3.20. It's very late for 3.20 and the code hasn't been in linux-next at all (but it's not me who's merging this code), unless you can squeeze it in as a bug-fix. This is in fact a bug fix as PCI on Keystone is broken without this. Oh, sorry, I didn't realize that this was so urgent. I guess I read "this adds an important capability" in the cover letter and concluded that it was new functionality. Bjorn, Thanks for responding. Let me give you some context on this without which my explanation won't be complete. For using PCI driver on Keystone, I had submitted patches related to machine and DTS to the arm mailing list to enable the driver on Keystone. Subsequenty one of the patch from my series was Nack-ed and I was asked to implememented in a different way and started this series. You can refer to the discussion of this at http://www.gossamer-threads.com/lists/linux/kernel/2024591 The PCI driver enablement on Keystone is still a working in progress and I am trying to get it fully functional on the upstream. Another missing piece is the SerDes phy driver patch. We have started working on the other part (SerDes phy driver) already as the initial one was not accepted. So it is fine if we are too late for the v3.20 merge window to merge this series and this can be applied to the next branch for v3.21. Anyway, if it's broken, presumably PCI on Keystone *did* work at one point. Can you identify the commit that broke it and requires these fixes, so we can figure out how far the fixes need to be backported? I am trying to get this driver enabled on Keystone by adding the missing pieces as described above. So I guess we don't have to back port anything here. If I merge it, I would like to get into my for-linus branch and get a little time in -next before asking Linus to pull it. The merge window is a little wrinkle there -- I don't like to add new things to the mix during the window. But if it's an important fix we can still get it in before the final v3.20. Please apply this to next branch for v3.21. It currently apply cleanly to v3.19-rc7. If you want me rebase to another branch, let me know I can apply and send you an updated patch. Bjorn, Arnd, I am assuming, Bjorn is going to merge this to his next branch for v3.21. If not, it might have to be merged through the arm soc? There are a couple of Tested-by and Acked-by received after v7. Do you want me to post v8 with these updated in the patches? FYI. These are the updates. Series was 1) Tested-by: Suravee Suthikulpanit (on AMD Seattle platform w/ PCI Generic Host controller) 2) Acked-by: Will Deacon 3) Reviewed-by: Catalin Marinas If you want to send a updated series with these, please let me know. Thanks and regards, Murali Murali Thanks Murali Bjorn -- Murali Karicheri Linux Kernel, Texas Instruments -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 0/7] PCI: get DMA configuration from parent device
On 02/06/2015 01:36 PM, Murali Karicheri wrote: On 02/06/2015 12:53 PM, Bjorn Helgaas wrote: On Fri, Feb 6, 2015 at 9:28 AM, Murali Karicheri wrote: On 02/06/2015 10:15 AM, Catalin Marinas wrote: On Thu, Feb 05, 2015 at 09:52:52PM +, Murali Karicheri wrote: This patch add an important capability to PCI driver on Keystone. I hope to have this merged to the upstream branch so that it is available for v3.20. It's very late for 3.20 and the code hasn't been in linux-next at all (but it's not me who's merging this code), unless you can squeeze it in as a bug-fix. This is in fact a bug fix as PCI on Keystone is broken without this. Oh, sorry, I didn't realize that this was so urgent. I guess I read "this adds an important capability" in the cover letter and concluded that it was new functionality. Bjorn, Thanks for responding. Let me give you some context on this without which my explanation won't be complete. For using PCI driver on Keystone, I had submitted patches related to machine and DTS to the arm mailing list to enable the driver on Keystone. Subsequenty one of the patch from my series was Nack-ed and I was asked to implememented in a different way and started this series. You can refer to the discussion of this at http://www.gossamer-threads.com/lists/linux/kernel/2024591 The PCI driver enablement on Keystone is still a working in progress and I am trying to get it fully functional on the upstream. Another missing piece is the SerDes phy driver patch. We have started working on the other part (SerDes phy driver) already as the initial one was not accepted. So it is fine if we are too late for the v3.20 merge window to merge this series and this can be applied to the next branch for v3.21. Anyway, if it's broken, presumably PCI on Keystone *did* work at one point. Can you identify the commit that broke it and requires these fixes, so we can figure out how far the fixes need to be backported? I am trying to get this driver enabled on Keystone by adding the missing pieces as described above. So I guess we don't have to back port anything here. If I merge it, I would like to get into my for-linus branch and get a little time in -next before asking Linus to pull it. The merge window is a little wrinkle there -- I don't like to add new things to the mix during the window. But if it's an important fix we can still get it in before the final v3.20. Please apply this to next branch for v3.21. It currently apply cleanly to v3.19-rc7. If you want me rebase to another branch, let me know I can apply and send you an updated patch. Bjorn, Arnd, I am assuming, Bjorn is going to merge this to his next branch for v3.21. If not, it might have to be merged through the arm soc? There are a couple of Tested-by and Acked-by received after v7. Do you want me to post v8 with these updated in the patches? Murali Thanks Murali Bjorn -- Murali Karicheri Linux Kernel, Texas Instruments -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] irqchip: Add DT binding doc for the virtual irq demuxer chip
On Wed, 11 Feb 2015 16:32:31 + Mark Rutland wrote: > On Wed, Feb 11, 2015 at 04:15:15PM +, Boris Brezillon wrote: > > On Wed, 11 Feb 2015 15:57:20 + > > Mark Rutland wrote: > > > > > [...] > > > > > > > > > > So for the flag at request time approach to work, all the drivers > > > > > > > using > > > > > > > the interrupt would have to flag they're safe in that context. > > > > > > > > > > > > Something like IRQF_"I can share the line with a timer" I guess? > > > > > > That wouldn't > > > > > > hurt and can be checked at request time even. > > > > > > > > > > I guess that would have to imply IRQF_SHARED, so we'd have something > > > > > like: > > > > > > > > > > IRQF_SHARED_SUSPEND_OK - This handler is safe to call spuriously > > > > > during > > > > >suspend in the case the line is shared. The > > > > >handler will not access unavailable hardware > > > > >or kernel infrastructure during this period. > > > > > > > > > > #define __IRQF_SUSPEND_SPURIOUS 0x0004 > > > > > #define IRQF_SHARED_SUSPEND_OK (IRQF_SHARED | > > > > > __IRQF_SUSPEND_SPURIOUS) > > > > > > > > What about > > > > > > > > #define __IRQF_TIMER_SIBLING_OK 0x0004 > > > > #define IRQF_SHARED_TIMER_OK(IRQF_SHARED | __IRQF_TIMER_SIBLING_OK) > > > > > > > > The "suspend" part is kind of a distraction to me here, because that > > > > really > > > > only is about sharing an IRQ with a timer and the "your interrupt > > > > handler > > > > may be called when the device is suspended" part is just a consequence > > > > of that. > > > > > > My rationale was that you didn't really care who else was using the IRQ > > > (e.g. the timer); you're just stating that you can survive being called > > > during suspend (which is what the driver may need to check for in the > > > handler if the device happens to be powered down or whatever). > > > > > > So I guess I see it the other way around. This is essentially claiming > > > we can handle sharing with IRQF_NO_SUSPEND rather than IRQF_TIMER. > > > > > > > So IMO it's better to have "TIMER" in the names to avoid encouraging > > > > people to > > > > abuse this for other purposes not related to timers. > > > > > > In the end a name is a name, and if you think IRQF_SHARED_TIMER_OK is > > > better I shan't complain. > > > > > > The fundamental issue I'm concerned with is addressed by this approach. > > > > Okay then, is anyone taking care of submitting such a patch (Mark ?) ? > > I'll have the core patch shortly. > > I'll need to ask for your help tagging the relevant drivers and testing. For the list of impacted drivers, you can have a look at this series [1] (patches 2 to 5), and I'll take care of the testing part once every one has agreed on the solution ;-). [1]https://lkml.org/lkml/2014/12/15/552 -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] Expose more controls from tegra-max98090
On 02/11/2015 07:49 AM, Tomeu Vizoso wrote: Hello, we need some more controls in userspace so policy can be applied at events such as microphone and headphone jacks being plugged in, to be used by Tegra-based Chromebooks. The series, Acked-by: Stephen Warren -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] irqchip: Add DT binding doc for the virtual irq demuxer chip
On Wed, Feb 11, 2015 at 04:15:15PM +, Boris Brezillon wrote: > On Wed, 11 Feb 2015 15:57:20 + > Mark Rutland wrote: > > > [...] > > > > > > > > So for the flag at request time approach to work, all the drivers > > > > > > using > > > > > > the interrupt would have to flag they're safe in that context. > > > > > > > > > > Something like IRQF_"I can share the line with a timer" I guess? > > > > > That wouldn't > > > > > hurt and can be checked at request time even. > > > > > > > > I guess that would have to imply IRQF_SHARED, so we'd have something > > > > like: > > > > > > > > IRQF_SHARED_SUSPEND_OK - This handler is safe to call spuriously during > > > > suspend in the case the line is shared. The > > > > handler will not access unavailable hardware > > > > or kernel infrastructure during this period. > > > > > > > > #define __IRQF_SUSPEND_SPURIOUS 0x0004 > > > > #define IRQF_SHARED_SUSPEND_OK (IRQF_SHARED | > > > > __IRQF_SUSPEND_SPURIOUS) > > > > > > What about > > > > > > #define __IRQF_TIMER_SIBLING_OK 0x0004 > > > #define IRQF_SHARED_TIMER_OK(IRQF_SHARED | __IRQF_TIMER_SIBLING_OK) > > > > > > The "suspend" part is kind of a distraction to me here, because that > > > really > > > only is about sharing an IRQ with a timer and the "your interrupt handler > > > may be called when the device is suspended" part is just a consequence of > > > that. > > > > My rationale was that you didn't really care who else was using the IRQ > > (e.g. the timer); you're just stating that you can survive being called > > during suspend (which is what the driver may need to check for in the > > handler if the device happens to be powered down or whatever). > > > > So I guess I see it the other way around. This is essentially claiming > > we can handle sharing with IRQF_NO_SUSPEND rather than IRQF_TIMER. > > > > > So IMO it's better to have "TIMER" in the names to avoid encouraging > > > people to > > > abuse this for other purposes not related to timers. > > > > In the end a name is a name, and if you think IRQF_SHARED_TIMER_OK is > > better I shan't complain. > > > > The fundamental issue I'm concerned with is addressed by this approach. > > Okay then, is anyone taking care of submitting such a patch (Mark ?) ? I'll have the core patch shortly. I'll need to ask for your help tagging the relevant drivers and testing. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
