Re: [PATCH 3/3] mailbox: Add support for ST's Mailbox IP
On Wed, Mar 18, 2015 at 9:04 PM, Lee Jones wrote:
> On Wed, 18 Mar 2015, Jassi Brar wrote:
>
>> On Wed, Mar 18, 2015 at 6:47 PM, Lee Jones wrote:
>> > On Tue, 03 Mar 2015, Jassi Brar wrote:
>> >
>> >> On 3 March 2015 at 17:04, Arnd Bergmann wrote:
>> >> > On Tuesday 03 March 2015 10:41:23 Lee Jones wrote:
>> >> >> +
>> >> >> +/*
>> >> >> + * struct sti_mbox_msg - sti mailbox message description
>> >> >> + * @dsize: data payload size
>> >> >> + * @pdata: message data payload
>> >> >> + */
>> >> >> +struct sti_mbox_msg {
>> >> >> + u32 dsize;
>> >> >> + u8 *pdata;
>> >> >> +};
>> >> >
>> >> > As mentioned in another thread, we may just want to add a 'size'
>> >> > argument to the message send function, and a default helper for
>> >> > messages with size of 32 bits.
>> >> >
>> >> Case-a) 'size' is a member of the payload structure itself
>> >> The extra 'size' argument would only be used for sanity check.
>> >> This driver seems so. Lee, can you not do without 'dsize'?
>> >>
>> >> Case-b) 'size' is not a member of payload structure:
>> >> b1) payload is fixed length, that is 'size' := sizeof(struct
>> >> my_payload)
>> >> Here the size argument is redundant.
>> >>
>> >> b2) payload length varies
>> >> This case is highly unlikely because there would be no way
>> >> for remote to know how many bytes to read as the payload. Not to mean
>> >> we can't do without the 'size' argument.
>> >>
>> >> Your opinion has huge weight, but I would like to be enlightened
>> >> before agreeing.
>> >
>> > Let's simplify this.
>> >
>> > If you want to have varying length payloads, you have to carry the
>> > size in the payload. If you wish to force fixed size payloads, then
>> > you may do without a size segment.
>> >
>> > Do you really want to force all users of Mailbox to use fixed size
>> > payloads?
>> >
>> No. I only observed the fact that every known mailbox controller
>> driver already has a way to figure out the payload length because
>> either the protocol uses fixed length payloads or has the 'size' field
>> in every payload.
>> I am yet to see a platform that uses both, then the 'size' argument
>> will be helpful but still not necessary.
>
> I see. So your real concern is that controllers shouldn't have two
> means of obtaining size.
>
I think right now there's not much need to expand the api for 'u32'
sized payloads.
> Arnd's idea of placing the message size as part of the send_message()
> call is fine, but it's still going to end up in the payload isn't it?
>
... or it will be implied by sizeof(struct my_packet) if the protocol
has finite set of payloads.
> And what about receiving?
>
Similar to sending - controller driver passes pointer to RX buffer
which the client parses. Remember the protocol would already have a
way to communicate payload length.
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Re: [PATCH 3/3] mailbox: Add support for ST's Mailbox IP
On Wed, Mar 18, 2015 at 8:56 PM, Lee Jones wrote:
> On Wed, 18 Mar 2015, Jassi Brar wrote:
>> >> > + mbox->irq =
>> >> > irq_create_mapping(mbinst->irq_domain,
>> >> > + mbox->rx_id);
>> >> >
>> >> simply assigning same IRQ to all controller DT nodes and using
>> >> IRQF_SHARED for the common handler, wouldn't work?
>> >
>> > I do have intentions to simplify this driver somewhat, but that will
>> > take some time as it will require a great deal of consultation and
>> > testing from the ST side. This is the current internal implementation
>> > which is used in the wild and has been fully tested. If you'll allow
>> > me to conduct my adaptions subsequently we can have full history and a
>> > possible reversion plan if anything untoward take place i.e. I mess
>> > something up.
>> >
>> OK, but wouldn't that break the bindings of this driver when you
>> eventually do that?
>
> That's going to happen regardless, since these bindings are already in
> use internally. Mainline (i.e. v4.0+) isn't going to be used in
> products for years to come, so we have a lot of time until any new
> bindings become ABI.
>
I thought time starts from upstream. It doesn't seem right to
knowingly introduce a binding that we are going to break in coming
weeks. For this reason, it needs ACK from some DT maintainer.
>> >> > + * struct sti_mbox_msg - sti mailbox message description
>> >> > + * @dsize: data payload size
>> >> > + * @pdata: message data payload
>> >> > + */
>> >> > +struct sti_mbox_msg {
>> >> > + u32 dsize;
>> >> > + u8 *pdata;
>> >> > +};
>> >> >
>> >> There isn't any client driver in this patchset to tell exactly, but it
>> >> seems the header could be split into one shared between mailbox
>> >> clients and provider and another internal to client/provider ?
>> >
>> > I believe only the above will be required by the client. Seems silly
>> > to create a client specific header just for that, don't you think?
>> >
>> Do you mean to have copies of the structure in controller and client driver?
>> :O
>
> I do not. I planned on sharing the main header with with client
> also.
>
> But I guess by your reaction you suggest having a teeny client header
> as the best way forward then.
>
Yes, please. And also no header that's included by exactly one file.
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[patch 7/7] dt: dtb version: report dtb info
From: Frank Rowand
Report the /chosen/dtb-info properties on boot.
Signed-off-by: Frank Rowand
---
The beginning of the context for hunk 2 includes a line from
2fa645cb2703d9b3786d850db815414dfeefa51d, which is in 4.0-rc4. The
author of that commit has submitted a request to revert the commit:
http://lkml.iu.edu/hypermail/linux/kernel/1503.2/02134.html
drivers/of/base.c | 42 ++
1 file changed, 42 insertions(+)
Index: b/drivers/of/base.c
===
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1880,6 +1880,7 @@ static void of_alias_add(struct alias_pr
void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align))
{
struct property *pp;
+ struct device_node *dtb_info = NULL;
of_aliases = of_find_node_by_path("/aliases");
of_chosen = of_find_node_by_path("/chosen");
@@ -1899,6 +1900,47 @@ void of_alias_scan(void * (*dt_alloc)(u6
}
}
+ dtb_info = of_find_node_by_path("/chosen/dtb-info");
+ if (dtb_info == NULL)
+ dtb_info = of_find_node_by_path("/chosen@0/dtb-info");
+
+ if (dtb_info) {
+ const char *string;
+ int len;
+
+ string = of_get_property(dtb_info, "version", &len);
+ if (string) {
+ pr_notice("DTB version ");
+ for ( ; len > 0;
+ len -= (strlen(string) + 1),
+ string += (strlen(string) + 1)) {
+ pr_cont("%s", string);
+ }
+ pr_cont("\n");
+ }
+
+ string = of_get_property(dtb_info, "version-linux", &len);
+ if (string) {
+ pr_notice("DTB linux version ");
+ for ( ; len > 0;
+ len -= (strlen(string) + 1),
+ string += (strlen(string) + 1)) {
+ pr_cont("%s", string);
+ }
+ pr_cont("\n");
+ }
+
+ string = of_get_property(dtb_info, "dts-path", &len);
+ if (string)
+ pr_notice("DTB source %s\n", string);
+
+ string = of_get_property(dtb_info, "dtb-path", &len);
+ if (string)
+ pr_notice("DTB blob %s\n", string);
+
+ of_node_put(dtb_info);
+ }
+
if (!of_aliases)
return;
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[patch 6/7] dt: dtb version: dtsi files
From: Frank Rowand
Create a .dtsi file to contain the /chosen/dtb-info node and populate the
properties in that node.
Signed-off-by: Frank Rowand
---
arch/arm/boot/dts/skeleton.dtsi |2
include/dt-bindings/version.dtsi | 19 +
Index: b/include/dt-bindings/version.dtsi
===
--- /dev/null
+++ b/include/dt-bindings/version.dtsi
@@ -0,0 +1,19 @@
+
+#include
+#include
+#include
+
+/ {
+ chosen {
+ dtb-info {
+ version = UTS_RELEASE, " ", DTB_VERSION;
+ version-linux =
+ UTS_RELEASE,
+ " (", LINUX_COMPILE_BY, "@",
LINUX_COMPILE_HOST, ") ",
+ "(", LINUX_COMPILER, ") ",
+ UTS_VERSION;
+ dtb-path = ___DTB_DTB_PATH;
+ dts-path = ___DTB_DTS_PATH;
+ };
+ };
+};
Index: b/arch/arm/boot/dts/skeleton.dtsi
===
--- a/arch/arm/boot/dts/skeleton.dtsi
+++ b/arch/arm/boot/dts/skeleton.dtsi
@@ -11,3 +11,5 @@
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};
+
+#include
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[patch 5/7] dt: dtb version: kbuild scripts
From: Frank Rowand
After applying this patch, need to add execute permission to the new file
scripts/version_dtb_increment_once
Modify the dtb compile rules to generate dtb version header files.
Create script to increment .version_dtb just once per make of one of more
dtbs, and to generate the dtb version header files.
Signed-off-by: Frank Rowand
---
scripts/Makefile.lib | 20 --
scripts/version_dtb_increment_once | 90 +++
Index: b/scripts/Makefile.lib
===
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -159,11 +159,19 @@ cpp_flags = -Wp,-MD,$(depfile) $(NO
ld_flags = $(LDFLAGS) $(ldflags-y)
+# Do not want to pull kernel header files into .dtb, so minimize the risk of
+# that by adding include/generated/ to include path instead of include/
+# Headers in include/generated/ are used by include/dt-bindings/version.dtsi
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc\
-I$(srctree)/arch/$(SRCARCH)/boot/dts \
-I$(srctree)/arch/$(SRCARCH)/boot/dts/include \
-I$(srctree)/drivers/of/testcase-data \
--undef -D__DTS__
+-Iinclude/generated \
+-undef -D__DTS__\
+-D___DTB_DTB_PATH="\"$@\"" \
+-D___DTB_DTS_PATH="\"$<\"" \
+-D"___DTB_DTC_VERSION=\"$(shell scripts/dtc/dtc -v | cut -d" "
-f2-)\""
+
# Finds the multi-part object the current object will be linked into
modname-multi = $(sort $(foreach m,$(multi-used),\
@@ -282,10 +290,12 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
$(call cmd,dt_S_dtb)
quiet_cmd_dtc = DTC $@
-cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
- $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
- -i $(dir $<) $(DTC_FLAGS) \
- -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+cmd_dtc = \
+ $(srctree)/scripts/version_dtb_increment_once ;\
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
$(obj)/%.dtb: $(src)/%.dts FORCE
Index: b/scripts/version_dtb_increment_once
===
--- /dev/null
+++ b/scripts/version_dtb_increment_once
@@ -0,0 +1,90 @@
+#!/bin/sh
+
+# increment .version_dtb at most once per build
+
+# VERSION_DTB_BASE is exported instead of passed to this script as an arg.
+#
+# If the value is passed as an arg then the make dependency triggers on
+# every build of a .dtb because if_changed_dep detects that cmd_dtc has
+# changed since the previous build (see scripts/Makefile.lib).
+
+# Nice output in kbuild format
+# Will be supressed by "make -s"
+info()
+{
+ if [ "${quiet}" != "silent_" ]; then
+ printf " %-7s %s\n" ${1} ${2}
+ fi
+}
+
+
+# flock(1) to avoid race in parallel build
+(flock 9
+
+ if [ ! -r .version_dtb -o ! -s .version_dtb ] ; then
+ rm -f .version_dtb
+ touch .version_dtb
+ fi
+
+ VERSION_DTB=`cat .version_dtb`
+ if [ "${VERSION_DTB}" != "${VERSION_DTB_BASE}" ] ; then
+ exit
+ fi
+
+ info GEN .version_dtb
+
+ VERSION_DTB=`expr 0${VERSION_DTB} + 1`
+ echo ${VERSION_DTB} > .version_dtb
+
+ # Do not expand names
+ set -f
+
+ # Fix the language to get consistent output
+ LC_ALL=C
+ export LC_ALL
+
+ if [ -z "$KBUILD_BUILD_TIMESTAMP" ]; then
+ TIMESTAMP=`date`
+ else
+ TIMESTAMP=$KBUILD_BUILD_TIMESTAMP
+ fi
+ if test -z "$KBUILD_BUILD_USER"; then
+ COMPILE_BY=$(whoami | sed 's/\\//')
+ else
+ COMPILE_BY=$KBUILD_BUILD_USER
+ fi
+ if test -z "$KBUILD_BUILD_HOST"; then
+ COMPILE_HOST=`hostname`
+ else
+ COMPILE_HOST=$KBUILD_BUILD_HOST
+ fi
+
+ DTB_COMPILER=`scripts/dtc/dtc -v | cut -d" " -f2-`
+
+ VERSION="UTS_RELEASE (${COMPILE_BY}@${COMPILE_HOST}) (${DTB_COMPILER})
#${VERSION_DTB} ${TIMESTAMP}"
+
+ # truncate to get same result as scripts/mkcompile_h
+ UTS_LEN=64
+ TRUNCATE="cut -b -$UTS_LEN"
+
+
+ # Generate compile_dtb.h
+ TARGET=include/generated/compile_dtb.h
+ info UPD $TARGET
+
+ ( echo /\* This file is auto ge
[patch 4/7] dt: dtb version: kernel Makefile
From: Frank Rowand Capture the initial value of .version_dtb so that when multiple .dtb files are created in a single make the make scripts will be able to increment .version_dtb only once instead of for each .dtb. Signed-off-by: Frank Rowand --- Makefile |4 + Index: b/Makefile === --- a/Makefile +++ b/Makefile @@ -416,6 +416,9 @@ KBUILD_LDFLAGS_MODULE := -T $(srctree)/s KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) KERNELVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) +VERSION_DTB_BASE := $(shell cat .version_dtb 2> /dev/null) + +export VERSION_DTB_BASE export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC export CPP AR NM STRIP OBJCOPY OBJDUMP @@ -1181,6 +1184,7 @@ CLEAN_DIRS += $(MODVERDIR) MRPROPER_DIRS += include/config usr/include include/generated \ arch/*/include/generated .tmp_objdiff MRPROPER_FILES += .config .config.old .version .old_version \ + .version_dtb .version_dtb_flock \ Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \ signing_key.priv signing_key.x509 x509.genkey \ extra_certificates signing_key.x509.keyid \ -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch 3/7] dt: dtb version: arm dts Makefile
From: Frank Rowand Remove generated files from the dependencies of .dtb files, where the generated files are created as a result of making a .dtb. Signed-off-by: Frank Rowand --- arch/arm/boot/dts/Makefile | 10 +++ Index: b/arch/arm/boot/dts/Makefile === --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -650,5 +650,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8135-evbp1.dtb endif +# These files are generated by a kernel make if .version has changed. +# Do not allow them to act as a dependency for rebuilding a .dtb that +# has included dt-bindings/version.dtsi. +PHONY += include/generated/compile.h include/generated/utsrelease.h + +# This file is generated by a .dtb make if .version_dtb has changed. +# Do not allow it to act as a dependency for rebuilding a .dtb that +# has included dt-bindings/version.dtsi. +PHONY += include/generated/compile_dtb.h + always := $(dtb-y) clean-files:= *.dtb -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch 2/7] dt: dtb version: document chosen/dtb-info node binding
From: Frank Rowand Add /chosen/dtb-node binding. Signed-off-by: Frank Rowand --- Documentation/devicetree/bindings/chosen.txt | 37 +++ Index: b/Documentation/devicetree/bindings/chosen.txt === --- a/Documentation/devicetree/bindings/chosen.txt +++ b/Documentation/devicetree/bindings/chosen.txt @@ -46,6 +46,43 @@ on PowerPC "stdout" if "stdout-path" is should only use the "stdout-path" property. +dtb-info node + + +Information that describes where the device tree blob (DTB) came from and the +environment it was created in. + +This node is normally created by including arch/arm/boot/dts/skeleton.dtsi, +which includes include/dt-bindings/version.dtsi. + +Properties: + +version + The version of the DTB. This is analagous to the linux kernel version. + + This is a format free field intended for human consumption. User space + programs should not have any expections about this property. + + The DTB number in this property is incremented each time a make that + creates one or more DTBs is invoked. If the make creates multiple + DTBs then this number is only incremented once. + + The DTB number is stored in file .version_dtb. + +version-linux + The version of the linux kernel most recently built in the source + control system that contains the source used to build the DTB. + + The linux kernel version number is not incremented for a make that + creates a DTB. + +dtb-path + The build directory relative path of the DTB. + +dts-path + The absolute path of the .dts file compiled to create the DTB. + + Properties documented in other bindings --- #address-cells video/simple-framebuffer-sunxi.txt -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch 1/7] dt: dtb version: consolidate documentation of chosen node bindings
From: Frank Rowand Documentation of bindings in node /chosen are scattered in several bindings files. If not already in Documentation/devicetree/bindings/chosen.txt, add a pointer in that file to where the property and node bindings are described. This is a clean up in anticipation of adding another node binding in /chosen. Signed-off-by: Frank Rowand --- Documentation/devicetree/bindings/chosen.txt | 31 +++ 1 file changed, 31 insertions(+) Index: b/Documentation/devicetree/bindings/chosen.txt === --- a/Documentation/devicetree/bindings/chosen.txt +++ b/Documentation/devicetree/bindings/chosen.txt @@ -44,3 +44,34 @@ Implementation note: Linux will look for on PowerPC "stdout" if "stdout-path" is not found. However, the "linux,stdout-path" and "stdout" properties are deprecated. New platforms should only use the "stdout-path" property. + + +Properties documented in other bindings +--- +#address-cells video/simple-framebuffer-sunxi.txt + +#size-cells video/simple-framebuffer-sunxi.txt + +bootargsbooting-without-of.txt +usage-model.txt + +initrd-end usage-model.txt +initrd-startusage-model.txt + +interrupt-controller (obsolete) booting-without-of.txt + +linux,pci-probe-onlypci/host-generic-pci.txt + +linux,stdout-path booting-without-of.txt + +ranges video/simple-framebuffer-sunxi.txt + +stdout-path video/simple-framebuffer.txt + + +Nodes documented in other bindings +-- +framebuffer video/simple-framebuffer.txt +video/simple-framebuffer-sunxi.txt + +linux,sysrq-reset-seq input/input-reset.txt -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch 0/7] dt: dtb version: add version info to dtb
Rob, Can this be added to the next trees to get some test exposure before submitting to Linus? There is currently no way to tie a device tree blob (DTB) back to the source and environment used to create it. Add this information, including a DTB version number, which is somewhat analogous to the Linux kernel version number. The DTB version number is independent of the kernel version number, and is incremented for each make of one or more DTBs. The DTB information is placed in node /chosen/dtb-info. The data for this node will be automatically generated by the .dtb make system for any .dts that includes arch/arm/boot/dts/skeleton.dtsi, either directly or indirectly. This means that architectures other than arm will not receive this feature. This can be added to other architectures by modifying their skeleton.dtsi. There are 70 of the 557 arm .dts files that do not include skeleton.dtsi. Thus the .dtb files created for these systems will not have the /chosen/dtb-info node: armada-xp-axpwifiap.dts armada-xp-db.dts armada-xp-gp.dts armada-xp-lenovo-ix4-300d.dts armada-xp-matrix.dts armada-xp-netgear-rn2120.dts armada-xp-openblocks-ax3-4.dts armada-xp-synology-ds414.dts atlas6-evb.dts atlas7-evb.dts axm5516-amarillo.dts bcm2835-rpi-b-plus.dts bcm2835-rpi-b.dts ea3250.dts ecx-2000.dts highbank.dts hip04-d01.dts integratorap.dts integratorcp.dts ls1021a-qds.dts ls1021a-twr.dts meson6-atv1200.dts moxart-uc7112lx.dts mt8127-moose.dts mt8135-evbp1.dts nspire-clp.dts nspire-cx.dts nspire-tp.dts phy3250.dts picoxcell-pc7302-pc3x2.dts picoxcell-pc7302-pc3x3.dts prima2-evb.dts r7s72100-genmai.dts r8a73a4-ape6evm-reference.dts r8a73a4-ape6evm.dts r8a7790-lager.dts r8a7791-henninger.dts r8a7791-koelsch.dts r8a7794-alt.dts spear1310-evb.dts spear1340-evb.dts spear300-evb.dts spear310-evb.dts spear320-evb.dts spear320-hmi.dts spear600-evb.dts stih407-b2120.dts stih410-b2120.dts stih415-b2000.dts stih415-b2020.dts stih416-b2000.dts stih416-b2020.dts stih416-b2020e.dts stih418-b2199.dts sun9i-a80-optimus.dts vexpress-v2p-ca15-tc1.dts vexpress-v2p-ca15_a7.dts vexpress-v2p-ca5s.dts vexpress-v2p-ca9.dts vt8500-bv07.dts wm8505-ref.dts wm8650-mid.dts wm8750-apc8750.dts wm8850-w70v2.dts xenvm-4.2.dts zynq-parallella.dts zynq-zc702.dts zynq-zc706.dts zynq-zed.dts zynq-zybo.dts An example of the DTB information reported is: $ echo ; cat /proc/version; echo ; echo ; dmesg | grep DTB Linux version 4.0.0-rc4-dirty (frank@buildhost) (gcc version 4.6.x-google 20120106 (prerelease) (GCC) ) #5 SMP PREEMPT Wed Mar 18 20:04:48 PDT 2015 DTB version 4.0.0-rc4-dirty (frank@buildhost) (DTC 1.4.0-dirty) #4 Wed Mar 18 20:04:11 PDT 2015 DTB linux version 4.0.0-rc4-dirty (frank@build_host) (gcc version 4.6.x-google 20120106 (prerelease) (GCC) ) #3 SMP PREEMPT Wed Mar 18 20:02:46 PDT 2015 DTB source /local/nobackup/src/git_linus/linux--4.0/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts DTB blob arch/arm/boot/dts/qcom-apq8074-dragonboard.dtb The values of the /chosen/dtb-info/ properties are also available in /proc/device-tree/chosen/dtb-info/ -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/4] mtd: nand: add common DT init code
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.
If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().
Signed-off-by: Brian Norris
---
drivers/mtd/nand/nand_base.c | 41 +
include/linux/mtd/nand.h | 5 +
2 files changed, 46 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d4cec2f8a016..692142da62e7 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -48,6 +48,7 @@
#include
#include
#include
+#include
/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
@@ -3779,6 +3780,39 @@ ident_done:
return type;
}
+static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip,
+ struct device_node *dn)
+{
+ int ecc_mode, ecc_strength, ecc_step;
+
+ if (of_get_nand_bus_width(dn) == 16)
+ chip->options |= NAND_BUSWIDTH_16;
+
+ if (of_get_nand_on_flash_bbt(dn))
+ chip->bbt_options |= NAND_BBT_USE_FLASH;
+
+ ecc_mode = of_get_nand_ecc_mode(dn);
+ ecc_strength = of_get_nand_ecc_strength(dn);
+ ecc_step = of_get_nand_ecc_step_size(dn);
+
+ if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
+ (!(ecc_step >= 0) && ecc_strength >= 0)) {
+ pr_err("must set both strength and step size in DT\n");
+ return -EINVAL;
+ }
+
+ if (ecc_mode >= 0)
+ chip->ecc.mode = ecc_mode;
+
+ if (ecc_strength >= 0)
+ chip->ecc.strength = ecc_strength;
+
+ if (ecc_step > 0)
+ chip->ecc.size = ecc_step;
+
+ return 0;
+}
+
/**
* nand_scan_ident - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
@@ -3796,6 +3830,13 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
int i, nand_maf_id, nand_dev_id;
struct nand_chip *chip = mtd->priv;
struct nand_flash_dev *type;
+ int ret;
+
+ if (chip->dn) {
+ ret = nand_dt_init(mtd, chip, chip->dn);
+ if (ret)
+ return ret;
+ }
/* Set the default functions */
nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 3d4ea7eb2b68..e0f40e12a2c8 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -26,6 +26,8 @@
struct mtd_info;
struct nand_flash_dev;
+struct device_node;
+
/* Scan and identify a NAND device */
extern int nand_scan(struct mtd_info *mtd, int max_chips);
/*
@@ -542,6 +544,7 @@ struct nand_buffers {
* flash device
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
* flash device.
+ * @dn:[BOARDSPECIFIC] device node describing this
instance
* @read_byte: [REPLACEABLE] read one byte from the chip
* @read_word: [REPLACEABLE] read one word from the chip
* @write_byte:[REPLACEABLE] write a single byte to the chip
on the
@@ -644,6 +647,8 @@ struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
+ struct device_node *dn;
+
uint8_t (*read_byte)(struct mtd_info *mtd);
u16 (*read_word)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
--
1.9.1
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[PATCH v2 3/4] mtd: nand: add NAND driver for Broadcom STB NAND controller
This core originated in Set-Top Box chips (BCM7xxx) but is used in a
variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and
iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it
to those architectures.
There are multiple revisions of this core throughout the years, and
almost every version broke register compatibility in some small way, but
with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0,
and v7.1. It's been tested on v5.0, v6.0, v7.0, and v7.1 recently, so
there hopefully are no more lurking inconsistencies.
Signed-off-by: Brian Norris
---
drivers/mtd/nand/Kconfig|8 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/brcmstb_nand.c | 2196 +++
3 files changed, 2205 insertions(+)
create mode 100644 drivers/mtd/nand/brcmstb_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5b76a173cd95..6445323a8cff 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -394,6 +394,14 @@ config MTD_NAND_GPMI_NAND
block, such as SD card. So pay attention to it when you enable
the GPMI.
+config MTD_NAND_BRCMSTB
+ tristate "Broadcom STB NAND controller"
+ depends on ARM || MIPS
+ help
+ Enables the Broadcom NAND controller driver. The controller was
+ originally designed for Set-Top Box but is used on various BCM7xxx,
+ BCM3xxx, BCM63xxx, iProc/Cygnus and more.
+
config MTD_NAND_BCM47XXNFLASH
tristate "Support for NAND flash on BCM4706 BCMA bus"
depends on BCMA_NFLASH
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 582bbd05aff7..3b1adddc83dd 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
+obj-$(CONFIG_MTD_NAND_BRCMSTB) += brcmstb_nand.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/brcmstb_nand.c b/drivers/mtd/nand/brcmstb_nand.c
new file mode 100644
index ..da63515f763f
--- /dev/null
+++ b/drivers/mtd/nand/brcmstb_nand.c
@@ -0,0 +1,2196 @@
+/*
+ * Copyright © 2010-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * This flag controls if WP stays on between erase/write commands to mitigate
+ * flash corruption due to power glitches. Values:
+ * 0: NAND_WP is not used or not available
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
+static int wp_on = 1;
+module_param(wp_on, int, 0444);
+
+/***
+ * Definitions
+ ***/
+
+#define DRV_NAME "brcmstb_nand"
+
+#define CMD_NULL 0x00
+#define CMD_PAGE_READ 0x01
+#define CMD_SPARE_AREA_READ0x02
+#define CMD_STATUS_READ0x03
+#define CMD_PROGRAM_PAGE 0x04
+#define CMD_PROGRAM_SPARE_AREA 0x05
+#define CMD_COPY_BACK 0x06
+#define CMD_DEVICE_ID_READ 0x07
+#define CMD_BLOCK_ERASE0x08
+#define CMD_FLASH_RESET0x09
+#define CMD_BLOCKS_LOCK0x0a
+#define CMD_BLOCKS_LOCK_DOWN 0x0b
+#define CMD_BLOCKS_UNLOCK 0x0c
+#define CMD_READ_BLOCKS_LOCK_STATUS0x0d
+#define CMD_PARAMETER_READ 0x0e
+#define CMD_PARAMETER_CHANGE_COL 0x0f
+#define CMD_LOW_LEVEL_OP 0x10
+
+struct brcm_nand_dma_desc {
+ u32 next_desc;
+ u32 next_desc_ext;
+ u32 cmd_irq;
+ u32 dram_addr;
+ u32 dram_addr_ext;
+ u32 tfr_len;
+ u32 total_len;
+ u32 flash_addr;
+ u32 flash_addr_ext;
+ u32 cs;
+ u32 pad2[5];
+ u32 status_valid;
+} __packed;
+
+/* Bitfields for brcm_nand_dma_desc::status_valid */
+#define FLASH_DMA_ECC_ERROR(1 << 8)
+#define FLASH_DMA_CORR_ERROR (1 << 9)
+
+/* 512B flash cache in the NAND controller
[PATCH v2 0/4] mtd: nand: add Broadcom NAND controller support
Hi,
This is version 2 of the (long in coming) support for the Broadcom BCM7xxx
Set-Top Box NAND controller. This controller has been used in a variety of
Broadcom SoCs.
There are a few more features I'd like add in the near future, mostly to
support more SoCs, but this is the base set, which should only need relatively
minor additions to support chips like BCM63138, BCM3384, and Cygnus/iProc.
Particularly, we may need to straighten out some endianness issues for the data
path on iProc, and interrupt enabling/acking on iProc, BCM63xxx, BCM3xxx, and
others.
I think I've addressed everybody's comments, but the delta changelog is:
v1 -> v2:
* add NAND to DTS for BCM7445 / BCM97445SVMB
* rename DT binding file to have 'brcm,' prefix
* catch DMA mapping errors
* fixup timeout / error messages (hex, remove misleading info)
* MODULE_LICENSE("GPL v2")
* fix incorrect comments
* print why we fail, when checking for supported controller revisions
* disable prefetch when using Flash DMA (see FIXME); will re-enable once we
get a good erased-page verification scheme merged
To be clear: this does NOT yet handle some of the per-SoC quirks required for
BCM53xxx/BCM4708 and Cygnus/iProc. Those patches are still WIP, and I want to
keep this patch series going while the Cygnus guys are straightening this out.
Happy reviewing!
Brian
Brian Norris (4):
mtd: nand: add common DT init code
Documentation: devicetree: add binding doc for Broadcom NAND
controller
mtd: nand: add NAND driver for Broadcom STB NAND controller
ARM: bcm7445: add NAND to DTS
.../devicetree/bindings/mtd/brcm,brcmstb-nand.txt | 109 +
arch/arm/boot/dts/bcm7445-bcm97445svmb.dts | 23 +
arch/arm/boot/dts/bcm7445.dtsi | 22 +
drivers/mtd/nand/Kconfig |8 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/brcmstb_nand.c| 2196
drivers/mtd/nand/nand_base.c | 41 +
include/linux/mtd/nand.h |5 +
8 files changed, 2405 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
create mode 100644 drivers/mtd/nand/brcmstb_nand.c
--
1.9.1
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[PATCH v2 2/4] Documentation: devicetree: add binding doc for Broadcom NAND controller
Signed-off-by: Brian Norris
---
.../devicetree/bindings/mtd/brcm,brcmstb-nand.txt | 109 +
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
b/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
new file mode 100644
index ..933d44943cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
@@ -0,0 +1,109 @@
+* Broadcom STB NAND Controller
+
+The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
+flash chips. It has a memory-mapped register interface for both control
+registers and for its data input/output buffer. On some SoCs, this controller
is
+paired with a custom DMA engine (inventively named "Flash DMA") which supports
+basic PROGRAM and READ functions, among other features.
+
+This controller was originally designed for STB SoCs (BCM7xxx) but is now
+available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
+iProc/Cygnus. Its history includes several similar (but not fully register
+compatible) versions.
+
+Required properties:
+- compatible : should contain "brcm,brcmnand" and an appropriate version
+ compatibility string, like "brcm,brcmnand-v7.0"
+ Possible values:
+ brcm,brcmnand-v4.0
+ brcm,brcmnand-v5.0
+ brcm,brcmnand-v6.0
+ brcm,brcmnand-v7.0
+ brcm,brcmnand-v7.1
+ brcm,brcmnand
+- reg : the register start and length for NAND register region.
+ (optional) Flash DMA register range (if present)
+ (optional) NAND flash cache range (if at non-standard
offset)
+- reg-names: a list of the names corresponding to the previous register
+ ranges. Should contain "nand" and (optionally)
+ "flash-dma" and/or "nand-cache".
+- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
+ FLASH_DMA_DONE
+- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done"
+- interrupt-parent : See standard interrupt bindings
+- #address-cells : <1> - subnodes give the chip-select number
+- #size-cells : <0>
+
+Optional properties:
+- brcm,nand-has-wp : Some versions of this IP include a write-protect
+ (WP) control bit. It is always available on >=
+ v7.0. Use this property to describe the rare
+ earlier versions of this core that include WP
+
+* NAND chip-select
+
+Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes
+to represent enabled chip-selects which (may) contain NAND flash chips. Their
+properties are as follows.
+
+Required properties:
+- compatible: should contain "brcm,nandcs"
+- reg : a single integer representing the chip-select
+ number (e.g., 0, 1, 2, etc.)
+- #address-cells: see partition.txt
+- #size-cells : see partition.txt
+- nand-ecc-strength : see nand.txt
+- nand-ecc-step-size: must be 512 or 1024. See nand.txt
+
+Optional properties:
+- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
+ chip-select. See nand.txt
+- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
+ expected for the ECC layout in use. This size, in
+ addition to the strength and step-size,
+ determines how the hardware BCH engine will lay
+ out the parity bytes it stores on the flash.
+ This property can be automatically determined by
+ the flash geometry (particularly the NAND page
+ and OOB size) in many cases, but when booting
+ from NAND, the boot controller has only a limited
+ number of available options for its default ECC
+ layout.
+
+Each nandcs device node may optionally contain sub-nodes describing the flash
+partition mapping. See partition.txt for more detail.
+
+Example:
+
+nand@f0442800 {
+ compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
+ reg = <0xF0442800 0x600>,
+ <0xF0443000 0x100>;
+ reg-names = "nand", "flash-dma";
+ interrupt-parent = <&hif_intr2_intc>;
+ interrupts = <24>, <4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <1>; // Chip select 1
+ nand-on-flash-bbt;
+
[PATCH v2 4/4] ARM: bcm7445: add NAND to DTS
Signed-off-by: Brian Norris
---
Light dependency on:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/331921.html
for the surrounding text.
arch/arm/boot/dts/bcm7445-bcm97445svmb.dts | 23 +++
arch/arm/boot/dts/bcm7445.dtsi | 22 ++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
index 9eec2ac1112f..0bb8d17e4c2d 100644
--- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
+++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
@@ -12,3 +12,26 @@
<0x00 0x8000 0x00 0x4000>;
};
};
+
+&nand {
+ status = "okay";
+
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <1>;
+ nand-ecc-step-size = <512>;
+ nand-ecc-strength = <8>;
+ nand-on-flash-bbt;
+
+ #size-cells = <2>;
+ #address-cells = <2>;
+
+ flash1.rootfs0@0 {
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ flash1.rootfs1@8000 {
+ reg = <0x0 0x8000 0x0 0x8000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 9eaeac8dce1b..c148dcf8c69b 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -108,6 +108,28 @@
brcm,int-map-mask = <0x25c>, <0x700>;
brcm,int-fwd-mask = <0x7>;
};
+
+ hif_intr2_intc: interrupt-controller@3e1000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x3e1000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0x0 0x20 0x0>;
+ interrupt-parent = <&gic>;
+ interrupt-names = "hif";
+ };
+
+ nand: nand@3e2800 {
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg-names = "nand", "flash-dma";
+ reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
+ interrupt-parent = <&hif_intr2_intc>;
+ interrupts = <24>, <4>;
+ interrupt-names = "nand_ctlrdy", "flash_dma_done";
+ };
};
smpboot {
--
1.9.1
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Re: [PATCH 1/2] ARM: dts: brcmstb: un-hexify clock frequency
On Wed, Mar 18, 2015 at 5:31 PM, Brian Norris wrote: > This value makes much more sense in decimal. > > Signed-off-by: Brian Norris Acked-by: Gregory Fong -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] mtd: nand: add NAND driver for Broadcom STB NAND controller
On Mon, Mar 16, 2015 at 11:55:16AM -0700, Florian Fainelli wrote:
> On 06/03/15 17:18, Brian Norris wrote:
> > +static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
> > +{
> > + static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512,
> > 1024, 2048, 0 };
> > + static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256,
> > 1024, 2048, 0 };
> > + static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
> > +
> > + ctrl->nand_version = nand_readreg(ctrl, 0) & 0x;
> > +
> > + /* Only support v4.0+? */
> > + if (ctrl->nand_version < 0x0400)
> > + return -ENODEV;
>
> It could be nice to have an informative error message here that this is
> either:
>
> - an unknown controller revision (> 7.1)
> - an older controller revision
> - a check against the compatible property, just in case?
I'll add a message that the revision is not supported. The DT binding
should catch this too, so this check is just an extra safeguard.
> [snip]
>
> > + ctrl->cs_offsets = brcmnand_cs_offsets_v71;
> > + } else {
> > + ctrl->cs_offsets = brcmnand_cs_offsets;
> > +
> > + /* pre-v5.0 has a different CS0 offset layout */
> > + if (ctrl->nand_version <= 0x0500)
> > + ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
>
> Based on this check, should the comment should be "pre-v5.0 and v5.0
> have a different CS0 offset layout"?
Yes. Fixed.
Brian
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Re: [PATCH 0/7] ARM: shmobile: Add IRQC clock to device tree
Thanks Geert,
On Wed, Mar 18, 2015 at 07:55:54PM +0100, Geert Uytterhoeven wrote:
> Hi,
>
> This patch series adds the IRQC clock to the device tree on SoCs that
> have such a clock (r8a73a4 and r8a779x), and adds mininal runtime PM
> support to the renesas-irqc driver, to make sure the clock is enabled
> when needed by the external IRQ controller(s).
> Before, the clock was assumed enabled by the bootloader or reset state.
>
> As usual when involving clocks, the DTS changes depend stricly on the
> driver changes. Else the clock will be disabled as assumed unused,
> breaking the boot.
>
> This was tested on r8a73a4/ape6evm and r8a7791/koelsch.
I will defer the DTS changes until the irqchip changes, which I
have reviewed, are accepted.
>
> Thanks!
>
> Geert Uytterhoeven (7):
> irqchip: renesas-irqc: Add more register documentation
> irqchip: renesas-irqc: Add minimal runtime PM support
> irqchip: renesas-irqc: Add functional clock to bindings
> ARM: shmobile: r8a7734: Add IRQC clock to device tree
> ARM: shmobile: r8a7790: Add IRQC clock to device tree
> ARM: shmobile: r8a7791: Add IRQC clock to device tree
> ARM: shmobile: r8a7794: Add IRQC clock to device tree
>
> .../bindings/interrupt-controller/renesas,irqc.txt | 4 +++-
> arch/arm/boot/dts/r8a73a4.dtsi | 11 +
> arch/arm/boot/dts/r8a7790.dtsi | 9 +++
> arch/arm/boot/dts/r8a7791.dtsi | 9 +++
> arch/arm/boot/dts/r8a7794.dtsi | 9 +++
> drivers/irqchip/irq-renesas-irqc.c | 28
> ++
> include/dt-bindings/clock/r8a73a4-clock.h | 1 +
> include/dt-bindings/clock/r8a7790-clock.h | 3 +++
> include/dt-bindings/clock/r8a7791-clock.h | 3 +++
> include/dt-bindings/clock/r8a7794-clock.h | 3 +++
> 10 files changed, 70 insertions(+), 10 deletions(-)
>
> --
> 1.9.1
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
>
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Re: [PATCH v6 0/6] Add common clock support for Broadcom iProc architecture
Patchset looks good now. Scott On 15-03-17 10:45 PM, Ray Jui wrote: This patchset contains the initial common clock support for Broadcom's iProc family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the basic reference clock for these PLLs. Each PLL may have several leaf clocks. One special group of clocks is the ASIU clocks, which are dervied directly from the crystal reference clock. This patchset also contains the basic clock support for the Broadcom Cygnus SoC, which implements the iProc clock architecture Changes from v5: - Rebase to v4.0-rc4 - Drop of_clk_get_parent_rate helper function from the clock framework - Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add standard clock set_rate and round_rate support and make use of DT properties "assigned-clocks" and "assigned-clock-rates" to initialize PLL to the desired rate when registering to the clock framework - Add SW workaround for ASIC bug on MIPI PLL to always read back the same register following a write transaction, to ensure value is written to the correct register Changes from v4: - Add of_clk_get_parent_rate helper function into the clock framework - Switch to use of_clk_get_parent_rate in the iProc PLL clock driver Changes from v3: - Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL and other iProc PLLs as clock provider. These PLLs have zero cells in DT and thefore of_clk_src_simple_get should be used instead - Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been integrated into Cygnus revision B0 and has its core clock running off MIPI PLL Channel 2 - Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This allows us to derive 300 MHz V3D clock from channel 2 through the post divisor Changes from v2: - Re-arrange Cygnus clock/pll init functions so each init function is right next to its clock table - Removed #defines for number of clocks in Cygnus. Have the number of clocks automatically determined based on array size of the clock table Changes from v1: - Separate drivers/clk/Makefile change for drivers/clk/bcm out to a standalone patch Ray Jui (6): clk: iproc: define Broadcom iProc clock binding clk: iproc: add initial common clock support clk: Change bcm clocks build dependency clk: cygnus: add clock support for Broadcom Cygnus ARM: dts: enable clock support for Broadcom Cygnus clk: cygnus: remove Cygnus dummy clock binding .../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34 -- .../bindings/clock/brcm,iproc-clocks.txt | 171 +++ arch/arm/boot/dts/bcm-cygnus-clock.dtsi| 112 - arch/arm/boot/dts/bcm-cygnus.dtsi |2 +- drivers/clk/Makefile |2 +- drivers/clk/bcm/Kconfig|9 + drivers/clk/bcm/Makefile |2 + drivers/clk/bcm/clk-cygnus.c | 284 drivers/clk/bcm/clk-iproc-armpll.c | 282 +++ drivers/clk/bcm/clk-iproc-asiu.c | 275 +++ drivers/clk/bcm/clk-iproc-clk.c| 244 ++ drivers/clk/bcm/clk-iproc-pll.c| 490 drivers/clk/bcm/clk-iproc.h| 164 +++ include/dt-bindings/clock/bcm-cygnus.h | 65 +++ 14 files changed, 2075 insertions(+), 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt create mode 100644 drivers/clk/bcm/clk-cygnus.c create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c create mode 100644 drivers/clk/bcm/clk-iproc-clk.c create mode 100644 drivers/clk/bcm/clk-iproc-pll.c create mode 100644 drivers/clk/bcm/clk-iproc.h create mode 100644 include/dt-bindings/clock/bcm-cygnus.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/7] irqchip: renesas-irqc: Add functional clock to bindings
On Wed, Mar 18, 2015 at 07:55:57PM +0100, Geert Uytterhoeven wrote: > The external IRQ controller has a functional clock, which is used for > power management. Document it. > > Fix a typo in the r8a73a4 SoC name while we're at it. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman > --- > .../devicetree/bindings/interrupt-controller/renesas,irqc.txt | 4 > +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt > b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt > index 1a88e62228e59631..4f85aeb658e4c833 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt > @@ -4,7 +4,7 @@ Required properties: > > - compatible: has to be "renesas,irqc-", "renesas,irqc" as fallback. >Examples with soctypes are: > -- "renesas,irqc-r8a73a4" (R-Mobile AP6) > +- "renesas,irqc-r8a73a4" (R-Mobile APE6) > - "renesas,irqc-r8a7790" (R-Car H2) > - "renesas,irqc-r8a7791" (R-Car M2-W) > - "renesas,irqc-r8a7792" (R-Car V2H) > @@ -12,6 +12,7 @@ Required properties: > - "renesas,irqc-r8a7794" (R-Car E2) > - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined > in >interrupts.txt in this directory > +- clocks: Must contain a reference to the functional clock. > > Optional properties: > > @@ -29,4 +30,5 @@ Example: ><0 1 IRQ_TYPE_LEVEL_HIGH>, ><0 2 IRQ_TYPE_LEVEL_HIGH>, ><0 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp4_clks R8A7790_CLK_IRQC>; > }; > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/7] irqchip: renesas-irqc: Add minimal runtime PM support
On Wed, Mar 18, 2015 at 07:55:56PM +0100, Geert Uytterhoeven wrote:
> This is just enough to let pm_clk_*() enable the functional clock, and
> manage it for suspend/resume, if present.
> Before, it was assumed enabled by the bootloader or reset state.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
> ---
> drivers/irqchip/irq-renesas-irqc.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/irqchip/irq-renesas-irqc.c
> b/drivers/irqchip/irq-renesas-irqc.c
> index 2ce2edf8ec8ec182..718f01cd1aea19f6 100644
> --- a/drivers/irqchip/irq-renesas-irqc.c
> +++ b/drivers/irqchip/irq-renesas-irqc.c
> @@ -29,6 +29,7 @@
> #include
> #include
> #include
> +#include
>
> #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
>
> @@ -180,6 +181,9 @@ static int irqc_probe(struct platform_device *pdev)
> p->pdev = pdev;
> platform_set_drvdata(pdev, p);
>
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_get_sync(&pdev->dev);
> +
> /* get hold of manadatory IOMEM */
> io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!io) {
> @@ -260,6 +264,8 @@ err3:
> err2:
> iounmap(p->iomem);
> err1:
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> kfree(p);
> err0:
> return ret;
> @@ -275,6 +281,8 @@ static int irqc_remove(struct platform_device *pdev)
>
> irq_domain_remove(p->irq_domain);
> iounmap(p->iomem);
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> kfree(p);
> return 0;
> }
> --
> 1.9.1
>
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Re: [PATCH 1/7] irqchip: renesas-irqc: Add more register documentation
On Wed, Mar 18, 2015 at 07:55:55PM +0100, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
> ---
> drivers/irqchip/irq-renesas-irqc.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/irqchip/irq-renesas-irqc.c
> b/drivers/irqchip/irq-renesas-irqc.c
> index 2ea3412fdf8cc668..2ce2edf8ec8ec182 100644
> --- a/drivers/irqchip/irq-renesas-irqc.c
> +++ b/drivers/irqchip/irq-renesas-irqc.c
> @@ -30,14 +30,24 @@
> #include
> #include
>
> -#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
> +#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
>
> -#define IRQC_REQ_STS 0x00
> -#define IRQC_EN_STS 0x04
> -#define IRQC_EN_SET 0x08
> +#define IRQC_REQ_STS 0x00/* Interrupt Request Status Register */
> +#define IRQC_EN_STS 0x04/* Interrupt Enable Status Register */
> +#define IRQC_EN_SET 0x08/* Interrupt Enable Set Register */
> #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
> -#define DETECT_STATUS 0x100
> + /* SYS-CPU vs. RT-CPU */
> +#define DETECT_STATUS0x100 /* IRQn Detect Status Register */
> +#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
> +#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
> +#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
> +#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
> +#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
> +#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
> +#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
> +#define CHTEN_STS0x120 /* Chattering Reduction Status Register */
> #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
> + /* IRQn Configuration Register */
>
> struct irqc_irq {
> int hw_irq;
> --
> 1.9.1
>
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[PATCH 04/12] usb: chipidea: imx: add stream mode enable for device mode at imx6sl/imx6sx
Stream mode enable is known for better performance, this stream mode
enable patch has been passed with stress tests at device mode for
imx6sl and imx6sx, and no issue is found.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/ci_hdrc_imx.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c
b/drivers/usb/chipidea/ci_hdrc_imx.c
index 389f0e0..5373984 100644
--- a/drivers/usb/chipidea/ci_hdrc_imx.c
+++ b/drivers/usb/chipidea/ci_hdrc_imx.c
@@ -29,26 +29,31 @@ struct ci_hdrc_imx_platform_flag {
};
static const struct ci_hdrc_imx_platform_flag imx27_usb_data = {
+ CI_HDRC_DISABLE_STREAMING,
};
static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
.flags = CI_HDRC_IMX28_WRITE_FIX |
- CI_HDRC_TURN_VBUS_EARLY_ON,
+ CI_HDRC_TURN_VBUS_EARLY_ON |
+ CI_HDRC_DISABLE_STREAMING,
};
static const struct ci_hdrc_imx_platform_flag imx6q_usb_data = {
.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
- CI_HDRC_TURN_VBUS_EARLY_ON,
+ CI_HDRC_TURN_VBUS_EARLY_ON |
+ CI_HDRC_DISABLE_STREAMING,
};
static const struct ci_hdrc_imx_platform_flag imx6sl_usb_data = {
.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
- CI_HDRC_TURN_VBUS_EARLY_ON,
+ CI_HDRC_TURN_VBUS_EARLY_ON |
+ CI_HDRC_DISABLE_HOST_STREAMING,
};
static const struct ci_hdrc_imx_platform_flag imx6sx_usb_data = {
.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
- CI_HDRC_TURN_VBUS_EARLY_ON,
+ CI_HDRC_TURN_VBUS_EARLY_ON |
+ CI_HDRC_DISABLE_HOST_STREAMING,
};
static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
@@ -126,7 +131,6 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev)
struct ci_hdrc_platform_data pdata = {
.name = dev_name(&pdev->dev),
.capoffset = DEF_CAPOFFSET,
- .flags = CI_HDRC_DISABLE_STREAMING,
};
int ret;
const struct of_device_id *of_id =
--
1.9.1
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[PATCH 4/5] phy: add Broadcom SATA3 PHY driver for Broadcom STB SoCs
Supports up to two ports which can each be powered on/off and configured
independently.
Signed-off-by: Brian Norris
---
drivers/phy/Kconfig| 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-brcmstb-sata.c | 333 +
3 files changed, 343 insertions(+)
create mode 100644 drivers/phy/phy-brcmstb-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2962de205ba7..c8b22074bcf6 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -291,4 +291,13 @@ config PHY_QCOM_UFS
help
Support for UFS PHY on QCOM chipsets.
+config PHY_BRCMSTB_SATA
+ tristate "Broadcom STB SATA PHY driver"
+ depends on ARCH_BRCMSTB
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
+ Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f080e1bb2a74..28a10804b4f4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
+obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
new file mode 100644
index ..413bc94225ac
--- /dev/null
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -0,0 +1,333 @@
+/*
+ * Broadcom SATA3 AHCI Controller PHY Driver
+ *
+ * Copyright © 2009-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SATA_MDIO_BANK_OFFSET 0x23c
+#define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4)
+#define SATA_MDIO_REG_SPACE_SIZE 0x1000
+#define SATA_MDIO_REG_LENGTH 0x1f00
+
+#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
+ #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
+
+#define SATA_TOP_CTRL_PHY_CTRL_2 0x4
+ #define SATA_TOP_CTRL_2_SW_RST_MDIOREGBIT(0)
+ #define SATA_TOP_CTRL_2_SW_RST_OOBBIT(1)
+ #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
+ #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
+ #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
+
+#define MAX_PORTS 2
+/* Register offset between PHYs in port-ctrl */
+#define SATA_TOP_CTRL_PHY_CTRL_LEN 0x8
+/* Register offset between PHYs in PCB space */
+#define SATA_MDIO_REG_SPACE_SIZE 0x1000
+
+struct brcm_sata_port {
+ int portnum;
+ struct phy *phy;
+ struct brcm_sata_phy *phy_priv;
+ bool ssc_en;
+};
+
+struct brcm_sata_phy {
+ struct device *dev;
+ void __iomem *port_ctrl;
+ void __iomem *phy_base;
+
+ struct brcm_sata_port phys[MAX_PORTS];
+};
+
+enum sata_mdio_phy_regs_28nm {
+ PLL_REG_BANK_0 = 0x50,
+ PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
+
+ TXPMD_REG_BANK = 0x1a0,
+ TXPMD_CONTROL1 = 0x81,
+ TXPMD_CONTROL1_TX_SSC_EN_FRC= BIT(0),
+ TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL= BIT(1),
+ TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
+ TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
+ TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
+ TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
+ TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
+};
+
+static inline void __iomem *sata_phy_get_port_ctrl(struct brcm_sata_port *port)
+{
+ struct brcm_sata_phy *priv = port->phy_priv;
+
+ return priv->port_ctrl + (port->portnum * SATA_TOP_CTRL_PHY_CTRL_LEN);
+}
+static inline void __iomem *sata_phy_get_phy_base(struct brcm_sata_port *port)
+{
+ struct brcm_sata_phy *priv = port->phy_priv;
+
+ return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
+}
+
+static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
+ u32 msk, u32 value)
+{
+ u32 tmp;
+
+ writel(bank, addr + SATA_MDIO_BANK_OFFSET);
+ tmp = readl(addr + SATA_MDIO_R
[PATCH 2/5] Documentation: devicetree: add Broadcom SATA PHY binding
For 28nm STB chips, based on BCM7445.
Signed-off-by: Brian Norris
---
.../bindings/phy/brcm,brcmstb-sata-phy.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
new file mode 100644
index ..39eddd53b318
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
@@ -0,0 +1,40 @@
+* Broadcom SATA3 PHY for STB
+
+Required properties:
+- compatible: should be one or more of
+ "brcm,bcm7445-sata-phy"
+ "brcm,phy-sata3"
+- address-cells: should be 1
+- size-cells: should be 0
+- phy-cells: generic PHY binding; must be 1
+- reg: register ranges for the PHY PCB interface, and for the PHY port control
+ registers found in the SATA_TOP_CTRL block (i.e., PHY_CTRL 1/2/3/4)
+- reg-names: should be "phy" and "port-ctrl"
+
+Sub-nodes:
+ Each port's PHY should be represented as a sub-node.
+
+Sub-nodes required properties:
+- reg: the PHY number
+Optional:
+- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
+
+
+Example:
+
+ sata-phy@f0458100 {
+ compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
+ reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
+ reg-names = "phy", "port-ctrl";
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata-phy@0 {
+ reg = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ };
+ };
--
1.9.1
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[PATCH 1/5] Documentation: devicetree: add Broadcom SATA binding
Signed-off-by: Brian Norris
---
.../devicetree/bindings/ata/brcm,sata-brcmstb.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
new file mode 100644
index ..afeede13e195
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
@@ -0,0 +1,35 @@
+* Broadcom SATA3 AHCI Controller for STB
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, may contain "brcm,bcm7445-ahci" and/or
+ "brcm,sata3-ahci"
+- reg: register mappings for AHCI and SATA_TOP_CTRL
+- reg-names : "ahci" and "top-ctrl"
+- interrupts : interrupt mapping for SATA IRQ
+
+Also see ahci-platform.txt.
+
+Example:
+
+ sata@f045a000 {
+ compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+ reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
+ reg-names = "ahci", "top-ctrl";
+ interrupts = <0 30 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ };
+ };
+
--
1.9.1
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[PATCH 5/5] ARM: dts: brcmstb: add nodes for SATA controller and PHY
Signed-off-by: Brian Norris
---
Light dependency on:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/331921.html
for the surrounding text.
arch/arm/boot/dts/bcm7445.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 9eaeac8dce1b..7a7c4d8c2afe 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -108,6 +108,42 @@
brcm,int-map-mask = <0x25c>, <0x700>;
brcm,int-fwd-mask = <0x7>;
};
+
+ sata@f045a000 {
+ compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0x45a000 0xa9c>, <0x458040 0x24>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ };
+ };
+
+ sata_phy: sata-phy@f0458100 {
+ compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
+ reg = <0x458100 0x1e00>, <0x45804c 0x10>;
+ reg-names = "phy", "port-ctrl";
+ #phy-cells = <1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ sata-phy@0 {
+ reg = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ };
+ };
};
smpboot {
--
1.9.1
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[PATCH 3/5] ata: add Broadcom AHCI SATA3 driver for STB chips
Pretty straightforward driver, using the nice library-ization of the
generic ahci_platform driver.
Signed-off-by: Brian Norris
---
drivers/ata/Kconfig| 9 +++
drivers/ata/Makefile | 1 +
drivers/ata/sata_brcmstb.c | 148 +
3 files changed, 158 insertions(+)
create mode 100644 drivers/ata/sata_brcmstb.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 5f601553b9b0..33d4b3031705 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -98,6 +98,15 @@ config SATA_AHCI_PLATFORM
If unsure, say N.
+config SATA_BRCMSTB
+ tristate "Broadcom STB AHCI SATA support"
+ depends on ARCH_BRCMSTB
+ help
+ This option enables support for the AHCI SATA3 controller found on
+ STB SoC's.
+
+ If unsure, say N.
+
config AHCI_DA850
tristate "DaVinci DA850 AHCI SATA support"
depends on ARCH_DAVINCI_DA850
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index ae41107afc1f..5d1e6a96bc93 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_ATA) += libata.o
obj-$(CONFIG_SATA_AHCI)+= ahci.o libahci.o
obj-$(CONFIG_SATA_ACARD_AHCI) += acard-ahci.o libahci.o
obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
libahci_platform.o
+obj-$(CONFIG_SATA_BRCMSTB) += sata_brcmstb.o libahci.o libahci_platform.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
obj-$(CONFIG_SATA_INIC162X)+= sata_inic162x.o
obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
diff --git a/drivers/ata/sata_brcmstb.c b/drivers/ata/sata_brcmstb.c
new file mode 100644
index ..2a3aff419332
--- /dev/null
+++ b/drivers/ata/sata_brcmstb.c
@@ -0,0 +1,148 @@
+/*
+ * Broadcom SATA3 AHCI Controller Driver
+ *
+ * Copyright © 2009-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ahci.h"
+
+#define DRV_NAME "brcm-ahci"
+
+#define SATA_TOP_CTRL_VERSION 0x0
+#define SATA_TOP_CTRL_BUS_CTRL 0x4
+
+#ifdef __BIG_ENDIAN
+#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
+#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
+#else
+#define DATA_ENDIAN 0
+#define MMIO_ENDIAN 0
+#endif
+
+struct brcm_ahci_priv {
+ struct device *dev;
+ struct ahci_host_priv *hpriv;
+
+ void __iomem *top_ctrl;
+};
+
+static const struct ata_port_info ahci_brcm_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static void brcm_sata3_init_config(struct brcm_ahci_priv *priv)
+{
+ /* Configure endianness */
+ writel((DATA_ENDIAN << 4) | (DATA_ENDIAN << 2) | (MMIO_ENDIAN << 0),
+ priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+}
+
+static int brcm_ahci_suspend(struct device *dev)
+{
+ return ahci_platform_suspend(dev);
+}
+
+static int brcm_ahci_resume(struct device *dev)
+{
+ struct brcm_ahci_priv *priv = dev_get_drvdata(dev);
+
+ brcm_sata3_init_config(priv);
+ return ahci_platform_resume(dev);
+}
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int brcm_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct brcm_ahci_priv *priv;
+ struct ahci_host_priv *hpriv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ dev_set_drvdata(dev, priv);
+ priv->dev = dev;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ priv->hpriv = hpriv;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
+ priv->top_ctrl = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->top_ctrl))
+ return PTR_ERR(priv->top_ctrl);
+
+ brcm_sata3_init_config(priv);
+
+ ret = ahci_platform_enable_resources(hpriv);
+ if (ret)
+ return ret;
+
+ hpriv->plat_data = priv;
+
+ ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
+
[PATCH 10/12] Doc: usb: ci-hdrc-imx: add tx(rx)-burst-config-dword for binding doc
It is used to override the default setting for burst size, changing
burst size takes effect only when the SBUSCFG.AHBBRST = 0.
Signed-off-by: Peter Chen
---
Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index a548502..892bac8 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -24,6 +24,10 @@ Optional properties:
should be aligned with ITC bits at register USBCMD.
- ahb-burst-config: it is vendor dependent, the required value should be
aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7.
+- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
+ (4 bytes)
+- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
+ (4 bytes)
Examples:
usb@02184000 { /* USB OTG */
@@ -38,4 +42,6 @@ usb@02184000 { /* USB OTG */
tpl-support;
gadget-itc-setting = <0x4>; /* 4 micro-frames */
ahb-burst-config = <0x0>; /* Incremental burst of unspecified length */
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
};
--
1.9.1
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[PATCH 07/12] ARM: imx6: set ahb-burst-config as 0 for USB
After setting ahb burst configuration as 0, we can increase tx/rx burst size, it will improve the USB performance Signed-off-by: Peter Chen --- arch/arm/boot/dts/imx6qdl.dtsi | 4 arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ 3 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d6c69ec..2430cc9 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -835,6 +835,7 @@ clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -845,6 +846,7 @@ clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -854,6 +856,7 @@ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -863,6 +866,7 @@ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 3>; + ahb-burst-config = <0x0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 36ab8e0..9f283cc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -680,6 +680,7 @@ clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -690,6 +691,7 @@ clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -699,6 +701,7 @@ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; + ahb-burst-config = <0x0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7a24fee..0cdfa01 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -742,6 +742,7 @@ fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -752,6 +753,7 @@ clocks = <&clks IMX6SX_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; status = "disabled"; }; @@ -763,6 +765,7 @@ fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; status = "disabled"; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/12] usb: chipidea: add ahb burst configuration
The users can change it through dts or platform data if they
want to change the default value.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/bits.h | 3 +++
drivers/usb/chipidea/core.c | 18 ++
include/linux/usb/chipidea.h | 2 ++
3 files changed, 23 insertions(+)
diff --git a/drivers/usb/chipidea/bits.h b/drivers/usb/chipidea/bits.h
index 3cb9bda..3af6213 100644
--- a/drivers/usb/chipidea/bits.h
+++ b/drivers/usb/chipidea/bits.h
@@ -25,6 +25,9 @@
#define VERSION (0xF << 25)
#define CIVERSION(0x7 << 29)
+/* SBUSCFG */
+#define AHBBRST_MASK 0x7
+
/* HCCPARAMS */
#define HCCPARAMS_LEN BIT(17)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index f713e32..c0e6bb1 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -412,6 +412,8 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
*/
void ci_platform_config(struct ci_hdrc *ci, int usb_mode)
{
+ bool override_needed;
+
if (usb_mode == USBMODE_CM_DC) {
if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
@@ -439,6 +441,12 @@ void ci_platform_config(struct ci_hdrc *ci, int usb_mode)
hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
}
+ /* Override AHB burst configuration if needed */
+ override_needed = hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK) !=
+ (ci->platdata->ahbburst_config & AHBBRST_MASK);
+ if (override_needed)
+ hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
+ ci->platdata->ahbburst_config);
}
/**
@@ -633,6 +641,16 @@ static int ci_get_platdata(struct device *dev,
}
}
+ if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
+ ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
+ &platdata->ahbburst_config);
+ if (ret) {
+ dev_err(dev,
+ "failed to get ahb-burst-config value\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index d3906a4..4d7ceb3 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -32,6 +32,7 @@ struct ci_hdrc_platform_data {
#define CI_HDRC_DISABLE_HOST_STREAMING BIT(9)
#define CI_HDRC_DISABLE_STREAMING (CI_HDRC_DISABLE_DEVICE_STREAMING | \
CI_HDRC_DISABLE_HOST_STREAMING)
+#define CI_HDRC_OVERRIDE_AHB_BURST BIT(10)
enum usb_dr_modedr_mode;
#define CI_HDRC_CONTROLLER_RESET_EVENT 0
#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
@@ -40,6 +41,7 @@ struct ci_hdrc_platform_data {
booltpl_support;
/* interrupt threshold value for gadget */
u32 gadget_itc_setting;
+ u32 ahbburst_config;
};
/* Default offset of capability registers */
--
1.9.1
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[PATCH 09/12] usb: chipidea: usbmisc_imx: add unburst setting for imx6
With this setting and AHBBRST at SBUSCFG as "Incremental burst of
unspecified length", each unburst size can be taken as one single transfer.
It is benefit for unburst size transfer.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/usbmisc_imx.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/chipidea/usbmisc_imx.c
b/drivers/usb/chipidea/usbmisc_imx.c
index 8af070f..6a6e73c 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -54,6 +54,7 @@
#define MX53_USB_PHYCTRL1_PLLDIV_MASK 0x3
#define MX53_USB_PLL_DIV_24_MHZ0x01
+#define MX6_BM_UNBURST_SETTING BIT(1)
#define MX6_BM_OVER_CUR_DISBIT(7)
#define MX6_BM_WAKEUP_ENABLE BIT(10)
#define MX6_BM_ID_WAKEUP BIT(16)
@@ -255,14 +256,21 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data
*data)
if (data->index > 3)
return -EINVAL;
+ spin_lock_irqsave(&usbmisc->lock, flags);
+
if (data->disable_oc) {
- spin_lock_irqsave(&usbmisc->lock, flags);
reg = readl(usbmisc->base + data->index * 4);
writel(reg | MX6_BM_OVER_CUR_DIS,
usbmisc->base + data->index * 4);
- spin_unlock_irqrestore(&usbmisc->lock, flags);
}
+ /* SoC unburst setting */
+ reg = readl(usbmisc->base + data->index * 4);
+ writel(reg | MX6_BM_UNBURST_SETTING,
+ usbmisc->base + data->index * 4);
+
+ spin_unlock_irqrestore(&usbmisc->lock, flags);
+
usbmisc_imx6q_set_wakeup(data, false);
return 0;
--
1.9.1
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[PATCH 12/12] usb: chipidea: add burst size configuration interface
The user can adjust it through dts or other platform interfaces.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/bits.h | 4
drivers/usb/chipidea/ci.h| 1 +
drivers/usb/chipidea/core.c | 39 +++
include/linux/usb/chipidea.h | 2 ++
4 files changed, 46 insertions(+)
diff --git a/drivers/usb/chipidea/bits.h b/drivers/usb/chipidea/bits.h
index 3af6213..466ce89 100644
--- a/drivers/usb/chipidea/bits.h
+++ b/drivers/usb/chipidea/bits.h
@@ -56,6 +56,10 @@
#define DEVICEADDR_USBADRABIT(24)
#define DEVICEADDR_USBADR (0x7FUL << 25)
+/* BURSTSIZE */
+#define RX_BURST_MASK 0xff
+#define TX_BURST_MASK 0xff00
+
/* PORTSC */
#define PORTSC_CCSBIT(0)
#define PORTSC_CSCBIT(1)
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index 888606b..232156b 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -50,6 +50,7 @@ enum ci_hw_regs {
OP_USBINTR,
OP_DEVICEADDR,
OP_ENDPTLISTADDR,
+ OP_BURSTSIZE,
OP_PORTSC,
OP_DEVLC,
OP_OTGSC,
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index c0e6bb1..beb4236 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -84,6 +84,7 @@ static const u8 ci_regs_nolpm[] = {
[OP_USBINTR]= 0x08U,
[OP_DEVICEADDR] = 0x14U,
[OP_ENDPTLISTADDR] = 0x18U,
+ [OP_BURSTSIZE] = 0x20U,
[OP_PORTSC] = 0x44U,
[OP_DEVLC] = 0x84U,
[OP_OTGSC] = 0x64U,
@@ -106,6 +107,7 @@ static const u8 ci_regs_lpm[] = {
[OP_USBINTR]= 0x08U,
[OP_DEVICEADDR] = 0x14U,
[OP_ENDPTLISTADDR] = 0x18U,
+ [OP_BURSTSIZE] = 0x20U,
[OP_PORTSC] = 0x44U,
[OP_DEVLC] = 0x84U,
[OP_OTGSC] = 0xC4U,
@@ -412,6 +414,7 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
*/
void ci_platform_config(struct ci_hdrc *ci, int usb_mode)
{
+ u32 ahb_burst_config;
bool override_needed;
if (usb_mode == USBMODE_CM_DC) {
@@ -447,6 +450,22 @@ void ci_platform_config(struct ci_hdrc *ci, int usb_mode)
if (override_needed)
hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
ci->platdata->ahbburst_config);
+
+ ahb_burst_config = hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK);
+
+ /* Override tx burst size if needed */
+ override_needed = hw_read(ci, OP_BURSTSIZE, RX_BURST_MASK) !=
+ (ci->platdata->rx_burst_size & RX_BURST_MASK);
+ if (!ahb_burst_config && override_needed)
+ hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
+ ci->platdata->rx_burst_size);
+
+ /* Override tx burst size if needed */
+ override_needed = ((hw_read(ci, OP_BURSTSIZE, TX_BURST_MASK) >>
+ __ffs(TX_BURST_MASK)) != ci->platdata->tx_burst_size);
+ if (!ahb_burst_config && override_needed)
+ hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
+ ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
}
/**
@@ -651,6 +670,26 @@ static int ci_get_platdata(struct device *dev,
}
}
+ if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
+ ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
+ &platdata->tx_burst_size);
+ if (ret) {
+ dev_err(dev,
+ "failed to get tx-burst-size-dword value\n");
+ return ret;
+ }
+ }
+
+ if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
+ ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
+ &platdata->rx_burst_size);
+ if (ret) {
+ dev_err(dev,
+ "failed to get rx-burst-size-dword value\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index 4d7ceb3..b5f0d7b 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -42,6 +42,8 @@ struct ci_hdrc_platform_data {
/* interrupt threshold value for gadget */
u32 gadget_itc_setting;
u32 ahbburst_config;
+ u32 tx_burst_size;
+ u32 rx_burst_size;
};
/* Default offset of capability registers */
--
1.9.1
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[PATCH 11/12] ARM: imx6: change default burst size for USB
It can improve the USB performance when choosing larger burst size at some systems (bus size is larger), there is no side effect if this burst size is larger than bus size. Signed-off-by: Peter Chen --- arch/arm/boot/dts/imx6qdl.dtsi | 8 arch/arm/boot/dts/imx6sl.dtsi | 6 ++ arch/arm/boot/dts/imx6sx.dtsi | 6 ++ 3 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2430cc9..4446218 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -836,6 +836,8 @@ fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -847,6 +849,8 @@ fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -857,6 +861,8 @@ clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -867,6 +873,8 @@ clocks = <&clks IMX6QDL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 3>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 9f283cc..9117c4c 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -681,6 +681,8 @@ fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -692,6 +694,8 @@ fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -702,6 +706,8 @@ clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 0cdfa01..464cc3a 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -743,6 +743,8 @@ fsl,usbmisc = <&usbmisc 0>; fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -754,6 +756,8 @@ fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; @@ -766,6 +770,8 @@ phy_type = "hsic"; fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; -- 1.9.1 -- To unsubscribe from this list: send the line
[PATCH 00/12] USB: chipidea: patchset for performance improvement
Hi all, In this patch set, I add some interfaces for tuning the performance of chipidea usb driver. With this set, the USB performance can be improved at some user cases with suitable parameters. The main changes: - Interface to tune interrupt threshold control, and set 'Immediate' for default value - The glue layer can disable stream mode according to USB role - Interface to tune AHB burst configuration at SBUSCFG - Interface to tune tx/rx burst size - i.mx changes for achieving better performance, it can reduce the latecy between bus and USB FIFO, and reduce the overrun and underrun occurrences, it is useful for the system bus is busy. we see great improvement for ISO transfer, eg, high resolution USB camera when the bus is busy. Below are some test results at imx6sx sdb board (set ehci_hcd.park=3 at bootargs), the tests are done at v4.0 kernel, no other bus loading during the tests, so we have not seen performance change for some use cases. USB Mass Storage (Host mode) With Patch Set Without Patch Set R: 26.9 MB/s27 MB/s W: 25.2 MB/s24.5 MB/s 1G USB Ethernet Card With Patch Set Without Patch Set TX: 186 Mb/s185 Mb/s RX: 219 Mb/s216 Mb/s g_ncm (Device Mode) With Patch Set Without Patch Set TX: 166MB/s 163MB/s RX: 230MB/s 184MB/s Peter Chen (12): Doc: usb: ci-hdrc-imx: add gadget-itc-setting for binding doc usb: chipidea: set ITC to 0 for device mode usb: chipidea: define stream mode disable for both roles usb: chipidea: imx: add stream mode enable for device mode at imx6sl/imx6sx usb: chipidea: introduce ci_platform_config Doc: usb: ci-hdrc-imx: add ahb-burst-config for binding doc ARM: imx6: set ahb-burst-config as 0 for USB usb: chipidea: add ahb burst configuration usb: chipidea: usbmisc_imx: add unburst setting for imx6 Doc: usb: ci-hdrc-imx: add tx(rx)-burst-config-dword for binding doc ARM: imx6: change default burst size for USB usb: chipidea: add burst size configuration interface .../devicetree/bindings/usb/ci-hdrc-imx.txt| 12 +++ arch/arm/boot/dts/imx6qdl.dtsi | 12 +++ arch/arm/boot/dts/imx6sl.dtsi | 9 ++ arch/arm/boot/dts/imx6sx.dtsi | 9 ++ drivers/usb/chipidea/bits.h| 7 ++ drivers/usb/chipidea/ci.h | 3 + drivers/usb/chipidea/ci_hdrc_imx.c | 14 ++- drivers/usb/chipidea/core.c| 119 +++-- drivers/usb/chipidea/host.c| 6 +- drivers/usb/chipidea/usbmisc_imx.c | 12 ++- include/linux/usb/chipidea.h | 11 +- 11 files changed, 191 insertions(+), 23 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/12] usb: chipidea: introduce ci_platform_config
It is used to configure controller parameters according to
platform data, like speed, interrupt threshold, stream mode, etc.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/ci.h | 2 ++
drivers/usb/chipidea/core.c | 57 +++--
drivers/usb/chipidea/host.c | 6 +
3 files changed, 43 insertions(+), 22 deletions(-)
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index aeec5f0..888606b 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -426,4 +426,6 @@ u8 hw_port_test_get(struct ci_hdrc *ci);
int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
u32 value, unsigned int timeout_ms);
+void ci_platform_config(struct ci_hdrc *ci, int usb_mode);
+
#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 4d79392..f713e32 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -403,6 +403,44 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
return ret;
}
+
+/**
+ * ci_platform_config: do controller configure
+ * @ci: the controller
+ * @usb_mode: the usb mode
+ *
+ */
+void ci_platform_config(struct ci_hdrc *ci, int usb_mode)
+{
+ if (usb_mode == USBMODE_CM_DC) {
+ if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
+ USBMODE_CI_SDIS);
+
+ /*
+* Set interrupt interval for device mode
+* host set ITC according to ehci-hcd module
+* parameter log2_irq_thresh
+*/
+ hw_write(ci, OP_USBCMD, 0xff,
+ ci->platdata->gadget_itc_setting << 16);
+ } else if (usb_mode == USBMODE_CM_HC) {
+ if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
+ USBMODE_CI_SDIS);
+ } else {
+ dev_warn(ci->dev, "USB mode in still not set\n");
+ }
+
+ if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
+ if (ci->hw_bank.lpm)
+ hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
+ else
+ hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
+ }
+
+}
+
/**
* hw_controller_reset: do controller reset
* @ci: the controller
@@ -447,35 +485,20 @@ int hw_device_reset(struct ci_hdrc *ci)
ci->platdata->notify_event(ci,
CI_HDRC_CONTROLLER_RESET_EVENT);
- if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
- hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
-
- if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
- if (ci->hw_bank.lpm)
- hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
- else
- hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
- }
-
/* USBMODE should be configured step by step */
hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
/* HW >= 2.3 */
hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
- /*
-* Set interrupt interval for device mode
-* host set ITC according to ehci-hcd module parameter log2_irq_thresh
-*/
- hw_write(ci, OP_USBCMD, 0xff,
- ci->platdata->gadget_itc_setting << 16);
-
if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
pr_err("cannot enter in %s device mode", ci_role(ci)->name);
pr_err("lpm = %i", ci->hw_bank.lpm);
return -ENODEV;
}
+ ci_platform_config(ci, USBMODE_CM_DC);
+
return 0;
}
diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
index b262c1c..c4f76b7 100644
--- a/drivers/usb/chipidea/host.c
+++ b/drivers/usb/chipidea/host.c
@@ -141,11 +141,7 @@ static int host_start(struct ci_hdrc *ci)
}
}
- if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED)
- hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
-
- if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
- hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
+ ci_platform_config(ci, USBMODE_CM_HC);
return ret;
--
1.9.1
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[PATCH 02/12] usb: chipidea: set ITC to 0 for device mode
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.
Reduce ITC value is benefit for USB performance, and the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 0 (immediate) as default value.
Signed-off-by: Peter Chen
---
drivers/usb/chipidea/core.c | 19 +++
include/linux/usb/chipidea.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 74fea4f..8af9cbf 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -463,6 +463,13 @@ int hw_device_reset(struct ci_hdrc *ci)
/* HW >= 2.3 */
hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
+ /*
+* Set interrupt interval for device mode
+* host set ITC according to ehci-hcd module parameter log2_irq_thresh
+*/
+ hw_write(ci, OP_USBCMD, 0xff,
+ ci->platdata->gadget_itc_setting << 16);
+
if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
pr_err("cannot enter in %s device mode", ci_role(ci)->name);
pr_err("lpm = %i", ci->hw_bank.lpm);
@@ -560,6 +567,8 @@ static irqreturn_t ci_irq(int irq, void *data)
static int ci_get_platdata(struct device *dev,
struct ci_hdrc_platform_data *platdata)
{
+ int ret;
+
if (!platdata->phy_mode)
platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
@@ -591,6 +600,16 @@ static int ci_get_platdata(struct device *dev,
if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
+ if (of_find_property(dev->of_node, "gadget-itc-setting", NULL)) {
+ ret = of_property_read_u32(dev->of_node, "gadget-itc-setting",
+ &platdata->gadget_itc_setting);
+ if (ret) {
+ dev_err(dev,
+ "failed to get gadget-itc-setting value\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index ab94f78..e69d829 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -35,6 +35,8 @@ struct ci_hdrc_platform_data {
void(*notify_event) (struct ci_hdrc *ci, unsigned event);
struct regulator*reg_vbus;
booltpl_support;
+ /* interrupt threshold value for gadget */
+ u32 gadget_itc_setting;
};
/* Default offset of capability registers */
--
1.9.1
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[PATCH 06/12] Doc: usb: ci-hdrc-imx: add ahb-burst-config for binding doc
It is used to change ahb burst configuration for platforms.
Signed-off-by: Peter Chen
---
Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index c21171e..a548502 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -22,6 +22,8 @@ Optional properties:
- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
- gadget-itc-setting: the ITC setting for gadget, the required value
should be aligned with ITC bits at register USBCMD.
+- ahb-burst-config: it is vendor dependent, the required value should be
+ aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7.
Examples:
usb@02184000 { /* USB OTG */
@@ -35,4 +37,5 @@ usb@02184000 { /* USB OTG */
maximum-speed = "full-speed";
tpl-support;
gadget-itc-setting = <0x4>; /* 4 micro-frames */
+ ahb-burst-config = <0x0>; /* Incremental burst of unspecified length */
};
--
1.9.1
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[PATCH 03/12] usb: chipidea: define stream mode disable for both roles
The chipidea IP has different limitations for host and device mode, see below errata, we may need to enable SDIS(Stream Disable Mode) at host mode. But we don't want it at device mode at some situations. TAR 9000378958 Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to Hang on OUT Retry Impacted Configuration: Host mode, all transfer types Description: The host core operating in streaming mode may under run while sending the data packet of an OUT transaction. This under run can occur if there are unexpected system delays in fetching the remaining packet data from memory. The host forces a bad CRC on the packet, the device detects the error and discards the packet. The host then retries a Bulk, Interrupt, or Control transfer if an under run occurs according to the USB specification. During simulations, it was found that the host does not issue the retry of the failed bulk OUT. It does not issue any other transactions except SOF packets that have incorrect frame numbers. The second failure mode occurs if the under run occurs on an ISO OUT transaction and the next ISO transaction is a zero byte packet. The host does not issue any transactions (including SOFs). The device detects a Suspend condition, reverts to full speed, and waits for resume signaling. A third failure mode occurs when the host under runs on an ISO OUT and the next ISO in the schedule is an ISO OUT with two max packets of 1024 bytes each. The host should issue MDATA for the first OUT followed by DATA1 for the second. However, it drops the MDATA transaction, and issues the DATA1 transaction. The system impact of this bug is the same regardless of the failure mode observed. The host core hangs, the ehci_ctrl state machine waits for the protocol engine to send the completion status for the corrupted transaction, which never occurs. No indication is sent to the host controller driver, no register bits change and no interrupts occur. Eventually the requesting application times out. Detailed internal behavior: The EHCI control state machine (ehci_ctrl) in the DMA block is responsible for parsing the schedules and initiating all transactions. The ehci_ctrl state machine passes the transaction details to the protocol block by writing the transaction information in to the TxFIFO. It then asserts the pe_hst_run_pkt signal to inform the host protocol state machine (pe_hst_state) that there is a packet in the TxFIFO. A tag of 0x0 indicates a start of packet with the data providing the following information: 35:32 Tag 31:30 Reserved 29:23 Endpoint (lowest 4 bits) 22:16 Address 15:10 Reserved 9:8 Endpoint speed 7:6 Endpoint type 5:6 Data Toggle 3:0 PID The pe_hst_state reads the packet information and constructs the packet and issues it to the PHY interface. The ehci_ctrl state machine writes the start transaction information in to the TxFIFO as 0x03002910c for the OUT packet that had the under run error. However, it writes 0xC3002910C for the retry of the Out transaction, which is incorrect. The pe_hst_state enters a bus timeout state after sending the bad CRC for the packet that under ran. It then purges any data that was back filled in to the TxFIFO for the packet that under ran. The pe_hst_state machine stops purging the TxFIFO when it is empty or if it reads a location that has a tag of 0x0, indicating a start of packet command. The pe_hst_state reads 0xC3002910C and discards it as it does not decode to a start of packet command. It continues to purge the OUT data that has been pre-buffered for the OUT retry . The pe_hst_state detects the hst_packet_run signal and attempts to read the PID and address information from the TxFIFO. This location has packet data and so does not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD state where the frame_num_counter is updated. The frame_num_counter is updated with the data in the TxFIFO. In this case, the data is incorrect as the ehci_ctrl state machine did not initiate the load. The hst_pe_state machine detects the SOF request signal and sends an SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine waits indefinitely in the run_pkt state waiting for the completion status from pe_hst_state machine, which will never happen. The ISO failure case is similar except that there is no retry for ISO. The ehci_ctrl state machine moves to the next transfer in the periodic schedule. If the under run occurs on the last entry of the periodic list then it moves to the Async schedule. In the case of ISO OUT simulations, the next ISO is a zero byte OUT and again the start of packet command gets corrupted. The TxFIFO is empty when the hst_pe_state attempts to read the Address and PID information as the transaction is a zero byte packet. This results in the hst_pe_state machine staying in the GET_PID state, which means that it does not issue any transactions (including SOFs). The device detects a Suspend condition and rever
[PATCH 01/12] Doc: usb: ci-hdrc-imx: add gadget-itc-setting for binding doc
It is used to configure the ITC (in register USBCMD) value
for gadget mode.
Signed-off-by: Peter Chen
---
Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index 38a5480..c21171e 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -20,6 +20,8 @@ Optional properties:
- external-vbus-divider: enables off-chip resistor divider for Vbus
- maximum-speed: limit the maximum connection speed to "full-speed".
- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
+- gadget-itc-setting: the ITC setting for gadget, the required value
+ should be aligned with ITC bits at register USBCMD.
Examples:
usb@02184000 { /* USB OTG */
@@ -32,4 +34,5 @@ usb@02184000 { /* USB OTG */
external-vbus-divider;
maximum-speed = "full-speed";
tpl-support;
+ gadget-itc-setting = <0x4>; /* 4 micro-frames */
};
--
1.9.1
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Re: [PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC
Dear Daniel, On Thu, 19 Mar 2015 01:13:21 + Daniel Stone wrote: > Hi Hyungwon, > > On 19 March 2015 at 01:02, Hyungwon Hwang > wrote: > >> > + /* > >> > +* The input PLL clock for MIPI DSI in Exynos5433 seems > >> > to be fixed > >> > +* by OSC CLK. > >> > +*/ > >> > + fin = 24 * MHZ; > >> > >> Er, is this always true on other platforms as well? Shouldn't this > >> be a part of the DeviceTree description? > > > > I forgot to change the comment in development. Finally it is found > > that all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I > > will remove the comment, but remain the code as it is. > > Fair enough. Should pll_clk be removed from the DT description then, > if it's fixed to the oscillator? Yes. It is redundant to represent pll_clk in DT, and it should be removed. > > > Thanks for your review. I will send it again with the changes you > > suggested. > > Thanks very much! > > Cheers, > Daniel Best regards, Hyungwon Hwang -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC
Hi Hyungwon, On 19 March 2015 at 01:02, Hyungwon Hwang wrote: >> > + /* >> > +* The input PLL clock for MIPI DSI in Exynos5433 seems to >> > be fixed >> > +* by OSC CLK. >> > +*/ >> > + fin = 24 * MHZ; >> >> Er, is this always true on other platforms as well? Shouldn't this be >> a part of the DeviceTree description? > > I forgot to change the comment in development. Finally it is found that > all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I will remove > the comment, but remain the code as it is. Fair enough. Should pll_clk be removed from the DT description then, if it's fixed to the oscillator? > Thanks for your review. I will send it again with the changes you > suggested. Thanks very much! Cheers, Daniel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC
Dear Daniel,
On Wed, 18 Mar 2015 09:52:33 +
Daniel Stone wrote:
> Hi,
>
> On 18 March 2015 at 08:16, Hyungwon Hwang
> wrote:
> > +#define REG(dsi, reg) ((dsi)->reg_base +
> > dsi->driver_data->regs[(reg)])
>
> This seems like a good change in general, but please split it up: it
> makes bisection much easier if you have one patch which adds no
> functionality and should have exactly the same behaviour, and then
> another patch which introduces your changes.
Yes. I agree with you.
>
> > @@ -431,15 +579,11 @@ static unsigned long
> > exynos_dsi_set_pll(struct exynos_dsi *dsi, u16 m;
> > u32 reg;
> >
> > - clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
> > -
> > - fin = clk_get_rate(dsi->pll_clk);
> > - if (!fin) {
> > - dev_err(dsi->dev, "failed to get PLL clock
> > frequency\n");
> > - return 0;
> > - }
> > -
> > - dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
> > + /*
> > +* The input PLL clock for MIPI DSI in Exynos5433 seems to
> > be fixed
> > +* by OSC CLK.
> > +*/
> > + fin = 24 * MHZ;
>
> Er, is this always true on other platforms as well? Shouldn't this be
> a part of the DeviceTree description?
I forgot to change the comment in development. Finally it is found that
all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I will remove
the comment, but remain the code as it is.
>
> > @@ -509,7 +656,7 @@ static int exynos_dsi_enable_clock(struct
> > exynos_dsi *dsi) dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu,
> > esc_clk = %lu\n", hs_clk, byte_clk, esc_clk);
> >
> > - reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
> > + reg = readl(REG(dsi, DSIM_CLKCTRL_REG));
>
> Instead of this readl(REG()) pattern you have everywhere, maybe it
> would be easier to introduce a dsi_read_reg(dsi, reg_enum_value)
> helper, and the same for write_reg.
I think that it can make the code more readable. I agree.
>
> > @@ -1720,18 +1873,16 @@ static int exynos_dsi_probe(struct
> > platform_device *pdev) return -EPROBE_DEFER;
> > }
> >
> > - dsi->pll_clk = devm_clk_get(dev, "pll_clk");
> > - if (IS_ERR(dsi->pll_clk)) {
> > - dev_info(dev, "failed to get dsi pll input
> > clock\n");
> > - ret = PTR_ERR(dsi->pll_clk);
> > - goto err_del_component;
> > - }
> > -
> > - dsi->bus_clk = devm_clk_get(dev, "bus_clk");
> > - if (IS_ERR(dsi->bus_clk)) {
> > - dev_info(dev, "failed to get dsi bus clock\n");
> > - ret = PTR_ERR(dsi->bus_clk);
> > - goto err_del_component;
> > + dsi->clks = devm_kzalloc(dev,
> > + sizeof(*dsi->clks) *
> > dsi->driver_data->num_clks,
> > + GFP_KERNEL);
> > + for (i = 0; i < dsi->driver_data->num_clks; i++) {
> > + dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
> > + if (IS_ERR(dsi->clks[i])) {
> > + dev_info(dev, "failed to get dsi pll input
> > clock\n");
>
> This error message seems wrong; it should contain the name of the
> actual failing clock.
Oh. I forgot. I will change it.
Thanks for your review. I will send it again with the changes you
suggested.
>
> Cheers,
> Daniel
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Re: [PATCH 1/3] mfd: devicetree: qcom_rpm: document IPQ8064 resources
On 11/24/14 02:38, Lee Jones wrote: > On Thu, 20 Nov 2014, Josh Cartwright wrote: > >> The IPQ8064 SoC has several RPM-controlled resources, an NSS fabrick >> clock and four regulator resources. Provide definitions for them. >> >> Signed-off-by: Josh Cartwright >> --- >> Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 6 +- >> include/dt-bindings/mfd/qcom-rpm.h | 6 ++ >> 2 files changed, 11 insertions(+), 1 deletion(-) > For my own reference: > > Acked-by: Lee Jones Lee, can you pick this patch up please? > >> diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt >> b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt >> index 4264021..6d4e3ec 100644 >> --- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt >> +++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt >> @@ -12,6 +12,7 @@ frequencies. >> "qcom,rpm-apq8064" >> "qcom,rpm-msm8660" >> "qcom,rpm-msm8960" >> +"qcom,rpm-ipq8064" >> >> - reg: >> Usage: required >> @@ -67,6 +68,7 @@ of valid subnodes that can operate on these resources. >> "qcom,rpm-pm8901-ftsmps" >> "qcom,rpm-pm8921-smps" >> "qcom,rpm-pm8921-ftsmps" >> +"qcom,rpm-smb208" >> >> - reg: >> Usage: required >> @@ -76,7 +78,9 @@ of valid subnodes that can operate on these resources. >> QCOM_RPM_PM8058_SMPS0 - QCOM_RPM_PM8058_SMPS4, >> QCOM_RPM_PM8821_SMPS1 - QCOM_RPM_PM8821_SMPS2, >> QCOM_RPM_PM8901_SMPS0 - QCOM_RPM_PM8901_SMPS4, >> -QCOM_RPM_PM8921_SMPS1 - QCOM_RPM_PM8921_SMPS8 >> +QCOM_RPM_PM8921_SMPS1 - QCOM_RPM_PM8921_SMPS8, >> +QCOM_RPM_SMB208_S1a, QCOM_RPM_SMB208_S1b, >> +QCOM_RPM_SMB208_S2a, QCOM_RPM_SMB208_S2b >> >> - bias-pull-down: >> Usage: optional >> diff --git a/include/dt-bindings/mfd/qcom-rpm.h >> b/include/dt-bindings/mfd/qcom-rpm.h >> index 388a6f3..13a9d4b 100644 >> --- a/include/dt-bindings/mfd/qcom-rpm.h >> +++ b/include/dt-bindings/mfd/qcom-rpm.h >> @@ -141,6 +141,12 @@ >> #define QCOM_RPM_SYS_FABRIC_MODE131 >> #define QCOM_RPM_USB_OTG_SWITCH 132 >> #define QCOM_RPM_VDDMIN_GPIO133 >> +#define QCOM_RPM_NSS_FABRIC_0_CLK 134 >> +#define QCOM_RPM_NSS_FABRIC_1_CLK 135 >> +#define QCOM_RPM_SMB208_S1a 136 >> +#define QCOM_RPM_SMB208_S1b 137 >> +#define QCOM_RPM_SMB208_S2a 138 >> +#define QCOM_RPM_SMB208_S2b 139 >> >> /* >> * Constants used to select force mode for regulators. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: dts: brcmstb: add IRQ0 controller
This L2 controller handles multiplexing a few different interrupts. We
also need it for configuring the interrupt forwarding masks for the
UART.
With this, we can *now* boot BCM7445 to a prompt using the upstream
kernel + DTB.
Signed-off-by: Brian Norris
---
arch/arm/boot/dts/bcm7445.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index b183dc99111a..9eaeac8dce1b 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -96,6 +96,18 @@
"syscon";
reg = <0x452000 0x100>;
};
+
+ irq0_intc: interrupt-controller@f040a780 {
+ compatible = "brcm,bcm7120-l2-intc";
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ reg = <0x40a780 0x8>;
+ interrupt-controller;
+ interrupts = ,
+;
+ brcm,int-map-mask = <0x25c>, <0x700>;
+ brcm,int-fwd-mask = <0x7>;
+ };
};
smpboot {
--
1.9.1
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[PATCH 1/2] ARM: dts: brcmstb: un-hexify clock frequency
This value makes much more sense in decimal.
Signed-off-by: Brian Norris
---
arch/arm/boot/dts/bcm7445.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 0ca0f4e523d0..b183dc99111a 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -76,7 +76,7 @@
reg-shift = <2>;
reg-io-width = <4>;
interrupts = ;
- clock-frequency = <0x4d3f640>;
+ clock-frequency = <8100>;
};
sun_top_ctrl: syscon@404000 {
--
1.9.1
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Re: [PATCH v3 00/15] Add support to STMicroelectronics STM32 family
Hi Maxime, I tested this patch-set on Linux 4.0-rc4 for STM32F429IDISCOVERY board. I completed the kernel booting successfully without any modification . Looks good to me for this patch-set. Tested-by: Chanwoo Choi Best Regards, Chanwoo Choi On 03/13/2015 06:55 AM, Maxime Coquelin wrote: > From: Maxime Coquelin > > This third round tries to address most of the comments made on previous > series. > > It contains few less patches, as the reset_controller_of_init() patch has been > removed, now that the bootlaoder handles the reset of the timers. > > The pinctrl driver has also been removed after Linus review. > It will be reworked to use the generic pinconf bindings, and may contain > changes for other machines (Mediatek), to add support for pinmux property > handling directly in pinconf-generic. > > STM32 MCUs are Cortex-M CPU, used in various applications (consumer > electronics, industrial applications, hobbyists...). > Datasheets, user and programming manuals are publicly available on > STMicroelectronics website. > > With this series applied, the STM32F419 Discovery can boot succesfully. > > > Changes since v2: > - > - Remove pinctrl driver from the series. > - Remove reset_controller_of_init(), and reset the timers in the bootloader > - Add HW flow contrl property for serial driver > - Lots of changes in the DTS file, as per Andreas recommendations > - Some Kconfig clean-ups > - Adapt the config to be compatible with Andreas' bootwrapper, except UART > port. > - Various fixes in documentation > > Changes since v1: > - > - Move bindings documentation in their own patches (Andreas) > - Rename ARM System timer to armv7m-systick (Rob) > - Add clock-frequency property handling in armv7m-systick (Rob) > - Re-factor the reset controllers into a single controller (Philipp) > - Add kerneldoc to reset_controller_of_init (Philipp) > - Add named constants in include/dt-bindings/reset/ (Philipp) > - Make pinctrl driver to depend on ARCH_STM32 or COMPILE_TEST (Geert) > - Introduce CPUV7M_NUM_IRQ config flag to indicate the number of interrupts > supported by the MCU, in order to limit memory waste in vectors' table (Uwe) > > > Maxime Coquelin (15): > scripts: link-vmlinux: Don't pass page offset to kallsyms if XIP > Kernel > ARM: ARMv7-M: Enlarge vector table up to 256 entries > dt-bindings: Document the ARM System timer bindings > clocksource: Add ARM System timer driver > dt-bindings: Document the STM32 reset bindings > drivers: reset: Add STM32 reset driver > dt-bindings: Document the STM32 timer bindings > clockevent: Add STM32 Timer driver > dt-bindings: Document the STM32 USART bindings > serial: stm32-usart: Add STM32 USART Driver > ARM: Add STM32 family machine > ARM: dts: Add ARM System timer as clockevent in armv7m > ARM: dts: Introduce STM32F429 MCU > ARM: configs: Add STM32 defconfig > MAINTAINERS: Add entry for STM32 MCUs > > Documentation/arm/stm32/overview.txt | 32 + > Documentation/arm/stm32/stm32f429-overview.txt | 22 + > .../devicetree/bindings/arm/armv7m_systick.txt | 26 + > .../devicetree/bindings/reset/st,stm32-rcc.txt | 102 +++ > .../devicetree/bindings/serial/st,stm32-usart.txt | 32 + > .../devicetree/bindings/timer/st,stm32-timer.txt | 22 + > MAINTAINERS| 8 + > arch/arm/Kconfig | 18 + > arch/arm/Makefile | 1 + > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/armv7-m.dtsi | 6 + > arch/arm/boot/dts/stm32f429-disco.dts | 71 +++ > arch/arm/boot/dts/stm32f429.dtsi | 226 +++ > arch/arm/configs/stm32_defconfig | 71 +++ > arch/arm/kernel/entry-v7m.S| 13 +- > arch/arm/mach-stm32/Makefile | 1 + > arch/arm/mach-stm32/Makefile.boot | 3 + > arch/arm/mach-stm32/board-dt.c | 19 + > arch/arm/mm/Kconfig| 15 + > drivers/clocksource/Kconfig| 15 + > drivers/clocksource/Makefile | 2 + > drivers/clocksource/armv7m_systick.c | 78 +++ > drivers/clocksource/timer-stm32.c | 184 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-stm32.c| 125 > drivers/tty/serial/Kconfig | 17 + > drivers/tty/serial/Makefile| 1 + > drivers/tty/serial/stm32-usart.c | 695 > + > include/uapi/linux/serial_core.h | 3 + > scripts/link-vmlinux.sh| 2 +- > 30 files changed, 1807 insertions(+), 5 deletions(-) > create mode 100644 Documentation/arm/stm32/overview.
Re: [PATCH 3/4 v4] mailbox: Enable BCM2835 mailbox support
Stephen Warren writes: > On 03/12/2015 08:32 PM, Eric Anholt wrote: >> diff --git a/drivers/mailbox/bcm2835-mailbox.c >> b/drivers/mailbox/bcm2835-mailbox.c > >> +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & >> 0xf)) >> +#define MBOX_CHAN(msg) ((msg) & 0xf) >> +#define MBOX_DATA28(msg)((msg) & ~0xf) > > Even the concept of storing channel IDs in the LSBs feels like it might > be RPi-firmware-specific rather than HW-specific? I guess? If we found another firmware protocol, we could have that device's dt just specify a different compatible string. But in the absence of another firmware to talk to, I'm not sure what you want here. Note that Roku's kernel code dump doesn't even communicate through the mailbox. vcio.c exists, but is disconnected from the build. signature.asc Description: PGP signature
Re: [PATCH v3 1/4] i2c: mux-pinctrl: Rework to honor disabled child nodes
On 18.03.2015 15:00, Wolfram Sang wrote: On Wed, Mar 18, 2015 at 02:23:18PM +0100, Sebastian Hesselbarth wrote: Possible. But this change just makes i2c-mux-pinctrl honor status property at all. There is no functional change except it now allows you to disable any of the sub-busses. Actually, this is the feature I like. However, I wonder if we shouldn't have that in the core, say in of_i2c_register_devices()? Hmm, looking at of_i2c_register_devices(): for_each_available_child_of_node(adap->dev.of_node, node) of_i2c_register_device(adap, node); already honors status properties by using for_each_available_foo. Therefore, i2c-core will also skip i2c device nodes disabled by status property. I agree that this driver still does not cope well with DYNAMIC_OF but neither did the former implementation. How about we settle this driver to this implementation now and wait for any maniac that wants to use it the way you are suggesting above? Sure. I don't want you to make this driver OF_DYNAMIC compatible. I just thought it makes it harder, though, e.g. you allocate memory for the number of active busses not the number of possibilities, so that would have to be reverted by the "maniac". I am still at the glimpse level, but what if we let the mux-pinctrl parse all the data (even for disabled busses), but only the enabled ones will get a muxed adapter because this is handled in of_i2c_register_devices()? I am not too deep into i2c-core, but AFAIKS i2c-mux-pinctrl is not an i2c device but an i2c mux that is dealt with differently? It is not probed with of_i2c_register_devices() but as a separate platform_device with a reference to the parent i2c bus. About the memory allocation for the maximum potential number of muxes: We would need some way to distinguish disabled from enabled muxes in i2c-mux-pinctrl's platform_data. i2c_mux_pinctrl_probe() is basically DT-agnostic and it should definitely stay that way. Currently, each mux within pd->bus_count requires a non-NULL pd->pinctrl_states[i] otherwise _probe() will bail out for all sub-busses. We could rework it to (a) deal with each sub-bus individually with respect to pinctrl_lookup_state() and i2c_add_mux_adapter() and (b) allow (and skip) muxes with pinctrl_states[i] == NULL for now and let the "maniac" deal with storing/re-probing the corresponding pinctrl_state name once it gets dynamically enabled. I am still not too eager working on it but if you insist, I can see what I can do as long as Stephen sticks with testing it on Tegra. ;) Sebastian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [REGRESSION] "of: Fix premature bootconsole disable with 'stdout-path'" breaks console on tty0
Hi Peter, On 03/18/2015 09:00 AM, Peter Hurley wrote: > On 03/17/2015 08:13 PM, Jon Masters wrote: Can you be specific about your concerns? The license has already been changed once (I instigated the request that lead to that change to drop several pages of terse terms that used to cover the first few pages). I have found the Microsoft team extremely responsive and amenable to resolving issues, so if you would do us the service of articulating what the concern is, I'll reach back out and get that addressed. I have a direct line into their server and legal teams to discuss this issue. >>> >>> Well, I'm deducing somewhat here because the code that would use the >>> SPCR table format has not been submitted. So I don't _know_ what license(s) >>> you intend to submit with. >> >> Fair enough. I wrote an initial quick and dirty implementation of SPCR >> parsing which I handed off to a colleague to cleanup. They are indeed >> planning such a submission. So such an implementation does in fact exist >> and there is an intent to submit. > > I assumed that because I received no reply to my first email that this > effort had been abandoned, so I didn't bother to raise the technical > issues that plague the devicetree hack. I apologize for that. These patches are currently being developed against an internal tree and we'll get them posted for review. >>> So if you and Microsoft have worked out some deal where Microsoft has >>> licensed the SPCR spec to you under GPL v2 terms, then, great! there is no >>> problem. >> >> I am willing to assist in brokering a discussion on this. But first we >> should ascertain what is necessary here and articulate that succinctly. > > The kernel source is licensed under GPL v2 (see ./COPYING), so contributions > are expected to be licensed under compatible terms. Just a sidenote, that this is a data structure, not code. There are plenty of other specifications and standards that the kernel uses that are licensed under a variety of terms. The specific issue seems to be the potential for conflict over the patent language in that document as possibly pertaining to implementations, not the specific license of the document per se. I'll ping a few and get a conversation going. Jon. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4 v4] mailbox: Enable BCM2835 mailbox support
Lee Jones writes: > On Thu, 12 Mar 2015, Eric Anholt wrote: > >> From: Lubomir Rintel >> >> Implement BCM2835 mailbox support as a device registered with the >> general purpose mailbox framework. Implementation based on commits by >> Lubomir Rintel [1], Suman Anna and Jassi Brar [2] on which to base the >> implementation. >> >> [1] >> http://lists.infradead.org/pipermail/linux-rpi-kernel/2013-April/000528.html >> [2] >> http://lists.infradead.org/pipermail/linux-rpi-kernel/2013-May/000546.html >> >> Signed-off-by: Lubomir Rintel >> Signed-off-by: Craig McGeachie >> Signed-off-by: Suman Anna >> Signed-off-by: Jassi Brar >> Signed-off-by: Eric Anholt >> Cc: Jassi Brar >> Acked-by: Lee Jones >> --- >> >> >> v2: Squashed Craig's work for review, carried over to new version of >> Mailbox framework (changes by Lubomir) >> >> v3: Fix multi-line comment style. Refer to the documentation by >> filename. Only declare one MODULE_AUTHOR. Alphabetize includes. >> Drop some excessive dev_dbg()s (changes by anholt). >> >> v4: Use the new bcm2835_peripheral_read_workaround(), drop the > > Can you explain to me why this is required (and don't just point me in > the direction of the other patch ;) ). You appear to be using the > non-relaxed variants of readl and writel, which already do memory > barriers, so I'm a little perplexed as to how the problem can arise. Hmm. A shorter restatement of the architecture requirement would be, I think, "Don't let there be two outstanding reads of different peripherals on the AXI bus, or the CPU might mis-assign the read results. Use rmb() to wait for the previous bus reads when you need to prevent this" arch/arm/include/asm/io.h's readl() does __iormb() after each __raw_readl(). Imagine taking an interrupt for a new peripheral between the driver's __raw_readl() and the following __iormb(): Now you've got two __raw_readl()s in between iormb()s and you can theoretically get unordered reads. We could hope that the architecture IRQ handler would happen to do an incidental rmb(), resolving the need to protect from interrupt handling inside of device drivers. The interrupt controller's presence at 0x7e00b200 sounds like it's an AXI peripheral, so it would need to be ensuring ordering of reads. However, it's doing readl_relaxed()s. So my rmb() at the start of my irq handler is silly -- if somebody got interrupted between readl and rmb, we've already had a chance to get the wrong result inside of the IRQ chip's status read. My new idea for handling this would be to: 1) Assume drivers don't exit with reads outstanding. This means they don't do a readl_relaxed() from an AXI peripheral at the end of a path without doing something with the result. 2) Make bcm2835_handle_irq() do this rmb() at the top, with the big explanation, to avoid a race against the interrupted code device being inside a readl() before the __iormb(). We don't worry about the 1-2 readl_relaxed()s inside of bcm2835_handle_irq(), because their return values get waited on before continuing on to calling the device driver, so the device driver knows its IRQ handler is being entered with no AXI reads outstanding. signature.asc Description: PGP signature
Re: [PATCH v3] dt-bindings: brcm: rationalize Broadcom documentation naming
On 18/03/15 15:08, Scott Branden wrote:
> This patchset attempts to standarize the naming of dt-bindings
> documents based on the Broadcom vendor prefix of brcm.
>
> Although there are no guidelines currently present for how to name
> the dt-bindings document the "vendor,binding.txt" style is in use by
> some of the other vendors.
>
> Acked-by: Stephen Warren
> Signed-off-by: Scott Branden
Acked-by: Florian Fainelli
> ---
> .../arm/bcm/{brcm,bcm11351-cpu-method => brcm,bcm11351-cpu-method.txt}| 0
> .../devicetree/bindings/arm/bcm/{bcm11351.txt => brcm,bcm11351.txt} | 0
> .../devicetree/bindings/arm/bcm/{bcm21664.txt => brcm,bcm21664.txt} | 0
> .../devicetree/bindings/arm/{bcm2835.txt => bcm/brcm,bcm2835.txt} | 0
> .../devicetree/bindings/arm/{bcm4708.txt => bcm/brcm,bcm4708.txt} | 0
> .../devicetree/bindings/arm/bcm/{bcm63138.txt => brcm,bcm63138.txt} | 0
> .../devicetree/bindings/arm/{brcm-brcmstb.txt => bcm/brcm,brcmstb.txt}| 0
> Documentation/devicetree/bindings/arm/bcm/{cygnus.txt => brcm,cygnus.txt} | 0
> Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt} | 0
> .../devicetree/bindings/clock/{bcm-kona-clock.txt => brcm,kona-ccu.txt} | 0
> .../devicetree/bindings/dma/{bcm2835-dma.txt => brcm,bcm2835-dma.txt} | 0
> .../devicetree/bindings/gpio/{gpio-bcm-kona.txt => brcm,kona-gpio.txt}| 0
> .../devicetree/bindings/i2c/{i2c-bcm-kona.txt => brcm,kona-i2c.txt} | 0
> Documentation/devicetree/bindings/mfd/{bcm590xx.txt => brcm,bcm59056.txt} | 0
> .../bindings/mips/brcm/{bcm3384-intc.txt => brcm,bcm3384-intc.txt}| 0
> Documentation/devicetree/bindings/mips/brcm/{bmips.txt => brcm,bmips.txt} | 0
> .../devicetree/bindings/mips/brcm/{cm-dsl.txt => brcm,cm-dsl.txt} | 0
> Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt} | 0
> .../devicetree/bindings/mmc/{kona-sdhci.txt => brcm,kona-sdhci.txt} | 0
> .../bindings/net/{broadcom-sf2.txt => brcm,bcm7445-switch-v4.0.txt} | 0
> .../devicetree/bindings/net/{broadcom-bcmgenet.txt => brcm,bcmgenet.txt} | 0
> .../bindings/net/{broadcom-systemport.txt => brcm,systemport.txt} | 0
> .../bindings/net/{broadcom-mdio-unimac.txt => brcm,unimac-mdio.txt} | 0
> .../devicetree/bindings/phy/{bcm-phy.txt => brcm,kona-usb2-phy.txt} | 0
> .../devicetree/bindings/pwm/{bcm-kona-pwm.txt => brcm,kona-pwm.txt} | 0
> .../{arm/bcm/kona-resetmgr.txt => reset/brcm,bcm21664-resetmgr.txt} | 0
> .../bindings/serial/{bcm63xx-uart.txt => brcm,bcm6345-uart.txt} | 0
> .../devicetree/bindings/sound/{bcm2835-i2s.txt => brcm,bcm2835-i2s.txt} | 0
> .../bindings/{arm/bcm/kona-timer.txt => timer/brcm,kona-timer.txt}| 0
> .../devicetree/bindings/{mips/brcm/usb.txt => usb/brcm,bcm3384-usb.txt} | 0
> .../bindings/{arm/bcm/kona-wdt.txt => watchdog/brcm,kona-wdt.txt} | 0
> 31 files changed, 0 insertions(+), 0 deletions(-)
> rename Documentation/devicetree/bindings/arm/bcm/{brcm,bcm11351-cpu-method
> => brcm,bcm11351-cpu-method.txt} (100%)
> rename Documentation/devicetree/bindings/arm/bcm/{bcm11351.txt =>
> brcm,bcm11351.txt} (100%)
> rename Documentation/devicetree/bindings/arm/bcm/{bcm21664.txt =>
> brcm,bcm21664.txt} (100%)
> rename Documentation/devicetree/bindings/arm/{bcm2835.txt =>
> bcm/brcm,bcm2835.txt} (100%)
> rename Documentation/devicetree/bindings/arm/{bcm4708.txt =>
> bcm/brcm,bcm4708.txt} (100%)
> rename Documentation/devicetree/bindings/arm/bcm/{bcm63138.txt =>
> brcm,bcm63138.txt} (100%)
> rename Documentation/devicetree/bindings/arm/{brcm-brcmstb.txt =>
> bcm/brcm,brcmstb.txt} (100%)
> rename Documentation/devicetree/bindings/arm/bcm/{cygnus.txt =>
> brcm,cygnus.txt} (100%)
> rename Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt}
> (100%)
> rename Documentation/devicetree/bindings/clock/{bcm-kona-clock.txt =>
> brcm,kona-ccu.txt} (100%)
> rename Documentation/devicetree/bindings/dma/{bcm2835-dma.txt =>
> brcm,bcm2835-dma.txt} (100%)
> rename Documentation/devicetree/bindings/gpio/{gpio-bcm-kona.txt =>
> brcm,kona-gpio.txt} (100%)
> rename Documentation/devicetree/bindings/i2c/{i2c-bcm-kona.txt =>
> brcm,kona-i2c.txt} (100%)
> rename Documentation/devicetree/bindings/mfd/{bcm590xx.txt =>
> brcm,bcm59056.txt} (100%)
> rename Documentation/devicetree/bindings/mips/brcm/{bcm3384-intc.txt =>
> brcm,bcm3384-intc.txt} (100%)
> rename Documentation/devicetree/bindings/mips/brcm/{bmips.txt =>
> brcm,bmips.txt} (100%)
> rename Documentation/devicetree/bindings/mips/brcm/{cm-dsl.txt =>
> brcm,cm-dsl.txt} (100%)
> rename Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt}
> (100%)
> rename Documentation/devicetree/bindings/mmc/{kona-sdhci.txt =>
> brcm,kona-sdhci.txt} (100%)
> rename Documentation/devicetree/bindings/net/{broadcom-sf2.txt =>
> brcm,bcm7445-switch-v4.0.txt} (100%)
> rename Documentati
Re: [PATCH v7] media: i2c: add support for omnivision's ov2659 sensor
Hi Prabhakar,
Lad Prabhakar wrote:
...
+static int ov2659_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov2659 *ov2659 =
+ container_of(ctrl->handler, struct ov2659, ctrls);
+ struct v4l2_mbus_framefmt *fmt = &ov2659->format;
+
+ switch (ctrl->id) {
+ case V4L2_CID_PIXEL_RATE:
+ if (fmt->code != MEDIA_BUS_FMT_SBGGR8_1X8)
+ ov2659->link_frequency->val =
+ ov2659->pdata->link_frequency / 2;
+ else
+ ov2659->link_frequency->val =
+ ov2659->pdata->link_frequency;
You should simply use v4l2_ctrl_s_ctrl_int64() in ..._set_fmt() as this
isn't really a proper volatile control, but its value depends on the format.
--
Sakari Ailus
sakari.ai...@linux.intel.com
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[PATCH v3] dt-bindings: brcm: rationalize Broadcom documentation naming
This patchset attempts to standarize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the dt-bindings document the "vendor,binding.txt" style is in use by
some of the other vendors.
Acked-by: Stephen Warren
Signed-off-by: Scott Branden
---
.../arm/bcm/{brcm,bcm11351-cpu-method => brcm,bcm11351-cpu-method.txt}| 0
.../devicetree/bindings/arm/bcm/{bcm11351.txt => brcm,bcm11351.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm21664.txt => brcm,bcm21664.txt} | 0
.../devicetree/bindings/arm/{bcm2835.txt => bcm/brcm,bcm2835.txt} | 0
.../devicetree/bindings/arm/{bcm4708.txt => bcm/brcm,bcm4708.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm63138.txt => brcm,bcm63138.txt} | 0
.../devicetree/bindings/arm/{brcm-brcmstb.txt => bcm/brcm,brcmstb.txt}| 0
Documentation/devicetree/bindings/arm/bcm/{cygnus.txt => brcm,cygnus.txt} | 0
Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt} | 0
.../devicetree/bindings/clock/{bcm-kona-clock.txt => brcm,kona-ccu.txt} | 0
.../devicetree/bindings/dma/{bcm2835-dma.txt => brcm,bcm2835-dma.txt} | 0
.../devicetree/bindings/gpio/{gpio-bcm-kona.txt => brcm,kona-gpio.txt}| 0
.../devicetree/bindings/i2c/{i2c-bcm-kona.txt => brcm,kona-i2c.txt} | 0
Documentation/devicetree/bindings/mfd/{bcm590xx.txt => brcm,bcm59056.txt} | 0
.../bindings/mips/brcm/{bcm3384-intc.txt => brcm,bcm3384-intc.txt}| 0
Documentation/devicetree/bindings/mips/brcm/{bmips.txt => brcm,bmips.txt} | 0
.../devicetree/bindings/mips/brcm/{cm-dsl.txt => brcm,cm-dsl.txt} | 0
Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt} | 0
.../devicetree/bindings/mmc/{kona-sdhci.txt => brcm,kona-sdhci.txt} | 0
.../bindings/net/{broadcom-sf2.txt => brcm,bcm7445-switch-v4.0.txt} | 0
.../devicetree/bindings/net/{broadcom-bcmgenet.txt => brcm,bcmgenet.txt} | 0
.../bindings/net/{broadcom-systemport.txt => brcm,systemport.txt} | 0
.../bindings/net/{broadcom-mdio-unimac.txt => brcm,unimac-mdio.txt} | 0
.../devicetree/bindings/phy/{bcm-phy.txt => brcm,kona-usb2-phy.txt} | 0
.../devicetree/bindings/pwm/{bcm-kona-pwm.txt => brcm,kona-pwm.txt} | 0
.../{arm/bcm/kona-resetmgr.txt => reset/brcm,bcm21664-resetmgr.txt} | 0
.../bindings/serial/{bcm63xx-uart.txt => brcm,bcm6345-uart.txt} | 0
.../devicetree/bindings/sound/{bcm2835-i2s.txt => brcm,bcm2835-i2s.txt} | 0
.../bindings/{arm/bcm/kona-timer.txt => timer/brcm,kona-timer.txt}| 0
.../devicetree/bindings/{mips/brcm/usb.txt => usb/brcm,bcm3384-usb.txt} | 0
.../bindings/{arm/bcm/kona-wdt.txt => watchdog/brcm,kona-wdt.txt} | 0
31 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/bcm/{brcm,bcm11351-cpu-method =>
brcm,bcm11351-cpu-method.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm11351.txt =>
brcm,bcm11351.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm21664.txt =>
brcm,bcm21664.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm2835.txt =>
bcm/brcm,bcm2835.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm4708.txt =>
bcm/brcm,bcm4708.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm63138.txt =>
brcm,bcm63138.txt} (100%)
rename Documentation/devicetree/bindings/arm/{brcm-brcmstb.txt =>
bcm/brcm,brcmstb.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{cygnus.txt =>
brcm,cygnus.txt} (100%)
rename Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt}
(100%)
rename Documentation/devicetree/bindings/clock/{bcm-kona-clock.txt =>
brcm,kona-ccu.txt} (100%)
rename Documentation/devicetree/bindings/dma/{bcm2835-dma.txt =>
brcm,bcm2835-dma.txt} (100%)
rename Documentation/devicetree/bindings/gpio/{gpio-bcm-kona.txt =>
brcm,kona-gpio.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-bcm-kona.txt =>
brcm,kona-i2c.txt} (100%)
rename Documentation/devicetree/bindings/mfd/{bcm590xx.txt =>
brcm,bcm59056.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bcm3384-intc.txt =>
brcm,bcm3384-intc.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bmips.txt =>
brcm,bmips.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{cm-dsl.txt =>
brcm,cm-dsl.txt} (100%)
rename Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt}
(100%)
rename Documentation/devicetree/bindings/mmc/{kona-sdhci.txt =>
brcm,kona-sdhci.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-sf2.txt =>
brcm,bcm7445-switch-v4.0.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-bcmgenet.txt =>
brcm,bcmgenet.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-systemport.txt =>
brcm,systemport.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadc
Re: [PATCH] dt-bindings: brcm: rationalize Broadcom documentation naming
On 15-03-18 03:03 PM, Stephen Warren wrote: On 03/18/2015 03:53 PM, Scott Branden wrote: Hi Stephen, On 15-03-18 12:42 PM, Stephen Warren wrote: On 03/18/2015 01:24 PM, Scott Branden wrote: This patchset attempts to standarize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Conceptually I'm fine with this. Acked-by: Stephen Warren The only comment I have is that some bindings refer to other bindings, e.g. an I2C controller binding might refer to the core I2C binding to define core I2C properties. Since this patch moves a couple files between directories, did you double-check that none of the pathnames in those references need fixing up? Yes, I read all the brcm documents and did not find references to the moved files. Oh, I meant references *from* the moved files to other files. Yes, some of the moved/renamed files reference other files. But those are to references to common dt-binding documentation files and of the form Documentation/devicetree/bindings/xxx/yyy.txt BTW, I just noticed that both your patches don't have signed-off-by lines. Whoops - thanks - will have to correct. Plus, add your Acked-by. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dt-bindings: brcm: rationalize Broadcom documentation naming
On 03/18/2015 03:53 PM, Scott Branden wrote: Hi Stephen, On 15-03-18 12:42 PM, Stephen Warren wrote: On 03/18/2015 01:24 PM, Scott Branden wrote: This patchset attempts to standarize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Conceptually I'm fine with this. Acked-by: Stephen Warren The only comment I have is that some bindings refer to other bindings, e.g. an I2C controller binding might refer to the core I2C binding to define core I2C properties. Since this patch moves a couple files between directories, did you double-check that none of the pathnames in those references need fixing up? Yes, I read all the brcm documents and did not find references to the moved files. Oh, I meant references *from* the moved files to other files. BTW, I just noticed that both your patches don't have signed-off-by lines. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 0/4] hwspinlock core & omap dt support
Hi Mark, On 03/12/2015 04:24 AM, Ohad Ben-Cohen wrote: > Hi Suman, > > On Thu, Mar 5, 2015 at 4:01 AM, Suman Anna wrote: >> This is the latest version of the hwspinlock dt support series, >> rebased onto v4.0-rc1 and addressing the long discussion on the >> bindings in v7 [1]. I really hope that this series can make it >> into 4.1. > > From a quick glance this looks great, thanks! > >> Mark, >> Can you please provide your Acked-by for the binding documents >> so that Ohad can pick up the patches for the next merge window? > > That would be perfect. Once we'll have it I could move forward with > this towards 4.1. Gentle reminder. Can you please provide your ack on the bindings in this series (Patches 1 & 3) for Ohad to queue up the series for 4.1. Thanks Suman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] dt-bindings: brcm: rationalize Broadcom documentation naming
This patchset attempts to standarize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the dt-bindings document the "vendor,binding.txt" style is in use by
some of the other vendors.
---
.../arm/bcm/{brcm,bcm11351-cpu-method => brcm,bcm11351-cpu-method.txt}| 0
.../devicetree/bindings/arm/bcm/{bcm11351.txt => brcm,bcm11351.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm21664.txt => brcm,bcm21664.txt} | 0
.../devicetree/bindings/arm/{bcm2835.txt => bcm/brcm,bcm2835.txt} | 0
.../devicetree/bindings/arm/{bcm4708.txt => bcm/brcm,bcm4708.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm63138.txt => brcm,bcm63138.txt} | 0
.../devicetree/bindings/arm/{brcm-brcmstb.txt => bcm/brcm,brcmstb.txt}| 0
Documentation/devicetree/bindings/arm/bcm/{cygnus.txt => brcm,cygnus.txt} | 0
Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt} | 0
.../devicetree/bindings/clock/{bcm-kona-clock.txt => brcm,kona-ccu.txt} | 0
.../devicetree/bindings/dma/{bcm2835-dma.txt => brcm,bcm2835-dma.txt} | 0
.../devicetree/bindings/gpio/{gpio-bcm-kona.txt => brcm,kona-gpio.txt}| 0
.../devicetree/bindings/i2c/{i2c-bcm-kona.txt => brcm,kona-i2c.txt} | 0
Documentation/devicetree/bindings/mfd/{bcm590xx.txt => brcm,bcm59056.txt} | 0
.../bindings/mips/brcm/{bcm3384-intc.txt => brcm,bcm3384-intc.txt}| 0
Documentation/devicetree/bindings/mips/brcm/{bmips.txt => brcm,bmips.txt} | 0
.../devicetree/bindings/mips/brcm/{cm-dsl.txt => brcm,cm-dsl.txt} | 0
Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt} | 0
.../devicetree/bindings/mmc/{kona-sdhci.txt => brcm,kona-sdhci.txt} | 0
.../bindings/net/{broadcom-sf2.txt => brcm,bcm7445-switch-v4.0.txt} | 0
.../devicetree/bindings/net/{broadcom-bcmgenet.txt => brcm,bcmgenet.txt} | 0
.../bindings/net/{broadcom-systemport.txt => brcm,systemport.txt} | 0
.../bindings/net/{broadcom-mdio-unimac.txt => brcm,unimac-mdio.txt} | 0
.../devicetree/bindings/phy/{bcm-phy.txt => brcm,kona-usb2-phy.txt} | 0
.../devicetree/bindings/pwm/{bcm-kona-pwm.txt => brcm,kona-pwm.txt} | 0
.../{arm/bcm/kona-resetmgr.txt => reset/brcm,bcm21664-resetmgr.txt} | 0
.../bindings/serial/{bcm63xx-uart.txt => brcm,bcm6345-uart.txt} | 0
.../devicetree/bindings/sound/{bcm2835-i2s.txt => brcm,bcm2835-i2s.txt} | 0
.../bindings/{arm/bcm/kona-timer.txt => timer/brcm,kona-timer.txt}| 0
.../devicetree/bindings/{mips/brcm/usb.txt => usb/brcm,bcm3384-usb.txt} | 0
.../bindings/{arm/bcm/kona-wdt.txt => watchdog/brcm,kona-wdt.txt} | 0
31 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/bcm/{brcm,bcm11351-cpu-method =>
brcm,bcm11351-cpu-method.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm11351.txt =>
brcm,bcm11351.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm21664.txt =>
brcm,bcm21664.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm2835.txt =>
bcm/brcm,bcm2835.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm4708.txt =>
bcm/brcm,bcm4708.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm63138.txt =>
brcm,bcm63138.txt} (100%)
rename Documentation/devicetree/bindings/arm/{brcm-brcmstb.txt =>
bcm/brcm,brcmstb.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{cygnus.txt =>
brcm,cygnus.txt} (100%)
rename Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt}
(100%)
rename Documentation/devicetree/bindings/clock/{bcm-kona-clock.txt =>
brcm,kona-ccu.txt} (100%)
rename Documentation/devicetree/bindings/dma/{bcm2835-dma.txt =>
brcm,bcm2835-dma.txt} (100%)
rename Documentation/devicetree/bindings/gpio/{gpio-bcm-kona.txt =>
brcm,kona-gpio.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-bcm-kona.txt =>
brcm,kona-i2c.txt} (100%)
rename Documentation/devicetree/bindings/mfd/{bcm590xx.txt =>
brcm,bcm59056.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bcm3384-intc.txt =>
brcm,bcm3384-intc.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bmips.txt =>
brcm,bmips.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{cm-dsl.txt =>
brcm,cm-dsl.txt} (100%)
rename Documentation/devicetree/bindings/misc/{smc.txt => brcm,kona-smc.txt}
(100%)
rename Documentation/devicetree/bindings/mmc/{kona-sdhci.txt =>
brcm,kona-sdhci.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-sf2.txt =>
brcm,bcm7445-switch-v4.0.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-bcmgenet.txt =>
brcm,bcmgenet.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-systemport.txt =>
brcm,systemport.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-mdio-unimac.txt =>
brcm,unimac-mdio.txt} (100%)
rena
Re: [PATCH] dt-bindings: brcm: rationalize Broadcom documentation naming
Hi Stephen, On 15-03-18 12:42 PM, Stephen Warren wrote: On 03/18/2015 01:24 PM, Scott Branden wrote: This patchset attempts to standarize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Conceptually I'm fine with this. Acked-by: Stephen Warren The only comment I have is that some bindings refer to other bindings, e.g. an I2C controller binding might refer to the core I2C binding to define core I2C properties. Since this patch moves a couple files between directories, did you double-check that none of the pathnames in those references need fixing up? Yes, I read all the brcm documents and did not find references to the moved files. In my search I found 4 more files inconsistently named from the Kona family. I'm submitting a new patch with those files renamed as well. Thanks, Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] i2c: driver for the Conexant Digicolor I2C controller
Hi,
On Mon, Feb 16, 2015 at 03:20:04PM +0200, Baruch Siach wrote:
> This commit adds a driver for the I2C master controller on the CX92755 SoC.
> The
> CX92755 is one SoC in the Conexant Digicolor series. This driver should
> support
> other SoCs from that series.
>
> Only 7bit slave addresses are currently supported.
>
> Tested on the Equinox CX92755 EVK, using i2c-tools utilities to read and write
> the on-chip (sic) audio codec.
>
> Signed-off-by: Baruch Siach
Looks mostly good.
> +static u32 dc_i2c_func(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
You probably want to advertise I2C_FUNC_NOSTART here, too?
And if you could rebase to something after 4.0-rc1, that would be much
appreciated.
Thanks,
Wolfram
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Re: [PATCH v7 0/6] wlcore: add device-tree support
* Eliad Peller [150318 09:39]: > Add device-tree support to the wlcore (wl12xx/wl18xx) > driver. > > Update the current users to use the bindings instead > of pdata-quirks. > > Finally, remove the deprecated wl12xx_platform_data > struct (along with the da850 board file code that > still uses it) > > v7: > * rebase (v4.0-rc4) > * fix wlcore_spi compilation (remove platform data) > * additional minor changes in driver code Thanks for updating it, looks good to me now and still works for me. Regards, Tony > v6: > * Add Luca's patches to pass irq_trigger/freq > * Support wl12xx as well > * Update all relevant platforms > > Eliad Peller (4): > dt: bindings: add TI's wilink wireless device > wlcore: add device-tree support > ARM: dts: add wl12xx/wl18xx bindings > wlcore: remove wl12xx_platform_data > > Luciano Coelho (2): > wlcore: set irq_trigger in board files instead of hiding behind a > quirk > wl12xx: use frequency instead of enumerations for pdata clocks > > .../devicetree/bindings/net/wireless/ti,wlcore.txt | 47 + > arch/arm/boot/dts/am335x-evmsk.dts | 11 ++ > arch/arm/boot/dts/omap3-cm-t3517.dts | 10 ++ > arch/arm/boot/dts/omap3-cm-t3730.dts | 10 ++ > arch/arm/boot/dts/omap3-evm-common.dtsi| 10 ++ > arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 9 ++ > arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 9 ++ > arch/arm/boot/dts/omap3-zoom3.dts | 10 ++ > arch/arm/boot/dts/omap4-panda-common.dtsi | 10 ++ > arch/arm/boot/dts/omap4-sdp.dts| 11 ++ > arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi | 10 ++ > arch/arm/mach-davinci/Kconfig | 11 -- > arch/arm/mach-davinci/board-da850-evm.c| 112 > - > arch/arm/mach-omap2/pdata-quirks.c | 74 -- > drivers/net/wireless/ti/wilink_platform_data.c | 25 - > drivers/net/wireless/ti/wl12xx/main.c | 63 ++-- > drivers/net/wireless/ti/wl12xx/wl12xx.h| 28 ++ > drivers/net/wireless/ti/wlcore/boot.c | 1 - > drivers/net/wireless/ti/wlcore/debugfs.c | 2 +- > drivers/net/wireless/ti/wlcore/main.c | 31 +++--- > drivers/net/wireless/ti/wlcore/sdio.c | 63 ++-- > drivers/net/wireless/ti/wlcore/spi.c | 6 +- > drivers/net/wireless/ti/wlcore/wlcore.h| 5 +- > drivers/net/wireless/ti/wlcore/wlcore_i.h | 6 +- > include/linux/wl12xx.h | 49 - > 25 files changed, 311 insertions(+), 312 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt > > -- > 1.8.5.2.229.g4448466.dirty > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] v4l: mt9v032: Add OF support
Hi Laurent,
On Wed, Mar 18, 2015 at 03:32:28PM +0200, Laurent Pinchart wrote:
...
> > > @@ -876,10 +879,59 @@ static const struct regmap_config
> > > mt9v032_regmap_config = {>
> > > * Driver initialization and probing
> > > */
> > >
> > > +static struct mt9v032_platform_data *
> > > +mt9v032_get_pdata(struct i2c_client *client)
> > > +{
> > > + struct mt9v032_platform_data *pdata;
> > > + struct v4l2_of_endpoint endpoint;
> > > + struct device_node *np;
> > > + struct property *prop;
> > > +
> > > + if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
> > > + return client->dev.platform_data;
> > > +
> > > + np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
> > > + if (!np)
> > > + return NULL;
> > > +
> > > + if (v4l2_of_parse_endpoint(np, &endpoint) < 0)
> > > + goto done;
> > > +
> > > + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
> > > + if (!pdata)
> > > + goto done;
> > > +
> > > + prop = of_find_property(np, "link-frequencies", NULL);
> > > + if (prop) {
> > > + size_t size = prop->length / 8;
> > > + u64 *link_freqs;
> > > +
> > > + link_freqs = devm_kzalloc(&client->dev,
> > > + size * sizeof(*link_freqs),
> >
> > You could simply use prop->length here. I think that'd look nicer.
>
> How about devm_kcalloc(&client->dev, size, sizeof(*link_freqs)) as this is
> allocating an array ?
That's certainly fine as well, I think. Feel free to divide prop->length by
sizeof(*link_freqs) instead of plain 8.
--
Sakari Ailus
e-mail: sakari.ai...@iki.fi XMPP: sai...@retiisi.org.uk
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[PATCH/RFC 1/5] clk: shmobile: rcar-gen2: Add CPG Clock Domain support
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG Clock Domain and can be
power-managed through their primary clock should be tagged in DT with a
proper "power-domains" property.
Signed-off-by: Geert Uytterhoeven
---
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 -
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-rcar-gen2.c | 63 ++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index b02944fba9de4f86..fc013f225a348929 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG Clock Domain and can be power-managed
+through their primary clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
+
+Examples
+
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e615 {
compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG Clock Domain member node:
+
+ thermal@e61f {
+ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0fb484221c90e0eb..048101a3253c52de 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
config PM_RCAR
bool
+ select PM_GENERIC_DOMAINS
config PM_RMOBILE
bool
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c
b/drivers/clk/shmobile/clk-rcar-gen2.c
index acfb6d7dbd6bc049..b54439d3722a13ad 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -18,6 +18,8 @@
#include
#include
#include
+#include
+#include
#include
struct rcar_gen2_cpg {
@@ -364,6 +366,65 @@ rcar_gen2_cpg_register_clock(struct device_node *np,
struct rcar_gen2_cpg *cpg,
4, 0, table, &cpg->lock);
}
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+static int cpg_pd_attach_dev(struct generic_pm_domain *domain,
+struct device *dev)
+{
+ int error;
+
+ error = pm_clk_create(dev);
+ if (error) {
+ dev_err(dev, "pm_clk_create failed %d\n", error);
+ return error;
+ }
+
+ error = pm_clk_add(dev, NULL);
+ if (error) {
+ dev_err(dev, "pm_clk_add failed %d\n", error);
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ pm_clk_destroy(dev);
+ return error;
+}
+
+static void cpg_pd_detach_dev(struct generic_pm_domain *domain,
+ struct device *dev)
+{
+ pm_clk_destroy(dev);
+}
+
+static void __init rcar_gen2_cpg_add_pm_domain(struct device_node *np)
+{
+ struct generic_pm_domain *pd;
+ u32 ncells;
+
+ if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+ pr_warn("%s lacks #power-domain-cells. Clocks may fail.\n",
+ np->full_name);
+ return;
+ }
+
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return;
+
+ pd->name = np->name;
+
+ pd->flags = GENPD_FLAG_PM_CLK;
+ pm_genpd_init(pd, &simple_qos_governor, false);
+ pd->attach_dev = cpg_pd_attach_dev;
+ pd->detach_dev = cpg_pd_detach_dev;
+
+ of_g
[PATCH/RFC 4/5] ARM: shmobile: r8a7794 dtsi: Add CPG Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG Clock Domain and can be power-managed through their
primary clock. This includes most present on-SoC devices.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 5667d284a3f0af92..2d0d5b20f98c16fa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -49,6 +49,7 @@
<0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
+ power-domains = <&cpg_clocks>;
};
cmt0: timer@ffca {
@@ -58,6 +59,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -77,6 +79,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -107,6 +110,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e670 {
@@ -135,6 +139,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -165,6 +170,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -175,6 +181,7 @@
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -184,6 +191,7 @@
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +201,7 @@
interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -202,6 +211,7 @@
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -211,6 +221,7 @@
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -220,6 +231,7 @@
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -229,6 +241,7 @@
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -238,6 +251,7 @@
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -247,6 +261,7 @@
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -256,6 +271,7 @@
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7794_CLK_SC
[PATCH/RFC 0/5] ARM: shmobile: rcar-gen2: Add CPG Clock Domain
Hi, This RFC patch series adds Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock are tagged in DT with a proper "power-domains" property. Drivers for devices with multiple clocks (notably du and rcar-sound) still have to manage their (multiple module) clocks themselves. Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c is disabled when running on an R-Car Gen2 SoC with genpd support. Compared to the legacy default PM domain hack, the CPG Clock Domain has several advantages: - It only affects on-SoC devices, not all platform devices, - It only affects the on-SoC devices we want, as specified in DT, - Allmost all module clocks of all on-SoC devices (barring devices needed for wake-up[*]) are now gated during s2ram, saving more power. Here's a list of all devices in the CPG Clock Domain on r8a7791: root@koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary domain status slaves /device runtime status -- cpg_clocks on /devices/platform/e61c.interrupt-controller active /devices/platform/e60b.i2c suspended /devices/platform/ffca.timersuspended /devices/platform/e605.gpio active /devices/platform/e6051000.gpio active /devices/platform/e6052000.gpio active /devices/platform/e6053000.gpio active /devices/platform/e6054000.gpio active /devices/platform/e6055000.gpio active /devices/platform/e6055400.gpio active /devices/platform/e6055800.gpio active /devices/platform/ee09.pci active /devices/platform/ee0d.pci active /devices/platform/fe00.pcie unsupported /devices/platform/e670.dma-controller active /devices/platform/e672.dma-controller active /devices/platform/ec70.dma-controller active /devices/platform/ec72.dma-controller suspended /devices/platform/e6e6.serial active /devices/platform/e6e68000.serial active /devices/platform/ee30.sata unsupported /devices/platform/e6b1.spi suspended /devices/platform/e6e2.spi suspended /devices/platform/ee70.ethernet active /devices/platform/e653.i2c suspended /devices/platform/e6ef1000.videosuspended /devices/platform/e61f.thermal active /devices/platform/ee10.sd active /devices/platform/ee14.sd active /devices/platform/ee16.sd active root@koelsch:~# Logically, the CPG Clock Domain operates on the SoC CPG/MSTP block. As there's no single device node in DT representing this block (there are separate device nodes for the CPG and for the individual MSTP clocks), I bound the logic to the CPG device node. Perhaps this is something we should change for future SoCs? As usual when involving clocks and/or PM Domains, the DTS changes depend stricly on the driver change. The final patch must be applied last. The DTS changes also depend on the series "[PATCH 0/5] ARM: shmobile: Add INTC-SYS clock to device tree" I've just sent. This was tested on r8a7791/koelsch. Thanks for your comments! [*] GPIO wake-up requires "[PATCH 0/3] gpio: rcar: Fix wake up using gpio-keys with PM domain"). Geert Uytterhoeven (5): [RFC] clk: shmobile: rcar-gen2: Add CPG Clock Domain support [RFC] ARM: shmobile: r8a7790 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7791 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7794 dtsi: Add CPG Clock Domain drivers: sh: Disable PM runtime for multi-platform R-Car Gen2 with genpd .../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++- arch/arm/boot/dts/r8a7790.dtsi | 77 +++-- arch/arm/boot/dts/r8a7791.dtsi | 80 -- arch/arm/boot/dts/r8a7794.dtsi | 29 arch/arm/mach-shmobile/Kconfig | 1 + drivers/clk/shmobile/clk-rcar-gen2.c | 63 + drivers/sh/pm_runtime.c| 10 +-- 7 files changed, 268 insertions(+), 18
[PATCH/RFC 2/5] ARM: shmobile: r8a7790 dtsi: Add CPG Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG Clock Domain and can be power-managed through their
primary clock. This includes most on-SoC devices. Notable exceptions
are:
- du, which references 3 or 5 clocks; I assume the driver manages all
of them itself?
- rcar_sound, which references lots of clock; idem?
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7790.dtsi | 77 ++
1 file changed, 71 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d4210f5b692a42b5..3c1f3b27dfdf506f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -123,6 +123,7 @@
<0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
+ power-domains = <&cpg_clocks>;
};
gpio0: gpio@e605 {
@@ -135,6 +136,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -147,6 +149,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -159,6 +162,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -171,6 +175,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -183,6 +188,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -195,6 +201,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f {
@@ -202,6 +209,7 @@
reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -219,6 +227,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -238,6 +247,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -254,6 +264,7 @@
<0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e670 {
@@ -282,6 +293,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -312,6 +324,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -340,6 +353,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -368,6 +382,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -379,6 +394,7 @@
reg = <0 0xe6508000 0 0x40>;
[PATCH/RFC 3/5] ARM: shmobile: r8a7791 dtsi: Add CPG Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG Clock Domain and can be power-managed through their
primary clock. This includes most on-SoC devices. Notable exceptions
are:
- du, which references 3 or 5 clocks; I assume the driver manages all
of them itself?
- rcar_sound, which references lots of clock; idem?
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7791.dtsi | 80 +++---
1 file changed, 75 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 9191acce98a6eeb2..cd11c6dd75021edb 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -80,6 +80,7 @@
<0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
+ power-domains = <&cpg_clocks>;
};
gpio0: gpio@e605 {
@@ -92,6 +93,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -104,6 +106,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -116,6 +119,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -128,6 +132,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -140,6 +145,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -152,6 +158,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
gpio6: gpio@e6055400 {
@@ -164,6 +171,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
+ power-domains = <&cpg_clocks>;
};
gpio7: gpio@e6055800 {
@@ -176,6 +184,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f {
@@ -183,6 +192,7 @@
reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -200,6 +210,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -219,6 +230,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -241,6 +253,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e670 {
@@ -269,6 +282,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -299,6 +313,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -327,6 +342,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
clock-names = "fck"
[PATCH/RFC 5/5] drivers: sh: Disable PM runtime for multi-platform R-Car Gen2 with genpd
Now we have an R-Car Gen2 CPG Clock Domain driver using the generic PM
domain to take care of PM runtime management of the module clocks, we no
longer need the legacy default PM domain hack, which also prevents
registering the real PM domain.
Hence do not enable it when running a multi-platform kernel with genpd
support on an R-Car Gen2 SoC.
The default PM domain is still needed:
- for platforms without genpd support,
- for the legacy (non-DT) case, where genpd may take over later,
- if genpd is not enabled.
Signed-off-by: Geert Uytterhoeven
---
drivers/sh/pm_runtime.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index fe8875f0d7be1155..97d5738f21ae8f04 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -83,15 +83,15 @@ static int __init sh_pm_runtime_init(void)
#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
!of_machine_is_compatible("renesas,r8a73a4") &&
!of_machine_is_compatible("renesas,r8a7740") &&
- !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
- !of_machine_is_compatible("renesas,r8a7778") &&
- !of_machine_is_compatible("renesas,r8a7779") &&
!of_machine_is_compatible("renesas,r8a7790") &&
!of_machine_is_compatible("renesas,r8a7791") &&
!of_machine_is_compatible("renesas,r8a7792") &&
!of_machine_is_compatible("renesas,r8a7793") &&
- !of_machine_is_compatible("renesas,r8a7794"))
+ !of_machine_is_compatible("renesas,r8a7794") &&
+ !of_machine_is_compatible("renesas,sh73a0") &&
+#endif
+ !of_machine_is_compatible("renesas,r8a7778") &&
+ !of_machine_is_compatible("renesas,r8a7779"))
return 0;
}
--
1.9.1
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Re: [PATCH] of_net: factor out repetitive code from of_get_mac_address()
On 18/03/15 12:25, Sergei Shtylyov wrote:
> of_get_mac_address() basically does the same thing thrice, every time with
> a
> different property name, so it makes sense to factor out the repetitive
> code
> into separate function. While at it, we can start using ETH_ALEN instead of
> the
> bare number and drop unnecessary parens around the property length check.
>
> The resulting ARM object file is 100 bytes less in size than before the patch.
>
> Signed-off-by: Sergei Shtylyov
Acked-by: Florian Fainelli
>
> ---
> The patch is against Grant Likely's 'linux.git' repo's 'devicetree/next'
> branch.
>
> drivers/of/of_net.c | 29 +
> 1 file changed, 17 insertions(+), 12 deletions(-)
>
> Index: linux/drivers/of/of_net.c
> ===
> --- linux.orig/drivers/of/of_net.c
> +++ linux/drivers/of/of_net.c
> @@ -38,6 +38,15 @@ int of_get_phy_mode(struct device_node *
> }
> EXPORT_SYMBOL_GPL(of_get_phy_mode);
>
> +static const void *of_get_mac_addr(struct device_node *np, const char *name)
> +{
> + struct property *pp = of_find_property(np, name, NULL);
> +
> + if (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value))
> + return pp->value;
> + return NULL;
> +}
> +
> /**
> * Search the device tree for the best MAC address to use. 'mac-address' is
> * checked first, because that is supposed to contain to "most recent" MAC
> @@ -58,20 +67,16 @@ EXPORT_SYMBOL_GPL(of_get_phy_mode);
> */
> const void *of_get_mac_address(struct device_node *np)
> {
> - struct property *pp;
> + const void *addr;
>
> - pp = of_find_property(np, "mac-address", NULL);
> - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
> - return pp->value;
> + addr = of_get_mac_addr(np, "mac-address");
> + if (addr)
> + return addr;
>
> - pp = of_find_property(np, "local-mac-address", NULL);
> - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
> - return pp->value;
> + addr = of_get_mac_addr(np, "local-mac-address");
> + if (addr)
> + return addr;
>
> - pp = of_find_property(np, "address", NULL);
> - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
> - return pp->value;
> -
> - return NULL;
> + return of_get_mac_addr(np, "address");
> }
> EXPORT_SYMBOL(of_get_mac_address);
>
--
Florian
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Re: [PATCH] dt-bindings: brcm: rationalize Broadcom documentation naming
On 03/18/2015 01:24 PM, Scott Branden wrote: This patchset attempts to standarize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Conceptually I'm fine with this. Acked-by: Stephen Warren The only comment I have is that some bindings refer to other bindings, e.g. an I2C controller binding might refer to the core I2C binding to define core I2C properties. Since this patch moves a couple files between directories, did you double-check that none of the pathnames in those references need fixing up? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] USB: ehci-atmel: rework clk handling
On 15-03-18 08:28 AM, Greg Kroah-Hartman wrote:
On Wed, Mar 18, 2015 at 12:16:22PM +0100, Nicolas Ferre wrote:
Le 17/03/2015 20:01, Alan Stern a écrit :
On Tue, 17 Mar 2015, Boris Brezillon wrote:
The EHCI IP only needs the UTMI/UPLL (uclk) and the peripheral (iclk)
clocks to work properly. Remove the useless system clock (fclk).
Avoid calling set_rate on the fixed rate UTMI/IPLL clock and remove
useless IS_ENABLED(CONFIG_COMMON_CLK) tests (all at91 platforms have been
moved to the CCF).
This patch also fixes a bug introduced by 3440ef1 (ARM: at91/dt: fix USB
high-speed clock to select UTMI), which was leaving the usb clock
uninitialized and preventing the OHCI driver from setting the usb clock
rate to 48MHz.
This bug was caused by several things:
1/ usb clock drivers set the CLK_SET_RATE_GATE flag, which means the rate
cannot be changed once the clock is prepared
2/ The EHCI driver was retrieving and preparing/enabling the uhpck
clock which was in turn preparing its parent clock (the usb clock),
thus preventing any rate change because of 1/
Signed-off-by: Boris Brezillon
Acked-by: Alan Stern
Acked-by: Nicolas Ferre
and:
Fixes: 3440ef169100 ("ARM: at91/dt: fix USB high-speed clock to select UTMI")
Alan, Greg,
Can you please take this patch (only this patch 1/5 of the series) as a fix
for the 4.0-rc? It would solve the issue that we see on at91sam9x5/at91sam9n12.
I'll take care of the rest of the series for 4.1.
If you want me to take it of to re-send the patch, tell me.
I'll queue it up now, thanks. You can take the rest of the series :)
Hi,
I reported this error to Nicolas based on tests with
lk 4.0-rc4. With the same USB WiFi dongle and platform
this patch fixes my problem.
Tested-by: Douglas Gilbert
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Re: [PATCH] of_net: factor out repetitive code from of_get_mac_address()
From: Sergei Shtylyov Date: Wed, 18 Mar 2015 22:25:46 +0300 > of_get_mac_address() basically does the same thing thrice, every time with > a > different property name, so it makes sense to factor out the repetitive > code > into separate function. While at it, we can start using ETH_ALEN instead of > the > bare number and drop unnecessary parens around the property length check. > > The resulting ARM object file is 100 bytes less in size than before the patch. > > Signed-off-by: Sergei Shtylyov > > --- > The patch is against Grant Likely's 'linux.git' repo's 'devicetree/next' > branch. Acked-by: David S. Miller -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] of_net: factor out repetitive code from of_get_mac_address()
of_get_mac_address() basically does the same thing thrice, every time with a
different property name, so it makes sense to factor out the repetitive code
into separate function. While at it, we can start using ETH_ALEN instead of the
bare number and drop unnecessary parens around the property length check.
The resulting ARM object file is 100 bytes less in size than before the patch.
Signed-off-by: Sergei Shtylyov
---
The patch is against Grant Likely's 'linux.git' repo's 'devicetree/next' branch.
drivers/of/of_net.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
Index: linux/drivers/of/of_net.c
===
--- linux.orig/drivers/of/of_net.c
+++ linux/drivers/of/of_net.c
@@ -38,6 +38,15 @@ int of_get_phy_mode(struct device_node *
}
EXPORT_SYMBOL_GPL(of_get_phy_mode);
+static const void *of_get_mac_addr(struct device_node *np, const char *name)
+{
+ struct property *pp = of_find_property(np, name, NULL);
+
+ if (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value))
+ return pp->value;
+ return NULL;
+}
+
/**
* Search the device tree for the best MAC address to use. 'mac-address' is
* checked first, because that is supposed to contain to "most recent" MAC
@@ -58,20 +67,16 @@ EXPORT_SYMBOL_GPL(of_get_phy_mode);
*/
const void *of_get_mac_address(struct device_node *np)
{
- struct property *pp;
+ const void *addr;
- pp = of_find_property(np, "mac-address", NULL);
- if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
- return pp->value;
+ addr = of_get_mac_addr(np, "mac-address");
+ if (addr)
+ return addr;
- pp = of_find_property(np, "local-mac-address", NULL);
- if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
- return pp->value;
+ addr = of_get_mac_addr(np, "local-mac-address");
+ if (addr)
+ return addr;
- pp = of_find_property(np, "address", NULL);
- if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
- return pp->value;
-
- return NULL;
+ return of_get_mac_addr(np, "address");
}
EXPORT_SYMBOL(of_get_mac_address);
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[PATCH] dt-bindings: brcm: rationalize Broadcom documentation naming
This patchset attempts to standarize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the dt-bindings document the "vendor,binding.txt" style is in use by
some of the other vendors.
---
.../arm/bcm/{brcm,bcm11351-cpu-method => brcm,bcm11351-cpu-method.txt}| 0
.../devicetree/bindings/arm/bcm/{bcm11351.txt => brcm,bcm11351.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm21664.txt => brcm,bcm21664.txt} | 0
.../devicetree/bindings/arm/{bcm2835.txt => bcm/brcm,bcm2835.txt} | 0
.../devicetree/bindings/arm/{bcm4708.txt => bcm/brcm,bcm4708.txt} | 0
.../devicetree/bindings/arm/bcm/{bcm63138.txt => brcm,bcm63138.txt} | 0
.../devicetree/bindings/arm/{brcm-brcmstb.txt => bcm/brcm,brcmstb.txt}| 0
Documentation/devicetree/bindings/arm/bcm/{cygnus.txt => brcm,cygnus.txt} | 0
Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt} | 0
.../devicetree/bindings/clock/{bcm-kona-clock.txt => brcm,kona-ccu.txt} | 0
.../devicetree/bindings/dma/{bcm2835-dma.txt => brcm,bcm2835-dma.txt} | 0
Documentation/devicetree/bindings/mfd/{bcm590xx.txt => brcm,bcm59056.txt} | 0
.../bindings/mips/brcm/{bcm3384-intc.txt => brcm,bcm3384-intc.txt}| 0
Documentation/devicetree/bindings/mips/brcm/{bmips.txt => brcm,bmips.txt} | 0
.../devicetree/bindings/mips/brcm/{cm-dsl.txt => brcm,cm-dsl.txt} | 0
.../bindings/net/{broadcom-sf2.txt => brcm,bcm7445-switch-v4.0.txt} | 0
.../devicetree/bindings/net/{broadcom-bcmgenet.txt => brcm,bcmgenet.txt} | 0
.../bindings/net/{broadcom-systemport.txt => brcm,systemport.txt} | 0
.../bindings/net/{broadcom-mdio-unimac.txt => brcm,unimac-mdio.txt} | 0
.../devicetree/bindings/phy/{bcm-phy.txt => brcm,kona-usb2-phy.txt} | 0
.../devicetree/bindings/pwm/{bcm-kona-pwm.txt => brcm,kona-pwm.txt} | 0
.../{arm/bcm/kona-resetmgr.txt => reset/brcm,bcm21664-resetmgr.txt} | 0
.../bindings/serial/{bcm63xx-uart.txt => brcm,bcm6345-uart.txt} | 0
.../devicetree/bindings/sound/{bcm2835-i2s.txt => brcm,bcm2835-i2s.txt} | 0
.../bindings/{arm/bcm/kona-timer.txt => timer/brcm,kona-timer.txt}| 0
.../devicetree/bindings/{mips/brcm/usb.txt => usb/brcm,bcm3384-usb.txt} | 0
.../bindings/{arm/bcm/kona-wdt.txt => watchdog/brcm,kona-wdt.txt} | 0
27 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/bcm/{brcm,bcm11351-cpu-method =>
brcm,bcm11351-cpu-method.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm11351.txt =>
brcm,bcm11351.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm21664.txt =>
brcm,bcm21664.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm2835.txt =>
bcm/brcm,bcm2835.txt} (100%)
rename Documentation/devicetree/bindings/arm/{bcm4708.txt =>
bcm/brcm,bcm4708.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{bcm63138.txt =>
brcm,bcm63138.txt} (100%)
rename Documentation/devicetree/bindings/arm/{brcm-brcmstb.txt =>
bcm/brcm,brcmstb.txt} (100%)
rename Documentation/devicetree/bindings/arm/bcm/{cygnus.txt =>
brcm,cygnus.txt} (100%)
rename Documentation/devicetree/bindings/bus/{bcma.txt => brcm,bus-axi.txt}
(100%)
rename Documentation/devicetree/bindings/clock/{bcm-kona-clock.txt =>
brcm,kona-ccu.txt} (100%)
rename Documentation/devicetree/bindings/dma/{bcm2835-dma.txt =>
brcm,bcm2835-dma.txt} (100%)
rename Documentation/devicetree/bindings/mfd/{bcm590xx.txt =>
brcm,bcm59056.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bcm3384-intc.txt =>
brcm,bcm3384-intc.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{bmips.txt =>
brcm,bmips.txt} (100%)
rename Documentation/devicetree/bindings/mips/brcm/{cm-dsl.txt =>
brcm,cm-dsl.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-sf2.txt =>
brcm,bcm7445-switch-v4.0.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-bcmgenet.txt =>
brcm,bcmgenet.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-systemport.txt =>
brcm,systemport.txt} (100%)
rename Documentation/devicetree/bindings/net/{broadcom-mdio-unimac.txt =>
brcm,unimac-mdio.txt} (100%)
rename Documentation/devicetree/bindings/phy/{bcm-phy.txt =>
brcm,kona-usb2-phy.txt} (100%)
rename Documentation/devicetree/bindings/pwm/{bcm-kona-pwm.txt =>
brcm,kona-pwm.txt} (100%)
rename Documentation/devicetree/bindings/{arm/bcm/kona-resetmgr.txt =>
reset/brcm,bcm21664-resetmgr.txt} (100%)
rename Documentation/devicetree/bindings/serial/{bcm63xx-uart.txt =>
brcm,bcm6345-uart.txt} (100%)
rename Documentation/devicetree/bindings/sound/{bcm2835-i2s.txt =>
brcm,bcm2835-i2s.txt} (100%)
rename Documentation/devicetree/bindings/{arm/bcm/kona-timer.txt =>
timer/brcm,kona-timer.txt} (100%)
rename Documentation/devicetree/bindings/{mips/brcm/usb.txt =>
usb/brcm,bcm3384-usb.t
[PATCH 0/7] ARM: shmobile: Add IRQC clock to device tree
Hi,
This patch series adds the IRQC clock to the device tree on SoCs that
have such a clock (r8a73a4 and r8a779x), and adds mininal runtime PM
support to the renesas-irqc driver, to make sure the clock is enabled
when needed by the external IRQ controller(s).
Before, the clock was assumed enabled by the bootloader or reset state.
As usual when involving clocks, the DTS changes depend stricly on the
driver changes. Else the clock will be disabled as assumed unused,
breaking the boot.
This was tested on r8a73a4/ape6evm and r8a7791/koelsch.
Thanks!
Geert Uytterhoeven (7):
irqchip: renesas-irqc: Add more register documentation
irqchip: renesas-irqc: Add minimal runtime PM support
irqchip: renesas-irqc: Add functional clock to bindings
ARM: shmobile: r8a7734: Add IRQC clock to device tree
ARM: shmobile: r8a7790: Add IRQC clock to device tree
ARM: shmobile: r8a7791: Add IRQC clock to device tree
ARM: shmobile: r8a7794: Add IRQC clock to device tree
.../bindings/interrupt-controller/renesas,irqc.txt | 4 +++-
arch/arm/boot/dts/r8a73a4.dtsi | 11 +
arch/arm/boot/dts/r8a7790.dtsi | 9 +++
arch/arm/boot/dts/r8a7791.dtsi | 9 +++
arch/arm/boot/dts/r8a7794.dtsi | 9 +++
drivers/irqchip/irq-renesas-irqc.c | 28 ++
include/dt-bindings/clock/r8a73a4-clock.h | 1 +
include/dt-bindings/clock/r8a7790-clock.h | 3 +++
include/dt-bindings/clock/r8a7791-clock.h | 3 +++
include/dt-bindings/clock/r8a7794-clock.h | 3 +++
10 files changed, 70 insertions(+), 10 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH 6/7] ARM: shmobile: r8a7791: Add IRQC clock to device tree
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7791.dtsi| 9 +
include/dt-bindings/clock/r8a7791-clock.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 4696062f6ddeaaeb..20ab7668088493b9 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -239,6 +239,7 @@
<0 15 IRQ_TYPE_LEVEL_HIGH>,
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
};
dmac0: dma-controller@e670 {
@@ -1160,6 +1161,14 @@
"mmcif0", "i2c7", "pciec", "i2c8", "ssusb",
"cmt1",
"usbdmac0", "usbdmac1";
};
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7791-mstp-clocks",
"renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>;
+ #clock-cells = <1>;
+ clock-indices = ;
+ clock-output-names = "irqc";
+ };
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7791-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
diff --git a/include/dt-bindings/clock/r8a7791-clock.h
b/include/dt-bindings/clock/r8a7791-clock.h
index 8fc5dc8faeea4051..402268384b99093c 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -70,6 +70,9 @@
#define R8A7791_CLK_USBDMAC0 30
#define R8A7791_CLK_USBDMAC1 31
+/* MSTP4 */
+#define R8A7791_CLK_IRQC 7
+
/* MSTP5 */
#define R8A7791_CLK_AUDIO_DMAC11
#define R8A7791_CLK_AUDIO_DMAC02
--
1.9.1
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[PATCH 4/7] ARM: shmobile: r8a7734: Add IRQC clock to device tree
Link the external IRQ controllers irqc0 and irqc1 to the IRQC module
clock, so they can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a73a4.dtsi| 11 +++
include/dt-bindings/clock/r8a73a4-clock.h | 1 +
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 0fd889f88109de17..7ee22a41c6c97488 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -163,6 +163,7 @@
<0 29 IRQ_TYPE_LEVEL_HIGH>,
<0 30 IRQ_TYPE_LEVEL_HIGH>,
<0 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>;
};
@@ -197,6 +198,7 @@
<0 55 IRQ_TYPE_LEVEL_HIGH>,
<0 56 IRQ_TYPE_LEVEL_HIGH>,
<0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>;
};
@@ -724,15 +726,16 @@
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a73a4-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
- clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
+ clocks = <&main_div2_clk>, <&main_div2_clk>,
+<&cpg_clocks R8A73A4_CLK_HP>,
<&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
- R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
- R8A73A4_CLK_IIC3
+ R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
+ R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
>;
clock-output-names =
- "iic5", "iic4", "iic3";
+ "irqc", "iic5", "iic4", "iic3";
};
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a73a4-mstp-clocks",
"renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r8a73a4-clock.h
b/include/dt-bindings/clock/r8a73a4-clock.h
index 9a4b4c9ca44aba70..dd11ecdf837e8e65 100644
--- a/include/dt-bindings/clock/r8a73a4-clock.h
+++ b/include/dt-bindings/clock/r8a73a4-clock.h
@@ -54,6 +54,7 @@
#define R8A73A4_CLK_IIC3 11
#define R8A73A4_CLK_IIC4 10
#define R8A73A4_CLK_IIC5 9
+#define R8A73A4_CLK_IRQC 7
/* MSTP5 */
#define R8A73A4_CLK_THERMAL22
--
1.9.1
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[PATCH 5/7] ARM: shmobile: r8a7790: Add IRQC clock to device tree
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7790.dtsi| 9 +
include/dt-bindings/clock/r8a7790-clock.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4bb2f4c17321bd55..a81cfda0872fc30a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -252,6 +252,7 @@
<0 1 IRQ_TYPE_LEVEL_HIGH>,
<0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
};
dmac0: dma-controller@e670 {
@@ -1158,6 +1159,14 @@
"iic0", "pciec", "iic1", "ssusb", "cmt1",
"usbdmac0", "usbdmac1";
};
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7790-mstp-clocks",
"renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>;
+ #clock-cells = <1>;
+ clock-indices = ;
+ clock-output-names = "irqc";
+ };
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7790-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
diff --git a/include/dt-bindings/clock/r8a7790-clock.h
b/include/dt-bindings/clock/r8a7790-clock.h
index 3f2c6b198d4ac289..ff7ca3584e169589 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -79,6 +79,9 @@
#define R8A7790_CLK_USBDMAC0 30
#define R8A7790_CLK_USBDMAC1 31
+/* MSTP4 */
+#define R8A7790_CLK_IRQC 7
+
/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC11
#define R8A7790_CLK_AUDIO_DMAC02
--
1.9.1
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[PATCH 2/7] irqchip: renesas-irqc: Add minimal runtime PM support
This is just enough to let pm_clk_*() enable the functional clock, and
manage it for suspend/resume, if present.
Before, it was assumed enabled by the bootloader or reset state.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/irqchip/irq-renesas-irqc.c
b/drivers/irqchip/irq-renesas-irqc.c
index 2ce2edf8ec8ec182..718f01cd1aea19f6 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
@@ -180,6 +181,9 @@ static int irqc_probe(struct platform_device *pdev)
p->pdev = pdev;
platform_set_drvdata(pdev, p);
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
/* get hold of manadatory IOMEM */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!io) {
@@ -260,6 +264,8 @@ err3:
err2:
iounmap(p->iomem);
err1:
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
kfree(p);
err0:
return ret;
@@ -275,6 +281,8 @@ static int irqc_remove(struct platform_device *pdev)
irq_domain_remove(p->irq_domain);
iounmap(p->iomem);
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
kfree(p);
return 0;
}
--
1.9.1
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[PATCH 7/7] ARM: shmobile: r8a7794: Add IRQC clock to device tree
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi| 9 +
include/dt-bindings/clock/r8a7794-clock.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 7a3ffa51a8bf2c8b..01cf54f70501e8c2 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -105,6 +105,7 @@
<0 15 IRQ_TYPE_LEVEL_HIGH>,
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
};
dmac0: dma-controller@e670 {
@@ -625,6 +626,14 @@
"sdhi2", "sdhi1", "sdhi0",
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
};
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7794-mstp-clocks",
"renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>;
+ #clock-cells = <1>;
+ clock-indices = ;
+ clock-output-names = "irqc";
+ };
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7794-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
diff --git a/include/dt-bindings/clock/r8a7794-clock.h
b/include/dt-bindings/clock/r8a7794-clock.h
index d63323032d6ef80e..09da38a58776b403 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -60,6 +60,9 @@
#define R8A7794_CLK_USBDMAC0 30
#define R8A7794_CLK_USBDMAC1 31
+/* MSTP4 */
+#define R8A7794_CLK_IRQC 7
+
/* MSTP5 */
#define R8A7794_CLK_THERMAL22
#define R8A7794_CLK_PWM23
--
1.9.1
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[PATCH 1/7] irqchip: renesas-irqc: Add more register documentation
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-irqc.c
b/drivers/irqchip/irq-renesas-irqc.c
index 2ea3412fdf8cc668..2ce2edf8ec8ec182 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -30,14 +30,24 @@
#include
#include
-#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
+#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
-#define IRQC_REQ_STS 0x00
-#define IRQC_EN_STS 0x04
-#define IRQC_EN_SET 0x08
+#define IRQC_REQ_STS 0x00/* Interrupt Request Status Register */
+#define IRQC_EN_STS0x04/* Interrupt Enable Status Register */
+#define IRQC_EN_SET0x08/* Interrupt Enable Set Register */
#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
-#define DETECT_STATUS 0x100
+ /* SYS-CPU vs. RT-CPU */
+#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
+#define MONITOR0x104 /* IRQn Signal Level Monitor Register */
+#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
+#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
+#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
+#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
+#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
+#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
+#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
+ /* IRQn Configuration Register */
struct irqc_irq {
int hw_irq;
--
1.9.1
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[PATCH 3/7] irqchip: renesas-irqc: Add functional clock to bindings
The external IRQ controller has a functional clock, which is used for power management. Document it. Fix a typo in the r8a73a4 SoC name while we're at it. Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/interrupt-controller/renesas,irqc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt index 1a88e62228e59631..4f85aeb658e4c833 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt @@ -4,7 +4,7 @@ Required properties: - compatible: has to be "renesas,irqc-", "renesas,irqc" as fallback. Examples with soctypes are: -- "renesas,irqc-r8a73a4" (R-Mobile AP6) +- "renesas,irqc-r8a73a4" (R-Mobile APE6) - "renesas,irqc-r8a7790" (R-Car H2) - "renesas,irqc-r8a7791" (R-Car M2-W) - "renesas,irqc-r8a7792" (R-Car V2H) @@ -12,6 +12,7 @@ Required properties: - "renesas,irqc-r8a7794" (R-Car E2) - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in interrupts.txt in this directory +- clocks: Must contain a reference to the functional clock. Optional properties: @@ -29,4 +30,5 @@ Example: <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7790_CLK_IRQC>; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 6/8] ARM: cpuidle: Enable the ARM64 driver for both ARM32/ARM64
ARM32 and ARM64 have the same DT definitions and the same approaches.
The generic ARM cpuidle driver can be put in common for those two
architectures.
Signed-off-by: Daniel Lezcano
Acked-by: Kevin Hilman
Acked-by: Rob Herring
---
drivers/cpuidle/Kconfig| 7 +--
drivers/cpuidle/Kconfig.arm| 10 ++
drivers/cpuidle/Kconfig.arm64 | 13 -
drivers/cpuidle/Makefile | 5 +
drivers/cpuidle/{cpuidle-arm64.c => cpuidle-arm.c} | 0
5 files changed, 12 insertions(+), 23 deletions(-)
delete mode 100644 drivers/cpuidle/Kconfig.arm64
rename drivers/cpuidle/{cpuidle-arm64.c => cpuidle-arm.c} (100%)
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index c5029c1..8c7930b 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -29,15 +29,10 @@ config DT_IDLE_STATES
bool
menu "ARM CPU Idle Drivers"
-depends on ARM
+depends on ARM || ARM64
source "drivers/cpuidle/Kconfig.arm"
endmenu
-menu "ARM64 CPU Idle Drivers"
-depends on ARM64
-source "drivers/cpuidle/Kconfig.arm64"
-endmenu
-
menu "MIPS CPU Idle Drivers"
depends on MIPS
source "drivers/cpuidle/Kconfig.mips"
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 8e07c94..f08043e 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -14,6 +14,16 @@ config ARM_BIG_LITTLE_CPUIDLE
define different C-states for little and big cores through the
multiple CPU idle drivers infrastructure.
+config ARM_CPUIDLE
+ bool "Generic ARM/ARM64 CPU idle Driver"
+ select DT_IDLE_STATES
+ help
+ Select this to enable generic cpuidle driver for ARM.
+ It provides a generic idle driver whose idle states are configured
+ at run-time through DT nodes. The CPUidle suspend backend is
+ initialized by calling the CPU operations init idle hook
+ provided by architecture code.
+
config ARM_CLPS711X_CPUIDLE
bool "CPU Idle Driver for CLPS711X processors"
depends on ARCH_CLPS711X || COMPILE_TEST
diff --git a/drivers/cpuidle/Kconfig.arm64 b/drivers/cpuidle/Kconfig.arm64
deleted file mode 100644
index 6effb36..000
--- a/drivers/cpuidle/Kconfig.arm64
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# ARM64 CPU Idle drivers
-#
-
-config ARM64_CPUIDLE
- bool "Generic ARM64 CPU idle Driver"
- select DT_IDLE_STATES
- help
- Select this to enable generic cpuidle driver for ARM64.
- It provides a generic idle driver whose idle states are configured
- at run-time through DT nodes. The CPUidle suspend backend is
- initialized by calling the CPU operations init idle hook
- provided by architecture code.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 4d177b9..3ba81b1 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -17,16 +17,13 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) +=
cpuidle-zynq.o
obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o
obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+= cpuidle-exynos.o
+obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o
###
# MIPS drivers
obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
###
-# ARM64 drivers
-obj-$(CONFIG_ARM64_CPUIDLE)+= cpuidle-arm64.o
-
-###
# POWERPC drivers
obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm.c
similarity index 100%
rename from drivers/cpuidle/cpuidle-arm64.c
rename to drivers/cpuidle/cpuidle-arm.c
--
1.9.1
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[PATCH V2 4/8] ARM64: cpuidle: Rename cpu_init_idle to a common function name
With this change the cpuidle-arm64.c file calls the same function name
for both ARM and ARM64.
Signed-off-by: Daniel Lezcano
Acked-by: Kevin Hilman
Acked-by: Rob Herring
---
arch/arm64/include/asm/cpuidle.h | 4 ++--
arch/arm64/kernel/cpuidle.c | 2 +-
drivers/cpuidle/cpuidle-arm64.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
index 460a38b..141b2fc 100644
--- a/arch/arm64/include/asm/cpuidle.h
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -4,10 +4,10 @@
#include
#ifdef CONFIG_CPU_IDLE
-extern int cpu_init_idle(unsigned int cpu);
+extern int arm_cpuidle_init(unsigned int cpu);
extern int cpu_suspend(unsigned long arg);
#else
-static inline int cpu_init_idle(unsigned int cpu)
+static inline int arm_cpuidle_init(unsigned int cpu)
{
return -EOPNOTSUPP;
}
diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
index 5c08966..a78143a 100644
--- a/arch/arm64/kernel/cpuidle.c
+++ b/arch/arm64/kernel/cpuidle.c
@@ -15,7 +15,7 @@
#include
#include
-int cpu_init_idle(unsigned int cpu)
+int arm_cpuidle_init(unsigned int cpu)
{
int ret = -EOPNOTSUPP;
struct device_node *cpu_node = of_cpu_device_node_get(cpu);
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
index 0cea244..6ef291c7 100644
--- a/drivers/cpuidle/cpuidle-arm64.c
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -110,7 +110,7 @@ static int __init arm64_idle_init(void)
* idle states suspend back-end specific data
*/
for_each_possible_cpu(cpu) {
- ret = cpu_init_idle(cpu);
+ ret = arm_cpuidle_init(cpu);
if (ret) {
pr_err("CPU %d failed to init idle CPU ops\n", cpu);
return ret;
--
1.9.1
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[PATCH V2 0/8] ARM: cpuidle: Unify the ARM64/ARM DT approach
There is a big number of cpuidle drivers for the ARM architecture.
These drivers have been cleaned up and grouped into the drivers/cpuidle
directory to keep track of the changes more easily and ensure the code
is following the same scheme across the drivers.
That had the benefit of simplifying the code and factor out a lot of common
parts. Beside that, as the drivers belong to the 'drivers' directory, we had
to split the arch specific bits and the generic code in order to keep
everything self contained. The platform driver paradigm was used for this
purpose.
Unfortunately, this approach is now no longer accepted and a different solution
must be provided to reach the same goal: one example is the Qualcomm cpuidle
driver upstreaming attempt.
In the meantime, ARM64 developed a generic cpuidle driver based on DT
definition.
The DT definition provides an 'enable-method' to specify one of the cpu
operations (PSCI, ...).
This patchset unify this driver with ARM32, using the same DT definition.
Thanks with this patchset we can use the 'enable-method' to specify a cpu
operations, hence get rid of the platform driver approach and go further in the
cpuidle driver flexibility via the DT.
Changelog:
V2:
* Fixed some nits in the comments
* Added a patch to change the name of the functions
* Added per cpu device registration patch
Daniel Lezcano (8):
ARM: cpuidle: Remove duplicate header inclusion
ARM: cpuidle: Add a cpuidle ops structure to be used for DT
ARM64: cpuidle: Replace cpu_suspend by the common ARM/ARM64 function
ARM64: cpuidle: Rename cpu_init_idle to a common function name
ARM64: cpuidle: Remove arm64 reference
ARM: cpuidle: Enable the ARM64 driver for both ARM32/ARM64
ARM: cpuidle: Register per cpuidle device
ARM: cpuidle: Change function name to be consistent with x86
arch/arm/include/asm/cpuidle.h | 21 ++
arch/arm/kernel/cpuidle.c | 74 ++-
arch/arm/mach-davinci/cpuidle.c| 1 -
arch/arm/mach-imx/cpuidle-imx6q.c | 1 -
arch/arm/mach-imx/cpuidle-imx6sl.c | 1 -
arch/arm/mach-imx/cpuidle-imx6sx.c | 1 -
arch/arm/mach-omap2/cpuidle44xx.c | 1 -
arch/arm/mach-s3c64xx/cpuidle.c| 2 +-
arch/arm/mach-tegra/cpuidle-tegra20.c | 1 -
arch/arm/mach-tegra/cpuidle-tegra30.c | 1 -
arch/arm64/include/asm/cpuidle.h | 9 ++-
arch/arm64/kernel/cpuidle.c| 2 +-
drivers/cpuidle/Kconfig| 7 +-
drivers/cpuidle/Kconfig.arm| 10 +++
drivers/cpuidle/Kconfig.arm64 | 13
drivers/cpuidle/Makefile | 5 +-
drivers/cpuidle/{cpuidle-arm64.c => cpuidle-arm.c} | 83 --
drivers/cpuidle/cpuidle-at91.c | 1 -
drivers/cpuidle/cpuidle-exynos.c | 1 -
drivers/cpuidle/cpuidle-kirkwood.c | 1 -
drivers/cpuidle/cpuidle-ux500.c| 1 -
drivers/cpuidle/cpuidle-zynq.c | 1 -
include/asm-generic/vmlinux.lds.h | 2 +
23 files changed, 178 insertions(+), 62 deletions(-)
delete mode 100644 drivers/cpuidle/Kconfig.arm64
rename drivers/cpuidle/{cpuidle-arm64.c => cpuidle-arm.c} (56%)
--
1.9.1
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[PATCH V2 3/8] ARM64: cpuidle: Replace cpu_suspend by the common ARM/ARM64 function
Call the common ARM/ARM64 'arm_cpuidle_suspend' instead of cpu_suspend function which is specific to ARM64. Signed-off-by: Daniel Lezcano Acked-by: Kevin Hilman Acked-by: Rob Herring --- drivers/cpuidle/cpuidle-arm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c index 39a2c62..0cea244 100644 --- a/drivers/cpuidle/cpuidle-arm64.c +++ b/drivers/cpuidle/cpuidle-arm64.c @@ -49,7 +49,7 @@ static int arm64_enter_idle_state(struct cpuidle_device *dev, * call the CPU ops suspend protocol with idle index as a * parameter. */ - ret = cpu_suspend(idx); + arm_cpuidle_suspend(idx); cpu_pm_exit(); } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 7/8] ARM: cpuidle: Register per cpuidle device
Some architectures have some cpus which does not support idle states.
Let the underlying low level code to return -ENOSYS when it is not
possible to set an idle state.
Signed-off-by: Daniel Lezcano
---
drivers/cpuidle/cpuidle-arm.c | 45 +--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
index 1c94b88..0682ed0 100644
--- a/drivers/cpuidle/cpuidle-arm.c
+++ b/drivers/cpuidle/cpuidle-arm.c
@@ -17,11 +17,14 @@
#include
#include
#include
+#include
#include
#include "dt_idle_states.h"
+static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
+
/*
* arm_enter_idle_state - Programs CPU to enter the specified state
*
@@ -94,6 +97,7 @@ static int __init arm_idle_init(void)
{
int cpu, ret;
struct cpuidle_driver *drv = &arm_idle_driver;
+ struct cpuidle_device *dev;
/*
* Initialize idle states data, starting at index 1.
@@ -105,18 +109,55 @@ static int __init arm_idle_init(void)
if (ret <= 0)
return ret ? : -ENODEV;
+ ret = cpuidle_register_driver(drv);
+ if (ret) {
+ pr_err("Failed to register cpuidle driver\n");
+ return ret;
+ }
+
/*
* Call arch CPU operations in order to initialize
* idle states suspend back-end specific data
*/
for_each_possible_cpu(cpu) {
ret = arm_cpuidle_init(cpu);
+
+ /* This cpu does not support any idle states */
+ if (ret == -ENOSYS)
+ continue;
+
if (ret) {
pr_err("CPU %d failed to init idle CPU ops\n", cpu);
- return ret;
+ goto out_fail;
+ }
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev) {
+ pr_err("Failed to allocate cpuidle device\n");
+ goto out_fail;
+ }
+
+ dev->cpu = cpu;
+ per_cpu(cpuidle_arm_dev, cpu) = dev;
+
+ ret = cpuidle_register_device(dev);
+ if (ret) {
+ pr_err("Failed to register cpuidle device for CPU %d\n",
+ cpu);
+ kfree(dev);
+ goto out_fail;
}
}
+out:
+ return ret;
- return cpuidle_register(drv, NULL);
+out_fail:
+ for (cpu--; cpu <= 0; cpu--) {
+ dev = per_cpu(cpuidle_arm_dev, cpu);
+ cpuidle_unregister_device(dev);
+ kfree(dev);
+ }
+ cpuidle_unregister_driver(drv);
+ goto out;
}
device_initcall(arm_idle_init);
--
1.9.1
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[PATCH V2 1/8] ARM: cpuidle: Remove duplicate header inclusion
The cpu_do_idle() function is always used by the cpuidle drivers. That led to have each driver including cpuidle.h and proc-fns.h, they are always paired. That makes a lot of duplicate headers inclusion. Instead of including both in each .c file, move the proc-fns.h header inclusion in the cpuidle.h header file directly, so we can save some line of code. Signed-off-by: Daniel Lezcano Acked-by: Kevin Hilman Acked-by: Lorenzo Pieralisi --- arch/arm/include/asm/cpuidle.h| 2 ++ arch/arm/kernel/cpuidle.c | 2 +- arch/arm/mach-davinci/cpuidle.c | 1 - arch/arm/mach-imx/cpuidle-imx6q.c | 1 - arch/arm/mach-imx/cpuidle-imx6sl.c| 1 - arch/arm/mach-imx/cpuidle-imx6sx.c| 1 - arch/arm/mach-omap2/cpuidle44xx.c | 1 - arch/arm/mach-s3c64xx/cpuidle.c | 2 +- arch/arm/mach-tegra/cpuidle-tegra20.c | 1 - arch/arm/mach-tegra/cpuidle-tegra30.c | 1 - drivers/cpuidle/cpuidle-at91.c| 1 - drivers/cpuidle/cpuidle-exynos.c | 1 - drivers/cpuidle/cpuidle-kirkwood.c| 1 - drivers/cpuidle/cpuidle-ux500.c | 1 - drivers/cpuidle/cpuidle-zynq.c| 1 - 15 files changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h index af319ac..348dc81 100644 --- a/arch/arm/include/asm/cpuidle.h +++ b/arch/arm/include/asm/cpuidle.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_CPUIDLE_H #define __ASM_ARM_CPUIDLE_H +#include + #ifdef CONFIG_CPU_IDLE extern int arm_cpuidle_simple_enter(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c index 89545f6..45969f8 100644 --- a/arch/arm/kernel/cpuidle.c +++ b/arch/arm/kernel/cpuidle.c @@ -10,7 +10,7 @@ */ #include -#include +#include int arm_cpuidle_simple_enter(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index e365c1b..306ebc5 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index d76d086..8e21ccc 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "common.h" #include "cpuidle.h" diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index 7d92e65..5742a9f 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "common.h" #include "cpuidle.h" diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 5a36722..2c9f1a8 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include "common.h" diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index 01e398a..7622dbb 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -17,7 +17,6 @@ #include #include -#include #include "common.h" #include "pm.h" diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c index 2eb0724..93aa8cb 100644 --- a/arch/arm/mach-s3c64xx/cpuidle.c +++ b/arch/arm/mach-s3c64xx/cpuidle.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 4f25a7c..e22b0d9 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -27,7 +27,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index f8815ed..a2400ab4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -27,7 +27,6 @@ #include #include -#include #include #include diff --git a/drivers/cpuidle/cpuidle-at91.c b/drivers/cpuidle/cpuidle-at91.c index aae7bfc..f2446c7 100644 --- a/drivers/cpuidle/cpuidle-at91.c +++ b/drivers/cpuidle/cpuidle-at91.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #define AT91_MAX_STATES2 diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c index 26f5f29..0c06ea2 100644 --- a/drivers/cpuidle/cpuidle-exynos.c +++ b/drivers/cpuidle/cpuidle-exynos.c @@ -19,7 +19,6 @@ #include #include -#include #include #include diff --git a/drivers/cpuidle/cpuidle-kirkwood.c b/drivers/cpuidle/cpuidle-kirkwood.c index cea0a6c..d23d8f4 100644 --- a/drivers/cpuidle/cpuidle-kirkwood.c +++ b/drivers/cpuidle/cpuidle-kirkwood.c @@ -21,7 +21,6 @@ #inclu
[PATCH V2 2/8] ARM: cpuidle: Add a cpuidle ops structure to be used for DT
The current state of the different cpuidle drivers is the different PM
operations are passed via the platform_data using the platform driver
paradigm.
This approach allowed to split the low level PM code from the arch specific
and the generic cpuidle code.
Unfortunately there are complaints about this approach as, in the context of the
single kernel image, we have multiple drivers loaded in memory for nothing and
the platform driver is not adequate for cpuidle.
This patch provides a common interface via cpuidle ops for all new cpuidle
driver and a definition for the device tree.
It will allow with the next patches to a have a common definition with ARM64
and share the same cpuidle driver.
The code is optimized to use the __init section intensively in order to reduce
the memory footprint after the driver is initialized and unify the function
names with ARM64.
Signed-off-by: Daniel Lezcano
Acked-by: Kevin Hilman
Acked-by: Rob Herring
---
arch/arm/include/asm/cpuidle.h| 19 +++
arch/arm/kernel/cpuidle.c | 72 +++
arch/arm64/include/asm/cpuidle.h | 5 ++-
include/asm-generic/vmlinux.lds.h | 2 ++
4 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 348dc81..1851e9d 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -27,4 +27,23 @@ static inline int arm_cpuidle_simple_enter(struct
cpuidle_device *dev,
*/
#define ARM_CPUIDLE_WFI_STATE ARM_CPUIDLE_WFI_STATE_PWR(UINT_MAX)
+struct cpuidle_ops {
+ int (*suspend)(int cpu, unsigned long arg);
+ int (*init)(struct device_node *, int cpu);
+};
+
+struct of_cpuidle_method {
+ const char *method;
+ struct cpuidle_ops *ops;
+};
+
+#define CPUIDLE_METHOD_OF_DECLARE(name, _method, _ops) \
+ static const struct of_cpuidle_method __cpuidle_method_of_table_##name \
+ __used __section(__cpuidle_method_of_table) \
+ = { .method = _method, .ops = _ops }
+
+extern int arm_cpuidle_suspend(int index);
+
+extern int arm_cpuidle_init(int cpu);
+
#endif
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index 45969f8..7b42a40 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -10,8 +10,17 @@
*/
#include
+#include
+#include
#include
+extern struct of_cpuidle_method __cpuidle_method_of_table[];
+
+static const struct of_cpuidle_method __cpuidle_method_of_table_sentinel
+ __used __section(__cpuidle_method_of_table_end);
+
+static struct cpuidle_ops cpuidle_ops[NR_CPUS];
+
int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
@@ -19,3 +28,66 @@ int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
return index;
}
+
+int arm_cpuidle_suspend(int index)
+{
+ int ret = -EOPNOTSUPP;
+ int cpu = smp_processor_id();
+
+ if (cpuidle_ops[cpu].suspend)
+ ret = cpuidle_ops[cpu].suspend(cpu, index);
+
+ return ret;
+}
+
+static struct cpuidle_ops *__init arm_cpuidle_get_ops(const char *method)
+{
+ struct of_cpuidle_method *m = __cpuidle_method_of_table;
+
+ for (; m->method; m++)
+ if (!strcmp(m->method, method))
+ return m->ops;
+
+ return NULL;
+}
+
+static int __init arm_cpuidle_read_ops(struct device_node *dn, int cpu)
+{
+ const char *enable_method;
+ struct cpuidle_ops *ops;
+
+ enable_method = of_get_property(dn, "enable-method", NULL);
+ if (!enable_method)
+ return -ENOENT;
+
+ ops = arm_cpuidle_get_ops(enable_method);
+ if (!ops) {
+ pr_warn("%s: unsupported enable-method property: %s\n",
+ dn->full_name, enable_method);
+ return -EOPNOTSUPP;
+ }
+
+ cpuidle_ops[cpu] = *ops; /* structure copy */
+
+ pr_notice("cpuidle: enable-method property '%s'"
+ " found operations\n", enable_method);
+
+ return 0;
+}
+
+int __init arm_cpuidle_init(int cpu)
+{
+ int ret = -EOPNOTSUPP;
+ struct device_node *cpu_node = of_cpu_device_node_get(cpu);
+
+ if (!cpu_node)
+ return -ENODEV;
+
+ ret = arm_cpuidle_read_ops(cpu_node, cpu);
+ if (!ret && cpuidle_ops[cpu].init)
+ ret = cpuidle_ops[cpu].init(cpu_node, cpu);
+
+ of_node_put(cpu_node);
+
+ return ret;
+}
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
index c60643f..460a38b 100644
--- a/arch/arm64/include/asm/cpuidle.h
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -17,5 +17,8 @@ static inline int cpu_suspend(unsigned long arg)
return -EOPNOTSUPP;
}
#endif
-
+static inline int arm_cpuidle_suspend(int index)
+{
+ return cpu_suspend(index);
+}
#endif
diff --git a/include/asm-generic/vmlinux.lds.h
b/include/asm-generic/vmlin
[PATCH V2 8/8] ARM: cpuidle: Change function name to be consistent with x86
Change the functions name:
arm_cpuidle_suspend => arm_idle
arm_cpuidle_init=> arm_idle_cpu_init
Signed-off-by: Daniel Lezcano
---
arch/arm/include/asm/cpuidle.h | 4 ++--
arch/arm/kernel/cpuidle.c| 4 ++--
arch/arm64/include/asm/cpuidle.h | 6 +++---
arch/arm64/kernel/cpuidle.c | 2 +-
drivers/cpuidle/cpuidle-arm.c| 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 1851e9d..7968948 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -42,8 +42,8 @@ struct of_cpuidle_method {
__used __section(__cpuidle_method_of_table) \
= { .method = _method, .ops = _ops }
-extern int arm_cpuidle_suspend(int index);
+extern int arm_idle(int index);
-extern int arm_cpuidle_init(int cpu);
+extern int arm_idle_cpu_init(int cpu);
#endif
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index 7b42a40..05a2c3e 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -29,7 +29,7 @@ int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
return index;
}
-int arm_cpuidle_suspend(int index)
+int arm_idle(int index)
{
int ret = -EOPNOTSUPP;
int cpu = smp_processor_id();
@@ -75,7 +75,7 @@ static int __init arm_cpuidle_read_ops(struct device_node
*dn, int cpu)
return 0;
}
-int __init arm_cpuidle_init(int cpu)
+int __init arm_idle_cpu_init(int cpu)
{
int ret = -EOPNOTSUPP;
struct device_node *cpu_node = of_cpu_device_node_get(cpu);
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
index 141b2fc..e9c0dc4e 100644
--- a/arch/arm64/include/asm/cpuidle.h
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -4,10 +4,10 @@
#include
#ifdef CONFIG_CPU_IDLE
-extern int arm_cpuidle_init(unsigned int cpu);
+extern int arm_idle_cpu_init(unsigned int cpu);
extern int cpu_suspend(unsigned long arg);
#else
-static inline int arm_cpuidle_init(unsigned int cpu)
+static inline int arm_idle_cpu_init(unsigned int cpu)
{
return -EOPNOTSUPP;
}
@@ -17,7 +17,7 @@ static inline int cpu_suspend(unsigned long arg)
return -EOPNOTSUPP;
}
#endif
-static inline int arm_cpuidle_suspend(int index)
+static inline int arm_idle(int index)
{
return cpu_suspend(index);
}
diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
index a78143a..b6b4fcf 100644
--- a/arch/arm64/kernel/cpuidle.c
+++ b/arch/arm64/kernel/cpuidle.c
@@ -15,7 +15,7 @@
#include
#include
-int arm_cpuidle_init(unsigned int cpu)
+int arm_idle_cpu_init(unsigned int cpu)
{
int ret = -EOPNOTSUPP;
struct device_node *cpu_node = of_cpu_device_node_get(cpu);
diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
index 0682ed0..cd8c32f 100644
--- a/drivers/cpuidle/cpuidle-arm.c
+++ b/drivers/cpuidle/cpuidle-arm.c
@@ -52,7 +52,7 @@ static int arm_enter_idle_state(struct cpuidle_device *dev,
* call the CPU ops suspend protocol with idle index as a
* parameter.
*/
- arm_cpuidle_suspend(idx);
+ arm_idle(idx);
cpu_pm_exit();
}
@@ -120,7 +120,7 @@ static int __init arm_idle_init(void)
* idle states suspend back-end specific data
*/
for_each_possible_cpu(cpu) {
- ret = arm_cpuidle_init(cpu);
+ ret = arm_idle_cpu_init(cpu);
/* This cpu does not support any idle states */
if (ret == -ENOSYS)
--
1.9.1
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[PATCH V2 5/8] ARM64: cpuidle: Remove arm64 reference
In the next patch, this driver will be common across ARM/ARM64. Remove all refs
to ARM64 as it will be shared with ARM32.
Signed-off-by: Daniel Lezcano
Acked-by: Kevin Hilman
Acked-by: Rob Herring
---
drivers/cpuidle/cpuidle-arm64.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
index 6ef291c7..1c94b88 100644
--- a/drivers/cpuidle/cpuidle-arm64.c
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -1,5 +1,5 @@
/*
- * ARM64 generic CPU idle driver.
+ * ARM/ARM64 generic CPU idle driver.
*
* Copyright (C) 2014 ARM Ltd.
* Author: Lorenzo Pieralisi
@@ -9,7 +9,7 @@
* published by the Free Software Foundation.
*/
-#define pr_fmt(fmt) "CPUidle arm64: " fmt
+#define pr_fmt(fmt) "CPUidle arm: " fmt
#include
#include
@@ -23,7 +23,7 @@
#include "dt_idle_states.h"
/*
- * arm64_enter_idle_state - Programs CPU to enter the specified state
+ * arm_enter_idle_state - Programs CPU to enter the specified state
*
* dev: cpuidle device
* drv: cpuidle driver
@@ -32,8 +32,8 @@
* Called from the CPUidle framework to program the device to the
* specified target state selected by the governor.
*/
-static int arm64_enter_idle_state(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int idx)
+static int arm_enter_idle_state(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int idx)
{
int ret;
@@ -57,8 +57,8 @@ static int arm64_enter_idle_state(struct cpuidle_device *dev,
return ret ? -1 : idx;
}
-static struct cpuidle_driver arm64_idle_driver = {
- .name = "arm64_idle",
+static struct cpuidle_driver arm_idle_driver = {
+ .name = "arm_idle",
.owner = THIS_MODULE,
/*
* State at index 0 is standby wfi and considered standard
@@ -68,32 +68,32 @@ static struct cpuidle_driver arm64_idle_driver = {
* handler for idle state index 0.
*/
.states[0] = {
- .enter = arm64_enter_idle_state,
+ .enter = arm_enter_idle_state,
.exit_latency = 1,
.target_residency = 1,
.power_usage= UINT_MAX,
.name = "WFI",
- .desc = "ARM64 WFI",
+ .desc = "ARM WFI",
}
};
-static const struct of_device_id arm64_idle_state_match[] __initconst = {
+static const struct of_device_id arm_idle_state_match[] __initconst = {
{ .compatible = "arm,idle-state",
- .data = arm64_enter_idle_state },
+ .data = arm_enter_idle_state },
{ },
};
/*
- * arm64_idle_init
+ * arm_idle_init
*
- * Registers the arm64 specific cpuidle driver with the cpuidle
+ * Registers the arm specific cpuidle driver with the cpuidle
* framework. It relies on core code to parse the idle states
* and initialize them using driver data structures accordingly.
*/
-static int __init arm64_idle_init(void)
+static int __init arm_idle_init(void)
{
int cpu, ret;
- struct cpuidle_driver *drv = &arm64_idle_driver;
+ struct cpuidle_driver *drv = &arm_idle_driver;
/*
* Initialize idle states data, starting at index 1.
@@ -101,7 +101,7 @@ static int __init arm64_idle_init(void)
* let the driver initialization fail accordingly since there is no
* reason to initialize the idle driver if only wfi is supported.
*/
- ret = dt_init_idle_driver(drv, arm64_idle_state_match, 1);
+ ret = dt_init_idle_driver(drv, arm_idle_state_match, 1);
if (ret <= 0)
return ret ? : -ENODEV;
@@ -119,4 +119,4 @@ static int __init arm64_idle_init(void)
return cpuidle_register(drv, NULL);
}
-device_initcall(arm64_idle_init);
+device_initcall(arm_idle_init);
--
1.9.1
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[PATCH v3] add support for Freescale's MMA8653FC 10 bit accelerometer
From: Martin Kepplinger The MMA8653FC is a low-power, three-axis, capacitive micromachined accelerometer with 10 bits of resolution with flexible user-programmable options. Embedded interrupt functions enable overall power savings, by relieving the host processor from continuously polling data, for example using the poll() system call. The device can be configured to generate wake-up interrupt signals from any combination of the configurable embedded functions, enabling the MMA8653FC to monitor events while remaining in a low-power mode during periods of inactivity. This driver provides devicetree properties to program the device's behaviour and a simple, tested and documented sysfs interface. The data sheet and more information is available on Freescale's website. Signed-off-by: Martin Kepplinger Signed-off-by: Christoph Muellner --- applies to v4.0-rc4 and the current -next. patch revision history .. v3 moves the driver from drivers/input/misc to drivers/misc v2 corrects licensing and commit messages and adds appropriate recipients .../testing/sysfs-bus-i2c-devices-fsl-mma8653fc| 39 + .../devicetree/bindings/misc/fsl,mma8653fc.txt | 96 +++ MAINTAINERS| 5 + drivers/misc/Kconfig | 11 + drivers/misc/Makefile | 1 + drivers/misc/mma8653fc.c | 913 + 6 files changed, 1065 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc create mode 100644 Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt create mode 100644 drivers/misc/mma8653fc.c diff --git a/Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc b/Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc new file mode 100644 index 000..8172c27 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc @@ -0,0 +1,39 @@ +What: /sys/bus/i2c/drivers/mma8653fc/*/standby +Date: March 2015 +Contact: Martin Kepplinger +Description: + Write 0 to this in order to turn on the device, and 1 to turn + it off. Read to see if it is turned on or off. + + +What: /sys/bus/i2c/drivers/mma8653fc/*/currentmode +Date: March 2015 +Contact: Martin Kepplinger +Description: + Reading this provides the current state of the device, read + directly from a register. This can be "standby", "wake" or + "sleep". + + +What: /sys/bus/i2c/drivers/mma8653fc/*/position +Date: March 2015 +Contact: Martin Kepplinger +Description: + Read only. Without interrupts enabled gets current position + values by reading. Poll "position" with interrupt conditions + set, to get notified; see Documentation/.../fsl,mma8653fc.txt + + position file format: + "x y z [landscape/portrait status] [front/back status]" + + x y z values: + in mg + landscape/portrait status char: + r landscape right + d portrait down + u portrait up + l landscape left + front/back status char: + f front facing + b back facing + diff --git a/Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt b/Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt new file mode 100644 index 000..3921acb --- /dev/null +++ b/Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt @@ -0,0 +1,96 @@ +Freescale MMA8653FC 3-axis Accelerometer + +Required properties: +- compatible + "fsl,mma8653fc" +- reg + I2C address + +Optional properties: + +- interrupt-parent + a phandle for the interrupt controller (see + Documentation/devicetree/bindings/interrupt-controller/interrupts.txt) +- interrupts + interrupt line to which the chip is connected +- int1 + set to use interrupt line 1 instead of 2 +- int_active_high + set interrupt line active high +- ir_freefall_motion_x + activate freefall/motion interrupts on x axis +- ir_freefall_motion_y + activate freefall/motion interrupts on y axis +- ir_freefall_motion_z + activate freefall/motion interrupts on z axis +- irq_threshold + 0 < value < 8000: threshold for motion interrupts in mg +- ir_landscape_portrait + activate landscape/portrait interrupts +- ir_data_ready: + activate data-ready interrupts + Interrupt events can be activated in any combination. +- range + 2, 4, or 8: range in g, default: 2 +- auto_wake_sleep + auto sleep mode (lower frequency) +- motion_mode + use motion mode instead of freefall mode (trigger if >threshold). + per default an interrupt occurs if mot
Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
Am 2015-03-18 um 19:05 schrieb Bastien Nocera: > On Wed, 2015-03-18 at 19:02 +0100, Martin Kepplinger wrote: >> Am 2015-03-18 um 17:59 schrieb Bastien Nocera: >>> On Wed, 2015-03-18 at 17:42 +0100, Martin Kepplinger wrote: >>> It could have gone to drivers/iio/accel if it would use an iio interface, which would make more sense, you are right, but I simply don't have the time to merge it in to iio. It doesn't use an input interface either but I don't see a good place for an accelerometer that uses sysfs only. It works well, is a relatively recent chip and a clean dirver. But this is all I can provide. >>> >>> As a person who works on the user-space interaction of those with >>> desktops [1]: Urgh. >>> >>> I already have 3 (probably 4) types of accelerometers to contend >>> with, I'm not fond of adding yet another type. >>> >>> Is there any way to get this hardware working outside the SoCs >>> it's designed for (say, a device with I2C like a Raspberry Pi), >>> so that a kind soul could handle getting this using the right >>> interfaces? >>> >> >> It works on basically any SoC and is in no way limited in this >> regard. Sure, userspace has to expicitely support it and I hear you. >> Using the iio interface would make more sense. I can only say I'd >> love to have the time to move this driver over. I'm very sorry. > > How can we get the hardware for somebody to use on their own > laptops/embedded boards to implement this driver? > It's connected over I2C. If the included documentation is not clear please tell me what exacly. Thanks! -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
On Wed, 2015-03-18 at 19:02 +0100, Martin Kepplinger wrote: > Am 2015-03-18 um 17:59 schrieb Bastien Nocera: > > On Wed, 2015-03-18 at 17:42 +0100, Martin Kepplinger wrote: > > > > > > > > It could have gone to drivers/iio/accel if it would use an iio > > > interface, which would make more sense, you are right, but I > > > simply don't have the time to merge it in to iio. > > > > > > It doesn't use an input interface either but I don't see a good > > > place for an accelerometer that uses sysfs only. > > > > > > It works well, is a relatively recent chip and a clean dirver. > > > But this is all I can provide. > > > > As a person who works on the user-space interaction of those with > > desktops [1]: Urgh. > > > > I already have 3 (probably 4) types of accelerometers to contend > > with, I'm not fond of adding yet another type. > > > > Is there any way to get this hardware working outside the SoCs > > it's designed for (say, a device with I2C like a Raspberry Pi), > > so that a kind soul could handle getting this using the right > > interfaces? > > > > It works on basically any SoC and is in no way limited in this > regard. Sure, userspace has to expicitely support it and I hear you. > Using the iio interface would make more sense. I can only say I'd > love to have the time to move this driver over. I'm very sorry. How can we get the hardware for somebody to use on their own laptops/embedded boards to implement this driver? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
Am 2015-03-18 um 17:59 schrieb Bastien Nocera: > On Wed, 2015-03-18 at 17:42 +0100, Martin Kepplinger wrote: >> > >> It could have gone to drivers/iio/accel if it would use an iio >> interface, which would make more sense, you are right, but I simply >> don't have the time to merge it in to iio. >> >> It doesn't use an input interface either but I don't see a good >> place for an accelerometer that uses sysfs only. >> >> It works well, is a relatively recent chip and a clean dirver. But >> this is all I can provide. > > As a person who works on the user-space interaction of those with > desktops [1]: Urgh. > > I already have 3 (probably 4) types of accelerometers to contend with, > I'm not fond of adding yet another type. > > Is there any way to get this hardware working outside the SoCs it's > designed for (say, a device with I2C like a Raspberry Pi), so that a > kind soul could handle getting this using the right interfaces? > It works on basically any SoC and is in no way limited in this regard. Sure, userspace has to expicitely support it and I hear you. Using the iio interface would make more sense. I can only say I'd love to have the time to move this driver over. I'm very sorry. > Cheers > > [1]: https://github.com/hadess/iio-sensor-proxy > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: renesas-intc-irqpin: Add optional functional clock to bindings
Hello.
On 03/18/2015 07:37 PM, Geert Uytterhoeven wrote:
This clock is managed since commit 705bc96c2c15313c ("irqchip:
renesas-intc-irqpin: Add minimal runtime PM support").
Also add an example while we're at.
Signed-off-by: Geert Uytterhoeven
---
.../interrupt-controller/renesas,intc-irqpin.txt | 29 ++
1 file changed, 29 insertions(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
index 4f7946ae8adcdc04..e7cfcec056159b93 100644
---
a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -25,3 +25,32 @@ Optional properties:
if different from the default 4 bits
- control-parent: disable and enable interrupts on the parent interrupt
controller, needed for some broken implementations
+- clocks: Must contain a reference to the functional clock. The property is
+ mandatory if the hardware implements a controllable functional clock for
+ the irqpin controller instance.
+
+
+Example
+---
+
+ irqpin1: irqpin@e694 {
The node name should be "interrupt-controller@e694".
+ compatible = "renesas,intc-irqpin-r8a7740",
+"renesas,intc-irqpin";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xe694 4>,
+ <0xe6900014 4>,
+ <0xe6900024 1>,
+ <0xe6900044 1>,
+ <0xe6900064 1>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH
+ 0 149 IRQ_TYPE_LEVEL_HIGH>;
Hm, 8 similar interrupts?
+ clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
+ power-domains = <&pd_a4s>;
+ };
WBR, Sergei
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Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
On Wed, 2015-03-18 at 17:42 +0100, Martin Kepplinger wrote: > > It could have gone to drivers/iio/accel if it would use an iio > interface, which would make more sense, you are right, but I simply > don't have the time to merge it in to iio. > > It doesn't use an input interface either but I don't see a good > place for an accelerometer that uses sysfs only. > > It works well, is a relatively recent chip and a clean dirver. But > this is all I can provide. As a person who works on the user-space interaction of those with desktops [1]: Urgh. I already have 3 (probably 4) types of accelerometers to contend with, I'm not fond of adding yet another type. Is there any way to get this hardware working outside the SoCs it's designed for (say, a device with I2C like a Raspberry Pi), so that a kind soul could handle getting this using the right interfaces? Cheers [1]: https://github.com/hadess/iio-sensor-proxy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
On Wed, Mar 18, 2015 at 05:42:13PM +0100, Martin Kepplinger wrote: > Am 2015-03-18 um 17:21 schrieb Alexander Stein: > > On Wednesday 18 March 2015 16:55:57, Martin Kepplinger wrote: > >> From: Martin Kepplinger > >> > >> The MMA8653FC is a low-power, three-axis, capacitive micromachined > >> accelerometer with 10 bits of resolution with flexible user-programmable > >> options. > >> > >> Embedded interrupt functions enable overall power savings, by relieving the > >> host processor from continuously polling data, for example using the poll() > >> system call. > >> > >> The device can be configured to generate wake-up interrupt signals from any > >> combination of the configurable embedded functions, enabling the MMA8653FC > >> to monitor events while remaining in a low-power mode during periods of > >> inactivity. > >> > >> This driver provides devicetree properties to program the device's > >> behaviour > >> and a simple, tested and documented sysfs interface. The data sheet and > >> more > >> information is available on Freescale's website. > >> > >> Signed-off-by: Martin Kepplinger > >> Signed-off-by: Christoph Muellner > >> > >> --- > >> applies to v4.0-rc4 and the current -next. > >> > >> patch revision history > >> .. > >> v2 corrects licensing and commit messages and adds appropriate recipients > >> > >> .../testing/sysfs-bus-i2c-devices-fsl-mma8653fc| 39 + > >> .../devicetree/bindings/misc/fsl,mma8653fc.txt | 96 +++ > >> MAINTAINERS| 5 + > >> drivers/input/misc/Kconfig | 11 + > >> drivers/input/misc/Makefile| 1 + > >> drivers/input/misc/mma8653fc.c | 913 > >> + > >> 6 files changed, 1065 insertions(+) > >> create mode 100644 > >> Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc > >> create mode 100644 > >> Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt > >> create mode 100644 drivers/input/misc/mma8653fc.c > > > > Shouldn't this go to drivers/iio/magnetometer instead of defining a new > > sysfs ABI? > > > > It could have gone to drivers/iio/accel if it would use an iio > interface, which would make more sense, you are right, but I simply > don't have the time to merge it in to iio. > > It doesn't use an input interface either but I don't see a good place > for an accelerometer that uses sysfs only. drivers/misc? Since it is not using input infrastructure (nor should it), it does not belong in drivers/input. Thanks. -- Dmitry -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] add support for Freescale's MMA8653FC 10 bit accelerometer
Am 2015-03-18 um 17:21 schrieb Alexander Stein: > On Wednesday 18 March 2015 16:55:57, Martin Kepplinger wrote: >> From: Martin Kepplinger >> >> The MMA8653FC is a low-power, three-axis, capacitive micromachined >> accelerometer with 10 bits of resolution with flexible user-programmable >> options. >> >> Embedded interrupt functions enable overall power savings, by relieving the >> host processor from continuously polling data, for example using the poll() >> system call. >> >> The device can be configured to generate wake-up interrupt signals from any >> combination of the configurable embedded functions, enabling the MMA8653FC >> to monitor events while remaining in a low-power mode during periods of >> inactivity. >> >> This driver provides devicetree properties to program the device's behaviour >> and a simple, tested and documented sysfs interface. The data sheet and more >> information is available on Freescale's website. >> >> Signed-off-by: Martin Kepplinger >> Signed-off-by: Christoph Muellner >> --- >> applies to v4.0-rc4 and the current -next. >> >> patch revision history >> .. >> v2 corrects licensing and commit messages and adds appropriate recipients >> >> .../testing/sysfs-bus-i2c-devices-fsl-mma8653fc| 39 + >> .../devicetree/bindings/misc/fsl,mma8653fc.txt | 96 +++ >> MAINTAINERS| 5 + >> drivers/input/misc/Kconfig | 11 + >> drivers/input/misc/Makefile| 1 + >> drivers/input/misc/mma8653fc.c | 913 >> + >> 6 files changed, 1065 insertions(+) >> create mode 100644 >> Documentation/ABI/testing/sysfs-bus-i2c-devices-fsl-mma8653fc >> create mode 100644 Documentation/devicetree/bindings/misc/fsl,mma8653fc.txt >> create mode 100644 drivers/input/misc/mma8653fc.c > > Shouldn't this go to drivers/iio/magnetometer instead of defining a new sysfs > ABI? > It could have gone to drivers/iio/accel if it would use an iio interface, which would make more sense, you are right, but I simply don't have the time to merge it in to iio. It doesn't use an input interface either but I don't see a good place for an accelerometer that uses sysfs only. It works well, is a relatively recent chip and a clean dirver. But this is all I can provide. > Best regards, > Alexander > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 1/6] wlcore: set irq_trigger in board files instead of hiding behind a quirk
From: Luciano Coelho
The platform_quirk element in the platform data was used
to change the way the IRQ is triggered. When set,
the EDGE_IRQ quirk would change the irqflags used
and treat edge trigger differently from the rest.
Instead of hiding this irq flag setting behind the quirk,
have the board files set the irq_trigger explicitly.
This will allow us to use standard irq DT definitions
later on.
Signed-off-by: Luciano Coelho
[Eliad - rebase, add irq_trigger field and pass it,
update board file changes]
Signed-off-by: Eliad Peller
---
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-omap2/pdata-quirks.c | 1 +
drivers/net/wireless/ti/wlcore/debugfs.c | 2 +-
drivers/net/wireless/ti/wlcore/main.c| 27 ---
drivers/net/wireless/ti/wlcore/sdio.c| 2 +-
drivers/net/wireless/ti/wlcore/wlcore.h | 5 ++---
include/linux/wl12xx.h | 5 +
7 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c
b/arch/arm/mach-davinci/board-da850-evm.c
index 6b5a97d..916589c 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1385,8 +1385,8 @@ static const short da850_wl12xx_pins[] __initconst = {
static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
.irq= -1,
+ .irq_trigger= IRQ_TYPE_EDGE_RISING,
.board_ref_clock= WL12XX_REFCLOCK_38,
- .platform_quirks= WL12XX_PLATFORM_QUIRK_EDGE_IRQ,
};
static __init int da850_wl12xx_init(void)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index e642b07..e86fb0d 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -48,6 +48,7 @@ static void __init __used legacy_init_wl12xx(unsigned
ref_clock,
wl12xx.board_ref_clock = ref_clock;
wl12xx.board_tcxo_clock = tcxo_clock;
wl12xx.irq = gpio_to_irq(gpio);
+ wl12xx.irq_trigger = IRQ_TYPE_LEVEL_HIGH;
res = wl12xx_set_platform_data(&wl12xx);
if (res) {
diff --git a/drivers/net/wireless/ti/wlcore/debugfs.c
b/drivers/net/wireless/ti/wlcore/debugfs.c
index 68f3bf2..eb43f94 100644
--- a/drivers/net/wireless/ti/wlcore/debugfs.c
+++ b/drivers/net/wireless/ti/wlcore/debugfs.c
@@ -502,7 +502,7 @@ static ssize_t driver_state_read(struct file *file, char
__user *user_buf,
DRIVER_STATE_PRINT_HEX(irq);
/* TODO: ref_clock and tcxo_clock were moved to wl12xx priv */
DRIVER_STATE_PRINT_HEX(hw_pg_ver);
- DRIVER_STATE_PRINT_HEX(platform_quirks);
+ DRIVER_STATE_PRINT_HEX(irq_flags);
DRIVER_STATE_PRINT_HEX(chip.id);
DRIVER_STATE_PRINT_STR(chip.fw_ver_str);
DRIVER_STATE_PRINT_STR(chip.phy_fw_ver_str);
diff --git a/drivers/net/wireless/ti/wlcore/main.c
b/drivers/net/wireless/ti/wlcore/main.c
index 1e13699..67518f6 100644
--- a/drivers/net/wireless/ti/wlcore/main.c
+++ b/drivers/net/wireless/ti/wlcore/main.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include "wlcore.h"
#include "debug.h"
@@ -538,7 +539,7 @@ static int wlcore_irq_locked(struct wl1271 *wl)
* In case edge triggered interrupt must be used, we cannot iterate
* more than once without introducing race conditions with the hardirq.
*/
- if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
+ if (wl->irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
loopcount = 1;
wl1271_debug(DEBUG_IRQ, "IRQ work");
@@ -6249,7 +6250,6 @@ struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size,
u32 aggr_buf_size,
wl->ap_ps_map = 0;
wl->ap_fw_ps_map = 0;
wl->quirks = 0;
- wl->platform_quirks = 0;
wl->system_hlid = WL12XX_SYSTEM_HLID;
wl->active_sta_count = 0;
wl->active_link_count = 0;
@@ -6391,7 +6391,8 @@ static void wlcore_nvs_cb(const struct firmware *fw, void
*context)
struct platform_device *pdev = wl->pdev;
struct wlcore_platdev_data *pdev_data = dev_get_platdata(&pdev->dev);
struct wl12xx_platform_data *pdata = pdev_data->pdata;
- unsigned long irqflags;
+ struct resource *res;
+
int ret;
irq_handler_t hardirq_fn = NULL;
@@ -6418,19 +6419,23 @@ static void wlcore_nvs_cb(const struct firmware *fw,
void *context)
/* adjust some runtime configuration parameters */
wlcore_adjust_conf(wl);
- wl->irq = platform_get_irq(pdev, 0);
- wl->platform_quirks = pdata->platform_quirks;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ wl1271_error("Could not get IRQ resource");
+ goto out_free_nvs;
+ }
+
+ wl->irq = res->start;
+ wl->irq_flags = res->flags & IRQF_TRIGGER_MASK;
wl->if_ops = pdev_data->if_ops;
- if (wl->platform_quirks & WL12XX_P
