Re: [PATCH 14/14] ARM: dts: qs600: Add SD card detect support.

[Igor Grinberg]

On 09/18/15 15:32, Srinivas Kandagatla wrote:
> This patch adds SD card detect support.
> 
> Signed-off-by: Srinivas Kandagatla 

Acked-by: Igor Grinberg 

> ---
>  arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts 
> b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> index cc9d942..03784f1 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> @@ -29,6 +29,16 @@
>   };
>  
>   soc {
> + pinctrl@80 {
> + card_detect: card_detect {
> + mux {
> + pins = "gpio26";
> + function = "gpio";
> + bias-disable;
> + };
> + };
> + };
> +
>   rpm@108000 {
>   regulators {
>   vin_lvs1_3_6-supply = <&pm8921_s4>;
> @@ -197,6 +207,9 @@
>   sdcc3: sdcc@1218 {
>   status = "okay";
>   vmmc-supply = <&v3p3_fixed>;
> + pinctrl-names   = "default";
> + pinctrl-0   = <&card_detect>;
> + cd-gpios= <&tlmm_pinmux 26 
> GPIO_ACTIVE_LOW>;
>   };
>   /* WLAN */
>   sdcc4: sdcc@121c {
> 

-- 
Regards,
Igor.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 12/14] ARM: dts: qs600: add pwrseq support to WLAN

[Igor Grinberg]

On 09/18/15 15:32, Srinivas Kandagatla wrote:
> Add pwrseq support to sdcc4 which would enable a proper reset of WLAN
> without ugly hacks in the board support file.
> 
> Signed-off-by: Srinivas Kandagatla 

Thanks Srini!

Acked-by: Igor Grinberg 

> ---
>  arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 32 
> +
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts 
> b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> index 8aac3be..cc9d942 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> @@ -1,4 +1,6 @@
>  #include "qcom-apq8064-v2.0.dtsi"
> +#include 
> +#include 
>  
>  / {
>   model = "CompuLab CM-QS600";
> @@ -12,6 +14,20 @@
>   stdout-path = "serial0:115200n8";
>   };
>  
> + pwrseq {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "simple-bus";
> +
> + sdcc4_pwrseq: sdcc4_pwrseq {
> + pinctrl-names = "default";
> + pinctrl-0 = <&wlan_default_gpios>;
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
>   soc {
>   rpm@108000 {
>   regulators {
> @@ -154,6 +170,21 @@
>   regulator-always-on;
>   };
>  
> + qcom,ssbi@50 {
> + pmic@0 {
> + gpio@150 {
> + wlan_default_gpios: wlan-gpios {
> + pios {
> + pins = "gpio43";
> + function = "normal";
> + bias-disable;
> + power-source = 
> ;
> + };
> + };
> + };
> + };
> + };
> +
>   amba {
>   /* eMMC */
>   sdcc1: sdcc@1240 {
> @@ -172,6 +203,7 @@
>   status = "okay";
>   vmmc-supply = <&v3p3_fixed>;
>   vqmmc-supply = <&v3p3_fixed>;
> + mmc-pwrseq = <&sdcc4_pwrseq>;
>   };
>   };
>   };
> 

-- 
Regards,
Igor.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 10/14] ARM: dts: qs600: Add missing pinctrl property for gsbi7 uart

[Igor Grinberg]

On 09/18/15 15:31, Srinivas Kandagatla wrote:
> This patch adds missing 2pin uart pinctrl property to gsbi7 uart on
> CM-QS600.
> 
> Signed-off-by: Srinivas Kandagatla 

Acked-by: Igor Grinberg 

> ---
>  arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts 
> b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> index bdea747..8aac3be 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
> @@ -101,6 +101,8 @@
>   qcom,mode = ;
>   serial@1664 {
>   status = "ok";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gsbi7_uart_2pins>;
>   };
>   };
>  
> 

-- 
Regards,
Igor.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v10 0/4] Implement OCOTP driver for Vybrid using NVMEM

[maitysanchayan]

Hello,

Ping?

- Sanchayan.

On 15-09-07 13:51:34, Sanchayan Maity wrote:
> Hello,
> 
> Tested on Greg's tree char-misc-next branch along with Stefan's NAND driver
> patchset.
> 
> Sample output on Colibri VF50
> 
> root@colibri-vf:/sys/bus/nvmem/devices/ocotp0# uname -a
> Linux colibri-vf 4.2.0-rc6-9-g1cec223 #5 SMP Mon Sep 7 12:34:37 IST 2015 
> armv7l GNU/Linux
> 
> root@colibri-vf:/sys/bus/nvmem/devices/ocotp0# hexdump nvmem
> 000        
> *
> 410 72a6 df64      
> 420 11d4 2006      
> 430        
> *
> 450 0280       
> 460        
> *
> 880 8f01       
> 890        
> *
> 8c0  1300      
> 8d0 320a 0800      
> 8e0  e200      
> 8f0        
> *
> c80 bada bada      
> *
> cc0        
> *
> cf0
> 
> Changes since v9:
> 1. Drop clock-names property from DT
> 2. Rebase on top of latest char-misc-next
> 
> Changes since v8:
> 1. Fix three lines over 80 characters
> 2. Rebase on top of Greg's char-misc-next branch
> 
> Changes since v7:
> 1. Add COMPILE_TEST to Kconfig
> 2. Use GENMASK and BIT macros where applicable
> 3. Fix a code alignment issue
> 4. Get the max_register value for regmap config using
> resource_size()
> 5. Also add copyright info as the driver logic is based off
> on ocotp code in barebox
> 6. Add missing info related to clock in DT binding doc
> 
> Changes since v6:
> 1. Use the v9 of NVMEM framework patchset
> 2. Add a few comments
> 3. Initialise buffer address not part of the fuse map to 0
> instead of only handling buffer locations with valid fuse
> addresses.
> 
> Changes since v5:
> Use NVMEM framework by Srinivas and Maxime
> 
> Changes since v4:
> 1. Use devm_* family of functions and use a struct to get rid of
> global variables (suggested by Joachim Eastwood)
> 2. Make Kconfig govern the compilation with tristate, instead of
> earlier bool. Paul Bolle raised a valid point that perhaps this
> should have been built in with the bool, however I had not taken
> into consideration generic distro kernels and it makes sense to
> have this tristated. (comments from Paul Bolle and Andreas Farber)
> 
> Changes since v3:
> Instead of using the syscon_regmap_lookup_by_compatible function
> use a phandle in the device tree along with offsets specified in
> this phandle node and then read the offset along with the device
> node in the driver for reading from the required region.
> 
> Changes since v2:
> Implement the SoC bus code as a driver in drivers/soc
> by registering with fsl,mscm-cpucfg as per Arnd's feedback
> 
> Changes since v1:
> Sort the headers in alphabetical order
> 
> Changes since RFC:
> Use a DT entry for the ROM area while specifying it as syscon.
> 
> Version 9 patches can be found here
> https://lkml.org/lkml/2015/8/12/530
> 
> Version 8 patches can be found here
> https://lkml.org/lkml/2015/8/10/566
> 
> Version 7 patches can be found here
> https://lkml.org/lkml/2015/8/6/440
> 
> Version 6 RFC patches can be found here
> http://lkml.iu.edu/hypermail/linux/kernel/1506.2/05123.html
> 
> Version 5 of the patchset can be found here
> http://lkml.iu.edu/hypermail/linux/kernel/1506.0/03787.html
> 
> Version 4 of the patchset can be found here
> https://lkml.org/lkml/2015/5/26/199
> 
> Version 3 of the patchset can be found here
> http://www.spinics.net/lists/arm-kernel/msg420847.html
> 
> Version 2 of the patchset can be found here
> http://www.spinics.net/lists/devicetree/msg80654.html
> 
> Version 1 of the patchset can be found here
> http://www.spinics.net/lists/devicetree/msg80257.html
> 
> The RFC version can be found here
> https://lkml.org/lkml/2015/5/11/13
> 
> Thanks & Regards,
> Sanchayan Maity.
> 
> Sanchayan Maity (4):
>   clk: clk-vf610: Add clock for Vybrid OCOTP controller
>   ARM: dts: vfxxx: Add OCOTP node
>   drivers: nvmem: Add Vybrid OCOTP support
>   nvmem: Add DT binding documentation for Vybrid OCOTP driver
> 
>  .../devicetree/bindings/nvmem/vf610-ocotp.txt  |  19 ++
>  arch/arm/boot/dts/vfxxx.dtsi   |   8 +
>  drivers/clk/imx/clk-vf610.c|   1 +
>  drivers/nvmem/Kconfig  |  10 +
>  drivers/nvmem/Makefile |   2 +
>  drivers/nvmem/vf610-ocotp.c| 302 
> +
>  include/dt-bindings/clock/vf610-clock.h|   3 +-
>  7 files changed, 344 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt
>  create mode 100644 drivers/nvmem/vf610-ocotp.c
> 
> -- 
> 2.5.1
> 
--
To unsubscribe from this list: s

Re: [PATCH v2 1/2] input: Add Qualcomm PM8941 power key driver

[Bjorn Andersson]

On Tue 15 Sep 04:36 PDT 2015, Ivan T. Ivanov wrote:

> 
> On Fri, 2015-01-23 at 16:19 -0800, Bjorn Andersson wrote:
> > From: Courtney Cavin ca...@sonymobile.com>
> > 
> > Signed-off-by: Courtney Cavin ca...@sonymobile.com>
> > Signed-off-by: Bjorn Andersson anders...@sonymobile.com>
> > 
> 
> 
> 
> > 
> > +config INPUT_PM8941_PWRKEY
> > +   tristate "Qualcomm PM8941 power key support"
> > +   depends on MFD_SPMI_PMIC
> > +   help
> > +   Say Y here if you want support for the power key 
> > usually found
> > +   on boards using a Qualcomm PM8941 compatible PMIC.
> > +
> 
> Hi Bjorn, Courtney, 
> 
> Do you plan to extend this driver to support RESIN_N PMIC input?
>  

It's way down on the todo-list, so not right now.

> It looks like the same downstream "qcom,qpnp-power-on" handle
> this functionality for recent PMIC versions.
> 

Right, it seems to be functionality in the PON block.

> What will be the best way to add this new functionality, extend
> this driver, write new one...?
> 

Perhaps the naming of the driver isn't the best in the end, but I think
it should be implemented by the same driver...

Regards,
Bjorn
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 0/5] net: Hisilicon Network Subsystem support

[David Miller]

From: huangdaode 
Date: Thu, 17 Sep 2015 14:51:45 +0800

> This is V2 of Hisilicon Network Subsystem(HNS) patchesets taking care
> about LKML comments.
> 
> Please find out the changes from the change logs. 
> This patchset is rebased on mainline kernel Linux 4.3-rc1 branch.
> 
> [PATCH v2 1/5] Device Tree Binding Documentation
> [PATCH v2 2/5] Merge MDIO Module
> [PATCH v2 3/5] Hisilicon Network Acceleration Engine Framework
> [PATCH v2 4/5] Distributed System Area Fabric Module
> [PATCH v2 5/5] Basic Ethernet Driver Module
> 
> Changes from V1:
> 1. Remove "inline" in C file (according to LKML comment, same in below).
> 2. Fix a bug about class_find_device.
> 3. Change the DTS pattern on hnae, restruct it to compatible with Hi1610 soc.
> 4. Unified hip04_mdio and hip05_mdio into hns_mdio, which is more usaul for 
>later SOCs.
> 
> V1 Patches Reference: https://lkml.org/lkml/2015/8/14/165

Series applied, thanks.

 
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 5/5] arm64: dts: Enable the Thermal on R88 board

[Caesar Wang]

This patch enable the TS-ADC.

When a thermal temperature is invoked use the CRU to reset the chip
on R88 board. TSHUT is low active on this board.

Signed-off-by: Caesar Wang 
---

 arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts 
b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index 401a812..7684426a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -336,6 +336,12 @@
status = "okay";
 };
 
+&tsadc {
+   rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+   rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+   status = "okay";
+}
+
 &uart2 {
status = "okay";
 };
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 3/5] arm64: dts: Add the thermal data found on RK3368

[Caesar Wang]

This patchset add the thermal for RK3368 dts,
Since the two CPU clusters, with four CPU core for each cluster,
One cluster is optimized for high-performance(big cluster) and the othe
is optimized for low power(little cluster).

This patch adds the second order for thermal throttle, and the critical
temperature for thermal over-tempeature protection on Software.

Signed-off-by: Caesar Wang 
---

 arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi | 112 +++
 1 file changed, 112 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi
new file mode 100644
index 000..a10010f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi
@@ -0,0 +1,112 @@
+/*
+ * Device Tree Source for RK3368 SoC thermal
+ *
+ * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ * Caesar Wang 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+
+cpu_thermal: cpu_thermal {
+   polling-delay-passive = <100>; /* milliseconds */
+   polling-delay = <5000>; /* milliseconds */
+
+   thermal-sensors = <&tsadc 0>;
+
+   trips {
+   cpu_alert0: cpu_alert0 {
+   temperature = <75000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   cpu_alert1: cpu_alert1 {
+   temperature = <8>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   cpu_crit: cpu_crit {
+   temperature = <95000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <&cpu_alert0>;
+   cooling-device =
+   <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   map1 {
+   trip = <&cpu_alert1>;
+   cooling-device =
+   <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   };
+};
+
+gpu_thermal: gpu_thermal {
+   polling-delay-passive = <100>; /* milliseconds */
+   polling-delay = <5000>; /* milliseconds */
+
+   thermal-sensors = <&tsadc 1>;
+
+   trips {
+   gpu_alert0: gpu_alert0 {
+   temperature = <8>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   gpu_crit: gpu_crit {
+   temperature = <115>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+

[PATCH 2/5] thermal: rockchip: Support the RK3368 SoCs in thermal driver

[Caesar Wang]

The RK3368 SoCs support to 2 channel TS-ADC, the temperature criteria
of each channel can be configurable.

The system has two Temperature Sensors, channel 0 is for CPU,
and channel 1 is for GPU.

Signed-off-by: Caesar Wang 
---

 drivers/thermal/rockchip_thermal.c | 201 -
 1 file changed, 176 insertions(+), 25 deletions(-)

diff --git a/drivers/thermal/rockchip_thermal.c 
b/drivers/thermal/rockchip_thermal.c
index 4d5b7d4..16d2476 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -1,6 +1,9 @@
 /*
  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  *
+ * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ * Caesar Wang 
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
@@ -43,16 +46,11 @@ enum tshut_polarity {
TSHUT_HIGH_ACTIVE,
 };
 
-/**
- * The system has three Temperature Sensors.  channel 0 is reserved,
- * channel 1 is for CPU, and channel 2 is for GPU.
- */
-enum sensor_id {
-   SENSOR_CPU = 1,
-   SENSOR_GPU,
-};
-
 struct rockchip_tsadc_chip {
+   /* The sensor id of chip correspond to the ADC channel */
+   int cpu_id;
+   int gpu_id;
+
/* The hardware-controlled tshut property */
long tshut_temp;
enum tshut_mode tshut_mode;
@@ -72,10 +70,11 @@ struct rockchip_tsadc_chip {
 struct rockchip_thermal_sensor {
struct rockchip_thermal_data *thermal;
struct thermal_zone_device *tzd;
-   enum sensor_id id;
+   int id;
 };
 
-#define NUM_SENSORS2 /* Ignore unused sensor 0 */
+/* Two sensors: CPU and GPU */
+#define NUM_SENSORS2
 
 struct rockchip_thermal_data {
const struct rockchip_tsadc_chip *chip;
@@ -94,7 +93,7 @@ struct rockchip_thermal_data {
enum tshut_polarity tshut_polarity;
 };
 
-/* TSADC V2 Sensor info define: */
+/* TSADC Sensor info define: */
 #define TSADCV2_AUTO_CON   0x04
 #define TSADCV2_INT_EN 0x08
 #define TSADCV2_INT_PD 0x0c
@@ -116,6 +115,8 @@ struct rockchip_thermal_data {
 #define TSADCV2_INT_PD_CLEAR_MASK  ~BIT(8)
 
 #define TSADCV2_DATA_MASK  0xfff
+#define TSADCV3_DATA_MASK  0x3ff
+
 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT   4
 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
 #define TSADCV2_AUTO_PERIOD_TIME   250 /* msec */
@@ -164,6 +165,45 @@ static const struct tsadc_table v2_code_table[] = {
{3421, 125000},
 };
 
+static const struct tsadc_table v3_code_table[] = {
+   {0, -4},
+   {106, -4},
+   {108, -35000},
+   {110, -3},
+   {112, -25000},
+   {114, -2},
+   {116, -15000},
+   {118, -1},
+   {120, -5000},
+   {122, 0},
+   {124, 5000},
+   {126, 1},
+   {128, 15000},
+   {130, 2},
+   {132, 25000},
+   {134, 3},
+   {136, 35000},
+   {138, 4},
+   {140, 45000},
+   {142, 5},
+   {144, 55000},
+   {146, 6},
+   {148, 65000},
+   {150, 7},
+   {152, 75000},
+   {154, 8},
+   {156, 85000},
+   {158, 9},
+   {160, 95000},
+   {162, 10},
+   {163, 105000},
+   {165, 11},
+   {167, 115000},
+   {169, 12},
+   {171, 125000},
+   {TSADCV3_DATA_MASK, 125000},
+};
+
 static u32 rk_tsadcv2_temp_to_code(long temp)
 {
int high, low, mid;
@@ -227,16 +267,83 @@ static int rk_tsadcv2_code_to_temp(u32 code, int *temp)
return 0;
 }
 
+static u32 rk_tsadcv3_temp_to_code(long temp)
+{
+   int high, low, mid;
+
+   low = 0;
+   high = ARRAY_SIZE(v3_code_table) - 1;
+   mid = (high + low) / 2;
+
+   if (temp < v3_code_table[low].temp || temp > v3_code_table[high].temp)
+   return 0;
+
+   while (low <= high) {
+   if (temp == v3_code_table[mid].temp)
+   return v3_code_table[mid].code;
+   else if (temp < v3_code_table[mid].temp)
+   high = mid - 1;
+   else
+   low = mid + 1;
+   mid = (low + high) / 2;
+   }
+
+   return 0;
+}
+
+static int rk_tsadcv3_code_to_temp(u32 code, int *temp)
+{
+   unsigned int low = 1;
+   unsigned int high = ARRAY_SIZE(v3_code_table) - 1;
+   unsigned int mid = (low + high) / 2;
+   unsigned int num;
+   unsigned long denom;
+
+   BUILD_BUG_ON(ARRAY_SIZE(v3_code_table) < 2);
+
+   code &= TSADCV3_DATA_MASK;
+   if (code < v3_code_table[low].code)
+   return -EAGAIN; /* Incorrect reading */
+
+   while (low <= high) {
+   if (code >= v3_code_table[mid - 1].code &&
+   code < v3_code_table[mid].code)
+  

[PATCH 4/5] arm64: dts: Add main Thermal info to rk3368.dtsi

[Caesar Wang]

This patch add the thermal needed info on RK3368.
Meanwhile, support the trips to throttle for thermal.

Signed-off-by: Caesar Wang 
---

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a712bea..71d7793 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "rockchip,rk3368";
@@ -123,6 +124,8 @@
reg = <0x0 0x0>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+
+   #cooling-cells = <2>; /* min followed by max */
};
 
cpu_l1: cpu@1 {
@@ -155,6 +158,8 @@
reg = <0x0 0x100>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
+
+   #cooling-cells = <2>; /* min followed by max */
};
 
cpu_b1: cpu@101 {
@@ -404,6 +409,25 @@
status = "disabled";
};
 
+   thermal-zones {
+   #include "rk3368-thermal.dtsi"
+   };
+
+   tsadc: tsadc@ff28 {
+   compatible = "rockchip,rk3368-tsadc";
+   reg = <0x0 0xff28 0x0 0x100>;
+   interrupts = ;
+   clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+   clock-names = "tsadc", "apb_pclk";
+   resets = <&cru SRST_TSADC>;
+   reset-names = "tsadc-apb";
+   pinctrl-names = "default";
+   pinctrl-0 = <&otp_out>;
+   #thermal-sensor-cells = <1>;
+   rockchip,hw-tshut-temp = <95000>;
+   status = "disabled";
+   };
+
gmac: ethernet@ff29 {
compatible = "rockchip,rk3368-gmac";
reg = <0x0 0xff29 0x0 0x1>;
@@ -829,6 +853,12 @@
};
};
 
+   tsadc {
+   otp_out: otp-out {
+   rockchip,pins = <0 10 RK_FUNC_1 
&pcfg_pull_none>;
+   };
+   };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/5] dt-bindings: thermal: Support the RK3368 SoCs compatible

[Caesar Wang]

This patchset attempts to new compatible for thermal founding
on RK3368 SoCs.

Signed-off-by: Caesar Wang 
---

 Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..52682db 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -1,7 +1,9 @@
 * Temperature Sensor ADC (TSADC) on rockchip SoCs
 
 Required properties:
-- compatible : "rockchip,rk3288-tsadc"
+- compatible : should be "rockchip,-tsadc"
+   "rockchip,rk3288-tsadc": found on RK3288 SoCs
+   "rockchip,rk3368-tsadc": found on RK3368 SoCs
 - reg : physical base address of the controller and length of memory mapped
region.
 - interrupts : The interrupt number to the cpu. The interrupt specifier format
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 0/5] Support the thermal for RK3368 SoCs

[Caesar Wang]

This series patchs are working for RK3368 on Rockchip platform.

This patchset are based on linus master branch.
(Note: add Dmitry two thermal patchs for rockchip
 https://patchwork.kernel.org/patch/6973101/
 https://patchwork.kernel.org/patch/6973131/
)

the git log oneline as follows:

30451f4 arm64: dts: Enable the Thermal on R88 board.
1637a7c arm64: dts: Add main Thermal info to rk3368.dtsi
8f908b7 arm64: dts: Add the thermal data found on RK3368
a501fad thermal: rockchip: Support the RK3368 SoCs in thermal driver
c765254 dt-bindings: thermal: Support the RK3368 SoCs compatible
ff7fd5d thermal: rockhip: fix setting thermal shutdown polarity
f54373c thermal: rockchip: fix handling of invalid readings
0410a40 arm64: dts: rockchip: Add the needed timer for RK3368 SoC
f696cac arm64: Enable the timer on Rockchip architecture
e84d626 clocksource: rockchip: Make the driver more readability and compatible
1f93e4a Linux 4.3-rc2
.

@Heiko,
The PATCH [4/5] is working based on big/littel cluster cpufreq added.
Anyway, the PATCH [4/5] also work for next kernel.

@Eduardo,

The PATCH[2/4] is based on the Dmitry's patchs.

 https://patchwork.kernel.org/patch/6973101/
 https://patchwork.kernel.org/patch/6973131/

---
This series are tested on RK3368 board.

while true;do ls >/dev/null; done&

while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;date;sleep .5;
done &

You can get the temperature form sensors.

/sys/class/thermal/thermal_zone0/temp:27500
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:3
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:27500
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:3
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:25000
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:32500
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:3
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:22500
/sys/class/thermal/thermal_zone1/temp:32500
/sys/class/thermal/thermal_zone0/temp:25000
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:25000
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:22500
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:3
/sys/class/thermal/thermal_zone1/temp:32500
/sys/class/thermal/thermal_zone0/temp:25000
/sys/class/thermal/thermal_zone1/temp:32500
/sys/class/thermal/thermal_zone0/temp:32500
/sys/class/thermal/thermal_zone1/temp:3
/sys/class/thermal/thermal_zone0/temp:25000
/sys/class/thermal/thermal_zone1/temp:32500



Caesar Wang (5):
  dt-bindings: thermal: Support the RK3368 SoCs compatible
  thermal: rockchip: Support the RK3368 SoCs in thermal driver
  arm64: dts: Add the thermal data found on RK3368
  arm64: dts: Add main Thermal info to rk3368.dtsi
  arm64: dts: Enable the Thermal on R88 board

 .../bindings/thermal/rockchip-thermal.txt  |   4 +-
 arch/arm64/boot/dts/rockchip/rk3368-r88.dts|   6 +
 arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi   | 112 
 arch/arm64/boot/dts/rockchip/rk3368.dtsi   |  30 +++
 drivers/thermal/rockchip_thermal.c | 201 ++---
 5 files changed, 327 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi

-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..eeb9ec9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7938,6 +7938,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -8039,6 +8047,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 591 +
 3 files changed, 600 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..df9ed4f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,12 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   tristate "Altera PCIe controller"
+   depends on ARCH_SOCFPGA || NIOS2
+   select PCI_DOMAINS
+   help
+ Say Y here if you want to enable PCIe controller support for Altera
+ SoCFPGA family of SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..41cd4fd
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,591 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define A2P_ADDR_MAP_LO0   0x1000
+#define A2P_ADDR_MAP_HI0   0x1004
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xF
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xF
+#define RP_LTSSM   0x3C64
+#define LTSSM_L0   0xF
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1D
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag)(((reqid) << 16) | (tag << 8) | 
0xF)
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_COMPL_STATUS(hdr)  (((hdr) & 0xE0) >> 13)
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   500
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
+
+   if ((linkcap & PCI_

Re: [PATCH 3/3] arm64: dts: add dts file for Marvell Berlin4CT STB board

[Jisheng Zhang]

On Sun, 20 Sep 2015 21:06:19 +0200
Sebastian Hesselbarth  wrote:

> On 18.09.2015 15:47, Jisheng Zhang wrote:
> > This patch adds dts for the Berlin4CT STB reference board which is also
> > based on the Berlin4CT SoC. The Berlin4CT DMP board will be deprecated as
> > time goes.
> >
> > Signed-off-by: Jisheng Zhang 
> > ---
> >   arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 66 
> > +++
> 
> This is missing the corresponding Makefile change to add the
> board to the default dtb build list.

oops, sorry, I missed it.

> 
> I've fixed it up and
> 
> Applied the two dts patches to berlin64/dt

Thanks a lot ;)

> 
> Sebastian
> 
> >   1 file changed, 66 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> >
> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts 
> > b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> > new file mode 100644
> > index 000..348c37e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> > @@ -0,0 +1,66 @@
> > +/*
> > + * Copyright (C) 2015 Marvell Technology Group Ltd.
> > + *
> > + * Author: Jisheng Zhang 
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPLv2 or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > + * included in all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "berlin4ct.dtsi"
> > +
> > +/ {
> > +   model = "Marvell BG4CT STB board";
> > +   compatible = "marvell,berlin4ct-stb", "marvell,berlin4ct", 
> > "marvell,berlin";
> > +
> > +   chosen {
> > +   stdout-path = "serial0:115200n8";
> > +   };
> > +
> > +   memory {
> > +   device_type = "memory";
> > +   /* the first 16MB is for firmwares' usage */
> > +   reg = <0 0x0100 0 0x7f00>;
> > +   };
> > +};
> > +
> > +&uart0 {
> > +   status = "okay";
> > +};
> >
> 

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index be648eb..bd42530 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += local.h
 generic-y += local64.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 310 +
 3 files changed, 319 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index df9ed4f..0da697e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -153,4 +153,12 @@ config PCIE_ALTERA
  Say Y here if you want to enable PCIe controller support for Altera
  SoCFPGA family of SoCs.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera SocFPGA SoC.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..667421c
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, u32 value, u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(unsigned int irq, struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_data_get_irq_chip_data(data);
+   phys_addr_t addr = msi->vector_phy + (d

[PATCH v7 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..53ad2388
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller = <1>;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..4440db1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs" or "txs": TX slave port region
+   "Cra" or "cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..08e4462 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v7 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 7th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Lorenzo Pieralisi in v6 and minor fixes.

This patchset is based on v4.3-rc1.

v6->v7 changes:
-pcie-altera: add pcie_bus_configure_settings()
-pcie-altera: update comment
-pcie-altera: merge tlp_write_packet_unaligned and tlp_write_packet_aligned
-pcie-altera: pass in NULL for iobase for of_pci_get_host_bridge_resources
-pcie-altera: remove pcie->root_bus_nr = 0

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238
[v6]: https://lkml.org/lkml/2015/9/1/177

Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  16 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 310 +++
 drivers/pci/host/pcie-altera.c | 591 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1015 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 0/5] usb: change clock information for chipidea

[Peter Chen]

This patch set changes usb clock information for legacy i.mx platforms.
At these platforms, they needs three clocks to let controller work.

Hi Fabio,

Would you please have a test at imx27 and imx25 boards, thanks.

Changes for v3:
- Delete property "needs-three-clocks", and using of_device_id->data
  to differentiate platforms
- change  #v3.19+ to  #v4.1+

Changes for v2:
- Add imx25 & imx27 dts change
- Add Fabio's tested-by and Cc:  #v3.19+
- Some typo and commit description

Peter Chen (5):
  doc: dt-binding: ci-hdrc-usb2: split vendor specific properties
  ARM: dts: imx27.dtsi: change the clock information for usb
  ARM: dts: imx25.dtsi: change the clock information for usb
  ARM: dts: imx35.dtsi: change the clock information for usb
  usb: chipidea: imx: refine clock operations to adapt for all platforms

 .../devicetree/bindings/usb/ci-hdrc-usb2.txt   |  10 +-
 arch/arm/boot/dts/imx25.dtsi   |   8 +-
 arch/arm/boot/dts/imx27.dtsi   |  16 ++-
 arch/arm/boot/dts/imx35.dtsi   |   8 +-
 drivers/usb/chipidea/ci_hdrc_imx.c | 156 ++---
 5 files changed, 164 insertions(+), 34 deletions(-)

-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/2] irqchip/gicv3-its: Handle OF device tree "msi-map" properties.

[Rob Herring]

On Fri, Sep 18, 2015 at 12:54 PM, David Daney  wrote:
> On 09/18/2015 01:51 AM, Marc Zyngier wrote:
>>
>> On Thu, 17 Sep 2015 11:00:59 -0700
>> David Daney  wrote:
>>
>> Hi David,
>>
>>> From: David Daney 
>>>
>>> Search up the device hierarchy to find devices with a "msi-map"
>>> property, if found apply the mapping to the GIC device id.

[...]

>>> +   masked_devid = msi_mask & dev_alias.dev_id;
>>> +   matched = false;
>>> +   while (msi_map_len >= 4 * sizeof(__be32)) {
>>> +   rid_base = be32_to_cpup(msi_map + 0);
>>> +   phandle = be32_to_cpup(msi_map + 1);
>>> +   msi_base = be32_to_cpup(msi_map + 2);
>>> +   rid_len = be32_to_cpup(msi_map + 3);
>>
>>
>> Ouch. I wonder if that kind of thing should deserve a generic helper.
>> of_property_read_u32_array_from_index()? Rob, what do you think?
>
>
> I think it is possible to add too many wrapper functions.  IMO, this is not
> too unreadable.

Given you are not reading into an array, I don't think a new helper
would help. You could just use of_property_read_u32_index though.

Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 0/2] arm64: dts: qcom: 8x16: UARTDM additions

[Andy Gross]

On Fri, Sep 18, 2015 at 04:18:52PM +0300, Ivan T. Ivanov wrote:
> Hi,
> 
> This is second version of the changes previously posted [1].
> I have to rebase them on top of Andy's for-next[2] branch and rework them
> a little bit, because some of the definitions have been already merged.
> 
> Regards,
> Ivan
> 
> [1] https://lkml.org/lkml/2015/9/12/114
> [2] https://www.codeaurora.org/cgit/quic/kernel/agross-msm/

Thanks!  I have these applied.

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 4/5] ARM: dts: imx35.dtsi: change the clock information for usb

[Peter Chen]

For imx35, it needs three clocks to let the controller work,
the old code is wrong, and the usbmisc does not include
clock handling code any more.

Signed-off-by: Peter Chen 
---
 arch/arm/boot/dts/imx35.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e6540b5..5b887d0 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -305,7 +305,8 @@
compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>;
interrupts = <37>;
-   clocks = <&clks 73>;
+   clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
@@ -315,7 +316,8 @@
compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>;
interrupts = <35>;
-   clocks = <&clks 73>;
+   clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
@@ -325,8 +327,6 @@
usbmisc: usbmisc@53ff4600 {
#index-cells = <1>;
compatible = "fsl,imx35-usbmisc";
-   clocks = <&clks 9>, <&clks 73>, <&clks 28>;
-   clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>;
};
};
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 2/5] ARM: dts: imx27.dtsi: change the clock information for usb

[Peter Chen]

For imx27, it needs three clocks to let the controller work,
the old code is wrong, and usbmisc has not included clock handling
code any more. Without this patch, it will cause below data
abort when accessing usbmisc registers.

usbcore: registered new interface driver usb-storage
Unhandled fault: external abort on non-linefetch (0x008) at 0xf4424600
pgd = c0004000
[f4424600] *pgd=1452(bad)
Internal error: : 8 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.1.0-next-20150701-dirty #3089
Hardware name: Freescale i.MX27 (Device Tree Support)
task: c7832b60 ti: c783e000 task.ti: c783e000
PC is at usbmisc_imx27_init+0x4c/0xbc
LR is at usbmisc_imx27_init+0x40/0xbc
pc : []lr : []psr: 6093
sp : c783fe08  ip :   fp : 
r10: c0576434  r9 : 009c  r8 : c7a773a0
r7 : 0100  r6 : 6013  r5 : c7a776f0  r4 : c7a773f0
r3 : f4424600  r2 :   r1 : 0001  r0 : 0001
Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 0005317f  Table: a0004000  DAC: 0017
Process swapper (pid: 1, stack limit = 0xc783e190)
Stack: (0xc783fe08 to 0xc784)

Signed-off-by: Peter Chen 
Reported-by: Fabio Estevam 
Tested-by: Fabio Estevam 
Cc:  #v4.1+
---
 arch/arm/boot/dts/imx27.dtsi | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index feb9d34..f818ea4 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -486,7 +486,10 @@
compatible = "fsl,imx27-usb";
reg = <0x10024000 0x200>;
interrupts = <56>;
-   clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
+   clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
+   <&clks IMX27_CLK_USB_AHB_GATE>,
+   <&clks IMX27_CLK_USB_DIV>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
@@ -495,7 +498,10 @@
compatible = "fsl,imx27-usb";
reg = <0x10024200 0x200>;
interrupts = <54>;
-   clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
+   clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
+   <&clks IMX27_CLK_USB_AHB_GATE>,
+   <&clks IMX27_CLK_USB_DIV>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
@@ -505,7 +511,10 @@
compatible = "fsl,imx27-usb";
reg = <0x10024400 0x200>;
interrupts = <55>;
-   clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
+   clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
+   <&clks IMX27_CLK_USB_AHB_GATE>,
+   <&clks IMX27_CLK_USB_DIV>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
@@ -515,7 +524,6 @@
#index-cells = <1>;
compatible = "fsl,imx27-usbmisc";
reg = <0x10024600 0x200>;
-   clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
};
 
sahara2: sahara@10025000 {
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 5/5] usb: chipidea: imx: refine clock operations to adapt for all platforms

[Peter Chen]

Some i.mx platforms need three clocks to let controller work, but
others only need one, refine clock operation to adapt for all
platforms, it fixes a regression found at i.mx27.

Signed-off-by: Peter Chen 
Tested-by: Fabio Estevam 
Cc:  #v4.1+
---
 drivers/usb/chipidea/ci_hdrc_imx.c | 156 -
 1 file changed, 138 insertions(+), 18 deletions(-)

diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c 
b/drivers/usb/chipidea/ci_hdrc_imx.c
index 6ccbf60..6ec0fbc 100644
--- a/drivers/usb/chipidea/ci_hdrc_imx.c
+++ b/drivers/usb/chipidea/ci_hdrc_imx.c
@@ -32,6 +32,10 @@ static const struct ci_hdrc_imx_platform_flag imx27_usb_data 
= {
CI_HDRC_DISABLE_STREAMING,
 };
 
+static const struct ci_hdrc_imx_platform_flag imx31_usb_data = {
+   CI_HDRC_DISABLE_STREAMING,
+};
+
 static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
.flags = CI_HDRC_IMX28_WRITE_FIX |
CI_HDRC_TURN_VBUS_EARLY_ON |
@@ -68,6 +72,13 @@ static const struct ci_hdrc_imx_platform_flag imx7d_usb_data 
= {
 static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
{ .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
{ .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
+   { .compatible = "fsl,imx25-usb", .data = &imx27_usb_data},
+   { .compatible = "fsl,imx35-usb", .data = &imx27_usb_data},
+   { .compatible = "fsl,imx23-usb", .data = &imx31_usb_data},
+   { .compatible = "fsl,imx31-usb", .data = &imx31_usb_data},
+   { .compatible = "fsl,imx50-usb", .data = &imx31_usb_data},
+   { .compatible = "fsl,imx51-usb", .data = &imx31_usb_data},
+   { .compatible = "fsl,imx53-usb", .data = &imx31_usb_data},
{ .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
{ .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
{ .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data},
@@ -77,6 +88,15 @@ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, ci_hdrc_imx_dt_ids);
 
+static inline bool imx_needs_three_clocks
+   (const struct ci_hdrc_imx_platform_flag *imx_platform_flag)
+{
+   if (imx_platform_flag == &imx27_usb_data)
+   return true;
+
+   return false;
+}
+
 struct ci_hdrc_imx_data {
struct usb_phy *phy;
struct platform_device *ci_pdev;
@@ -84,6 +104,12 @@ struct ci_hdrc_imx_data {
struct imx_usbmisc_data *usbmisc_data;
bool supports_runtime_pm;
bool in_lpm;
+   /* SoC before i.mx6 (except imx23/imx28) needs three clks */
+   bool need_three_clks;
+   struct clk *clk_ipg;
+   struct clk *clk_ahb;
+   struct clk *clk_per;
+   /* - */
 };
 
 /* Common functions shared by usbmisc drivers */
@@ -135,6 +161,105 @@ static struct imx_usbmisc_data 
*usbmisc_get_init_data(struct device *dev)
 }
 
 /* End of common functions shared by usbmisc drivers*/
+static int imx_get_clks(struct device *dev)
+{
+   struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
+   int ret = 0;
+
+   if (data->need_three_clks) {
+   data->clk_ipg = devm_clk_get(dev, "ipg");
+   if (IS_ERR(data->clk_ipg)) {
+   ret = PTR_ERR(data->clk_ipg);
+   dev_err(dev,
+   "Failed to get ipg clock, err=%d\n", ret);
+   return ret;
+   }
+
+   data->clk_ahb = devm_clk_get(dev, "ahb");
+   if (IS_ERR(data->clk_ahb)) {
+   ret = PTR_ERR(data->clk_ahb);
+   dev_err(dev,
+   "Failed to get ahb clock, err=%d\n", ret);
+   return ret;
+   }
+
+   data->clk_per = devm_clk_get(dev, "per");
+   if (IS_ERR(data->clk_per)) {
+   ret = PTR_ERR(data->clk_per);
+   dev_err(dev,
+   "Failed to get per clock, err=%d\n", ret);
+   return ret;
+   }
+   } else {
+   data->clk = devm_clk_get(dev, NULL);
+   if (IS_ERR(data->clk)) {
+   ret = PTR_ERR(data->clk);
+   dev_err(dev,
+   "Failed to get clock, err=%d\n", ret);
+   return ret;
+   }
+   }
+
+   return ret;
+}
+
+static int imx_prepare_enable_clks(struct device *dev)
+{
+   struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
+   int ret = 0;
+
+   if (data->need_three_clks) {
+   ret = clk_prepare_enable(data->clk_ipg);
+   if (ret) {
+   dev_err(dev,
+   "Failed to prepare/enable ipg clk, err=%d\n",
+   ret);
+   return ret;
+   }
+
+   ret = clk_prepare_enable(dat

[PATCH v3 1/5] doc: dt-binding: ci-hdrc-usb2: split vendor specific properties

[Peter Chen]

Each vendor may have its specific properties, they are not belonged
to common optional properties, split them from common's.

Signed-off-by: Peter Chen 
---
 Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt 
b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
index 77946f5..27dc705 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
@@ -27,10 +27,6 @@ Optional properties:
 - vbus-supply: reference to the VBUS regulator
 - maximum-speed: limit the maximum connection speed to "full-speed".
 - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
-- fsl,usbmisc: (FSL only) phandler of non-core register device, with one
-  argument that indicate usb controller index
-- disable-over-current: (FSL only) disable over current detect
-- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
 - itc-setting: interrupt threshold control register control, the setting
   should be aligned with ITC bits at register USBCMD.
 - ahb-burst-config: it is vendor dependent, the required value should be
@@ -54,6 +50,12 @@ Optional properties:
 - phy-clkgate-delay-us: the delay time (us) between putting the PHY into
   low power mode and gating the PHY clock.
 
+i.mx specific properties
+- fsl,usbmisc: phandler of non-core register device, with one
+  argument that indicate usb controller index
+- disable-over-current: disable over current detect
+- external-vbus-divider: enables off-chip resistor divider for Vbus
+
 Example:
 
usb@f7ed {
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 3/5] ARM: dts: imx25.dtsi: change the clock information for usb

[Peter Chen]

For imx25, it needs three clocks to let the controller work,
the old code is wrong, and usbmisc has not included clock
handling code any more.

Signed-off-by: Peter Chen 
---
 arch/arm/boot/dts/imx25.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 677f81d..ab843bd 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -493,7 +493,8 @@
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>;
interrupts = <37>;
-   clocks = <&clks 70>;
+   clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
@@ -503,7 +504,8 @@
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>;
interrupts = <35>;
-   clocks = <&clks 70>;
+   clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+   clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
@@ -512,8 +514,6 @@
usbmisc: usbmisc@53ff4600 {
#index-cells = <1>;
compatible = "fsl,imx25-usbmisc";
-   clocks = <&clks 9>, <&clks 70>, <&clks 8>;
-   clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>;
};
 
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: Please suggest proper format for DT properties.

[Rob Herring]

On Fri, Sep 18, 2015 at 5:36 PM, Constantine Shulyupin
 wrote:
> Hi,
>
> I am designing DT support for a hwmon chip.
> It has some sensors, each of them can be:
>  - "disabled"
>  - "thermal diode"
>  - "thermistor"
>  - "voltage"
>
> Four possible options for DT properties format.
>
> Option 1: Separated property for each sensor.
>
> Example nct7802 node:
>
> nct7802 {
> compatible = "nuvoton,nct7802";
> reg = <0x2a>;
> nuvoton,sensor1-type = "thermistor";
> nuvoton,sensor2-type = "disabled";
> nuvoton,sensor3-type = "voltage";
> };
>
> Option 2: Array of strings for all sensors.
>
> nct7802 {
> compatible = "nuvoton,nct7802";
> reg = <0x2a>;
> nuvoton,sensors-types = "thermistor", "disabled", "voltage";
> };

It seems you are just listing out all possible modes. Why do you need
this in the DT at all? This can be inferred by the compatible string.

>
> Option 3: Sets of 4 cells.
>
>   Borrowed from marvell,reg-init and broadcom,c45-reg-init.
>
>   The first cell is the page address,
>   the second a register address within the page,
>   the third cell contains a mask to be ANDed with the existing register
>   value, and the fourth cell is ORed with the result to yield the
>   new register value. If the third cell has a value of zero,
>   no read of the existing value is performed.

I don't see how this relates to the first 2 options. The register you
write selects the mode? In general, we don't want bindings of just
random register writes.

Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH] ARM: at91/dt: ov2640: add hsync/vsync-active property

[Josh Wu]

Hi, Nicolas

On 9/18/2015 10:09 PM, Nicolas Ferre wrote:

Le 18/09/2015 13:28, Josh Wu a écrit :

On at91sam9x5ek/at91sam9m10g45ek/sama5d3xek boards, we use the parallel
connection for ov2640. So we must set the hsync/vsync property (1 means
active high).
Otherwise, the connection would be seen as BT.656 or BT.1120.

Signed-off-by: Josh Wu 

Hi Josh,

Does this patch apply because of the new enhancement that you had
proposed in "media: atmel-isi: parse the DT parameters for
vsync/hsync/pixclock polarity" or does it apply even before?
Is it a fix that applies to older kernels?

It's is a fix, according to the dt binding of video interface.
So it should be applied before:

"media: atmel-isi: parse the DT parameters for
vsync/hsync/pixclock polarity".


it has no impact in older kernel as the driver doesn't parse that 
property yet.




So, should I wait for the enhancements to enter media git tree or can I
take them anyway?


yes, you can take it without waiting for the media tree. Thanks.

Best Regards,
Josh Wu



Bye,


---

  arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 ++
  arch/arm/boot/dts/at91sam9x5ek.dtsi| 2 ++
  arch/arm/boot/dts/sama5d3xmb.dtsi  | 2 ++
  3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts 
b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index d1ae60a..9d16ef8 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -198,6 +198,8 @@
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
+   vsync-active = <1>;
+   hsync-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi 
b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index d237c46..479f200 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -66,6 +66,8 @@
isi_0: endpoint@0 {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
+   vsync-active = <1>;
+   hsync-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi 
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 83bee7a..8901042 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -87,6 +87,8 @@
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
+   vsync-active = <1>;
+   hsync-active = <1>;
};
};
};





--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v5 07/23] regulator: core: Remove regulator_list

[Russell King - ARM Linux]

On Sat, Sep 19, 2015 at 08:01:29AM -0700, Mark Brown wrote:
> On Thu, Sep 17, 2015 at 02:57:01PM +0200, Tomeu Vizoso wrote:
> > As we are already registering a device with regulator_class for each
> > regulator device, regulator_list is redundant and can be replaced with
> > calls to class_find_device() and class_for_each_device().
> 
> This appears to leak references to the struct devices returned by
> class_find_device() - it takes a reference before it returns so any
> device found using class_find_device() needs to be released with
> put_device() and I don't see any new put_device() calls in here.

When I've been fiding exactly that kind of bug in the PHY code, I've
been adding comments to the docbook function header detailing the
requirement to balance the reference.  IMHO, this is a good idea,
because the more places that get it with these APIs, the more likely
people are to potentially read it.

The comment I've been putting in the phy code is:

 * If successful, returns a pointer to the phy_device with the embedded
 * struct device refcount incremented by one, or NULL on failure. The
 * refcount must be dropped by calling phy_disconnect() or phy_detach().

which even goes as far as telling people how they should be dropping
the reference.  So there should be no excuse (ignorance is not an
excuse for this!)

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 2/2] input: gpio_keys_polled: Add support for abs/rel axis

[Hans de Goede]

Hi,

Dmitry Torokhov wrote:

> > + for_each_set_bit(i, input->relbit, REL_CNT) {
> > + if (!test_bit(i, bdev->rel_axis_seen))
> > + input_event(input, EV_REL, i, 0);
> > + }
>
> I wonder if this should be written as
>
>for_each_set_bit(i, bdev->rel_axis_seen, REL_CNT)
>input_event(input, EV_REL, i, 0);
>
> i.e. the 2nd bit test is not really needed because we should not see
> unsupported bits in "seen" axes.

Yes that makes sense, I'll make this change, re-test and post a new version.

> > + if (fwnode_property_read_u32(child, "linux,input-value",
> > +  (u32 *)&button->value))
> > + button->value = 1;
>
> Umm, we need negative values too... but there is no
> fwnode_property_read_s32 :(. We need to document in the bindings that
> value is treated as signed so that users can still achieve the needed
> effect.

Right, I was looking how to deal with this, and the generic fwnode
interface has no s32 version, but the devicetree  linux/of.h code has:

static inline int of_property_read_s32(const struct device_node *np,
   const char *propname,
   s32 *out_value)
{
return of_property_read_u32(np, propname, (u32*) out_value);
}

So this seemed like the best way to deal with this. You're right that
the devicetree binding docs should explicitly state that negative
numbers are allowed though, I will update the dt-bindings doc
patch accordingly.

Regards,

Hans

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 5/5] arm64: dts: berlin4ct: add the pinctrl node and muxing setup for uart0

[Sebastian Hesselbarth]

On 19.09.2015 12:02, Jisheng Zhang wrote:

Add the avio, soc, sm pinctrl nodes for Marvell berlin4ct SoC. This
patch also adds urt0 txd and rxd muxing setup in the dtsi because uart0
always use them to work, no other possibilities.


Please split the patch into two:
one adding the pinctrl nodes and
one adding the default pinmux to uart0 node.


Signed-off-by: Jisheng Zhang 
---
  arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 27 +++
  1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi 
b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
index a3b5f1d..4566e4e 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
@@ -225,6 +225,16 @@
};
};

+   soc_pinctrl: pinctrl@ea8000 {
+   compatible = "marvell,berlin4ct-soc-pinctrl";
+   reg = <0xea8000 0x14>;
+   };
+
+   avio_pinctrl: pinctrl@ea8400 {
+   compatible = "marvell,berlin4ct-avio-pinctrl";
+   reg = <0xea8400 8>;


s/8/0x8/


+   };
+
apb@fc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -278,6 +288,23 @@
clocks = <&osc>;
reg-shift = <2>;
status = "disabled";
+   pinctrl-0 = <&urt0_txd_pmux>, <&urt0_rxd_pmux>;
+   pinctrl-names = "default", "default";


pinctrl-names = "default", "default"; refers to pinctrl-0 and pinctrl-1
respectively. There is no pinctrl-1, so please remove the second
pinctrl-names element.


+   };
+   };
+
+   sm_pinctrl: pinctrl@fe2200 {
+   compatible = "marvell,berlin4ct-sm-pinctrl";
+   reg = <0xfe2200 0xc>;
+
+   urt0_txd_pmux: urt0_txd-pmux {
+   groups = "SM_URT0_TXD";
+   function = "sm_urt0_txd";
+   };
+
+   urt0_rxd_pmux: urt0_rxd-pmux {
+   groups = "SM_URT0_RXD";
+   function = "sm_urt0_rxd";


If you change the driver to generic function names ("uart0") this
boils down to a single

uart0_pmux: uart0-pmux {
groups = "SM_UART0_TXD", "SM_UART0_RXD";
function = "uart0";
};

pinmux node and the reference in uart0 node to

pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";

Sebastian


};
};
};



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/5] pinctrl: berlin: add the berlin4ct pinctrl driver

[Sebastian Hesselbarth]

On 19.09.2015 12:02, Jisheng Zhang wrote:

Add the pin-controller driver for Marvell Berlin BG4CT SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.

Signed-off-by: Jisheng Zhang 
---

[...]

diff --git a/drivers/pinctrl/berlin/berlin4ct.c 
b/drivers/pinctrl/berlin/berlin4ct.c
new file mode 100644
index 000..2960e16
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin4ct.c
@@ -0,0 +1,503 @@
+/*
+ * Marvell berlin4ct pinctrl driver

[...]

+static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = {
+   BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
+   BERLIN_PINCTRL_FUNCTION(0x0, "emmc_rstn"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "gpio47")),


Jisheng,

I am fine with naming the groups after the 0x0 function but
the functions themselves should be named after a generic
name, e.g. "emmc" instead of "emmc_rstn".

That will allow to add pinmux nodes like

uart_pmx {
groups = "SM_UART0_TXD", "SM_UART0_RXD";
function = "uart0";
};

instead of two separate nodes like in patch 5/5.

You should however keep the actual pin function e.g. in a comment
after the function define above:

BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RESETn */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),/* GPIO47 */


+   BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
+   BERLIN_PINCTRL_FUNCTION(0x0, "nand_io0"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "rgmii_rxd0"),
+   BERLIN_PINCTRL_FUNCTION(0x2, "sd1_clk"),
+   BERLIN_PINCTRL_FUNCTION(0x3, "gpio0")),

[...]

+   BERLIN_PINCTRL_GROUP("SD0_CLK", 0x4, 0x3, 0x12,
+   BERLIN_PINCTRL_FUNCTION(0x0, "gpio29"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "sd0_clk"),
+   BERLIN_PINCTRL_FUNCTION(0x2, "sts4_clk"),


Please find a better name for "sts" whatever it is for.


+   BERLIN_PINCTRL_FUNCTION(0x5, "v4g_dbg8"),


ditto for "v4g"


+   BERLIN_PINCTRL_FUNCTION(0x7, "phy_dbg8")),

[...]

+   BERLIN_PINCTRL_GROUP("SCRD0_RST", 0xc, 0x3, 0x06,
+   BERLIN_PINCTRL_FUNCTION(0x0, "gpio15"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "scrd0_rst"),


ditto for "scrd0"


+   BERLIN_PINCTRL_FUNCTION(0x3, "sd1a_clk")),
+   BERLIN_PINCTRL_GROUP("SCRD0_DCLK", 0xc, 0x3, 0x09,
+   BERLIN_PINCTRL_FUNCTION(0x0, "gpio16"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "scrd0_dclk"),
+   BERLIN_PINCTRL_FUNCTION(0x3, "sd1a_cmd")),


What is the "a" for in "sd1a" ? There is a "sd1b" below so I
guess that there is two pinmux groups that mux sd1?


+   BERLIN_PINCTRL_GROUP("SCRD0_GPIO0", 0xc, 0x3, 0x0c,
+   BERLIN_PINCTRL_FUNCTION(0x0, "gpio17"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "scrd0_gpio0"),
+   BERLIN_PINCTRL_FUNCTION(0x2, "sif_dio"),


What kind of interface is "sif" ?


+   BERLIN_PINCTRL_FUNCTION(0x3, "sd1a_dat0")),

[...]

+static const struct berlin_desc_group berlin4ct_soc_aviopinctrl_groups[] = {
+   BERLIN_PINCTRL_GROUP("TX_EDDC_SCL", 0x0, 0x3, 0x00,
+   BERLIN_PINCTRL_FUNCTION(0x0, "avio_gpio0"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc_scl"),
+   BERLIN_PINCTRL_FUNCTION(0x2, "tw1_scl")),
+   BERLIN_PINCTRL_GROUP("TX_EDDC_SDA", 0x0, 0x3, 0x03,
+   BERLIN_PINCTRL_FUNCTION(0x0, "avio_gpio1"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc_sda"),
+   BERLIN_PINCTRL_FUNCTION(0x2, "tw1_sda")),
+   BERLIN_PINCTRL_GROUP("I2S1_LRCKO", 0x0, 0x3, 0x06,
+   BERLIN_PINCTRL_FUNCTION(0x0, "avio_gpio2"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "i2s1_lrcko"),
+   BERLIN_PINCTRL_FUNCTION(0x3, "sts6_clk"),
+   BERLIN_PINCTRL_FUNCTION(0x4, "adac_dbg0"),
+   BERLIN_PINCTRL_FUNCTION(0x6, "sd1b_clk"),
+   BERLIN_PINCTRL_FUNCTION(0x7, "avio_dbg0")),

[...]

+static const struct berlin_desc_group berlin4ct_sysmgr_pinctrl_groups[] = {
+   BERLIN_PINCTRL_GROUP("SM_TW2_SCL", 0x0, 0x3, 0x00,
+   BERLIN_PINCTRL_FUNCTION(0x0, "sm_gpio19"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "sm_tw2_scl")),


I'd say, remove the "sm_" prefix for all of the SM functions if
there is no collusion with any of the other functions.


+   BERLIN_PINCTRL_GROUP("SM_TW2_SDA", 0x0, 0x3, 0x03,
+   BERLIN_PINCTRL_FUNCTION(0x0, "sm_gpio20"),
+   BERLIN_PINCTRL_FUNCTION(0x1, "sm_tw2_sda")),
+   BERLIN_PINCTRL_GROUP("SM_TW3_SCL", 0x0, 0x3, 0x06,
+   BERLIN_PINCTRL_FUNCTION(0x0, "sm_gpio21"),

Re: [PATCH 1/3] arm64: berlin: enable ARCH_REQUIRE_GPIOLIB

[Sebastian Hesselbarth]

On 18.09.2015 15:47, Jisheng Zhang wrote:

All berlin SoCs have GPIOs driven by the dwapb GPIO driver. Add GPIOLIB
as a dependency to be able to support them.

Signed-off-by: Jisheng Zhang 


Applied to berlin64/soc.

Thanks,
  Sebastian


---
  arch/arm64/Kconfig.platforms | 1 +
  1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 23800a1..c6e2c75 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -7,6 +7,7 @@ config ARCH_BCM_IPROC

  config ARCH_BERLIN
bool "Marvell Berlin SoC Family"
+   select ARCH_REQUIRE_GPIOLIB
select DW_APB_ICTL
help
  This enables support for Marvell Berlin SoC Family



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 3/3] arm64: dts: add dts file for Marvell Berlin4CT STB board

[Sebastian Hesselbarth]

On 18.09.2015 15:47, Jisheng Zhang wrote:

This patch adds dts for the Berlin4CT STB reference board which is also
based on the Berlin4CT SoC. The Berlin4CT DMP board will be deprecated as
time goes.

Signed-off-by: Jisheng Zhang 
---
  arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 66 +++


This is missing the corresponding Makefile change to add the
board to the default dtb build list.

I've fixed it up and

Applied the two dts patches to berlin64/dt

Sebastian


  1 file changed, 66 insertions(+)
  create mode 100644 arch/arm64/boot/dts/marvell/berlin4ct-stb.dts

diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts 
b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
new file mode 100644
index 000..348c37e
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2015 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "berlin4ct.dtsi"
+
+/ {
+   model = "Marvell BG4CT STB board";
+   compatible = "marvell,berlin4ct-stb", "marvell,berlin4ct", 
"marvell,berlin";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   /* the first 16MB is for firmwares' usage */
+   reg = <0 0x0100 0 0x7f00>;
+   };
+};
+
+&uart0 {
+   status = "okay";
+};



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v5 3/4] devicetree: add SGX Sensortech vendor id

[Jonathan Cameron]

On 14/09/15 04:26, Matt Ranostay wrote:
> Signed-off-by: Matt Ranostay 
Applied. Note there was fuzz in my tree as I am lagging mainline
somewhat.  However it is pretty obvious how to fix up merge
issues in this file so lets not worry about that ;)

Jonathan
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
> b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index ac5f0c3..281e8f0 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -191,6 +191,7 @@ sbs   Smart Battery System
>  schindlerSchindler
>  seagate  Seagate Technology PLC
>  semtech  Semtech Corporation
> +sgx  SGX Sensortech
>  sharpSharp Corporation
>  sil  Silicon Image
>  silabs   Silicon Laboratories
> 

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v5 1/4] iio: chemical: Add IIO_CONCENTRATION channel type

[Jonathan Cameron]

On 14/09/15 04:26, Matt Ranostay wrote:
> There are air quality sensors that report data back in parts per million
> of VOC (Volatile Organic Compounds) which are usually indexed from CO2
> or another common pollutant.
> 
> This patchset adds an IIO_CONCENTRATION type that returns a percentage
> of substance because no other channels types fit this use case.
> Modifiers for IIO_MOD_CO2 and IIO_MOD_VOC gas types are defined.
> 
> Signed-off-by: Matt Ranostay 
Applied to the togreg branch of iio.git - initially pushed out as
testing for the autobuilders to play with it.

Thanks,

Jonathan
> ---
>  Documentation/ABI/testing/sysfs-bus-iio | 11 +++
>  drivers/iio/industrialio-core.c |  3 +++
>  include/uapi/linux/iio/types.h  |  3 +++
>  3 files changed, 17 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio 
> b/Documentation/ABI/testing/sysfs-bus-iio
> index 42d360f..682c070 100644
> --- a/Documentation/ABI/testing/sysfs-bus-iio
> +++ b/Documentation/ABI/testing/sysfs-bus-iio
> @@ -1459,3 +1459,14 @@ Description:
>   measurements and return the average value as output data. Each
>   value resulted from [_name]_oversampling_ratio 
> measurements
>   is considered as one sample for 
> [_name]_sampling_frequency.
> +
> +What:/sys/bus/iio/devices/iio:deviceX/in_concentration_raw
> +What:/sys/bus/iio/devices/iio:deviceX/in_concentrationX_raw
> +What:
> /sys/bus/iio/devices/iio:deviceX/in_concentration_co2_raw
> +What:
> /sys/bus/iio/devices/iio:deviceX/in_concentrationX_co2_raw
> +What:
> /sys/bus/iio/devices/iio:deviceX/in_concentration_voc_raw
> +What:
> /sys/bus/iio/devices/iio:deviceX/in_concentrationX_voc_raw
> +KernelVersion:   4.3
> +Contact: linux-...@vger.kernel.org
> +Description:
> + Raw (unscaled no offset etc.) percentage reading of a substance.
> diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
> index b3fcc2c..8eb6064 100644
> --- a/drivers/iio/industrialio-core.c
> +++ b/drivers/iio/industrialio-core.c
> @@ -75,6 +75,7 @@ static const char * const iio_chan_type_name_spec[] = {
>   [IIO_ENERGY] = "energy",
>   [IIO_DISTANCE] = "distance",
>   [IIO_VELOCITY] = "velocity",
> + [IIO_CONCENTRATION] = "concentration",
>  };
>  
>  static const char * const iio_modifier_names[] = {
> @@ -111,6 +112,8 @@ static const char * const iio_modifier_names[] = {
>   [IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z] = "sqrt(x^2+y^2+z^2)",
>   [IIO_MOD_I] = "i",
>   [IIO_MOD_Q] = "q",
> + [IIO_MOD_CO2] = "co2",
> + [IIO_MOD_VOC] = "voc",
>  };
>  
>  /* relies on pairs of these shared then separate */
> diff --git a/include/uapi/linux/iio/types.h b/include/uapi/linux/iio/types.h
> index 2f8b117..1e4c4e3 100644
> --- a/include/uapi/linux/iio/types.h
> +++ b/include/uapi/linux/iio/types.h
> @@ -35,6 +35,7 @@ enum iio_chan_type {
>   IIO_ENERGY,
>   IIO_DISTANCE,
>   IIO_VELOCITY,
> + IIO_CONCENTRATION,
>  };
>  
>  enum iio_modifier {
> @@ -72,6 +73,8 @@ enum iio_modifier {
>   IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z,
>   IIO_MOD_I,
>   IIO_MOD_Q,
> + IIO_MOD_CO2,
> + IIO_MOD_VOC,
>  };
>  
>  enum iio_event_type {
> 

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v5 2/4] iio: resistance: add IIO_RESISTANCE channel type

[Jonathan Cameron]

On 14/09/15 04:26, Matt Ranostay wrote:
> Signed-off-by: Matt Ranostay 
Applied to the togreg branch of iio.git - initially pushed out as testing for 
the
autobuilders to play with it.

Thanks,

Jonathan
> ---
>  Documentation/ABI/testing/sysfs-bus-iio | 8 
>  drivers/iio/industrialio-core.c | 1 +
>  include/uapi/linux/iio/types.h  | 1 +
>  3 files changed, 10 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio 
> b/Documentation/ABI/testing/sysfs-bus-iio
> index 682c070..a91af51 100644
> --- a/Documentation/ABI/testing/sysfs-bus-iio
> +++ b/Documentation/ABI/testing/sysfs-bus-iio
> @@ -1470,3 +1470,11 @@ KernelVersion: 4.3
>  Contact: linux-...@vger.kernel.org
>  Description:
>   Raw (unscaled no offset etc.) percentage reading of a substance.
> +
> +What:/sys/bus/iio/devices/iio:deviceX/in_resistance_raw
> +What:/sys/bus/iio/devices/iio:deviceX/in_resistanceX_raw
> +KernelVersion:   4.3
> +Contact: linux-...@vger.kernel.org
> +Description:
> + Raw (unscaled no offset etc.) resistance reading that can be 
> processed
> + into an ohm value.
> diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
> index 8eb6064..80439a6 100644
> --- a/drivers/iio/industrialio-core.c
> +++ b/drivers/iio/industrialio-core.c
> @@ -76,6 +76,7 @@ static const char * const iio_chan_type_name_spec[] = {
>   [IIO_DISTANCE] = "distance",
>   [IIO_VELOCITY] = "velocity",
>   [IIO_CONCENTRATION] = "concentration",
> + [IIO_RESISTANCE] = "resistance",
>  };
>  
>  static const char * const iio_modifier_names[] = {
> diff --git a/include/uapi/linux/iio/types.h b/include/uapi/linux/iio/types.h
> index 1e4c4e3..7c63bd6 100644
> --- a/include/uapi/linux/iio/types.h
> +++ b/include/uapi/linux/iio/types.h
> @@ -36,6 +36,7 @@ enum iio_chan_type {
>   IIO_DISTANCE,
>   IIO_VELOCITY,
>   IIO_CONCENTRATION,
> + IIO_RESISTANCE,
>  };
>  
>  enum iio_modifier {
> 

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH RESEND 0/2] arm: dts: berlin: use stdout-path

[Sebastian Hesselbarth]

On 14.09.2015 08:42, Jisheng Zhang wrote:

These two simple patches use stdout-path to specify the console.
The first patch add aliases for serial uarts. The second patch
removes the console argument from the command line, uses stdout-path
instead.

Jisheng Zhang (2):
   arm: dts: berlin: add aliases for serial
   arm: dts: berlin: use stdout-path


Applied to berlin/dt.

Thanks,
  Sebastian


  arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts| 3 ++-
  arch/arm/boot/dts/berlin2.dtsi| 6 ++
  arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 3 ++-
  arch/arm/boot/dts/berlin2cd.dtsi  | 5 +
  arch/arm/boot/dts/berlin2q-marvell-dmp.dts| 3 ++-
  arch/arm/boot/dts/berlin2q.dtsi   | 5 +
  6 files changed, 22 insertions(+), 3 deletions(-)



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [linux-sunxi] Re: [PATCH 5/5] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Hans de Goede]

Hi,

On 09/20/2015 11:14 AM, Hans de Goede wrote:

Hi,

On 09/20/2015 10:46 AM, Chen-Yu Tsai wrote:

On Sun, Sep 20, 2015 at 8:30 PM, Hans de Goede  wrote:

All A13 based q8 formfactor tablets use the same backlight setup, add
a backlight devicetree node for controlling the backlight on these devices.

Signed-off-by: Hans de Goede 
---
  arch/arm/boot/dts/sun5i-q8-common.dtsi | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi 
b/arch/arm/boot/dts/sun5i-q8-common.dtsi
index 0641d68..76a5204 100644
--- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi
@@ -41,11 +41,22 @@
   */
  #include "sunxi-q8-common.dtsi"

+#include 
+
  / {
 aliases {
 serial0 = &uart1;
 };

+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+   default-brightness-level = <8>;
+   /* TODO: backlight uses axp gpio1 as enable pin */
+   /* TODO: backlight is powered by AXP209 DCDC1SW */


There's no DCDC1SW on AXP209. The reference design shows the backlight
regulator is powered directly from IPSOUT,


Ah, right, I'll do a v2 dropping this comment line.

 > but the PWM pullup is powered

by LCD-VCC,  which itself is enabled by AXP209 GPIO0.

Would that be the case, or maybe closer, given we don't have schematics?


gpio0 needs to be driven high to get the backlight to lite up, that
is pretty much all I know.


Correction, gpio1. I guess that pullup is only there to keep the backlight
off while the pwm pin is still muxed as input, rather then pwm-output.

Regards,

Hans
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Hans de Goede]

All A13 based q8 formfactor tablets use the same backlight setup, add
a backlight devicetree node for controlling the backlight on these devices.

Signed-off-by: Hans de Goede 
---
Changes in v2:
-Drop the comment about DCDC1SW, the axp209 used on A13 boards does not
 have a DCDC1SW
---
 arch/arm/boot/dts/sun5i-q8-common.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi 
b/arch/arm/boot/dts/sun5i-q8-common.dtsi
index 0641d68..a78e189 100644
--- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi
@@ -41,11 +41,21 @@
  */
 #include "sunxi-q8-common.dtsi"
 
+#include 
+
 / {
aliases {
serial0 = &uart1;
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+   default-brightness-level = <8>;
+   /* TODO: backlight uses axp gpio1 as enable pin */
+   };
+
chosen {
stdout-path = "serial0:115200n8";
};
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [linux-sunxi] Re: [PATCH 5/5] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Hans de Goede]

Hi,

On 09/20/2015 10:46 AM, Chen-Yu Tsai wrote:

On Sun, Sep 20, 2015 at 8:30 PM, Hans de Goede  wrote:

All A13 based q8 formfactor tablets use the same backlight setup, add
a backlight devicetree node for controlling the backlight on these devices.

Signed-off-by: Hans de Goede 
---
  arch/arm/boot/dts/sun5i-q8-common.dtsi | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi 
b/arch/arm/boot/dts/sun5i-q8-common.dtsi
index 0641d68..76a5204 100644
--- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi
@@ -41,11 +41,22 @@
   */
  #include "sunxi-q8-common.dtsi"

+#include 
+
  / {
 aliases {
 serial0 = &uart1;
 };

+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+   default-brightness-level = <8>;
+   /* TODO: backlight uses axp gpio1 as enable pin */
+   /* TODO: backlight is powered by AXP209 DCDC1SW */


There's no DCDC1SW on AXP209. The reference design shows the backlight
regulator is powered directly from IPSOUT,


Ah, right, I'll do a v2 dropping this comment line.

> but the PWM pullup is powered

by LCD-VCC,  which itself is enabled by AXP209 GPIO0.

Would that be the case, or maybe closer, given we don't have schematics?


gpio0 needs to be driven high to get the backlight to lite up, that
is pretty much all I know.

Regards,

Hans

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 5/5] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Chen-Yu Tsai]

On Sun, Sep 20, 2015 at 8:30 PM, Hans de Goede  wrote:
> All A13 based q8 formfactor tablets use the same backlight setup, add
> a backlight devicetree node for controlling the backlight on these devices.
>
> Signed-off-by: Hans de Goede 
> ---
>  arch/arm/boot/dts/sun5i-q8-common.dtsi | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi 
> b/arch/arm/boot/dts/sun5i-q8-common.dtsi
> index 0641d68..76a5204 100644
> --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
> +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi
> @@ -41,11 +41,22 @@
>   */
>  #include "sunxi-q8-common.dtsi"
>
> +#include 
> +
>  / {
> aliases {
> serial0 = &uart1;
> };
>
> +   backlight: backlight {
> +   compatible = "pwm-backlight";
> +   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
> +   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> +   default-brightness-level = <8>;
> +   /* TODO: backlight uses axp gpio1 as enable pin */
> +   /* TODO: backlight is powered by AXP209 DCDC1SW */

There's no DCDC1SW on AXP209. The reference design shows the backlight
regulator is powered directly from IPSOUT, but the PWM pullup is powered
by LCD-VCC, which itself is enabled by AXP209 GPIO0.

Would that be the case, or maybe closer, given we don't have schematics?


Regards
ChenYu

> +   };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> --
> 2.4.3
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 resend 0/2] power: Add an axp20x-usb-power driver

[Hans de Goede]

Hi,

This is a resend of v4 of the axp20x-usb-power power-supply driver,
after v4 there have been no further comments, so I assume that this
version is ready for merging, yet for some reason it has not been
merged yet.

Can we please get this driver merged (preferably into 4.3, but if
not at least lets get it into next / 4.4 asap).

Regards,

Hans

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 resend 1/2] ARM: dts: Add binding documentation for AXP20x pmic usb power supply

[Hans de Goede]

Add binding documentation for the usb power supply part of the AXP20x pmic.

Signed-off-by: Hans de Goede 
---
Changes in v2:
-Split out into a separate patch from the actual driver commit
Changes in v4:
-s/usb_power_supply/usb-power-supply/ in the dts example code
---
 .../bindings/power_supply/axp20x_usb_power.txt | 34 ++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/power_supply/axp20x_usb_power.txt

diff --git 
a/Documentation/devicetree/bindings/power_supply/axp20x_usb_power.txt 
b/Documentation/devicetree/bindings/power_supply/axp20x_usb_power.txt
new file mode 100644
index 000..862f4a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/axp20x_usb_power.txt
@@ -0,0 +1,34 @@
+AXP20x USB power supply
+
+Required Properties:
+-compatible: "x-powers,axp202-usb-power-supply"
+
+This node is a subnode of the axp20x PMIC.
+
+Example:
+
+axp209: pmic@34 {
+   compatible = "x-powers,axp209";
+   reg = <0x34>;
+   interrupt-parent = <&nmi_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   regulators {
+   x-powers,dcdc-freq = <1500>;
+
+   vdd_cpu: dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <145>;
+   regulator-name = "vdd-cpu";
+   };
+
+   ...
+   };
+
+   usb-power-supply: usb-power-supply {
+   compatible = "x-powers,axp202-usb-power-supply";
+   };
+};
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 resend 2/2] power: Add an axp20x-usb-power driver

[Hans de Goede]

This adds a driver for the usb power_supply bits of the axp20x PMICs.

I initially started writing my own driver, before coming aware of
Bruno Prémont's excellent earlier RFC with a driver for this.

My driver was lacking CURRENT_MAX and VOLTAGE_MIN support Bruno's
drvier has, so I've copied the code for those from his driver.

Note that the AC-power-supply and battery charger bits will need separate
drivers. Each one needs its own devictree child-node so that other
devicetree nodes can reference the right power-supply, and thus each one
will get its own mfd-cell / platform_device and platform-driver.

Cc: Bruno Prémont 
Acked-by: Lee Jones 
Signed-off-by: Bruno Prémont 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Split out the dt-bindings documentation into a separate patch
-Renamed axp20x_read_16bit to axp20x_read_variable_width
-Use better local variable names inside axp20x_read_variable_width
Changes in v3:
-Add Bruno's S-o-b
Changes in v4:
-Check that parent drv data is not NULL
-Replace "r" local variable with a "ret" variable
---
 drivers/power/Kconfig|   7 ++
 drivers/power/Makefile   |   1 +
 drivers/power/axp20x_usb_power.c | 248 +++
 include/linux/mfd/axp20x.h   |  24 
 4 files changed, 280 insertions(+)
 create mode 100644 drivers/power/axp20x_usb_power.c

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index f8758d6..914167e 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -472,6 +472,13 @@ config CHARGER_RT9455
help
  Say Y to enable support for Richtek RT9455 battery charger.
 
+config AXP20X_POWER
+   tristate "AXP20x power supply driver"
+   depends on MFD_AXP20X
+   help
+ This driver provides support for the power supply features of
+ AXP20x PMIC.
+
 source "drivers/power/reset/Kconfig"
 
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 5752ce8..fb4413e 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_ADC_BATTERY)   += generic-adc-battery.o
 
 obj-$(CONFIG_PDA_POWER)+= pda_power.o
 obj-$(CONFIG_APM_POWER)+= apm_power.o
+obj-$(CONFIG_AXP20X_POWER) += axp20x_usb_power.o
 obj-$(CONFIG_MAX8925_POWER)+= max8925_power.o
 obj-$(CONFIG_WM831X_BACKUP)+= wm831x_backup.o
 obj-$(CONFIG_WM831X_POWER) += wm831x_power.o
diff --git a/drivers/power/axp20x_usb_power.c b/drivers/power/axp20x_usb_power.c
new file mode 100644
index 000..421a90b
--- /dev/null
+++ b/drivers/power/axp20x_usb_power.c
@@ -0,0 +1,248 @@
+/*
+ * AXP20x PMIC USB power supply status driver
+ *
+ * Copyright (C) 2015 Hans de Goede 
+ * Copyright (C) 2014 Bruno Prémont 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRVNAME "axp20x-usb-power-supply"
+
+#define AXP20X_PWR_STATUS_VBUS_PRESENT BIT(5)
+#define AXP20X_PWR_STATUS_VBUS_USEDBIT(4)
+
+#define AXP20X_USB_STATUS_VBUS_VALID   BIT(2)
+
+#define AXP20X_VBUS_VHOLD_uV(b)(400 + (((b) >> 3) & 7) * 
10)
+#define AXP20X_VBUS_CLIMIT_MASK3
+#define AXP20X_VBUC_CLIMIT_900mA   0
+#define AXP20X_VBUC_CLIMIT_500mA   1
+#define AXP20X_VBUC_CLIMIT_100mA   2
+#define AXP20X_VBUC_CLIMIT_NONE3
+
+#define AXP20X_ADC_EN1_VBUS_CURR   BIT(2)
+#define AXP20X_ADC_EN1_VBUS_VOLT   BIT(3)
+
+#define AXP20X_VBUS_MON_VBUS_VALID BIT(3)
+
+struct axp20x_usb_power {
+   struct regmap *regmap;
+   struct power_supply *supply;
+};
+
+static irqreturn_t axp20x_usb_power_irq(int irq, void *devid)
+{
+   struct axp20x_usb_power *power = devid;
+
+   power_supply_changed(power->supply);
+
+   return IRQ_HANDLED;
+}
+
+static int axp20x_usb_power_get_property(struct power_supply *psy,
+   enum power_supply_property psp, union power_supply_propval *val)
+{
+   struct axp20x_usb_power *power = power_supply_get_drvdata(psy);
+   unsigned int input, v;
+   int ret;
+
+   switch (psp) {
+   case POWER_SUPPLY_PROP_VOLTAGE_MIN:
+   ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
+   if (ret)
+   return ret;
+
+   val->intval = AXP20X_VBUS_VHOLD_uV(v);
+   return 0;
+   case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+   ret = axp20x_read_variable_width(power->regmap,
+AXP20X_VBUS_V_ADC_H, 12);
+   if (ret < 0)
+   return ret;
+
+   val->intval = ret * 1700; /* 1 step = 1.7 mV */
+

[PATCH 4/5] ARM: dts: sun8i: Add pwm-backlight device for A23/A33 Q8 format tablets

[Hans de Goede]

From: Chen-Yu Tsai 

The LCD backlight on the A23/A33 Q8 format tablets is enabled
with a GPIO controlled regulator, and brightness controlled with
the SoC's PWM controller.

The backlight is powered from the AXP223 PMIC's DC1SW output,
which is not supported yet. A proper bootloader is required
to enable it.

The brightness levels are arbitrary. The FEX files do not have
such information. As such, actual brightness levels may differ
from device to device.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Hans de Goede 
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 6f8a8bb..f342736 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -41,11 +41,24 @@
  */
 #include "sunxi-q8-common.dtsi"
 
+#include 
+
 / {
aliases {
serial0 = &r_uart;
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pinctrl-names = "default";
+   pinctrl-0 = <&bl_en_pin_q8>;
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+   default-brightness-level = <8>;
+   enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+   /* backlight is powered by AXP223 DC1SW */
+   };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -62,6 +75,13 @@
 };
 
 &pio {
+   bl_en_pin_q8: bl_en_pin@0 {
+   allwinner,pins = "PH6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
mmc0_cd_pin_q8: mmc0_cd_pin@0 {
allwinner,pins = "PB4";
allwinner,function = "gpio_in";
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 0/5] ARM: dts: sunxi: Add backlight node to q8 tablets

[Hans de Goede]

Hi Maxime, Chen-Yu,

Here is a slightly updated version of Chen-Yu's backlight
patches, also adding support for the backlight found on A13 
based q8 tablets.

This series is based on mripard/sunxi/for-next with the following
patches on top (Maxime you've send mails indicating that you've merged
these alread, but you seem to have not pushed them yet) :

ARM: dts: sun5i: Add sun5i-q8-common.dtsi
ARM: dts: sun5i: Add dts file for q8 formfactor a13 based tablets
ARM: dts: sun8i: Add PWM controller node for A23/A33
ARM: dts: sun8i: Add PWM channel 0 pinmux setting for A23/A33

As discussed I've changed the "ARM: dts: sunxi: Enable PWM controller
on Q8 format tablets" patch to enable the pwm node in sunxi-q8-common.h
rather then in sunx8i-q8-common.h, other then that the 2 patches from
Chen-Yu are unchanged.

Regards,

Hans



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 3/5] ARM: dts: sunxi: Enable PWM controller on Q8 format tablets

[Hans de Goede]

From: Chen-Yu Tsai 

Q8 format tablets use channel 0 of the PWM controller for backlight dimming.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Enable the pwm controller in sunxi-q8-common.dtsi rather then in
 sun8i-q8-common.dtsi
---
 arch/arm/boot/dts/sunxi-q8-common.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-q8-common.dtsi 
b/arch/arm/boot/dts/sunxi-q8-common.dtsi
index 17b26ff..b824146 100644
--- a/arch/arm/boot/dts/sunxi-q8-common.dtsi
+++ b/arch/arm/boot/dts/sunxi-q8-common.dtsi
@@ -75,3 +75,9 @@
voltage = <40>;
};
 };
+
+&pwm {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm0_pins>;
+   status = "okay";
+};
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 2/5] ARM: dts: sun5i: Add PWM channel 0 pinmux setting for A13/A10s

[Hans de Goede]

Add a pinmux setting for the first pwm channel. This is often used for
backlight dimming on tablets.

Signed-off-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 5e036a4..f0714d3 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -529,6 +529,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   pwm0_pins: pwm0 {
+   allwinner,pins = "PB2";
+   allwinner,function = "pwm";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
 
timer@01c20c00 {
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/5] ARM: dts: sun5i: Add PWM controller node for A13/A10s

[Hans de Goede]

The sun5i die has a PWM controller that is compatible to the one on the A20.
Add a device node for it.

Signed-off-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 78b993a..5e036a4 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -543,6 +543,14 @@
reg = <0x01c20c90 0x10>;
};
 
+   pwm: pwm@01c20e00 {
+   compatible = "allwinner,sun7i-a20-pwm";
+   reg = <0x01c20e00 0xc>;
+   clocks = <&osc24M>;
+   #pwm-cells = <3>;
+   status = "disabled";
+   };
+
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 5/5] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Hans de Goede]

All A13 based q8 formfactor tablets use the same backlight setup, add
a backlight devicetree node for controlling the backlight on these devices.

Signed-off-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i-q8-common.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi 
b/arch/arm/boot/dts/sun5i-q8-common.dtsi
index 0641d68..76a5204 100644
--- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi
@@ -41,11 +41,22 @@
  */
 #include "sunxi-q8-common.dtsi"
 
+#include 
+
 / {
aliases {
serial0 = &uart1;
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
+   brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+   default-brightness-level = <8>;
+   /* TODO: backlight uses axp gpio1 as enable pin */
+   /* TODO: backlight is powered by AXP209 DCDC1SW */
+   };
+
chosen {
stdout-path = "serial0:115200n8";
};
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 1/3] mfd: axp20x: Rename supply names for AXP221 DC1SW and DC5LDO regulators

[Chen-Yu Tsai]

Hi Lee,

On Sun, Sep 20, 2015 at 12:17 PM, Lee Jones  wrote:
> On Wed, 16 Sep 2015, Chen-Yu Tsai wrote:
>
>> The DC1SW and DC5LDO regulators in the AXP221 are internally chained
>> to DCDC1 and DCDC5, hence the names. The original bindings used the
>> parent regulator names for the supply regulator property. This causes
>> some confusion when we actually use it in the dts:
>>
>>   axp221 {
>>   /* self supplying? */
>>   dcdc1-supply = <&dcdc1>;
>>   dcdc5-supply = <&dcdc5>;
>>
>>   dcdc1: dcdc1 {
>>   ...
>>   };
>>
>>   dcdc5: dcdc5 {
>>   ...
>>   };
>>   };
>>
>> Change them to the downstream regulator names, or "dc1sw" and "dc5ldo"
>> respectively.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  Documentation/devicetree/bindings/mfd/axp20x.txt | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Applied, thanks.

Mark (in his reply) has a point. If these are internally connect, we
should just remove them from the bindings, and associate them in the
driver.

I'm looking into this. In the mean time, could you drop this one?

Thanks
ChenYu

>> diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
>> b/Documentation/devicetree/bindings/mfd/axp20x.txt
>> index 41811223e5be..8e79252b1e7c 100644
>> --- a/Documentation/devicetree/bindings/mfd/axp20x.txt
>> +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
>> @@ -60,8 +60,8 @@ DCDC2   : DC-DC buck: vin2-supply
>>  DCDC3: DC-DC buck: vin3-supply
>>  DCDC4: DC-DC buck: vin4-supply
>>  DCDC5: DC-DC buck: vin5-supply
>> -DC1SW: On/Off Switch : dcdc1-supply  : DCDC1 
>> secondary output
>> -DC5LDO   : LDO   : dcdc5-supply  : input from 
>> DCDC5
>> +DC1SW: On/Off Switch : dc1sw-supply  : DCDC1 
>> secondary output
>> +DC5LDO   : LDO   : dc5ldo-supply : input from 
>> DCDC5
>>  ALDO1: LDO   : aldoin-supply : shared supply
>>  ALDO2: LDO   : aldoin-supply : shared supply
>>  ALDO3: LDO   : aldoin-supply : shared supply
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads

[Markus Pargmann]

Hi,

On Fri, Sep 18, 2015 at 11:29:54AM -0500, Adrian Alonso wrote:
> Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
> 
> Signed-off-by: Adrian Alonso 
> ---
> Changes for V2: Resend
> Changes for V3: Resend
> Changes for V4: Resend
> 
>  arch/arm/boot/dts/imx7d-sdb.dts | 15 +++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
> index 8059458..c8a178c 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -419,3 +419,18 @@
>  
>   };
>  };
> +
> +&iomuxc_lpsr {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog_2>;
> +
> + imx7d-sdb {
> + pinctrl_hog_2: hoggrp-2 {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14
> + MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59
> + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74

I think this belong to the watchdog node.

Also some comments for the GPIOs may probably be nice to know what they
are for.

Regards,

Markus

> + >;
> + };
> + };
> +};
> -- 
> 2.1.4
> 
> 
> 

-- 
Pengutronix e.K.   | |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |


signature.asc
Description: Digital signature