Re: [PATCH v2 3/5] misc: eeprom_93xx46: Implement eeprom_93xx46 DT bindings.

[Cory Tusar]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 11/19/2015 09:00 AM, Andrew F. Davis wrote:
> On 11/18/2015 11:50 PM, Vladimir Zapolskiy wrote:
>> Hi Cory,
>>
>> On 19.11.2015 05:29, Cory Tusar wrote:
>>> This commit implements bindings in the eeprom_93xx46 driver allowing
>>> device word size and read-only attributes to be specified via
>>> devicetree.
>>>
>>> Signed-off-by: Cory Tusar 

[snip]

>>> +error_free:
>>> +devm_kfree(&spi->dev, pd);
>>> +return ret;
>>> +}
>>> +
>>> +#else
>>> +static inline int eeprom_93xx46_probe_dt(struct spi_device *spi)
>>> +{
>>> +return 0;
>>> +}
>>> +#endif
>>> +
>>
>> I actually don't see a point to have #ifdef CONFIG_OF here.
>>
> 
> Usually to avoid a lot of dead code and data when OF is not enabled.

Hi Andrew,

I tend to agree, but I'm going to cross-check by building a couple
variants of this to see just how much gets optimized out automagically
when using Vladimir's suggestions.

>> Instead please add a check for !spi->dev.of_node at the beginning of
>> eeprom_93xx46_probe_dt() or in .probe()
>>
>>>   static int eeprom_93xx46_probe(struct spi_device *spi)
>>>   {
>>>   struct eeprom_93xx46_platform_data *pd;
>>>   struct eeprom_93xx46_dev *edev;
>>>   int err;
>>>
>>> +err = eeprom_93xx46_probe_dt(spi);
>>> +if (err < 0)
>>> +return err;
>>> +
>>>   pd = spi->dev.platform_data;
>>>   if (!pd) {
>>>   dev_err(&spi->dev, "missing platform data\n");
>>> @@ -370,6 +431,7 @@ static int eeprom_93xx46_remove(struct spi_device *spi)
>>>   static struct spi_driver eeprom_93xx46_driver = {
>>>   .driver = {
>>>   .name= "93xx46",
>>> +.of_match_table = eeprom_93xx46_of_table,
>>>   },
>>>   .probe= eeprom_93xx46_probe,
>>>   .remove= eeprom_93xx46_remove,
>>>


- -- 
Cory Tusar
Principal
PID 1 Solutions, Inc.


"There are two ways of constructing a software design.  One way is to
 make it so simple that there are obviously no deficiencies, and the
 other way is to make it so complicated that there are no obvious
 deficiencies."  --Sir Charles Anthony Richard Hoare

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Re: [PATCH v2 3/5] misc: eeprom_93xx46: Implement eeprom_93xx46 DT bindings.

[Cory Tusar]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 11/19/2015 12:50 AM, Vladimir Zapolskiy wrote:
> Hi Cory,
> 
> On 19.11.2015 05:29, Cory Tusar wrote:
>> This commit implements bindings in the eeprom_93xx46 driver allowing
>> device word size and read-only attributes to be specified via
>> devicetree.
>>
>> Signed-off-by: Cory Tusar 
>> ---
>>  drivers/misc/eeprom/eeprom_93xx46.c | 62 
>> +
>>  1 file changed, 62 insertions(+)
>>
>> diff --git a/drivers/misc/eeprom/eeprom_93xx46.c 
>> b/drivers/misc/eeprom/eeprom_93xx46.c
>> index e1bf0a5..1f29d9a 100644
>> --- a/drivers/misc/eeprom/eeprom_93xx46.c
>> +++ b/drivers/misc/eeprom/eeprom_93xx46.c
>> @@ -13,6 +13,8 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -294,12 +296,71 @@ static ssize_t eeprom_93xx46_store_erase(struct device 
>> *dev,
>>  }
>>  static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
>>  
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id eeprom_93xx46_of_table[] = {
>> +{ .compatible = "eeprom-93xx46", },
>> +{}
>> +};
>> +MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
>> +
> 
> Please move this declaration closer to struct spi_driver
> eeprom_93xx46_driver below.

As Andrew noted in his follow-up, it's used in the function immediately
after this declaration.  Seems logical to leave it here?

> Also you can avoid #ifdef here, if you write
> 
>.of_match_table = of_match_ptr(eeprom_93xx46_of_table)

Will change this to use of_match_ptr().

> Whenever possible please avoid #ifdef's in .c files.

Agreed.  #ifdef CONFIG_OF still seems to be fairly pervasive though...?

>> +static int eeprom_93xx46_probe_dt(struct spi_device *spi)
>> +{
>> +struct device_node *np = spi->dev.of_node;
>> +struct eeprom_93xx46_platform_data *pd;
>> +u32 tmp;
>> +int ret;
>> +
>> +if (!of_match_device(eeprom_93xx46_of_table, &spi->dev))
>> +return 0;
>> +
>> +pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
>> +if (!pd)
>> +return -ENOMEM;
>> +
>> +ret = of_property_read_u32(np, "data-size", &tmp);
>> +if (ret < 0) {
>> +dev_err(&spi->dev, "data-size property not found\n");
>> +goto error_free;
> 
> Because you use devm_* resource allocation in .probe, just return error.

Will fix.

> Plus I would suggest to change "data-size" property to an optional one,
> here I mean that if it is omitted, then by default consider pd->flags |=
> EE_ADDR8.

I don't see such an assumption as safe...data word size is an inherent
property of the device (or the way it's strapped on a given platform),
and should be required for proper operation.

>> +}
>> +
>> +if (tmp == 8) {
>> +pd->flags |= EE_ADDR8;
>> +} else if (tmp == 16) {
>> +pd->flags |= EE_ADDR16;
>> +} else {
>> +dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
>> +goto error_free;
> 
> Same here.

Will fix.

>> +}
>> +
>> +if (of_property_read_bool(np, "read-only"))
>> +pd->flags |= EE_READONLY;
>> +
>> +spi->dev.platform_data = pd;
>> +
>> +return 1;
> 
> On success please return 0.

Fixed.

>> +error_free:
>> +devm_kfree(&spi->dev, pd);
>> +return ret;
>> +}
>> +
>> +#else
>> +static inline int eeprom_93xx46_probe_dt(struct spi_device *spi)
>> +{
>> +return 0;
>> +}
>> +#endif
>> +
> 
> I actually don't see a point to have #ifdef CONFIG_OF here.
> 
> Instead please add a check for !spi->dev.of_node at the beginning of
> eeprom_93xx46_probe_dt() or in .probe()

How about...

if (IS_ENABLED(CONFIG_OF) && spi->dev.of_node) {
err = eeprom_93xx46_probe_dt(spi);
if (err < 0)
return err;
}

...at the beginning of eeprom_93xx46_probe() (as below)?

>>  static int eeprom_93xx46_probe(struct spi_device *spi)
>>  {
>>  struct eeprom_93xx46_platform_data *pd;
>>  struct eeprom_93xx46_dev *edev;
>>  int err;
>>  
>> +err = eeprom_93xx46_probe_dt(spi);
>> +if (err < 0)
>> +return err;
>> +
>>  pd = spi->dev.platform_data;
>>  if (!pd) {
>>  dev_err(&spi->dev, "missing platform data\n");
>> @@ -370,6 +431,7 @@ static int eeprom_93xx46_remove(struct spi_device *spi)
>>  static struct spi_driver eeprom_93xx46_driver = {
>>  .driver = {
>>  .name   = "93xx46",
>> +.of_match_table = eeprom_93xx46_of_table,
>>  },
>>  .probe  = eeprom_93xx46_probe,
>>  .remove = eeprom_93xx46_remove,
>>


- -- 
Cory Tusar
Principal
PID 1 Solutions, Inc.


"There are two ways of constructing a software design.  One way is to
 make it so simple that there are obviously no deficiencies, and the
 other way is to make it so complicated that there are no obvious
 deficiencies."  --Sir Charles Anthony Richard Hoare

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Re: [PATCH v12 0/3] Mediatek xHCI support

[chunfeng yun]

Hi,
On Fri, 2015-11-20 at 13:20 +0200, Mathias Nyman wrote:
> On 17.11.2015 11:18, Chunfeng Yun wrote:
> >  From 577f68d9c0ca1531d5f9cae0dcbea2ba116c8551 Mon Sep 17 00:00:00 2001
> > From: Chunfeng Yun 
> > Date: Tue, 17 Nov 2015 17:09:05 +0800
> > Subject: [PATCH v12 0/3] Mediatek xHCI support
> >
> > The patch supports MediaTek's xHCI controller.
> >
> > There are some differences from xHCI spec:
> > 1. The interval is specified in 250 * 8ns increments for Interrupt 
> > Moderation
> > Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times 
> > as
> > much as that defined in xHCI spec.
> >
> > 2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
> > number of packets that remain to be transferred for a TD after processing 
> > all
> > Max packets in all previous TRBs,that means don't include the current TRB's,
> > but in xHCI spec it includes the current ones.
> >
> > 3. To minimize the scheduling effort for synchronous endpoints in xHC, the 
> > MTK
> > architecture defines some extra SW scheduling parameters for HW. According 
> > to
> > these parameters provided by SW, the xHC can easily decide whether a
> > synchronous endpoint should be scheduled in a specific uFrame. The extra SW
> > scheduling parameters are put into reserved DWs in Slot and Endpoint 
> > Context.
> > And a bandwidth scheduler algorithm is added to support such feature.
> >
> > A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
> > supports two usb2.0 ports and one usb3.0 port.
> >
> 
> Added to my tree, I'll send it forward to Greg shortly
> 
> Fixed the documentation "wakeup_deb_p0" -> "wakeup_deb_p1" typo as well
Thank you very much.
> 
> -Mathias  
> 


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[PATCH] arm: dts: qcom: Add generic PMIC gpio/MPP compat strings

[Stephen Boyd]

Add the generic compatible strings for the PMIC gpio and MPP
modules found on qcom based PMICs.

Cc: 
Cc: "Ivan T. Ivanov" 
Cc: Bjorn Andersson 
Cc: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 6 --
 arch/arm/boot/dts/qcom-pm8841.dtsi  | 2 +-
 arch/arm/boot/dts/qcom-pm8941.dtsi  | 4 ++--
 arch/arm/boot/dts/qcom-pma8084.dtsi | 4 ++--
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 11aca7fb1793..d0670d0ee08c 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -430,7 +430,8 @@
 
pm8921_gpio: gpio@150 {
 
-   compatible = "qcom,pm8921-gpio";
+   compatible = "qcom,pm8921-gpio",
+"qcom,ssbi-gpio";
reg = <0x150>;
interrupts = <192 1>, <193 1>, <194 1>,
 <195 1>, <196 1>, <197 1>,
@@ -454,7 +455,8 @@
};
 
pm8921_mpps: mpps@50 {
-   compatible = "qcom,pm8921-mpp";
+   compatible = "qcom,pm8921-mpp",
+"qcom,ssbi-mpp";
reg = <0x50>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 523bee959f98..9f357f68713c 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -10,7 +10,7 @@
#size-cells = <0>;
 
pm8841_mpps: mpps@a000 {
-   compatible = "qcom,pm8841-mpp";
+   compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
reg = <0xa000 0x400>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi 
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 12c1202ba2ca..64622bd251d1 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -48,7 +48,7 @@
};
 
pm8941_gpios: gpios@c000 {
-   compatible = "qcom,pm8941-gpio";
+   compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio";
reg = <0xc000 0x2400>;
gpio-controller;
#gpio-cells = <2>;
@@ -91,7 +91,7 @@
};
 
pm8941_mpps: mpps@a000 {
-   compatible = "qcom,pm8941-mpp";
+   compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp";
reg = <0xa000 0x800>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi 
b/arch/arm/boot/dts/qcom-pma8084.dtsi
index 10b8f9e6d60b..4e9bd3f88473 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -19,7 +19,7 @@
};
 
pma8084_gpios: gpios@c000 {
-   compatible = "qcom,pma8084-gpio";
+   compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio";
reg = <0xc000 0x1600>;
gpio-controller;
#gpio-cells = <2>;
@@ -48,7 +48,7 @@
};
 
pma8084_mpps: mpps@a000 {
-   compatible = "qcom,pma8084-mpp";
+   compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp";
reg = <0xa000 0x800>;
gpio-controller;
#gpio-cells = <2>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [PATCH v8 1/2] mtd: mtk-nor: mtk serial flash controller driver

[Brian Norris]

On Wed, Nov 18, 2015 at 11:30:02AM +0800, Bayi Cheng wrote:
> add spi nor flash driver for mediatek controller
> 
> Signed-off-by: Bayi Cheng 
> ---
>  drivers/mtd/spi-nor/Kconfig   |   7 +
>  drivers/mtd/spi-nor/Makefile  |   1 +
>  drivers/mtd/spi-nor/mtk-quadspi.c | 486 
> ++
>  3 files changed, 494 insertions(+)
>  create mode 100644 drivers/mtd/spi-nor/mtk-quadspi.c

Looks good now. Thanks! Applied to l2-mtd.git, with a trivial whitespace
fixup.
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Re: [PATCH 2/2] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Felipe Balbi]

Hi,

Tim Bird  writes:
> On 11/16/2015 09:21 AM, Felipe Balbi wrote:
>> 
>> Hi,
>> 
>> Peter Chen  writes:
>>> On Wed, Nov 11, 2015 at 09:48:00AM -0800, Tim Bird wrote:


 On 11/10/2015 07:14 PM, Peter Chen wrote:
> On Tue, Nov 10, 2015 at 04:46:51PM -0800, Tim Bird wrote:
>> This fixes a bug where if you disconnect and re-connect the USB cable,
>> the gadget driver stops working.
>>
>> Add support for async_irq to wake up driver from low power mode.
>> Without this, the power management code never calls resume.
>> Also, have the phy driver kick the gadget driver (chipidea otg)
>> by having the chipidea driver register with it, for vbus connect
>> notifications.
>>
>> Signed-off-by: Tim Bird 
>> ---
>>  drivers/usb/chipidea/udc.c|  6 ++
>>  drivers/usb/phy/phy-msm-usb.c | 16 
>>  include/linux/usb/msm_hsusb.h |  1 +
>>  3 files changed, 23 insertions(+)
>> 
>> I just wanna know how you guys want this to be handled ? Through my tree
>> or chipidea's ? Or do we break the dependencies between the changes ?
>
> I'm fine with splitting it up.  I'm sending a new series with 3 patches
> right after this message.  Do both trees go to linux-next?

I have my fixes and next branches both on next. Not sure about chipidea.

-- 
balbi


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[PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller

[Joshua Henderson]

From: Cristian Birsan 

Document the devicetree bindings for the interrupt controller on Microchip
PIC32 class devices. This also adds a header defining associated interrupts
and related settings.

Signed-off-by: Cristian Birsan 
Signed-off-by: Joshua Henderson 
---
 .../microchip,pic32mz-evic.txt |   65 ++
 .../interrupt-controller/microchip,pic32mz-evic.h  |  238 
 2 files changed, 303 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
 create mode 100644 
include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
 
b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
new file mode 100644
index 000..12fb91f
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
@@ -0,0 +1,65 @@
+Microchip PIC32MZ Interrupt Controller
+==
+
+The Microchip PIC32MZ SOC contains an Enhanced Vectored Interrupt Controller
+(EVIC) version 2. It handles internal and external interrupts and provides
+support for priority, sub-priority, irq type and polarity.
+
+Required properties
+---
+
+- compatible: Should be "microchip,evic-v2"
+
+- reg: specifies physical base address and size of register range.
+
+- interrupt-controller: Identifies the node as an interrupt controller.
+
+- #interrupt cells: Specifies the number of cells used to encode an interrupt
+source connected to this controller. The value shall be 3 and interrupt
+descriptor shall have the following format:
+   
+
+hw_irq - represents the hardware interrupt number as in the data sheet.
+
+irq_priority_and_subpriority - sets the priority and sub-priority for the
+interrupt line. The INT_PRI(pri, subpri) macro can be used to set desired
+values or the DEFAULT_INT_PRI can be used for the default value.
+
+irq_type - is used to describe the type and polarity of an interrupt. For
+internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
+IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
+IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
+
+Example
+---
+
+evic: interrupt-controller@1f81 {
+compatible = "microchip,evic-v2";
+interrupt-controller;
+#interrupt-cells = <3>;
+reg = <0x1f81 0x1000>;
+device_type="evic-v2";
+};
+
+Each device must request his interrupt line with the associated priority and
+polarity
+
+Internal interrupt DTS snippet
+--
+
+device@1f80 {
+   ...
+   interrupt-parent = <&evic>;
+   interrupts = ;
+   ...
+};
+
+External interrupt DTS snippet
+--
+
+device@1f80 {
+   ...
+   interrupt-parent = <&evic>;
+   interrupts = ;
+   ...
+};
diff --git a/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h 
b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
new file mode 100644
index 000..2c466b8
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
@@ -0,0 +1,238 @@
+/*
+ * This header provides constants for the MICROCHIP PIC32 EVIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
+
+#include 
+
+/* Hardware interrupt number */
+#define CORE_TIMER_INTERRUPT 0
+#define CORE_SOFTWARE_INTERRUPT_0 1
+#define CORE_SOFTWARE_INTERRUPT_1 2
+#define EXTERNAL_INTERRUPT_0 3
+#define TIMER1 4
+#define INPUT_CAPTURE_1_ERROR 5
+#define INPUT_CAPTURE_1 6
+#define OUTPUT_COMPARE_1 7
+#define EXTERNAL_INTERRUPT_1 8
+#define TIMER2 9
+#define INPUT_CAPTURE_2_ERROR 10
+#define INPUT_CAPTURE_2 11
+#define OUTPUT_COMPARE_2 12
+#define EXTERNAL_INTERRUPT_2 13
+#define TIMER3 14
+#define INPUT_CAPTURE_3_ERROR 15
+#define INPUT_CAPTURE_3 16
+#define OUTPUT_COMPARE_3 17
+#define EXTERNAL_INTERRUPT_3 18
+#define TIMER4 19
+#define INPUT_CAPTURE_4_ERROR 20
+#define INPUT_CAPTURE_4 21
+#define OUTPUT_COMPARE_4 22
+#define EXTERNAL_INTERRUPT_4 23
+#define TIMER5 24
+#define INPUT_CAPTURE_5_ERROR 25
+#define INPUT_CAPTURE_5 26
+#define OUTPUT_COMPARE_5 27
+#define TIMER6 28
+#define INPUT_CAPTURE_6_ERROR 29
+#define INPUT_CAPTURE_6 30
+#define OUTPUT_COMPARE_6 31
+#define TIMER7 32
+#define INPUT_CAPTURE_7_ERROR 33
+#define INPUT_CAPTURE_7 34
+#define OUTPUT_COMPARE_7 35
+#define TIMER8 36
+#define INPUT_CAPTURE_8_ERROR 37
+#define INPUT_CAPTURE_8 38
+#define OUTPUT_COMPARE_8 39
+#define TIMER9 40
+#define INPUT_CAPTURE_9_ERROR 41
+#define INPUT_CAPTURE_9 42
+#define OUTPUT_COMPARE_9 43
+/* ADC */
+#define ADC1_GLOBAL 44
+/* Reserved */
+#define ADC1_DIGITAL_COMPARATOR_1 46
+#define ADC1_DIGITAL_COMPARATOR_2 47
+#define ADC1_DIGITAL_COMPARATOR_3 48
+#define ADC1_DIGITAL_COMPARATO

[PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller

[Joshua Henderson]

From: Andrei Pistirica 

Document the devicetree bindings for the SDHC peripheral found on
Microchip PIC32 class devices.

Signed-off-by: Andrei Pistirica 
Signed-off-by: Joshua Henderson 
---
 .../devicetree/bindings/mmc/sdhci-pic32.txt|   24 
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt 
b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
new file mode 100644
index 000..f16388c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
@@ -0,0 +1,24 @@
+* Microchip PIC32 SDHCI Controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-pic32 driver.
+
+Required properties:
+- compatible: Should be "microchip,pic32-sdhci"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+- pinctrl: Should contain pinctrl for data and command lines
+
+Optional properties:
+- no-1-8-v: 1.8V voltage selection not supported
+- piomode: disable DMA support
+
+Example:
+
+   sdhci@1f8ec000 {
+   compatible = "microchip,pic32-sdhci";
+   reg = <0x1f8ec000 0x100>;
+   interrupts = ;
+   clocks = <&REFCLKO4>, <&PBCLK5>;
+   clock-names = "base_clk", "sys_clk";
+   };
-- 
1.7.9.5

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[PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO

[Joshua Henderson]

From: Andrei Pistirica 

Document the devicetree bindings for PINCTRL and GPIO found on Microchip
PIC32 class devices. This also adds a header defining related port and
peripheral pin select functionality.

Signed-off-by: Andrei Pistirica 
Signed-off-by: Joshua Henderson 
---
 .../bindings/gpio/microchip,pic32-gpio.txt |   33 ++
 .../bindings/pinctrl/microchip,pic32-pinctrl.txt   |  100 +
 include/dt-bindings/pinctrl/pic32mzda.h|  404 
 3 files changed, 537 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
 create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h

diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt 
b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
new file mode 100644
index 000..f6eeb2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32 GPIO devices (PIO).
+
+Required properties:
+ - compatible: "microchip,pic32-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared be all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+   the second cell is unused.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+   is used to specify the trigger type:
+   PIC32_PIN_CN_RISING : low-to-high edge triggered.
+   PIC32_PIN_CN_FALLING: high-to-low edge triggered.
+   PIC32_PIN_CN_BOTH   : low-to-high and high-to-low edges triggered.
+
+Note:
+ - If gpio-ranges is missing, then all the pins (32) related to the gpio bank
+   are enabled.
+
+Example:
+   pioA: gpio@1f86 {
+   compatible = "microchip,pic32-gpio";
+   reg = <0x1f86 0x24>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   gpio-ranges = <&pic32_pinctrl 0 0 32>;
+   clocks = <&PBCLK4>;
+   };
diff --git 
a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
new file mode 100644
index 000..7cf4167
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -0,0 +1,100 @@
+* Microchip PIC32 Pinmux device.
+
+Please refer to pinctrl-bindings.txt for details of the pinctrl properties and
+common bindings.
+
+PIC32 'pin configuration node' is a node of a group of pins which can be
+used for a specific device or function. This node represents configuraions of
+single pins or a pairs of mux and related configuration.
+
+Required properties for pic32 device:
+ - compatible: "microchip,pic32-pinctrl", "microchip,pic32mz-pinctrl"
+ - reg: Base address and length for pps:in and pps:out registers.
+
+Properties for 'pin configuration node':
+ - pic32,pins: each entry consists of 3 intergers and represents the mux and
+   config settings for one pin. The first integer represent the remappable pin,
+   the second represent the peripheral pin and the last the configuration.
+   The format is pic32,pins = . The configurations
+   are divided in 2 classes: IN and OUT and each in 4 buckets. Each entry must
+   contains items from the same class and bucket, otherwise the driver will
+   notify an error and the initialization will fail.
+ - pic32,single-pins: each entry consists of 3 intergers and represents a pin
+   (that is not remappable) and related configuraion. The format is
+   pic32,single-pins = . Each port has
+   32 pins and please refer to chip documentation for details of remappable
+   pins.
+
+Available pin configurations (refer to dt-bindings/pinctrl/pic32.h):
+   PIC32_PIN_CONF_NONE : no configuration (default).
+   PIC32_PIN_CONF_OD   : indicate this pin need a open-drain (no 
direction).
+   PIC32_PIN_CONF_OD_OUT   : indicate this pin need a open-drain out.
+   PIC32_PIN_CONF_PU   : indicate this pin need a pull up (no 
direction).
+   PIC32_PIN_CONF_PU_IN: indicate this pin need a pull up in.
+   PIC32_PIN_CONF_PD   : indicate this pin need a pull down (no 
direction).
+   PIC32_PIN_CONF_PD_IN: indicate this pin need a pull down input.
+   PIC32_PIN_CONF_AN   : indicate this pin as analogic (no direction).
+   PIC32_PIN_CONF_AN_IN: indicate this pin as analogic input.
+   PIC32_PIN_CONF_DG   : indicate this pin as digital (no direction).
+   PIC32_PIN_CONF_DG_IN: indicate this pin as digital input.
+   PIC32_PIN_CONF_DG_OUT   : indicate this pin as digital output.
+
+NOTEs:
+1. The pins functions nods are define

[PATCH 13/14] MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit

[Joshua Henderson]

This adds basic DTS configuration for the PIC32MZDA and in turn the
PIC32MZDA Starter Kit.

Signed-off-by: Joshua Henderson 
---
 arch/mips/boot/dts/Makefile |1 +
 arch/mips/boot/dts/pic32/Makefile   |   12 ++
 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi |  251 
 arch/mips/boot/dts/pic32/pic32mzda.dtsi |  280 +++
 arch/mips/boot/dts/pic32/pic32mzda_sk.dts   |  150 ++
 arch/mips/pic32/Kconfig |   16 ++
 6 files changed, 710 insertions(+)
 create mode 100644 arch/mips/boot/dts/pic32/Makefile
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda.dtsi
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda_sk.dts

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index a0bf516..fc7a0a9 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs+= ingenic
 dts-dirs   += lantiq
 dts-dirs   += mti
 dts-dirs   += netlogic
+dts-dirs   += pic32
 dts-dirs   += qca
 dts-dirs   += ralink
 dts-dirs   += xilfpga
diff --git a/arch/mips/boot/dts/pic32/Makefile 
b/arch/mips/boot/dts/pic32/Makefile
new file mode 100644
index 000..7ac7905
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/Makefile
@@ -0,0 +1,12 @@
+dtb-$(CONFIG_DTB_PIC32_MZDA_SK)+= pic32mzda_sk.dtb
+
+dtb-$(CONFIG_DTB_PIC32_NONE)   += \
+   pic32mzda_sk.dtb
+
+obj-y  += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+
+# Force kbuild to make empty built-in.o if necessary
+obj-   += dummy.o
+
+always := $(dtb-y)
+clean-files:= *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi 
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
new file mode 100644
index 000..fa1d2bb
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
@@ -0,0 +1,251 @@
+/*
+ * Device Tree Source for PIC32MZDA clock data
+ *
+ * Purna Chandra Mandal 
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/* all fixed rate clocks */
+
+/ {
+   POSC:posc_clk { /* On-chip primary oscillator */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   };
+
+   FRC:frc_clk { /* internal FRC oscillator */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <800>;
+   };
+
+   BFRC:bfrc_clk { /* internal backup FRC oscillator */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <800>;
+   };
+
+   LPRC:lprc_clk { /* internal low-power FRC oscillator */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32000>;
+   };
+
+   /* UPLL provides UTMI clock to USBCORE */
+   UPLL:usb_phy_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "usbphy_clk";
+   };
+
+   TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <400>;
+   status = "disabled";
+   };
+
+   /* external clock input on REFCLKIx pin */
+   REFIx:refix_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   status = "disabled";
+   };
+
+   /* PIC32 specific clks */
+   pic32_clktree {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x1f801200 0x200>;
+   compatible = "microchip,pic32-clk";
+   interrupts = <12>;
+   ranges;
+
+   /* secondary oscillator; external input on SOSCI pin */
+   SOSC:sosc_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-sosc";
+   clock-frequency = <32768>;
+   reg = <0x1f801200 0x10   /* enable reg */
+  0x1f8013d0 0x10>; /* status reg */
+   microchip,bit-mask = <0x02>; /* enable mask */
+   microchip,status-bit-mask = <0x10>; /* status-mask*/
+   };
+
+   FRCDIV:frcdiv_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-frcdivclk";
+   clocks = <&FRC>;
+   clock-output-names = "frcdiv_clk";
+   };
+
+   /* System PLL clock */
+  

[PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation

[Joshua Henderson]

From: Purna Chandra Mandal 

Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.

Signed-off-by: Purna Chandra Mandal 
Signed-off-by: Joshua Henderson 
---
 .../devicetree/bindings/clock/microchip,pic32.txt  |  263 
 1 file changed, 263 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt

diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt 
b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
new file mode 100644
index 000..4cef72d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
@@ -0,0 +1,263 @@
+Binding for a Clock hardware block found on
+certain Microchip PIC32 MCU devices.
+
+Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
+and few divider nodes.
+
+We will find only the base address of the clock tree, this base
+address is common for some of the subnodes, not all. If no address is
+specified for any of subnode base address of the clock tree will be
+treated as its base. Each of subnodes follow the same common clock
+binding with some additional optional properties.
+
+   clocks_node {
+   reg = <>;
+
+   spll_node {
+   ...
+   };
+
+   frcdiv_node {
+   ...
+   };
+
+   sysclk_mux_node {
+   ...
+   };
+
+   pbdiv_node {
+   ...
+   };
+
+   refoclk_node {
+   ...
+   };
+   ...
+   };
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : should have "microchip,pic32-clk".
+- reg : A Base address and length of the register set.
+- interrupts : source of interrupt.
+
+Optional properties (for subnodes):
+- #clock-cells: From common clock binding, should be 0.
+
+- microchip,clock-indices: in multiplexer node clock sources always aren't 
linear
+and contiguous. This property helps define clock-sources with respect to
+the mux clock node.
+
+- microchip,ignore-unused : ignore gate request even if the gated clock is 
unused.
+- microchip,status-bit-mask: bitmask for status check. This will be used to 
confirm
+particular operation by clock sub-node is completed. It is dependent 
sub-node.
+- microchip,bit-mask: enable mask, similar to microchip,status-bit-mask.
+- microchip,slew-step: enable frequency slewing(stepping) during rate change;
+applicable only to sys-clock subnode.
+
+Example:
+
+/* PIC32 specific clks */
+pic32_clktree {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x1f801200 0x200>;
+   compatible = "microchip,pic32-clk";
+   interrupts = <12>;
+   ranges;
+
+   /* secondary oscillator; external input on SOSCI pin */
+   SOSC:sosc_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-sosc";
+   clock-frequency = <32768>;
+   reg = <0x1f801200 0x10   /* enable reg */
+   0x1f801390 0x10>; /* status reg */
+   microchip,bit-mask = <0x02>; /* enable mask */
+   microchip,status-bit-mask = <0x10>; /* status-mask*/
+   };
+
+   FRCDIV:frcdiv_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-frcdivclk";
+   clocks = <&FRC>;
+   clock-output-names = "frcdiv_clk";
+   };
+
+   /* System PLL clock */
+   SYSPLL:spll_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-syspll";
+   reg = <0x1f801220 0x10 /* SPLL register */
+   0x1f801390 0x10>; /* CLKSTAT register */
+   clocks = <&POSC>, <&FRC>;
+   clock-output-names = "sys_pll";
+   microchip,status-bit-mask = <0x80>; /* SPLLRDY */
+   };
+
+   /* system clock; mux with postdiv & slew */
+   SYSCLK:sys_clk {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-sysclk-v2";
+   reg = <0x1f8013c0 0x04>; /* SLEWCON */
+   clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
+   <&LPRC>, <&FRCDIV>;
+   microchip,clock-indices = <0>, <1>, <2>, <4>, <5>, <7>;
+   clock-output-names = "sys_clk";
+   };
+
+   /* DDR Ctrl & DDR PHY PLL */
+   MPLL: CLK_MPLL {
+   #clock-cells = <0>;
+   compatible = "microchip,pic32-mpll";
+   reg = <0x1f800100 0x04>; /* CFGMPLL */
+   clocks = <&POSC>;
+   clock-output-names = "pic32-mpll";
+   status = "disabled";
+   };
+
+   /* Peripheral bus1 clock */
+   PBCLK1:pb1_clk {
+   reg = <0x1f801340 0x10>;
+   #cl

[PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver

[Joshua Henderson]

From: Andrei Pistirica 

Document the devicetree bindings for the USART peripheral found on
Microchip PIC32 class devices.

Signed-off-by: Andrei Pistirica 
Signed-off-by: Joshua Henderson 
---
 .../bindings/serial/microchip,pic32-usart.txt  |   29 
 1 file changed, 29 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt

diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt 
b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
new file mode 100644
index 000..c87321c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
@@ -0,0 +1,29 @@
+* Microchip Universal Synchronous Asynchronous Receiver/Transmitter (USART)
+
+Required properties:
+- compatible: Should be "microchip,pic32-usart"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+- pinctrl: Should contain pinctrl for TX/RX/RTS/CTS
+
+Optional properties:
+- microchip,uart-has-rtscts : Indicate the uart has hardware flow control
+- rts-gpios: RTS pin for USP-based UART if microchip,uart-has-rtscts
+- cts-gpios: CTS pin for USP-based UART if microchip,uart-has-rtscts
+
+Example:
+   usart0: serial@1f822000 {
+   compatible = "microchip,pic32-usart";
+   reg = <0x1f822000 0x50>;
+   interrupts = ,
+,
+;
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   &pinctrl_uart1
+   &pinctrl_uart1_cts
+   &pinctrl_uart1_rts>;
+   microchip,uart-has-rtscts;
+   cts-gpios = <&pioB 15 0>;
+   rts-gpios = <&pioD 1 0>;
+   };
-- 
1.7.9.5

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[PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms

[Joshua Henderson]

This adds support for the Microchip PIC32 platform along with the
specific variant PIC32MZDA on a PIC32MZDA Starter Kit.

Signed-off-by: Joshua Henderson 
---
 .../bindings/mips/pic32/microchip,pic32mzda.txt|   33 
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt

diff --git 
a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt 
b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
new file mode 100644
index 000..bcf3e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32MZDA Platforms
+
+PIC32MZDA Starter Kit
+Required root node properties:
+- compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"
+
+CPU nodes:
+--
+A "cpus" node is required.  Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required.  Required properties:
+ - device_type: Must be "cpu".
+ - compatible: Must be "mti,mips14KEc".
+Example:
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "mti,mips14KEc";
+   };
+   };
+
+Boot protocol
+--
+In accordance with the MIPS UHI specification[1], the bootloader must pass the
+following arguments to the kernel:
+ - $a0: -2.
+ - $a1: KSEG0 address of the flattened device-tree blob.
+
+[1] http://prplfoundation.org/wiki/MIPS_documentation
-- 
1.7.9.5

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[PATCH 00/14] Initial Microchip PIC32MZDA Support

[Joshua Henderson]

This patch series adds support for the Microchip PIC32MZDA MIPS
platform. All drivers required to boot from MMC uSD card are
included. Clock and external interrupt controller drivers are
included. USART, console, and SDHCI peripheral drivers along with
the dependent pinctrl driver are included. This has been tested on
an applicable PIC32MZDA Starter Kit. A tree with these changes is
available at [0].

[0] https://github.com/joshua-henderson/linux/tree/pic32-upstream-v1

Andrei Pistirica (6):
  DEVICETREE: Add bindings for PIC32 pin control and GPIO
  pinctrl: Add PIC32 pin control driver
  DEVICETREE: Add bindings for PIC32 usart driver
  serial: pic32_uart: Add PIC32 uart driver
  mmc: sdhci-pic32: Add PIC32 SDHC host controller driver
  DEVICETREE: Add bindings for PIC32 SDHC host controller

Cristian Birsan (2):
  DEVICETREE: Add bindings for PIC32 interrupt controller
  irqchip: irq-pic32-evic: Add support for PIC32 interrupt controller

Joshua Henderson (4):
  DEVICETREE: Add bindings for PIC32/MZDA platforms
  MIPS: Add support for PIC32MZDA platform
  MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit
  MIPS: pic32mzda: Add initial PIC32MZDA Starter Kit defconfig

Purna Chandra Mandal (2):
  DEVICETREE: Add PIC32 clock binding documentation
  clk: clk-pic32: Add PIC32 clock driver

 .../devicetree/bindings/clock/microchip,pic32.txt  |  263 +++
 .../bindings/gpio/microchip,pic32-gpio.txt |   33 +
 .../microchip,pic32mz-evic.txt |   65 +
 .../bindings/mips/pic32/microchip,pic32mzda.txt|   33 +
 .../devicetree/bindings/mmc/sdhci-pic32.txt|   24 +
 .../bindings/pinctrl/microchip,pic32-pinctrl.txt   |  100 +
 .../bindings/serial/microchip,pic32-usart.txt  |   29 +
 arch/mips/Kbuild.platforms |1 +
 arch/mips/Kconfig  |9 +
 arch/mips/boot/dts/Makefile|1 +
 arch/mips/boot/dts/pic32/Makefile  |   12 +
 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi|  251 +++
 arch/mips/boot/dts/pic32/pic32mzda.dtsi|  280 +++
 arch/mips/boot/dts/pic32/pic32mzda_sk.dts  |  150 ++
 arch/mips/configs/pic32mzda_defconfig  |   88 +
 .../include/asm/mach-pic32/cpu-feature-overrides.h |   32 +
 arch/mips/include/asm/mach-pic32/gpio.h|   26 +
 arch/mips/include/asm/mach-pic32/irq.h |   22 +
 arch/mips/include/asm/mach-pic32/pic32.h   |   44 +
 arch/mips/include/asm/mach-pic32/spaces.h  |   24 +
 arch/mips/pic32/Kconfig|   50 +
 arch/mips/pic32/Makefile   |6 +
 arch/mips/pic32/Platform   |7 +
 arch/mips/pic32/common/Makefile|5 +
 arch/mips/pic32/common/irq.c   |   20 +
 arch/mips/pic32/common/reset.c |   62 +
 arch/mips/pic32/pic32mzda/Makefile |9 +
 arch/mips/pic32/pic32mzda/config.c |  148 ++
 arch/mips/pic32/pic32mzda/early_clk.c  |  106 +
 arch/mips/pic32/pic32mzda/early_console.c  |  171 ++
 arch/mips/pic32/pic32mzda/early_pin.c  |  275 +++
 arch/mips/pic32/pic32mzda/early_pin.h  |  241 +++
 arch/mips/pic32/pic32mzda/init.c   |  156 ++
 arch/mips/pic32/pic32mzda/pic32mzda.h  |   30 +
 arch/mips/pic32/pic32mzda/time.c   |   47 +
 drivers/clk/Kconfig|3 +
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-pic32.c| 1947 ++
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-pic32-evic.c   |  309 +++
 drivers/mmc/host/Kconfig   |   11 +
 drivers/mmc/host/Makefile  |1 +
 drivers/mmc/host/sdhci-pic32.c |  354 
 drivers/pinctrl/Kconfig|   17 +
 drivers/pinctrl/Makefile   |2 +
 drivers/pinctrl/pinctrl-pic32.c| 2127 
 drivers/pinctrl/pinctrl-pic32.h|  158 ++
 drivers/pinctrl/pinctrl-pic32mzda.c|  294 +++
 drivers/pinctrl/pinctrl-pic32mzda.h|   40 +
 drivers/tty/serial/Kconfig |   21 +
 drivers/tty/serial/Makefile|1 +
 drivers/tty/serial/pic32_uart.c|  930 +
 drivers/tty/serial/pic32_uart.h|  199 ++
 .../interrupt-controller/microchip,pic32mz-evic.h  |  238 +++
 include/dt-bindings/pinctrl/pic32mzda.h|  404 
 include/linux/irqchip/pic32-evic.h |   19 +
 include/linux/platform_data/sdhci-pic32.h  |   22 +
 include/uapi/linux/serial_core.h   |3 +
 58 files changed, 9922 insertions(+)
 create mode 100644 Documentation/d

[PATCH v4 2/3] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Tim Bird]

Add support for async_irq to wake up driver from low power mode.
Without this, the power management code never calls resume.
Remove a spurious interrupt enable in the driver resume function.

Signed-off-by: Tim Bird 
---
 drivers/usb/phy/phy-msm-usb.c | 17 -
 include/linux/usb/msm_hsusb.h |  1 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index e40a071..04fb056 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -648,7 +648,6 @@ skip_phy_resume:
if (motg->async_int) {
motg->async_int = 0;
pm_runtime_put(phy->dev);
-   enable_irq(motg->irq);
}
 
dev_info(phy->dev, "USB exited from low power mode\n");
@@ -1732,6 +1731,12 @@ static int msm_otg_probe(struct platform_device *pdev)
return motg->irq;
}
 
+   motg->async_irq = platform_get_irq_byname(pdev, "async");
+   if (motg->async_irq < 0) {
+   dev_err(&pdev->dev, "platform_get_irq for async irq failed\n");
+   motg->async_irq = 0;
+   }
+
regs[0].supply = "vddcx";
regs[1].supply = "v3p3";
regs[2].supply = "v1p8";
@@ -1781,6 +1786,16 @@ static int msm_otg_probe(struct platform_device *pdev)
goto disable_ldo;
}
 
+   if (motg->async_irq) {
+   ret = devm_request_irq(&pdev->dev, motg->async_irq,
+ msm_otg_irq, IRQF_TRIGGER_RISING,
+ "msm_otg", motg);
+   if (ret) {
+   dev_err(&pdev->dev, "request irq failed (ASYNC INT)\n");
+   goto disable_ldo;
+   }
+   }
+
phy->init = msm_phy_init;
phy->set_power = msm_otg_set_power;
phy->notify_disconnect = msm_phy_notify_disconnect;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 8c8f685..08c67a3 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -164,6 +164,7 @@ struct msm_otg {
struct usb_phy phy;
struct msm_otg_platform_data *pdata;
int irq;
+   int async_irq;
struct clk *clk;
struct clk *pclk;
struct clk *core_clk;
-- 
1.8.2.2

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Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support

[Stephen Boyd]

On 11/20, Florian Fainelli wrote:
> On 20/11/15 10:46, Stephen Boyd wrote:
> > On 11/19, Florian Fainelli wrote:
> >> On 19/11/15 17:00, Florian Fainelli wrote:
> >>> On 29/10/15 18:23, Florian Fainelli wrote:
>  This patch series adds support for the Broadcom BCM63138 DSL SoCs
>  clocking framework.
> 
>  Since the HW is identical to the one found in Broadcom iProc SoCs, but 
>  the
>  integration is different (obviously), there is still a new compatible 
>  string
>  introduced just in case we happen to find issues in the future.
> 
>  Stephen, could you stage the two patches in a clk-bcm63xx branch that I 
>  could
>  later utilize while doing the arm-soc DT pull request?
> >>>
> >>> Stephen, can you queue the first two patches in a topic branch for me to
> >>> merge as part of the commit adding the DTS changes?
> >>
> >> Well, now that I look back at the changes, you can actually merge the
> >> two patches in clk-next, and the DTS changes can come in before or
> >> after, it does not really matter, this would not cause breakage or
> >> anything. Sorry for the noise.
> > 
> > Really? I thought if the clk patches aren't there then the dts
> > change would cause some clocks to be orphaned. If that's ok with
> > you it's ok with me.
> 
> Woah, I guess I was not thinking very clearly yesterday, yes, we need to
> bundle these changes together, so if you are still okay with the topic
> branch for me to include as a merge commit, that's fine with me as well.

Ok. Done.

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Re: [PATCH v4 2/3] clk: bcm: Add BCM63138 clock support

[Stephen Boyd]

On 10/29, Florian Fainelli wrote:
> BCM63138 has a simple clocking domain which is primarily the ARMPLL
> clocking complex, from which the ARM (CPU), APB and AXI clocks would be
> derived from.
> 
> Since the ARMPLL controller is entirely compatible with the iProc ARM
> PLL, we just initialize it without additional parameters.
> 
> Signed-off-by: Florian Fainelli 
> ---

Applied to clk-bcm63xx

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Re: [PATCH v4 1/3] clk: iproc: Extend binding to cover BCM63138

[Stephen Boyd]

On 10/29, Florian Fainelli wrote:
> Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure
> as the Cygnus and iProc chips, add a dedicated compatible string and
> document that the ARMPLL node is a valid node for this chip.
> 
> Acked-by: Rob Herring 
> Signed-off-by: Florian Fainelli 
> ---

Applied to clk-bcm63xx

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[PATCH v4 3/3] usb: chipidea: register driver as a peripheral with the phy

[Tim Bird]

Register the chipidea driver with the phy, so that the phy
driver can kick the gadget driver when it resumes from low power.
The phy-msm-usb (Qualcomm) driver requires this in order to
recover gadget operation after you disconnect the USB cable
and reconnect it.

Signed-off-by: Tim Bird 
---
 drivers/usb/chipidea/udc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 8223fe7..06234cd 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1890,6 +1890,12 @@ static int udc_start(struct ci_hdrc *ci)
 
ci->gadget.ep0 = &ci->ep0in->ep;
 
+   if (ci->usb_phy) {
+   retval = otg_set_peripheral(ci->usb_phy->otg, &ci->gadget);
+   if (retval)
+   goto destroy_eps;
+   }
+
retval = usb_add_gadget_udc(dev, &ci->gadget);
if (retval)
goto destroy_eps;
-- 
1.8.2.2

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[PATCH v4 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

Add optional async_irq to msm_hsusb binding doc.

Signed-off-by: Tim Bird 
---
 Documentation/devicetree/bindings/usb/msm-hsusb.txt | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 8654a3e..2d13c1c 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -23,7 +23,12 @@ Required properties:
   "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
 
 - regs: Offset and length of the register set in the memory map
-- interrupts:   interrupt-specifier for the OTG interrupt.
+- interrupts:   interrupt-specifier for the OTG interrupts
+
+- interrupt-names: Should contain the following:
+  "core"USB core interrupt
+  "async"   Asynchronous interrupt to wake up from low power mode
+(optional)
 
 - clocks:   A list of phandle + clock-specifier pairs for the
 clocks listed in clock-names
@@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
 usb@f9a55000 {
 compatible = "qcom,usb-otg-snps";
 reg = <0xf9a55000 0x400>;
-interrupts = <0 134 0>;
+interrupts = <0 134 0>, <0 140 0>;
+interrupt-names = "core", "async";
 dr_mode = "peripheral";
 
 clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
-- 
1.8.2.2

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[PATCH v2 3/5] arm: dts: qcom: Update ifc6540 compat for qcom boot format

[Stephen Boyd]

The ifc6540 is an sbc (single board computer) board, so update
the compatible field accordingly.

Signed-off-by: Stephen Boyd 
---
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts 
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index c9c2b769554f..32aaa9d45228 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -3,7 +3,7 @@
 
 / {
model = "Qualcomm APQ8084/IFC6540";
-   compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
+   compatible = "qcom,apq8084-sbc", "qcom,apq8084";
 
aliases {
serial0 = &blsp2_uart2;
-- 
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[PATCH v2 4/5] arm64: dts: qcom: Alias pm8916 on msm8916 devices

[Stephen Boyd]

Add an alias for pm8916 on msm8916 based SoCs so that the newly
updated dtbTool can find the pmic compatible string and add the
pmic-id element to the QCDT header.

Signed-off-by: Stephen Boyd 
---
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 +
 arch/arm64/boot/dts/qcom/pm8916.dtsi  | 6 +++---
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 6b8abbe68746..46bfcb9b2e84 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -20,6 +20,7 @@
aliases {
serial0 = &blsp1_uart2;
serial1 = &blsp1_uart1;
+   usid0 = &pm8916_0;
};
 
chosen {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index a1aa0b201e92..ceeb8a6feed6 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -17,6 +17,7 @@
 / {
aliases {
serial0 = &blsp1_uart2;
+   usid0 = &pm8916_0;
};
 
chosen {
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi 
b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index b222ece7e3d2..37432451ee4c 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -4,8 +4,8 @@
 
 &spmi_bus {
 
-   usid0: pm8916@0 {
-   compatible = "qcom,spmi-pmic";
+   pm8916_0: pm8916@0 {
+   compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
@@ -90,7 +90,7 @@
};
};
 
-   usid1: pm8916@1 {
+   pm8916_1: pm8916@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
-- 
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[PATCH v2 5/5] arm: dts: qcom: Add aliases for PMICs

[Stephen Boyd]

Add an alias for the PMICs found on qcom based SoCs so that the
newly updated dtbTool can find the PMIC compatible string and add
the pmic-id element to the QCDT header.

Signed-off-by: Stephen Boyd 
---
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 2 ++
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 1 +
 arch/arm/boot/dts/qcom-apq8084-mtp.dts | 1 +
 arch/arm/boot/dts/qcom-pm8841.dtsi | 8 
 arch/arm/boot/dts/qcom-pm8941.dtsi | 8 
 arch/arm/boot/dts/qcom-pma8084.dtsi| 8 
 6 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts 
b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 835bdc71c5ba..c0e205315042 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -8,6 +8,8 @@
 
aliases {
serial0 = &blsp1_uart2;
+   usid0 = &pm8941_0;
+   usid4 = &pm8841_0;
};
 
chosen {
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts 
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index 32aaa9d45228..2052b84a77c6 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -7,6 +7,7 @@
 
aliases {
serial0 = &blsp2_uart2;
+   usid0 = &pma8084_0;
};
 
chosen {
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts 
b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 3016c7048d44..d174d15bcf70 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -7,6 +7,7 @@
 
aliases {
serial0 = &blsp2_uart2;
+   usid0 = &pma8084_0;
};
 
chosen {
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 8f1a0b162017..523bee959f98 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -3,8 +3,8 @@
 
 &spmi_bus {
 
-   usid4: pm8841@4 {
-   compatible = "qcom,spmi-pmic";
+   pm8841_0: pm8841@4 {
+   compatible = "qcom,pm8841", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
@@ -27,8 +27,8 @@
};
};
 
-   usid5: pm8841@5 {
-   compatible = "qcom,spmi-pmic";
+   pm8841_1: pm8841@5 {
+   compatible = "qcom,pm8841", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi 
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index c19a48732b2d..12c1202ba2ca 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -4,8 +4,8 @@
 
 &spmi_bus {
 
-   usid0: pm8941@0 {
-   compatible ="qcom,spmi-pmic";
+   pm8941_0: pm8941@0 {
+   compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
@@ -153,8 +153,8 @@
};
};
 
-   usid1: pm8941@1 {
-   compatible = "qcom,spmi-pmic";
+   pm8941_1: pm8941@1 {
+   compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi 
b/arch/arm/boot/dts/qcom-pma8084.dtsi
index 5e240ccc08b7..10b8f9e6d60b 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -4,8 +4,8 @@
 
 &spmi_bus {
 
-   usid0: pma8084@0 {
-   compatible = "qcom,spmi-pmic";
+   pma8084_0: pma8084@0 {
+   compatible = "qcom,pma8084", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
@@ -101,8 +101,8 @@
};
};
 
-   usid1: pma8084@1 {
-   compatible = "qcom,spmi-pmic";
+   pma8084_1: pma8084@1 {
+   compatible = "qcom,pma8084", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
-- 
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[PATCH v2 1/5] devicetree: bindings: Document qcom board compatible format

[Stephen Boyd]

Some qcom based bootloaders identify the dtb blob based on a set
of device properties like SoC, platform, PMIC, and revisions of
those components. In downstream kernels, these values are added
to the different component dtsi files (i.e. pmic dtsi file, SoC
dtsi file, board dtsi file, etc.) via qcom specific DT
properties. The dtb files are parsed by a program called dtbTool
that picks out these properties and creates a table of contents
binary blob with the property information and some offsets into
the concatenation of all the dtbs (termed a QCDT image).

The suggestion is to do this via the board compatible string
instead, because these qcom specific properties are never used by
the kernel. Add a document describing the format of the
compatible string that encodes all this information that's
currently encoded in the qcom,{msm-id,board-id,pmic-id}
properties in downstream devicetrees. Future bootloaders may be
updated to look at the compatible field instead of looking for
the table of contents image. For non-updateable bootloaders, a
new dtbTool program will parse the compatible string and generate
a QCDT image from it.

Signed-off-by: Stephen Boyd 
---
 Documentation/devicetree/bindings/arm/qcom.txt | 51 ++
 1 file changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom.txt

diff --git a/Documentation/devicetree/bindings/arm/qcom.txt 
b/Documentation/devicetree/bindings/arm/qcom.txt
new file mode 100644
index ..3e24518c6678
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -0,0 +1,51 @@
+QCOM device tree bindings
+-
+
+Some qcom based bootloaders identify the dtb blob based on a set of
+device properties like SoC and platform and revisions of those components.
+To support this scheme, we encode this information into the board compatible
+string.
+
+Each board must specify a top-level board compatible string with the following
+format:
+
+   compatible = 
"qcom,[-][-]-[/][-]"
+
+The 'SoC' and 'board' elements are required. All other elements are optional.
+
+The 'SoC' element must be one of the following strings:
+
+   apq8016
+   apq8074
+   apq8084
+   apq8096
+   msm8916
+   msm8974
+   msm8996
+
+The 'board' element must be one of the following strings:
+
+   cdp
+   liquid
+   dragonboard
+   mtp
+   sbc
+
+The 'soc_version' and 'board_version' elements take the form of 
v.
+where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
+as v1. If all versions of the 'board_version' elements match, then a
+wildcard '*' should be used, e.g. 'v*'.
+
+The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
+
+Examples:
+
+   "qcom,msm8916-v1-cdp-pm8916-v2.1"
+
+A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
+2.1.
+
+   "qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
+
+A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
+foundry 2.
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[PATCH v2 2/5] arm64: dts: qcom: Make msm8916-mtp compatible string compliant

[Stephen Boyd]

This compatible string isn't compliant with the format for
subtypes. Replace it with a compliant compatible type.

Signed-off-by: Stephen Boyd 
---
 arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts 
b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
index fced77f0fd3a..b0a064d3806b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -17,6 +17,6 @@
 
 / {
model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
-   compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
+   compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1",
"qcom,msm8916", "qcom,mtp";
 };
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[PATCH v2 0/5] Remove the need for qcom,{msm-id,board-id,pmic-id}

[Stephen Boyd]

This patchset documents a compatible string format that encodes
all the information that was being encoded in qcom specific DT
properties in downstream msm kernels. The goal being to come
up with a format that will allow us to express the information
we want to express without requiring the use of vendor specific
properties. An updated dtbTool will be released after these new
bindings are accepted so that users can work with non-updateable
bootloaders.

This is an attempt to resolve a discussion around March of this year[1]
where the arm-soc maintainers suggested we express this information
through the board's compatible string.

Changes from v1:
 * Remove unused elements (mb, panel, boot device)
 * Remove PMICs from board compatible
 * Add patches to allow us to parse PMIC compatibles with aliases

[1] 
http://lkml.kernel.org/g/1425503602-24916-1-git-send-email-ga...@codeaurora.org

Stephen Boyd (5):
  devicetree: bindings: Document qcom board compatible format
  arm64: dts: qcom: Make msm8916-mtp compatible string compliant
  arm: dts: qcom: Update ifc6540 compat for qcom boot format
  arm64: dts: qcom: Alias pm8916 on msm8916 devices
  arm: dts: qcom: Add aliases for PMICs

 Documentation/devicetree/bindings/arm/qcom.txt | 51 ++
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts |  2 +
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |  3 +-
 arch/arm/boot/dts/qcom-apq8084-mtp.dts |  1 +
 arch/arm/boot/dts/qcom-pm8841.dtsi |  8 ++--
 arch/arm/boot/dts/qcom-pm8941.dtsi |  8 ++--
 arch/arm/boot/dts/qcom-pma8084.dtsi|  8 ++--
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |  1 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dts   |  2 +-
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi  |  1 +
 arch/arm64/boot/dts/qcom/pm8916.dtsi   |  6 +--
 11 files changed, 74 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom.txt

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Re: [PATCH v3 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

On 11/20/2015 03:22 PM, Arnd Bergmann wrote:
> On Friday 20 November 2015 15:20:39 Tim Bird wrote:
>> +- interrupt-names: Should contain the following:
>> +  "core"USB core interrupt
>> +  "async"   Asynchronous interrupt to wake up from low power mode
>> +(optional)
>>  
>>  - clocks:   A list of phandle + clock-specifier pairs for the
>>  clocks listed in clock-names
>> @@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
>>  usb@f9a55000 {
>>  compatible = "qcom,usb-otg-snps";
>>  reg = <0xf9a55000 0x400>;
>> -interrupts = <0 134 0>;
>> +interrupts = <0 134 0>, <0 140 0>;
>> +interrupt-names = "core_irq", "async_irq";
>>  dr_mode = "peripheral";
>>  
>>
> 
> Now the example doesn't match the documentation any more.
Arrgh.  I'm an idiot.  V4 coming RSN.
 -- Tim

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Re: [PATCH v3 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Arnd Bergmann]

On Friday 20 November 2015 15:20:39 Tim Bird wrote:
> +- interrupt-names: Should contain the following:
> +  "core"USB core interrupt
> +  "async"   Asynchronous interrupt to wake up from low power mode
> +(optional)
>  
>  - clocks:   A list of phandle + clock-specifier pairs for the
>  clocks listed in clock-names
> @@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
>  usb@f9a55000 {
>  compatible = "qcom,usb-otg-snps";
>  reg = <0xf9a55000 0x400>;
> -interrupts = <0 134 0>;
> +interrupts = <0 134 0>, <0 140 0>;
> +interrupt-names = "core_irq", "async_irq";
>  dr_mode = "peripheral";
>  
> 

Now the example doesn't match the documentation any more.

Arnd
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Re: [PATCH v3 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

On 11/20/2015 03:20 PM, Tim Bird wrote:
> Add optional async_irq to msm_hsusb binding doc.
> 
> Signed-off-by: Tim Bird 
> Acked-by: Rob Herring 

I probably should have taken this Acked-by by Rob off.  Sorry about that.
  -- Tim

> ---
>  Documentation/devicetree/bindings/usb/msm-hsusb.txt | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
> b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> index 8654a3e..bb2b304 100644
> --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> @@ -23,7 +23,12 @@ Required properties:
>"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
>  
>  - regs: Offset and length of the register set in the memory map
> -- interrupts:   interrupt-specifier for the OTG interrupt.
> +- interrupts:   interrupt-specifier for the OTG interrupts
> +
> +- interrupt-names: Should contain the following:
> +  "core"USB core interrupt
> +  "async"   Asynchronous interrupt to wake up from low power mode
> +(optional)
>  
>  - clocks:   A list of phandle + clock-specifier pairs for the
>  clocks listed in clock-names
> @@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
>  usb@f9a55000 {
>  compatible = "qcom,usb-otg-snps";
>  reg = <0xf9a55000 0x400>;
> -interrupts = <0 134 0>;
> +interrupts = <0 134 0>, <0 140 0>;
> +interrupt-names = "core_irq", "async_irq";
>  dr_mode = "peripheral";
>  
>  clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
> 
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[PATCH v3 2/3] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Tim Bird]

Add support for async_irq to wake up driver from low power mode.
Without this, the power management code never calls resume.
Remove a spurious interrupt enable in the driver resume function.

Signed-off-by: Tim Bird 
---
 drivers/usb/phy/phy-msm-usb.c | 17 -
 include/linux/usb/msm_hsusb.h |  1 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index e40a071..04fb056 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -648,7 +648,6 @@ skip_phy_resume:
if (motg->async_int) {
motg->async_int = 0;
pm_runtime_put(phy->dev);
-   enable_irq(motg->irq);
}
 
dev_info(phy->dev, "USB exited from low power mode\n");
@@ -1732,6 +1731,12 @@ static int msm_otg_probe(struct platform_device *pdev)
return motg->irq;
}
 
+   motg->async_irq = platform_get_irq_byname(pdev, "async");
+   if (motg->async_irq < 0) {
+   dev_err(&pdev->dev, "platform_get_irq for async irq failed\n");
+   motg->async_irq = 0;
+   }
+
regs[0].supply = "vddcx";
regs[1].supply = "v3p3";
regs[2].supply = "v1p8";
@@ -1781,6 +1786,16 @@ static int msm_otg_probe(struct platform_device *pdev)
goto disable_ldo;
}
 
+   if (motg->async_irq) {
+   ret = devm_request_irq(&pdev->dev, motg->async_irq,
+ msm_otg_irq, IRQF_TRIGGER_RISING,
+ "msm_otg", motg);
+   if (ret) {
+   dev_err(&pdev->dev, "request irq failed (ASYNC INT)\n");
+   goto disable_ldo;
+   }
+   }
+
phy->init = msm_phy_init;
phy->set_power = msm_otg_set_power;
phy->notify_disconnect = msm_phy_notify_disconnect;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 8c8f685..08c67a3 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -164,6 +164,7 @@ struct msm_otg {
struct usb_phy phy;
struct msm_otg_platform_data *pdata;
int irq;
+   int async_irq;
struct clk *clk;
struct clk *pclk;
struct clk *core_clk;
-- 
1.8.2.2

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[PATCH v3 3/3] usb: chipidea: register driver as a peripheral with the phy

[Tim Bird]

Register the chipidea driver with the phy, so that the phy
driver can kick the gadget driver when it resumes from low power.
The phy-msm-usb (Qualcomm) driver requires this in order to
recover gadget operation after you disconnect the USB cable
and reconnect it.

Signed-off-by: Tim Bird 
---
 drivers/usb/chipidea/udc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 8223fe7..06234cd 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1890,6 +1890,12 @@ static int udc_start(struct ci_hdrc *ci)
 
ci->gadget.ep0 = &ci->ep0in->ep;
 
+   if (ci->usb_phy) {
+   retval = otg_set_peripheral(ci->usb_phy->otg, &ci->gadget);
+   if (retval)
+   goto destroy_eps;
+   }
+
retval = usb_add_gadget_udc(dev, &ci->gadget);
if (retval)
goto destroy_eps;
-- 
1.8.2.2

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[PATCH v3 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

Add optional async_irq to msm_hsusb binding doc.

Signed-off-by: Tim Bird 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/usb/msm-hsusb.txt | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 8654a3e..bb2b304 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -23,7 +23,12 @@ Required properties:
   "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
 
 - regs: Offset and length of the register set in the memory map
-- interrupts:   interrupt-specifier for the OTG interrupt.
+- interrupts:   interrupt-specifier for the OTG interrupts
+
+- interrupt-names: Should contain the following:
+  "core"USB core interrupt
+  "async"   Asynchronous interrupt to wake up from low power mode
+(optional)
 
 - clocks:   A list of phandle + clock-specifier pairs for the
 clocks listed in clock-names
@@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
 usb@f9a55000 {
 compatible = "qcom,usb-otg-snps";
 reg = <0xf9a55000 0x400>;
-interrupts = <0 134 0>;
+interrupts = <0 134 0>, <0 140 0>;
+interrupt-names = "core_irq", "async_irq";
 dr_mode = "peripheral";
 
 clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
-- 
1.8.2.2

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Re: [PATCH v2 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

On 11/20/2015 02:44 PM, Arnd Bergmann wrote:
> On Friday 20 November 2015 14:37:16 Tim Bird wrote:
>> +- interrupt-names: Should contain the following:
>> +  "core_irq"USB core interrupt
>> +  "async_irq"   Asynchronous interrupt to wake up from low power mode
>> +(optional)
>>  
>>
> 
> Sorry for the bike-shedding but how about just naming them "core" and "async"?
> 
> The redundant "_irq" postfix seems a little redundant.
OK - look for v3 RSN(tm)  (Real Soon Now)
 -- Tim

P.S. This is a cynical ploy to get me to automate my patch release process, 
isn't it? :-)

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Re: [PATCH v2 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Arnd Bergmann]

On Friday 20 November 2015 14:37:16 Tim Bird wrote:
> +- interrupt-names: Should contain the following:
> +  "core_irq"USB core interrupt
> +  "async_irq"   Asynchronous interrupt to wake up from low power mode
> +(optional)
>  
> 

Sorry for the bike-shedding but how about just naming them "core" and "async"?

The redundant "_irq" postfix seems a little redundant.

Arnd
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Re: [PATCH v2 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Sergei Shtylyov]

Hello.

On 11/21/2015 01:37 AM, Tim Bird wrote:


Add optional async_irq to msm_hsusb binding doc.

Signed-off-by: Tim Bird 
Acked-by: Rob Herring 
---
  Documentation/devicetree/bindings/usb/msm-hsusb.txt | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 8654a3e..7ba1dff 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -23,7 +23,12 @@ Required properties:
"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY

  - regs: Offset and length of the register set in the memory map
-- interrupts:   interrupt-specifier for the OTG interrupt.
+- interrupts:   interrupt-specifier for the OTG interrupts
+
+- interrupt-names: Should contain the following:
+  "core_irq"USB core interrupt
+  "async_irq"   Asynchronous interrupt to wake up from low power mode


   I think the "_irq" part can be dropped...

[...]

MBR, Sergei

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Re: [PATCH 2/2] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Tim Bird]

On 11/16/2015 09:21 AM, Felipe Balbi wrote:
> 
> Hi,
> 
> Peter Chen  writes:
>> On Wed, Nov 11, 2015 at 09:48:00AM -0800, Tim Bird wrote:
>>>
>>>
>>> On 11/10/2015 07:14 PM, Peter Chen wrote:
 On Tue, Nov 10, 2015 at 04:46:51PM -0800, Tim Bird wrote:
> This fixes a bug where if you disconnect and re-connect the USB cable,
> the gadget driver stops working.
>
> Add support for async_irq to wake up driver from low power mode.
> Without this, the power management code never calls resume.
> Also, have the phy driver kick the gadget driver (chipidea otg)
> by having the chipidea driver register with it, for vbus connect
> notifications.
>
> Signed-off-by: Tim Bird 
> ---
>  drivers/usb/chipidea/udc.c|  6 ++
>  drivers/usb/phy/phy-msm-usb.c | 16 
>  include/linux/usb/msm_hsusb.h |  1 +
>  3 files changed, 23 insertions(+)
> 
> I just wanna know how you guys want this to be handled ? Through my tree
> or chipidea's ? Or do we break the dependencies between the changes ?

I'm fine with splitting it up.  I'm sending a new series with 3 patches
right after this message.  Do both trees go to linux-next?
 -- Tim

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[PATCH v2 1/3] Documentation: dt-bindings: add async_irq to msm_hsusb

[Tim Bird]

Add optional async_irq to msm_hsusb binding doc.

Signed-off-by: Tim Bird 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/usb/msm-hsusb.txt | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 8654a3e..7ba1dff 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -23,7 +23,12 @@ Required properties:
   "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
 
 - regs: Offset and length of the register set in the memory map
-- interrupts:   interrupt-specifier for the OTG interrupt.
+- interrupts:   interrupt-specifier for the OTG interrupts
+
+- interrupt-names: Should contain the following:
+  "core_irq"USB core interrupt
+  "async_irq"   Asynchronous interrupt to wake up from low power mode
+(optional)
 
 - clocks:   A list of phandle + clock-specifier pairs for the
 clocks listed in clock-names
@@ -89,7 +94,8 @@ Example HSUSB OTG controller device node:
 usb@f9a55000 {
 compatible = "qcom,usb-otg-snps";
 reg = <0xf9a55000 0x400>;
-interrupts = <0 134 0>;
+interrupts = <0 134 0>, <0 140 0>;
+interrupt-names = "core_irq", "async_irq";
 dr_mode = "peripheral";
 
 clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
-- 
1.8.2.2

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[PATCH v2 2/3] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Tim Bird]

Add support for async_irq to wake up driver from low power mode.
Without this, the power management code never calls resume.
Remove a spurious interrupt enable in the driver resume function.

Signed-off-by: Tim Bird 
---
 drivers/usb/phy/phy-msm-usb.c | 17 -
 include/linux/usb/msm_hsusb.h |  1 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index e40a071..db6297c 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -648,7 +648,6 @@ skip_phy_resume:
if (motg->async_int) {
motg->async_int = 0;
pm_runtime_put(phy->dev);
-   enable_irq(motg->irq);
}
 
dev_info(phy->dev, "USB exited from low power mode\n");
@@ -1732,6 +1731,12 @@ static int msm_otg_probe(struct platform_device *pdev)
return motg->irq;
}
 
+   motg->async_irq = platform_get_irq_byname(pdev, "async_irq");
+   if (motg->async_irq < 0) {
+   dev_err(&pdev->dev, "platform_get_irq for async_irq failed\n");
+   motg->async_irq = 0;
+   }
+
regs[0].supply = "vddcx";
regs[1].supply = "v3p3";
regs[2].supply = "v1p8";
@@ -1781,6 +1786,16 @@ static int msm_otg_probe(struct platform_device *pdev)
goto disable_ldo;
}
 
+   if (motg->async_irq) {
+   ret = devm_request_irq(&pdev->dev, motg->async_irq,
+ msm_otg_irq, IRQF_TRIGGER_RISING,
+ "msm_otg", motg);
+   if (ret) {
+   dev_err(&pdev->dev, "request irq failed (ASYNC INT)\n");
+   goto disable_ldo;
+   }
+   }
+
phy->init = msm_phy_init;
phy->set_power = msm_otg_set_power;
phy->notify_disconnect = msm_phy_notify_disconnect;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 8c8f685..08c67a3 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -164,6 +164,7 @@ struct msm_otg {
struct usb_phy phy;
struct msm_otg_platform_data *pdata;
int irq;
+   int async_irq;
struct clk *clk;
struct clk *pclk;
struct clk *core_clk;
-- 
1.8.2.2

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[PATCH v2 3/3] usb: chipidea: register driver as a peripheral with the phy

[Tim Bird]

Register the chipidea driver with the phy, so that the phy
driver can kick the gadget driver when it resumes from low power.
The phy-msm-usb (Qualcomm) driver requires this in order to
recover gadget operation after you disconnect the USB cable
and reconnect it.

Signed-off-by: Tim Bird 
---
 drivers/usb/chipidea/udc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 8223fe7..06234cd 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1890,6 +1890,12 @@ static int udc_start(struct ci_hdrc *ci)
 
ci->gadget.ep0 = &ci->ep0in->ep;
 
+   if (ci->usb_phy) {
+   retval = otg_set_peripheral(ci->usb_phy->otg, &ci->gadget);
+   if (retval)
+   goto destroy_eps;
+   }
+
retval = usb_add_gadget_udc(dev, &ci->gadget);
if (retval)
goto destroy_eps;
-- 
1.8.2.2

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Re: [PATCH V2 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device

[Nicolin Chen]

On Fri, Nov 20, 2015 at 08:29:46AM -0600, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 02:17:53PM +0800, Shengjiu Wang wrote:
> > ASRC need to enable the spba clock, when sdma is using share peripheral
> > script. In this case, there is two spba master port is used, if don't
> > enable the clock, the spba bus will have arbitration issue, which may
> > cause read/write wrong data from/to ASRC registers
> > 
> > Signed-off-by: Shengjiu Wang 
> > ---
> >  Documentation/devicetree/bindings/sound/fsl,asrc.txt |  2 ++
> >  sound/soc/fsl/fsl_asrc.c | 10 ++
> >  sound/soc/fsl/fsl_asrc.h |  1 +
> >  3 files changed, 13 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt 
> > b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> > index b93362a..d83 100644
> > --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> > +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> > @@ -25,6 +25,8 @@ Required properties:
> > "mem" Peripheral access clock to access registers.
> > "ipg" Peripheral clock to driver module.
> > "asrck_<0-f>" Clock sources for input and output clock.
> > +   "spba"The spba clock is needed when two spba master port
> > + is used.
> 
> I'm assuming the same comments on patch 1 apply to all 3.

Yes. I should have mentioned that.

Nicolin
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Re: [PATCH] Documentation: dt-bindings: Fix interrupt documentation file path

[Andrew F. Davis]

On 09/21/2015 11:25 AM, Andrew F. Davis wrote:

Fix the incorrect interrupt documentation file path in binding docs.

Signed-off-by: Andrew F. Davis 


Ping? Still applies to v4.4-rc1.



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Re: [PATCH 1/2] arm64: dts: berlin4ct: add I2C nodes for BG4CT

[Sebastian Hesselbarth]

On 20.11.2015 10:47, Jisheng Zhang wrote:
> The Marvell Berlin BG4CT SoC has 4 TWSI which are compatible with the
> Synopsys DesignWare I2C driver. Add the corresponding nodes.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 52 
> ++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi 
> b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> index cca4c41..39d0676 100644
> --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> @@ -232,6 +232,32 @@
>   };
>   };
>  
> + i2c0: i2c@1400 {
> + compatible = "snps,designware-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x1400 0x100>;
> + clocks = <&clk CLK_APBCORE>;

This patch looks fine to me, except that clock node naming and
clock indices may change. We should really postpone this series
until we worked out clock.

Sebastian

> + i2c-sda-hold-time-ns = <35>;
> + i2c-sda-falling-time-ns = <425>;
> + i2c-scl-falling-time-ns = <205>;
> + interrupts = <4>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@1800 {
> + compatible = "snps,designware-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x1800 0x100>;
> + clocks = <&clk CLK_APBCORE>;
> + i2c-sda-hold-time-ns = <35>;
> + i2c-sda-falling-time-ns = <425>;
> + i2c-scl-falling-time-ns = <205>;
> + interrupts = <5>;
> + status = "disabled";
> + };
> +
>   aic: interrupt-controller@3800 {
>   compatible = "snps,dw-apb-ictl";
>   reg = <0x3800 0x30>;
> @@ -319,6 +345,32 @@
>   };
>   };
>  
> + i2c2: i2c@b000 {
> + compatible = "snps,designware-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xb000 0x100>;
> + clocks = <&osc>;
> + i2c-sda-hold-time-ns = <140>;
> + i2c-sda-falling-time-ns = <500>;
> + i2c-scl-falling-time-ns = <220>;
> + interrupts = <6>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@c000 {
> + compatible = "snps,designware-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xc000 0x100>;
> + clocks = <&osc>;
> + i2c-sda-hold-time-ns = <140>;
> + i2c-sda-falling-time-ns = <500>;
> + i2c-scl-falling-time-ns = <220>;
> + interrupts = <7>;
> + status = "disabled";
> + };
> +
>   uart0: uart@d000 {
>   compatible = "snps,dw-apb-uart";
>   reg = <0xd000 0x100>;
> 

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Re: [PATCH 2/2] arm64: dts: berlin4ct: enable all i2c nodes for the STB board

[Sebastian Hesselbarth]

On 20.11.2015 10:47, Jisheng Zhang wrote:
> Enable all i2c nodes for the Marvell berlin BG4CT STB board.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 50 
> +++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts 
> b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> index 348c37e..9e8e2e0 100644
> --- a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> +++ b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
> @@ -61,6 +61,56 @@
>   };
>  };
>  
> +&avio_pinctrl {
> + twsi1_pmux: twsi1-pmux {
> + groups = "TX_EDDC_SCL", "TX_EDDC_SDA";
> + function = "tx_eddc";
> + };

Please keep the pinmux sub-nodes in the SoC dtsi as long
as they are not strictly board specific, i.e. gpios.

> +};
> +
> +&i2c0 {
> + status = "okay";
> + pinctrl-0 = <&twsi0_pmux>;
> + pinctrl-names = "default";

If there is only one (or a default) pinctrl-0 option for i2c0,
you can also move it to the SoC dtsi.

> +};
> +
> +&i2c1 {
> + status = "okay";
> + pinctrl-0 = <&twsi1_pmux>;
> + pinctrl-names = "default";

ditto.

> +};
> +
> +&i2c2 {
> + status = "okay";
> + pinctrl-0 = <&twsi2_pmux>;
> + pinctrl-names = "default";

ditto.

> +};
> +
> +&i2c3 {
> + status = "okay";
> + pinctrl-0 = <&twsi3_pmux>;
> + pinctrl-names = "default";

ditto.

> +};
> +
> +&soc_pinctrl {
> + twsi0_pmux: twsi0-pmux {
> + groups = "TW0_SCL", "TW0_SDA";
> + function = "tw0";
> + };

Same comment about moving pinmux nodes to SoC dtsi.

> +};
> +
> +&system_pinctrl {
> + twsi2_pmux: twsi2-pmux {
> + groups = "SM_TW2_SCL", "SM_TW2_SDA";
> + function = "tw2";
> + };
> +
> + twsi3_pmux: twsi3-pmux {
> + groups = "SM_TW3_SCL", "SM_TW3_SDA";
> + function = "tw3";
> + };

ditto.

Sebastian

> +};
> +
>  &uart0 {
>   status = "okay";
>  };
> 

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Re: [PATCH v2 6/6] arm64: dts: berlin4ct: add pll and clock nodes

[Sebastian Hesselbarth]

On 20.11.2015 09:42, Jisheng Zhang wrote:
> Add syspll, mempll, cpupll, gateclk and berlin-clk nodes.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 
> ++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi 
> b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> index a4a1876..808a997 100644
> --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> @@ -42,6 +42,7 @@
>   * OTHER DEALINGS IN THE SOFTWARE.
>   */
>  
> +#include 
>  #include 
>  
>  / {
> @@ -135,6 +136,22 @@
>   interrupts =  IRQ_TYPE_LEVEL_HIGH)>;
>   };
>  
> + cpupll: cpupll {
> + compatible = "marvell,berlin-pll";
> + reg = <0x922000 0x14>, <0xea0710 4>;
> + #clock-cells = <0>;
> + clocks = <&osc>, <&clk CLK_CPUFASTREF>;
> + bypass-shift = /bits/ 8 <2>;
> + };
> +
> + mempll: mempll {
> + compatible = "marvell,berlin-pll";
> + reg = <0x940034 0x14>, <0xea0710 4>;

Whenever you see overlapping/repeating reg ranges, e.g. <0xea0710 4>
you can be sure you are not representing HW structure but driver
structure here.

Please merge clocks/gates/plls to a single clock complex node
and deal with the internals by using "simple-mfd" and "syscon" regmaps.

> + #clock-cells = <0>;
> + clocks = <&osc>, <&clk CLK_MEMFASTREF>;
> + bypass-shift = /bits/ 8 <1>;
> + };
> +
>   apb@e8 {
>   compatible = "simple-bus";
>   #address-cells = <1>;
> @@ -225,6 +242,27 @@
>   };
>   };
>  
> + syspll: syspll {
> + compatible = "marvell,berlin-pll";
> + reg = <0xea0200 0x14>, <0xea0710 4>;
> + #clock-cells = <0>;
> + clocks = <&osc>;
> + bypass-shift = /bits/ 8 <0>;
> + };
> +
> + gateclk: gateclk {
> + compatible = "marvell,berlin4ct-gateclk";
> + reg = <0xea0700 4>;
> + #clock-cells = <1>;
> + };
> +
> + clk: clk {
> + compatible = "marvell,berlin4ct-clk";
> + reg = <0xea0720 0x144>;

Looking at the reg ranges, I'd say that they are all clock related
and pretty close to each other:

gateclk: reg = <0xea0700 4>;
bypass:  reg = <0xea0710 4>;
clk: reg = <0xea0720 0x144>;

So, please just follow the OF/driver structure we already
have for Berlin2.

Sebastian

> + #clock-cells = <1>;
> + clocks = <&syspll>;
> + };
> +
>   soc_pinctrl: pin-controller@ea8000 {
>   compatible = "marvell,berlin4ct-soc-pinctrl";
>   reg = <0xea8000 0x14>;
> 

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Re: [PATCH 03/11] dt-bindings: clock: add NXP LPC32xx clock list for consumers

[Arnd Bergmann]

On Friday 20 November 2015 19:58:06 Vladimir Zapolskiy wrote:
> On 20.11.2015 15:56, Arnd Bergmann wrote:
> > On Friday 20 November 2015 03:05:03 Vladimir Zapolskiy wrote:
> >> +
> >> +/* LPC32XX System Control Block clocks */
> >> +#define LPC32XX_CLK_RTC0
> >> +#define LPC32XX_CLK_DMA1
> >> +#define LPC32XX_CLK_MLC2
> >> +#define LPC32XX_CLK_SLC3
> >> +#define LPC32XX_CLK_LCD4
> >> +#define LPC32XX_CLK_MAC5
> >> +#define LPC32XX_CLK_SD 6
> >> +#define LPC32XX_CLK_DDRAM  7
> >> +#define LPC32XX_CLK_SSP0   8
> >> +#define LPC32XX_CLK_SSP1   9
> >> +#define LPC32XX_CLK_UART3  10
> >> +#define LPC32XX_CLK_UART4  11
> >> +#define LPC32XX_CLK_UART5  12
> >> +#define LPC32XX_CLK_UART6  13
> >> +#define LPC32XX_CLK_IRDA   14
> >> +#define LPC32XX_CLK_I2C1   15
> >>
> > 
> > Any chance we can avoid the include file? This is going to make it really
> > hard to merge everything in one merge window with the dependencies between
> > the driver, the bindings and the platform code.
> 
> I see only one option to avoid this commit, namely squash it with the
> CCF driver and merge it before making changes in DTS.
> 
> However I suppose ARM trees won't be synced on clk tree, so probably it
> won't simplify maintainer's work.

I think the best way for this would then be to have one git branch that
contains the binding header, and base the other patches on top of that
branch, for both the changes going into the clk git and arm-soc.

That way, both have the commit we need, but we don't get duplicate
commits when they are both merged into mainline.

> > If there is a way to describe the clocks based on numbers from the
> > data sheet instead of making up your own, that makes life much
> > easier for us.
> 
> There are no any clock numbers in the datasheet, unfortunately.

I was thinking that maybe there would be a logical numbering based
on the register layout, e.g. a tuple of register index and bit position,
but it seems that the mmio area is too irregular to make that easy.

Arnd
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Re: [PATCH v2 4/6] clk: berlin: add clk support for berlin4ct

[Sebastian Hesselbarth]

On 20.11.2015 09:42, Jisheng Zhang wrote:
> This patch supports the gateclk and berlin-clk in berlin4ct SoC.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  drivers/clk/berlin/Makefile|  2 +-
>  drivers/clk/berlin/clk-berlin4ct.c | 97 
> ++
>  2 files changed, 98 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/berlin/clk-berlin4ct.c
> 
> diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
> index fc92151..accfc3a 100644
> --- a/drivers/clk/berlin/Makefile
> +++ b/drivers/clk/berlin/Makefile
> @@ -1,5 +1,5 @@
>  obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
> -obj-y += pll.o clk.o gate.o
> +obj-y += pll.o clk.o gate.o clk-berlin4ct.o

This will always compile clk-berlin4ct unconditionally on bg2x too.

Also, keep the naming style.

Sebastian

>  obj-$(CONFIG_MACH_BERLIN_BG2)+= bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2CD)  += bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2Q)   += bg2q.o
> diff --git a/drivers/clk/berlin/clk-berlin4ct.c 
> b/drivers/clk/berlin/clk-berlin4ct.c
> new file mode 100644
> index 000..0d994a4
> --- /dev/null
> +++ b/drivers/clk/berlin/clk-berlin4ct.c
> @@ -0,0 +1,97 @@
> +/*
> + * Copyright (c) 2015 Marvell Technology Group Ltd.
> + *
> + * Author: Jisheng Zhang 
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include 
> +
> +#include "clk.h"
> +
> +static struct clk_onecell_data gateclk_data;
> +static struct clk_onecell_data clk_data;
> +
> +static const struct gateclk_desc berlin4ct_gates[] __initconst = {
> + { "tspsysclk",  "perifsysclk",  0 },
> + { "usb0coreclk","perifsysclk",  1 },
> + { "zspsysclk",  "perifsysclk",  2 },
> + { "sdiosysclk", "perifsysclk",  3 },
> + { "ethcoreclk", "perifsysclk",  4 },
> + { "pcie0sys",   "perifsysclk",  6 },
> + { "sata0core",  "perifsysclk",  7 },
> + { "nfcsysclk",  "perifsysclk",  8 },
> + { "emmcsysclk", "perifsysclk",  9 },
> + { "ihb0sysclk", "perifsysclk",  10 },
> +};
> +
> +static void __init berlin4ct_gateclk_setup(struct device_node *np)
> +{
> + int n = ARRAY_SIZE(berlin4ct_gates);
> +
> + berlin_gateclk_setup(np, berlin4ct_gates, &gateclk_data, n);
> +}
> +CLK_OF_DECLARE(berlin4ct_gateclk, "marvell,berlin4ct-gateclk",
> +berlin4ct_gateclk_setup);
> +
> +static const struct clk_desc berlin4ct_descs[] __initconst = {
> + { "cpufastrefclk",  0x0 },
> + { "memfastrefclk",  0x4 },
> + { "cfgclk", 0x20,   CLK_IGNORE_UNUSED },
> + { "perifsysclk",0x24,   CLK_IGNORE_UNUSED },
> + { "hbclk",  0x28 },
> + { "atbclk", 0x2c },
> + { "decoderclk", 0x40 },
> + { "decoderm3clk",   0x44 },
> + { "decoderpcubeclk",0x48 },
> + { "encoderclk", 0x4c },
> + { "ovpcoreclk", 0x50 },
> + { "gfx2dcoreclk",   0x60 },
> + { "gfx3dcoreclk",   0x64 },
> + { "gfx3dshclk", 0x68 },
> + { "gfx3dsysclk",0x6c },
> + { "gfx2dsysclk",0x70 },
> + { "aviosysclk", 0x80 },
> + { "vppsysclk",  0x84 },
> + { "eddcclk",0x88 },
> + { "aviobiuclk", 0x8c },
> + { "zspclk", 0xa0 },
> + { "tspclk", 0xc0 },
> + { "tsprefclk",  0xc4 },
> + { "ndsclk", 0xc8 },
> + { "nocsclk",0xcc },
> + { "apbcoreclk", 0xd0,   CLK_IGNORE_UNUSED },
> + { "emmcclk",0xe0 },
> + { "sd0clk", 0xe4 },
> + { "sd1clk", 0xe8 },
> + { "dllmstrefclk",   0xec },
> + { "gethrgmiiclk",   0xf0 },
> + { "gethrgmiisysclk",0xf4 },
> + { "usim0clk",   0x100 },
> + { "pcietestclk",0x110 },
> + { "usb2testclk",0x120 },
> + { "usb3testclk",0x124 },
> + { "usb3coreclk",0x128 },
> + { "nfceccclk",  0x130 },
> + { "bcmclk", 0x140 },
> +};
> +
> +static void __init berlin4ct_clk_setup(struct device_node *np)
> +{
> + int n = ARRAY_SIZE(berlin4ct_descs);
> +
> + berlin_clk_setup(np, berlin4ct_descs, &clk_data, n);
> +}
> +CLK_OF_DECLARE(berlin4ct_clk, "marvell,berlin4ct-clk",
> +berlin4ct_clk_setup);
> 

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Re: [PATCH v2 2/6] clk: berlin: add common clk driver for newer SoCs

[Sebastian Hesselbarth]

On 20.11.2015 09:42, Jisheng Zhang wrote:
> Add common clk driver for Marvell SoCs newer than BG2, BG2CD, BG2Q.
> berlin_clk_setup() is provided to setup and register such kind of clks.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  drivers/clk/berlin/Makefile |   2 +-
>  drivers/clk/berlin/clk.c| 203 
> 
>  drivers/clk/berlin/clk.h|  33 +++
>  3 files changed, 237 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/berlin/clk.c
>  create mode 100644 drivers/clk/berlin/clk.h
> 
> diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
> index eee42b0..ee2e09d 100644
> --- a/drivers/clk/berlin/Makefile
> +++ b/drivers/clk/berlin/Makefile
> @@ -1,5 +1,5 @@
>  obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
> -obj-y += pll.o
> +obj-y += pll.o clk.o

Same comment about the naming convention.

>  obj-$(CONFIG_MACH_BERLIN_BG2)+= bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2CD)  += bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2Q)   += bg2q.o
> diff --git a/drivers/clk/berlin/clk.c b/drivers/clk/berlin/clk.c
> new file mode 100644
> index 000..70f2b9d
> --- /dev/null
> +++ b/drivers/clk/berlin/clk.c
> @@ -0,0 +1,203 @@
> +/*
> + * Copyright (c) 2015 Marvell Technology Group Ltd.
> + *
> + * Author: Jisheng Zhang 
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define CLKEN(1 << 0)

#define CLKEN   BIT(0)

> +#define CLKPLLSEL_MASK   7

Please use hex numbers for the mask.

> +#define CLKPLLSEL_SHIFT  1
> +#define CLKPLLSWITCH (1 << 4)
> +#define CLKSWITCH(1 << 5)
> +#define CLKD3SWITCH  (1 << 6)

BIT() again.

> +#define CLKSEL_MASK  7

Hex again.

> +#define CLKSEL_SHIFT 7
> +
> +#define CLK_SOURCE_MAX   5
> +
> +struct berlin_clk {
> + struct clk_hw hw;
> + void __iomem *base;
> +};
> +
> +#define to_berlin_clk(hw)container_of(hw, struct berlin_clk, hw)
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};

Hmm, this pretty much looks like berlin2-div dividers...

> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, divider;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + if (val & CLKD3SWITCH)
> + divider = 3;

and this looks like berlin2-div structure, doesn't it?

Again, please reuse what is already available.

Sebastian

> + else {
> + if (val & CLKSWITCH) {
> + val >>= CLKSEL_SHIFT;
> + val &= CLKSEL_MASK;
> + divider = clk_div[val];
> + } else
> + divider = 1;
> + }
> +
> + return parent_rate / divider;
> +}
> +
> +static u8 berlin_clk_get_parent(struct clk_hw *hw)
> +{
> + u32 val;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + if (val & CLKPLLSWITCH) {
> + val >>= CLKPLLSEL_SHIFT;
> + val &= CLKPLLSEL_MASK;
> + return val;
> + }
> +
> + return 0;
> +}
> +
> +static int berlin_clk_enable(struct clk_hw *hw)
> +{
> + u32 val;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + val |= CLKEN;
> + writel_relaxed(val, clk->base);
> +
> + return 0;
> +}
> +
> +static void berlin_clk_disable(struct clk_hw *hw)
> +{
> + u32 val;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + val &= ~CLKEN;
> + writel_relaxed(val, clk->base);
> +}
> +
> +static int berlin_clk_is_enabled(struct clk_hw *hw)
> +{
> + u32 val;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + val &= CLKEN;
> +
> + return val ? 1 : 0;
> +}
> +
> +static const struct clk_ops berlin_clk_ops = {
> + .recalc_rate= berlin_clk_recalc_rate,
> + .get_parent = berlin_clk_get_parent,
> + .enable = berlin_clk_enable,
> + .disable= berlin_clk_disable,
> + .is_enabled = berlin_clk_is_enabled,
> +};
> +
> +static struct clk * __init
> +berlin_clk_register(const char *name, int num_parents,
> + const char **parent_names, u

Re: [PATCH v2 1/6] clk: berlin: add common pll driver

[Sebastian Hesselbarth]

On 20.11.2015 09:42, Jisheng Zhang wrote:
> Add pll driver for Marvell SoCs newer than BG2, BG2CD, BG2Q.
> 
> Signed-off-by: Jisheng Zhang 
> ---
>  drivers/clk/berlin/Makefile |   1 +
>  drivers/clk/berlin/pll.c| 133 
> 
>  2 files changed, 134 insertions(+)
>  create mode 100644 drivers/clk/berlin/pll.c
> 
> diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
> index 2a36ab7..eee42b0 100644
> --- a/drivers/clk/berlin/Makefile
> +++ b/drivers/clk/berlin/Makefile
> @@ -1,4 +1,5 @@
>  obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
> +obj-y += pll.o

Jisheng,

please keep the naming style of files as we already have,
e.g. at least name the files for this driver berlin4-pll.

Even better you find the differences and merge it with
the berlin2-pll driver.

In general, I am not going to Ack any Berlin clock drivers
that expose the clock tree in any way. We recently merged
the Berlin2 clock stuff to a common OF node, I am not going
through the same mess for BG4 again.

>  obj-$(CONFIG_MACH_BERLIN_BG2)+= bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2CD)  += bg2.o
>  obj-$(CONFIG_MACH_BERLIN_BG2Q)   += bg2q.o
> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 000..435445e
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,133 @@
> +/*
> + * Copyright (c) 2015 Marvell Technology Group Ltd.
> + *
> + * Author: Jisheng Zhang 
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define PLL_CTRL00x0
> +#define PLL_CTRL10x4
> +#define PLL_CTRL20x8
> +#define PLL_CTRL30xC
> +#define PLL_CTRL40x10
> +#define PLL_STATUS   0x14
> +
> +#define PLL_SOURCE_MAX   2
> +
> +struct berlin_pll {
> + struct clk_hw   hw;
> + void __iomem*ctrl;
> + void __iomem*bypass;
> + u8  bypass_shift;
> +};
> +
> +#define to_berlin_pll(hw)   container_of(hw, struct berlin_pll, hw)
> +
> +static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, fbdiv, rfdiv, vcodivsel, bypass;
> + struct berlin_pll *pll = to_berlin_pll(hw);
> +
> + bypass = readl_relaxed(pll->bypass);
> + if (bypass & (1 << pll->bypass_shift))
> + return parent_rate;

Bypass could be modelled as a ccf clock-mux:

REF ---+|\
   |_   | |-- OUT
   +---| PLL |--|/

Please reuse what is already available.

> + val = readl_relaxed(pll->ctrl + PLL_CTRL0);
> + fbdiv = (val >> 12) & 0x1FF;
> + rfdiv = (val >> 3) & 0x1FF;

Please get rid of any magic numbers.

> + val = readl_relaxed(pll->ctrl + PLL_CTRL1);
> + vcodivsel = (val >> 9) & 0x7;
> + return parent_rate * fbdiv * 4 / rfdiv /
> + (1 << vcodivsel);

A comment at the top of recalc_rate how output frequency is
calculated would be great.

> +}
> +
> +static u8 berlin_pll_get_parent(struct clk_hw *hw)
> +{
> + struct berlin_pll *pll = to_berlin_pll(hw);
> + u32 bypass = readl_relaxed(pll->bypass);
> +
> + return !!(bypass & (1 << pll->bypass_shift));
> +}
> +
> +static const struct clk_ops berlin_pll_ops = {
> + .recalc_rate= berlin_pll_recalc_rate,
> + .get_parent = berlin_pll_get_parent,
> +};
> +
> +static void __init berlin_pll_setup(struct device_node *np)
> +{
> + struct clk_init_data init;
> + struct berlin_pll *pll;
> + const char *parent_names[PLL_SOURCE_MAX];
> + struct clk *clk;
> + int ret, num_parents;
> + u8 bypass_shift;
> +
> + num_parents = of_clk_get_parent_count(np);
> + if (num_parents <= 0 || num_parents > PLL_SOURCE_MAX)
> + return;
> +
> + ret = of_property_read_u8(np, "bypass-shift", &bypass_shift);
> + if (ret)
> + return;

The name "bypass" implies you can either choose to output the PLL
generated clock or pass the parent clock, i.e. bypass the PLL.

How can you choose from two parents then?

> + of_clk_parent_fill(np, parent_names, num_parents);
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return;
> +
> + pll->ctrl = of_iomap(np, 0);
> + if (WARN_ON(!pll->ctrl))
> + goto err_iomap_ctrl;
> +
> + pll->bypass = of_i

Re: [PATCH RESEND 1/8] arm: dts: berlin2q: add watchdog nodes

[Sebastian Hesselbarth]

On 20.11.2015 04:34, Jisheng Zhang wrote:
> On Thu, 19 Nov 2015 21:47:05 +0100
> Sebastian Hesselbarth wrote:
>> On 16.11.2015 12:09, Jisheng Zhang wrote:
>>> The Marvell Berlin BG2Q has 3 watchdogs which are compatible with the
>>> snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
>>> corresponding device tree nodes.
>>>
>>> Signed-off-by: Jisheng Zhang 
>>> ---
>>>  arch/arm/boot/dts/berlin2q.dtsi | 24 
>>>  1 file changed, 24 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi 
>>> b/arch/arm/boot/dts/berlin2q.dtsi
>>> index a3ecde5..fac4315 100644
>>> --- a/arch/arm/boot/dts/berlin2q.dtsi
>>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>>> @@ -483,6 +483,30 @@
>>> ranges = <0 0xfc 0x1>;
>>> interrupt-parent = <&sic>;
>>>  
>>> +   wdt0: watchdog@1000 {
>>> +   compatible = "snps,dw-wdt";
>>> +   reg = <0x1000 0x100>;
>>> +   clocks = <&refclk>;
>>> +   interrupts = <0>;
>>> +   status = "disabled";  
>>
>> as the watchdogs are internal and cannot be clock gated
>> at all, how about we remove the status = "disabled" and
>> make them always available?
> 
> there are two issues here:
> 
> 1. the dw-wdt can't support multiple variants now. I have rewrite the driver
> with watchdog core supplied framework, but the patch isn't sent out and
> may be need time to clean up and review.

Ok.

> 2. not all dw-wdt devices are available and functional. This depends on
> board design and configuration.

I understand that "board design and configuration" may hinder the wdt
to issue a hard reset. But all others are able to issue a soft reset
or just an interrupt, right?

So, I still don't see why we should disable wdt nodes by default
except for the driver issue above.

> So IMHO status=disabled and patch5-8 is necessary, what do you think?

No. I'd agree to enable wdt0 by default and leave wdt[1,2] disabled
because of the driver issue. Patches 5-8 only enable wdt0 anyway.

As soon as the driver issue is resolved, we enable all wdt nodes
unconditionally.

Sebastian

>> I have applied patches 1-4 with the status property removed.
>> This also renders patches 5-8 useless.
>>
>> So, for now tentatively
>>
>> Appled to berlin/dt and berlin64/dt respectivly
>>
>> with status property removed.
>>
>> Sebastian
>>
> 

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Re: [PATCH 09/11] clk: lpc32xx: add common clock framework driver

[Arnd Bergmann]

On Friday 20 November 2015 20:07:46 Vladimir Zapolskiy wrote:
> On 20.11.2015 16:04, Arnd Bergmann wrote:
> > On Friday 20 November 2015 03:05:09 Vladimir Zapolskiy wrote:
> >> +
> >> +struct clk_proto_t {
> >> +   const char *name;
> >> +   const u8 parents[LPC32XX_CLK_PARENTS_MAX];
> >> +   u8 num_parents;
> >> +   unsigned long flags;
> >> +};
> >> +
> >> +#define CLK_PREFIX(LITERAL)LPC32XX_CLK_ ## LITERAL
> >> +#define NUMARGS(...)   (sizeof((int[]){__VA_ARGS__})/sizeof(int))
> >> +
> >> +#define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...)   \
> >> +   [CLK_PREFIX(_idx)] = {  \
> >> +   .name = #_name, \
> >> +   .flags = _flags,\
> >> +   .parents = { __VA_ARGS__ }, \
> >> +   .num_parents = NUMARGS(__VA_ARGS__),\
> >> +}
> >> +
> > 
> > Try to not outsmart yourself with the macros. It's better to avoid
> > string concatenation so it's possible to grep for uses of some
> > constant.
> > 
> > I would probably not use a macro at all here and just open-code the
> > entire table. If you ensure that '0' is not a valid parent, then
> > you can leave out the .num_parents field and just look for the
> > zero-termination.
> 
> Macros are here for simplicity, code size reduction and to avoid some
> stupid mistakes like different number of .parents and .num_parents.
> 
> I believe macro unwrapping in this code will add another 1000 LoC and
> will result in quite unreadable and less maintainable code.

I mean specifically the macro above:

static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = {
+   LPC32XX_CLK_DEFINE(XTAL, xtal, 0x0),
+   LPC32XX_CLK_DEFINE(XTAL_32K, xtal_32k, 0x0),
+
+   LPC32XX_CLK_DEFINE(RTC, rtc, 0x0, LPC32XX_CLK_XTAL_32K),
+   LPC32XX_CLK_DEFINE(OSC, osc, CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
+   LPC32XX_CLK_DEFINE(SYS, sys, CLK_IGNORE_UNUSED,
+   LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
+   LPC32XX_CLK_DEFINE(PLL397X, pll_397x, CLK_IGNORE_UNUSED,
+   LPC32XX_CLK_RTC),

can become

static const struct clk_proto_t clk_proto[] __initconst = {
[LPC32XX_CLK_XTAL]  = { "xtal" },
[LPC32XX_CLK_XTAL_32K]  = { "xtal_32k" },
[LPC32XX_CLK_RTC]   = { "rtc",
.parents = { LPC32XX_CLK_XTAL_32K, 0 } },
[LPC32XX_CLK_OSC]   = { "osc", CLK_IGNORE_UNUSED,
.parents = { LPC32XX_CLK_XTAL, 0 } },
[LPC32XX_CLK_SYS]   = { "sys", CLK_IGNORE_UNUSED,
.parents = { LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X, 0) },
[LPC32XX_CLK_PLL397X]   = { "pll_397x", CLK_IGNORE_UNUSED,
.parents = { LPC32XX_CLK_RTC, 0 },

Not harder to read at all, not really longer, but easier to grep for.

Arnd
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Re: [PATCH v2 8/8] arm: dts: lpc32xx: move USB controller subdevices into own device node

[Vladimir Zapolskiy]

On 20.11.2015 21:47, Rob Herring wrote:
> On Sat, Oct 17, 2015 at 4:35 PM, Vladimir Zapolskiy  wrote:
>> NXP LPC32xx SoC has one USB OTG controller, which is supposed to work
>> with an external phy (default is NXP ISP1301).
>>
>> Practically the USB controller contains 5 subdevices:
>> - host controller   0x3102  -- 0x3102 00FF
>> - OTG controller0x3102 0100 -- 0x3102 01FF
>> - device controller 0x3102 0200 -- 0x3102 02FF
>> - I2C controller0x3102 0300 -- 0x3102 03FF
>> - clock controller  0x3102 0F00 -- 0x3102 0FFF
> 
> [...]
> 
>> -   /*
>> -* Enable either ohci or usbd (gadget)!
>> -*/
>> -   ohci: ohci@3102 {
>> -   compatible = "nxp,ohci-nxp", "usb-ohci";
>> -   reg = <0x3102 0x300>;
>> -   interrupts = <0x3b 0>;
>> -   status = "disabled";
>> -   };
>> +   usb {
>> +   #address-cells = <1>;
>> +   #size-cells = <1>;
>> +   compatible = "simple-bus";
>> +   ranges = <0x0 0x3102 0x1000>;
>>
>> -   usbd: usbd@3102 {
>> -   compatible = "nxp,lpc3220-udc";
>> -   reg = <0x3102 0x300>;
>> -   interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
>> -   status = "disabled";
>> +   /*
>> +* Enable either ohci or usbd (gadget)!
>> +*/
>> +   ohci: ohci@0 {
>> +   compatible = "nxp,ohci-nxp", "usb-ohci";
>> +   reg = <0x0 0x300>;
>> +   interrupts = <0x3b 0>;
>> +   status = "disabled";
>> +   };
>> +
>> +   usbd: usbd@0 {
>> +   compatible = "nxp,lpc3220-udc";
>> +   reg = <0x0 0x300>;
> 
> Not a result of this change, but you are overlapping addresses. Please
> don't do that. It causes problems adding device resources into the
> resource tree (i.e. request_resource).
> 

As you noticed this is legacy code, it will be corrected after fixing
USB host and device drivers, and this is in long term plans. USB changes
require at least CCF and IRQ chip changes applied.

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With best wishes,
Vladimir
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Re: [PATCH 01/11] dt-bindings: clock: add description of LPC32xx clock controller

[Arnd Bergmann]

On Friday 20 November 2015 20:01:00 Vladimir Zapolskiy wrote:
> > 
> > Please use a specific model number without 'xx' wildcards. If you have
> > multiple chips that are mutually compatible, pick one as the base number
> > and then list the others as more specific instances, like
> > 
> >   compatible = "nxp,lpc3250-clk", "nxp,lpc3220-clk";
> 
> Do you ask me to change a title? You may see that compatible property
> does not contain any wildcards?
> 

Nevermind, I saw so many 'xx's that I didn't notice you got the
important one right.

Arnd
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Re: [linux-sunxi] [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC

[Priit Laes]

On Sun, 2015-11-15 at 20:46 +0100, Hans de Goede wrote:
> From: Reinder de Haan 
> 
> Note this commit only adds support for phys 1-3, phy 0, the otg phy,
> is
> not yet (fully) supported after this commit.


This patch seems to be causing following compile warning:

In file included from include/linux/io.h:25:0,
 from drivers/phy/phy-sun4i-usb.c:28:
drivers/phy/phy-sun4i-usb.c: In function 'sun4i_usb_phy_write': 
./arch/arm/include/asm/io.h:94:2: warning: 'phyctl' may be used uninitialized 
in this function [-Wmaybe-uni
nitialized]
  asm volatile("strb %1, %0"
  ^
drivers/phy/phy-sun4i-usb.c:172:8: note: 'phyctl' was declared here
  void *phyctl;

> 
> Signed-off-by: Reinder de Haan 
> Signed-off-by: Hans de Goede 
> ---
>  .../devicetree/bindings/phy/sun4i-usb-phy.txt  |  1 +
>  drivers/phy/phy-sun4i-usb.c| 67
> +-
>  2 files changed, 53 insertions(+), 15 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 0cebf74..95736d7 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -9,6 +9,7 @@ Required properties:
>    * allwinner,sun7i-a20-usb-phy
>    * allwinner,sun8i-a23-usb-phy
>    * allwinner,sun8i-a33-usb-phy
> +  * allwinner,sun8i-h3-usb-phy
>  - reg : a list of offset + length pairs
>  - reg-names :
>    * "phy_ctrl"
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-
> usb.c
> index b12964b..17f97ab 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -46,6 +46,9 @@
>  #define REG_PHYBIST  0x08
>  #define REG_PHYTUNE  0x0c
>  #define REG_PHYCTL_A33   0x10
> +#define REG_PHY_UNK_H3   0x20
> +
> +#define REG_PMU_UNK_H3   0x10
>  
>  #define PHYCTL_DATA  BIT(7)
>  
> @@ -79,7 +82,7 @@
>  #define PHY_DISCON_TH_SEL0x2a
>  #define PHY_SQUELCH_DETECT   0x3c
>  
> -#define MAX_PHYS 3
> +#define MAX_PHYS 4
>  
>  /*
>   * Note do not raise the debounce time, we must report Vusb high
> within 100ms
> @@ -88,12 +91,19 @@
>  #define DEBOUNCE_TIMEmsecs_to_jiffies(50)
>  #define POLL_TIMEmsecs_to_jiffies(250)
>  
> +enum sun4i_usb_phy_type {
> + sun4i_a10_phy,
> + sun8i_a33_phy,
> + sun8i_h3_phy
> +};
> +
>  struct sun4i_usb_phy_data {
> + struct device *dev;
>   void __iomem *base;
>   struct mutex mutex;
>   int num_phys;
>   u32 disc_thresh;
> - bool has_a33_phyctl;
> + enum sun4i_usb_phy_type type;
>   struct sun4i_usb_phy {
>   struct phy *phy;
>   void __iomem *pmu;
> @@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct
> sun4i_usb_phy *phy, u32 addr, u32 data,
>  
>   mutex_lock(&phy_data->mutex);
>  
> - if (phy_data->has_a33_phyctl) {
> + switch (phy_data->type) {
> + case sun4i_a10_phy:
> + phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_a33_phy:
>   phyctl = phy_data->base + REG_PHYCTL_A33;
>   /* A33 needs us to set phyctl to 0 explicitly */
>   writel(0, phyctl);
> - } else {
> - phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_h3_phy:
> + dev_err(phy_data->dev, "H3 usb_phy_write is not
> supported\n");
> + break;
>   }
>  
>   for (i = 0; i < len; i++) {
> @@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>   struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
>   struct sun4i_usb_phy_data *data =
> to_sun4i_usb_phy_data(phy);
>   int ret;
> + u32 val;
>  
>   ret = clk_prepare_enable(phy->clk);
>   if (ret)
> @@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>   return ret;
>   }
>  
> - /* Enable USB 45 Ohm resistor calibration */
> - if (phy->index == 0)
> - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> + if (data->type == sun8i_h3_phy) {
> + if (phy->index == 0) {
> + val = readl(data->base + REG_PHY_UNK_H3);
> + writel(val & ~1, data->base +
> REG_PHY_UNK_H3);
> + }
> +
> + val = readl(phy->pmu + REG_PMU_UNK_H3);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> + } else {
> + /* Enable USB 45 Ohm resistor calibration */
> + if (phy->index == 0)
> + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
> 0x01, 1);
>  
> - /* Adjust PHY's magnitude and rate */
> - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> + /* Adjust PHY's magnitude and rate */
> + sun4i_usb

Re: [PATCH v2 10/10] dt-bindings: Add DSIv2 documentation

[Rob Herring]

+Stephen

On Wed, Nov 18, 2015 at 9:24 AM, Archit Taneja  wrote:
> Hi Rob,
>
> On 11/18/2015 6:48 PM, Rob Herring wrote:
>>
>> +dt list
>>
>> On Wed, Nov 18, 2015 at 4:55 AM, Archit Taneja 
>> wrote:
>>>
>>> Add additional property info needed for DSIv2 DT.
>>
>>
>> Please use get_maintainers.pl.
>
>
> Sorry about that, missed out doing that posting this time.
>
>>
>>> Signed-off-by: Archit Taneja 
>>> ---
>>>   Documentation/devicetree/bindings/display/msm/dsi.txt | 10 +-
>>>   1 file changed, 9 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>> b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>> index f344b9e..ca65a34 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>> @@ -13,18 +13,25 @@ Required properties:
>>>   - power-domains: Should be <&mmcc MDSS_GDSC>.
>>>   - clocks: device clocks
>>> See Documentation/devicetree/bindings/clocks/clock-bindings.txt for
>>> details.
>>> -- clock-names: the following clocks are required:
>>> +- clock-names: these vary based on the DSI version. For DSI6G:
>>> * "bus_clk"
>>> * "byte_clk"
>>> +  * "byte_clk_src
>>
>>
>> This sounds like the parent of byte_clk. Is that really a clock within
>> the block?
>
>
> byte_clk_src isn't in the block, but byte_clk_src's parent is one of
> the PLLs in this block. We take this clock so that we can re-parent
> it to an appropriate PLL. The decision of what PLL to choose needs to
> be done by the DSI block's driver.

Seems like abuse to me. The list of clocks should match what are
inputs to the block, not what the driver happens to need. Without a
full understanding of the clock tree here, I don't have a suggestion.
Maybe Stephen does.

>>> * "core_clk"
>>> * "core_mmss_clk"
>>> * "iface_clk"
>>> * "mdp_core_clk"
>>> * "pixel_clk"
>>> +  * "pixel_clk_src"
>>> +  For DSIv2, we need a few more:
>>
>>
>> What is the overall order of clocks? As listed?
>
>
> Order in which the driver does clk_get? It uses the clock
> name to get each one individually, so the order doesn't matter
> as such.

The order in DT. You may use the names, but the order should still be specified.

Rob
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Re: [PATCH v2 8/8] arm: dts: lpc32xx: move USB controller subdevices into own device node

[Rob Herring]

On Sat, Oct 17, 2015 at 4:35 PM, Vladimir Zapolskiy  wrote:
> NXP LPC32xx SoC has one USB OTG controller, which is supposed to work
> with an external phy (default is NXP ISP1301).
>
> Practically the USB controller contains 5 subdevices:
> - host controller   0x3102  -- 0x3102 00FF
> - OTG controller0x3102 0100 -- 0x3102 01FF
> - device controller 0x3102 0200 -- 0x3102 02FF
> - I2C controller0x3102 0300 -- 0x3102 03FF
> - clock controller  0x3102 0F00 -- 0x3102 0FFF

[...]

> -   /*
> -* Enable either ohci or usbd (gadget)!
> -*/
> -   ohci: ohci@3102 {
> -   compatible = "nxp,ohci-nxp", "usb-ohci";
> -   reg = <0x3102 0x300>;
> -   interrupts = <0x3b 0>;
> -   status = "disabled";
> -   };
> +   usb {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   compatible = "simple-bus";
> +   ranges = <0x0 0x3102 0x1000>;
>
> -   usbd: usbd@3102 {
> -   compatible = "nxp,lpc3220-udc";
> -   reg = <0x3102 0x300>;
> -   interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
> -   status = "disabled";
> +   /*
> +* Enable either ohci or usbd (gadget)!
> +*/
> +   ohci: ohci@0 {
> +   compatible = "nxp,ohci-nxp", "usb-ohci";
> +   reg = <0x0 0x300>;
> +   interrupts = <0x3b 0>;
> +   status = "disabled";
> +   };
> +
> +   usbd: usbd@0 {
> +   compatible = "nxp,lpc3220-udc";
> +   reg = <0x0 0x300>;

Not a result of this change, but you are overlapping addresses. Please
don't do that. It causes problems adding device resources into the
resource tree (i.e. request_resource).

Rob
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Re: [PATCH v1 3/7] mtd: fsl-quadspi: Support both 24- and 32-bit addressed commands.

[Cory Tusar]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 11/20/2015 02:24 PM, Brian Norris wrote:
> Cory and Han,
> 
> Did this series get dropped on the floor? I recall Han arguing
> previously that this controller is always used with two identical chips.
> But apparently that is not the case.
> 
> If this request is not truly dead, I'd appreciate it if Han could
> review/test.

Hi Brian,

Pretty sure this series will not apply & work cleanly with 4.4-rc1.

IIRC, there were also some changes (apart from these) that reworked
clocking and resulted in a fault the last time I tested this on actual
hardware.

I can see about rebasing and updating if there's additional interest.
I don't know that there's anything about the controller itself that
would preclude using different chips, apart from the overhead of having
to reconfigure the LUT when switching between devices...

We'd had a board which only included a device on QSPI0_B_CS0, whereas
the driver assumed that the channels would be populated in order (e.g.
QSPI0_A_CS0 first and then QSPI0_B_CS0)...that configuration was what
originally drove my changes.

- -Cory


> On Wed, Jul 08, 2015 at 04:21:17PM -0400, Cory Tusar wrote:
>> The current fsl-quadspi implementation assumes that all connected
>> devices are of the same size and type.  This commit adds lookup table
>> entries for both 24- and 32-bit addressed variants of the read, sector
>> erase, and page program operations as a precursor to later changes which
>> generalize the flash layout parsing logic and allow for non-contiguous
>> and non-homogeneous chip combinations.
>>
>> Signed-off-by: Cory Tusar 
>> ---
>>  drivers/mtd/spi-nor/fsl-quadspi.c | 116 
>> --
>>  1 file changed, 60 insertions(+), 56 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
>> b/drivers/mtd/spi-nor/fsl-quadspi.c
>> index 52a872f..4b8038b 100644
>> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
>> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
>> @@ -178,18 +178,21 @@
>>  #define QUADSPI_LUT_NUM 64
>>  
>>  /* SEQID -- we can have 16 seqids at most. */
>> -#define SEQID_QUAD_READ 0
>> -#define SEQID_WREN  1
>> -#define SEQID_WRDI  2
>> -#define SEQID_RDSR  3
>> -#define SEQID_SE4
>> -#define SEQID_CHIP_ERASE5
>> -#define SEQID_PP6
>> -#define SEQID_RDID  7
>> -#define SEQID_WRSR  8
>> -#define SEQID_RDCR  9
>> -#define SEQID_EN4B  10
>> -#define SEQID_BRWR  11
>> +#define SEQID_QUAD_READ_24  0
>> +#define SEQID_QUAD_READ_32  1
>> +#define SEQID_WREN  2
>> +#define SEQID_WRDI  3
>> +#define SEQID_RDSR  4
>> +#define SEQID_SE_24 5
>> +#define SEQID_SE_32 5
>> +#define SEQID_CHIP_ERASE7
>> +#define SEQID_PP_24 8
>> +#define SEQID_PP_32 8
>> +#define SEQID_RDID  9
>> +#define SEQID_WRSR  10
>> +#define SEQID_RDCR  11
>> +#define SEQID_EN4B  12
>> +#define SEQID_BRWR  13
>>  
>>  enum fsl_qspi_devtype {
>>  FSL_QUADSPI_VYBRID,
>> @@ -287,7 +290,6 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>>  void __iomem *base = q->iobase;
>>  int rxfifo = q->devtype_data->rxfifo;
>>  u32 lut_base;
>> -u8 cmd, addrlen, dummy;
>>  int i;
>>  
>>  fsl_qspi_unlock_lut(q);
>> @@ -297,22 +299,16 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>>  writel(0, base + QUADSPI_LUT_BASE + i * 4);
>>  
>>  /* Quad Read */
>> -lut_base = SEQID_QUAD_READ * 4;
>> -
>> -if (q->nor_size <= SZ_16M) {
>> -cmd = SPINOR_OP_READ_1_1_4;
>> -addrlen = ADDR24BIT;
>> -dummy = 8;
>> -} else {
>> -/* use the 4-byte address */
>> -cmd = SPINOR_OP_READ_1_1_4;
>> -addrlen = ADDR32BIT;
>> -dummy = 8;
>> -}
>> +lut_base = SEQID_QUAD_READ_24 * 4;
>> +writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, 
>> ADDR24BIT),
>> +base + QUADSPI_LUT(lut_base));
>> +writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
>> +base + QUADSPI_LUT(lut_base + 1));
>>  
>> -writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
>> +lut_base = SEQID_QUAD_READ_32 * 4;
>> +writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, 
>> ADDR32BIT),
>>  base + QUADSPI_LUT(lut_base));
>> -writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
>> +writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
>>  base + QUADSPI_LUT(lut_base + 1));
>>  
>>  /* Write enable */
>> @@ -320,18 +316,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>>  writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
>>  
>>  /* Page Program */
>> -lut_base = SEQID_PP * 4;
>> -
>> -if (q->nor_size <= SZ_16M) {
>> -cmd = SPINOR_OP_PP;
>> -   

[PATCH V4 net-next 3/5] net:hns: Add Hip06 "TSO(TCP Segment Offload)" support HNS Driver

[Salil Mehta]

This patch adds the support of "TSO (TCP Segment Offload)" feature
provided by the Hip06 ethernet hardware to the HNS ethernet
driver.

Enabling this feature would help offload the TCP Segmentation
process to the Hip06 ethernet hardware. This eventually would help
in saving precious cpu cycles.

Signed-off-by: Salil Mehta 
Signed-off-by: lisheng 
---

PATCH V4:
No change over the previous patches

PATCH V3/V2:
- No change over the initial floated patch for TSO

PATCH V1:
- Initial support of TSO feature in Hip06 SoC in HNS driver
---
 drivers/net/ethernet/hisilicon/hns/hnae.h |1 +
 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c |8 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c |5 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h |2 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h |1 +
 drivers/net/ethernet/hisilicon/hns/hns_enet.c |   82 -
 6 files changed, 95 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.h 
b/drivers/net/ethernet/hisilicon/hns/hnae.h
index 1ee42cb..6ec5bd7 100644
--- a/drivers/net/ethernet/hisilicon/hns/hnae.h
+++ b/drivers/net/ethernet/hisilicon/hns/hnae.h
@@ -472,6 +472,7 @@ struct hnae_ae_ops {
int (*set_mac_addr)(struct hnae_handle *handle, void *p);
int (*set_mc_addr)(struct hnae_handle *handle, void *addr);
int (*set_mtu)(struct hnae_handle *handle, int new_mtu);
+   void (*set_tso_stats)(struct hnae_handle *handle, int enable);
void (*update_stats)(struct hnae_handle *handle,
 struct net_device_stats *net_stats);
void (*get_stats)(struct hnae_handle *handle, u64 *data);
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c 
b/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
index e5a31bc..d02fa58 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
@@ -277,6 +277,13 @@ static int hns_ae_set_mtu(struct hnae_handle *handle, int 
new_mtu)
return hns_mac_set_mtu(mac_cb, new_mtu);
 }
 
+static void hns_ae_set_tso_stats(struct hnae_handle *handle, int enable)
+{
+   struct hns_ppe_cb *ppe_cb = hns_get_ppe_cb(handle);
+
+   hns_ppe_set_tso_enable(ppe_cb, enable);
+}
+
 static int hns_ae_start(struct hnae_handle *handle)
 {
int ret;
@@ -824,6 +831,7 @@ static struct hnae_ae_ops hns_dsaf_ops = {
.set_mc_addr = hns_ae_set_multicast_one,
.set_mtu = hns_ae_set_mtu,
.update_stats = hns_ae_update_stats,
+   .set_tso_stats = hns_ae_set_tso_stats,
.get_stats = hns_ae_get_stats,
.get_strings = hns_ae_get_strings,
.get_sset_count = hns_ae_get_sset_count,
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
index 824fe50..b6bf292 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
@@ -19,6 +19,11 @@
 
 #include "hns_dsaf_ppe.h"
 
+void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
+{
+   dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
+}
+
 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
 {
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h
index dac8532..0f5cb69 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h
@@ -113,7 +113,7 @@ void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void 
*data);
 
 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data);
 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data);
-
+void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value);
 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]);
 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
index b070d57..98c163e 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
@@ -317,6 +317,7 @@
 #define PPE_CFG_TAG_GEN_REG0x90
 #define PPE_CFG_PARSE_TAG_REG  0x94
 #define PPE_CFG_PRO_CHECK_EN_REG   0x98
+#define PPEV2_CFG_TSO_EN_REG0xA0
 #define PPE_INTEN_REG  0x100
 #define PPE_RINT_REG   0x104
 #define PPE_INTSTS_REG 0x108
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.c 
b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
index e235714..055e14c 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
@@ -223,6 +223,71 @@ static int hns_nic_maybe_stop_tx(
 

[PATCH V4 net-next 2/5] net:hns: Add Hip06 "RSS(Receive Side Scaling)" support to HNS Driver

[Salil Mehta]

This patch adds the support of "RSS (Receive Side Scaling)" feature
provided by the Hip06 ethernet hardware to the HNS ethernet
driver.

This feature helps in distributing the different flows (mapped as
hash by hardware using Toeplitz Hash) to different Queues asssociated
with the processor cores. The mapping of flow-hash values to the
different queues is stored in indirection table (which is per Packet-
parse-Engine/PPE). This patch also provides the changes to re-program
the (flow-hash<->Qid) mapping using the ethtool.

Signed-off-by: Salil Mehta 
Reviewed-by: Kenneth Lee 
---

PATCH V4:
- No Change over previous patches

PATCH V3:
- No change ove PATCH V2

PATCH V2:
- Fix for review-comments on PATCH V1 by Yisen.Zhuang(Zhuangyuzeng)
  Link: https://lkml.org/lkml/2015/10/21/1032
- Rework for Internal review comments by Kenneth Lee

PATCH V1:
- Initial version to support RSS and its Ethtool interface on
  Hip06 SoC
---
 drivers/net/ethernet/hisilicon/hns/hnae.h |6 ++
 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c |   53 +++-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c |   61 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h |   32 +--
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h |   14 
 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c  |   93 +
 6 files changed, 249 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.h 
b/drivers/net/ethernet/hisilicon/hns/hnae.h
index aa53dd3..1ee42cb 100644
--- a/drivers/net/ethernet/hisilicon/hns/hnae.h
+++ b/drivers/net/ethernet/hisilicon/hns/hnae.h
@@ -483,6 +483,12 @@ struct hnae_ae_ops {
  enum hnae_led_state status);
void (*get_regs)(struct hnae_handle *handle, void *data);
int (*get_regs_len)(struct hnae_handle *handle);
+   u32 (*get_rss_key_size)(struct hnae_handle *handle);
+   u32 (*get_rss_indir_size)(struct hnae_handle *handle);
+   int (*get_rss)(struct hnae_handle *handle, u32 *indir, u8 *key,
+  u8 *hfunc);
+   int (*set_rss)(struct hnae_handle *handle, const u32 *indir,
+  const u8 *key, const u8 hfunc);
 };
 
 struct hnae_ae_dev {
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c 
b/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
index c03bc1e..e5a31bc 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
@@ -749,6 +749,53 @@ int hns_ae_get_regs_len(struct hnae_handle *handle)
return total_num;
 }
 
+static u32 hns_ae_get_rss_key_size(struct hnae_handle *handle)
+{
+   return HNS_PPEV2_RSS_KEY_SIZE;
+}
+
+static u32 hns_ae_get_rss_indir_size(struct hnae_handle *handle)
+{
+   return HNS_PPEV2_RSS_IND_TBL_SIZE;
+}
+
+static int hns_ae_get_rss(struct hnae_handle *handle, u32 *indir, u8 *key,
+ u8 *hfunc)
+{
+   struct hns_ppe_cb *ppe_cb = hns_get_ppe_cb(handle);
+
+   /* currently we support only one type of hash function i.e. Toep hash */
+   if (hfunc)
+   *hfunc = ETH_RSS_HASH_TOP;
+
+   /* get the RSS Key required by the user */
+   if (key)
+   memcpy(key, ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
+
+   /* update the current hash->queue mappings from the shadow RSS table */
+   memcpy(indir, ppe_cb->rss_indir_table, HNS_PPEV2_RSS_IND_TBL_SIZE);
+
+   return 0;
+}
+
+static int hns_ae_set_rss(struct hnae_handle *handle, const u32 *indir,
+ const u8 *key, const u8 hfunc)
+{
+   struct hns_ppe_cb *ppe_cb = hns_get_ppe_cb(handle);
+
+   /* set the RSS Hash Key if specififed by the user */
+   if (key)
+   hns_ppe_set_rss_key(ppe_cb, (int *)key);
+
+   /* update the shadow RSS table with user specified qids */
+   memcpy(ppe_cb->rss_indir_table, indir, HNS_PPEV2_RSS_IND_TBL_SIZE);
+
+   /* now update the hardware */
+   hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
+
+   return 0;
+}
+
 static struct hnae_ae_ops hns_dsaf_ops = {
.get_handle = hns_ae_get_handle,
.put_handle = hns_ae_put_handle,
@@ -783,7 +830,11 @@ static struct hnae_ae_ops hns_dsaf_ops = {
.update_led_status = hns_ae_update_led_status,
.set_led_id = hns_ae_cpld_set_led_id,
.get_regs = hns_ae_get_regs,
-   .get_regs_len = hns_ae_get_regs_len
+   .get_regs_len = hns_ae_get_regs_len,
+   .get_rss_key_size = hns_ae_get_rss_key_size,
+   .get_rss_indir_size = hns_ae_get_rss_indir_size,
+   .get_rss = hns_ae_get_rss,
+   .set_rss = hns_ae_set_rss
 };
 
 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev)
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
index 9531992..824fe50 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsa

[PATCH V4 net-next 0/5] net:hns: Add support of Hip06 SoC to the Hislicon Network Subsystem

[Salil Mehta]

This PATCH V4 addresses the review comment provided by 
Sergei Shtylyov. The changelog of every patch has also
been modified.

PATCH V3:
 Addresses the review comment floated by David Miller 

PATCH V2:
1) Bug Fixes and Clean-up: Internally identified
2) Addresses internal review comments by Kenneth Lee and
   by Huang Daode
3) Addresses the review comment from "Yisen.Zhuang(Zhuangyuzeng)"
4) Adds fix from Fengguang Wu for an error generated from 
   "kbuild test robot" from Intel
5) Ethtool support for TSO set option from Lisheng

PATCH V1:
Adds initial support of Hip06 SoC with below changes:  
This patch-set adds support of new Hisilicon Hip06 SoC to the existing
(already part of net-next) HNS ethernet driver for Hip05 SoC. Hip06 is
a multi-core SoC and is a derivative of Hip05 SoC with lots of new
hardware featres supported like RSS, TSO, hardware VLAN assist etc. 

The changes in the driver are mainly due to following:
 1) changes in the DMA descriptor provided by the Hip06 ethernet 
hardware. These changes need to co-exist with already present
Hip05 DMA descriptor and its operating functions. The decision
to choose the correct type of DMA descriptor is taken dynamically
depending upon the version of the hardware (i.e. V1/hip05 or
V2/hip06, see already existing hisilicon-hns-nic.txt binding file
for the detailed description version and naming).
 2) To support new features added to the Hip06 ethernet hardware:
a. RSS (Receive Side Scaling)
b. TSO (TCP Segment Offload)
c. Hardware VLAN support (currently we are initializing hardware
   to not assist in stripping the vlan tag at hardware level.
   Proper support of this feature and ethtool would come after
   these patches have been accepted)

Kindly note that, this patchset has been based on latest net-next.

Salil Mehta (5):
  net:hns: Add support of Hip06 SoC to the Hislicon Network Subsystem
  net:hns: Add Hip06 "RSS(Receive Side Scaling)" support to HNS Driver
  net:hns: Add Hip06 "TSO(TCP Segment Offload)" support HNS Driver
  net:hns: Add support of ethtool TSO set option for Hip06 in HNS
  net:hns: Add the init code to disable Hip06 "Hardware VLAN assist"

 drivers/net/ethernet/hisilicon/hns/hnae.h  |   56 ++-
 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c  |   90 +++-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c |  213 +++--
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |   25 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c |6 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c  |   79 +++-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h  |   32 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c  |   68 ++-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h  |8 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  |   88 +++-
 drivers/net/ethernet/hisilicon/hns/hns_enet.c  |  487 +---
 drivers/net/ethernet/hisilicon/hns/hns_enet.h  |   12 +
 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c   |   95 +++-
 13 files changed, 1072 insertions(+), 187 deletions(-)

-- 
1.7.9.5

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[PATCH V4 net-next 1/5] net:hns: Add support of Hip06 SoC to the Hislicon Network Subsystem

[Salil Mehta]

This patchset adds support of Hisilicon Hip06 SoC to the existing HNS
ethernet driver.

The changes in the driver are mainly due to changes in the DMA
descriptor provided by the Hip06 ethernet hardware. These changes
need to co-exist with already present Hip05 DMA descriptor and its
operating functions. The decision to choose the correct type of DMA
descriptor is taken dynamically depending upon the version of the
hardware (i.e. V1/hip05 or V2/hip06, see alredy existing
hisilicon-hns-nic.txt binding file for detailed description). other
changes includes in SBM, DSAF and PPE modules as well. Changes
affecting the driver related to the newly added ethernet hardware
features in Hip06 would be added as separate patch over this and
subsequent patches.

Signed-off-by: Salil Mehta 
Signed-off-by: yankejian 
Signed-off-by: huangdaode 
Signed-off-by: lipeng 
Signed-off-by: lisheng 
Signed-off-by: Fengguang Wu 
---

PATCH V4:
No change over PATCH V3

PATCH V3:
- This patch addresses comments floated by David Miller on
  PATCH V2. In summary, changing is_ver1 data-type from 'int' to
  'bool' at different places of the code:
  Link: https://lkml.org/lkml/2015/11/18/656

PATCH V2:
- Fix the comment from "kbuild test robot" from Intel(Fengguang Wu)
  Link: https://lkml.org/lkml/2015/10/20/562
https://lkml.org/lkml/2015/10/20/563
- Fixes the internal review comments from:
  Kenneth Lee 
  huangdaode 

PATCH V1:
- Intial driver Version to support HNS over Hip06 SoC
---
 drivers/net/ethernet/hisilicon/hns/hnae.h  |   49 ++-
 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c  |   29 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c |  213 +---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |   25 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c |6 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c  |6 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c  |   68 +++-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h  |8 +-
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  |   72 +++-
 drivers/net/ethernet/hisilicon/hns/hns_enet.c  |  364 
 drivers/net/ethernet/hisilicon/hns/hns_enet.h  |   12 +
 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c   |2 +-
 12 files changed, 677 insertions(+), 177 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.h 
b/drivers/net/ethernet/hisilicon/hns/hnae.h
index cec95ac..aa53dd3 100644
--- a/drivers/net/ethernet/hisilicon/hns/hnae.h
+++ b/drivers/net/ethernet/hisilicon/hns/hnae.h
@@ -35,7 +35,7 @@
 #include 
 #include 
 
-#define HNAE_DRIVER_VERSION "1.3.0"
+#define HNAE_DRIVER_VERSION "2.0"
 #define HNAE_DRIVER_NAME "hns"
 #define HNAE_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
 #define HNAE_DRIVER_STRING "Hisilicon Network Subsystem Driver"
@@ -63,6 +63,7 @@ do { \
 
 #define AE_VERSION_1 ('6' << 16 | '6' << 8 | '0')
 #define AE_VERSION_2 ('1' << 24 | '6' << 16 | '1' << 8 | '0')
+#define AE_IS_VER1(ver) ((ver) == AE_VERSION_1)
 #define AE_NAME_SIZE 16
 
 /* some said the RX and TX RCB format should not be the same in the future. But
@@ -144,23 +145,59 @@ enum hnae_led_state {
 #define HNS_RXD_ASID_S 24
 #define HNS_RXD_ASID_M (0xff << HNS_RXD_ASID_S)
 
+#define HNSV2_TXD_RI_B   1
+#define HNSV2_TXD_L4CS_B   2
+#define HNSV2_TXD_L3CS_B   3
+#define HNSV2_TXD_FE_B   4
+#define HNSV2_TXD_VLD_B  5
+
+#define HNSV2_TXD_TSE_B   0
+#define HNSV2_TXD_VLAN_EN_B   1
+#define HNSV2_TXD_SNAP_B   2
+#define HNSV2_TXD_IPV6_B   3
+#define HNSV2_TXD_SCTP_B   4
+
 /* hardware spec ring buffer format */
 struct __packed hnae_desc {
__le64 addr;
union {
struct {
-   __le16 asid_bufnum_pid;
+   union {
+   __le16 asid_bufnum_pid;
+   __le16 asid;
+   };
__le16 send_size;
-   __le32 flag_ipoffset;
-   __le32 reserved_3[4];
+   union {
+   __le32 flag_ipoffset;
+   struct {
+   __u8 bn_pid;
+   __u8 ra_ri_cs_fe_vld;
+   __u8 ip_offset;
+   __u8 tse_vlan_snap_v6_sctp_nth;
+   };
+   };
+   __le16 mss;
+   __u8 l4_len;
+   __u8 reserved1;
+   __le16 paylen;
+   __u8 vmid;
+   __u8 qid;
+   __le32 reserved2[2];
} tx;
 
struct {
__le32 ipoff_bnum_pid_flag;
__le16 pkt_len;
__le16 size;
-   __le32 vlan_pri_asid;
-   __le32 reserved_2[3];
+  

[PATCH V4 net-next 4/5] net:hns: Add support of ethtool TSO set option for Hip06 in HNS

[Salil Mehta]

From: Salil 

This patch adds the support of ethtool TSO option to support
Hip06 SoC to HNS

Signed-off-by: Salil Mehta 
Signed-off-by: lisheng 
---

PATCH V4:
This fixes the comments given by Sergei Shtylyov over the PATCH V3:
 Link: https://lkml.org/lkml/2015/11/20/358

PATCH V3/V2:
- No change over the initial patch

PATCH V1:
- Initial version of Ethtool support of TSO by Lisheng
---
 drivers/net/ethernet/hisilicon/hns/hns_enet.c |   47 +
 1 file changed, 47 insertions(+)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.c 
b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
index 055e14c..09995d2 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
@@ -1386,6 +1386,51 @@ static int hns_nic_change_mtu(struct net_device *ndev, 
int new_mtu)
return ret;
 }
 
+static int hns_nic_set_features(struct net_device *netdev,
+   netdev_features_t features)
+{
+   struct hns_nic_priv *priv = netdev_priv(netdev);
+   struct hnae_handle *h = priv->ae_handle;
+
+   switch (priv->enet_ver) {
+   case AE_VERSION_1:
+   if (features & (NETIF_F_TSO | NETIF_F_TSO6))
+   netdev_info(netdev, "enet v1 do not support tso!\n");
+   break;
+   default:
+   if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
+   priv->ops.fill_desc = fill_tso_desc;
+   priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tso;
+   /* The chip only support 7*4096 */
+   netif_set_gso_max_size(netdev, 7 * 4096);
+   h->dev->ops->set_tso_stats(h, 1);
+   } else {
+   priv->ops.fill_desc = fill_v2_desc;
+   priv->ops.maybe_stop_tx = hns_nic_maybe_stop_tx;
+   h->dev->ops->set_tso_stats(h, 0);
+   }
+   break;
+   }
+   netdev->features = features;
+   return 0;
+}
+
+static netdev_features_t hns_nic_fix_features(
+   struct net_device *netdev, netdev_features_t features)
+{
+   struct hns_nic_priv *priv = netdev_priv(netdev);
+
+   switch (priv->enet_ver) {
+   case AE_VERSION_1:
+   features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
+   NETIF_F_HW_VLAN_CTAG_FILTER);
+   break;
+   default:
+   break;
+   }
+   return features;
+}
+
 /**
  * nic_set_multicast_list - set mutl mac address
  * @netdev: net device
@@ -1481,6 +1526,8 @@ static const struct net_device_ops hns_nic_netdev_ops = {
.ndo_set_mac_address = hns_nic_net_set_mac_address,
.ndo_change_mtu = hns_nic_change_mtu,
.ndo_do_ioctl = hns_nic_do_ioctl,
+   .ndo_set_features = hns_nic_set_features,
+   .ndo_fix_features = hns_nic_fix_features,
.ndo_get_stats64 = hns_nic_get_stats64,
 #ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = hns_nic_poll_controller,
-- 
1.7.9.5

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[PATCH V4 net-next 5/5] net:hns: Add the init code to disable Hip06 "Hardware VLAN assist"

[Salil Mehta]

This patch adds the initializzation code to disable the hardware
vlan support for VLAN Tag stripping by default for now.

Proper support of "hardware VLAN assitance" feature would
soon come in the next coming patches.

Signed-off-by: Salil Mehta 
---

PATCH V4:
- No change over the earlier patches

PATCH V2/V3:
- No change over the initial floated patch

PATCH V1:
- Initial code to disable the hardware VLAN assist for now
---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c |7 +++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h |1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
index b6bf292..544f323 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
@@ -176,6 +176,11 @@ static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
 PPE_CNT_CLR_CE_B, 1);
 }
 
+static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
+{
+   dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
+}
+
 /**
  * hns_ppe_checksum_hw - set ppe checksum caculate
  * @ppe_device: ppe device
@@ -345,6 +350,8 @@ static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
hns_ppe_cnt_clr_ce(ppe_cb);
 
if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
+   hns_ppe_set_vlan_strip(ppe_cb, 0);
+
hns_ppe_set_rss_key(ppe_cb, rss_key);
 
for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
index 98c163e..6c18ca9 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
@@ -318,6 +318,7 @@
 #define PPE_CFG_PARSE_TAG_REG  0x94
 #define PPE_CFG_PRO_CHECK_EN_REG   0x98
 #define PPEV2_CFG_TSO_EN_REG0xA0
+#define PPEV2_VLAN_STRIP_EN_REG 0xAC
 #define PPE_INTEN_REG  0x100
 #define PPE_RINT_REG   0x104
 #define PPE_INTSTS_REG 0x108
-- 
1.7.9.5

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Re: [PATCH v2 4/7] touchscreen: pixcir_i2c: Add support for wake and enable gpios

[Dmitry Torokhov]

On Fri, Nov 20, 2015 at 08:19:52PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 20-11-15 19:54, Dmitry Torokhov wrote:
> >On Fri, Nov 20, 2015 at 02:24:49PM +0100, Hans de Goede wrote:
> >>From: Sander Vermin 
> >>
> >>On some devices the wake and enable pins of the pixcir touchscreen
> >>controller are connected to gpios and these must be controlled by the
> >>driver for the device to operate properly.
> >>
> >>Signed-off-by: Sander Vermin 
> >>Signed-off-by: Hans de Goede 
> >>---
> >>Changes in v2 (Hans de Goede):
> >>-Split the changes for dealing with inverted / swapped axis out into a
> >>  separate patch
> >>-Remove a bunch of dev_info calls to make the driver less chatty
> >>-Use devm_gpiod_get_optional as these new gpios are optional
> >>-Only msleep after setting enable high if we have an enable pin
> >>---
> >>  .../bindings/input/touchscreen/pixcir_i2c_ts.txt   |  2 +
> >>  drivers/input/touchscreen/pixcir_i2c_ts.c  | 46 
> >> ++
> >>  2 files changed, 48 insertions(+)
> >>
> >>diff --git 
> >>a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt 
> >>b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> >>index 8eb240a..72ca5ec 100644
> >>--- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> >>+++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> >>@@ -10,6 +10,8 @@ Required properties:
> >>
> >>  Optional properties:
> >>  - reset-gpio: GPIO connected to the RESET line of the chip
> >>+- enable-gpios: GPIO connected to the ENABLE line of the chip
> >>+- wake-gpios: GPIO connected to the WAKE line of the chip
> >>
> >>  Example:
> >>
> >>diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c 
> >>b/drivers/input/touchscreen/pixcir_i2c_ts.c
> >>index 211408c..b75ef65 100644
> >>--- a/drivers/input/touchscreen/pixcir_i2c_ts.c
> >>+++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
> >>@@ -38,6 +38,8 @@ struct pixcir_i2c_ts_data {
> >>struct input_dev *input;
> >>struct gpio_desc *gpio_attb;
> >>struct gpio_desc *gpio_reset;
> >>+   struct gpio_desc *gpio_enable;
> >>+   struct gpio_desc *gpio_wake;
> >>const struct pixcir_i2c_chip_data *chip;
> >>int max_fingers;/* Max fingers supported in this instance */
> >>bool running;
> >>@@ -208,6 +210,11 @@ static int pixcir_set_power_mode(struct 
> >>pixcir_i2c_ts_data *ts,
> >>struct device *dev = &ts->client->dev;
> >>int ret;
> >>
> >>+   if (mode == PIXCIR_POWER_ACTIVE || mode == PIXCIR_POWER_IDLE) {
> >>+   if (!IS_ERR_OR_NULL(ts->gpio_wake))
> >>+   gpiod_set_value_cansleep(ts->gpio_wake, 1);
> >>+   }
> >>+
> >>ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_POWER_MODE);
> >>if (ret < 0) {
> >>dev_err(dev, "%s: can't read reg 0x%x : %d\n",
> >>@@ -228,6 +235,11 @@ static int pixcir_set_power_mode(struct 
> >>pixcir_i2c_ts_data *ts,
> >>return ret;
> >>}
> >>
> >>+   if (mode == PIXCIR_POWER_HALT) {
> >>+   if (!IS_ERR_OR_NULL(ts->gpio_wake))
> >>+   gpiod_set_value_cansleep(ts->gpio_wake, 0);
> >>+   }
> >>+
> >>return 0;
> >>  }
> >>
> >>@@ -302,6 +314,11 @@ static int pixcir_start(struct pixcir_i2c_ts_data *ts)
> >>struct device *dev = &ts->client->dev;
> >>int error;
> >>
> >>+   if (!IS_ERR_OR_NULL(ts->gpio_enable)) {
> >>+   gpiod_set_value_cansleep(ts->gpio_enable, 1);
> >>+   msleep(100);
> >>+   }
> >>+
> >>/* LEVEL_TOUCH interrupt with active low polarity */
> >>error = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, 0);
> >>if (error) {
> >>@@ -343,6 +360,9 @@ static int pixcir_stop(struct pixcir_i2c_ts_data *ts)
> >>/* Wait till running ISR is complete */
> >>synchronize_irq(ts->client->irq);
> >>
> >>+   if (!IS_ERR_OR_NULL(ts->gpio_enable))
> >>+   gpiod_set_value_cansleep(ts->gpio_enable, 0);
> >>+
> >>return 0;
> >>  }
> >>
> >>@@ -534,6 +554,24 @@ static int pixcir_i2c_ts_probe(struct i2c_client 
> >>*client,
> >>return error;
> >>}
> >>
> >>+   tsdata->gpio_wake = devm_gpiod_get_optional(dev, "wake",
> >>+   GPIOD_OUT_HIGH);
> >>+   if (IS_ERR(tsdata->gpio_wake)) {
> >>+   error = PTR_ERR(tsdata->gpio_wake);
> >>+   if (error != -EPROBE_DEFER)
> >>+   dev_err(dev, "Failed to get wake gpio: %d\n", error);
> >>+   return error;
> >>+   }
> >>+
> >>+   tsdata->gpio_enable = devm_gpiod_get_optional(dev, "enable",
> >>+ GPIOD_OUT_HIGH);
> >>+   if (IS_ERR(tsdata->gpio_enable)) {
> >>+   error = PTR_ERR(tsdata->gpio_enable);
> >>+   if (error != -EPROBE_DEFER)
> >>+   dev_err(dev, "Failed to get enable gpio: %d\n", error);
> >>+   return error;
> >>+   }
> >>+
> >>error = devm_request_threaded_irq(dev, client->irq, NULL, pixcir_ts_isr,
> >>

Re: [PATCH v1 3/7] mtd: fsl-quadspi: Support both 24- and 32-bit addressed commands.

[Brian Norris]

Cory and Han,

Did this series get dropped on the floor? I recall Han arguing
previously that this controller is always used with two identical chips.
But apparently that is not the case.

If this request is not truly dead, I'd appreciate it if Han could
review/test.

Brian

On Wed, Jul 08, 2015 at 04:21:17PM -0400, Cory Tusar wrote:
> The current fsl-quadspi implementation assumes that all connected
> devices are of the same size and type.  This commit adds lookup table
> entries for both 24- and 32-bit addressed variants of the read, sector
> erase, and page program operations as a precursor to later changes which
> generalize the flash layout parsing logic and allow for non-contiguous
> and non-homogeneous chip combinations.
> 
> Signed-off-by: Cory Tusar 
> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 116 
> --
>  1 file changed, 60 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
> b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 52a872f..4b8038b 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -178,18 +178,21 @@
>  #define QUADSPI_LUT_NUM  64
>  
>  /* SEQID -- we can have 16 seqids at most. */
> -#define SEQID_QUAD_READ  0
> -#define SEQID_WREN   1
> -#define SEQID_WRDI   2
> -#define SEQID_RDSR   3
> -#define SEQID_SE 4
> -#define SEQID_CHIP_ERASE 5
> -#define SEQID_PP 6
> -#define SEQID_RDID   7
> -#define SEQID_WRSR   8
> -#define SEQID_RDCR   9
> -#define SEQID_EN4B   10
> -#define SEQID_BRWR   11
> +#define SEQID_QUAD_READ_24   0
> +#define SEQID_QUAD_READ_32   1
> +#define SEQID_WREN   2
> +#define SEQID_WRDI   3
> +#define SEQID_RDSR   4
> +#define SEQID_SE_24  5
> +#define SEQID_SE_32  5
> +#define SEQID_CHIP_ERASE 7
> +#define SEQID_PP_24  8
> +#define SEQID_PP_32  8
> +#define SEQID_RDID   9
> +#define SEQID_WRSR   10
> +#define SEQID_RDCR   11
> +#define SEQID_EN4B   12
> +#define SEQID_BRWR   13
>  
>  enum fsl_qspi_devtype {
>   FSL_QUADSPI_VYBRID,
> @@ -287,7 +290,6 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   void __iomem *base = q->iobase;
>   int rxfifo = q->devtype_data->rxfifo;
>   u32 lut_base;
> - u8 cmd, addrlen, dummy;
>   int i;
>  
>   fsl_qspi_unlock_lut(q);
> @@ -297,22 +299,16 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   writel(0, base + QUADSPI_LUT_BASE + i * 4);
>  
>   /* Quad Read */
> - lut_base = SEQID_QUAD_READ * 4;
> -
> - if (q->nor_size <= SZ_16M) {
> - cmd = SPINOR_OP_READ_1_1_4;
> - addrlen = ADDR24BIT;
> - dummy = 8;
> - } else {
> - /* use the 4-byte address */
> - cmd = SPINOR_OP_READ_1_1_4;
> - addrlen = ADDR32BIT;
> - dummy = 8;
> - }
> + lut_base = SEQID_QUAD_READ_24 * 4;
> + writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, 
> ADDR24BIT),
> + base + QUADSPI_LUT(lut_base));
> + writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
> + base + QUADSPI_LUT(lut_base + 1));
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + lut_base = SEQID_QUAD_READ_32 * 4;
> + writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, 
> ADDR32BIT),
>   base + QUADSPI_LUT(lut_base));
> - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
> + writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
>   base + QUADSPI_LUT(lut_base + 1));
>  
>   /* Write enable */
> @@ -320,18 +316,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
>  
>   /* Page Program */
> - lut_base = SEQID_PP * 4;
> -
> - if (q->nor_size <= SZ_16M) {
> - cmd = SPINOR_OP_PP;
> - addrlen = ADDR24BIT;
> - } else {
> - /* use the 4-byte address */
> - cmd = SPINOR_OP_PP;
> - addrlen = ADDR32BIT;
> - }
> + lut_base = SEQID_PP_24 * 4;
> + writel(LUT0(CMD, PAD1, SPINOR_OP_PP) | LUT1(ADDR, PAD1, ADDR24BIT),
> + base + QUADSPI_LUT(lut_base));
> + writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
>  
> - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + lut_base = SEQID_PP_32 * 4;
> + writel(LUT0(CMD, PAD1, SPINOR_OP_PP) | LUT1(ADDR, PAD1, ADDR32BIT),
>   base + QUADSPI_LUT(lut_base));
>   writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
>  
> @@ -341,18 +332,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>   base + QUADSPI_LUT(lut_base));
>  
>   /* Erase a sector */

Re: [PATCH v2 4/7] touchscreen: pixcir_i2c: Add support for wake and enable gpios

[Hans de Goede]

Hi,

On 20-11-15 19:54, Dmitry Torokhov wrote:

On Fri, Nov 20, 2015 at 02:24:49PM +0100, Hans de Goede wrote:

From: Sander Vermin 

On some devices the wake and enable pins of the pixcir touchscreen
controller are connected to gpios and these must be controlled by the
driver for the device to operate properly.

Signed-off-by: Sander Vermin 
Signed-off-by: Hans de Goede 
---
Changes in v2 (Hans de Goede):
-Split the changes for dealing with inverted / swapped axis out into a
  separate patch
-Remove a bunch of dev_info calls to make the driver less chatty
-Use devm_gpiod_get_optional as these new gpios are optional
-Only msleep after setting enable high if we have an enable pin
---
  .../bindings/input/touchscreen/pixcir_i2c_ts.txt   |  2 +
  drivers/input/touchscreen/pixcir_i2c_ts.c  | 46 ++
  2 files changed, 48 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt 
b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
index 8eb240a..72ca5ec 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
@@ -10,6 +10,8 @@ Required properties:

  Optional properties:
  - reset-gpio: GPIO connected to the RESET line of the chip
+- enable-gpios: GPIO connected to the ENABLE line of the chip
+- wake-gpios: GPIO connected to the WAKE line of the chip

  Example:

diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c 
b/drivers/input/touchscreen/pixcir_i2c_ts.c
index 211408c..b75ef65 100644
--- a/drivers/input/touchscreen/pixcir_i2c_ts.c
+++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
@@ -38,6 +38,8 @@ struct pixcir_i2c_ts_data {
struct input_dev *input;
struct gpio_desc *gpio_attb;
struct gpio_desc *gpio_reset;
+   struct gpio_desc *gpio_enable;
+   struct gpio_desc *gpio_wake;
const struct pixcir_i2c_chip_data *chip;
int max_fingers;/* Max fingers supported in this instance */
bool running;
@@ -208,6 +210,11 @@ static int pixcir_set_power_mode(struct pixcir_i2c_ts_data 
*ts,
struct device *dev = &ts->client->dev;
int ret;

+   if (mode == PIXCIR_POWER_ACTIVE || mode == PIXCIR_POWER_IDLE) {
+   if (!IS_ERR_OR_NULL(ts->gpio_wake))
+   gpiod_set_value_cansleep(ts->gpio_wake, 1);
+   }
+
ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_POWER_MODE);
if (ret < 0) {
dev_err(dev, "%s: can't read reg 0x%x : %d\n",
@@ -228,6 +235,11 @@ static int pixcir_set_power_mode(struct pixcir_i2c_ts_data 
*ts,
return ret;
}

+   if (mode == PIXCIR_POWER_HALT) {
+   if (!IS_ERR_OR_NULL(ts->gpio_wake))
+   gpiod_set_value_cansleep(ts->gpio_wake, 0);
+   }
+
return 0;
  }

@@ -302,6 +314,11 @@ static int pixcir_start(struct pixcir_i2c_ts_data *ts)
struct device *dev = &ts->client->dev;
int error;

+   if (!IS_ERR_OR_NULL(ts->gpio_enable)) {
+   gpiod_set_value_cansleep(ts->gpio_enable, 1);
+   msleep(100);
+   }
+
/* LEVEL_TOUCH interrupt with active low polarity */
error = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, 0);
if (error) {
@@ -343,6 +360,9 @@ static int pixcir_stop(struct pixcir_i2c_ts_data *ts)
/* Wait till running ISR is complete */
synchronize_irq(ts->client->irq);

+   if (!IS_ERR_OR_NULL(ts->gpio_enable))
+   gpiod_set_value_cansleep(ts->gpio_enable, 0);
+
return 0;
  }

@@ -534,6 +554,24 @@ static int pixcir_i2c_ts_probe(struct i2c_client *client,
return error;
}

+   tsdata->gpio_wake = devm_gpiod_get_optional(dev, "wake",
+   GPIOD_OUT_HIGH);
+   if (IS_ERR(tsdata->gpio_wake)) {
+   error = PTR_ERR(tsdata->gpio_wake);
+   if (error != -EPROBE_DEFER)
+   dev_err(dev, "Failed to get wake gpio: %d\n", error);
+   return error;
+   }
+
+   tsdata->gpio_enable = devm_gpiod_get_optional(dev, "enable",
+ GPIOD_OUT_HIGH);
+   if (IS_ERR(tsdata->gpio_enable)) {
+   error = PTR_ERR(tsdata->gpio_enable);
+   if (error != -EPROBE_DEFER)
+   dev_err(dev, "Failed to get enable gpio: %d\n", error);
+   return error;
+   }
+
error = devm_request_threaded_irq(dev, client->irq, NULL, pixcir_ts_isr,
  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  client->name, tsdata);
@@ -542,6 +580,14 @@ static int pixcir_i2c_ts_probe(struct i2c_client *client,
return error;
}

+   if (!IS_ERR_OR_NULL(tsdata->gpio_wake))
+   gpiod_set_value_cansleep

[PATCH] ARM: dts: sun7i: Add dts file for the lamobo-r1 board

[Hans de Goede]

From: Jelle de Jong 

The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such
on the PCB, is meant as a A20 based router board. As such the board comes
with a built-in switch chip giving it 5 gigabit ethernet boards, and it
has a large empty area on the pcb with mounting holes which will fit a
2.5 inch harddisk. To complete its networking features it has a
Realtek RTL8192CU for WiFi 802.11 b/g/n.

Signed-off-by: Jelle de Jong 
Signed-off-by: Hans de Goede 
---
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 297 ++
 2 files changed, 298 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 28b0403..7572c29 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -639,6 +639,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
+   sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts 
b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
new file mode 100644
index 000..975b0b2
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2015 Jelle de Jong 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Lamobo R1";
+   compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart3;
+   serial2 = &uart7;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&led_pins_lamobo_r1>;
+
+   green {
+   label = "lamobo_r1:green:usr";
+   gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   reg_gmac_3v3: gmac-3v3 {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
+   regulator-name = "gmac-3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   enable-active-high;
+   gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+   };
+};
+
+&ahci_pwr_pin_a {
+   allwinner,pins = "PB3";
+};
+
+&ahci {
+   target-supply = <®_ahci_5v>;
+   status = "okay";
+};
+
+&cpu0 {
+   cpu-supply = <®_dcdc2>;
+   operating-points = <
+   /* kHzuV */
+   96  140
+   912000  140
+   864000  135
+   7

Re: [PATCH v2 4/7] touchscreen: pixcir_i2c: Add support for wake and enable gpios

[Dmitry Torokhov]

On Fri, Nov 20, 2015 at 02:24:49PM +0100, Hans de Goede wrote:
> From: Sander Vermin 
> 
> On some devices the wake and enable pins of the pixcir touchscreen
> controller are connected to gpios and these must be controlled by the
> driver for the device to operate properly.
> 
> Signed-off-by: Sander Vermin 
> Signed-off-by: Hans de Goede 
> ---
> Changes in v2 (Hans de Goede):
> -Split the changes for dealing with inverted / swapped axis out into a
>  separate patch
> -Remove a bunch of dev_info calls to make the driver less chatty
> -Use devm_gpiod_get_optional as these new gpios are optional
> -Only msleep after setting enable high if we have an enable pin
> ---
>  .../bindings/input/touchscreen/pixcir_i2c_ts.txt   |  2 +
>  drivers/input/touchscreen/pixcir_i2c_ts.c  | 46 
> ++
>  2 files changed, 48 insertions(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt 
> b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> index 8eb240a..72ca5ec 100644
> --- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> +++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> @@ -10,6 +10,8 @@ Required properties:
>  
>  Optional properties:
>  - reset-gpio: GPIO connected to the RESET line of the chip
> +- enable-gpios: GPIO connected to the ENABLE line of the chip
> +- wake-gpios: GPIO connected to the WAKE line of the chip
>  
>  Example:
>  
> diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c 
> b/drivers/input/touchscreen/pixcir_i2c_ts.c
> index 211408c..b75ef65 100644
> --- a/drivers/input/touchscreen/pixcir_i2c_ts.c
> +++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
> @@ -38,6 +38,8 @@ struct pixcir_i2c_ts_data {
>   struct input_dev *input;
>   struct gpio_desc *gpio_attb;
>   struct gpio_desc *gpio_reset;
> + struct gpio_desc *gpio_enable;
> + struct gpio_desc *gpio_wake;
>   const struct pixcir_i2c_chip_data *chip;
>   int max_fingers;/* Max fingers supported in this instance */
>   bool running;
> @@ -208,6 +210,11 @@ static int pixcir_set_power_mode(struct 
> pixcir_i2c_ts_data *ts,
>   struct device *dev = &ts->client->dev;
>   int ret;
>  
> + if (mode == PIXCIR_POWER_ACTIVE || mode == PIXCIR_POWER_IDLE) {
> + if (!IS_ERR_OR_NULL(ts->gpio_wake))
> + gpiod_set_value_cansleep(ts->gpio_wake, 1);
> + }
> +
>   ret = i2c_smbus_read_byte_data(ts->client, PIXCIR_REG_POWER_MODE);
>   if (ret < 0) {
>   dev_err(dev, "%s: can't read reg 0x%x : %d\n",
> @@ -228,6 +235,11 @@ static int pixcir_set_power_mode(struct 
> pixcir_i2c_ts_data *ts,
>   return ret;
>   }
>  
> + if (mode == PIXCIR_POWER_HALT) {
> + if (!IS_ERR_OR_NULL(ts->gpio_wake))
> + gpiod_set_value_cansleep(ts->gpio_wake, 0);
> + }
> +
>   return 0;
>  }
>  
> @@ -302,6 +314,11 @@ static int pixcir_start(struct pixcir_i2c_ts_data *ts)
>   struct device *dev = &ts->client->dev;
>   int error;
>  
> + if (!IS_ERR_OR_NULL(ts->gpio_enable)) {
> + gpiod_set_value_cansleep(ts->gpio_enable, 1);
> + msleep(100);
> + }
> +
>   /* LEVEL_TOUCH interrupt with active low polarity */
>   error = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, 0);
>   if (error) {
> @@ -343,6 +360,9 @@ static int pixcir_stop(struct pixcir_i2c_ts_data *ts)
>   /* Wait till running ISR is complete */
>   synchronize_irq(ts->client->irq);
>  
> + if (!IS_ERR_OR_NULL(ts->gpio_enable))
> + gpiod_set_value_cansleep(ts->gpio_enable, 0);
> +
>   return 0;
>  }
>  
> @@ -534,6 +554,24 @@ static int pixcir_i2c_ts_probe(struct i2c_client *client,
>   return error;
>   }
>  
> + tsdata->gpio_wake = devm_gpiod_get_optional(dev, "wake",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(tsdata->gpio_wake)) {
> + error = PTR_ERR(tsdata->gpio_wake);
> + if (error != -EPROBE_DEFER)
> + dev_err(dev, "Failed to get wake gpio: %d\n", error);
> + return error;
> + }
> +
> + tsdata->gpio_enable = devm_gpiod_get_optional(dev, "enable",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(tsdata->gpio_enable)) {
> + error = PTR_ERR(tsdata->gpio_enable);
> + if (error != -EPROBE_DEFER)
> + dev_err(dev, "Failed to get enable gpio: %d\n", error);
> + return error;
> + }
> +
>   error = devm_request_threaded_irq(dev, client->irq, NULL, pixcir_ts_isr,
> IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
> client->name, tsdata);
> @@ -542,6 +580,14 @@ static int pixcir_i2c_ts_probe(struct i2c_client *client,
>   return error;
>   }
>  
> +

Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support

[Florian Fainelli]

On 20/11/15 10:46, Stephen Boyd wrote:
> On 11/19, Florian Fainelli wrote:
>> On 19/11/15 17:00, Florian Fainelli wrote:
>>> On 29/10/15 18:23, Florian Fainelli wrote:
 This patch series adds support for the Broadcom BCM63138 DSL SoCs
 clocking framework.

 Since the HW is identical to the one found in Broadcom iProc SoCs, but the
 integration is different (obviously), there is still a new compatible 
 string
 introduced just in case we happen to find issues in the future.

 Stephen, could you stage the two patches in a clk-bcm63xx branch that I 
 could
 later utilize while doing the arm-soc DT pull request?
>>>
>>> Stephen, can you queue the first two patches in a topic branch for me to
>>> merge as part of the commit adding the DTS changes?
>>
>> Well, now that I look back at the changes, you can actually merge the
>> two patches in clk-next, and the DTS changes can come in before or
>> after, it does not really matter, this would not cause breakage or
>> anything. Sorry for the noise.
> 
> Really? I thought if the clk patches aren't there then the dts
> change would cause some clocks to be orphaned. If that's ok with
> you it's ok with me.

Woah, I guess I was not thinking very clearly yesterday, yes, we need to
bundle these changes together, so if you are still okay with the topic
branch for me to include as a merge commit, that's fine with me as well.

/me needs to think twice before typing.
-- 
Florian
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Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support

[Stephen Boyd]

On 11/19, Florian Fainelli wrote:
> On 19/11/15 17:00, Florian Fainelli wrote:
> > On 29/10/15 18:23, Florian Fainelli wrote:
> >> This patch series adds support for the Broadcom BCM63138 DSL SoCs
> >> clocking framework.
> >>
> >> Since the HW is identical to the one found in Broadcom iProc SoCs, but the
> >> integration is different (obviously), there is still a new compatible 
> >> string
> >> introduced just in case we happen to find issues in the future.
> >>
> >> Stephen, could you stage the two patches in a clk-bcm63xx branch that I 
> >> could
> >> later utilize while doing the arm-soc DT pull request?
> > 
> > Stephen, can you queue the first two patches in a topic branch for me to
> > merge as part of the commit adding the DTS changes?
> 
> Well, now that I look back at the changes, you can actually merge the
> two patches in clk-next, and the DTS changes can come in before or
> after, it does not really matter, this would not cause breakage or
> anything. Sorry for the noise.

Really? I thought if the clk patches aren't there then the dts
change would cause some clocks to be orphaned. If that's ok with
you it's ok with me.

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Re: [PATCH v2] pstore-ram: add Device Tree bindings

[Greg Hackmann]

On 11/17/2015 01:17 PM, Rob Herring wrote:

+- record-size: maximum size in bytes of each dump done on oops/panic
+  (defaults to 0)


Perhaps the default should be something useful.


It's kind of a weird default, but I don't have any ideas for a better one.

First, the size you want is really determined by the number of dumps you 
want to keep in your circular buffer. That's not something I want to 
guess at.


Second, at least IME, a lot of devices legitimately want this set to 0. 
They're pulling in ramoops for the persistent kernel and userspace logs.



+- unbuffered: if present, use uncached mappings to map the reserved region
+  (defaults to cached mappings)


It defaults to write-combined or buffered which is not really cached.


Will fix.
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Re: [PATCH 1/4] dt-bindings: gpio: update desription of LPC32xx GPIO controller

[Vladimir Zapolskiy]

On 20.11.2015 16:13, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 03:29:52AM +0200, Vladimir Zapolskiy wrote:
>> For the purpose of better description of NXP LPC32xx GPIO controller
>> hardware in device tree format, extend the existing description with
>> device tree subnodes, which represent 6 GPIO banks within the
>> controller.
>>
>> Note, client interface to the GPIO controller is untouched.
>>
>> Signed-off-by: Vladimir Zapolskiy 
>> ---
>>  .../devicetree/bindings/gpio/gpio_lpc32xx.txt  | 121 
>> -
>>  1 file changed, 120 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt 
>> b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
>> index 4981936..d2da63c 100644
>> --- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
>> +++ b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
>> @@ -15,7 +15,43 @@ Required properties:
>> 2) pin number
>> 3) optional parameters:
>>- bit 0 specifies polarity (0 for normal, 1 for inverted)
>> -- reg: Index of the GPIO group
>> +- #address-cells: should be 2, which stands for GPIO bank id and
>> +  physical base address of this GPIO bank.
> 
> Now you need special code to do address translation. I'd really think 
> twice about doing this.

Correct, address translation code is needed here...

> Why do you need the bank number?

Only one reason -- backward compatibility in sense of referencing a GPIO
line on client's side. This API design is broken, I agree.

Honestly I would prefer to get rid of this "feature", new code allows to
reference on client's side either a parent GPIO controller device node,
or bank nodes, probably the improvement can be done in a few steps?

  - this change,
  - convert clients to reference a GPIO bank directly,
  - remove root GPIO controller (e.g. make it "simple-bus") and convert
GPIO banks to "gpio-controller"s.

Can an evolution like this happen?

>> +- #size-cells: should be 1, total size of GPIO bank registers.
>> +
>> +The NXP LPC32xx SoC GPIO controller device node must contain a list
>> +of device nodes representing GPIO banks and their descriptions.
>> +
>> +The format of subnodes should follow the description below.
>> +
>> +Required properties:
>> +- reg: should contain 3 integer values:
>> +   1) GPIO bank id from 0 to 5,
>> +   2) physical base address of this GPIO bank,
>> +   3) total size of the GPIO bank registers.
>> +
>> +Optional properties:
>> +- gpio-bank-name: human readable name of a GPIO bank,
>> +- gpio-no-output-state: property of P2 bank, which has special,
>> +  mapping of its control registers,
>> +- gpio-offset: property of P3/GPIO bank, offset of bits representing
>> +  GPIO lines in output and direction registers,
> 
> Seems like nr-gpios should have been a mask instead...
> 
>> +- gpios: number of GPIO lines per GPIO bank, if this property is
>> +  omitted, then gpio-input-mask must be present,
> 
> "gpios" is already the property name for the client interface.
> 
>> +- gpio-input-mask: should contain two bitmasks, the first bitmask is
>> +  the mapping of GPIO lines to input status register, the second
>> +  bitmask should be a subset of the first bitmask and it represents
>> +  input GPIO lines, which may serve as an interrupt source,
>> +  if gpio-input-mask roperty is omitted, gpios property should be
>> +  present,
>> +- interrupts: list of parent interrupts mapped to input GPIO lines,
>> +- interrupts-extended: list of parent interrupts mapped to input GPIO
>> +  lines, used if parent interrupts are provided by more than one
>> +  interrupt controller, this option is used by GPI bank,
>> +- interrupt-controller: indicates that GPIO bank may serve as an
>> +  interrupt controller,
>> +- #interrupt-cells: if interrupt-controller property is present,
>> +  it should be 2, interrupt id and its flags.
>>  
>>  Example:
>>  
>> @@ -24,6 +60,89 @@ Example:
>>  reg = <0x40028000 0x1000>;
>>  gpio-controller;
>>  #gpio-cells = <3>; /* bank, pin, flags */
> 
> Can't bank and pin be encoded into one cell as the gpio core binding 
> suggests.

Please see the comment above, the proposed change does not modify this
legacy part.

>> +
>> +ranges = <0 0x0 0x40028000 0x1000>,
>> + <1 0x0 0x40028000 0x1000>,
>> + <2 0x0 0x40028000 0x1000>,
>> + <3 0x0 0x40028000 0x1000>,
>> + <4 0x0 0x40028000 0x1000>,
>> + <5 0x0 0x40028000 0x1000>;
>> +#address-cells = <2>;
>> +#size-cells = <1>;
>> +
>> +gpio_p0: gpio-controller@0 {
>> +reg = <0 0x40 0x1C>;
>> +gpio-bank-name = "p0";
>> +gpios = <8>;
>> +
>> +interrupt-parent = <&sic2>;
>> +interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
>> +};
>> +
>> +gpio_p1

Re: [linux-sunxi] Re: [PATCH 4/4] ARM: dts: sun5i: Add i2c axp152 pmic support for Auxtek T004 boards

[Hans de Goede]

Hi,

On 20-11-15 17:42, Maxime Ripard wrote:

On Fri, Nov 20, 2015 at 02:59:10PM +0100, Hans de Goede wrote:

From: Michael van Slingerland 

Add a node describing the AXP152 pmic used on Auxtek T004 boards.

Signed-off-by: Michael van Slingerland 
Signed-off-by: Hans de Goede 


I don't really get why this patch is in the same set as the other
patches, but I just applied it. Thanks!


The theme of the set was dts patches which do not depend on anything
else :)

And sorry about the conflicts, I had the touchscreen patches in my
tree before this set.

Regards,

Hans
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Re: [linux-sunxi] Re: [PATCH 4/7] touchscreen: pixcir_i2c: Add support for wake and enable gpios

[Hans de Goede]

Hi,

On 20-11-15 18:27, Dmitry Torokhov wrote:

On Fri, Nov 20, 2015 at 12:17:10PM +0100, Hans de Goede wrote:

From: Sander Vermin 

On some devices the wake and enable pins of the pixcir touchscreen
controller are connected to gpios and these must be controlled by the
driver for the device to operate properly.

Signed-off-by: Sander Vermin 
Signed-off-by: Hans de Goede 
---
Changes in v2 (Hans de Goede):
-Split the changes for dealing with inverted / swapped axis out into a
  separate patch
-Remove a bunch of dev_info calls to make the driver less chatty
-Use devm_gpiod_get_optional as these new gpios are optional
-Only msleep after setting enable high if we have an enable pin
---
  .../bindings/input/touchscreen/pixcir_i2c_ts.txt   |  2 +
  drivers/input/touchscreen/pixcir_i2c_ts.c  | 46 ++
  2 files changed, 48 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt 
b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
index 8eb240a..72ca5ec 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
@@ -10,6 +10,8 @@ Required properties:

  Optional properties:
  - reset-gpio: GPIO connected to the RESET line of the chip
+- enable-gpios: GPIO connected to the ENABLE line of the chip
+- wake-gpios: GPIO connected to the WAKE line of the chip

  Example:

diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c 
b/drivers/input/touchscreen/pixcir_i2c_ts.c
index 211408c..b75ef65 100644
--- a/drivers/input/touchscreen/pixcir_i2c_ts.c
+++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
@@ -38,6 +38,8 @@ struct pixcir_i2c_ts_data {
struct input_dev *input;
struct gpio_desc *gpio_attb;
struct gpio_desc *gpio_reset;
+   struct gpio_desc *gpio_enable;
+   struct gpio_desc *gpio_wake;
const struct pixcir_i2c_chip_data *chip;
int max_fingers;/* Max fingers supported in this instance */
bool running;
@@ -208,6 +210,11 @@ static int pixcir_set_power_mode(struct pixcir_i2c_ts_data 
*ts,
struct device *dev = &ts->client->dev;
int ret;

+   if (mode == PIXCIR_POWER_ACTIVE || mode == PIXCIR_POWER_IDLE) {
+   if (!IS_ERR_OR_NULL(ts->gpio_wake))
+   gpiod_set_value_cansleep(ts->gpio_wake, 1);


I believe you error out in case when IS_ERR(ts->gpio_wake) is true, so I
wonder if we should simply use

if (ts->gpio_wake)
gpiod_set_value_cansleep(ts->gpio_wake, 1);

here and elsewhere.


Yes that will work fine, I believe Sander went with his version because that
is what the existing gpio code (for the also optional reset pin) already does.

So from a consistency pov it is better to keep this patch as is.


No need to resubmit, just let me know.


Ok, either way is fine with me.

Regards,

Hans
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Re: [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Vladimir Zapolskiy]

Hi Marc,

On 20.11.2015 20:02, Marc Zyngier wrote:
> On 20/11/15 17:52, Vladimir Zapolskiy wrote:
>> Hi Rob,
>>
>> On 20.11.2015 18:58, Rob Herring wrote:
>>> On Fri, Nov 20, 2015 at 03:28:38AM +0200, Vladimir Zapolskiy wrote:
 NXP LPC32xx has three interrupt controllers, namely root Main
 Interrupt Controller (MIC) and two supplementary Sub Interrupt
 Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
 are connected to MIC.

 Also the change describes two additional optional properties:
 * interrupt-controller-name - human readable name of an interrupt
   controller,
>>>
>>> Why? compatible is human readable. If you don't like that, then put the 
>>> string in the driver.
>>
>> in runtime I'd like to differentiate various IRQ chips by name. Here for
>> example I have one compatible "*-sic" and two actual IRQ chips SIC1 and
>> SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping
>> I would prefer to visualize interrupts from SIC1 and SIC2.
>>
>> I understand that this property is not hardware specific, but there are
>> plenty of similar properties like "label" etc. Probably renaming of the
>> property may help?
> 
> You can always generate the name based on the probing order or the address.

But the probing order is not guaranteed in general.

It might be confusing, if the spec operates with strictly defined SIC1
and SIC2 names, and in runtime the names of interrupt controllers are
swapped.

Another option might be to introduce different compatibles, but I think
optional label/name property is better.

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Re: [PATCH v3 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks

[Florian Fainelli]

On 20/11/15 07:17, Jon Mason wrote:
> Changes in v3:
> Tweaked the NSP entry names, per Ray Jui
> 
> Changes in v2:
> Rebased off of outstanding NSP DT patches and tweaked the entry names
> per Ray Jui
> 
> 
> This patch series adds device tree support for the Broadcom Northstar,
> Northstar Plus, and Northstar 2 clocks.
> 
> Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to
> the inability to merge because of the driver dependencies.  Those
> necessary driver changes were merged into 4.4.  All comments have been
> addressed and it is ready to be pulled in.

Patches 1-2 applied to devicetree/next
Patch 3 applied to devicetree-arm64/next

Thanks Jon!

> 
> 
> Jon Mason (3):
>   ARM: dts: enable clock support for BCM5301X
>   ARM: dts: enable clock support for Broadcom NSP
>   ARM64: dts: enable clock support for Broadcom NS2
> 
>  arch/arm/boot/dts/bcm-nsp.dtsi| 81 --
>  arch/arm/boot/dts/bcm5301x.dtsi   | 92 
> +++
>  arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +-
>  3 files changed, 216 insertions(+), 37 deletions(-)
> 


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Re: [PATCH 02/11] dt-bindings: clock: add description of LPC32xx USB clock controller

[Vladimir Zapolskiy]

On 20.11.2015 18:41, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 03:05:02AM +0200, Vladimir Zapolskiy wrote:
>> NXP LPC32xx USB controller has a subdevice, which controls USB AHB
>> slave, USB OTG, USB OHCI, USB device and I2C controller to USB phy
>> clocks, this change adds description of the clock controller, for more
>> details reference LPC32xx User's Manual, namely USB control, OTG clock
>> control and OTG clock status registers.
>>
>> Signed-off-by: Vladimir Zapolskiy 
>> ---
>>  .../bindings/clock/nxp,lpc3220-usb-clk.txt | 22 
>> ++
>>  1 file changed, 22 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt 
>> b/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt
>> new file mode 100644
>> index 000..67fba7f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt
>> @@ -0,0 +1,22 @@
>> +NXP LPC32xx USB Clock Controller
>> +
>> +Required properties:
>> +- compatible: should be "nxp,lpc3220-usb-clk"
>> +- reg:  should contain clock controller registers location and length
>> +- #clock-cells: must be 1, the cell holds id of a clock provided by the
>> +  USB clock controller
>> +
>> +Examples:
>> +
>> +usb {
> 
> I don't understand the full structure of USB blocks. Can you make the 
> example complete. All the blocks are a child of this node?

Yes, all the blocks are children of this node.

USB controller contains 5 subdevices, interestingly one of these
subdevices, I2C controller, is the same as a general purpose I2C
controller device.

Please find some description here:
http://www.spinics.net/lists/devicetree/msg98538.html

>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +compatible = "simple-bus";
>> +ranges = <0x0 0x3102 0x1000>;
>> +
>> +usbclk: clock-controller@F00 {
> lower case   ^
> 
>> +compatible = "nxp,lpc3220-usb-clk";
>> +reg = <0xF00 0x100>;
> 
> lower case

Ok, thanks for pointing it out.

>> +#clock-cells = <1>;
>> +};
>> +};
>> -- 
>> 2.1.4
>>

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Re: [PATCH 09/11] clk: lpc32xx: add common clock framework driver

[Vladimir Zapolskiy]

On 20.11.2015 16:04, Arnd Bergmann wrote:
> On Friday 20 November 2015 03:05:09 Vladimir Zapolskiy wrote:
>> +
>> +struct clk_proto_t {
>> +   const char *name;
>> +   const u8 parents[LPC32XX_CLK_PARENTS_MAX];
>> +   u8 num_parents;
>> +   unsigned long flags;
>> +};
>> +
>> +#define CLK_PREFIX(LITERAL)LPC32XX_CLK_ ## LITERAL
>> +#define NUMARGS(...)   (sizeof((int[]){__VA_ARGS__})/sizeof(int))
>> +
>> +#define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...)   \
>> +   [CLK_PREFIX(_idx)] = {  \
>> +   .name = #_name, \
>> +   .flags = _flags,\
>> +   .parents = { __VA_ARGS__ }, \
>> +   .num_parents = NUMARGS(__VA_ARGS__),\
>> +}
>> +
> 
> Try to not outsmart yourself with the macros. It's better to avoid
> string concatenation so it's possible to grep for uses of some
> constant.
> 
> I would probably not use a macro at all here and just open-code the
> entire table. If you ensure that '0' is not a valid parent, then
> you can leave out the .num_parents field and just look for the
> zero-termination.

Macros are here for simplicity, code size reduction and to avoid some
stupid mistakes like different number of .parents and .num_parents.

I believe macro unwrapping in this code will add another 1000 LoC and
will result in quite unreadable and less maintainable code.

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Re: [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Marc Zyngier]

On 20/11/15 17:52, Vladimir Zapolskiy wrote:
> Hi Rob,
> 
> On 20.11.2015 18:58, Rob Herring wrote:
>> On Fri, Nov 20, 2015 at 03:28:38AM +0200, Vladimir Zapolskiy wrote:
>>> NXP LPC32xx has three interrupt controllers, namely root Main
>>> Interrupt Controller (MIC) and two supplementary Sub Interrupt
>>> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
>>> are connected to MIC.
>>>
>>> Also the change describes two additional optional properties:
>>> * interrupt-controller-name - human readable name of an interrupt
>>>   controller,
>>
>> Why? compatible is human readable. If you don't like that, then put the 
>> string in the driver.
> 
> in runtime I'd like to differentiate various IRQ chips by name. Here for
> example I have one compatible "*-sic" and two actual IRQ chips SIC1 and
> SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping
> I would prefer to visualize interrupts from SIC1 and SIC2.
> 
> I understand that this property is not hardware specific, but there are
> plenty of similar properties like "label" etc. Probably renaming of the
> property may help?

You can always generate the name based on the probing order or the address.

Thanks,

M.
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Re: [PATCH 01/11] dt-bindings: clock: add description of LPC32xx clock controller

[Vladimir Zapolskiy]

Arnd,

On 20.11.2015 15:58, Arnd Bergmann wrote:
> On Friday 20 November 2015 03:05:01 Vladimir Zapolskiy wrote:
>> NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
>> of system control block (SCB). CPC is supplied by two external
>> oscillators and it manages core and most of peripheral
>> clocks, the change adds description of DT bindings for clock
>> controller found on LPC32xx SoC series.
>>
>> Signed-off-by: Vladimir Zapolskiy 
>> ---
>>  .../devicetree/bindings/clock/nxp,lpc3220-clk.txt  | 30 
>> ++
>>  1 file changed, 30 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt 
>> b/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt
>> new file mode 100644
>> index 000..20cbca3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt
>> @@ -0,0 +1,30 @@
>> +NXP LPC32xx Clock Controller
>> +
>> +Required properties:
>> +- compatible: should be "nxp,lpc3220-clk"
> 
> Please use a specific model number without 'xx' wildcards. If you have
> multiple chips that are mutually compatible, pick one as the base number
> and then list the others as more specific instances, like
> 
>   compatible = "nxp,lpc3250-clk", "nxp,lpc3220-clk";

Do you ask me to change a title? You may see that compatible property
does not contain any wildcards?

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[PATCH 3/3] ARM: dts: enable pinctrl for Broadcom NSP

[Yendapally Reddy Dhananjaya Reddy]

This enables the pinctrl support for Broadcom NSP SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy 
---
 arch/arm/boot/dts/bcm-nsp.dtsi   | 7 +++
 arch/arm/boot/dts/bcm958625k.dts | 9 +
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b74438c..a16d743 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -226,5 +226,12 @@
interrupts = ;
clock-frequency = <10>;
};
+
+   pinctrl: pinctrl@3f1c0 {
+   compatible = "brcm,nsp-pinmux";
+   reg = <0x3f1c0 0x04>,
+ <0x30028 0x04>,
+ <0x3f408 0x04>;
+   };
};
 };
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index b966955..e298450 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -105,3 +105,12 @@
};
};
 };
+
+&pinctrl {
+   pinctrl-names = "default";
+   pinctrl-0 = <&nand_sel>;
+   nand_sel: nand_sel {
+   function = "nand";
+   groups = "nand_grp";
+   };
+};
-- 
2.1.0

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Re: [PATCH 03/11] dt-bindings: clock: add NXP LPC32xx clock list for consumers

[Vladimir Zapolskiy]

On 20.11.2015 15:56, Arnd Bergmann wrote:
> On Friday 20 November 2015 03:05:03 Vladimir Zapolskiy wrote:
>> +
>> +/* LPC32XX System Control Block clocks */
>> +#define LPC32XX_CLK_RTC0
>> +#define LPC32XX_CLK_DMA1
>> +#define LPC32XX_CLK_MLC2
>> +#define LPC32XX_CLK_SLC3
>> +#define LPC32XX_CLK_LCD4
>> +#define LPC32XX_CLK_MAC5
>> +#define LPC32XX_CLK_SD 6
>> +#define LPC32XX_CLK_DDRAM  7
>> +#define LPC32XX_CLK_SSP0   8
>> +#define LPC32XX_CLK_SSP1   9
>> +#define LPC32XX_CLK_UART3  10
>> +#define LPC32XX_CLK_UART4  11
>> +#define LPC32XX_CLK_UART5  12
>> +#define LPC32XX_CLK_UART6  13
>> +#define LPC32XX_CLK_IRDA   14
>> +#define LPC32XX_CLK_I2C1   15
>>
> 
> Any chance we can avoid the include file? This is going to make it really
> hard to merge everything in one merge window with the dependencies between
> the driver, the bindings and the platform code.

I see only one option to avoid this commit, namely squash it with the
CCF driver and merge it before making changes in DTS.

However I suppose ARM trees won't be synced on clk tree, so probably it
won't simplify maintainer's work.

> If there is a way to describe the clocks based on numbers from the
> data sheet instead of making up your own, that makes life much
> easier for us.

There are no any clock numbers in the datasheet, unfortunately.

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[PATCH 1/3] pinctrl: Broadcom NSP pinctrl device tree bindings

[Yendapally Reddy Dhananjaya Reddy]

Device tree binding documentation for Broadcom NSP IOMUX driver

Signed-off-by: Yendapally Reddy Dhananjaya Reddy 
---
 .../bindings/pinctrl/brcm,nsp-pinmux.txt   | 79 ++
 1 file changed, 79 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt 
b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt
new file mode 100644
index 000..603564e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt
@@ -0,0 +1,79 @@
+Broadcom NSP (Northstar plus) IOMUX Controller
+
+The NSP IOMUX controller supports group based mux configuration. In
+addition, certain pins can be muxed to GPIO function individually.
+
+Required properties:
+- compatible:
+Must be "brcm,nsp-pinmux"
+
+- reg:
+Should contain the register physical address and length for each of
+GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers
+
+Properties in subnodes:
+- function:
+The mux function to select
+
+- groups:
+The list of groups to select with a given function
+
+For more details, refer to
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+For example:
+
+   pinmux: pinmux@1803f1c0 {
+   compatible = "brcm,nsp-pinmux";
+   reg = <0x1803f1c0 0x04>,
+ <0x18030028 0x04>,
+ <0x1803f408 0x04>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm &gpio_b &nand_sel>;
+
+   pwm: pwm {
+   function = "pwm";
+   groups = "pwm0_grp", "pwm1_grp";
+   };
+
+   gpio_b: gpio_b {
+   function = "gpio_b";
+   groups = "gpio_b_0_grp", "gpio_b_1_grp";
+   };
+
+   nand_sel: nand_sel {
+   function = "nand";
+   groups = "nand_grp";
+   };
+   };
+
+List of supported functions and groups in Northstar Plus:
+
+"spi": "spi_grp"
+
+"i2c": "i2c_grp"
+
+"mdio": "mdio_grp"
+
+"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
+
+"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"
+
+"uart1": "uart1_grp"
+
+"uart2": "uart2_grp"
+
+"synce": "synce_grp"
+
+"sata_led_grps": "sata0_led_grp", "sata1_led_grp"
+
+"xtal_out": "xtal_out_grp"
+
+"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
+
+"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"
+
+"nand": "nand_grp"
+
+"emmc": "emmc_grp"
-- 
2.1.0

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Re: [RFC/PATCH] pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindings

[Stephen Boyd]

On 11/19, Rob Herring wrote:
> On Tue, Nov 17, 2015 at 05:00:26PM -0800, Stephen Boyd wrote:
> > The drivers don't really need to know which PMIC they're for, so
> > make a generic binding for them. This alleviates us from updating
> > the drivers every time a new PMIC comes out. It's still
> > recommended that we update the binding with new PMIC models and
> > always specify the specific model for the MPPs and gpios before
> > the generic compatible string in devicetree, but this at least
> > cuts down on adding more and more compatible strings to the
> > drivers until we actually need them.
> > 
> > Cc: 
> > Cc: "Ivan T. Ivanov" 
> > Cc: Bjorn Andersson 
> > Signed-off-by: Stephen Boyd 
> > ---
> 
> Seems okay to me. I assume you are going to update all the dts files?

Yep, I'll send out patches to do that.

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Re: [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Vladimir Zapolskiy]

Hi Rob,

On 20.11.2015 18:58, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 03:28:38AM +0200, Vladimir Zapolskiy wrote:
>> NXP LPC32xx has three interrupt controllers, namely root Main
>> Interrupt Controller (MIC) and two supplementary Sub Interrupt
>> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
>> are connected to MIC.
>>
>> Also the change describes two additional optional properties:
>> * interrupt-controller-name - human readable name of an interrupt
>>   controller,
> 
> Why? compatible is human readable. If you don't like that, then put the 
> string in the driver.

in runtime I'd like to differentiate various IRQ chips by name. Here for
example I have one compatible "*-sic" and two actual IRQ chips SIC1 and
SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping
I would prefer to visualize interrupts from SIC1 and SIC2.

I understand that this property is not hardware specific, but there are
plenty of similar properties like "label" etc. Probably renaming of the
property may help?

>> * wakeup-sources - list of mappings between a hardware interrupt and
>>   its correspondent wakeup source to exit CPU STOP mode.
> 
> This needs further discussion as I mentioned.

Ok.

> The rest looks fine.
> 

Thanks for review.

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Re: [PATCH v4] mmc: OCTEON: Add host driver for OCTEON MMC controller

[Aaro Koskinen]

Hi,

On Mon, May 18, 2015 at 02:40:44PM -0700, Aleksey Makarov wrote:
> On 05/18/2015 02:05 PM, Aaro Koskinen wrote:
> >On Mon, Mar 16, 2015 at 06:06:00PM +0300, Aleksey Makarov wrote:
> >>The OCTEON MMC controller is currently found on cn61XX and cnf71XX
> >>devices.  Device parameters are configured from device tree data.
> >>
> >>eMMC, MMC and SD devices are supported.
> >>
> >>Tested-by: Aaro Koskinen 
> >>Signed-off-by: Chandrakala Chavva 
> >>Signed-off-by: David Daney 
> >>Signed-off-by: Aleksey Makarov 
> >>Signed-off-by: Leonid Rosenboim 
> >>Signed-off-by: Peter Swain 
> >>Signed-off-by: Aaron Williams 
> >>---
> >
> >Any updates on this patch? Are you still working on it for
> >the mainline kernel inclusion?
>
> We are working on it.  It will also be used in ARM ThunderX arch.  So we
> will send a new version soon.

Any updates?

Also distros are waiting for this patch, MMC is the main medium on
some boards:

https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=800594

A.
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Re: [Xen-devel] [PATCH 11/13] xen/hvm/params: Add a new dilivery type for event-channel in HVM_PARAM_CALLBACK_IRQ

[Stefano Stabellini]

On Fri, 20 Nov 2015, Andrew Cooper wrote:
> On 20/11/15 17:07, Stefano Stabellini wrote:
> > On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> >> From: Shannon Zhao 
> >>
> >> Add a new dilivery type:
> > delivery
> >
> >> val[63:56] == 3: val[15:8] is flag: val[7:0] is a PPI.
> >> To the flag, bit 0 stands the interrupt mode is edge(1) or level(0) and
> >> bit 1 stands the interrupt polarity is active low(1) or high(0).
> >>
> >> Signed-off-by: Shannon Zhao 
> >> ---
> >>  include/xen/interface/hvm/params.h | 5 +
> >>  1 file changed, 5 insertions(+)
> >>
> >> diff --git a/include/xen/interface/hvm/params.h 
> >> b/include/xen/interface/hvm/params.h
> >> index a6c7991..550688a 100644
> >> --- a/include/xen/interface/hvm/params.h
> >> +++ b/include/xen/interface/hvm/params.h
> >> @@ -34,6 +34,11 @@
> >>   *  Domain = val[47:32], Bus  = val[31:16],
> >>   *  DevFn  = val[15: 8], IntX = val[ 1: 0]
> >>   * val[63:56] == 2: val[7:0] is a vector number.
> >> + * val[63:56] == 3: val[15:8] is flag of event-channel interrupt:
> >> + *  bit 0: interrupt is edge(1) or level(0) triggered
> >> + *  bit 1: interrupt is active low(1) or high(0)
> >> + *  val[7:0] is PPI number used by event-channel.
> >> + *  This is only used by ARM/ARM64.
> >>   * If val == 0 then CPU0 event-channel notifications are not delivered.
> >>   */
> >>  #define HVM_PARAM_CALLBACK_IRQ 0
> 
> Sadly NACK in this form.
> 
> This is not your fault, but this particular field has hidden ABI which
> the original submitter neglected to put into public API.
> 
> Bits 63:56 of this field currently have a hidden ABI with:
> 
> xen/include/asm-x86/hvm/irq.h
> enum {
> HVMIRQ_callback_none,
> HVMIRQ_callback_gsi,
> HVMIRQ_callback_pci_intx,
> HVMIRQ_callback_vector
> } callback_via_type;
 
I take the value should be "4" then?


> I will submit a patch to fix this this properly.

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Re: [PATCH 13/13] ARM: XEN: Move xen_early_init() before efi_init()

[Stefano Stabellini]

On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> From: Shannon Zhao 
> 
> Move xen_early_init() before efi_init(), then when calling efi_init()
> could initialize Xen specific UEFI.
> 
> Check if it runs on Xen hypervisor through the flat dts.
> 
> Signed-off-by: Shannon Zhao 
> ---
>  arch/arm/xen/enlighten.c  | 62 
> ---
>  arch/arm64/kernel/setup.c |  2 +-
>  2 files changed, 49 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index b8e9db8..d4f884c 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -48,8 +49,6 @@ struct xen_memory_region 
> xen_extra_mem[XEN_EXTRA_MEM_MAX_REGIONS] __initdata;
>  
>  static __read_mostly unsigned int xen_events_irq;
>  
> -static __initdata struct device_node *xen_node;
> -
>  int xen_remap_domain_gfn_array(struct vm_area_struct *vma,
>  unsigned long addr,
>  xen_pfn_t *gfn, int nr,
> @@ -142,6 +141,34 @@ static irqreturn_t xen_arm_callback(int irq, void *arg)
>   return IRQ_HANDLED;
>  }
>  
> +struct xen_node_info {
> + const char *compat;
> + const char *prefix;
> + const char *version;
> + bool found;
> +};
> +
> +static int __init fdt_find_xen_node(unsigned long node, const char *uname,
> + int depth, void *data)
> +{
> + struct xen_node_info *info = data;
> + const void *s = NULL;
> + int len;
> +
> + if (depth != 1 || strcmp(uname, "hypervisor") != 0)
> + return 0;
> +
> + if (of_flat_dt_is_compatible(node, info->compat))
> + info->found = true;
> +
> + s = of_get_flat_dt_prop(node, "compatible", &len);
> + if (strlen(info->prefix) + 3  < len &&
> +!strncmp(info->prefix, s, strlen(info->prefix)))
> +info->version = s + strlen(info->prefix);
> + return 0;
> +}
> +
>  /*
>   * see Documentation/devicetree/bindings/arm/xen.txt for the
>   * documentation of the Xen Device Tree format.
> @@ -149,26 +176,25 @@ static irqreturn_t xen_arm_callback(int irq, void *arg)
>  #define GRANT_TABLE_PHYSADDR 0
>  void __init xen_early_init(void)
>  {
> - int len;
> - const char *s = NULL;
> - const char *version = NULL;
> - const char *xen_prefix = "xen,xen-";
> + struct xen_node_info info;
> +
> + info.compat = "xen,xen";
> + info.prefix = "xen,xen-";
> + info.version = NULL;
> + info.found = false;

Can you initialize the fields directly when you define xen_node_info and
make it static?

The rest looks good.


> - xen_node = of_find_compatible_node(NULL, NULL, "xen,xen");
> - if (!xen_node) {
> + of_scan_flat_dt(fdt_find_xen_node, &info);
> + if (!info.found) {
>   pr_debug("No Xen support\n");
>   return;
>   }
> - s = of_get_property(xen_node, "compatible", &len);
> - if (strlen(xen_prefix) + 3  < len &&
> - !strncmp(xen_prefix, s, strlen(xen_prefix)))
> - version = s + strlen(xen_prefix);
>
> - if (version == NULL) {
> +
> + if (info.version == NULL) {
>   pr_debug("Xen version not found\n");
>   return;
>   }
>  
> - pr_info("Xen %s support found\n", version);
> + pr_info("Xen %s support found\n", info.version);
>  
>   xen_domain_type = XEN_HVM_DOMAIN;
>  
> @@ -204,6 +230,14 @@ static int __init xen_guest_init(void)
>   }
>   xen_events_irq = a.value & 0xff;
>   } else {
> + struct device_node *xen_node;
> +
> + xen_node = of_find_compatible_node(NULL, NULL, "xen,xen");
> + if (!xen_node) {
> + pr_debug("No Xen support\n");
> + return -ENODEV;
> + }
> +
>   xen_events_irq = irq_of_parse_and_map(xen_node, 0);
>   if (!xen_events_irq) {
>   pr_err("Xen event channel interrupt not found\n");
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index 2322479..ee95593 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -428,6 +428,7 @@ void __init setup_arch(char **cmdline_p)
>*/
>   local_async_enable();
>  
> + xen_early_init();
>   efi_init();
>   arm64_memblock_init();
>  
> @@ -446,7 +447,6 @@ void __init setup_arch(char **cmdline_p)
>   } else {
>   psci_acpi_init();
>   }
> - xen_early_init();
>  
>   cpu_read_bootcpu_ops();
>   smp_init_cpus();
> -- 
> 2.1.0
> 
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Re: [PATCH v3 5/9] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 7:12 PM, Maxime Ripard
 wrote:
> Hi,
>
> On Tue, Nov 17, 2015 at 12:38:24AM +0800, Chen-Yu Tsai wrote:
>> This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
>> provide power to various parts of the SoC and the board.
>>
>> Also update the regulator supply phandles.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 79 
>> +-
>>  1 file changed, 76 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
>> b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> index 13ce68f06dd6..91a0fde47fdd 100644
>> --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> @@ -68,7 +68,7 @@
>>  };
>>
>>  &lradc {
>> - vref-supply = <®_vcc3v0>;
>> + vref-supply = <®_dcdc1>;
>>   status = "okay";
>>
>>   button@200 {
>> @@ -96,7 +96,7 @@
>>  &mmc0 {
>>   pinctrl-names = "default";
>>   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
>> - vmmc-supply = <®_vcc3v0>;
>> + vmmc-supply = <®_dcdc1>;
>>   bus-width = <4>;
>>   cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
>>   cd-inverted;
>> @@ -106,7 +106,7 @@
>>  &mmc2 {
>>   pinctrl-names = "default";
>>   pinctrl-0 = <&mmc2_8bit_pins>;
>> - vmmc-supply = <®_vcc3v0>;
>> + vmmc-supply = <®_dcdc1>;
>>   bus-width = <8>;
>>   non-removable;
>>   status = "okay";
>> @@ -132,6 +132,79 @@
>>
>>  &r_rsb {
>>   status = "okay";
>> +
>> + axp22x: pmic@3e3 {
>> + compatible = "x-powers,axp223";
>> + reg = <0x3e3>;
>> + interrupt-parent = <&nmi_intc>;
>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> + eldoin-supply = <®_dcdc1>;
>> + };
>> +};
>> +
>> +#include "axp22x.dtsi"
>> +
>> +®_aldo1 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-io";
>> +};
>> +
>> +®_aldo2 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <235>;
>> + regulator-max-microvolt = <265>;
>> + regulator-name = "vdd-dll";
>> +};
>> +
>> +®_aldo3 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <270>;
>> + regulator-max-microvolt = <330>;
>> + regulator-name = "vcc-pll-avcc";
>> +};
>> +
>> +®_dc5ldo {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-cpus";
>> +};
>> +
>> +®_dcdc1 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-3v0";
>> +};
>> +
>> +®_dcdc2 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-sys";
>> +};
>> +
>> +®_dcdc3 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-cpu";
>> +};
>> +
>> +®_dcdc5 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <150>;
>> + regulator-max-microvolt = <150>;
>> + regulator-name = "vcc-dram";
>> +};
>> +
>> +®_rtc_ldo {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-rtc";
>>  };
>
> Isn't this supposed to be in the AXP DTSI?

Are you referring to ®_rtc_ldo? Yes, it should. I'll do a new version.

Thanks
ChenYu
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Re: [PATCH 4/7] touchscreen: pixcir_i2c: Add support for wake and enable gpios

[Dmitry Torokhov]

On Fri, Nov 20, 2015 at 12:17:10PM +0100, Hans de Goede wrote:
> From: Sander Vermin 
> 
> On some devices the wake and enable pins of the pixcir touchscreen
> controller are connected to gpios and these must be controlled by the
> driver for the device to operate properly.
> 
> Signed-off-by: Sander Vermin 
> Signed-off-by: Hans de Goede 
> ---
> Changes in v2 (Hans de Goede):
> -Split the changes for dealing with inverted / swapped axis out into a
>  separate patch
> -Remove a bunch of dev_info calls to make the driver less chatty
> -Use devm_gpiod_get_optional as these new gpios are optional
> -Only msleep after setting enable high if we have an enable pin
> ---
>  .../bindings/input/touchscreen/pixcir_i2c_ts.txt   |  2 +
>  drivers/input/touchscreen/pixcir_i2c_ts.c  | 46 
> ++
>  2 files changed, 48 insertions(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt 
> b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> index 8eb240a..72ca5ec 100644
> --- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> +++ b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt
> @@ -10,6 +10,8 @@ Required properties:
>  
>  Optional properties:
>  - reset-gpio: GPIO connected to the RESET line of the chip
> +- enable-gpios: GPIO connected to the ENABLE line of the chip
> +- wake-gpios: GPIO connected to the WAKE line of the chip
>  
>  Example:
>  
> diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c 
> b/drivers/input/touchscreen/pixcir_i2c_ts.c
> index 211408c..b75ef65 100644
> --- a/drivers/input/touchscreen/pixcir_i2c_ts.c
> +++ b/drivers/input/touchscreen/pixcir_i2c_ts.c
> @@ -38,6 +38,8 @@ struct pixcir_i2c_ts_data {
>   struct input_dev *input;
>   struct gpio_desc *gpio_attb;
>   struct gpio_desc *gpio_reset;
> + struct gpio_desc *gpio_enable;
> + struct gpio_desc *gpio_wake;
>   const struct pixcir_i2c_chip_data *chip;
>   int max_fingers;/* Max fingers supported in this instance */
>   bool running;
> @@ -208,6 +210,11 @@ static int pixcir_set_power_mode(struct 
> pixcir_i2c_ts_data *ts,
>   struct device *dev = &ts->client->dev;
>   int ret;
>  
> + if (mode == PIXCIR_POWER_ACTIVE || mode == PIXCIR_POWER_IDLE) {
> + if (!IS_ERR_OR_NULL(ts->gpio_wake))
> + gpiod_set_value_cansleep(ts->gpio_wake, 1);

I believe you error out in case when IS_ERR(ts->gpio_wake) is true, so I
wonder if we should simply use

if (ts->gpio_wake)
gpiod_set_value_cansleep(ts->gpio_wake, 1);

here and elsewhere.

No need to resubmit, just let me know.

Thanks.

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Re: [Xen-devel] [PATCH 11/13] xen/hvm/params: Add a new dilivery type for event-channel in HVM_PARAM_CALLBACK_IRQ

[Andrew Cooper]

On 20/11/15 17:07, Stefano Stabellini wrote:
> On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
>> From: Shannon Zhao 
>>
>> Add a new dilivery type:
> delivery
>
>> val[63:56] == 3: val[15:8] is flag: val[7:0] is a PPI.
>> To the flag, bit 0 stands the interrupt mode is edge(1) or level(0) and
>> bit 1 stands the interrupt polarity is active low(1) or high(0).
>>
>> Signed-off-by: Shannon Zhao 
>> ---
>>  include/xen/interface/hvm/params.h | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/include/xen/interface/hvm/params.h 
>> b/include/xen/interface/hvm/params.h
>> index a6c7991..550688a 100644
>> --- a/include/xen/interface/hvm/params.h
>> +++ b/include/xen/interface/hvm/params.h
>> @@ -34,6 +34,11 @@
>>   *  Domain = val[47:32], Bus  = val[31:16],
>>   *  DevFn  = val[15: 8], IntX = val[ 1: 0]
>>   * val[63:56] == 2: val[7:0] is a vector number.
>> + * val[63:56] == 3: val[15:8] is flag of event-channel interrupt:
>> + *  bit 0: interrupt is edge(1) or level(0) triggered
>> + *  bit 1: interrupt is active low(1) or high(0)
>> + *  val[7:0] is PPI number used by event-channel.
>> + *  This is only used by ARM/ARM64.
>>   * If val == 0 then CPU0 event-channel notifications are not delivered.
>>   */
>>  #define HVM_PARAM_CALLBACK_IRQ 0

Sadly NACK in this form.

This is not your fault, but this particular field has hidden ABI which
the original submitter neglected to put into public API.

Bits 63:56 of this field currently have a hidden ABI with:

xen/include/asm-x86/hvm/irq.h
enum {
HVMIRQ_callback_none,
HVMIRQ_callback_gsi,
HVMIRQ_callback_pci_intx,
HVMIRQ_callback_vector
} callback_via_type;

I will submit a patch to fix this this properly.

~Andrew
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Re: [PATCH] usb: dwc2: add support of hi6220

[Felipe Balbi]

"Herrero, Gregory"  writes:

> Hi Felipe,
>
> I just realized this patch miss "dma_desc_fs_enable" property in
> params_hi6220. (drivers/usb/dwc2/platform.c:57)
>
> You need to apply this patch:
>
> diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
> index d5102c4..2dfdae3 100644
> --- a/drivers/usb/dwc2/platform.c
> +++ b/drivers/usb/dwc2/platform.c
> @@ -59,6 +59,7 @@ static const struct dwc2_core_params params_hi6220 = {
> .otg_ver= 0,/* 1.3 */
> .dma_enable = 1,
> .dma_desc_enable= 0,
> +   .dma_desc_fs_enable = 0,
> .speed  = 0,/* High Speed */
> .enable_dynamic_fifo= 1,
> .en_multiple_tx_fifo= 1,
>
>
> Note that it is needed due to below patch.
> "usb: dwc2: host: enable descriptor dma for fs devices"

done, thanks.

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Re: [PATCH v11 6/8] Input: goodix - add support for ESD

[Dmitry Torokhov]

On Fri, Nov 20, 2015 at 7:44 AM, Rob Herring  wrote:
> On Thu, Nov 19, 2015 at 02:26:39PM +0200, Irina Tirdea wrote:
>> Add ESD (Electrostatic Discharge) protection mechanism.
>
> [...]
>
>> This is based on Goodix datasheets for GT911 and GT9271 and on Goodix
>> driver gt9xx.c for Android (publicly available in Android kernel
>> trees for various devices).
>>
>> Signed-off-by: Irina Tirdea 
>> For the binding: Acked-by: Rob Herring 
>
> You should not have the "For the binding:" part here. It was just a note
> so it was clear what part I looked at.
>
> It is preferred to split DT bindings to separate patches for this
> reason.
>

It however does not make sense if one wants to research when and why
something was changed. We do not split patches to .h files from .c
either.

Whenever I can I merge the driver and dt binding changes together if
they have been posted and reviewed as separate patches. The
Acks/Reviewed are mostly important for maintainers anyway.

Thanks.

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Re: [PATCH 10/13] ARM64: ACPI: Check if it runs on Xen to enable or disable ACPI

[Stefano Stabellini]

On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> From: Shannon Zhao 
> 
> When it's a Xen domain0 booting with ACPI, it will supply a /chosen and
> a /hypervisor node in DT. So check if it needs to enable ACPI.
> 
> Signed-off-by: Shannon Zhao 
> ---
>  arch/arm64/kernel/acpi.c | 12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index 19de753..7b67426 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -62,10 +62,13 @@ static int __init dt_scan_depth1_nodes(unsigned long node,
>  {
>   /*
>* Return 1 as soon as we encounter a node at depth 1 that is
> -  * not the /chosen node.
> +  * not the /chosen node or to Xen initial domain that is not
> +  * either /chosen or /hypervisor node.

* not the /chosen node, or /hypervisor node when running on Xen.

>*/
>   if (depth == 1 && (strcmp(uname, "chosen") != 0))
> - return 1;
> + if (!xen_initial_domain() || (strcmp(uname, "hypervisor") != 0))
> + return 1;

Please add { } around the inner if statement.


>   return 0;
>  }
>  
> @@ -179,8 +182,9 @@ void __init acpi_boot_table_init(void)
>   /*
>* Enable ACPI instead of device tree unless
>* - ACPI has been disabled explicitly (acpi=off), or
> -  * - the device tree is not empty (it has more than just a /chosen node)
> -  *   and ACPI has not been force enabled (acpi=force)
> +  * - the device tree is not empty (it has more than just a /chosen node
> +  *   or to Xen initial domain it has more than a /chosen node and
> +  *   /hypervisor node) and ACPI has not been force enabled (acpi=force)

the device tree is not empty (it has more than just a /chosen node, and
an /hypervisor node when running on Xen


>*/
>   if (param_acpi_off ||
>   (!param_acpi_force && of_scan_flat_dt(dt_scan_depth1_nodes, NULL)))
> -- 
> 2.1.0
> 
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Re: [PATCH 12/13] arm/xen: Get event-channel irq through HVM_PARAM when booting with ACPI

[Stefano Stabellini]

On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> From: Shannon Zhao 
> 
> When booting with ACPI, it could get the event-channel irq through
> HVM_PARAM_CALLBACK_IRQ.
> 
> Signed-off-by: Shannon Zhao 
> ---
>  arch/arm/xen/enlighten.c | 23 +++
>  1 file changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 1373d6d..b8e9db8 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  
> @@ -190,10 +191,24 @@ static int __init xen_guest_init(void)
>   if (!xen_domain())
>   return 0;
>  
> - xen_events_irq = irq_of_parse_and_map(xen_node, 0);
> - if (!xen_events_irq) {
> - pr_err("Xen event channel interrupt not found\n");
> - return -ENODEV;
> + if (!acpi_disabled) {
> + struct xen_hvm_param a;
> +
> + a.domid = DOMID_SELF;
> + a.index = HVM_PARAM_CALLBACK_IRQ;
> + if (HYPERVISOR_hvm_op(HVMOP_get_param, &a)) {

If HYPERVISOR_hvm_op returns an error (ret != 0), I wouldn't bother
checking for the returned value and simply return error.

On the other hand, if HYPERVISOR_hvm_op is successful (ret == 0), then
it might make sense to check for (a.value >> 56) == 3.


> + if ((a.value >> 56) != 3) {
> + pr_err("Can't get Xen event-channel irq\n");
> + return -ENODEV;
> + }
> + }
> + xen_events_irq = a.value & 0xff;
> + } else {
> + xen_events_irq = irq_of_parse_and_map(xen_node, 0);
> + if (!xen_events_irq) {
> + pr_err("Xen event channel interrupt not found\n");
> + return -ENODEV;

Please make the error message common and move it out of the if/else.


> + }
>   }
>  
>   shared_info_page = (struct shared_info *)get_zeroed_page(GFP_KERNEL);
> -- 
> 2.1.0
> 
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Re: [PATCH v3 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks

[Ray Jui]

Hi Jon,

On 11/20/2015 7:17 AM, Jon Mason wrote:

Changes in v3:
Tweaked the NSP entry names, per Ray Jui

Changes in v2:
Rebased off of outstanding NSP DT patches and tweaked the entry names
per Ray Jui


This patch series adds device tree support for the Broadcom Northstar,
Northstar Plus, and Northstar 2 clocks.

Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to
the inability to merge because of the driver dependencies.  Those
necessary driver changes were merged into 4.4.  All comments have been
addressed and it is ready to be pulled in.


Jon Mason (3):
   ARM: dts: enable clock support for BCM5301X
   ARM: dts: enable clock support for Broadcom NSP
   ARM64: dts: enable clock support for Broadcom NS2

  arch/arm/boot/dts/bcm-nsp.dtsi| 81 --
  arch/arm/boot/dts/bcm5301x.dtsi   | 92 +++
  arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +-
  3 files changed, 216 insertions(+), 37 deletions(-)



This entire patch series looks good to me! Thanks!

Reviewed-by: Ray Jui 
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Re: [PATCH 11/13] xen/hvm/params: Add a new dilivery type for event-channel in HVM_PARAM_CALLBACK_IRQ

[Stefano Stabellini]

On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> From: Shannon Zhao 
> 
> Add a new dilivery type:

delivery

> val[63:56] == 3: val[15:8] is flag: val[7:0] is a PPI.
> To the flag, bit 0 stands the interrupt mode is edge(1) or level(0) and
> bit 1 stands the interrupt polarity is active low(1) or high(0).
> 
> Signed-off-by: Shannon Zhao 
> ---
>  include/xen/interface/hvm/params.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/xen/interface/hvm/params.h 
> b/include/xen/interface/hvm/params.h
> index a6c7991..550688a 100644
> --- a/include/xen/interface/hvm/params.h
> +++ b/include/xen/interface/hvm/params.h
> @@ -34,6 +34,11 @@
>   *  Domain = val[47:32], Bus  = val[31:16],
>   *  DevFn  = val[15: 8], IntX = val[ 1: 0]
>   * val[63:56] == 2: val[7:0] is a vector number.
> + * val[63:56] == 3: val[15:8] is flag of event-channel interrupt:
> + *  bit 0: interrupt is edge(1) or level(0) triggered
> + *  bit 1: interrupt is active low(1) or high(0)
> + *  val[7:0] is PPI number used by event-channel.
> + *  This is only used by ARM/ARM64.
>   * If val == 0 then CPU0 event-channel notifications are not delivered.
>   */
>  #define HVM_PARAM_CALLBACK_IRQ 0
> -- 
> 2.1.0
> 
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Re: [PATCH 08/13] Xen: EFI: Parse DT parameters for Xen specific UEFI

[Stefano Stabellini]

On Tue, 17 Nov 2015, shannon.z...@linaro.org wrote:
> From: Shannon Zhao 
> 
> Add a new function to parse DT parameters for Xen specific UEFI just
> like the way for normal UEFI. Then it could reuse the existing codes.
> 
> Signed-off-by: Shannon Zhao 
> ---
>  drivers/firmware/efi/efi.c | 67 
> ++
>  1 file changed, 62 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
> index d6144e3..629bd06 100644
> --- a/drivers/firmware/efi/efi.c
> +++ b/drivers/firmware/efi/efi.c
> @@ -24,6 +24,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  struct efi __read_mostly efi = {
>   .mps= EFI_INVALID_TABLE_ADDR,
> @@ -488,12 +489,60 @@ static __initdata struct {
>   UEFI_PARAM("MemMap Desc. Version", "linux,uefi-mmap-desc-ver", desc_ver)
>  };
>  
> +static __initdata struct {
> + const char name[32];
> + const char propname[32];
> + int offset;
> + int size;
> +} xen_dt_params[] = {
> + UEFI_PARAM("System Table", "xen,uefi-system-table", system_table),
> + UEFI_PARAM("MemMap Address", "xen,uefi-mmap-start", mmap),
> + UEFI_PARAM("MemMap Size", "xen,uefi-mmap-size", mmap_size),
> + UEFI_PARAM("MemMap Desc. Size", "xen,uefi-mmap-desc-size", desc_size),
> + UEFI_PARAM("MemMap Desc. Version", "xen,uefi-mmap-desc-ver", desc_ver)
> +};
> +
>  struct param_info {
>   int verbose;
>   int found;
>   void *params;
>  };
>  
> +static int __init fdt_find_xen_uefi_params(unsigned long node,
> +const char *uname, int depth,
> +void *data)
> +{
> + struct param_info *info = data;
> + const void *prop;
> + void *dest;
> + u64 val;
> + int i, len;
> +
> + if (xen_initial_domain() && (depth != 2 || strcmp(uname, "uefi") != 0))
> + return 0;
> +
> + for (i = 0; i < ARRAY_SIZE(xen_dt_params); i++) {
> + prop = of_get_flat_dt_prop(node, xen_dt_params[i].propname,
> +&len);
> + if (!prop)
> + return 0;
> + dest = info->params + xen_dt_params[i].offset;
> + info->found++;
> +
> + val = of_read_number(prop, len / sizeof(u32));
> +
> + if (dt_params[i].size == sizeof(u32))
> + *(u32 *)dest = val;
> + else
> + *(u64 *)dest = val;
> +
> + if (info->verbose)
> + pr_info("  %s: 0x%0*llx\n", xen_dt_params[i].name,
> + xen_dt_params[i].size * 2, val);
> + }
> +
> + return 1;
> +}
>  static int __init fdt_find_uefi_params(unsigned long node, const char *uname,
>  int depth, void *data)
>  {
> @@ -538,12 +587,20 @@ int __init efi_get_fdt_params(struct efi_fdt_params 
> *params, int verbose)
>   info.found = 0;
>   info.params = params;
>  
> - ret = of_scan_flat_dt(fdt_find_uefi_params, &info);
> - if (!info.found)
> + if (xen_initial_domain())
> + ret = of_scan_flat_dt(fdt_find_xen_uefi_params, &info);
> + else
> + ret = of_scan_flat_dt(fdt_find_uefi_params, &info);
> + if (!info.found) {
>   pr_info("UEFI not found.\n");
> - else if (!ret)
> - pr_err("Can't find '%s' in device tree!\n",
> -dt_params[info.found].name);
> + } else if (!ret) {
> + if (xen_initial_domain())
> + pr_err("Can't find '%s' in device tree!\n",
> +xen_dt_params[info.found].name);
> + else
> + pr_err("Can't find '%s' in device tree!\n",
> +xen_dt_params[info.found].name);

xen_dt_params is obviously wrong here

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RE: [PATCH v2 6/7] Documentation: Rename gpio controller name from cygnus to iproc

[Pramod Kumar]

Hi Rob,

> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: 20 November 2015 21:05
> To: Pramod Kumar
> Cc: Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Ray Jui; Scott 
> Branden;
> Russell King; Linus Walleij; linux-g...@vger.kernel.org; bcm-kernel-feedback-
> list; Jason Uy; Masahiro Yamada; Thomas Gleixner; Laurent Pinchart;
> devicetree@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Jonas Gorski
> Subject: Re: [PATCH v2 6/7] Documentation: Rename gpio controller name from
> cygnus to iproc
> 
> On Thu, Nov 19, 2015 at 09:22:18AM +0530, Pramod Kumar wrote:
> > Renamed gpio controller's driver name from cygnus to iproc to make it
> > more generic so that all iProc based SoCs having the same gpio
> > controller could use this.
> >
> > Signed-off-by: Pramod Kumar 
> > Reviewed-by: Ray Jui 
> > Reviewed-by: Scott Branden 
> 
> Where's my ack?

Somehow it got missed. I'm sincerely apologetic for it. Will add it.  

Regards,
Pramod
> 
> > ---
> >  .../bindings/pinctrl/{brcm,cygnus-gpio.txt => brcm,iproc-gpio.txt}| 4 
> > ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)  rename
> > Documentation/devicetree/bindings/pinctrl/{brcm,cygnus-gpio.txt =>
> > brcm,iproc-gpio.txt} (97%)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
> > b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
> > similarity index 97%
> > rename from
> > Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
> > rename to
> > Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
> > index 8b1e5d1..e427792 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
> > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
> > @@ -1,4 +1,4 @@
> > -Broadcom Cygnus GPIO/PINCONF Controller
> > +Broadcom iProc GPIO/PINCONF Controller
> >
> >  Required properties:
> >
> > @@ -7,7 +7,7 @@ Required properties:
> >  "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
> >
> >  - reg:
> > -Define the base and range of the I/O address space that contains the
> Cygnus
> > +Define the base and range of the I/O address space that contains
> > + SoC
> >  GPIO/PINCONF controller registers
> >
> >  - ngpios:
> > --
> > 1.9.1
> >
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Re: [PATCH 1/4] ASoC: sun4i-codec: Add support for PA gpio pin

[Maxime Ripard]

On Sat, Nov 21, 2015 at 12:42:41AM +0800, Chen-Yu Tsai wrote:
> >>  static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
> >>  {
> >> - /*
> >> -  * FIXME: according to the BSP, we might need to drive a PA
> >> -  *GPIO low here on some boards
> >> -  */
> >> -
> >>   /* Disable DAC DRQ */
> >>   regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
> >>  BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
> >>  0);
> >> +
> >> + if (scodec->gpio_pa)
> >> + gpiod_set_value_cansleep(scodec->gpio_pa, 0);
> >
> > You should rather plug that into DAPM, using a speaker widget, and a
> > custom event function that will enable or disable the amplifier only
> > when this audio path is going to be used.
> 
> Isn't an "amplifier" widget better suited?

This is exactly what SND_SOC_DAPM_SPK is used for:
http://lxr.free-electrons.com/source/Documentation/sound/alsa/soc/dapm.txt#L273 
;)

Maxime

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Re: [PATCH] thermal: Add support for Sunxi THS on the Allwinner H3

[Maxime Ripard]

Hi!

Thanks for your patch.

On Wed, Nov 18, 2015 at 09:51:48PM +0100, Josef Gajdusek wrote:
> This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
> Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the
> dividers as they are not continuous (clk-divider.c cannot be used as it
> does not support setting an enable bit).
> Should be easily extendable for the A33/A83T/... as they have similar but
> not completely identical sensors.
> 
> Signed-off-by: Josef Gajdusek 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
>  .../devicetree/bindings/thermal/sunxi-ths.txt  |  24 ++
>  arch/arm/boot/dts/sun8i-h3.dtsi|  27 +++
>  drivers/clk/sunxi/clk-sunxi.c  |  16 ++
>  drivers/thermal/Kconfig|   7 +
>  drivers/thermal/Makefile   |   1 +
>  drivers/thermal/sunxi_ths.c| 263 
> +
>  7 files changed, 339 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sunxi-ths.txt
>  create mode 100644 drivers/thermal/sunxi_ths.c

Like other have pointed out, this should be split in several patches.

> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 6293c65..637401a 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -604,6 +604,13 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 
> parent_rate,
>   *p = calcp;
>  }
>  
> +static void sun8i_h3_get_ths_factors(u32 *freq, u32 parent_rate,
> +   u8 *n, u8 *k, u8 *m, u8 *p)
> +{
> + /* Ignore the dividers as they are not continuous */

You'd rather use a divider table.

> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index c463c89..0111d4d 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL
> Thermal reporting device will provide temperature reading,
> programmable trip points and other information.
>  
> +config SUNXI_THS
> + tristate "Sunxi THS driver"

Allwinner H3 Thermal Sensor

> + depends on ARCH_SUNXI

ARCH_SUN8I maybe ?

> + depends on OF
> + help
> +   Enable this to support thermal reporting on some newer Allwinner SoC.
> +
>  menu "Texas Instruments thermal drivers"
>  depends on ARCH_HAS_BANDGAP || COMPILE_TEST
>  source "drivers/thermal/ti-soc-thermal/Kconfig"
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index cfae6a6..3a25e3c 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
>  obj-$(CONFIG_ST_THERMAL) += st/
>  obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
>  obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
> +obj-$(CONFIG_SUNXI_THS)  += sunxi_ths.o

And call it sun8i_ths.

> diff --git a/drivers/thermal/sunxi_ths.c b/drivers/thermal/sunxi_ths.c
> new file mode 100644
> index 000..650cd39
> --- /dev/null
> +++ b/drivers/thermal/sunxi_ths.c
> @@ -0,0 +1,263 @@
> +/*
> + * Sunxi THS driver
> + *
> + * Copyright (C) 2015 Josef Gajdusek
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include 

You don't need this header, it's meant for clock providers, as its
name suggest. You're only using the consumer API.

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define THS_H3_CTRL0 0x00
> +#define THS_H3_CTRL1 0x04
> +#define THS_H3_CDAT  0x14
> +#define THS_H3_CTRL2 0x40
> +#define THS_H3_INT_CTRL  0x44
> +#define THS_H3_STAT  0x48
> +#define THS_H3_ALARM_CTRL0x50
> +#define THS_H3_SHUTDOWN_CTRL 0x60
> +#define THS_H3_FILTER0x70
> +#define THS_H3_CDATA 0x74
> +#define THS_H3_DATA  0x80
> +
> +#define THS_H3_CTRL0_SENSOR_ACQ0 0
> +
> +#define THS_H3_CTRL1_ADC_CALI_EN 17
> +#define THS_H3_CTRL1_OP_BIAS 20
> +
> +#define THS_H3_CTRL2_SENSE_EN0
> +#define THS_H3_CTRL2_SENSOR_ACQ1 16
> +
> +#define THS_H3_INT_CTRL_ALARM_INT_EN 0
> +#define THS_H3_INT_CTRL_SHUT_INT_EN  4
> +#define THS_H3_INT_CTRL_DATA_IRQ_EN  8
> +#define THS_H3_INT_CTRL_THERMAL_PER