Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On Wed, 25 Nov 2015 05:40:49 + Bharat Kumar Gogada wrote: > > On Thu, 19 Nov 2015 11:05:23 +0530 > > Bharat Kumar Gogada wrote: > > > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > > > Signed-off-by: Bharat Kumar Gogada > > > Signed-off-by: Ravi Kiran Gummaluri > > > Acked-by: Rob Herring > > > --- > > > + > > > +#define MSI_ADDRESS 0xDEED > > > > How did you pick this value? What if it intersect with some actual RAM? > > What if a device actually does DMA to that location? > > > > Wouldn't it make sense to actually pick a real *device* address (hint: > > your MSI controller itself) for this purpose, as the device will never DMA > > there? > > > > > We have already mentioned in previous patch discussion, we don't have > any device address on our SOC for MSI, that's the reason we are > allocating a page for MSI in RAM. Since our memory write is consumed > by bridge and doesn't write to memory, you suggested to use some > random address, so using some random address. This is becoming painful. - "write is consumed by bridge and doesn't write to memory": So why are you using something that has a chance of actually being memory??? Are you in the business of corrupting unsuspecting data? - "we don't have any device address on our SOC for MSI": You have plenty, and that's the whole of your device space. *All of it*. So just take the base address of your PCIe controller, and be done with it. Or your UART. Anything that cannot be DMA'ed to from a PCIe device, and that is downstream of your PCIe bridge. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: dts: ls1021a: Add a TFT LCD panel.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
arch/arm/boot/dts/ls1021a-twr.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts
b/arch/arm/boot/dts/ls1021a-twr.dts
index fbb89d1..fad2e3b 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -105,6 +105,17 @@
bitclock-master;
};
};
+
+ panel: panel {
+ compatible = "nec,nl4827hc19-05b";
+ };
+
+};
+
+&dcu {
+ fsl,panel = <&panel>;
+ status = "okay";
+
};
&dspi1 {
--
2.1.0.27.g96db324
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[PATCH 1/2] ARM: dts: ls1021a: Add DCU dts node.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
arch/arm/boot/dts/ls1021a.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9430a99..f01c98b 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -428,6 +428,16 @@
<&platform_clk 1>;
};
+ dcu: dcu@2ce {
+ compatible = "fsl,ls1021a-dcu";
+ reg = <0x0 0x2ce 0x0 0x1>;
+ interrupts = ;
+ clocks = <&platform_clk 0>;
+ clock-names = "dcu";
+ big-endian;
+ status = "disabled";
+ };
+
mdio0: mdio@2d24000 {
compatible = "gianfar";
device_type = "mdio";
--
2.1.0.27.g96db324
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[PATCH 18/18] ARM: am57xx: sbc-am57x: dts: add HDMI support
Add HDMI video output support.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 13555aa..4b29223 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -18,6 +18,7 @@
aliases {
display0 = &lcd0;
+ display1 = &hdmi;
};
};
@@ -61,6 +62,19 @@
DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14)
/* vin2a_vsync0.gpio4_0 */
>;
};
+
+ hdmi_pins: pinmux_hdmi_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)
/* i2c2_sda.hdmi1_ddc_scl */
+ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)
/* i2c2_scl.hdmi1_ddc_sda */
+ >;
+ };
+
+ hdmi_conn_pins: pinmux_hdmi_conn_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14)
/* spi1_cs2.gpio7_12 */
+ >;
+ };
};
&uart3 {
@@ -136,3 +150,30 @@
};
};
};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo4_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+};
+
+&hdmi_conn {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_conn_pins>;
+
+ hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+};
--
1.9.1
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[PATCH 01/18] ARM: am57xx: cl-som-am57x: dts: add basic module support
Add support for CompuLab CM-SOM-AM57X board.
CL-SOM-AM57x is a miniature System-on-Module (SoM) based on
TI Sitara AM57x ARM Cortex-A15 System-on-Chip family.
https://www.compulab.co.il/products/computer-on-modules/cl-som-am57x-ti-am5728-am5718-system-on-module/
Add basic DT support for standalone module (without a carrier board):
* Memory configuration
* Heartbeat led
* I2C1 bus
* PMIC
* SATA
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
.../devicetree/bindings/arm/omap/omap.txt | 3 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 259 +
3 files changed, 264 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/am57xx-cl-som-am57x.dts
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt
b/Documentation/devicetree/bindings/arm/omap/omap.txt
index da84372..dd53c90 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -156,6 +156,9 @@ Boards:
- AM437x SK EVM: AM437x StarterKit Evaluation Module
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
+- AM57XX CL-SOM-AM57x
+ compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5492a24..803a020 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -477,8 +477,9 @@ dtb-$(CONFIG_SOC_OMAP5) += \
omap5-sbc-t54.dtb \
omap5-uevm.dtb
dtb-$(CONFIG_SOC_DRA7XX) += \
- dra7-evm.dtb \
am57xx-beagle-x15.dtb \
+ am57xx-cl-som-am57x.dtb \
+ dra7-evm.dtb \
dra72-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-lacie-d2-network.dtb \
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
new file mode 100644
index 000..b11d7da
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -0,0 +1,259 @@
+/*
+ * Support for CompuLab CL-SOM-AM57x System-on-Module
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Dmitry Lifshitz
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include "dra74x.dtsi"
+
+/ {
+ model = "CompuLab CL-SOM-AM57x";
+ compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742",
"ti,dra74", "ti,dra7";
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x2000>; /* 512 MB - minimal
configuration */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>;
+
+ led@0 {
+ label = "cl-som-am57x:green";
+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+};
+
+&dra7_pmx_core {
+ leds_pins_default: leds_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14)
/* gpmc_a15.gpio2_5 */
+ >;
+ };
+
+ i2c1_pins_default: i2c1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0)
/* i2c1_sda.sda */
+ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0)
/* i2c1_scl.scl */
+ >;
+ };
+
+ tps659038_pins_default: tps659038_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP |
MUX_MODE14) /* wakeup0.gpio1_0 */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_default>;
+ clock-frequency = <40>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps659038_pins_default>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ regulators {
+ smps12_reg: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+
[PATCH 14/18] ARM: am57xx: sbc-am57x: dts: add EEPROM support
On-board EEPROM chip is used for storing a board production info.
Add carrier board EEPROM support (over I2C5 bus).
Signed-off-by: Dmitry Lifshitz
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index b92650b..7b65efb 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -44,6 +44,13 @@
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0)
/* usb1_drvvbus */
>;
};
+
+ i2c5_pins_default: i2c5_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10)
/* mcasp1_axr0.i2c5_sda */
+ DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10)
/* mcasp1_axr1.i2c5_scl */
+ >;
+ };
};
&uart3 {
@@ -71,3 +78,16 @@
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_default>;
+ clock-frequency = <40>;
+
+ eeprom_base: atmel@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
--
1.9.1
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[PATCH 13/18] ARM: am57xx: sbc-am57x: dts: add usb vbus pinmux
usb1_drvvbus pin is used to Drive-VBUS enable to external charge
pump/power switch.
Add a pinmux for that pin.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 67e7f4a..b92650b 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -38,6 +38,12 @@
DRA7XX_CORE_IOPAD(0x3770, PIN_INPUT | MUX_MODE14)
/* mmc1_sdwp.gpio6_28 */
>;
};
+
+ usb1_pins: pinmux_usb1_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0)
/* usb1_drvvbus */
+ >;
+ };
};
&uart3 {
@@ -60,3 +66,8 @@
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+};
--
1.9.1
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[PATCH 11/18] ARM: am57xx: sbc-am57x: dts: add basic board support
SBC-AM57x is a single board computer designed for industrial and
embedded applications. It is based on the Texas Instruments Sitara AM57x
system-on-chip family. SBC-AM57x is implemented with the CL-SOM-AM57x
computer-on-module providing most of the functions, and SB-SOM-AM57x
carrier board providing additional peripheral functions and connectors.
https://www.compulab.co.il/products/sbcs/sbc-am57x-ti-am5728-am5718-single-board-computer/
https://www.compulab.co.il/products/computer-on-modules/cl-som-am57x-ti-am5728-am5718-system-on-module/
Add basic board support, including UART3, used as a serial console.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
.../devicetree/bindings/arm/omap/omap.txt | 3 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 36 ++
3 files changed, 40 insertions(+)
create mode 100644 arch/arm/boot/dts/am57xx-sbc-am57x.dts
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt
b/Documentation/devicetree/bindings/arm/omap/omap.txt
index dd53c90..42cdad1 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -159,6 +159,9 @@ Boards:
- AM57XX CL-SOM-AM57x
compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7"
+- AM57XX SBC-AM57x
+ compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728",
"ti,dra742", "ti,dra74", "ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 803a020..4c73ab9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -479,6 +479,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \
dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-beagle-x15.dtb \
am57xx-cl-som-am57x.dtb \
+ am57xx-sbc-am57x.dtb \
dra7-evm.dtb \
dra72-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
new file mode 100644
index 000..804ad72
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -0,0 +1,36 @@
+/*
+ * Support for CompuLab SBC-AM57x single board computer
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Dmitry Lifshitz
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include "am57xx-cl-som-am57x.dts"
+#include "compulab-sb-som.dtsi"
+
+/ {
+ model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
+ compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x",
"ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+};
+
+&dra7_pmx_core {
+ uart3_pins_default: uart3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2)
/* uart2_ctsn.uart3_rxd */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1)
/* uart2_rtsn.uart3_txd */
+ >;
+ };
+};
+
+&uart3 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3f8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_default>;
+};
--
1.9.1
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[PATCH 10/18] ARM: am57xx: cl-som-am57x: dts: add analog audio support
Add analog audio DT nodes:
1. simple-audio-card node
2. wm8731 codec node
3. MCASP3 pinmux
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 67 +++
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 1830d4f..f7bec0d 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -50,6 +50,33 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
+
+ sound0: sound@0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink0_master>;
+ simple-audio-card,frame-master = <&dailink0_master>;
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Microphone", "Microphone Jack",
+ "Line", "Line Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
+ dailink0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&wm8731>;
+ system-clock-frequency = <1200>;
+ };
+ };
};
&dra7_pmx_core {
@@ -196,6 +223,24 @@
DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN |
MUX_MODE14) /* gpmc_a9.gpio1_31 */
>;
};
+
+ mcasp3_pins_default: mcasp3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
+ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
+ DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN |
MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
+ >;
+ };
+
+ mcasp3_pins_sleep: mcasp3_pins_sleep {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
+ >;
+ };
};
&i2c1 {
@@ -420,6 +465,13 @@
reg = <0x50>;
pagesize = <16>;
};
+
+ wm8731: wm8731@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ status = "okay";
+ };
};
&mmc2 {
@@ -537,3 +589,18 @@
&usb2 {
dr_mode = "peripheral";
};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp3_pins_default>;
+ pinctrl-1 = <&mcasp3_pins_sleep>;
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+};
--
1.9.1
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[PATCH 08/18] ARM: am57xx: cl-som-am57x: dts: add USB support
Add USB support.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index a838ea4..eba12a4 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -477,3 +477,19 @@
pinctrl-0 = <&davinci_mdio_pins_default>;
pinctrl-1 = <&davinci_mdio_pins_sleep>;
};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ dr_mode = "host";
+};
+
+&usb2 {
+ dr_mode = "peripheral";
+};
--
1.9.1
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[PATCH 07/18] ARM: am57xx: cl-som-am57x: dts: add dual EMAC support
Add dual EMAC support.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 105 ++
1 file changed, 105 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index cf2328d..a838ea4 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -104,6 +104,85 @@
DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_cs3.qspi1_cs1 */
>;
};
+
+ cpsw_pins_default: cpsw_pins_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_tclk */
+ DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_tctl */
+ DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_td3 */
+ DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_td2 */
+ DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_td1 */
+ DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)
/* rgmii1_td0 */
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)
/* rgmii1_rclk */
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)
/* rgmii1_rctl */
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)
/* rgmii1_rd3 */
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)
/* rgmii1_rd2 */
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)
/* rgmii1_rd1 */
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)
/* rgmii1_rd0 */
+
+ /* Slave 2 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_tclk */
+ DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_tctl */
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_td3 */
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_td2 */
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_td1 */
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)
/* rgmii2_td0 */
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)
/* rgmii2_rclk */
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)
/* rgmii2_rctl */
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)
/* rgmii2_rd3 */
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)
/* rgmii2_rd2 */
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)
/* rgmii2_rd1 */
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)
/* rgmii2_rd0 */
+ >;
+ };
+
+ cpsw_pins_sleep: cpsw_pins_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
+
+ /* Slave 2 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_M
[PATCH 05/18] ARM: am57xx: cl-som-am57x: dts: add eMMC support
CM-SOM-AM57X has two options of main storage devices - eMMC or NAND.
Add eMMC chip support (over MMC2 bus).
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 33 +++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index b6919a7..ed50a75 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -36,6 +36,13 @@
default-state = "off";
};
};
+
+ vdd_3v3: fixedregulator-vdd_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
};
&dra7_pmx_core {
@@ -71,6 +78,21 @@
DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP |
MUX_MODE14) /* wakeup0.gpio1_0 */
>;
};
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a22.mmc2_dat7 */
+ >;
+ };
};
&i2c1 {
@@ -297,4 +319,15 @@
};
};
+&mmc2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&vdd_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+ cap-mmc-dual-data-rate;
+};
--
1.9.1
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[PATCH 16/18] ARM: am57xx: sbc-am57x: dts: add LCD support
Startek-kd050c 800x480 LCD panel timings are described in
compulab-sb-som.dtsi.
Add appropriate DT endpoints to connect DPI output and LCD.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 8b7c0b5..13555aa 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -15,6 +15,10 @@
/ {
model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x",
"ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ aliases {
+ display0 = &lcd0;
+ };
};
&dra7_pmx_core {
@@ -51,6 +55,12 @@
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10)
/* mcasp1_axr1.i2c5_scl */
>;
};
+
+ lcd_pins_default: lcd_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14)
/* vin2a_vsync0.gpio4_0 */
+ >;
+ };
};
&uart3 {
@@ -98,3 +108,31 @@
#gpio-cells = <2>;
};
};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+
+ port {
+ dpi_lcd_out: endpoint@0 {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&lcd0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins_default>;
+
+ enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
+ &gpio4 0 GPIO_ACTIVE_HIGH>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_lcd_out>;
+ data-lines = <24>;
+ };
+ };
+};
--
1.9.1
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[PATCH 00/18] Add support for CL-SOM-AM57X and SBC-AM57X
This patch series adds support for CompuLab CL-SOM-AM57X and
SBC-AM57X boards.
CL-SOM-AM57x is a miniature System-on-Module (SoM) based on
TI Sitara AM57x ARM Cortex-A15 System-on-Chip family.
SBC-AM57x is a single board computer, implemented with the
CL-SOM-AM57x computer-on-module providing most of the functions,
and SB-SOM-AM57x carrier board providing additional peripheral
functions and connectors.
The SBC-AM57x has the following features:
CPU:Texas Instruments Sitara AM5728 dual-core ARM Cortex-A15,
1.5GHz or
Texas Instruments Sitara AM5718 single-core ARM Cortex-A15,
1.5GHz
RAM:DDR3, 512MB – 4GB
Storage:NAND flash, 512MB - 1GB or eMMC flash, 4GB - 32GB
SPI-flash 2MB
Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY)
WiFi/BT:802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or
Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837
chipset)
Analog Audio: Audio codec with stereo output, stereo input and microphone
support
More details can be found here:
https://www.compulab.co.il/products/computer-on-modules/cl-som-am57x-ti-am5728-am5718-system-on-module/
https://www.compulab.co.il/products/sbcs/sbc-am57x-ti-am5728-am5718-single-board-computer/
This series is based on the following patch set ("Add support for sbc-t43"
Nikita Kiryanov):
https://www.mail-archive.com/linux-omap@vger.kernel.org/msg121614.html
Dmitry Lifshitz (18):
ARM: am57xx: cl-som-am57x: dts: add basic module support
ARM: am57xx: cl-som-am57x: dts: add RTC support
ARM: am57xx: cl-som-am57x: dts: add I2C3 support
ARM: am57xx: cl-som-am57x: dts: add EEPROM support
ARM: am57xx: cl-som-am57x: dts: add eMMC support
ARM: am57xx: cl-som-am57x: dts: add spi-flash support
ARM: am57xx: cl-som-am57x: dts: add dual EMAC support
ARM: am57xx: cl-som-am57x: dts: add USB support
ARM: am57xx: cl-som-am57x: dts: add touchscreen support
ARM: am57xx: cl-som-am57x: dts: add analog audio support
ARM: am57xx: sbc-am57x: dts: add basic board support
ARM: am57xx: cl-som-am57x: dts: add MMC1 support
ARM: am57xx: sbc-am57x: dts: add usb vbus pinmux
ARM: am57xx: sbc-am57x: dts: add EEPROM support
ARM: am57xx: sbc-am57x: dts: add GPIO extender support
ARM: am57xx: sbc-am57x: dts: add LCD support
ARM: am57xx: compulab-sb-som: dts: add HDMI connector
ARM: am57xx: sbc-am57x: dts: add HDMI support
.../devicetree/bindings/arm/omap/omap.txt | 6 +
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 606 +
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 179 ++
arch/arm/boot/dts/compulab-sb-som.dtsi | 7 +
5 files changed, 801 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/am57xx-cl-som-am57x.dts
create mode 100644 arch/arm/boot/dts/am57xx-sbc-am57x.dts
--
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[PATCH 09/18] ARM: am57xx: cl-som-am57x: dts: add touchscreen support
Add ADS7846 touchscreen support.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 44 +++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index eba12a4..1830d4f 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -43,6 +43,13 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
+
+ ads7846reg: fixedregulator-ads7846-reg {
+ compatible = "regulator-fixed";
+ regulator-name = "ads7846-reg";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
};
&dra7_pmx_core {
@@ -183,6 +190,12 @@
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
>;
};
+
+ ads7846_pins: pinmux_ads7846_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN |
MUX_MODE14) /* gpmc_a9.gpio1_31 */
+ >;
+ };
};
&i2c1 {
@@ -450,6 +463,37 @@
reg = <0x10 0x0>;
};
};
+
+ /* touch controller */
+ ads7846@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ads7846_pins>;
+
+ compatible = "ti,ads7846";
+ vcc-supply = <&ads7846reg>;
+
+ reg = <1>; /* CS1 */
+ spi-max-frequency = <150>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <31 0>;
+ pendown-gpio = <&gpio1 31 0>;
+
+
+ ti,x-min = /bits/ 16 <0x0>;
+ ti,x-max = /bits/ 16 <0x0fff>;
+ ti,y-min = /bits/ 16 <0x0>;
+ ti,y-max = /bits/ 16 <0x0fff>;
+
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+
+ ti,debounce-max = /bits/ 16 <30>;
+ ti,debounce-tol = /bits/ 16 <10>;
+ ti,debounce-rep = /bits/ 16 <1>;
+
+ linux,wakeup;
+ };
};
&mac {
--
1.9.1
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[PATCH 04/18] ARM: am57xx: cl-som-am57x: dts: add EEPROM support
On-board EEPROM chip is used for storing a board production
info.
Add module EEPROM support (over I2C4 bus).
Signed-off-by: Dmitry Lifshitz
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index eb9b81b..b6919a7 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -289,6 +289,12 @@
compatible = "emmicro,em3027";
reg = <0x56>;
};
+
+ eeprom_module: atmel@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
--
1.9.1
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[PATCH 15/18] ARM: am57xx: sbc-am57x: dts: add GPIO extender support
Add PCA9555 GPIO extender support (over I2C5 bus).
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 7b65efb..8b7c0b5 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -90,4 +90,11 @@
reg = <0x50>;
pagesize = <16>;
};
+
+ pca9555: pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
--
1.9.1
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[PATCH 06/18] ARM: am57xx: cl-som-am57x: dts: add spi-flash support
On-board spi-flash chip is used as a main boot device.
Add spi-flash chip support (over QSPI bus).
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index ed50a75..cf2328d 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -93,6 +93,17 @@
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_a22.mmc2_dat7 */
>;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)
/* gpmc_a13.qspi1_rtclk */
+ DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)
/* gpmc_a16.qspi1_d0 */
+ DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)
/* gpmc_a17.qspi1_d1 */
+ DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)
/* qpmc_a18.qspi1_sclk */
+ DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_cs2.qspi1_cs0 */
+ DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)
/* gpmc_cs3.qspi1_cs1 */
+ >;
+ };
};
&i2c1 {
@@ -331,3 +342,33 @@
cap-mmc-dual-data-rate;
};
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_pins>;
+
+ spi_flash: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* CS0 */
+ spi-max-frequency = <2000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0xc>;
+ };
+
+ partition@c {
+ label = "uboot environment";
+ reg = <0xc 0x4>;
+ };
+
+ partition@10 {
+ label = "reserved";
+ reg = <0x10 0x0>;
+ };
+ };
+};
--
1.9.1
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[PATCH 17/18] ARM: am57xx: compulab-sb-som: dts: add HDMI connector
Add HDMI connector node without a valid input endpoint.
CompuLab SB-SOM is a carrier board, hence the endpoint
should be added in the board DT with a valid HDMI output.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/compulab-sb-som.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi
b/arch/arm/boot/dts/compulab-sb-som.dtsi
index 402a143..93d7e23 100644
--- a/arch/arm/boot/dts/compulab-sb-som.dtsi
+++ b/arch/arm/boot/dts/compulab-sb-som.dtsi
@@ -39,4 +39,11 @@
pixelclk-active = <1>;
};
};
+
+ hdmi_conn: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+ };
};
--
1.9.1
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[PATCH 02/18] ARM: am57xx: cl-som-am57x: dts: add RTC support
Add EM3027 RTC chip support (over I2C4 bus).
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index b11d7da..773e5389 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -52,6 +52,13 @@
>;
};
+ i2c4_pins_default: i2c4_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10)
/* mcasp1_acl.i2c4_sda */
+ DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10)
/* mcasp1_fsr.i2c4_scl */
+ >;
+ };
+
tps659038_pins_default: tps659038_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP |
MUX_MODE14) /* wakeup0.gpio1_0 */
@@ -257,3 +264,17 @@
status = "okay";
};
};
+
+&i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_default>;
+ clock-frequency = <10>;
+
+ rtc0: rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+};
+
+
--
1.9.1
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[PATCH 12/18] ARM: am57xx: cl-som-am57x: dts: add MMC1 support
Add MMC1 support, used for SD/MMC card.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-sbc-am57x.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 804ad72..67e7f4a 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -24,6 +24,20 @@
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1)
/* uart2_rtsn.uart3_txd */
>;
};
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)
/* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc1_dat3.dat3 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT | MUX_MODE14)
/* mmc1_sdcd.gpio6_27 */
+ DRA7XX_CORE_IOPAD(0x3770, PIN_INPUT | MUX_MODE14)
/* mmc1_sdwp.gpio6_28 */
+ >;
+ };
};
&uart3 {
@@ -34,3 +48,15 @@
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
+
+&mmc1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
+};
--
1.9.1
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[PATCH 03/18] ARM: am57xx: cl-som-am57x: dts: add I2C3 support
Enable I2C3 bus and add appropriate pinmux.
Signed-off-by: Dmitry Lifshitz
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 773e5389..eb9b81b 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -52,6 +52,13 @@
>;
};
+ i2c3_pins_default: i2c3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10)
/* mcasp1_aclkx.i2c3_sda */
+ DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10)
/* mcasp1_fsx.i2c3_scl */
+ >;
+ };
+
i2c4_pins_default: i2c4_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10)
/* mcasp1_acl.i2c4_sda */
@@ -265,6 +272,13 @@
};
};
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_default>;
+ clock-frequency = <40>;
+};
+
&i2c4 {
status = "okay";
pinctrl-names = "default";
--
1.9.1
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[PATCH v5 1/4] crypto: rockchip/crypto - add DT bindings documentation
Add DT bindings documentation for the rk3288 crypto drivers.
Signed-off-by: Zain Wang
Acked-by: Rob Herring
Tested-by: Heiko Stuebner
---
Changed in v5:
- None
Changed in v4:
- None
Changed in v3:
- add reset property
Changed in v2:
- None
Changed in v1:
- remove the _crypto suffix
- use "rockchip,rk3288-crypto" instead of "rockchip,rk3288"
- remove the description of status
.../devicetree/bindings/crypto/rockchip-crypto.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/rockchip-crypto.txt
diff --git a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt
b/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt
new file mode 100644
index 000..096df34
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt
@@ -0,0 +1,29 @@
+Rockchip Electronics And Security Accelerator
+
+Required properties:
+- compatible: Should be "rockchip,rk3288-crypto"
+- reg: Base physical address of the engine and length of memory mapped
+ region
+- interrupts: Interrupt number
+- clocks: Reference to the clocks about crypto
+- clock-names: "aclk" used to clock data
+ "hclk" used to clock data
+ "sclk" used to clock crypto accelerator
+ "apb_pclk" used to clock dma
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the name "crypto-rst".
+
+Examples:
+
+ crypto: cypto-controller@ff8a {
+ compatible = "rockchip,rk3288-crypto";
+ reg = <0xff8a 0x4000>;
+ interrupts = ;
+ clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
+<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ status = "okay";
+ };
--
1.9.1
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[PATCH v5 2/4] clk: rockchip: set an ID for crypto clk
Set an ID for crypto clk, so that it can be called in other part.
Signed-off-by: Zain Wang
Acked-by: Michael Turquette
Tested-by: Heiko Stuebner
---
Changed in v5:
- None
Changed in v4:
- None
Changed in v3:
- None
Changed in v2:
- None
Changed in v1:
- define SCLK_CRYPTO in rk3288-cru.h
- use SCLK_CRYPTO instead of SRST_CRYPTO
drivers/clk/rockchip/clk-rk3288.c | 2 +-
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 9040878..3fceda1 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -295,7 +295,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
__initdata = {
RK3288_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "c2c_host", "aclk_cpu_src", 0,
RK3288_CLKGATE_CON(13), 8, GFLAGS),
- COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
+ COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
RK3288_CLKGATE_CON(5), 4, GFLAGS),
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index c719aac..30dcd60 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -86,6 +86,7 @@
#define SCLK_USBPHY480M_SRC122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
+#define SCLK_CRYPTO125
#define SCLK_MAC 151
#define SCLK_MACREF_OUT152
--
1.9.1
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[PATCH v5 3/4] Crypto: rockchip/crypto - add crypto driver for rk3288
Crypto driver support:
ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede)
You can alloc tags above in your case.
And other algorithms and platforms will be added later on.
Signed-off-by: Zain Wang
Tested-by: Heiko Stuebner
---
Changed in v5:
- copy IV back after operation
- use cra_block_size to tell AES from DES instaed flag AES/TDES
Changed in v4:
- modify irq function
- add devm_add_action in probe
- fix some minor mistakes
Changed in v3:
- add OF depended in Kconfig
- rename some variate
- add reset property
- remove crypto_p variate
Changed in v2:
- remove some part about hash
- add weak key detection
- changed some variate's type
Changed in v1:
- modify some variate's name
- modify some variate's type
- modify some return value
- remove or modify some print info
- use more dev_xxx in probe
- modify the prio of cipher
- add Kconfig
drivers/crypto/Kconfig | 11 +
drivers/crypto/Makefile| 1 +
drivers/crypto/rockchip/Makefile | 3 +
drivers/crypto/rockchip/rk3288_crypto.c| 393
drivers/crypto/rockchip/rk3288_crypto.h| 216 +
drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c | 503 +
6 files changed, 1127 insertions(+)
create mode 100644 drivers/crypto/rockchip/Makefile
create mode 100644 drivers/crypto/rockchip/rk3288_crypto.c
create mode 100644 drivers/crypto/rockchip/rk3288_crypto.h
create mode 100644 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5357bc1..95dccde 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -497,4 +497,15 @@ config CRYPTO_DEV_SUN4I_SS
To compile this driver as a module, choose M here: the module
will be called sun4i-ss.
+config CRYPTO_DEV_ROCKCHIP
+ tristate "Rockchip's Cryptographic Engine driver"
+ depends on OF && ARCH_ROCKCHIP
+ select CRYPTO_AES
+ select CRYPTO_DES
+ select CRYPTO_BLKCIPHER
+
+ help
+ This driver interfaces with the hardware crypto accelerator.
+ Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index c3ced6f..713de9d 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
+obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
new file mode 100644
index 000..7051c6c
--- /dev/null
+++ b/drivers/crypto/rockchip/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
+rk_crypto-objs := rk3288_crypto.o \
+ rk3288_crypto_ablkcipher.o \
diff --git a/drivers/crypto/rockchip/rk3288_crypto.c
b/drivers/crypto/rockchip/rk3288_crypto.c
new file mode 100644
index 000..6b72f8d
--- /dev/null
+++ b/drivers/crypto/rockchip/rk3288_crypto.c
@@ -0,0 +1,393 @@
+/*
+ * Crypto acceleration support for Rockchip RK3288
+ *
+ * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Author: Zain Wang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Some ideas are from marvell-cesa.c and s5p-sss.c driver.
+ */
+
+#include "rk3288_crypto.h"
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
+{
+ int err;
+
+ err = clk_prepare_enable(dev->sclk);
+ if (err) {
+ dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
+ __func__, __LINE__);
+ goto err_return;
+ }
+ err = clk_prepare_enable(dev->aclk);
+ if (err) {
+ dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
+ __func__, __LINE__);
+ goto err_aclk;
+ }
+ err = clk_prepare_enable(dev->hclk);
+ if (err) {
+ dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
+ __func__, __LINE__);
+ goto err_hclk;
+ }
+ err = clk_prepare_enable(dev->dmaclk);
+ if (err) {
+ dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
+ __func__, __LINE__);
+ goto err_dmaclk;
+ }
+ return err;
+err_dmaclk:
+ clk_disable_unprepare(dev->hclk);
+err_hclk:
+ clk_disable_unprepare(dev->aclk);
+err_aclk:
+ clk_disable_unprepare(dev->sclk);
+err_return:
+ return err;
+}
+
+static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
+{
+ clk_d
[PATCH v5 0/4] crypto: add crypto accelerator support for rk3288
Changed in v5: - copy IV back after operation - use cra_block_size to tell AES from DES instaed flag AES/TDES Changed in v4: - modify irq function - add devm_add_action in probe - fix some minor mistakes Changed in v3: - add OF depended in Kconfig - rename some variate - add reset property - remove crypto_p variate Changed in v2: - remove some part about hash - add weak key detection - changed some variate's type Changed in v1: - modify some variate's name - modify some variate's type - modify some return value - remove or modify some print info - use more dev_xxx in probe - modify the prio of cipher - add Kconfig Zain Wang (4): crypto: rockchip/crypto - add DT bindings documentation clk: rockchip: set an ID for crypto clk Crypto: rockchip/crypto - add crypto driver for rk3288 ARM: dts: rockchip: Add Crypto node for rk3288 .../devicetree/bindings/crypto/rockchip-crypto.txt | 29 ++ arch/arm/boot/dts/rk3288.dtsi | 12 + drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/crypto/Kconfig | 11 + drivers/crypto/Makefile| 1 + drivers/crypto/rockchip/Makefile | 3 + drivers/crypto/rockchip/rk3288_crypto.c| 393 drivers/crypto/rockchip/rk3288_crypto.h| 216 + drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c | 503 + include/dt-bindings/clock/rk3288-cru.h | 1 + 10 files changed, 1170 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/crypto/rockchip-crypto.txt create mode 100644 drivers/crypto/rockchip/Makefile create mode 100644 drivers/crypto/rockchip/rk3288_crypto.c create mode 100644 drivers/crypto/rockchip/rk3288_crypto.h create mode 100644 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 4/4] ARM: dts: rockchip: Add Crypto node for rk3288
Add Crypto node for rk3288 including crypto controller and dma clk.
Signed-off-by: Zain Wang
Tested-by: Heiko Stuebner
---
Changed in v5:
- None
Changed in v4:
- None
Changed in v3:
- add reset property
Changed in v2:
- None
Changed in v1:
- remove the _crypto suffix
- use "rockchip,rk3288-crypto" instead of "rockchip,rk3288"
arch/arm/boot/dts/rk3288.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ad44d80..c6b1aa4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -781,6 +781,18 @@
status = "disabled";
};
+ crypto: cypto-controller@ff8a {
+ compatible = "rockchip,rk3288-crypto";
+ reg = <0xff8a 0x4000>;
+ interrupts = ;
+ clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
+<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ status = "okay";
+ };
+
vopb: vop@ff93 {
compatible = "rockchip,rk3288-vop";
reg = <0xff93 0x19c>;
--
1.9.1
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[PATCH] thermal: rcar: add .set_trip_temp support
From: Kuninori Morimoto
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
-45000 < $temp < 125000 is supported
Default is 9
Signed-off-by: Kuninori Morimoto
---
This patch is v2 of "[PATCH] thermal: rcar: enable to set tripN-temp via DT"
I think it will be full-DT feature if it uses of-thermal, but this driver is
used
from non-DT SoC too. We would like to keep non-DT support.
And we would like to do is only exchange trip temp.
.set_trip_temp is very enouth for it at this point.
But, it can use of-thermal feature in the future.
drivers/thermal/rcar_thermal.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 5d4ae7d..1eaa1be 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -63,6 +63,7 @@ struct rcar_thermal_priv {
struct mutex lock;
struct list_head list;
int id;
+ int trip_temp;
u32 ctemp;
};
@@ -222,7 +223,7 @@ static int rcar_thermal_get_trip_type(struct
thermal_zone_device *zone,
/* see rcar_thermal_get_temp() */
switch (trip) {
- case 0: /* +90 <= temp */
+ case 0:
*type = THERMAL_TRIP_CRITICAL;
break;
default:
@@ -241,8 +242,8 @@ static int rcar_thermal_get_trip_temp(struct
thermal_zone_device *zone,
/* see rcar_thermal_get_temp() */
switch (trip) {
- case 0: /* +90 <= temp */
- *temp = MCELSIUS(90);
+ case 0:
+ *temp = priv->trip_temp;
break;
default:
dev_err(dev, "rcar driver trip error\n");
@@ -270,10 +271,27 @@ static int rcar_thermal_notify(struct thermal_zone_device
*zone,
return 0;
}
+static int rcar_thermal_set_trip_temp(struct thermal_zone_device *zone,
+ int trip, int temp)
+{
+ struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone);
+
+ if (trip != 0)
+ return -EINVAL;
+
+ if (temp < -45000 || temp > 125000)
+ return -EINVAL;
+
+ priv->trip_temp = temp;
+
+ return 0;
+}
+
static struct thermal_zone_device_ops rcar_thermal_zone_ops = {
.get_temp = rcar_thermal_get_temp,
.get_trip_type = rcar_thermal_get_trip_type,
.get_trip_temp = rcar_thermal_get_trip_temp,
+ .set_trip_temp = rcar_thermal_set_trip_temp,
.notify = rcar_thermal_notify,
};
@@ -418,13 +436,14 @@ static int rcar_thermal_probe(struct platform_device
*pdev)
priv->common = common;
priv->id = i;
+ priv->trip_temp = MCELSIUS(90); /* default*/
mutex_init(&priv->lock);
INIT_LIST_HEAD(&priv->list);
INIT_DELAYED_WORK(&priv->work, rcar_thermal_work);
rcar_thermal_update_temp(priv);
priv->zone = thermal_zone_device_register("rcar_thermal",
- 1, 0, priv,
+ 1, 1, priv,
&rcar_thermal_zone_ops, NULL, 0,
idle);
if (IS_ERR(priv->zone)) {
--
1.9.1
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Re: [PATCH 4/4] ARM: dts: vf610-twr: relicense vf610-twr.dts under GPLv2/X11
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/23/2015 07:01 PM, Stefan Agner wrote: > GPLv2-only devicetrees make reuse difficult for software components > licensed under a different license. > > The consensus is that a GPL/X11 dual-license should allow all necessary > uses, so relicense the vf610-twr.dts file to this combination. > > CCs were acquired using (updated some email addresses): > git shortlog -sne --no-merges arch/arm/boot/dts/vf610-twr.dts > > CC: Bill Pringlemeir > CC: Chao Fu > CC: Cory Tusar Acked-by: Cory Tusar > CC: Cosmin Stoica > CC: Fugang Duan > CC: Jingchang Lu > CC: Shawn Guo > CC: Xiubo Li > Signed-off-by: Stefan Agner - -- Cory Tusar Principal PID 1 Solutions, Inc. "There are two ways of constructing a software design. One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies." --Sir Charles Anthony Richard Hoare -BEGIN PGP SIGNATURE- Version: GnuPG v2 iEYEARECAAYFAlZVSlkACgkQHT1tsfGwHJ8KNwCfZ447EX1WDTNHtozjnAMJH9SP y8wAoJDqarHEEUSSYvRQzEln0R6aaNMK =tTfg -END PGP SIGNATURE- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] ARM: dts: vf610-cosmic: relicense vf610-cosmic.dts under GPLv2/X11
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/23/2015 07:01 PM, Stefan Agner wrote: > GPLv2-only devicetrees make reuse difficult for software components > licensed under a different license. > > The consensus is that a GPL/X11 dual-license should allow all necessary > uses, so relicense the vf610-twr.dts file to this combination. > > CCs were acquired using (updated some email addresses): > git shortlog -sne --no-merges arch/arm/boot/dts/vf610-cosmic.dts > > CC: Cory Tusar Acked-by: Cory Tusar > CC: Matt Porter > CC: Olof Johansson > CC: Shawn Guo > Signed-off-by: Stefan Agner - -- Cory Tusar Principal PID 1 Solutions, Inc. "There are two ways of constructing a software design. One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies." --Sir Charles Anthony Richard Hoare -BEGIN PGP SIGNATURE- Version: GnuPG v2 iEYEARECAAYFAlZVSgIACgkQHT1tsfGwHJ8+WgCgpIksiDYnrAinLzsEv11cl5Ez Hb4An1Bm9qpykikhgs+BDjuNiDp7KDC/ =8817 -END PGP SIGNATURE- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
> On Thu, 19 Nov 2015 11:05:23 +0530
> Bharat Kumar Gogada wrote:
>
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada
> > Signed-off-by: Ravi Kiran Gummaluri
> > Acked-by: Rob Herring
> > ---
> > +
> > +#define MSI_ADDRESS0xDEED
>
> How did you pick this value? What if it intersect with some actual RAM?
> What if a device actually does DMA to that location?
>
> Wouldn't it make sense to actually pick a real *device* address (hint:
> your MSI controller itself) for this purpose, as the device will never DMA
> there?
>
>
We have already mentioned in previous patch discussion, we don't have any
device address on our SOC for MSI, that's
the reason we are allocating a page for MSI in RAM. Since our memory write is
consumed by bridge and doesn't write to memory, you suggested to use
some random address, so using some random address.
>
>
> > +
> > +static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int
> virq,
> > + unsigned int nr_irqs, void *args) {
> > + struct nwl_pcie *pcie = domain->host_data;
> > + struct nwl_msi *msi = &pcie->msi;
> > + int bit;
> > + int i;
> > + int ret;
> > +
> > + mutex_lock(&msi->lock);
> > + if (nr_irqs > 1) {
> > + ret = nwl_check_hwirq(msi, nr_irqs);
> > + if (ret < 0) {
> > + mutex_unlock(&msi->lock);
> > + return ret;
> > + }
> > + } else {
> > + ret = find_first_zero_bit(msi->used, INT_PCI_MSI_NR);
> > + if (ret == INT_PCI_MSI_NR) {
> > + mutex_unlock(&msi->lock);
> > + return -ENOSPC;
> > + }
> > + }
>
> Let's be serious for a minute. What's wrong with
> bitmap_find_next_zero_area, for example?
Ok, will explore this API and do accordingly, and address in next patch.
>
> > +
> > + for (i = 0; i < nr_irqs; i++) {
> > + bit = ret + i;
> > + set_bit(bit, msi->used);
> > +
> > + irq_domain_set_info(domain, virq + i, bit, &nwl_irq_chip,
> > + domain->host_data, handle_simple_irq,
> > + NULL, NULL);
> > + }
> > + mutex_unlock(&msi->lock);
> > +
> > + return 0;
> > +}
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny.
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Re: [PATCH 2/4] ARM: dts: vf610-colibri: relicense vf*colibri* under GPLv2/X11
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/23/2015 07:01 PM, Stefan Agner wrote: > GPLv2-only devicetrees make reuse difficult for software components > licensed under a different license. > > The consensus is that a GPL/X11 dual-license should allow all necessary > uses, so relicense the vf*colibri* files to this combination. > > CCs were acquired using: > git shortlog -sne --no-merges arch/arm/boot/dts/vf*colibri* > > CC: Bhuvanchandra DV > CC: Cory Tusar Acked-by: Cory Tusar > CC: Sanchayan Maity > Signed-off-by: Stefan Agner - -- Cory Tusar Principal PID 1 Solutions, Inc. "There are two ways of constructing a software design. One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies." --Sir Charles Anthony Richard Hoare -BEGIN PGP SIGNATURE- Version: GnuPG v2 iEYEARECAAYFAlZVSXIACgkQHT1tsfGwHJ/85gCgmqUH+q6crKOHEineLrFWPrA8 5kAAniD8W67H4c/oeDIdy2hPWXjtEO9z =EewI -END PGP SIGNATURE- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] ARM: dts: vf610: relicense vf???.dtsi under GPLv2/X11
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/23/2015 06:57 PM, Stefan Agner wrote: > GPLv2-only devicetrees make reuse difficult for software components > licensed under a different license. > > The consensus is that a GPL/X11 dual-license should allow all necessary > uses, so relicense the vfxxx.dtsi, vf500.dtsi and vf610.dtsi files to > this combination. > > CCs were acquired using (updated some email addresses): > git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi > > CC: Bhuvanchandra DV > CC: Chao Fu > CC: Cory Tusar Acked-by: Cory Tusar > CC: Cosmin Stoica > CC: Frank Li > CC: Fugang Duan > CC: Huang Shijie > CC: Jingchang Lu > CC: Lucas Stach > CC: Sanchayan Maity > CC: Shawn Guo > CC: Stephen Warren > CC: Xiubo Li > CC: Yuan Yao > Signed-off-by: Stefan Agner - -- Cory Tusar Principal PID 1 Solutions, Inc. "There are two ways of constructing a software design. One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies." --Sir Charles Anthony Richard Hoare -BEGIN PGP SIGNATURE- Version: GnuPG v2 iEYEARECAAYFAlZVSMMACgkQHT1tsfGwHJ/rYQCgnPy1XpNbNsUDGrutOANmQwoi Q0YAmwfO5LbZvZOLIqZyLLdc34sLBEHn =hsX0 -END PGP SIGNATURE- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/5] misc: eeprom_93xx46: Add quirks to support Atmel AT93C46D device.
Atmel devices in this family have some quirks not found in other similar
chips - they do not support a sequential read of the entire EEPROM
contents, and the control word sent at the start of each operation
varies in bit length.
This commit adds quirk support to the driver and modifies the read
implementation to support non-sequential reads for consistency with
other misc/eeprom drivers.
Tested on a custom Freescale VF610-based platform, with an AT93C46D
device attached via dspi2. The spi-gpio driver was used to allow the
necessary non-byte-sized transfers.
Signed-off-by: Cory Tusar
---
drivers/misc/eeprom/eeprom_93xx46.c | 126 ++--
include/linux/eeprom_93xx46.h | 6 ++
2 files changed, 97 insertions(+), 35 deletions(-)
diff --git a/drivers/misc/eeprom/eeprom_93xx46.c
b/drivers/misc/eeprom/eeprom_93xx46.c
index cc27e11..d50bc17 100644
--- a/drivers/misc/eeprom/eeprom_93xx46.c
+++ b/drivers/misc/eeprom/eeprom_93xx46.c
@@ -27,6 +27,15 @@
#define ADDR_ERAL 0x20
#define ADDR_EWEN 0x30
+struct eeprom_93xx46_devtype_data {
+ unsigned int quirks;
+};
+
+static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
+ .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
+ EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
+};
+
struct eeprom_93xx46_dev {
struct spi_device *spi;
struct eeprom_93xx46_platform_data *pdata;
@@ -35,6 +44,16 @@ struct eeprom_93xx46_dev {
int addrlen;
};
+static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
+{
+ return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
+}
+
+static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
+{
+ return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
+}
+
static ssize_t
eeprom_93xx46_bin_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
@@ -42,58 +61,73 @@ eeprom_93xx46_bin_read(struct file *filp, struct kobject
*kobj,
{
struct eeprom_93xx46_dev *edev;
struct device *dev;
- struct spi_message m;
- struct spi_transfer t[2];
- int bits, ret;
- u16 cmd_addr;
+ ssize_t ret = 0;
dev = container_of(kobj, struct device, kobj);
edev = dev_get_drvdata(dev);
- cmd_addr = OP_READ << edev->addrlen;
+ mutex_lock(&edev->lock);
- if (edev->addrlen == 7) {
- cmd_addr |= off & 0x7f;
- bits = 10;
- } else {
- cmd_addr |= (off >> 1) & 0x3f;
- bits = 9;
- }
+ if (edev->pdata->prepare)
+ edev->pdata->prepare(edev);
- dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
- cmd_addr, edev->spi->max_speed_hz);
+ while (count) {
+ struct spi_message m;
+ struct spi_transfer t[2] = { { 0 } };
+ u16 cmd_addr = OP_READ << edev->addrlen;
+ size_t nbytes = count;
+ int bits;
+ int err;
+
+ if (edev->addrlen == 7) {
+ cmd_addr |= off & 0x7f;
+ bits = 10;
+ if (has_quirk_single_word_read(edev))
+ nbytes = 1;
+ } else {
+ cmd_addr |= (off >> 1) & 0x3f;
+ bits = 9;
+ if (has_quirk_single_word_read(edev))
+ nbytes = 2;
+ }
- spi_message_init(&m);
- memset(t, 0, sizeof(t));
+ dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
+ cmd_addr, edev->spi->max_speed_hz);
- t[0].tx_buf = (char *)&cmd_addr;
- t[0].len = 2;
- t[0].bits_per_word = bits;
- spi_message_add_tail(&t[0], &m);
+ spi_message_init(&m);
- t[1].rx_buf = buf;
- t[1].len = count;
- t[1].bits_per_word = 8;
- spi_message_add_tail(&t[1], &m);
+ t[0].tx_buf = (char *)&cmd_addr;
+ t[0].len = 2;
+ t[0].bits_per_word = bits;
+ spi_message_add_tail(&t[0], &m);
- mutex_lock(&edev->lock);
+ t[1].rx_buf = buf;
+ t[1].len = count;
+ t[1].bits_per_word = 8;
+ spi_message_add_tail(&t[1], &m);
- if (edev->pdata->prepare)
- edev->pdata->prepare(edev);
+ err = spi_sync(edev->spi, &m);
+ /* have to wait at least Tcsl ns */
+ ndelay(250);
- ret = spi_sync(edev->spi, &m);
- /* have to wait at least Tcsl ns */
- ndelay(250);
- if (ret) {
- dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
- count, (int)off, ret);
+ if (err) {
+ dev_err(&edev->spi->dev, "read %zu bytes at %d: err.
%d\n",
+
[PATCH v3 3/5] misc: eeprom_93xx46: Implement eeprom_93xx46 DT bindings.
This commit implements bindings in the eeprom_93xx46 driver allowing
device word size and read-only attributes to be specified via
devicetree.
Signed-off-by: Cory Tusar
---
drivers/misc/eeprom/eeprom_93xx46.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/drivers/misc/eeprom/eeprom_93xx46.c
b/drivers/misc/eeprom/eeprom_93xx46.c
index e1bf0a5..cc27e11 100644
--- a/drivers/misc/eeprom/eeprom_93xx46.c
+++ b/drivers/misc/eeprom/eeprom_93xx46.c
@@ -13,6 +13,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -294,12 +296,58 @@ static ssize_t eeprom_93xx46_store_erase(struct device
*dev,
}
static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
+static const struct of_device_id eeprom_93xx46_of_table[] = {
+ { .compatible = "eeprom-93xx46", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
+
+static int eeprom_93xx46_probe_dt(struct spi_device *spi)
+{
+ struct device_node *np = spi->dev.of_node;
+ struct eeprom_93xx46_platform_data *pd;
+ u32 tmp;
+ int ret;
+
+ pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ ret = of_property_read_u32(np, "data-size", &tmp);
+ if (ret < 0) {
+ dev_err(&spi->dev, "data-size property not found\n");
+ return ret;
+ }
+
+ if (tmp == 8) {
+ pd->flags |= EE_ADDR8;
+ } else if (tmp == 16) {
+ pd->flags |= EE_ADDR16;
+ } else {
+ dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
+ return -EINVAL;
+ }
+
+ if (of_property_read_bool(np, "read-only"))
+ pd->flags |= EE_READONLY;
+
+ spi->dev.platform_data = pd;
+
+ return 0;
+}
+
static int eeprom_93xx46_probe(struct spi_device *spi)
{
struct eeprom_93xx46_platform_data *pd;
struct eeprom_93xx46_dev *edev;
int err;
+ if (spi->dev.of_node) {
+ err = eeprom_93xx46_probe_dt(spi);
+ if (err < 0)
+ return err;
+ }
+
pd = spi->dev.platform_data;
if (!pd) {
dev_err(&spi->dev, "missing platform data\n");
@@ -370,6 +418,7 @@ static int eeprom_93xx46_remove(struct spi_device *spi)
static struct spi_driver eeprom_93xx46_driver = {
.driver = {
.name = "93xx46",
+ .of_match_table = of_match_ptr(eeprom_93xx46_of_table),
},
.probe = eeprom_93xx46_probe,
.remove = eeprom_93xx46_remove,
--
2.4.10
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[PATCH v3 2/5] Documentation: devicetree: Add DT bindings to eeprom_93xx46 driver.
This commit documents bindings to be added to the eeprom_93xx46 driver
which will allow:
- Device word size and read-only attributes to be specified.
- A device-specific compatible string for use with Atmel AT93C46D
EEPROMs.
- Specifying a GPIO line to function as a 'select' or 'enable' signal
prior to accessing the EEPROM.
Signed-off-by: Cory Tusar
Acked-by: Rob Herring
---
.../devicetree/bindings/misc/eeprom-93xx46.txt | 25 ++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt
b/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt
new file mode 100644
index 000..a8ebb46
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt
@@ -0,0 +1,25 @@
+EEPROMs (SPI) compatible with Microchip Technology 93xx46 family.
+
+Required properties:
+- compatible : shall be one of:
+"atmel,at93c46d"
+"eeprom-93xx46"
+- data-size : number of data bits per word (either 8 or 16)
+
+Optional properties:
+- read-only : parameter-less property which disables writes to the EEPROM
+- select-gpios : if present, specifies the GPIO that will be asserted prior to
+ each access to the EEPROM (e.g. for SPI bus multiplexing)
+
+Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
+apply. In particular, "reg" and "spi-max-frequency" properties must be given.
+
+Example:
+ eeprom@0 {
+ compatible = "eeprom-93xx46";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ spi-cs-high;
+ data-size = <8>;
+ select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ };
--
2.4.10
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[PATCH v3 5/5] misc: eeprom_93xx46: Add support for a GPIO 'select' line.
This commit adds support to the eeprom_93x46 driver allowing a GPIO line
to function as a 'select' or 'enable' signal prior to accessing the
EEPROM.
Signed-off-by: Cory Tusar
---
drivers/misc/eeprom/eeprom_93xx46.c | 35 +++
include/linux/eeprom_93xx46.h | 3 +++
2 files changed, 38 insertions(+)
diff --git a/drivers/misc/eeprom/eeprom_93xx46.c
b/drivers/misc/eeprom/eeprom_93xx46.c
index d50bc17..d28fac2 100644
--- a/drivers/misc/eeprom/eeprom_93xx46.c
+++ b/drivers/misc/eeprom/eeprom_93xx46.c
@@ -10,11 +10,13 @@
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -343,6 +345,20 @@ static ssize_t eeprom_93xx46_store_erase(struct device
*dev,
}
static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
+static void select_assert(void *context)
+{
+ struct eeprom_93xx46_dev *edev = context;
+
+ gpiod_set_value_cansleep(edev->pdata->select, 1);
+}
+
+static void select_deassert(void *context)
+{
+ struct eeprom_93xx46_dev *edev = context;
+
+ gpiod_set_value_cansleep(edev->pdata->select, 0);
+}
+
static const struct of_device_id eeprom_93xx46_of_table[] = {
{ .compatible = "eeprom-93xx46", },
{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
@@ -357,6 +373,8 @@ static int eeprom_93xx46_probe_dt(struct spi_device *spi)
struct device_node *np = spi->dev.of_node;
struct eeprom_93xx46_platform_data *pd;
u32 tmp;
+ int gpio;
+ enum of_gpio_flags of_flags;
int ret;
pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
@@ -381,6 +399,23 @@ static int eeprom_93xx46_probe_dt(struct spi_device *spi)
if (of_property_read_bool(np, "read-only"))
pd->flags |= EE_READONLY;
+ gpio = of_get_named_gpio_flags(np, "select-gpios", 0, &of_flags);
+ if (gpio_is_valid(gpio)) {
+ unsigned long flags =
+ of_flags == OF_GPIO_ACTIVE_LOW ? GPIOF_ACTIVE_LOW : 0;
+
+ ret = devm_gpio_request_one(&spi->dev, gpio, flags,
+ "eeprom_93xx46_select");
+ if (ret)
+ return ret;
+
+ pd->select = gpio_to_desc(gpio);
+ pd->prepare = select_assert;
+ pd->finish = select_deassert;
+
+ gpiod_direction_output(pd->select, 0);
+ }
+
if (of_id->data) {
const struct eeprom_93xx46_devtype_data *data = of_id->data;
diff --git a/include/linux/eeprom_93xx46.h b/include/linux/eeprom_93xx46.h
index 92fa4c3..03f3435 100644
--- a/include/linux/eeprom_93xx46.h
+++ b/include/linux/eeprom_93xx46.h
@@ -3,6 +3,8 @@
* platform description for 93xx46 EEPROMs.
*/
+#include
+
struct eeprom_93xx46_platform_data {
unsigned char flags;
#define EE_ADDR8 0x01/* 8 bit addr. cfg */
@@ -21,4 +23,5 @@ struct eeprom_93xx46_platform_data {
*/
void (*prepare)(void *);
void (*finish)(void *);
+ struct gpio_desc *select;
};
--
2.4.10
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[PATCH v3 0/5] Devicetree support for misc/eeprom/eeprom_93xx46.
This series of patches adds an initial set of devicetree bindings to the eeprom_93xx46 driver which mirror the configuration options previously available as a platform device. These bindings are then extended to include support for specific Atmel devices in this family and also to support GPIO-based selection of the device (e.g. for use with an SPI bus mux). Additionally, an address aliasing issue with 16-bit read and write accesses in the eeprom_93xx46 driver discovered during testing is fixed. Changes since v2: - Changed node name to 'eeprom' in DT bindings example. - Simplified several bits of return logic. - Removed #ifdef CONFIG_OF. - Allow compiler to handle promotion to bool return values. - Reworked GPIO handling to use gpiod_* functions throughout (and fixed an oversight where GPIO flags were being ignored). Changes since v1: - Consolidated all Documentation/devictree additions into a single patch. - Clarified compatible string shall be only one of the supported values. - Renamed the 'select-gpio' binding to 'select-gpios'. Cory Tusar (5): misc: eeprom_93xx46: Fix 16-bit read and write accesses. Documentation: devicetree: Add DT bindings to eeprom_93xx46 driver. misc: eeprom_93xx46: Implement eeprom_93xx46 DT bindings. misc: eeprom_93xx46: Add quirks to support Atmel AT93C46D device. misc: eeprom_93xx46: Add support for a GPIO 'select' line. .../devicetree/bindings/misc/eeprom-93xx46.txt | 25 +++ drivers/misc/eeprom/eeprom_93xx46.c| 212 + include/linux/eeprom_93xx46.h | 9 + 3 files changed, 210 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/eeprom-93xx46.txt -- 2.4.10 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/5] misc: eeprom_93xx46: Fix 16-bit read and write accesses.
Compatible at93xx46 devices from both Microchip and Atmel expect a
word-based address, regardless of whether the device is strapped for 8-
or 16-bit operation. However, the offset parameter passed in when
reading or writing at a specific location is always specified in terms
of bytes.
This commit fixes 16-bit read and write accesses by shifting the offset
parameter to account for this difference between a byte offset and a
word-based address.
Signed-off-by: Cory Tusar
---
drivers/misc/eeprom/eeprom_93xx46.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/eeprom/eeprom_93xx46.c
b/drivers/misc/eeprom/eeprom_93xx46.c
index ff63f05..e1bf0a5 100644
--- a/drivers/misc/eeprom/eeprom_93xx46.c
+++ b/drivers/misc/eeprom/eeprom_93xx46.c
@@ -54,7 +54,7 @@ eeprom_93xx46_bin_read(struct file *filp, struct kobject
*kobj,
cmd_addr |= off & 0x7f;
bits = 10;
} else {
- cmd_addr |= off & 0x3f;
+ cmd_addr |= (off >> 1) & 0x3f;
bits = 9;
}
@@ -155,7 +155,7 @@ eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
bits = 10;
data_len = 1;
} else {
- cmd_addr |= off & 0x3f;
+ cmd_addr |= (off >> 1) & 0x3f;
bits = 9;
data_len = 2;
}
--
2.4.10
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Re: [PATCH] thermal: rcar: enable to set tripN-temp via DT
Hi Eduardo Thank you for your feedback > > From: Kuninori Morimoto > > > > Current rcar thermal driver is using 90 degrees as trip temp, but it > > should be based on each SoC / platform. > > This patch enables to set trip temp via DT. (It uses db8500-thermal > > style for it) > > It will use 90 degrees as default trip temp if DT doesn't have it. > > > > Signed-off-by: Kuninori Morimoto > > --- > > .../devicetree/bindings/thermal/rcar-thermal.txt | 2 ++ > > drivers/thermal/rcar_thermal.c | 34 > > -- > > 2 files changed, 33 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > > b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > > index 332e625..6c57f7e 100644 > > --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > > +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > > @@ -18,6 +18,8 @@ Required properties: > > Option properties: > > > > - interrupts : use interrupt > > +- tripN-temp : temperature of trip point N. it will use > > 9 as default > > + if DT doesn't have tripN-temp > > First of all, you are creating an entry with is specific to your driver. > That requires it to use proper prefixing. > > Besides, your property is already covered by of-thermal. Please convert > your driver to use of-thermal, this way it will give you the flexibility > to configure thermal data in DT. I see, but we need to keep compatibility for non-DT SoC. (This driver is used from both DT, non-DT SoC) Then, I noticed we can use .set_trip_temp, and it is very enough for us. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/5] misc: eeprom_93xx46: Add support for a GPIO 'select' line.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/19/2015 01:05 AM, Vladimir Zapolskiy wrote:
> On 19.11.2015 05:29, Cory Tusar wrote:
>> This commit adds support to the eeprom_93x46 driver allowing a GPIO line
>> to function as a 'select' or 'enable' signal prior to accessing the
>> EEPROM.
>>
>> Signed-off-by: Cory Tusar
>> ---
>> drivers/misc/eeprom/eeprom_93xx46.c | 26 ++
>> include/linux/eeprom_93xx46.h | 1 +
>> 2 files changed, 27 insertions(+)
>>
>> diff --git a/drivers/misc/eeprom/eeprom_93xx46.c
>> b/drivers/misc/eeprom/eeprom_93xx46.c
>> index 0386b03..375951f 100644
>> --- a/drivers/misc/eeprom/eeprom_93xx46.c
>> +++ b/drivers/misc/eeprom/eeprom_93xx46.c
>> @@ -10,11 +10,14 @@
>>
>> #include
>> #include
>> +#include
>> +#include
>> #include
>> #include
>> #include
>> #include
>> #include
>> +#include
>
> Please double check, adding only linux/of_gpio.h header should work,
> linux/gpio.h and linux/gpio/consumer.h are redundant.
There was an error which turned up on a 0-day build related to this:
tree: https://github.com/lunn/linux.git asl_v4.3-rc2-zii-stable-dsa-reset
head: c91bad95b39a98e0d06809c4c70c9c26747c874a
commit: a3e1b85039c722799102366b527b6bab9543e4ac [4/41] misc: eeprom:
93xx46: Add support for a GPIO 'select' line.
config: x86_64-randconfig-x007-11010710 (attached as .config)
reproduce:
git checkout a3e1b85039c722799102366b527b6bab9543e4ac
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/misc/eeprom/eeprom_93xx46.c: In function 'select_assert':
>> drivers/misc/eeprom/eeprom_93xx46.c:342:2: error: implicit declaration
of function 'gpiod_set_value_cansleep' [-Werror=implicit-function-declaration]
gpiod_set_value_cansleep(gpio_to_desc(edev->pdata->select_gpio), 1);
^
>> drivers/misc/eeprom/eeprom_93xx46.c:342:27: error: implicit declaration
of function 'gpio_to_desc' [-Werror=implicit-function-declaration]
gpiod_set_value_cansleep(gpio_to_desc(edev->pdata->select_gpio), 1);
I'll re-check with v3 (where everything uses the gpiod_*() interface) to
see if this can be eliminated...
>> #include
>> #include
>> #include
>> @@ -344,6 +347,20 @@ static ssize_t eeprom_93xx46_store_erase(struct device
>> *dev,
>> static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
>>
>> #ifdef CONFIG_OF
>> +static void select_assert(void *context)
>> +{
>> +struct eeprom_93xx46_dev *edev = context;
>> +
>> +gpiod_set_value_cansleep(gpio_to_desc(edev->pdata->select_gpio), 1);
>
> I would suggest to use gpio_set_value()
v3 uses gpiod_*() throughout. This also addresses an issue where flags
were not being tracked and used properly...
>> +}
>> +
>> +static void select_deassert(void *context)
>> +{
>> +struct eeprom_93xx46_dev *edev = context;
>> +
>> +gpiod_set_value_cansleep(gpio_to_desc(edev->pdata->select_gpio), 0);
>
> Same here.
As above.
>> +}
>> +
>> static const struct of_device_id eeprom_93xx46_of_table[] = {
>> { .compatible = "eeprom-93xx46", },
>> { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
>> @@ -385,6 +402,15 @@ static int eeprom_93xx46_probe_dt(struct spi_device
>> *spi)
>> if (of_property_read_bool(np, "read-only"))
>> pd->flags |= EE_READONLY;
>>
>> +ret = of_get_named_gpio(np, "select-gpios", 0);
>
> gpios or gpio? I see only one requested gpio.
gpios - for consistency.
>> +if (ret < 0) {
>> +pd->select_gpio = -1;
>> +} else {
>> +pd->select_gpio = ret;
>> +pd->prepare = select_assert;
>> +pd->finish = select_deassert;
>> +}
>> +
>> if (of_id->data) {
>> const struct eeprom_93xx46_devtype_data *data = of_id->data;
>>
>> diff --git a/include/linux/eeprom_93xx46.h b/include/linux/eeprom_93xx46.h
>> index 92fa4c3..aa472c7 100644
>> --- a/include/linux/eeprom_93xx46.h
>> +++ b/include/linux/eeprom_93xx46.h
>> @@ -21,4 +21,5 @@ struct eeprom_93xx46_platform_data {
>> */
>> void (*prepare)(void *);
>> void (*finish)(void *);
>> +unsigned int select_gpio;
>
> Same questions as in v2 4/5.
I simply see it as more straightforward to keep all platform-specific
data together, rather than mix-and-match between eeprom_93xx46_dev and
eeprom_93xx46_platform_data...
Also, the private eeprom_93xx46_dev structure has not been allocated
prior to parsing for DT bindings (without additional restructuring of
.probe() logic).
>> };
>>
>
> --
> With best wishes,
> Vladimir
>
- --
Cory Tusar
Principal
PID 1 Solutions, Inc.
"There are two ways of constructing a software design. One way is to
make it so simple that there are obviously no deficiencies, and the
other way is to make it so complicated that there are no obvious
deficiencies." --Sir Charles Anthony Richard Hoa
Re: [PATCH v3 1/4] iio: adc: add IMX7D ADC driver support
Hi Haibo, Some comments below: On 2015-11-20 07:48, Haibo Chen wrote: > Freescale i.MX7D soc contains a new ADC IP. This patch add this ADC > driver support, and the driver only support ADC software trigger. > > Signed-off-by: Haibo Chen > --- > drivers/iio/adc/Kconfig | 9 + > drivers/iio/adc/Makefile| 1 + > drivers/iio/adc/imx7d_adc.c | 570 > > 3 files changed, 580 insertions(+) > create mode 100644 drivers/iio/adc/imx7d_adc.c > > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > index 7868c74..bf0611c 100644 > --- a/drivers/iio/adc/Kconfig > +++ b/drivers/iio/adc/Kconfig > @@ -194,6 +194,15 @@ config HI8435 > This driver can also be built as a module. If so, the module will be > called hi8435. > > +config IMX7D_ADC > + tristate "IMX7D ADC driver" > + depends on OF Hm, not sure, but shouldn't we use a proper depends here? Otherwise this will show up as modules in all kinds of distributions. > + help > + Say yes here to build support for IMX7D ADC. > + > + This driver can also be built as a module. If so, the module will be > + called imx7d_adc. > + > config LP8788_ADC > tristate "LP8788 ADC driver" > depends on MFD_LP8788 > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile > index 99b37a9..282ffc01 100644 > --- a/drivers/iio/adc/Makefile > +++ b/drivers/iio/adc/Makefile > @@ -20,6 +20,7 @@ obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o > obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o > obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o > obj-$(CONFIG_HI8435) += hi8435.o > +obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o > obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o > obj-$(CONFIG_MAX1027) += max1027.o > obj-$(CONFIG_MAX1363) += max1363.o > diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c > new file mode 100644 > index 000..d9547bf > --- /dev/null > +++ b/drivers/iio/adc/imx7d_adc.c > @@ -0,0 +1,570 @@ > +/* > + * Freescale i.MX7D ADC driver > + * > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Can you sort these alphabetically > + > +#include > +#include > +#include > + > +/* ADC register */ > +#define IMX7D_REG_ADC_CH_A_CFG1 0x00 > +#define IMX7D_REG_ADC_CH_A_CFG2 0x10 > +#define IMX7D_REG_ADC_CH_B_CFG1 0x20 > +#define IMX7D_REG_ADC_CH_B_CFG2 0x30 > +#define IMX7D_REG_ADC_CH_C_CFG1 0x40 > +#define IMX7D_REG_ADC_CH_C_CFG2 0x50 > +#define IMX7D_REG_ADC_CH_D_CFG1 0x60 > +#define IMX7D_REG_ADC_CH_D_CFG2 0x70 > +#define IMX7D_REG_ADC_CH_SW_CFG 0x80 > +#define IMX7D_REG_ADC_TIMER_UNIT 0x90 > +#define IMX7D_REG_ADC_DMA_FIFO 0xa0 > +#define IMX7D_REG_ADC_FIFO_STATUS0xb0 > +#define IMX7D_REG_ADC_INT_SIG_EN 0xc0 > +#define IMX7D_REG_ADC_INT_EN 0xd0 > +#define IMX7D_REG_ADC_INT_STATUS 0xe0 > +#define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0 > +#define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100 > +#define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110 > +#define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120 > +#define IMX7D_REG_ADC_ADC_CFG0x130 > + > +#define IMX7D_EACH_CHANNEL_REG_SHIF 0x20 I would call that OFFSET, SHIFT is typically used for a bit offset within a register. > + > +#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31) > +#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_DISABLE(0x0 << > 31) I would just define the _EN definition (along with using BIT). Bitshifting a 0 is not really useful. > +#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30) > +#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29) > +#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL_SHIF 24 > + > +#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << > 12) > +#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << > 12) > +#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12) > +#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12) > + > +#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29) > +#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29) > +#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29) > +#define IMX7D_REG_ADC_TIMER_UNIT
Re: [PATCH] thermal: rcar: enable to set tripN-temp via DT
Morimoto-san, On Wed, Nov 25, 2015 at 01:45:14AM +, Kuninori Morimoto wrote: > > From: Kuninori Morimoto > > Current rcar thermal driver is using 90 degrees as trip temp, but it > should be based on each SoC / platform. > This patch enables to set trip temp via DT. (It uses db8500-thermal > style for it) > It will use 90 degrees as default trip temp if DT doesn't have it. > > Signed-off-by: Kuninori Morimoto > --- > .../devicetree/bindings/thermal/rcar-thermal.txt | 2 ++ > drivers/thermal/rcar_thermal.c | 34 > -- > 2 files changed, 33 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > index 332e625..6c57f7e 100644 > --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt > @@ -18,6 +18,8 @@ Required properties: > Option properties: > > - interrupts : use interrupt > +- tripN-temp : temperature of trip point N. it will use 9 as > default > + if DT doesn't have tripN-temp First of all, you are creating an entry with is specific to your driver. That requires it to use proper prefixing. Besides, your property is already covered by of-thermal. Please convert your driver to use of-thermal, this way it will give you the flexibility to configure thermal data in DT. BR, -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] watchdog: add Alphascale asm9260-wdt driver
On 11/24/2015 01:40 PM, Oleksij Rempel wrote:
Add WD support for Alphascale asm9260 SoC. This driver
provide support for different function modes:
- HW mode to trigger SoC reset on timeout
- SW mode do soft reset if needed
- DEBUG mode
Optional support for stopping watchdog. If reset binding are not provided
this driver will work in nowayout mode.
I think this is no longer optional ?
Signed-off-by: Oleksij Rempel
---
drivers/watchdog/Kconfig | 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/asm9260_wdt.c | 400 +
3 files changed, 411 insertions(+)
create mode 100644 drivers/watchdog/asm9260_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c68edc1..9cd9b75 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -173,6 +173,16 @@ config ARM_SP805_WATCHDOG
ARM Primecell SP805 Watchdog timer. This will reboot your system when
the timeout is reached.
+config ASM9260_WATCHDOG
+ tristate "Alphascale ASM9260 watchdog"
+ depends on MACH_ASM9260
+ depends on OF
+ select WATCHDOG_CORE
+ select RESET_CONTROLLER
+ help
+ Watchdog timer embedded into Alphascale asm9260 chips. This will
reboot your
+ system when the timeout is reached.
+
config AT91RM9200_WATCHDOG
tristate "AT91RM9200 watchdog"
depends on SOC_AT91RM9200 && MFD_SYSCON
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0c616e3..bd7b0cd 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
# ARM Architecture
obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
+obj-$(CONFIG_ASM9260_WATCHDOG) += asm9260_wdt.o
obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
obj-$(CONFIG_CADENCE_WATCHDOG) += cadence_wdt.o
diff --git a/drivers/watchdog/asm9260_wdt.c b/drivers/watchdog/asm9260_wdt.c
new file mode 100644
index 000..c8daeff
--- /dev/null
+++ b/drivers/watchdog/asm9260_wdt.c
@@ -0,0 +1,400 @@
+/*
+ * Watchdog driver for Alphascale ASM9260.
+ *
+ * Copyright (c) 2014 Oleksij Rempel
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CLOCK_FREQ 100
+
+/* Watchdog Mode register */
+#define HW_WDMOD 0x00
+/* Wake interrupt. Set by HW, can't be cleared. */
+#define BM_MOD_WDINT BIT(3)
+/* This bit set if timeout reached. Cleared by SW. */
+#define BM_MOD_WDTOF BIT(2)
+/* HW Reset on timeout */
+#define BM_MOD_WDRESET BIT(1)
+/* WD enable */
+#define BM_MOD_WDENBIT(0)
+
+/*
+ * Watchdog Timer Constant register
+ * Minimal value is 0xff, the meaning of this value
+ * depends on used clock: T = WDCLK * (0xff + 1) * 4
+ */
+#define HW_WDTC0x04
+#define BM_WDTC_MAX(freq) (0x7fff / (freq))
+
+/* Watchdog Feed register */
+#define HW_WDFEED 0x08
+
+/* Watchdog Timer Value register */
+#define HW_WDTV0x0c
+
+#define ASM9260_WDT_DEFAULT_TIMEOUT30
+
+enum asm9260_wdt_mode {
+ HW_RESET,
+ SW_RESET,
+ DEBUG,
+};
+
+struct asm9260_wdt_priv {
+ struct device *dev;
+ struct watchdog_device wdd;
+ struct clk *clk;
+ struct clk *clk_ahb;
+ struct reset_control*rst;
+ struct notifier_block restart_handler;
+
+ void __iomem*iobase;
+ int irq;
+ unsigned long wdt_freq;
+ enum asm9260_wdt_mode mode;
+};
+
+static int asm9260_wdt_feed(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+
+ iowrite32(0xaa, priv->iobase + HW_WDFEED);
+ iowrite32(0x55, priv->iobase + HW_WDFEED);
+
+ return 0;
+}
+
+static unsigned int asm9260_wdt_gettimeleft(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 counter;
+
+ counter = ioread32(priv->iobase + HW_WDTV);
+
+ return DIV_ROUND_CLOSEST(counter, priv->wdt_freq);
+}
+
+static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 counter;
+
+ counter = wdd->timeout * priv->wdt_freq;
+
+ iowrite32(counter, priv->iobase + HW_WDTC);
+
+ return 0;
+}
+
+static int asm9260_wdt_enable(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 mode = 0;
+
+ if (priv->mode == HW_RESET)
+ mode = BM_MOD_WDRESET;
+
+ iowrite32(BM_MOD_WDEN | mode, priv->iobase + HW_WDMOD);
+
+ asm9260
Re: [PATCH (v2) 1/10] clocksource: Add brcm,bcm6345-timer device tree binding
On Mon, Nov 23, 2015 at 06:55:38PM +, Simon Arlott wrote:
> Add device tree bindings for the BCM6345/BCM6318 timers. This is required
> for the BCM6345 watchdog which needs to respond to one of the timer
> interrupts.
>
> Signed-off-by: Simon Arlott
Acked-by: Rob Herring
> ---
> On 23/11/15 15:33, Jonas Gorski wrote:
> > On Sat, Nov 21, 2015 at 8:02 PM, Simon Arlott wrote:
> >> +- compatible: should be "brcm,bcm-timer", "brcm,bcm6345-timer"
> >
> > Since bcm6318 uses a slightly different register layout than the
> > earlier SoCs, I'd argue that using bcm6345-timer as a compatible for
> > bcm6318 is wrong.
>
> I've split them out into two very similar bindings.
>
> Patches 1/4 and 2/4 are replaced with (v2) 1/10 and (v2) 2/10.
>
> .../bindings/timer/brcm,bcm6318-timer.txt | 44
> .../bindings/timer/brcm,bcm6345-timer.txt | 47
> ++
> 2 files changed, 91 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/timer/brcm,bcm6318-timer.txt
> create mode 100644
> Documentation/devicetree/bindings/timer/brcm,bcm6345-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm6318-timer.txt
> b/Documentation/devicetree/bindings/timer/brcm,bcm6318-timer.txt
> new file mode 100644
> index 000..cf4be7e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/brcm,bcm6318-timer.txt
> @@ -0,0 +1,44 @@
> +Broadcom BCM6318 Timer
> +
> +This block is a timer that is connected to multiple interrupts on the main
> +interrupt controller and functions as a programmable interrupt controller for
> +timer events. There is a main timer interrupt for all timers.
> +
> +- 4 independent timers with their own interrupt, and own maskable level
> + interrupt bit in the main timer interrupt
> +
> +- 1 watchdog timer with an unmaskable level interrupt bit in the main timer
> + interrupt
> +
> +- Contains one enable/status word pair
> +
> +- No atomic set/clear operations
> +
> +Required properties:
> +
> +- compatible: should be "brcm,bcm-timer", "brcm,bcm6318-timer"
> +- reg: specifies the base physical address and size of the registers,
> excluding
> + the watchdog registers
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: specifies the number of cells needed to encode an
> interrupt
> + source, should be 1.
> +- interrupt-parent: specifies the phandle to the parent interrupt
> controller(s)
> + this one is cascaded from
> +- interrupts: specifies the interrupt line(s) in the interrupt-parent
> controller
> + node for the main timer interrupt, followed by the individual timer
> + interrupts; valid values depend on the type of parent interrupt controller
> +- clocks: phandle of timer reference clock (periph)
> +
> +Example:
> +
> +timer: timer@1040 {
> + compatible = "brcm,bcm63148-timer", "brcm,bcm6318-timer";
> + reg = <0x1040 0x28>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&periph_intc>;
> + interrupts = <31>, <0>, <1>, <2>, <3>;
> + clock = <&periph_osc>;
> +};
> diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm6345-timer.txt
> b/Documentation/devicetree/bindings/timer/brcm,bcm6345-timer.txt
> new file mode 100644
> index 000..03250dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/brcm,bcm6345-timer.txt
> @@ -0,0 +1,47 @@
> +Broadcom BCM6345 Timer
> +
> +This block is a timer that is connected to one interrupt on the main
> interrupt
> +controller and functions as a programmable interrupt controller for timer
> +events.
> +
> +- 3 independent timers with their own maskable level interrupt bit (but not
> + per CPU because there is only one parent interrupt and the timers share it)
> +
> +- 1 watchdog timer with an unmaskable level interrupt
> +
> +- Contains one enable/status word pair
> +
> +- No atomic set/clear operations
> +
> +The lack of per CPU ability of timers makes them unusable as a set of
> +clockevent devices, otherwise they could be attached to the remaining
> +interrupts.
> +
> +Required properties:
> +
> +- compatible: should be "brcm,bcm-timer", "brcm,bcm6345-timer"
> +- reg: specifies the base physical address and size of the registers,
> excluding
> + the watchdog registers
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: specifies the number of cells needed to encode an
> interrupt
> + source, should be 1.
> +- interrupt-parent: specifies the phandle to the parent interrupt
> controller(s)
> + this one is cascaded from
> +- interrupts: specifies the interrupt line(s) in the interrupt-parent
> controller
> + node for the timer interrupt; valid values depend on the type of parent
> + interrupt controller
> +- clocks: phandle of timer reference clock (periph)
> +
> +Example:
> +
> +timer: timer@1080 {
> + compatible = "brcm,bcm63168-timer", "brcm,bcm6345-timer
Re: [PATCH (v2) 7/10] watchdog: bcm63xx_wdt: Add get_timeleft function
On 11/24/2015 02:15 PM, Simon Arlott wrote:
Return the remaining time from the hardware control register.
Warn when the device is registered if the hardware watchdog is currently
running and report the remaining time left.
This is really two logical changes, isn't it ?
Nice trick to figure out if the watchdog is running.
What is the impact ? Will this result in interrupts ?
If so, would it make sense to _not_ reset the system after a timeout
in this case, but to keep pinging the watchdog while the watchdog device
is not open ?
Thanks,
Guenter
Signed-off-by: Simon Arlott
---
Changed "if (timeleft > 0)" to "if (hw->running)" when checking if a
warning should be printed, in case the time left is truncated down to
0 seconds.
drivers/watchdog/bcm63xx_wdt.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 3c7667a..9d099e0 100644
--- a/drivers/watchdog/bcm63xx_wdt.c
+++ b/drivers/watchdog/bcm63xx_wdt.c
@@ -14,6 +14,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include
+#include
#include
#include
#include
@@ -75,6 +76,19 @@ static int bcm63xx_wdt_stop(struct watchdog_device *wdd)
return 0;
}
+static unsigned int bcm63xx_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
+ unsigned long flags;
+ u32 val;
+
+ raw_spin_lock_irqsave(&hw->lock, flags);
+ val = __raw_readl(hw->regs + WDT_CTL_REG);
+ val /= hw->clock_hz;
+ raw_spin_unlock_irqrestore(&hw->lock, flags);
+ return val;
+}
+
static int bcm63xx_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
@@ -130,6 +144,7 @@ static struct watchdog_ops bcm63xx_wdt_ops = {
.owner = THIS_MODULE,
.start = bcm63xx_wdt_start,
.stop = bcm63xx_wdt_stop,
+ .get_timeleft = bcm63xx_wdt_get_timeleft,
.set_timeout = bcm63xx_wdt_set_timeout,
};
@@ -144,6 +159,8 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
struct bcm63xx_wdt_hw *hw;
struct watchdog_device *wdd;
struct resource *r;
+ u32 timeleft1, timeleft2;
+ unsigned int timeleft;
int ret;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
@@ -197,6 +214,23 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
watchdog_init_timeout(wdd, 0, &pdev->dev);
watchdog_set_nowayout(wdd, nowayout);
+ /* Compare two reads of the time left value, 2 clock ticks apart */
+ rmb();
+ timeleft1 = __raw_readl(hw->regs + WDT_CTL_REG);
+ udelay(DIV_ROUND_UP(100, hw->clock_hz / 2));
+ /* Ensure the register is read twice */
+ rmb();
+ timeleft2 = __raw_readl(hw->regs + WDT_CTL_REG);
+
+ /* If the time left is changing, the watchdog is running */
+ if (timeleft1 != timeleft2) {
+ hw->running = true;
+ timeleft = bcm63xx_wdt_get_timeleft(wdd);
+ } else {
+ hw->running = false;
+ timeleft = 0;
+ }
+
ret = bcm63xx_timer_register(TIMER_WDT_ID, bcm63xx_wdt_isr, wdd);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register wdt timer isr\n");
@@ -214,6 +248,8 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
dev_name(wdd->dev), hw->regs,
wdd->timeout, wdd->max_timeout);
+ if (hw->running)
+ dev_alert(wdd->dev, "running, reboot in %us\n", timeleft);
return 0;
unregister_timer:
@@ -255,6 +291,7 @@ module_platform_driver(bcm63xx_wdt_driver);
MODULE_AUTHOR("Miguel Gaio ");
MODULE_AUTHOR("Florian Fainelli ");
+MODULE_AUTHOR("Simon Arlott");
MODULE_DESCRIPTION("Driver for the Broadcom BCM63xx SoC watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bcm63xx-wdt");
--
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Re: [PATCH 5/10] watchdog: bcm63xx_wdt: Use WATCHDOG_CORE
Hi Simon,
On 11/22/2015 06:06 AM, Simon Arlott wrote:
Convert bcm63xx_wdt to use WATCHDOG_CORE.
The default and maximum time constants that are only used once have been
moved to the initialisation of the struct watchdog_device.
Comments inline.
Thanks,
Guenter
Signed-off-by: Simon Arlott
---
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/bcm63xx_wdt.c | 249 -
2 files changed, 74 insertions(+), 176 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7a8a6c6..6815b74 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1273,6 +1273,7 @@ config OCTEON_WDT
config BCM63XX_WDT
tristate "Broadcom BCM63xx hardware watchdog"
depends on BCM63XX
+ select WATCHDOG_CORE
help
Watchdog driver for the built in watchdog hardware in Broadcom
BCM63xx SoC.
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index f88fc97..1d2a501 100644
--- a/drivers/watchdog/bcm63xx_wdt.c
+++ b/drivers/watchdog/bcm63xx_wdt.c
@@ -13,20 +13,15 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include
#include
-#include
#include
#include
-#include
#include
#include
#include
#include
-#include
#include
#include
-#include
#include
#include
@@ -38,53 +33,57 @@
#define PFX KBUILD_MODNAME
#define WDT_HZ5000/* Fclk */
-#define WDT_DEFAULT_TIME 30 /* seconds */
-#define WDT_MAX_TIME (0x / WDT_HZ) /* seconds */
struct bcm63xx_wdt_hw {
raw_spinlock_t lock;
void __iomem *regs;
- unsigned long inuse;
bool running;
The "running" flag should no longer be needed. watchdog_active()
should provide that information.
};
-static struct bcm63xx_wdt_hw bcm63xx_wdt_device;
-static int expect_close;
-
-static int wdt_time = WDT_DEFAULT_TIME;
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-/* HW functions */
-static void bcm63xx_wdt_hw_start(void)
+static int bcm63xx_wdt_start(struct watchdog_device *wdd)
{
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
unsigned long flags;
- raw_spin_lock_irqsave(&bcm63xx_wdt_device.lock, flags);
- bcm_writel(wdt_time * WDT_HZ, bcm63xx_wdt_device.regs + WDT_DEFVAL_REG);
- bcm_writel(WDT_START_1, bcm63xx_wdt_device.regs + WDT_CTL_REG);
- bcm_writel(WDT_START_2, bcm63xx_wdt_device.regs + WDT_CTL_REG);
- bcm63xx_wdt_device.running = true;
- raw_spin_unlock_irqrestore(&bcm63xx_wdt_device.lock, flags);
+ raw_spin_lock_irqsave(&hw->lock, flags);
+ bcm_writel(wdd->timeout * WDT_HZ, hw->regs + WDT_DEFVAL_REG);
+ bcm_writel(WDT_START_1, hw->regs + WDT_CTL_REG);
+ bcm_writel(WDT_START_2, hw->regs + WDT_CTL_REG);
+ hw->running = true;
+ raw_spin_unlock_irqrestore(&hw->lock, flags);
+ return 0;
}
-static void bcm63xx_wdt_hw_stop(void)
+static int bcm63xx_wdt_stop(struct watchdog_device *wdd)
{
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
unsigned long flags;
- raw_spin_lock_irqsave(&bcm63xx_wdt_device.lock, flags);
- bcm_writel(WDT_STOP_1, bcm63xx_wdt_device.regs + WDT_CTL_REG);
- bcm_writel(WDT_STOP_2, bcm63xx_wdt_device.regs + WDT_CTL_REG);
- bcm63xx_wdt_device.running = false;
- raw_spin_unlock_irqrestore(&bcm63xx_wdt_device.lock, flags);
+ raw_spin_lock_irqsave(&hw->lock, flags);
+ bcm_writel(WDT_STOP_1, hw->regs + WDT_CTL_REG);
+ bcm_writel(WDT_STOP_2, hw->regs + WDT_CTL_REG);
+ hw->running = false;
+ raw_spin_unlock_irqrestore(&hw->lock, flags);
+ return 0;
+}
+
+static int bcm63xx_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ wdd->timeout = timeout;
+ return bcm63xx_wdt_start(wdd);
If I see correctly, there is no ping function. In that case, the watchdog core
will call the start function after updating the timeout, so there is no need
to do it here.
}
/* The watchdog interrupt occurs when half the timeout is remaining */
static void bcm63xx_wdt_isr(void *data)
{
- struct bcm63xx_wdt_hw *hw = &bcm63xx_wdt_device;
+ struct watchdog_device *wdd = data;
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
unsigned long flags;
raw_spin_lock_irqsave(&hw->lock, flags);
@@ -118,147 +117,36 @@ static void bcm63xx_wdt_isr(void *data)
}
ms = timeleft / (WDT_HZ / 1000);
- pr_alert("warning timer fired, reboot in %ums\n", ms);
+ dev_alert(wdd->dev,
+ "warning timer fired, reboot in %ums\n", ms);
}
raw_spin_unlock_irqrestore(&hw->lock
Re: [PATCH v5 4/4] devicetree: update documentation for fw_cfg ARM bindings
On Mon, Nov 23, 2015 at 10:57:44AM -0500, Gabriel L. Somlo wrote: > From: Gabriel Somlo > > Remove fw_cfg hardware interface details from > Documentation/devicetree/bindings/arm/fw-cfg.txt, > and replace them with a pointer to the authoritative > documentation in the QEMU source tree. > > Signed-off-by: Gabriel Somlo > Cc: Laszlo Ersek Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/arm/fw-cfg.txt | 38 > ++-- > 1 file changed, 2 insertions(+), 36 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt > b/Documentation/devicetree/bindings/arm/fw-cfg.txt > index 953fb64..ce27386 100644 > --- a/Documentation/devicetree/bindings/arm/fw-cfg.txt > +++ b/Documentation/devicetree/bindings/arm/fw-cfg.txt > @@ -11,43 +11,9 @@ QEMU exposes the control and data register to ARM guests > as memory mapped > registers; their location is communicated to the guest's UEFI firmware in the > DTB that QEMU places at the bottom of the guest's DRAM. > > -The guest writes a selector value (a key) to the selector register, and then > -can read the corresponding data (produced by QEMU) via the data register. If > -the selected entry is writable, the guest can rewrite it through the data > -register. > +The authoritative guest-side hardware interface documentation to the fw_cfg > +device ca be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. > > -The selector register takes keys in big endian byte order. > - > -The data register allows accesses with 8, 16, 32 and 64-bit width (only at > -offset 0 of the register). Accesses larger than a byte are interpreted as > -arrays, bundled together only for better performance. The bytes constituting > -such a word, in increasing address order, correspond to the bytes that would > -have been transferred by byte-wide accesses in chronological order. > - > -The interface allows guest firmware to download various parameters and blobs > -that affect how the firmware works and what tables it installs for the guest > -OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel > and > -initrd images for direct kernel booting, virtual machine UUID, SMP > information, > -virtual NUMA topology, and so on. > - > -The authoritative registry of the valid selector values and their meanings is > -the QEMU source code; the structure of the data blobs corresponding to the > -individual key values is also defined in the QEMU source code. > - > -The presence of the registers can be verified by selecting the "signature" > blob > -with key 0x, and reading four bytes from the data register. The returned > -signature is "QEMU". > - > -The outermost protocol (involving the write / read sequences of the control > and > -data registers) is expected to be versioned, and/or described by feature > bits. > -The interface revision / feature bitmap can be retrieved with key 0x0001. The > -blob to be read from the data register has size 4, and it is to be > interpreted > -as a uint32_t value in little endian byte order. The current value > -(corresponding to the above outer protocol) is zero. > - > -The guest kernel is not expected to use these registers (although it is > -certainly allowed to); the device tree bindings are documented here because > -this is where device tree bindings reside in general. > > Required properties: > > -- > 2.4.3 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] dt-bindings: add multidomain support to i.MX GPC DT binding
On Mon, Nov 23, 2015 at 04:07:01PM +0100, Lucas Stach wrote: > This adds a new binding for the Freescale i.MX GPC block, which allows > to describe multiple power domains in a more natural way. The driver > will continue to support the old binding for existing DTBs, but new > features like the additional domains present on i.MX6SX will only be > usable with the new binding. > > Signed-off-by: Lucas Stach > --- > .../devicetree/bindings/power/fsl,imx-gpc.txt | 81 > ++ > 1 file changed, 54 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > index 65cc0345747d..0b777b623812 100644 > --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > @@ -1,22 +1,41 @@ > Freescale i.MX General Power Controller > === > > -The i.MX6Q General Power Control (GPC) block contains DVFS load tracking > -counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power > -domains. > +The i.MX6 General Power Control (GPC) block contains DVFS load tracking > +counters and Power Gating Control (PGC). > > Required properties: > - compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc" > - reg: should be register base and length as documented in the >datasheet > -- interrupts: Should contain GPC interrupt request 1 > -- pu-supply: Link to the LDO regulator powering the PU power domain > -- clocks: Clock phandles to devices in the PU power domain that need > - to be enabled during domain power-up for reset propagation. > -- #power-domain-cells: Should be 1, see below: > +- interrupts: Should contain GPC interrupts How many and order? The rest looks fine. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device
On Tue, Nov 24, 2015 at 05:21:30PM -0600, Rob Herring wrote:
> On Tue, Nov 24, 2015 at 03:03:28PM +0800, Shengjiu Wang wrote:
> > ESAI need to enable the spba clock, when sdma is using share peripheral
> > script. In this case, there is two spba master port is used, if don't
> > enable the clock, the spba bus will have arbitration issue, which may
> > cause read/write wrong data from/to ESAI registers.
> >
> > Signed-off-by: Shengjiu Wang
> > ---
> > Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +
>
> Acked-by: Rob Herring
Hi Mark, Rob
Just a reminder. There is V4 for this patch set. I think the "Acked-by:" is
for the V4. Thanks.
best regards
wang shengjiu
>
> > sound/soc/fsl/fsl_esai.c | 13 +
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> > b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> > index d3b6b5f..cd3ee5d 100644
> > --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> > +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> > @@ -27,6 +27,11 @@ Required properties:
> > derive HCK, SCK and FS.
> > "fsys"The system clock derived from ahb clock used to
> > derive HCK, SCK and FS.
> > + "spba"The spba clock is required when ESAI is placed as a
> > + bus slave of the Shared Peripheral Bus and when two
> > + or more bus masters (CPU, DMA or DSP) try to access
> > + it. This property is optional depending on the SoC
> > + design.
> >
> >- fsl,fifo-depth : The number of elements in the transmit and receive
> > FIFOs. This number is the maximum allowed value for
> > diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> > index 504e731..4d7589c 100644
> > --- a/sound/soc/fsl/fsl_esai.c
> > +++ b/sound/soc/fsl/fsl_esai.c
> > @@ -35,6 +35,7 @@
> > * @coreclk: clock source to access register
> > * @extalclk: esai clock source to derive HCK, SCK and FS
> > * @fsysclk: system clock source to derive HCK, SCK and FS
> > + * @spbaclk: SPBA clock (optional, depending on SoC design)
> > * @fifo_depth: depth of tx/rx FIFO
> > * @slot_width: width of each DAI slot
> > * @slots: number of slots
> > @@ -54,6 +55,7 @@ struct fsl_esai {
> > struct clk *coreclk;
> > struct clk *extalclk;
> > struct clk *fsysclk;
> > + struct clk *spbaclk;
> > u32 fifo_depth;
> > u32 slot_width;
> > u32 slots;
> > @@ -469,6 +471,9 @@ static int fsl_esai_startup(struct snd_pcm_substream
> > *substream,
> > ret = clk_prepare_enable(esai_priv->coreclk);
> > if (ret)
> > return ret;
> > + ret = clk_prepare_enable(esai_priv->spbaclk);
> > + if (ret)
> > + goto err_spbaclk;
> > if (!IS_ERR(esai_priv->extalclk)) {
> > ret = clk_prepare_enable(esai_priv->extalclk);
> > if (ret)
> > @@ -499,6 +504,8 @@ err_fsysclk:
> > if (!IS_ERR(esai_priv->extalclk))
> > clk_disable_unprepare(esai_priv->extalclk);
> > err_extalck:
> > + clk_disable_unprepare(esai_priv->spbaclk);
> > +err_spbaclk:
> > clk_disable_unprepare(esai_priv->coreclk);
> >
> > return ret;
> > @@ -564,6 +571,7 @@ static void fsl_esai_shutdown(struct snd_pcm_substream
> > *substream,
> > clk_disable_unprepare(esai_priv->fsysclk);
> > if (!IS_ERR(esai_priv->extalclk))
> > clk_disable_unprepare(esai_priv->extalclk);
> > + clk_disable_unprepare(esai_priv->spbaclk);
> > clk_disable_unprepare(esai_priv->coreclk);
> > }
> >
> > @@ -819,6 +827,11 @@ static int fsl_esai_probe(struct platform_device *pdev)
> > dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
> > PTR_ERR(esai_priv->fsysclk));
> >
> > + esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
> > + if (IS_ERR(esai_priv->spbaclk))
> > + dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
> > + PTR_ERR(esai_priv->spbaclk));
> > +
> > irq = platform_get_irq(pdev, 0);
> > if (irq < 0) {
> > dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
> > --
> > 1.9.1
> >
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Re: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node
On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote:
> On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote:
>> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote:
>>>
>>> Hi,
>>>
>>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
Add a node describing the Security ID memory to the
Allwinner H3 .dtsi file.
Signed-off-by: Josef Gajdusek >
---
arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>>> b/arch/arm/boot/dts/sun8i-h3.dtsi
index 0faa38a..58de718 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -359,6 +359,13 @@
#size-cells = <0>;
};
+sid: eeprom@01c14000 {
+compatible = "allwinner,sun4i-a10-sid";
+reg = <0x01c14000 0x400>;
>>>
>>> The datasheet says it's 256 bytes wide, while the size here is of 1kB,
>>> is it intentional?
>>
>> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space.
>> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100.
>
> Interesting, what is below the 0x200 registers?
>
Some control register about SID.
offset: 0x40 SID Program/Read Control Register
offset: 0x50 SID Program Key Value Register
offset: 0x60 SID Read Key Value Register
offset: 0x70 \
offset: 0x80 SJTAG Attribute 0 Register
offset: 0x84 SJTAG Attribute 1 Register
offset: 0x88 SJTAG Select Register
offset: 0x90 SID Program Ctrol register for burned timing
>
> Thanks!
> Maxime
>
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Re: [PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling
On Mon, Nov 23, 2015 at 02:55:58PM +0100, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> This patch series add minimal L1 and L2 cache descriptions to DT for
> r8a7740 and sh73a0, and migrates the shmobile DT-based generic r8a7740
> platform from calling l2x0_of_init() to the generic l2c OF
> initialization.
>
> Note that the conversion to the generic l2c OF initialization is not
> done yet for sh73a0, as this initializes the L2 cache earlier, breaking
> the (fragile) sh73a0 secondary CPU bringup code.
>
> Also note that this conversion should be done on r8a7778, and r8a7779,
> too.
Based on your work I have prepared a DT patch for the r8a7779.
I don't think that a C patch is necessary, please correct me if I am wrong.
Regarding the r8a7778: My reading of the documentation is that although a
pl310 L2 cache controller is present it is not available for use as there
is no L2 cache memory present. For this reason I do not think any patches
are required for the r8a7798.
> Changes compared to v4 ("[PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT
> Cache Handling",
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
> - Drop optional cache-{size,sets,{block,line}-size} properties, as
> this information is auto-detected (I verified this for both L1 and
> L2 cache properties),
> - Merge the L1 patches into the L2 patches, as the only part left from
> the L1 patches was adding the links from CPU to L2 cache nodes.
>
> Changes compared to v3 ("[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 :
> Shared Override",
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
> - "l2c: Add support for the "arm,shared-override" property" was split
> off into an independent patch, and is now queued for v4.3 in
> arm/for-next,
> - Dropped armadillo legacy migration, as it no longer exists,
> - Added sh73a0 L1 and L2 DT cache description.
>
> Changes compared to v2 ("[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
> Migrate to generic l2c OF",
> http://www.spinics.net/lists/devicetree/msg68176.html):
> - Add DT support for Shared Override,
> - Setting Shared Override is done only if CMA is not available (as
> Russell claims it's not needed if CMA is available),
> - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
> "arm,shared-override".
>
> Changes compared to v1:
> - Fix interrupt reference in DT,
> - Describe L2 better in DT,
> - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
> machine_desc.l2c_aux_{val,mask}, as there's no DT property for
> this.
> - Add L1 cache to DT.
>
> Dependencies:
> - This series applies to renesas-devel-20151123-v4.4-rc2,
> - Patch 3 depends on patch 1,
> - Patch 4 depends on patch 3.
>
> Given C code changesets depending on DT changesets in the same branch
> are frowned upon, you may want to postpone patches 3 and 4 to v4.6.
> Of course I'll sleep better if you just apply all 4 of them now ;-)
I have queued up the DT changes for v4.5.
And tentatively queued up the C changes for v4.6.
> I've been running this on r8a7740/armadillo and sh73a0/kzm9g for more
> than a year.
>
> Thanks for applying!
>
> Geert Uytterhoeven (4):
> ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
> ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node
> ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
> ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
> registers
>
> arch/arm/boot/dts/r8a7740.dtsi | 13 +
> arch/arm/boot/dts/sh73a0.dtsi | 14 ++
> arch/arm/mach-shmobile/setup-r8a7740.c | 18 ++
> 3 files changed, 29 insertions(+), 16 deletions(-)
>
> --
> 1.9.1
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
>
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[PATCH] thermal: rcar: enable to set tripN-temp via DT
From: Kuninori Morimoto
Current rcar thermal driver is using 90 degrees as trip temp, but it
should be based on each SoC / platform.
This patch enables to set trip temp via DT. (It uses db8500-thermal
style for it)
It will use 90 degrees as default trip temp if DT doesn't have it.
Signed-off-by: Kuninori Morimoto
---
.../devicetree/bindings/thermal/rcar-thermal.txt | 2 ++
drivers/thermal/rcar_thermal.c | 34 --
2 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 332e625..6c57f7e 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -18,6 +18,8 @@ Required properties:
Option properties:
- interrupts : use interrupt
+- tripN-temp : temperature of trip point N. it will use 9 as
default
+ if DT doesn't have tripN-temp
Example (non interrupt support):
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 5d4ae7d..d1d0b58 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -63,6 +63,7 @@ struct rcar_thermal_priv {
struct mutex lock;
struct list_head list;
int id;
+ int trip_temp;
u32 ctemp;
};
@@ -222,7 +223,7 @@ static int rcar_thermal_get_trip_type(struct
thermal_zone_device *zone,
/* see rcar_thermal_get_temp() */
switch (trip) {
- case 0: /* +90 <= temp */
+ case 0:
*type = THERMAL_TRIP_CRITICAL;
break;
default:
@@ -241,8 +242,8 @@ static int rcar_thermal_get_trip_temp(struct
thermal_zone_device *zone,
/* see rcar_thermal_get_temp() */
switch (trip) {
- case 0: /* +90 <= temp */
- *temp = MCELSIUS(90);
+ case 0:
+ *temp = priv->trip_temp;
break;
default:
dev_err(dev, "rcar driver trip error\n");
@@ -361,6 +362,30 @@ static irqreturn_t rcar_thermal_irq(int irq, void *data)
/*
* platform functions
*/
+static void rcar_thermal_of_parse(struct rcar_thermal_priv *priv)
+{
+ struct device *dev = rcar_priv_to_dev(priv);
+ struct device_node *np = dev->of_node;
+ char prop_name[32];
+ s32 val;
+
+ /*
+* let's use db8500 thermal style
+*/
+ sprintf(prop_name, "trip%d-temp", priv->id);
+ if (of_property_read_s32(np, prop_name, &val))
+ return;
+
+ if (val < -45000 ||
+ val > 125000) {
+ dev_err(dev, "unsupported trip temp, use default\n");
+ return;
+ }
+
+ /* overwrite trip temp */
+ priv->trip_temp = val;
+}
+
static int rcar_thermal_probe(struct platform_device *pdev)
{
struct rcar_thermal_common *common;
@@ -418,11 +443,14 @@ static int rcar_thermal_probe(struct platform_device
*pdev)
priv->common = common;
priv->id = i;
+ priv->trip_temp = MCELSIUS(90); /* default*/
mutex_init(&priv->lock);
INIT_LIST_HEAD(&priv->list);
INIT_DELAYED_WORK(&priv->work, rcar_thermal_work);
rcar_thermal_update_temp(priv);
+ rcar_thermal_of_parse(priv);
+
priv->zone = thermal_zone_device_register("rcar_thermal",
1, 0, priv,
&rcar_thermal_zone_ops, NULL, 0,
--
1.9.1
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Re: [PATCH v5 0/6] MT8173 IOMMU SUPPORT
On Tue, 2015-11-24 at 11:38 +0100, Thierry Reding wrote: > On Tue, Nov 24, 2015 at 01:58:13PM +0800, Yong Wu wrote: > > On Fri, 2015-10-23 at 11:26 +0200, Joerg Roedel wrote: > > > On Thu, Oct 22, 2015 at 12:40:02PM +0800, Yong Wu wrote: > > > > But the mtk-iommu depend on the drivers/memory/mtk-smi.c(mtk-iommu > > > > has called a function of the mtk-smi). > > > > So if there is dependence here, How should we do to merge them? > > > > > > I can surely merge mtk-smi too, if it gets proper Reviewed-by and > > > Acked-by tags from the maintainer(s). > > > > > > > > > Joerg > > > > > Hi Joerg, > > > >About the driver/memory/, We don't know who is his maintainer. > > MAINTAINERS file don't have drivers/memory maintainer. > > From the history in drivers/memory/ it looks like most of the > > drivers land with an ack from the architecture maintainer. > > And Matthias Brugger is our "ARM/Mediatek SoC support" maintainer. > > > > Then do you mean that we need Matthias's ACK or whom others? > > Yes, I think the sub-architecture maintainer's ACK is probably going to > be as good as it gets. Historically drivers/memory hasn't had enough of > a common ground to instate a framework. > > Thierry Got it. Thanks very much for your reply. > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: vf6xx: Cosmic+: M4(nommu) initial support
On Sun, Oct 25, 2015 at 11:20:56PM +0530, Afzal Mohammed wrote: > Minimal Cortex-M4 device tree to boot Linux to shell. M4 is booted via > Cortex-A5 running Linux using Stefan Agner's "m4boot" > utility. > > Signed-off-by: Afzal Mohammed Applied, thanks. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: usb-dmac: Document SoC specific bindings
On Tue, Nov 24, 2015 at 05:49:05AM +, Yoshihiro Shimoda wrote: > Hi Simon-san, > > > From: Simon Horman [mailto:horms+rene...@verge.net.au] > > Sent: Tuesday, November 24, 2015 11:21 AM > > > > In general Renesas hardware is not documented to the extent where the > > relationship between IP blocks on different SoCs can be assumed although > > they may appear to operate the same way. Furthermore the documentation > > typically does not specify a version for individual IP blocks. For these > > reasons a convention of using the SoC name in place of a version and > > providing SoC-specific compat strings has been adopted. > > > > Although not universally liked this convention is used in the bindings for > > most drivers for Renesas hardware. The purpose of this patch is to > > update the Renesas USB DMA Controller driver to follow this convention. > > > > Cc: devicetree@vger.kernel.org > > Cc: Yoshihiro Shimoda > > Signed-off-by: Simon Horman > > Thank you for the patch! > > > --- > > * r8a7792 (R-Car V2H) is omitted as my reading of the documentation > > is that Renesas USB-DMAC does not exist on that SoC > > I agree with you. > > > * r8a7795 (R-Car H2) is omitted as its unclear to me on the compatibility > > of USB-DMAC that SoC > > I think this is R-Car H3, not H2. Yes, H3. Sorry about that. > Since R-Car H3's USB-DMAC is compatible with other SoCs, > would you add the R-Car H3's compatible string, if possible? Sure, will do. > Anyway, > Acked-by: Yoshihiro Shimoda Thanks! -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: usb-dmac: Document SoC specific bindings
On Tue, Nov 24, 2015 at 02:16:55PM -0600, Rob Herring wrote:
> On Tue, Nov 24, 2015 at 11:20:41AM +0900, Simon Horman wrote:
> > In general Renesas hardware is not documented to the extent where the
> > relationship between IP blocks on different SoCs can be assumed although
> > they may appear to operate the same way. Furthermore the documentation
> > typically does not specify a version for individual IP blocks. For these
> > reasons a convention of using the SoC name in place of a version and
> > providing SoC-specific compat strings has been adopted.
> >
> > Although not universally liked this convention is used in the bindings for
> > most drivers for Renesas hardware. The purpose of this patch is to
> > update the Renesas USB DMA Controller driver to follow this convention.
> >
> > Cc: devicetree@vger.kernel.org
> > Cc: Yoshihiro Shimoda
> > Signed-off-by: Simon Horman
> >
> > ---
> > * r8a7792 (R-Car V2H) is omitted as my reading of the documentation
> > is that Renesas USB-DMAC does not exist on that SoC
> > * r8a7795 (R-Car H2) is omitted as its unclear to me on the compatibility
> > of USB-DMAC that SoC
> >
> > * Once this has been merged I intend to provide follow-up patches
> > to use these new compat strings in the relevant dtsi files.
> > ---
> > Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> > b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> > index 040f365954cc..3bb624e10615 100644
> > --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> > +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> > @@ -1,7 +1,12 @@
> > * Renesas USB DMA Controller Device Tree bindings
> >
> > Required Properties:
> > -- compatible: must contain "renesas,usb-dmac"
> > +- compatible: "renesas,usb-dmac-", "renesas,usb-dmac" as fallback.
> > + Examples with soctypes are:
> > + - "renesas,usb-dmac-r8a7790" (R-Car H2)
> > + - "renesas,usb-dmac-r8a7791" (R-Car M2-W)
> > + - "renesas,usb-dmac-r8a7793" (R-Car M2-N)
> > + - "renesas,usb-dmac-r8a7794" (R-Car E2)
>
> Weren't you changing the order of SoC and block names on new bindings?
Could you clarify what the desired order is?
My intention is for these bindings to use the preferred order.
> Either way:
>
> Acked-by: Rob Herring
>
> Rob
>
> > - reg: base address and length of the registers block for the DMAC
> > - interrupts: interrupt specifiers for the DMAC, one for each entry in
> >interrupt-names.
> > @@ -15,7 +20,7 @@ Required Properties:
> > Example: R8A7790 (R-Car H2) USB-DMACs
> >
> > usb_dmac0: dma-controller@e65a {
> > - compatible = "renesas,usb-dmac";
> > + compatible = "renesas,usb-dmac-r8a7790", "renesas,usb-dmac";
> > reg = <0 0xe65a 0 0x100>;
> > interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
> > 0 109 IRQ_TYPE_LEVEL_HIGH>;
> > --
> > 2.1.4
> >
> > --
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> > the body of a message to majord...@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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Re: [PATCH] Enable PCIe PHY support in Cygnus
On 18/11/15 10:16, Ray Jui wrote: > This patch enales PCIe PHY in device tree for Broadcom Cygnus based platforms > > This patch is developed based on v4.4-rc1 and available here: > https://github.com/Broadcom/cygnus-linux/tree/cygnus-pcie-phy-dt-v1 > > Ray Jui (1): > ARM: dts: enable PCIe PHY support for Cygnus Applied to devicetree/next with Scott's Acked-by, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/7] dts: define ngpios property in gpio controller's node
On 18/11/15 19:52, Pramod Kumar wrote: > Add ngpios property in cygnus ASIU, CCM and CRMU gpio controller's node > > Signed-off-by: Pramod Kumar > Reviewed-by: Ray Jui > Reviewed-by: Scott Branden Applied to devicetree/next with a more specific subject, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: enable pinctrl for Broadcom NSP
On 20/11/15 09:58, Yendapally Reddy Dhananjaya Reddy wrote:
> This enables the pinctrl support for Broadcom NSP SoC
>
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy
Looks like a sane pinctrl node here, unless there are objections, I
would like to go ahead and apply this for v4.5, thanks!
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++
> arch/arm/boot/dts/bcm958625k.dts | 9 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index b74438c..a16d743 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -226,5 +226,12 @@
> interrupts = ;
> clock-frequency = <10>;
> };
> +
> + pinctrl: pinctrl@3f1c0 {
> + compatible = "brcm,nsp-pinmux";
> + reg = <0x3f1c0 0x04>,
> + <0x30028 0x04>,
> + <0x3f408 0x04>;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/bcm958625k.dts
> b/arch/arm/boot/dts/bcm958625k.dts
> index b966955..e298450 100644
> --- a/arch/arm/boot/dts/bcm958625k.dts
> +++ b/arch/arm/boot/dts/bcm958625k.dts
> @@ -105,3 +105,12 @@
> };
> };
> };
> +
> +&pinctrl {
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_sel>;
> + nand_sel: nand_sel {
> + function = "nand";
> + groups = "nand_grp";
> + };
> +};
>
--
Florian
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Re: [RESEND v4 1/6] remoteproc: dt: Provide bindings for ST's Remote Processor Controller driver
On Tue, Nov 24, 2015 at 01:14:17PM +, Lee Jones wrote:
> Signed-off-by: Ludovic Barre
> Signed-off-by: Lee Jones
> ---
> .../devicetree/bindings/remoteproc/st-rproc.txt| 41
> ++
Acked-by: Rob Herring
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/remoteproc/st-rproc.txt
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/st-rproc.txt
> b/Documentation/devicetree/bindings/remoteproc/st-rproc.txt
> new file mode 100644
> index 000..1031bcd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/st-rproc.txt
> @@ -0,0 +1,41 @@
> +STMicroelectronics Co-Processor Bindings
> +
> +
> +This binding provides support for adjunct processors found on ST SoCs.
> +
> +Co-processors can be controlled from the bootloader or the primary OS. If
> +the bootloader starts a co-processor, the primary OS must detect its state
> +and act accordingly.
> +
> +Required properties:
> +- compatible Should be one of:
> + "st,st231-rproc"
> + "st,st40-rproc"
> +- memory-region Reserved memory (See:
> ../reserved-memory/reserved-memory.txt)
> +- resets Reset lines (See: ../reset/reset.txt)
> +- reset-namesMust be "sw_reset" and "pwr_reset"
> +- clocks Clock for co-processor (See:
> ../clock/clock-bindings.txt)
> +- clock-frequencyClock frequency to set co-processor at if the bootloader
> + hasn't already done so
> +- st,syscfg System configuration register which holds the boot
> vector
> + for the co-processor
> + 1st cell: Phandle to syscon block
> + 2nd cell: Boot vector register offset
> +
> +Example:
> +
> + audio_reserved: rproc@4200 {
> + compatible = "shared-dma-pool";
> + reg = <0x4200 0x0100>;
> + no-map;
> + };
> +
> + st231-audio {
> + compatible = "st,st231-rproc";
> + memory-region = <&audio_reserved>;
> + resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
> + reset-names = "sw_reset";
> + clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
> + clock-frequency = <6>;
> + st,syscfg = <&syscfg_core 0x228>;
> + };
> --
> 1.9.1
>
> --
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Re: [PATCH RESEND v2 0/4] SMP support for Broadcom NSP
On 06/11/15 11:49, Kapil Hali wrote:
> This is the second iteration in the series.
>
> Changes in v2:
> Removed the pen_holding method of SMP bringup for NSP SoC and
> replaced it with simple wakeup of secondary core using ARM IPI.
>
>
> This series adds SMP support for Broadcom's Northstar Plus SoC.
>
> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
> BCM NSP SoC, has a typical such mechanism - after power-on, the
> secondary core is held in a standby state, primary core provides a
> startup address for the secondary core and wakes it up. Booting of
> the secondary core is serialized using pen_release global variable.
>
> The startup address is programmed at a special register location
> which is defined in the device tree using a "secondary-boot-reg"
> property in a node whose "enable-method" property matches.
>
> The first patch adds cpu-enable-method in the device tree bindings
> documentation. It also updates ARM CPU device tree documentation
> with Broadcom Northstar Plus CPU details.
>
> The second patch adds SMP support to the BCM NSP device tree file.
>
> The third patch, enables SMP on BCM NSP. It also consolidates
> common SMP handling between BCM NSP and BCM Kona.
>
> The final patch, enables SMP on BCM 4708 and this patch is pulled
> in from Jon Mason's patch from the mailing list.
>
> This patch series is constructed based on Linux v4.3-rc2.
>
> The source code is available at GITHUB:
> https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1
Kapil, were there additional changes requested for this patch series to
be applied? The secondary-boot-reg property should probably be made part
of the CPU node, even though you are strictly following the existing
Kona SMP binding here (which was partially wrong on that subject).
Could you resubmit these patches if there is anything that needs
changing? Thanks!
>
> Jon Mason (1):
> ARM: BCM: Add SMP support for Broadcom 4708
>
> Kapil Hali (3):
> dt-bindings: add SMP enable-method for Broadcom NSP
> ARM: dts: add SMP support for Broadcom NSP
> ARM: BCM: Add SMP support for Broadcom NSP
>
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 +
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> arch/arm/boot/dts/bcm-nsp.dtsi | 33 ++---
> arch/arm/boot/dts/bcm4708.dtsi | 2 +
> arch/arm/mach-bcm/Kconfig | 3 +
> arch/arm/mach-bcm/Makefile | 11 ++-
> arch/arm/mach-bcm/bcm_nsp.h| 19 +
> arch/arm/mach-bcm/{kona_smp.c => platsmp.c}| 85
> +++---
> 8 files changed, 167 insertions(+), 23 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
> rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)
>
--
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Re: [PATCH v2 1/2] Add binding documentation for Zodiac Watchdog Timer
On Tue, Nov 24, 2015 at 01:04:09PM +, Martyn Welch wrote:
> This patchs adds documentation for the binding of the Zodiac RAVE
> Switch Watchdog Processor. This is an i2c based watchdog.
>
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Martyn Welch
> ---
>
> v2: Addition of optional properties.
>
> .../devicetree/bindings/watchdog/ziirave-wdt.txt | 19
> +++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt
>
> diff --git a/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt
> b/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt
> new file mode 100644
> index 000..069cc2a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt
> @@ -0,0 +1,19 @@
> +Zodiac RAVE Watchdog Timer
> +
> +Required properties:
> +- compatible: must be "zii,rave-wdt"
> +- reg: i2c slave address of device, usually 0x38
> +
> +Optional Properties:
> +- timeout-sec: Watchdog timeout value in seconds.
> +- reset-duration-msec: Duration of the pulse generated when the watchdog
> times
Should be "-ms" rather than msec.
> + out. Value in milliseconds.
> +
> +Example:
> +
> + watchdog@38 {
> + compatible = "zii,rave-wdt";
> + reg = <0x38>;
> + timeout-sec = <30>;
> + reset-duration-msec = <30>;
> + };
> --
> 2.1.4
>
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Re: [PATCH 2/5] Documentation: devicetree: Add property for controlling power saving mode for the us5182 als sensor
On Tue, Nov 24, 2015 at 12:59:49PM +0200, Adriana Reus wrote: > Add a property to allow changing the default power-saving mode. > By default, at read raw the chip will activate and provide > one measurent, then it will shut itself down. However, the > chip can also work in "continuous" mode which may be more reliable > but is also more power consuming. > > Signed-off-by: Adriana Reus > --- > Documentation/devicetree/bindings/iio/light/us5182d.txt | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iio/light/us5182d.txt > b/Documentation/devicetree/bindings/iio/light/us5182d.txt > index 6f0a530..a619799 100644 > --- a/Documentation/devicetree/bindings/iio/light/us5182d.txt > +++ b/Documentation/devicetree/bindings/iio/light/us5182d.txt > @@ -7,13 +7,24 @@ Required properties: > Optional properties: > - upisemi,glass-coef: glass attenuation factor - compensation factor of >resolution 1000 for material transmittance. > + > - upisemi,dark-ths: array of 8 elements containing 16-bit thresholds (adc > counts) corresponding to every scale. > + > - upisemi,upper-dark-gain: 8-bit dark gain compensation factor(4 int and 4 > fractional bits - Q4.4) applied when light > > threshold > + > - upisemi,lower-dark-gain: 8-bit dark gain compensation factor(4 int and 4 > fractional bits - Q4.4) applied when light < > threshold > > +- upisemi,continuous: This chip has two power modes: one-shot (chip takes one > + measurement and then shuts itself down) and continuous > ( > + chip takes continuous measurements). The one-shot mode > is > + more power-friendly but the continuous mode may be more > + reliable. If this property is specified the continuous > + mode will be used instead of the default one-shot one > for > + raw reads. I could imagine an OS may want to decide this on its own or use a mixture of the modes. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] Documentation: devicetree: add epson rx6110 binding
On Tue, Nov 24, 2015 at 12:12:41PM +0100, Philipp Zabel wrote: > Am Dienstag, den 24.11.2015, 11:38 +0100 schrieb Steffen Trumtrar: > > Add the binding documentation for the Epson RX6110 RTC. > > > > Signed-off-by: Steffen Trumtrar [...] > > +Required properties: > > +- compatible: should be: "epson,rtc-rx6110" > > Should this just be "epson,rx6110" ? Yes. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] Documentation: devicetree: add epson rx6110 binding
On Tue, Nov 24, 2015 at 11:38:52AM +0100, Steffen Trumtrar wrote:
> Add the binding documentation for the Epson RX6110 RTC.
>
> Signed-off-by: Steffen Trumtrar
> ---
> I'm not sure what the current policy for such simple SPI bindings is.
> Are they necessary?
Yes. We do have trivial-devices.txt for i2c. We could do one for spi.
Although, you need the mode configuration for each device, so spi is not
so trivial.
>
> .../devicetree/bindings/rtc/epson,rtc-rx6110.txt | 25
> ++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
>
> diff --git a/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> b/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> new file mode 100644
> index ..7ce7ae761657
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> @@ -0,0 +1,25 @@
> +Epson RX6110 Real Time Clock
> +
> +
> +The Epson RX6110 can be used with SPI or I2C busses. The kind of
> +bus depends on the SPISEL pin and can not be configured via software.
Can you document I2C mode. It should just be the compatible and reg
properties.
> +
> +SPI mode
> +
> +
> +Required properties:
> +- compatible: should be: "epson,rtc-rx6110"
> +- reg: chip select number
> +- spi-cs-high: RX6110 needs chipselect high
> +- spi-cpha: RX6110 works with SPI shifted clock phase
> +- spi-cpol: RX6110 works with SPI inverse clock polarity
> +
> +Example:
> +
> + rtc: rtc@3 {
> + compatible = "epson,rtc-rx6110"
> + reg = <3>
> + spi-cs-high;
> + spi-cpba;
> + spi-cpol;
> + };
> --
> 2.6.2
>
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Re: [PATCH] ARM: keystone: dts: add PCI serdes driver bindings
Hi WingMan,
On Thu, Oct 15, 2015 at 10:27:10AM -0400, WingMan Kwok wrote:
> This patch adds the required PCI serdes bindings whcih can then be
> enabled by setting the corresponding statuses to "ok" in order to
> configure and start the PCI serdes.
>
> This patch depends on the updates to the Keystone PCIe host driver
> and common serdes driver patch series that is submitted separately.
>
> Signed-off-by: WingMan Kwok
Is there a reason to separate the binding update from the PCIe host
driver update? It would make sense to me to have them in the same
patch to make it easier to keep them consistent.
Bjorn
> ---
> arch/arm/boot/dts/k2e.dtsi | 21 +
> arch/arm/boot/dts/keystone.dtsi | 21 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
> index 675fb8e..3b36575 100644
> --- a/arch/arm/boot/dts/k2e.dtsi
> +++ b/arch/arm/boot/dts/k2e.dtsi
> @@ -86,6 +86,16 @@
> gpio,syscon-dev = <&devctrl 0x240>;
> };
>
> + pcie1_phy: pciephy@2326000 {
> + #phy-cells = <0>;
> + compatible = "ti,keystone-serdes-pcie";
> + reg = <0x02326000 0x4000>;
> + reg-names = "serdes";
> + link-rate-kbps = <500>;
> + num-lanes = <2>;
> + status = "disabled";
> + };
> +
> pcie1: pcie@2102 {
> compatible = "ti,keystone-pcie","snps,dw-pcie";
> clocks = <&clkpcie1>;
> @@ -130,6 +140,17 @@
> ,
> ;
> };
> +
> + /* PCIE phy */
> + serdeses {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + serdes@0 {
> + reg = <0>;
> + phys = <&pcie1_phy>;
> + };
> + };
> +
> };
>
> mdio: mdio@24200f00 {
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 72816d6..6566cc4 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -275,6 +275,16 @@
> ti,syscon-dev = <&devctrl 0x2a0>;
> };
>
> + pcie0_phy: pciephy@232 {
> + #phy-cells = <0>;
> + compatible = "ti,keystone-serdes-pcie";
> + reg = <0x0232 0x4000>;
> + reg-names = "serdes";
> + link-rate-kbps = <500>;
> + num-lanes = <2>;
> + status = "disabled";
> + };
> +
> pcie0: pcie@2180 {
> compatible = "ti,keystone-pcie", "snps,dw-pcie";
> clocks = <&clkpcie>;
> @@ -319,6 +329,17 @@
> ,
> ;
> };
> +
> + /* PCIE phy */
> + serdeses {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + serdes@0 {
> + reg = <0>;
> + phys = <&pcie0_phy>;
> + };
> + };
> +
> };
> };
> };
> --
> 1.7.9.5
>
> --
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Re: [PATCH V3 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device
On Tue, Nov 24, 2015 at 03:03:30PM +0800, Shengjiu Wang wrote:
> ASRC need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to ASRC registers
>
> Signed-off-by: Shengjiu Wang
> ---
> Documentation/devicetree/bindings/sound/fsl,asrc.txt | 5 +
For the binding:
Acked-by: Rob Herring
> sound/soc/fsl/fsl_asrc.c | 10 ++
> sound/soc/fsl/fsl_asrc.h | 2 ++
> 3 files changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> index b93362a..3e26a94 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> @@ -25,6 +25,11 @@ Required properties:
> "mem" Peripheral access clock to access registers.
> "ipg" Peripheral clock to driver module.
> "asrck_<0-f>" Clock sources for input and output clock.
> + "spba"The spba clock is required when ASRC is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
> - big-endian : If this property is absent, the little endian
> mode
> will be in use as default. Otherwise, the big endian
> diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
> index 9f087d4..800828e 100644
> --- a/sound/soc/fsl/fsl_asrc.c
> +++ b/sound/soc/fsl/fsl_asrc.c
> @@ -859,6 +859,10 @@ static int fsl_asrc_probe(struct platform_device *pdev)
> return PTR_ERR(asrc_priv->ipg_clk);
> }
>
> + asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(asrc_priv->spba_clk))
> + dev_warn(&pdev->dev, "failed to get spba clock\n");
> +
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
> sprintf(tmp, "asrck_%x", i);
> asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
> @@ -939,6 +943,9 @@ static int fsl_asrc_runtime_resume(struct device *dev)
> ret = clk_prepare_enable(asrc_priv->ipg_clk);
> if (ret)
> goto disable_mem_clk;
> + ret = clk_prepare_enable(asrc_priv->spba_clk);
> + if (ret)
> + goto disable_ipg_clk;
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
> ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
> if (ret)
> @@ -950,6 +957,8 @@ static int fsl_asrc_runtime_resume(struct device *dev)
> disable_asrck_clk:
> for (i--; i >= 0; i--)
> clk_disable_unprepare(asrc_priv->asrck_clk[i]);
> + clk_disable_unprepare(asrc_priv->spba_clk);
> +disable_ipg_clk:
> clk_disable_unprepare(asrc_priv->ipg_clk);
> disable_mem_clk:
> clk_disable_unprepare(asrc_priv->mem_clk);
> @@ -963,6 +972,7 @@ static int fsl_asrc_runtime_suspend(struct device *dev)
>
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
> clk_disable_unprepare(asrc_priv->asrck_clk[i]);
> + clk_disable_unprepare(asrc_priv->spba_clk);
> clk_disable_unprepare(asrc_priv->ipg_clk);
> clk_disable_unprepare(asrc_priv->mem_clk);
>
> diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h
> index 4aed63c..68802cd 100644
> --- a/sound/soc/fsl/fsl_asrc.h
> +++ b/sound/soc/fsl/fsl_asrc.h
> @@ -426,6 +426,7 @@ struct fsl_asrc_pair {
> * @paddr: physical address to the base address of registers
> * @mem_clk: clock source to access register
> * @ipg_clk: clock source to drive peripheral
> + * @spba_clk: SPBA clock (optional, depending on SoC design)
> * @asrck_clk: clock sources to driver ASRC internal logic
> * @lock: spin lock for resource protection
> * @pair: pair pointers
> @@ -442,6 +443,7 @@ struct fsl_asrc {
> unsigned long paddr;
> struct clk *mem_clk;
> struct clk *ipg_clk;
> + struct clk *spba_clk;
> struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
> spinlock_t lock;
>
> --
> 1.9.1
>
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Re: [PATCH V3 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device
On Tue, Nov 24, 2015 at 03:03:29PM +0800, Shengjiu Wang wrote:
> SPDIF need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to SPDIF registers.
>
> Signed-off-by: Shengjiu Wang
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.txt | 5 +
For the binding:
Acked-by: Rob Herring
> sound/soc/fsl/fsl_spdif.c | 15 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> index b5ee32e..4ca39dd 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -27,6 +27,11 @@ Required properties:
> Transceiver Clock Diagram" of SoC reference manual.
> It can also be referred to TxClk_Source bit of
> register SPDIF_STC.
> + "spba"The spba clock is required when SPDIF is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
> - big-endian : If this property is absent, the native endian
> mode
> will be in use as default, or the big endian mode
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> index 28a8823..64e2a1f 100644
> --- a/sound/soc/fsl/fsl_spdif.c
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -88,6 +88,7 @@ struct spdif_mixer_control {
> * @rxclk: rx clock sources for capture
> * @coreclk: core clock for register access via DMA
> * @sysclk: system clock for rx clock rate measurement
> + * @spbaclk: SPBA clock (optional, depending on SoC design)
> * @dma_params_tx: DMA parameters for transmit channel
> * @dma_params_rx: DMA parameters for receive channel
> */
> @@ -106,6 +107,7 @@ struct fsl_spdif_priv {
> struct clk *rxclk;
> struct clk *coreclk;
> struct clk *sysclk;
> + struct clk *spbaclk;
> struct snd_dmaengine_dai_dma_data dma_params_tx;
> struct snd_dmaengine_dai_dma_data dma_params_rx;
> /* regcache for SRPC */
> @@ -474,6 +476,12 @@ static int fsl_spdif_startup(struct snd_pcm_substream
> *substream,
> return ret;
> }
>
> + ret = clk_prepare_enable(spdif_priv->spbaclk);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to enable spba clock\n");
> + goto err_spbaclk;
> + }
> +
> ret = spdif_softreset(spdif_priv);
> if (ret) {
> dev_err(&pdev->dev, "failed to soft reset\n");
> @@ -515,6 +523,8 @@ disable_txclk:
> for (i--; i >= 0; i--)
> clk_disable_unprepare(spdif_priv->txclk[i]);
> err:
> + clk_disable_unprepare(spdif_priv->spbaclk);
> +err_spbaclk:
> clk_disable_unprepare(spdif_priv->coreclk);
>
> return ret;
> @@ -548,6 +558,7 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream
> *substream,
> spdif_intr_status_clear(spdif_priv);
> regmap_update_bits(regmap, REG_SPDIF_SCR,
> SCR_LOW_POWER, SCR_LOW_POWER);
> + clk_disable_unprepare(spdif_priv->spbaclk);
> clk_disable_unprepare(spdif_priv->coreclk);
> }
> }
> @@ -1261,6 +1272,10 @@ static int fsl_spdif_probe(struct platform_device
> *pdev)
> return PTR_ERR(spdif_priv->coreclk);
> }
>
> + spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(spdif_priv->spbaclk))
> + dev_warn(&pdev->dev, "no spba clock in devicetree\n");
> +
> /* Select clock source for rx/tx clock */
> spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
> if (IS_ERR(spdif_priv->rxclk)) {
> --
> 1.9.1
>
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Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device
On Tue, Nov 24, 2015 at 03:03:28PM +0800, Shengjiu Wang wrote:
> ESAI need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to ESAI registers.
>
> Signed-off-by: Shengjiu Wang
> ---
> Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +
Acked-by: Rob Herring
> sound/soc/fsl/fsl_esai.c | 13 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> index d3b6b5f..cd3ee5d 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> @@ -27,6 +27,11 @@ Required properties:
> derive HCK, SCK and FS.
> "fsys"The system clock derived from ahb clock used to
> derive HCK, SCK and FS.
> + "spba"The spba clock is required when ESAI is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
>- fsl,fifo-depth : The number of elements in the transmit and receive
> FIFOs. This number is the maximum allowed value for
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 504e731..4d7589c 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -35,6 +35,7 @@
> * @coreclk: clock source to access register
> * @extalclk: esai clock source to derive HCK, SCK and FS
> * @fsysclk: system clock source to derive HCK, SCK and FS
> + * @spbaclk: SPBA clock (optional, depending on SoC design)
> * @fifo_depth: depth of tx/rx FIFO
> * @slot_width: width of each DAI slot
> * @slots: number of slots
> @@ -54,6 +55,7 @@ struct fsl_esai {
> struct clk *coreclk;
> struct clk *extalclk;
> struct clk *fsysclk;
> + struct clk *spbaclk;
> u32 fifo_depth;
> u32 slot_width;
> u32 slots;
> @@ -469,6 +471,9 @@ static int fsl_esai_startup(struct snd_pcm_substream
> *substream,
> ret = clk_prepare_enable(esai_priv->coreclk);
> if (ret)
> return ret;
> + ret = clk_prepare_enable(esai_priv->spbaclk);
> + if (ret)
> + goto err_spbaclk;
> if (!IS_ERR(esai_priv->extalclk)) {
> ret = clk_prepare_enable(esai_priv->extalclk);
> if (ret)
> @@ -499,6 +504,8 @@ err_fsysclk:
> if (!IS_ERR(esai_priv->extalclk))
> clk_disable_unprepare(esai_priv->extalclk);
> err_extalck:
> + clk_disable_unprepare(esai_priv->spbaclk);
> +err_spbaclk:
> clk_disable_unprepare(esai_priv->coreclk);
>
> return ret;
> @@ -564,6 +571,7 @@ static void fsl_esai_shutdown(struct snd_pcm_substream
> *substream,
> clk_disable_unprepare(esai_priv->fsysclk);
> if (!IS_ERR(esai_priv->extalclk))
> clk_disable_unprepare(esai_priv->extalclk);
> + clk_disable_unprepare(esai_priv->spbaclk);
> clk_disable_unprepare(esai_priv->coreclk);
> }
>
> @@ -819,6 +827,11 @@ static int fsl_esai_probe(struct platform_device *pdev)
> dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
> PTR_ERR(esai_priv->fsysclk));
>
> + esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(esai_priv->spbaclk))
> + dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
> + PTR_ERR(esai_priv->spbaclk));
> +
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
> dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
> --
> 1.9.1
>
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Re: [PATCH V4 1/5] dt-bindings: Add QorIQ TMU thermal bindings
On Tue, Nov 24, 2015 at 02:52:44PM +0800, Jia Hongtao wrote:
> Add bindings documentation for TMU (Thermal Monitoring Unit) on QorIQ
> platform.
>
> Signed-off-by: Jia Hongtao
> Reviewed-by: Scott Wood
Acked-by: Rob Herring
> ---
> .../devicetree/bindings/thermal/qoriq-thermal.txt | 63
> ++
> 1 file changed, 63 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> new file mode 100644
> index 000..66223d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -0,0 +1,63 @@
> +* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
> +
> +Required properties:
> +- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> + determined by the TMU IP Block Revision Register (IPBRR0) at
> + offset 0x0BF8.
> + Table of correspondences between IPBRR0 values and example chips:
> + Value Device
> + -- -
> + 0x01900102 T1040
> +- reg : Address range of TMU registers.
> +- interrupts : Contains the interrupt for TMU.
> +- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
> + the SoC reference manual. The first cell is TTR0CR, the second is
> + TTR1CR, etc.
> +- fsl,tmu-calibration : A list of cell pairs containing temperature
> + calibration data, as specified by the SoC reference manual.
> + The first cell of each pair is the value to be written to TTCFGR,
> + and the second is the value to be written to TSCFGR.
> +
> +Example:
> +
> +tmu@f {
> + compatible = "fsl,qoriq-tmu";
> + reg = <0xf 0x1000>;
> + interrupts = <18 2 0 0>;
> + fsl,tmu-range = <0x000a 0x00090026 0x0008004a 0x0001006a>;
> + fsl,tmu-calibration = <0x 0x0025
> +0x0001 0x0028
> +0x0002 0x002d
> +0x0003 0x0031
> +0x0004 0x0036
> +0x0005 0x003a
> +0x0006 0x0040
> +0x0007 0x0044
> +0x0008 0x004a
> +0x0009 0x004f
> +0x000a 0x0054
> +
> +0x0001 0x000d
> +0x00010001 0x0013
> +0x00010002 0x0019
> +0x00010003 0x001f
> +0x00010004 0x0025
> +0x00010005 0x002d
> +0x00010006 0x0033
> +0x00010007 0x0043
> +0x00010008 0x004b
> +0x00010009 0x0053
> +
> +0x0002 0x0010
> +0x00020001 0x0017
> +0x00020002 0x001f
> +0x00020003 0x0029
> +0x00020004 0x0031
> +0x00020005 0x003c
> +0x00020006 0x0042
> +0x00020007 0x004d
> +0x00020008 0x0056
> +
> +0x0003 0x0012
> +0x00030001 0x001d>;
> +};
> --
> 2.1.0.27.g96db324
>
> --
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Re: [PATCH (v2) 7/10] watchdog: bcm63xx_wdt: Add get_timeleft function
On 24/11/15 14:15, Simon Arlott wrote: > Return the remaining time from the hardware control register. > > Warn when the device is registered if the hardware watchdog is currently > running and report the remaining time left. > > Signed-off-by: Simon Arlott Reviewed-by: Florian Fainelli At some point, we should probably consider merging bcm63xx_wdt with bcm7038_wdt which are nearly 100% identical pieces of hardware (coming from the same design group originally). -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v2) 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk
On 24/11/15 14:12, Simon Arlott wrote: > Instead of using a fixed clock HZ in the driver, obtain it from the > "periph" clk that the watchdog timer uses. > > Signed-off-by: Simon Arlott Reviewed-by: Florian Fainelli -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v3) 2/10] MIPS: bmips: Add bcm6345-l2-timer interrupt controller
On 24/11/15 14:10, Simon Arlott wrote:
> Add the BCM6345/BCM6318 timer as an interrupt controller so that it can be
> used by the watchdog to warn that its timer will expire soon.
>
> Support for clocksource/clockevents is not implemented as the timer
> interrupt is not per CPU (except on the BCM6318) and the MIPS clock is
> better. This could be added later if required without changing the device
> tree binding.
>
> Signed-off-by: Simon Arlott
> ---
> Fixed the offset of the count registers, they were writing off by one which
> caused it to set the watchdog timeout to 0.
>
> drivers/irqchip/Kconfig| 5 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-bcm6345-l2-timer.c | 324
> +
> 3 files changed, 330 insertions(+)
> create mode 100644 drivers/irqchip/irq-bcm6345-l2-timer.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index d307bb3..21c3d9b 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -70,6 +70,11 @@ config BCM6345_L1_IRQ
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
>
> +config BCM6345_L2_TIMER_IRQ
> + bool
> + select GENERIC_IRQ_CHIP
> + select IRQ_DOMAIN
> +
> config BCM7038_L1_IRQ
> bool
> select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index ded59cf..2687dea 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_XTENSA_MX) +=
> irq-xtensa-mx.o
> obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
> obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
> obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
> +obj-$(CONFIG_BCM6345_L2_TIMER_IRQ) += irq-bcm6345-l2-timer.o
> obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
> obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
> obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
> diff --git a/drivers/irqchip/irq-bcm6345-l2-timer.c
> b/drivers/irqchip/irq-bcm6345-l2-timer.c
> new file mode 100644
> index 000..4e6f71b
> --- /dev/null
> +++ b/drivers/irqchip/irq-bcm6345-l2-timer.c
> @@ -0,0 +1,324 @@
> +/*
> + * Copyright 2015 Simon Arlott
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Based on arch/mips/bcm63xx/timer.c:
> + * Copyright (C) 2008 Maxime Bizon
> + *
> + * Registers for SoCs with 4 timers: BCM6345, BCM6328, BCM6362, BCM6816,
> + * BCM68220,BCM63168, BCM63268
> + * 0x02: IRQ enable (u8)
> + * 0x03: IRQ status (u8)
> + * 0x04: Timer 0 control
> + * 0x08: Timer 1 control
> + * 0x0c: Timer 2 control
> + * 0x10: Timer 0 count
> + * 0x14: Timer 1 count
> + * 0x18: Timer 2 count
> + * 0x1c+: Watchdog registers
> + *
> + * Registers for SoCs with 5 timers: BCM6318
> + * 0x00: IRQ enable (u32)
> + * 0x04: IRQ status (u32)
> + * 0x08: Timer 0 control
> + * 0x0c: Timer 1 control
> + * 0x10: Timer 2 control
> + * 0x14: Timer 3 control
> + * 0x18: Timer 0 count
> + * 0x1c: Timer 1 count
> + * 0x20: Timer 2 count
> + * 0x24: Timer 3 count
> + * 0x28+: Watchdog registers
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define REG_6345_IRQ_ENABLE 0x02
> +#define REG_6345_IRQ_STATUS 0x03
> +#define REG_6345_CONTROL_BASE0x04
> +#define REG_6345_COUNT_BASE 0x10
> +
> +#define REG_6318_IRQ_ENABLE 0x00
> +#define REG_6318_IRQ_STATUS 0x04
> +#define REG_6318_CONTROL_BASE0x08
> +#define REG_6318_COUNT_BASE 0x18
> +
> +#define NR_TIMERS_6345 4
> +#define WDT_TIMER_ID_6345(NR_TIMERS_6345 - 1)
> +
> +#define NR_TIMERS_6318 5
> +#define WDT_TIMER_ID_6318(NR_TIMERS_6318 - 1)
> +
> +/* Per-timer count register */
> +#define COUNT_MASK (0x3fff)
> +
> +/* Per-timer control register */
> +#define CONTROL_COUNTDOWN_MASK (0x3fff)
> +#define CONTROL_RSTCNTCLR_MASK (1 << 30)
> +#define CONTROL_ENABLE_MASK (1 << 31)
> +
> +enum bcm6345_timer_type {
> + TIMER_TYPE_6345,
> + TIMER_TYPE_6318,
> +};
> +
> +struct bcm6345_timer {
> + raw_spinlock_t lock;
> + void __io
[PATCH (v2) 7/10] watchdog: bcm63xx_wdt: Add get_timeleft function
Return the remaining time from the hardware control register.
Warn when the device is registered if the hardware watchdog is currently
running and report the remaining time left.
Signed-off-by: Simon Arlott
---
Changed "if (timeleft > 0)" to "if (hw->running)" when checking if a
warning should be printed, in case the time left is truncated down to
0 seconds.
drivers/watchdog/bcm63xx_wdt.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 3c7667a..9d099e0 100644
--- a/drivers/watchdog/bcm63xx_wdt.c
+++ b/drivers/watchdog/bcm63xx_wdt.c
@@ -14,6 +14,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include
+#include
#include
#include
#include
@@ -75,6 +76,19 @@ static int bcm63xx_wdt_stop(struct watchdog_device *wdd)
return 0;
}
+static unsigned int bcm63xx_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
+ unsigned long flags;
+ u32 val;
+
+ raw_spin_lock_irqsave(&hw->lock, flags);
+ val = __raw_readl(hw->regs + WDT_CTL_REG);
+ val /= hw->clock_hz;
+ raw_spin_unlock_irqrestore(&hw->lock, flags);
+ return val;
+}
+
static int bcm63xx_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
@@ -130,6 +144,7 @@ static struct watchdog_ops bcm63xx_wdt_ops = {
.owner = THIS_MODULE,
.start = bcm63xx_wdt_start,
.stop = bcm63xx_wdt_stop,
+ .get_timeleft = bcm63xx_wdt_get_timeleft,
.set_timeout = bcm63xx_wdt_set_timeout,
};
@@ -144,6 +159,8 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
struct bcm63xx_wdt_hw *hw;
struct watchdog_device *wdd;
struct resource *r;
+ u32 timeleft1, timeleft2;
+ unsigned int timeleft;
int ret;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
@@ -197,6 +214,23 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
watchdog_init_timeout(wdd, 0, &pdev->dev);
watchdog_set_nowayout(wdd, nowayout);
+ /* Compare two reads of the time left value, 2 clock ticks apart */
+ rmb();
+ timeleft1 = __raw_readl(hw->regs + WDT_CTL_REG);
+ udelay(DIV_ROUND_UP(100, hw->clock_hz / 2));
+ /* Ensure the register is read twice */
+ rmb();
+ timeleft2 = __raw_readl(hw->regs + WDT_CTL_REG);
+
+ /* If the time left is changing, the watchdog is running */
+ if (timeleft1 != timeleft2) {
+ hw->running = true;
+ timeleft = bcm63xx_wdt_get_timeleft(wdd);
+ } else {
+ hw->running = false;
+ timeleft = 0;
+ }
+
ret = bcm63xx_timer_register(TIMER_WDT_ID, bcm63xx_wdt_isr, wdd);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register wdt timer isr\n");
@@ -214,6 +248,8 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
dev_name(wdd->dev), hw->regs,
wdd->timeout, wdd->max_timeout);
+ if (hw->running)
+ dev_alert(wdd->dev, "running, reboot in %us\n", timeleft);
return 0;
unregister_timer:
@@ -255,6 +291,7 @@ module_platform_driver(bcm63xx_wdt_driver);
MODULE_AUTHOR("Miguel Gaio ");
MODULE_AUTHOR("Florian Fainelli ");
+MODULE_AUTHOR("Simon Arlott");
MODULE_DESCRIPTION("Driver for the Broadcom BCM63xx SoC watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bcm63xx-wdt");
--
2.1.4
--
Simon Arlott
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[PATCH (v2) 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk
Instead of using a fixed clock HZ in the driver, obtain it from the
"periph" clk that the watchdog timer uses.
Signed-off-by: Simon Arlott
---
Changed to check for -EPROBE_DEFER before printing an error.
drivers/watchdog/bcm63xx_wdt.c | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 1d2a501..3c7667a 100644
--- a/drivers/watchdog/bcm63xx_wdt.c
+++ b/drivers/watchdog/bcm63xx_wdt.c
@@ -13,6 +13,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include
#include
#include
#include
@@ -32,11 +33,13 @@
#define PFX KBUILD_MODNAME
-#define WDT_HZ 5000/* Fclk */
+#define WDT_CLK_NAME "periph"
struct bcm63xx_wdt_hw {
raw_spinlock_t lock;
void __iomem *regs;
+ struct clk *clk;
+ unsigned long clock_hz;
bool running;
};
@@ -51,7 +54,7 @@ static int bcm63xx_wdt_start(struct watchdog_device *wdd)
unsigned long flags;
raw_spin_lock_irqsave(&hw->lock, flags);
- bcm_writel(wdd->timeout * WDT_HZ, hw->regs + WDT_DEFVAL_REG);
+ bcm_writel(wdd->timeout * hw->clock_hz, hw->regs + WDT_DEFVAL_REG);
bcm_writel(WDT_START_1, hw->regs + WDT_CTL_REG);
bcm_writel(WDT_START_2, hw->regs + WDT_CTL_REG);
hw->running = true;
@@ -116,7 +119,7 @@ static void bcm63xx_wdt_isr(void *data)
die(PFX ": watchdog timer expired\n", get_irq_regs());
}
- ms = timeleft / (WDT_HZ / 1000);
+ ms = timeleft / (hw->clock_hz / 1000);
dev_alert(wdd->dev,
"warning timer fired, reboot in %ums\n", ms);
}
@@ -160,14 +163,32 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
return -ENXIO;
}
+ hw->clk = devm_clk_get(&pdev->dev, WDT_CLK_NAME);
+ if (IS_ERR(hw->clk)) {
+ if (PTR_ERR(hw->clk) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "unable to request clock\n");
+ return PTR_ERR(hw->clk);
+ }
+
+ hw->clock_hz = clk_get_rate(hw->clk);
+ if (!hw->clock_hz) {
+ dev_err(&pdev->dev, "unable to fetch clock rate\n");
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(hw->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_init(&hw->lock);
- hw->running = false;
wdd->parent = &pdev->dev;
wdd->ops = &bcm63xx_wdt_ops;
wdd->info = &bcm63xx_wdt_info;
wdd->min_timeout = 1;
- wdd->max_timeout = 0x / WDT_HZ;
+ wdd->max_timeout = 0x / hw->clock_hz;
wdd->timeout = min(30U, wdd->max_timeout);
watchdog_set_drvdata(wdd, hw);
@@ -179,7 +200,7 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
ret = bcm63xx_timer_register(TIMER_WDT_ID, bcm63xx_wdt_isr, wdd);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register wdt timer isr\n");
- return ret;
+ goto disable_clk;
}
ret = watchdog_register_device(wdd);
@@ -197,15 +218,20 @@ static int bcm63xx_wdt_probe(struct platform_device *pdev)
unregister_timer:
bcm63xx_timer_unregister(TIMER_WDT_ID);
+
+disable_clk:
+ clk_disable_unprepare(hw->clk);
return ret;
}
static int bcm63xx_wdt_remove(struct platform_device *pdev)
{
struct watchdog_device *wdd = platform_get_drvdata(pdev);
+ struct bcm63xx_wdt_hw *hw = watchdog_get_drvdata(wdd);
bcm63xx_timer_unregister(TIMER_WDT_ID);
watchdog_unregister_device(wdd);
+ clk_disable_unprepare(hw->clk);
return 0;
}
--
2.1.4
--
Simon Arlott
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[PATCH (v3) 2/10] MIPS: bmips: Add bcm6345-l2-timer interrupt controller
Add the BCM6345/BCM6318 timer as an interrupt controller so that it can be
used by the watchdog to warn that its timer will expire soon.
Support for clocksource/clockevents is not implemented as the timer
interrupt is not per CPU (except on the BCM6318) and the MIPS clock is
better. This could be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
Fixed the offset of the count registers, they were writing off by one which
caused it to set the watchdog timeout to 0.
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-l2-timer.c | 324 +
3 files changed, 330 insertions(+)
create mode 100644 drivers/irqchip/irq-bcm6345-l2-timer.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index d307bb3..21c3d9b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -70,6 +70,11 @@ config BCM6345_L1_IRQ
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
+config BCM6345_L2_TIMER_IRQ
+ bool
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+
config BCM7038_L1_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ded59cf..2687dea 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_XTENSA_MX) +=
irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_SOC_VF610)+= irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
+obj-$(CONFIG_BCM6345_L2_TIMER_IRQ) += irq-bcm6345-l2-timer.o
obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
diff --git a/drivers/irqchip/irq-bcm6345-l2-timer.c
b/drivers/irqchip/irq-bcm6345-l2-timer.c
new file mode 100644
index 000..4e6f71b
--- /dev/null
+++ b/drivers/irqchip/irq-bcm6345-l2-timer.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Based on arch/mips/bcm63xx/timer.c:
+ * Copyright (C) 2008 Maxime Bizon
+ *
+ * Registers for SoCs with 4 timers: BCM6345, BCM6328, BCM6362, BCM6816,
+ * BCM68220,BCM63168, BCM63268
+ * 0x02: IRQ enable (u8)
+ * 0x03: IRQ status (u8)
+ * 0x04: Timer 0 control
+ * 0x08: Timer 1 control
+ * 0x0c: Timer 2 control
+ * 0x10: Timer 0 count
+ * 0x14: Timer 1 count
+ * 0x18: Timer 2 count
+ * 0x1c+: Watchdog registers
+ *
+ * Registers for SoCs with 5 timers: BCM6318
+ * 0x00: IRQ enable (u32)
+ * 0x04: IRQ status (u32)
+ * 0x08: Timer 0 control
+ * 0x0c: Timer 1 control
+ * 0x10: Timer 2 control
+ * 0x14: Timer 3 control
+ * 0x18: Timer 0 count
+ * 0x1c: Timer 1 count
+ * 0x20: Timer 2 count
+ * 0x24: Timer 3 count
+ * 0x28+: Watchdog registers
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_6345_IRQ_ENABLE0x02
+#define REG_6345_IRQ_STATUS0x03
+#define REG_6345_CONTROL_BASE 0x04
+#define REG_6345_COUNT_BASE0x10
+
+#define REG_6318_IRQ_ENABLE0x00
+#define REG_6318_IRQ_STATUS0x04
+#define REG_6318_CONTROL_BASE 0x08
+#define REG_6318_COUNT_BASE0x18
+
+#define NR_TIMERS_6345 4
+#define WDT_TIMER_ID_6345 (NR_TIMERS_6345 - 1)
+
+#define NR_TIMERS_6318 5
+#define WDT_TIMER_ID_6318 (NR_TIMERS_6318 - 1)
+
+/* Per-timer count register */
+#define COUNT_MASK (0x3fff)
+
+/* Per-timer control register */
+#define CONTROL_COUNTDOWN_MASK (0x3fff)
+#define CONTROL_RSTCNTCLR_MASK (1 << 30)
+#define CONTROL_ENABLE_MASK(1 << 31)
+
+enum bcm6345_timer_type {
+ TIMER_TYPE_6345,
+ TIMER_TYPE_6318,
+};
+
+struct bcm6345_timer {
+ raw_spinlock_t lock;
+ void __iomem *base;
+ unsigned int irq;
+ struct irq_domain *domain;
+
+ enum bcm6345_timer_type type;
+ unsigned int nr_timers;
+ /* The watchdog timer has separate control/remaining registers
+* and cannot be masked.
+*/
+ int wdt_timer_id;
+};
+
+static inline u32
Re: [PATCH 2/3] ARM: bcm2835: add rpi power domain driver
Alexander Aring writes:
> This patch adds support for RPi several Power Domains and enable support
> to enable the USB Power Domain when it's not enabled before.
>
> This patch based on Eric Anholt's patch to support Power Domains. He had
> an issue about -EPROBE_DEFER inside the power domain subsystem, this
> issue was solved by commit <311fa6a> ("PM / Domains: Return -EPROBE_DEFER
> if we fail to init or turn-on domain").
Glad to see you pick this up!
> It was tested with barebox and the following scripts before booting
> linux:
>
> /env/a_off:
>
> # cat /env/a_off
> #turn off which are enabled by default
> regulator -n bcm2835_mci0 -s disable
> regulator -n uart0-pl0110 -s disable
>
> /env/a_on:
>
> # cat /env/a_on
> #turn off which are enabled by default
> regulator -n bcm2835_mci0 -s disable
> regulator -n uart0-pl0110 -s disable
>
> regulator -n bcm2835_mci0 -s enable
> regulator -n uart0-pl0110 -s enable
> regulator -n uart0-pl0111 -s enable
> regulator -n bcm2835_usb -s enable
> regulator -n bcm2835_i2c0 -s enable
> regulator -n bcm2835_i2c1 -s enable
> regulator -n bcm2835_i2c2 -s enable
> regulator -n bcm2835_spi -s enable
> regulator -n bcm2835_ccp2tx -s enable
> regulator -n bcm2835_dsi -s enable
>
> /env/b:
>
> # cat /env/b
> sh /env/a_on
>
> regulator -n bcm2835_mci0 -s disable
> regulator -n uart0-pl0110 -s disable
> regulator -n uart0-pl0111 -s disable
> regulator -n bcm2835_usb -s disable
> regulator -n bcm2835_i2c0 -s disable
> regulator -n bcm2835_i2c1 -s disable
> regulator -n bcm2835_i2c2 -s disable
> regulator -n bcm2835_spi -s disable
> regulator -n bcm2835_ccp2tx -s disable
> regulator -n bcm2835_dsi -s disable
>
> /env/c:
>
> # cat /env/c
> sh ./env/b
>
> regulator -n bcm2835_mci0 -s enable
> regulator -n uart0-pl0110 -s enable
> regulator -n uart0-pl0111 -s enable
> regulator -n bcm2835_usb -s enable
> regulator -n bcm2835_i2c0 -s enable
> regulator -n bcm2835_i2c1 -s enable
> regulator -n bcm2835_i2c2 -s enable
> regulator -n bcm2835_spi -s enable
> regulator -n bcm2835_ccp2tx -s enable
> regulator -n bcm2835_dsi -s enable
>
> These scripts enables/disable all regulators inside the bootloader. It
> was running with a "hard" and "soft" reset without any issues. These
> testcases should fit to Stephen Warren suggestions:
>
> "(a) before having explicitly turned the power domain on or off at all (b)
> after having turned it on (c) after having turned it off, and for all
> power domains."
I would drop this whole block from the commit message. It doesn't seem
worth keeping associated with this code (though thanks for testing it!).
> Cc: Stephen Warren
> Cc: Lee Jones
> Cc: Eric Anholt
> Signed-off-by: Alexander Aring
If I'm going to be credited as an author, we should probably keep my:
Signed-off-by: Eric Anholt
It looks like you've mostly rewritten things, and there's not a whole
lot of meat to this driver so I don't care about getting credit myself,
but best not to give people reasons to be suspicious.
> ---
> arch/arm/boot/dts/bcm2835-rpi.dtsi | 11 ++
> arch/arm/boot/dts/bcm2835.dtsi | 2 +-
> arch/arm/mach-bcm/Kconfig | 10 ++
> arch/arm/mach-bcm/Makefile | 1 +
> arch/arm/mach-bcm/raspberrypi-power.c | 180
>
> include/dt-bindings/arm/raspberrypi-power.h | 14 +++
> 6 files changed, 217 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-bcm/raspberrypi-power.c
> create mode 100644 include/dt-bindings/arm/raspberrypi-power.h
To merge the patch, the .dtsi changes need to be in a separate commit
which I would pick up in the dt branch. I'm hoping Ulf or another PM
domains maintainer would be able to pick up the Kconfig/Makefile/.c
patch in their tree, so it can be queued after the uninit function
change. If they won't, then it would go through my tree, but still on a
different branch from DT changes.
This is the only thing I see needing to change before I can Ack.
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index 8c53c55..20479d7 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -134,6 +134,16 @@ config ARCH_BCM2835
> This enables support for the Broadcom BCM2835 SoC. This SoC is
> used in the Raspberry Pi and Roku 2 devices.
>
> +config RASPBERRYPI_POWER
> + bool "Raspberry Pi power domain driver"
> + depends on ARCH_BCM2835
> + depends on RASPBERRYPI_FIRMWARE
> + select PM_GENERIC_DOMAINS if PM
> + select PM_GENERIC_DOMAINS_OF if PM
> + help
> + This enables support for the RPi power domains which can be enabled
> + or disabled via the RPi firmware.
> +
> config ARCH_BCM_63XX
> bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
> depends on MMU
I'd love to have this be "depends on ARCH_BCM2835 || COMPILE_TEST" --
that gets us better coverage from automated builders in -next.
signatu
[PATCH v3 2/2] DT: watchdog: add Alphascale asm9260 watchdog binding documentation.
Signed-off-by: Oleksij Rempel
---
.../bindings/watchdog/alphascale-asm9260.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt
diff --git a/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt
b/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt
new file mode 100644
index 000..75b265a
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt
@@ -0,0 +1,35 @@
+Alphascale asm9260 Watchdog timer
+
+Required properties:
+
+- compatible : should be "alphascale,asm9260-wdt".
+- reg : Specifies base physical address and size of the registers.
+- clocks : the clocks feeding the watchdog timer. See clock-bindings.txt
+- clock-names : should be set to
+ "mod" - source for tick counter.
+ "ahb" - ahb gate.
+- resets : phandle pointing to the system reset controller with
+ line index for the watchdog.
+- reset-names : should be set to "wdt_rst".
+
+Optional properties:
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+ if unset, the default timeout is 30 seconds.
+- alphascale,mode : three modes are supported
+ "hw" - hw reset (default).
+ "sw" - sw reset.
+ "debug" - no action is taken.
+
+Example:
+
+watchdog0: watchdog@80048000 {
+ compatible = "alphascale,asm9260-wdt";
+ reg = <0x80048000 0x10>;
+ clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>;
+ clock-names = "mod", "ahb";
+ interrupts = <55>;
+ resets = <&rst WDT_RESET>;
+ reset-names = "wdt_rst";
+ timeout-sec = <30>;
+ alphascale,mode = "hw";
+};
--
2.5.0
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[PATCH v3 0/2] add Alphascale asm9260-wdt driver
v2: - fix DT types - remove obsolet comments - add clk error handling - reduce log noise - allow to return an error in asm9260_wdt_get_dt_mode v3: - split patch to two parts, binding documentation and driver - spelling fixes - make reset a required property. It will make the code easier - reduce timeout for asm9260_wdt_sys_reset - rework error handling in asm9260_wdt_get_dt_clks - asm9260_wdt_get_dt_mode - convert return type from int to void - don't touch watchdog_set_nowayout - don't do dev_err() if driver is still working, use dev_warn instead. - asm9260_wdt_remove - use asm9260_wdt_disable() instead of asm9260_wdt_shutdown() Oleksij Rempel (2): watchdog: add Alphascale asm9260-wdt driver DT: watchdog: add Alphascale asm9260 watchdog binding documentation. .../bindings/watchdog/alphascale-asm9260.txt | 35 ++ drivers/watchdog/Kconfig | 10 + drivers/watchdog/Makefile | 1 + drivers/watchdog/asm9260_wdt.c | 400 + 4 files changed, 446 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt create mode 100644 drivers/watchdog/asm9260_wdt.c -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/2] watchdog: add Alphascale asm9260-wdt driver
Add WD support for Alphascale asm9260 SoC. This driver
provide support for different function modes:
- HW mode to trigger SoC reset on timeout
- SW mode do soft reset if needed
- DEBUG mode
Optional support for stopping watchdog. If reset binding are not provided
this driver will work in nowayout mode.
Signed-off-by: Oleksij Rempel
---
drivers/watchdog/Kconfig | 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/asm9260_wdt.c | 400 +
3 files changed, 411 insertions(+)
create mode 100644 drivers/watchdog/asm9260_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c68edc1..9cd9b75 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -173,6 +173,16 @@ config ARM_SP805_WATCHDOG
ARM Primecell SP805 Watchdog timer. This will reboot your system when
the timeout is reached.
+config ASM9260_WATCHDOG
+ tristate "Alphascale ASM9260 watchdog"
+ depends on MACH_ASM9260
+ depends on OF
+ select WATCHDOG_CORE
+ select RESET_CONTROLLER
+ help
+ Watchdog timer embedded into Alphascale asm9260 chips. This will
reboot your
+ system when the timeout is reached.
+
config AT91RM9200_WATCHDOG
tristate "AT91RM9200 watchdog"
depends on SOC_AT91RM9200 && MFD_SYSCON
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0c616e3..bd7b0cd 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
# ARM Architecture
obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
+obj-$(CONFIG_ASM9260_WATCHDOG) += asm9260_wdt.o
obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
obj-$(CONFIG_CADENCE_WATCHDOG) += cadence_wdt.o
diff --git a/drivers/watchdog/asm9260_wdt.c b/drivers/watchdog/asm9260_wdt.c
new file mode 100644
index 000..c8daeff
--- /dev/null
+++ b/drivers/watchdog/asm9260_wdt.c
@@ -0,0 +1,400 @@
+/*
+ * Watchdog driver for Alphascale ASM9260.
+ *
+ * Copyright (c) 2014 Oleksij Rempel
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CLOCK_FREQ 100
+
+/* Watchdog Mode register */
+#define HW_WDMOD 0x00
+/* Wake interrupt. Set by HW, can't be cleared. */
+#define BM_MOD_WDINT BIT(3)
+/* This bit set if timeout reached. Cleared by SW. */
+#define BM_MOD_WDTOF BIT(2)
+/* HW Reset on timeout */
+#define BM_MOD_WDRESET BIT(1)
+/* WD enable */
+#define BM_MOD_WDENBIT(0)
+
+/*
+ * Watchdog Timer Constant register
+ * Minimal value is 0xff, the meaning of this value
+ * depends on used clock: T = WDCLK * (0xff + 1) * 4
+ */
+#define HW_WDTC0x04
+#define BM_WDTC_MAX(freq) (0x7fff / (freq))
+
+/* Watchdog Feed register */
+#define HW_WDFEED 0x08
+
+/* Watchdog Timer Value register */
+#define HW_WDTV0x0c
+
+#define ASM9260_WDT_DEFAULT_TIMEOUT30
+
+enum asm9260_wdt_mode {
+ HW_RESET,
+ SW_RESET,
+ DEBUG,
+};
+
+struct asm9260_wdt_priv {
+ struct device *dev;
+ struct watchdog_device wdd;
+ struct clk *clk;
+ struct clk *clk_ahb;
+ struct reset_control*rst;
+ struct notifier_block restart_handler;
+
+ void __iomem*iobase;
+ int irq;
+ unsigned long wdt_freq;
+ enum asm9260_wdt_mode mode;
+};
+
+static int asm9260_wdt_feed(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+
+ iowrite32(0xaa, priv->iobase + HW_WDFEED);
+ iowrite32(0x55, priv->iobase + HW_WDFEED);
+
+ return 0;
+}
+
+static unsigned int asm9260_wdt_gettimeleft(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 counter;
+
+ counter = ioread32(priv->iobase + HW_WDTV);
+
+ return DIV_ROUND_CLOSEST(counter, priv->wdt_freq);
+}
+
+static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 counter;
+
+ counter = wdd->timeout * priv->wdt_freq;
+
+ iowrite32(counter, priv->iobase + HW_WDTC);
+
+ return 0;
+}
+
+static int asm9260_wdt_enable(struct watchdog_device *wdd)
+{
+ struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
+ u32 mode = 0;
+
+ if (priv->mode == HW_RESET)
+ mode = BM_MOD_WDRESET;
+
+ iowrite32(BM_MOD_WDEN | mode, priv->iobase + HW_WDMOD);
+
+ asm9260_wdt_updatetimeout(wdd);
+
+ asm9260_wdt_feed(wdd);
+
+ return 0;
+}
+
+static int asm
Re: [PATCH 3/3] drm: panel-simple: implement URT UMSH-8596MD-xT panel support
On 08.10.2015 10:24, Thierry Reding wrote: > On Wed, Oct 07, 2015 at 11:02:20PM +0200, Maciej S. Szmigiero wrote: >> This patch implements support for United Radiant Technology >> UMSH-8596MD-xT 7.0" WVGA TFT LCD panels in DRM panel-simple >> driver. >> >> Signed-off-by: Maciej Szmigiero >> --- >> This replaces "drm: panel-simple: add URT UMSH-8596MD-xT panel support" >> submission. >> >> drivers/gpu/drm/panel/panel-simple.c | 54 >> >> 1 file changed, 54 insertions(+) > > Looks good to me. I'll wait for Rob or anyone else to ack the vendor > prefix before merging this. > > Thierry Is anybody there who can ack this prefix? Maciej Szmigiero -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: bcm2835: add rpi power domain driver
Hi, On Tue, Nov 24, 2015 at 09:44:59PM +0100, Ulf Hansson wrote: > [...] > > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig > > index 8c53c55..20479d7 100644 > > --- a/arch/arm/mach-bcm/Kconfig > > +++ b/arch/arm/mach-bcm/Kconfig > > @@ -134,6 +134,16 @@ config ARCH_BCM2835 > > This enables support for the Broadcom BCM2835 SoC. This SoC is > > used in the Raspberry Pi and Roku 2 devices. > > > > +config RASPBERRYPI_POWER > > You don't need a new Kconfig option I think. If you fold in the below > "select" under ARCH_BCM2835, that should work as well, right? > > select PM_GENERIC_DOMAINS if (RASPBERRYPI_FIRMWARE && PM && OF) > I think this depends on what the maintainers like to have here. The raspberrypi firmware isn't BCM2835 specific, when some SoC which is BCM2835 and enabled the RASPBERRYPI_FIRMWARE (for what reason ever) it will enable also the power domain driver for the RPi. When some BCM2835 enable it, then it will do nothing because the devicetree entries should not match then. > > + bool "Raspberry Pi power domain driver" > > + depends on ARCH_BCM2835 > > + depends on RASPBERRYPI_FIRMWARE > > + select PM_GENERIC_DOMAINS if PM > > + select PM_GENERIC_DOMAINS_OF if PM > > + help > > + This enables support for the RPi power domains which can be > > enabled > > + or disabled via the RPi firmware. > > + > > config ARCH_BCM_63XX > > bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 > > depends on MMU > > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile > > index 892261f..fec2d6b 100644 > > --- a/arch/arm/mach-bcm/Makefile > > +++ b/arch/arm/mach-bcm/Makefile > > @@ -36,6 +36,7 @@ endif > > > > # BCM2835 > > obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o > > +obj-$(CONFIG_RASPBERRYPI_POWER)+= raspberrypi-power.o > > According to above, then this should become: > > obj-$(CONFIG_PM_GENERIC_DOMAINS) += raspberrypi-power.o > What about other BCM$FOOBAR arch's which might select/enables CONFIG_PM_GENERIC_DOMAINS somehow? Like ARCH_BCM_63XX. Possible other solution would be to make the CONFIG_RASPBERRYPI_POWER as a hidden entry inside Kconfig without a prompt. Then it should look like this: config RASPBERRYPI_POWER bool select PM_GENERIC_DOMAINS select PM_GENERIC_DOMAINS_OF config ARCH_BCM2835 ... select RASPBERRYPI_POWER if (RASPBERRYPI_FIRMWARE && PM && OF) ... and leave the Makefile as it is. - Alex -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: bcm2835: add rpi power domain driver
[...] > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig > index 8c53c55..20479d7 100644 > --- a/arch/arm/mach-bcm/Kconfig > +++ b/arch/arm/mach-bcm/Kconfig > @@ -134,6 +134,16 @@ config ARCH_BCM2835 > This enables support for the Broadcom BCM2835 SoC. This SoC is > used in the Raspberry Pi and Roku 2 devices. > > +config RASPBERRYPI_POWER You don't need a new Kconfig option I think. If you fold in the below "select" under ARCH_BCM2835, that should work as well, right? select PM_GENERIC_DOMAINS if (RASPBERRYPI_FIRMWARE && PM && OF) > + bool "Raspberry Pi power domain driver" > + depends on ARCH_BCM2835 > + depends on RASPBERRYPI_FIRMWARE > + select PM_GENERIC_DOMAINS if PM > + select PM_GENERIC_DOMAINS_OF if PM > + help > + This enables support for the RPi power domains which can be enabled > + or disabled via the RPi firmware. > + > config ARCH_BCM_63XX > bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 > depends on MMU > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile > index 892261f..fec2d6b 100644 > --- a/arch/arm/mach-bcm/Makefile > +++ b/arch/arm/mach-bcm/Makefile > @@ -36,6 +36,7 @@ endif > > # BCM2835 > obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o > +obj-$(CONFIG_RASPBERRYPI_POWER)+= raspberrypi-power.o According to above, then this should become: obj-$(CONFIG_PM_GENERIC_DOMAINS) += raspberrypi-power.o [...] Kind regards Uffe -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] ARM: dts: vf610: relicense vf???.dtsi under GPLv2/X11
On 11/23/2015 04:57 PM, Stefan Agner wrote: GPLv2-only devicetrees make reuse difficult for software components licensed under a different license. The consensus is that a GPL/X11 dual-license should allow all necessary uses, so relicense the vfxxx.dtsi, vf500.dtsi and vf610.dtsi files to this combination. CCs were acquired using (updated some email addresses): git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi Acked-by: Stephen Warren -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dts/ls2080a: Update PCIe compatible
On Tue, Nov 24, 2015 at 02:04:35PM +0800, Mingkai Hu wrote:
> From: Minghuan Lian
>
> The patch adds LS2085a to PCIe compatible to fix the compatibility
> issue when using firmware with LS2085a compatible property.
>
> Signed-off-by: Minghuan Lian
> Signed-off-by: Mingkai Hu
> ---
> Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 12
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index e376785..467 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -15,6 +15,7 @@ Required properties:
> - compatible: should contain the platform identifier such as:
> "fsl,ls1021a-pcie", "snps,dw-pcie"
> "fsl,ls2080a-pcie", "snps,dw-pcie"
> +"fsl,ls2085a-pcie", "snps,dw-pcie"
> - reg: base addresses and lengths of the PCIe controller
> - interrupts: A list of interrupt outputs of the controller. Must contain an
>entry for each entry in the interrupt-names property.
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index e81cd48..3821bb1 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -383,7 +383,8 @@
> };
>
> pcie@340 {
> - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
> + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
> + "snps,dw-pcie";
This doesn't match the doc as to what are valid combinations. The order
here seems backwards too. ls2085a is older?
> reg = <0x00 0x0340 0x0 0x0010 /* controller
> registers */
> 0x10 0x 0x0 0x2000>; /*
> configuration space */
> reg-names = "regs", "config";
> @@ -406,7 +407,8 @@
> };
>
> pcie@350 {
> - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
> + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
> + "snps,dw-pcie";
> reg = <0x00 0x0350 0x0 0x0010 /* controller
> registers */
> 0x12 0x 0x0 0x2000>; /*
> configuration space */
> reg-names = "regs", "config";
> @@ -429,7 +431,8 @@
> };
>
> pcie@360 {
> - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
> + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
> + "snps,dw-pcie";
> reg = <0x00 0x0360 0x0 0x0010 /* controller
> registers */
> 0x14 0x 0x0 0x2000>; /*
> configuration space */
> reg-names = "regs", "config";
> @@ -452,7 +455,8 @@
> };
>
> pcie@370 {
> - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
> + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
> + "snps,dw-pcie";
> reg = <0x00 0x0370 0x0 0x0010 /* controller
> registers */
> 0x16 0x 0x0 0x2000>; /*
> configuration space */
> reg-names = "regs", "config";
> --
> 2.1.0.27.g96db324
>
> --
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Re: [PATCH 1/3] power: domain: add pm_genpd_uninit
On 19 November 2015 at 19:08, Alexander Aring wrote:
> This patch adds function pm_genpd_uninit for undo a pm_genpd_init. This
> is useful for multiple power domains while probing. If the probing fails
> after one pm_genpd_init was called we need to undo all previous
> registrations of generic pm domains inside the gpd_list list.
>
> There is a check on IS_ERR_OR_NULL(genpd) which is useful to check again
> registered power domains and not registered domains, the driver can use
> this mechanism to have an array with registered and non-registered power
> domains, where non-registered power domains are NULL.
>
> Cc: Rafael J. Wysocki
> Cc: Kevin Hilman
> Cc: Ulf Hansson
> Cc: Pavel Machek
> Cc: Len Brown
> Cc: Greg Kroah-Hartman
> Signed-off-by: Alexander Aring
> ---
> drivers/base/power/domain.c | 22 ++
> include/linux/pm_domain.h | 4
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
> index e03b1ad..24f54b8 100644
> --- a/drivers/base/power/domain.c
> +++ b/drivers/base/power/domain.c
> @@ -1509,6 +1509,28 @@ void pm_genpd_init(struct generic_pm_domain *genpd,
> }
> EXPORT_SYMBOL_GPL(pm_genpd_init);
>
> +/**
> + * pm_genpd_uninit - Uninitialize a generic I/O PM domain object.
> + * @genpd: PM domain object to initialize.
> + */
> +void pm_genpd_uninit(struct generic_pm_domain *genpd)
> +{
> + if (IS_ERR_OR_NULL(genpd))
> + return;
> +
> + /* check if domain is still in registered inside the pm subsystem */
> + WARN_ON_ONCE(!list_empty(&genpd->master_links) ||
> +!list_empty(&genpd->slave_links) ||
> +!list_empty(&genpd->dev_list));
> +
We did discuss about verifying that the genpd mustn't have a
corresponding DT provider. I do realize that it becomes a bit complex
to verify that, unless we decide to add some handle to it within the
genpd struct.
Anyway, perhaps this minimal effort is good enough as is. Especially
since we won't be able to handle the error cases, besides giving a
WARN.
> + mutex_lock(&gpd_list_lock);
> + list_del(&genpd->gpd_list_node);
> + mutex_unlock(&gpd_list_lock);
> +
> + mutex_destroy(&genpd->lock);
> +}
> +EXPORT_SYMBOL_GPL(pm_genpd_uninit);
> +
> #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
> /*
> * Device Tree based PM domain providers.
> diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
> index ba4ced3..df84a45 100644
> --- a/include/linux/pm_domain.h
> +++ b/include/linux/pm_domain.h
> @@ -123,6 +123,7 @@ extern int pm_genpd_remove_subdomain(struct
> generic_pm_domain *genpd,
> struct generic_pm_domain *target);
> extern void pm_genpd_init(struct generic_pm_domain *genpd,
> struct dev_power_governor *gov, bool is_off);
> +extern void pm_genpd_uninit(struct generic_pm_domain *genpd);
>
> extern struct dev_power_governor simple_qos_governor;
> extern struct dev_power_governor pm_domain_always_on_gov;
> @@ -161,6 +162,9 @@ static inline void pm_genpd_init(struct generic_pm_domain
> *genpd,
> struct dev_power_governor *gov, bool is_off)
> {
> }
> +static inline void pm_genpd_uninit(struct generic_pm_domain *genpd)
> +{
> +}
> #endif
>
> static inline int pm_genpd_add_device(struct generic_pm_domain *genpd,
> --
> 2.6.1
>
So, I am fine with this, but let's see if other people have objections.
Acked-by: Ulf Hansson
Kind regards
Uffe
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[PATCH (v6) 2/2] mtd: brcmnand: Add support for the BCM63268
The BCM63268 has a NAND interrupt register with combined status and enable
registers. It also has a clock for the NAND controller that needs to be
enabled.
Set up the device by enabling the clock, disabling and acking all
interrupts, then handle the CTRL_READY interrupt.
Add a brcmnand_get_socdata() function so that bcm63268_nand can obtain its
data and disable the clock when the device is removed.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/Makefile| 1 +
drivers/mtd/nand/brcmnand/bcm63268_nand.c | 179 ++
drivers/mtd/nand/brcmnand/brcmnand.c | 7 ++
drivers/mtd/nand/brcmnand/brcmnand.h | 1 +
4 files changed, 188 insertions(+)
create mode 100644 drivers/mtd/nand/brcmnand/bcm63268_nand.c
diff --git a/drivers/mtd/nand/brcmnand/Makefile
b/drivers/mtd/nand/brcmnand/Makefile
index 3b1fbfd..b83a9ae 100644
--- a/drivers/mtd/nand/brcmnand/Makefile
+++ b/drivers/mtd/nand/brcmnand/Makefile
@@ -2,5 +2,6 @@
# more specific iproc_nand.o, for instance
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= iproc_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= bcm63138_nand.o
+obj-$(CONFIG_MTD_NAND_BRCMNAND)+= bcm63268_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmstb_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand.o
diff --git a/drivers/mtd/nand/brcmnand/bcm63268_nand.c
b/drivers/mtd/nand/brcmnand/bcm63268_nand.c
new file mode 100644
index 000..70ad907
--- /dev/null
+++ b/drivers/mtd/nand/brcmnand/bcm63268_nand.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Derived from bcm63138_nand.c:
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * Derived from
bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
+ * Copyright 2000-2010 Broadcom Corporation
+ *
+ * Derived from
bcm963xx_4.12L.06B_consumer/shared/opensource/flash/nandflash.c:
+ * Copyright 2000-2010 Broadcom Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "brcmnand.h"
+
+struct bcm63268_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *base;
+ struct clk *clk;
+};
+
+#define BCM63268_NAND_INT 0x00
+#define BCM63268_NAND_STATUS_SHIFT0
+#define BCM63268_NAND_STATUS_MASK (0xfff << BCM63268_NAND_STATUS_SHIFT)
+#define BCM63268_NAND_ENABLE_SHIFT16
+#define BCM63268_NAND_ENABLE_MASK (0x << BCM63268_NAND_ENABLE_SHIFT)
+#define BCM63268_NAND_BASE_ADDR0 0x04
+#define BCM63268_NAND_BASE_ADDR1 0x0c
+
+enum {
+ BCM63268_NP_READ= BIT(0),
+ BCM63268_BLOCK_ERASE= BIT(1),
+ BCM63268_COPY_BACK = BIT(2),
+ BCM63268_PAGE_PGM = BIT(3),
+ BCM63268_CTRL_READY = BIT(4),
+ BCM63268_DEV_RBPIN = BIT(5),
+ BCM63268_ECC_ERR_UNC= BIT(6),
+ BCM63268_ECC_ERR_CORR = BIT(7),
+};
+
+static bool bcm63268_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct bcm63268_nand_soc *priv =
+ container_of(soc, struct bcm63268_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63268_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & (BCM63268_CTRL_READY << BCM63268_NAND_STATUS_SHIFT)) {
+ /* Ack interrupt */
+ val &= ~BCM63268_NAND_STATUS_MASK;
+ val |= BCM63268_CTRL_READY << BCM63268_NAND_STATUS_SHIFT;
+ brcmnand_writel(val, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void bcm63268_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct bcm63268_nand_soc *priv =
+ container_of(soc, struct bcm63268_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63268_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ /* Don't ack any interrupts */
+ val &= ~BCM63268_NAND_STATUS_MASK;
+
+ if (en)
+ val |= BCM63268_CTRL_READY << BCM63268_NAND_ENABLE_SHIFT;
+ else
+ val &= ~(BCM63268_CTRL_READY << BCM63268_NAND_ENABLE_SHIFT);
+
+ brcmnand_writel(val, mmio);
+}
+
+static int bcm63268_nand_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct bcm63268_nand_soc *priv;
+ struct brcmnand_soc *soc;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ soc = &priv->soc;
[PATCH (v6) 1/2] mtd: brcmnand: Add brcm,bcm63268-nand device tree binding
Add device tree binding for NAND on the BCM63268.
The BCM63268 has a NAND interrupt register with combined status and enable
registers.
Signed-off-by: Simon Arlott
---
.../devicetree/bindings/mtd/brcm,brcmnand.txt | 35 ++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
index 4ff7128..f2a71c8 100644
--- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
+++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
@@ -72,6 +72,14 @@ we define additional 'compatible' properties and associated
register resources w
and enable registers
- reg-names: (required) "nand-int-base"
+ * "brcm,nand-bcm63268"
+ - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm63268"
+ - reg: (required) the 'NAND_INTR_BASE' register range, with combined
status
+ and enable registers, and boot address registers
+ - reg-names: (required) "nand-intr-base"
+ - clock: (required) reference to the clock for the NAND controller
+ - clock-names: (required) "nand"
+
* "brcm,nand-iproc"
- reg: (required) the "IDM" register range, for interrupt enable and APB
bus access endianness configuration, and the "EXT" register range,
@@ -148,3 +156,30 @@ nand@f0442800 {
};
};
};
+
+nand@1200 {
+ compatible = "brcm,nand-bcm63168", "brcm,nand-bcm63268",
+ "brcm,brcmnand-v4.0", "brcm,brcmnand";
+ reg = <0x1200 0x180>,
+ <0x1600 0x200>,
+ <0x10b0 0x10>;
+ reg-names = "nand", "nand-cache", "nand-intr-base";
+ interrupt-parent = <&periph_intc>;
+ interrupts = <50>;
+ clocks = <&periph_clk 20>;
+ clock-names = "nand";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand0: nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <1>;
+ nand-ecc-step-size = <512>;
+
+ #address-cells = <0>;
+ #size-cells = <0>;
+ };
+};
--
2.1.4
--
Simon Arlott
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Re: [PATCH] dmaengine: usb-dmac: Document SoC specific bindings
On Tue, Nov 24, 2015 at 11:20:41AM +0900, Simon Horman wrote:
> In general Renesas hardware is not documented to the extent where the
> relationship between IP blocks on different SoCs can be assumed although
> they may appear to operate the same way. Furthermore the documentation
> typically does not specify a version for individual IP blocks. For these
> reasons a convention of using the SoC name in place of a version and
> providing SoC-specific compat strings has been adopted.
>
> Although not universally liked this convention is used in the bindings for
> most drivers for Renesas hardware. The purpose of this patch is to
> update the Renesas USB DMA Controller driver to follow this convention.
>
> Cc: devicetree@vger.kernel.org
> Cc: Yoshihiro Shimoda
> Signed-off-by: Simon Horman
>
> ---
> * r8a7792 (R-Car V2H) is omitted as my reading of the documentation
> is that Renesas USB-DMAC does not exist on that SoC
> * r8a7795 (R-Car H2) is omitted as its unclear to me on the compatibility
> of USB-DMAC that SoC
>
> * Once this has been merged I intend to provide follow-up patches
> to use these new compat strings in the relevant dtsi files.
> ---
> Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> index 040f365954cc..3bb624e10615 100644
> --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
> @@ -1,7 +1,12 @@
> * Renesas USB DMA Controller Device Tree bindings
>
> Required Properties:
> -- compatible: must contain "renesas,usb-dmac"
> +- compatible: "renesas,usb-dmac-", "renesas,usb-dmac" as fallback.
> + Examples with soctypes are:
> + - "renesas,usb-dmac-r8a7790" (R-Car H2)
> + - "renesas,usb-dmac-r8a7791" (R-Car M2-W)
> + - "renesas,usb-dmac-r8a7793" (R-Car M2-N)
> + - "renesas,usb-dmac-r8a7794" (R-Car E2)
Weren't you changing the order of SoC and block names on new bindings?
Either way:
Acked-by: Rob Herring
Rob
> - reg: base address and length of the registers block for the DMAC
> - interrupts: interrupt specifiers for the DMAC, one for each entry in
>interrupt-names.
> @@ -15,7 +20,7 @@ Required Properties:
> Example: R8A7790 (R-Car H2) USB-DMACs
>
> usb_dmac0: dma-controller@e65a {
> - compatible = "renesas,usb-dmac";
> + compatible = "renesas,usb-dmac-r8a7790", "renesas,usb-dmac";
> reg = <0 0xe65a 0 0x100>;
> interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
> 0 109 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.1.4
>
> --
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Re: [alsa-devel] [PATCH 4/4] sound: codecs: pcm1792a: introduce channel side
Hi
On Tue, Nov 24, 2015 at 5:04 PM, Raphaël Poggi wrote:
> Hi,
>
> 2015-11-24 9:27 GMT+01:00 Michael Trimarchi :
>> Hi
>>
>> On Tue, Nov 24, 2015 at 9:21 AM, Raphaël Poggi wrote:
>>> Hi,
>>>
>>> 2015-11-21 10:37 GMT+01:00 Michael Trimarchi :
Hi
On Fri, Nov 20, 2015 at 11:09 AM, Raphael Poggi
wrote:
> From: Raphael Poggi
>
> Add possibility to choose the channel side using the device tree,
> and also modify it using alsa ctrl.
>
> Signed-off-by: Raphael Poggi
> ---
> sound/soc/codecs/pcm1792a.c | 46
> +
> 1 file changed, 46 insertions(+)
>
> diff --git a/sound/soc/codecs/pcm1792a.c b/sound/soc/codecs/pcm1792a.c
> index febaa48..005b679 100644
> --- a/sound/soc/codecs/pcm1792a.c
> +++ b/sound/soc/codecs/pcm1792a.c
> @@ -65,6 +65,12 @@ static const struct reg_default
> pcm1792a_reg_defaults[] = {
> { PCM1792A_DEVICE_ID, 0x00 },
> };
>
> +enum __pcm1792_side {
> + STEREO,
> + MONORAL_LEFT,
> + MONORAL_RIGHT
> +};
> +
> static bool pcm1792a_accessible_reg(struct device *dev, unsigned int reg)
> {
> return reg >= 0x10 && reg <= 0x17;
> @@ -83,6 +89,7 @@ struct pcm1792a_private {
> struct regmap *regmap;
> unsigned int format;
> unsigned int rate;
> + unsigned int side;
> };
>
> static int pcm1792a_set_dai_fmt(struct snd_soc_dai *codec_dai,
> @@ -153,6 +160,13 @@ static int pcm1792a_hw_params(struct
> snd_pcm_substream *substream,
> ret = regmap_update_bits(priv->regmap, PCM1792A_FMT_CONTROL,
> PCM1792A_FMT_MASK |
> PCM1792A_ATLD_ENABLE, val);
>
> + if (priv->side == MONORAL_LEFT)
> + val = PCM1792A_CHANNEL_MONO_LEFT;
> + else if (priv->side == MONORAL_RIGHT)
> + val = PCM1792A_CHANNEL_MONO_RIGHT;
> +
> + regmap_update_bits(priv->regmap, PCM1792A_CHANNEL,
> PCM1792A_CHANNEL_MONO_MASK, val);
> +
> return ret;
> }
>
> @@ -222,10 +236,31 @@ static struct snd_soc_codec_driver
> soc_codec_dev_pcm1792a = {
> .num_dapm_routes= ARRAY_SIZE(pcm1792a_dapm_routes),
> };
>
> +static int pcm1792a_of_init(struct spi_device *spi)
> +{
> + int ret = 0;
> + struct pcm1792a_private *pcm1792a = dev_get_drvdata(&spi->dev);
> + const char *name;
> + struct device_node *np = spi->dev.of_node;
> +
> + name = of_get_property(np, "ti,side", NULL);
> + if (name) {
> + if (!strcmp(name, "left"))
> + pcm1792a->side = MONORAL_LEFT;
> + else
> + pcm1792a->side = MONORAL_RIGHT;
> + }
> + else
> + pcm1792a->side = STEREO;
> +
> + return ret;
> +}
> +
> static int pcm1792a_spi_probe(struct spi_device *spi)
> {
> struct pcm1792a_private *pcm1792a;
> int ret;
> + struct device_node *np = spi->dev.of_node;
>
> pcm1792a = devm_kzalloc(&spi->dev, sizeof(struct
> pcm1792a_private),
> GFP_KERNEL);
> @@ -241,6 +276,17 @@ static int pcm1792a_spi_probe(struct spi_device *spi)
> return ret;
> }
>
> + if (np) {
> + ret = pcm1792a_of_init(spi);
> + if (ret)
> + return ret;
> + }
> +
> + if (pcm1792a->side == MONORAL_LEFT)
> + regmap_update_bits(pcm1792a->regmap, PCM1792A_CHANNEL,
> PCM1792A_CHANNEL_MONO_MASK, PCM1792A_CHANNEL_MONO_LEFT);
> + else if (pcm1792a->side == MONORAL_RIGHT)
> + regmap_update_bits(pcm1792a->regmap, PCM1792A_CHANNEL,
> PCM1792A_CHANNEL_MONO_MASK, PCM1792A_CHANNEL_MONO_RIGHT);
> +
Why this is a part of dts and not a part of mixer control?
Michael
>>>
>>> The "channel side" bindings should be used when the pcm7192a is used
>>> in monaural mode (which requires two DACs, both DACs operate in a
>>> balanced mode for one channel of audio input data).
>>> This is a hardware level design, it will never change at runtime.
>>> I feel that a device tree binding is more appropriate than a control.
>>>
If you put this in mixer control then you can avoid to have it in dts
because you not suppose to
boot playing music. Basically you can get the same result restore some
alsa config that match
your topology. Even if you have two mono amplifier you can have the
situation that you want to
invert channel left and right and this can be done easily just
reconfigure one as mono left and the other
as mono right or write your own sound card
Re: [PATCH v4] mmc: OCTEON: Add host driver for OCTEON MMC controller
On 11/20/2015 09:32 AM, Aaro Koskinen wrote: Hi, On Mon, May 18, 2015 at 02:40:44PM -0700, Aleksey Makarov wrote: On 05/18/2015 02:05 PM, Aaro Koskinen wrote: On Mon, Mar 16, 2015 at 06:06:00PM +0300, Aleksey Makarov wrote: The OCTEON MMC controller is currently found on cn61XX and cnf71XX devices. Device parameters are configured from device tree data. eMMC, MMC and SD devices are supported. Tested-by: Aaro Koskinen Signed-off-by: Chandrakala Chavva Signed-off-by: David Daney Signed-off-by: Aleksey Makarov Signed-off-by: Leonid Rosenboim Signed-off-by: Peter Swain Signed-off-by: Aaron Williams --- Any updates on this patch? Are you still working on it for the mainline kernel inclusion? We are working on it. It will also be used in ARM ThunderX arch. So we will send a new version soon. Any updates? Also distros are waiting for this patch, MMC is the main medium on some boards: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=800594 I am aware of the need, but haven't been able to find the time to work on the MMC patch. David Daney A. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: vf6xx: Cosmic+: M4(nommu) initial support
On 2015-11-23 19:26, Shawn Guo wrote:
> On Sun, Oct 25, 2015 at 11:20:56PM +0530, Afzal Mohammed wrote:
>> Minimal Cortex-M4 device tree to boot Linux to shell. M4 is booted via
>> Cortex-A5 running Linux using Stefan Agner's "m4boot"
>> utility.
>>
>> Signed-off-by: Afzal Mohammed
>
> Stefan,
>
> Are you okay with this patch?
Looks good to me:
Acked-by: Stefan Agner
--
Stefan
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/vf610m4-cosmic.dts | 90
>>
>> 2 files changed, 91 insertions(+)
>> create mode 100644 arch/arm/boot/dts/vf610m4-cosmic.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index bb8fa023d574..06a1a7a1d104 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -347,6 +347,7 @@ dtb-$(CONFIG_SOC_VF610) += \
>> vf610-colibri-eval-v3.dtb \
>> vf610m4-colibri.dtb \
>> vf610-cosmic.dtb \
>> +vf610m4-cosmic.dtb \
>> vf610-twr.dtb
>> dtb-$(CONFIG_ARCH_MXS) += \
>> imx23-evk.dtb \
>> diff --git a/arch/arm/boot/dts/vf610m4-cosmic.dts
>> b/arch/arm/boot/dts/vf610m4-cosmic.dts
>> new file mode 100644
>> index ..8944a2d2054c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/vf610m4-cosmic.dts
>> @@ -0,0 +1,90 @@
>> +/*
>> + * Device tree for Cosmic+ VF6xx Cortex-M4 support
>> + *
>> + * Copyright (C) 2015
>> + *
>> + * Based on vf610m4 Colibri
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +#include "vf610m4.dtsi"
>> +
>> +/ {
>> +model = "VF610 Cortex-M4";
>> +compatible = "fsl,vf610m4";
>> +};
>> +
>> +&gpio0 {
>> +status = "disabled";
>> +};
>> +
>> +&gpio1 {
>> +status = "disabled";
>> +};
>> +
>> +&gpio2 {
>> +status = "disabled";
>> +};
>> +
>> +&gpio3 {
>> +status = "disabled";
>> +};
>> +
>> +&gpio4 {
>> +status = "disabled";
>> +};
>> +
>> +&uart3 {
>> +pinctrl-names = "default";
>> +pinctrl-0 = <&pinctrl_uart3>;
>> +status = "okay";
>> +};
>> +
>> +&iomuxc {
>> +vf610-cosmic {
>> +pinctrl_uart3: uart3grp {
>> +fsl,pins = <
>> +VF610_PAD_PTA20__UART3_TX 0x21a2
>> +VF610_PAD_PTA21__UART3_RX 0x21a1
>> +>;
>> +};
>> +};
>> +};
>> --
>> 2.5.1
>>
>>
>> ___
>> linux-arm-kernel mailing list
>> linux-arm-ker...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
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Re: [PATCH (v4) 2/2] mtd: brcmnand: Add support for the BCM63268
On 24/11/15 00:12, Simon Arlott wrote: > On 23/11/15 18:22, Florian Fainelli wrote: >> On 22/11/15 14:17, Simon Arlott wrote: >>> The BCM63268 has a NAND interrupt register with combined status and enable >>> registers. It also has a clock for the NAND controller that needs to be >>> enabled. >>> >>> Set up the device by enabling the clock, disabling and acking all >>> interrupts, then handle the CTRL_READY interrupt. >>> >>> Add a "device_remove" function to struct brcmnand_soc so that the clock >>> can be disabled when the device is removed. >>> >>> Signed-off-by: Simon Arlott >>> --- >>> On 22/11/15 21:59, Rob Herring wrote: >>> + * "brcm,nand-bcm63268" >>> + - compatible: should contain "brcm,nand-bcm", >>> "brcm,nand-bcm63268" > > vendor,-device is preferred. >>> >>> The existing two bindings use brcm,nand-, but I've changed this one. >> >> Could we stick with the existing binding naming convention of using: >> >> brcm,nand- just so automated tools or other things can match this >> one too, and +1 for consistency? > > I could submit another patch renaming the existing bindings to > brcm,-nand, and add that to the drivers? Then they'd be consistent. No, let's not create unnecessary churn because of a minor mistake. So, yes we *should* have used brcm,-nand in the first place, but now that there are DTSes out there using "brcm,nand-" there is not really any point in doing this, so please update your patches so they match the existing convention. > >> Other than, that, same comment as Jonas, why do we we need the >> device_remove callback to be called from the main driver down to this one? > > I'll add a "struct brcmnand_soc *brcmnand_get_socdata(struct device *)" > instead so that I can access the soc data before calling brcmnand_remove. > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/10] watchdog: bcm63xx_wdt: Handle hardware interrupt and remove software timer
On Sun, Nov 22, 2015 at 02:05:16PM +, Simon Arlott wrote:
> There is a level triggered interrupt for the watchdog timer as part of
> the bcm63xx_timer device. The interrupt occurs when the hardware watchdog
> timer reaches 50% of the remaining time.
>
> It is not possible to mask the interrupt within the bcm63xx_timer device.
> To get around this limitation, handle the interrupt by restarting the
> watchdog with the current remaining time (which will be half the previous
> timeout) so that the interrupt occurs again at 1/4th, 1/8th, etc. of the
> original timeout value until the watchdog forces a reboot.
>
> The software timer was restarting the hardware watchdog with a 85 second
> timeout until the software timer expired, and then causing a panic()
> about 42.5 seconds later when the hardware interrupt occurred. The
> hardware watchdog would not reboot until a further 42.5 seconds had
> passed.
>
> Remove the software timer and rely on the hardware timer directly,
> reducing the maximum timeout from 256 seconds to 85 seconds
> (2^32 / WDT_HZ).
>
Florian,
can you have a look into this patch and confirm that there is no better
way to clear the interrupt status ?
Thanks,
Guenter
> Signed-off-by: Simon Arlott
> ---
> drivers/watchdog/bcm63xx_wdt.c | 124
> -
> 1 file changed, 72 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
> index ab26fd9..f88fc97 100644
> --- a/drivers/watchdog/bcm63xx_wdt.c
> +++ b/drivers/watchdog/bcm63xx_wdt.c
> @@ -3,6 +3,7 @@
> *
> * Copyright (C) 2007, Miguel Gaio
> * Copyright (C) 2008, Florian Fainelli
> + * Copyright 2015 Simon Arlott
> *
> * This program is free software; you can redistribute it and/or
> * modify it under the terms of the GNU General Public License
> @@ -20,11 +21,10 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> -#include
> -#include
> #include
> #include
> #include
> @@ -37,16 +37,17 @@
>
> #define PFX KBUILD_MODNAME
>
> -#define WDT_HZ 5000 /* Fclk */
> -#define WDT_DEFAULT_TIME 30 /* seconds */
> -#define WDT_MAX_TIME 256 /* seconds */
> +#define WDT_HZ 5000/* Fclk */
> +#define WDT_DEFAULT_TIME 30 /* seconds */
> +#define WDT_MAX_TIME (0x / WDT_HZ) /* seconds */
>
> -static struct {
> +struct bcm63xx_wdt_hw {
> + raw_spinlock_t lock;
> void __iomem *regs;
> - struct timer_list timer;
> unsigned long inuse;
> - atomic_t ticks;
> -} bcm63xx_wdt_device;
> + bool running;
> +};
> +static struct bcm63xx_wdt_hw bcm63xx_wdt_device;
>
> static int expect_close;
>
> @@ -59,48 +60,67 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped
> once started (default="
> /* HW functions */
> static void bcm63xx_wdt_hw_start(void)
> {
> - bcm_writel(0xfffe, bcm63xx_wdt_device.regs + WDT_DEFVAL_REG);
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&bcm63xx_wdt_device.lock, flags);
> + bcm_writel(wdt_time * WDT_HZ, bcm63xx_wdt_device.regs + WDT_DEFVAL_REG);
> bcm_writel(WDT_START_1, bcm63xx_wdt_device.regs + WDT_CTL_REG);
> bcm_writel(WDT_START_2, bcm63xx_wdt_device.regs + WDT_CTL_REG);
> + bcm63xx_wdt_device.running = true;
> + raw_spin_unlock_irqrestore(&bcm63xx_wdt_device.lock, flags);
> }
>
> static void bcm63xx_wdt_hw_stop(void)
> {
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&bcm63xx_wdt_device.lock, flags);
> bcm_writel(WDT_STOP_1, bcm63xx_wdt_device.regs + WDT_CTL_REG);
> bcm_writel(WDT_STOP_2, bcm63xx_wdt_device.regs + WDT_CTL_REG);
> + bcm63xx_wdt_device.running = false;
> + raw_spin_unlock_irqrestore(&bcm63xx_wdt_device.lock, flags);
> }
>
> +/* The watchdog interrupt occurs when half the timeout is remaining */
> static void bcm63xx_wdt_isr(void *data)
> {
> - struct pt_regs *regs = get_irq_regs();
> -
> - die(PFX " fire", regs);
> -}
> -
> -static void bcm63xx_timer_tick(unsigned long unused)
> -{
> - if (!atomic_dec_and_test(&bcm63xx_wdt_device.ticks)) {
> - bcm63xx_wdt_hw_start();
> - mod_timer(&bcm63xx_wdt_device.timer, jiffies + HZ);
> - } else
> - pr_crit("watchdog will restart system\n");
> -}
> -
> -static void bcm63xx_wdt_pet(void)
> -{
> - atomic_set(&bcm63xx_wdt_device.ticks, wdt_time);
> -}
> -
> -static void bcm63xx_wdt_start(void)
> -{
> - bcm63xx_wdt_pet();
> - bcm63xx_timer_tick(0);
> -}
> + struct bcm63xx_wdt_hw *hw = &bcm63xx_wdt_device;
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&hw->lock, flags);
> + if (!hw->running) {
> + /* Stop the watchdog as it shouldn't be running */
> + bcm_writel(WDT_STOP_1, hw->regs + WDT_CTL_REG);
> + bcm_writel(WDT_STOP_2, hw->regs + WD
[PATCH (v5) 2/2] mtd: brcmnand: Add support for the BCM63268
The BCM63268 has a NAND interrupt register with combined status and enable
registers. It also has a clock for the NAND controller that needs to be
enabled.
Set up the device by enabling the clock, disabling and acking all
interrupts, then handle the CTRL_READY interrupt.
Add a brcmnand_get_socdata() function so that bcm63268_nand can obtain its
data and disable the clock when the device is removed.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/Makefile| 1 +
drivers/mtd/nand/brcmnand/bcm63268_nand.c | 179 ++
drivers/mtd/nand/brcmnand/brcmnand.c | 7 ++
drivers/mtd/nand/brcmnand/brcmnand.h | 1 +
4 files changed, 188 insertions(+)
create mode 100644 drivers/mtd/nand/brcmnand/bcm63268_nand.c
diff --git a/drivers/mtd/nand/brcmnand/Makefile
b/drivers/mtd/nand/brcmnand/Makefile
index 3b1fbfd..b83a9ae 100644
--- a/drivers/mtd/nand/brcmnand/Makefile
+++ b/drivers/mtd/nand/brcmnand/Makefile
@@ -2,5 +2,6 @@
# more specific iproc_nand.o, for instance
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= iproc_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= bcm63138_nand.o
+obj-$(CONFIG_MTD_NAND_BRCMNAND)+= bcm63268_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmstb_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand.o
diff --git a/drivers/mtd/nand/brcmnand/bcm63268_nand.c
b/drivers/mtd/nand/brcmnand/bcm63268_nand.c
new file mode 100644
index 000..91d8e4d
--- /dev/null
+++ b/drivers/mtd/nand/brcmnand/bcm63268_nand.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Derived from bcm63138_nand.c:
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * Derived from
bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
+ * Copyright 2000-2010 Broadcom Corporation
+ *
+ * Derived from
bcm963xx_4.12L.06B_consumer/shared/opensource/flash/nandflash.c:
+ * Copyright 2000-2010 Broadcom Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "brcmnand.h"
+
+struct bcm63268_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *base;
+ struct clk *clk;
+};
+
+#define BCM63268_NAND_INT 0x00
+#define BCM63268_NAND_STATUS_SHIFT0
+#define BCM63268_NAND_STATUS_MASK (0xfff << BCM63268_NAND_STATUS_SHIFT)
+#define BCM63268_NAND_ENABLE_SHIFT16
+#define BCM63268_NAND_ENABLE_MASK (0x << BCM63268_NAND_ENABLE_SHIFT)
+#define BCM63268_NAND_BASE_ADDR0 0x04
+#define BCM63268_NAND_BASE_ADDR1 0x0c
+
+enum {
+ BCM63268_NP_READ= BIT(0),
+ BCM63268_BLOCK_ERASE= BIT(1),
+ BCM63268_COPY_BACK = BIT(2),
+ BCM63268_PAGE_PGM = BIT(3),
+ BCM63268_CTRL_READY = BIT(4),
+ BCM63268_DEV_RBPIN = BIT(5),
+ BCM63268_ECC_ERR_UNC= BIT(6),
+ BCM63268_ECC_ERR_CORR = BIT(7),
+};
+
+static bool bcm63268_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct bcm63268_nand_soc *priv =
+ container_of(soc, struct bcm63268_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63268_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & (BCM63268_CTRL_READY << BCM63268_NAND_STATUS_SHIFT)) {
+ /* Ack interrupt */
+ val &= ~BCM63268_NAND_STATUS_MASK;
+ val |= BCM63268_CTRL_READY << BCM63268_NAND_STATUS_SHIFT;
+ brcmnand_writel(val, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void bcm63268_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct bcm63268_nand_soc *priv =
+ container_of(soc, struct bcm63268_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63268_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ /* Don't ack any interrupts */
+ val &= ~BCM63268_NAND_STATUS_MASK;
+
+ if (en)
+ val |= BCM63268_CTRL_READY << BCM63268_NAND_ENABLE_SHIFT;
+ else
+ val &= ~(BCM63268_CTRL_READY << BCM63268_NAND_ENABLE_SHIFT);
+
+ brcmnand_writel(val, mmio);
+}
+
+static int bcm63268_nand_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct bcm63268_nand_soc *priv;
+ struct brcmnand_soc *soc;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ soc = &priv->soc;
Re: [Qemu-devel] [PATCH v5 1/4] firmware: introduce sysfs driver for QEMU's fw_cfg device
On Tue, Nov 24, 2015 at 10:38:18AM -0700, Eric Blake wrote: > On 11/24/2015 09:55 AM, Gabriel L. Somlo wrote: > > On Tue, Nov 24, 2015 at 04:14:50AM +0800, kbuild test robot wrote: > > >> > >>drivers/firmware/qemu_fw_cfg.c: In function 'fw_cfg_cmdline_set': > drivers/firmware/qemu_fw_cfg.c:510:7: warning: format '%lli' expects > argument of type 'long long int *', but argument 3 has type 'phys_addr_t > *' [-Wformat=] > >> &ctrl_off, &data_off, &consumed); > >> ^ > > > > Oh, I think I know why this happened: > > > > > > > So, I could use u64 instead of phys_addr_t and resource_size_t, and > > keep "%lli" (or "%Li"), but then I'd have to check if the parsed value > > %Li is not POSIX. Don't use it (stick with %lli). > > > would overflow a 32-bit address value on arches where phys_addr_t is > > u32, which would make things a bit more messy and awkward. > > > > I'm planning on #ifdef-ing the format string instead: > > > > #ifdef CONFIG_PHYS_ADDR_T_64BIT > > #define PH_ADDR_SCAN_FMT "@%Li%n:%Li:%Li%n" > > #else > > #define PH_ADDR_SCAN_FMT "@%li%n:%li:%li%n" > > #endif > > A more typical approach is akin to ; have PH_ADDR_FMT > defined to either "lli" or "li", then write sscanf(str, "@%"PH_ADDR_FMT > "%n:..., ...), using PH_ADDR_FMT multiple times. That sounds almost like it should be a separate patch against include/linux/types.h: diff --git a/include/linux/types.h b/include/linux/types.h index 70d8500..35be16e 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -160,8 +160,10 @@ typedef unsigned __bitwise__ oom_flags_t; #ifdef CONFIG_PHYS_ADDR_T_64BIT typedef u64 phys_addr_t; +#define __PHYS_ADDR_PREFIX "ll" #else typedef u32 phys_addr_t; +#define __PHYS_ADDR_PREFIX "l" #endif typedef phys_addr_t resource_size_t; But whether it's a good idea for me to detour from fw_cfg/sysfs into sorting this out with the kernel community right now, I don't know :) I'll just try to do it inside the fw_cfg sysfs driver for now, see how that goes... > > > ... > > processed = sscanf(str, PH_ADDR_SCAN_FMT, > >&base, &consumed, > >&ctrl_off, &data_off, &consumed); > > Umm, why are you passing &consumed to more than one sscanf() %? That's > (probably) undefined behavior. Input might end after reading 'base', in which case %n would store the next character's index in consumed, and evaluate (but otherwise ignore) the remaining pointer arguments (including the second &consumed). Or, it might end after reading data_off, then the earlier value of consumed gets overwritten with the new (past data_off) index. I get to verify that str[index] is '\0', i.e. that there were no left-over, unprocessed characters, whether I got one or three items processed by scanf. I don't think passing '&consumed' in twice is a problem. I also didn't cleverly come up with this myself, but rather lifted it from drivers/virtio/virtio_mmio.c, so at least there's precedent :) > [In general, sscanf() is a horrid interface to use for parsing integers > - it has undefined behavior if the input text would trigger integer > overflow, making it safe to use ONLY on text that you control and can > guarantee won't overflow. By the time you've figured out if untrusted > text meets the requirement for safe parsing via sscanf(), you've > practically already parsed it via safer strtol() and friends.] Just like (I think) is the case with virtio_mmio, this is an optional feature to allow specifying a base address, range, and register offsets for fw_cfg via the insmod (or modprobe) command line, so one would already have to be root. Also, perfectly well-formated base and size values could be used to hose the system, which is why virtio_mmio (and also fw_cfg) leave this feature off by default, and recommend caution before one would turn it on. Thanks much, --Gabriel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] spi: mediatek: revise mtk_spi_probe() failure flow
On 24/11/15 03:38, Leilk Liu wrote:
This patch revises failure flow while pm_runtime_enable().
Please write a proper commit message explaining what this patch does.
Signed-off-by: Leilk Liu
---
drivers/spi/spi-mt65xx.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 6c1a96e..00a36da 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -607,7 +607,8 @@ static int mtk_spi_probe(struct platform_device *pdev)
ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
- goto err_disable_clk;
+ clk_disable_unprepare(mdata->spi_clk);
+ goto err_put_master;
}
clk_disable_unprepare(mdata->spi_clk);
@@ -617,7 +618,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
ret = devm_spi_register_master(&pdev->dev, master);
if (ret) {
dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
- goto err_put_master;
+ goto err_disable_runtime_pm;
}
if (mdata->dev_comp->need_pad_sel) {
@@ -626,14 +627,14 @@ static int mtk_spi_probe(struct platform_device *pdev)
"pad_num does not match num_chipselect(%d !=
%d)\n",
mdata->pad_num, master->num_chipselect);
ret = -EINVAL;
- goto err_put_master;
+ goto err_disable_runtime_pm;
}
if (!master->cs_gpios && master->num_chipselect > 1) {
dev_err(&pdev->dev,
"cs_gpios not specified and num_chipselect >
1\n");
ret = -EINVAL;
- goto err_put_master;
+ goto err_disable_runtime_pm;
}
if (master->cs_gpios) {
@@ -644,7 +645,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev,
"can't get CS GPIO %i\n", i);
- goto err_put_master;
+ goto err_disable_runtime_pm;
}
}
}
@@ -652,8 +653,8 @@ static int mtk_spi_probe(struct platform_device *pdev)
return 0;
-err_disable_clk:
- clk_disable_unprepare(mdata->spi_clk);
+err_disable_runtime_pm:
+ pm_runtime_disable(&pdev->dev);
err_put_master:
spi_master_put(master);
--
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Re: [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver
Hi,
> >> +UniPhier System Bus Controller
> >> +--
> >> +
> >> +The UniPhier System Bus Controller is a hardware block with registers that
> >> +controls the System Bus accessing; how each bank is mapped onto the
> >> parent bus,
> >> +various timing parameters of the bus access, etc.
> >> +
> >> +Required properties for System Bus Controller:
> >> +- compatible: should be "socionext,uniphier-system-bus-controller".
> >> +- reg: offsets and lengths of the register sets for the device. It should
> >> + contain 2 regions: base & control register, misc register, in this
> >> order.
> >
> > The example also has a system-bus phandle.
>
> Actually, I was wondering which is better to describe the relation between
> the bus and the controller, phandle or compatible string..
To describe relationships between nodes, use phandles.
Compatible strings alone cannot define relationships -- you cannot
encode how multiple instances are related.
> > Is the "misc register" part of the bus controller, or is it a shared
> > system controller?
>
> It is a part of the bus controller, but used for another purpose.
> (i.e. partly this is syscon. I know this is strange, but it is
> what the hardware developers designed.)
Ok. What else is going to need to use this in future?
> > Assuming that the controller and bus are 1-1 related, make this a single
> > node. e.g.
> >
> > system-bus {
> > compatible = "socionext,uniphier-system-bus";
> > reg = <0x58c0 0x400>, <0x5980 0x2000>;
> > #address-cells = <2>;
> > #size-cells = <1>;
> > ranges = <1 0x 0x4200 0x0200>,
> > <5 0x 0x4800 0x0100>;
> >
> > ...
> > child nodes here
> > ...
> >
> > };
>
> Hmm, make sense. But, I prefer to reflect the hardware structure.
>
> The range of System Bus is <0x4000 0x1000>.
>
> The register of the System Bus Controller is
> <0x58c0 0x400> (and <0x5980 0x2000>)
>
>
> The bus and its controller is different.
So? We always describe the programming interface (i.e. the slave
interface of the device that responds to the CPU).
There's no need for separate nodes. It only makes the driver more
complicated.
> >> +static int uniphier_sbc_probe(struct platform_device *pdev)
> >> +{
> >> + struct device *dev = &pdev->dev;
> >> + struct uniphier_sbc_priv *priv;
> >> + struct resource *regs;
> >> + struct device_node *bus_np;
> >> + int child_addrc, addrc, sizec, bank;
> >> + u64 child_addr, addr, size;
> >> + const __be32 *ranges;
> >> + int rlen, rone, ret;
> >> +
> >> + bus_np = of_find_compatible_node(NULL, NULL,
> >> + "socionext,uniphier-system-bus");
> >
> > This is broken if you ever have multiple instances.
> >
> > Either use a single node, or if there is a more complex relationship
> > between busses and their controllers, describe that explicitly with
> > phandles.
>
>
> Probably, I will stick to phandle in v2.
I would prefer a single node unless there's some other complication
regarding the relationship of the controller and the bus itself.
Thanks,
Mark.
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Re: [Qemu-devel] [PATCH v5 1/4] firmware: introduce sysfs driver for QEMU's fw_cfg device
On 11/24/15 18:38, Eric Blake wrote: > On 11/24/2015 09:55 AM, Gabriel L. Somlo wrote: >> On Tue, Nov 24, 2015 at 04:14:50AM +0800, kbuild test robot wrote: > >>> >>>drivers/firmware/qemu_fw_cfg.c: In function 'fw_cfg_cmdline_set': > drivers/firmware/qemu_fw_cfg.c:510:7: warning: format '%lli' expects > argument of type 'long long int *', but argument 3 has type 'phys_addr_t > *' [-Wformat=] >>> &ctrl_off, &data_off, &consumed); >>> ^ >> >> Oh, I think I know why this happened: >> > >> >> So, I could use u64 instead of phys_addr_t and resource_size_t, and >> keep "%lli" (or "%Li"), but then I'd have to check if the parsed value > > %Li is not POSIX. Don't use it (stick with %lli). > >> would overflow a 32-bit address value on arches where phys_addr_t is >> u32, which would make things a bit more messy and awkward. >> >> I'm planning on #ifdef-ing the format string instead: >> >> #ifdef CONFIG_PHYS_ADDR_T_64BIT >> #define PH_ADDR_SCAN_FMT "@%Li%n:%Li:%Li%n" >> #else >> #define PH_ADDR_SCAN_FMT "@%li%n:%li:%li%n" >> #endif > > A more typical approach is akin to ; have PH_ADDR_FMT > defined to either "lli" or "li", then write sscanf(str, "@%"PH_ADDR_FMT > "%n:..., ...), using PH_ADDR_FMT multiple times. > >> ... >> processed = sscanf(str, PH_ADDR_SCAN_FMT, >>&base, &consumed, >>&ctrl_off, &data_off, &consumed); > > Umm, why are you passing &consumed to more than one sscanf() %? That's > (probably) undefined behavior. > > [In general, sscanf() is a horrid interface to use for parsing integers > - it has undefined behavior if the input text would trigger integer > overflow, making it safe to use ONLY on text that you control and can > guarantee won't overflow. By the time you've figured out if untrusted > text meets the requirement for safe parsing via sscanf(), you've > practically already parsed it via safer strtol() and friends.] > Yes, but this is the kernel, which may or may not follow POSIX semantics. (And may or may not curse at POSIX in the process, either way! :)) Laszlo -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
