[PATCH v4 3/5] clk: sunxi: Add sun9i A80 cpus (cpu special) clock support
The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-sun9i-cpus.c| 240 ++
3 files changed, 242 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-sun9i-cpus.c
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index b6859ed6913f..153ac72869e8 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
+ "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index c55d5cd1c0e5..f7d439fa9980 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -16,6 +16,7 @@ obj-y += clk-sun9i-mmc.o
obj-y += clk-usb.o
obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
+obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
diff --git a/drivers/clk/sunxi/clk-sun9i-cpus.c
b/drivers/clk/sunxi/clk-sun9i-cpus.c
new file mode 100644
index ..7626d2194b96
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun9i-cpus.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai
+ *
+ * Allwinner A80 CPUS clock driver
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static DEFINE_SPINLOCK(sun9i_a80_cpus_lock);
+
+/**
+ * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
+ */
+
+#define SUN9I_CPUS_MAX_PARENTS 4
+#define SUN9I_CPUS_MUX_PARENT_PLL4 3
+#define SUN9I_CPUS_MUX_SHIFT 16
+#define SUN9I_CPUS_MUX_MASKGENMASK(17, 16)
+#define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \
+ SUN9I_CPUS_MUX_SHIFT)
+
+#define SUN9I_CPUS_DIV_SHIFT 4
+#define SUN9I_CPUS_DIV_MASKGENMASK(5, 4)
+#define SUN9I_CPUS_DIV_GET(reg)((reg & SUN9I_CPUS_DIV_MASK) >>
\
+ SUN9I_CPUS_DIV_SHIFT)
+#define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \
+ (div << SUN9I_CPUS_DIV_SHIFT))
+#define SUN9I_CPUS_PLL4_DIV_SHIFT 8
+#define SUN9I_CPUS_PLL4_DIV_MASK GENMASK(12, 8)
+#define SUN9I_CPUS_PLL4_DIV_GET(reg) ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \
+ SUN9I_CPUS_PLL4_DIV_SHIFT)
+#define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) |
\
+ (div <<
SUN9I_CPUS_PLL4_DIV_SHIFT))
+
+struct sun9i_a80_cpus_clk {
+ struct clk_hw hw;
+ void __iomem *reg;
+};
+
+#define to_sun9i_a80_cpus_clk(_hw) container_of(_hw, struct
sun9i_a80_cpus_clk, hw)
+
+static unsigned long sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw);
+ unsigned long rate;
+ u32 reg;
+
+ /* Fetch the register value */
+ reg = readl(cpus->reg);
+
+ /* apply pre-divider first if parent is pll4 */
+ if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4)
+ parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;
+
+ /* clk divider */
+ rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);
+
+ return rate;
+}
+
+static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8
*pre_divp,
+u8 parent, unsigned long parent_rate)
+{
+ u8 div, pre_div = 1;
+
+ /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+ if (parent_rate && rate > parent_rate)
+ rate = parent_rate;
+
+ div = DIV_ROUND_UP(parent_rate, rate);
+
+ /* calculate pre-divider if parent is pll4 */
+ if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && di
[PATCH v4 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver
The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.
Also, build it for sun9i/A80, and not just for configurations with
MFD_SUN6I_PRCM enabled.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi/Makefile | 5 +--
drivers/clk/sunxi/clk-sun8i-apb0.c | 71 +++---
2 files changed, 62 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index cb4c299214ce..c55d5cd1c0e5 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -15,6 +15,7 @@ obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
obj-y += clk-usb.o
+obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
+
obj-$(CONFIG_MFD_SUN6I_PRCM) += \
- clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
- clk-sun8i-apb0.o
+ clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c
b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 7ae5d2c2cde1..c1e2ac8f4b0d 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -17,13 +17,68 @@
#include
#include
#include
+#include
#include
+static struct clk *sun8i_a23_apb0_register(struct device_node *node,
+ void __iomem *reg)
+{
+ const char *clk_name = node->name;
+ const char *clk_parent;
+ struct clk *clk;
+ int ret;
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+ if (!clk_parent)
+ return ERR_PTR(-EINVAL);
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ /* The A23 APB0 clock is a standard 2 bit wide divider clock */
+ clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
+ 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ if (IS_ERR(clk))
+ return clk;
+
+ ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ if (ret)
+ goto err_unregister;
+
+ return clk;
+
+err_unregister:
+ clk_unregister_divider(clk);
+
+ return ERR_PTR(ret);
+}
+
+static void sun8i_a23_apb0_setup(struct device_node *node)
+{
+ void __iomem *reg;
+ struct resource res;
+ struct clk *clk;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk = sun8i_a23_apb0_register(node, reg);
+ if (IS_ERR(clk))
+ goto err_unmap;
+
+ return;
+
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
+ sun8i_a23_apb0_setup);
+
static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
- const char *clk_name = np->name;
- const char *clk_parent;
struct resource *r;
void __iomem *reg;
struct clk *clk;
@@ -33,19 +88,11 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device
*pdev)
if (IS_ERR(reg))
return PTR_ERR(reg);
- clk_parent = of_clk_get_parent_name(np, 0);
- if (!clk_parent)
- return -EINVAL;
-
- of_property_read_string(np, "clock-output-names", &clk_name);
-
- /* The A23 APB0 clock is a standard 2 bit wide divider clock */
- clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
- 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ clk = sun8i_a23_apb0_register(np, reg);
if (IS_ERR(clk))
return PTR_ERR(clk);
- return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return 0;
}
static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
--
2.6.2
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[PATCH v4 0/5] ARM: sun9i: Add Allwinner A80 PRCM clock/reset support
Hi everyone, (resent with mailing lists CC-ed) This is v4 of the Allwinner A80 PRCM support series. Since v4, the series moved away from the mfd approach, and just lists the various controls directly under the "clocks" and "soc" nodes. Changes since v3: - Only build new clock drivers for CONFIG_MACH_SUN9I - Refactor sun8i-a23-apb0-clk driver to share common clock registering code Changes since v2: - Move away from mfd approach and directly list the clock and reset controls as first class devices. - Use the new clk-simple-gates driver for the apbs clock gates. - Update clk code to use struct clk_request. - Add 1wire clk node. - Use GENMASK and always use shifted bitmasks in cpus clk driver. Changes since v1: - Added missing clock gates based on updated documents - Added new cpus clock driver based on updated documents - Added pll3 clock placeholder - Added comments about 24M & 32k oscillators The series adds support for the Power Reset and Clock Management module on Allwinner's A80 SoC. The PRCM manages clocks and resets for the "special" block of peripherals, or the R/RTC block in earlier SoCs, as well as power domain and resets for various parts of the SoC, such as the 2 processor clusters, the GPU and others. The special peripherals include a standby processor core, a timer block, a watchdog, pin controller, 1 wire interface, PS/2 interface, a UART, the RSB controller, a DMA controller, a consumer IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do not have documents for all the peripherals. Support will be added where possible. Patch 1 adds CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver. This driver was used with the mfd approach for the A23/A33 PRCM. As such it is a platform device driver. Patch 2 adds a new compatible string for the apbs gates to the clk-simple-gates driver. Patch 3 adds a new driver for the cpus clock. Patch 4 adds the various supported clock and reset control device nodes to the A80 dtsi. Patch 5 adds some TODO comments regarding the 2 system oscillators. Regards ChenYu Chen-Yu Tsai (5): clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver clk: sunxi: Add sun9i A80 apbs gates support clk: sunxi: Add sun9i A80 cpus (cpu special) clock support ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes ARM: dts: sun9i: Add TODO comments for the main and low power clocks Documentation/devicetree/bindings/clock/sunxi.txt | 2 + arch/arm/boot/dts/sun9i-a80.dtsi | 97 - drivers/clk/sunxi/Makefile| 6 +- drivers/clk/sunxi/clk-simple-gates.c | 2 + drivers/clk/sunxi/clk-sun8i-apb0.c| 71 +-- drivers/clk/sunxi/clk-sun9i-cpus.c| 240 ++ 6 files changed, 403 insertions(+), 15 deletions(-) create mode 100644 drivers/clk/sunxi/clk-sun9i-cpus.c -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 4/5] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes
This adds the supported PRCM clocks and reset controls to the A80 dtsi.
The DAUDIO module clocks are not supported yet.
Also update clock and reset phandles for r_uart.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 79 +++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1118bf5cc4fb..a4ce348c0831 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -164,6 +164,14 @@
"usb_phy2", "usb_hsic_12M";
};
+ pll3: clk@0608 {
+ /* placeholder until implemented */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-rate = <0>;
+ clock-output-names = "pll3";
+ };
+
pll4: clk@060c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
@@ -350,6 +358,68 @@
"apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5";
};
+
+ cpus_clk: clk@08001410 {
+ compatible = "allwinner,sun9i-a80-cpus-clk";
+ reg = <0x08001410 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
+ clock-output-names = "cpus";
+ };
+
+ ahbs: ahbs_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&cpus_clk>;
+ clock-output-names = "ahbs";
+ };
+
+ apbs: clk@0800141c {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ reg = <0x0800141c 0x4>;
+ #clock-cells = <0>;
+ clocks = <&ahbs>;
+ clock-output-names = "apbs";
+ };
+
+ apbs_gates: clk@08001428 {
+ compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+ reg = <0x08001428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apbs>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>,
+ <6>, <7>,
+ <12>, <13>,
+ <16>, <17>,
+ <18>, <20>;
+ clock-output-names = "apbs_pio", "apbs_ir",
+ "apbs_timer", "apbs_rsb",
+ "apbs_uart", "apbs_1wire",
+ "apbs_i2c0", "apbs_i2c1",
+ "apbs_ps2_0", "apbs_ps2_1",
+ "apbs_dma", "apbs_i2s0",
+ "apbs_i2s1", "apbs_twd";
+ };
+
+ r_1wire_clk: clk@08001450 {
+ reg = <0x08001450 0x4>;
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "r_1wire";
+ };
+
+ r_ir_clk: clk@08001454 {
+ reg = <0x08001454 0x4>;
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "r_ir";
+ };
};
soc {
@@ -764,13 +834,20 @@
interrupts = ;
};
+ apbs_rst: reset@080014b0 {
+ reg = <0x080014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
r_uart: serial@08002800 {
compatible = "snps,dw-apb-uart";
reg = <0x08002800 0x400>;
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apbs_gates 4>;
+ resets = <&apbs_rst 4>;
status = "disabled";
};
};
--
2.6.2
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[PATCH v4 5/5] ARM: dts: sun9i: Add TODO comments for the main and low power clocks
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a4ce348c0831..eb69a62f6bc4 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -128,6 +128,17 @@
*/
ranges = <0 0 0 0x2000>;
+ /*
+* This clock is actually configurable from the PRCM address
+* space. The external 24M oscillator can be turned off, and
+* the clock switched to an internal 16M RC oscillator. Under
+* normal operation there's no reason to do this, and the
+* default is to use the external good one, so just model this
+* as a fixed clock. Also it is not entirely clear if the
+* osc24M mux in the PRCM affects the entire clock tree, which
+* would also throw all the PLL clock rates off, or just the
+* downstream clocks in the PRCM.
+*/
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -135,6 +146,13 @@
clock-output-names = "osc24M";
};
+ /*
+* The 32k clock is from an external source, normally the
+* AC100 codec/RTC chip. This clock is by default enabled
+* and clocked at 32768 Hz, from the oscillator connected
+* to the AC100. It is configurable, but no such driver or
+* bindings exist yet.
+*/
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
--
2.6.2
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[PATCH v4 2/5] clk: sunxi: Add sun9i A80 apbs gates support
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index a94bb56a0e9e..b6859ed6913f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -55,6 +55,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+ "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c
b/drivers/clk/sunxi/clk-simple-gates.c
index 0214c6548afd..c8acc0612c15 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -140,6 +140,8 @@ CLK_OF_DECLARE(sun9i_a80_apb0,
"allwinner,sun9i-a80-apb0-gates-clk",
sunxi_simple_gates_init);
CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-gates-clk",
+ sunxi_simple_gates_init);
static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
14, /* ahb_sdram */
--
2.6.2
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Re: [PATCH 1/2] Documentation: DT: Add entry for ARM SP805-WDT
Hi Rob, On Wed, Nov 18, 2015 at 7:49 PM, Rob Herring wrote: > On Wed, Nov 18, 2015 at 8:03 AM, Bhupesh SHARMA > wrote: >> Hi Rob, >> >> Thanks for the review. >> >> On Tue, Nov 17, 2015 at 5:44 AM, Rob Herring wrote: >>> On Mon, Nov 16, 2015 at 02:45:25PM +, Mark Rutland wrote: On Mon, Nov 16, 2015 at 07:54:42PM +0530, Bhupesh Sharma wrote: > This patch adds a devicetree binding documentation for ARM's > SP805 WatchDog Timer. > > Signed-off-by: Bhupesh Sharma > --- > .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 > > 1 file changed, 33 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/watchdog/sp805-wdt.txt > > diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt > b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt > new file mode 100644 > index 000..ec70fe9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt > @@ -0,0 +1,33 @@ > +* ARM SP805 Watchdog Timer (WDT) Controller > + > +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register > that > +can be used to identify the peripheral type, vendor, and revision. > +This value can be used for driver matching. > + >> >> [snip..] >> > +As SP805 WDT is a primecell IP, it follows the base bindings specified > in > +'arm/primecell.txt' > + > +Required properties: > +- compatible : Should be "arm,sp805-wdt", "arm,primecell" > +- reg : Base address and size of the watchdog timer registers. > +- interrupts : Should specify WDT interrupt number. > + > +Optional properties: > +- clocks : From common clock binding. First clock is phandle to clock > for apb > + pclk. Additional clocks are optional. > +- clock-names : From common clock binding. Shall be "apb_pclk" for > first clock. The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly. >>> >>> The h/w has 2 clocks, PCLK and WDOGCLK, so both should be described and >>> neither should be optional. >> >> As per the SP805 WDT TRM I have with me (see [1], Figure 1-1), this >> h/w has only only input >> clock WDOGCLK. >> >> [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf > > Look closer, PCLK is in the AMBA bus signals. The version online has > some timing diagrams also which I didn't find here. Correct. So will add both PCLK and WDOGCLK to the compatible node in the v2 of this patch. Regards, Bhupesh -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] Documentation: DT: Add entry for ARM SP805-WDT
Hi Mark,
On Wed, Nov 18, 2015 at 7:21 PM, Bhupesh SHARMA wrote:
> Hi Mark,
>
> Thanks for the review.
>
> On Mon, Nov 16, 2015 at 8:15 PM, Mark Rutland wrote:
>> On Mon, Nov 16, 2015 at 07:54:42PM +0530, Bhupesh Sharma wrote:
>>> This patch adds a devicetree binding documentation for ARM's
>>> SP805 WatchDog Timer.
>>>
>>> Signed-off-by: Bhupesh Sharma
>>> ---
>>> .../devicetree/bindings/watchdog/sp805-wdt.txt | 33
>>>
>>> 1 file changed, 33 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
>>> b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
>>> new file mode 100644
>>> index 000..ec70fe9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
>>> @@ -0,0 +1,33 @@
>>> +* ARM SP805 Watchdog Timer (WDT) Controller
>>> +
>>> +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
>>> +can be used to identify the peripheral type, vendor, and revision.
>>> +This value can be used for driver matching.
>>> +
>>> +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c'
>>> +framework to invoke the probe function of the sp805_wdt driver using the
>>> +unique PRIMECELL identifiers of the sp805 wdt IP.
>>
>> This paragraph can go. We shouldn't describe kernel internals.
>
> Ok.
>
>>> +As SP805 WDT is a primecell IP, it follows the base bindings specified in
>>> +'arm/primecell.txt'
>>> +
>>> +Required properties:
>>> +- compatible : Should be "arm,sp805-wdt", "arm,primecell"
>>> +- reg : Base address and size of the watchdog timer registers.
>>> +- interrupts : Should specify WDT interrupt number.
>>> +
>>> +Optional properties:
>>> +- clocks : From common clock binding. First clock is phandle to clock for
>>> apb
>>> + pclk. Additional clocks are optional.
>>> +- clock-names : From common clock binding. Shall be "apb_pclk" for first
>>> clock.
>>
>> The hardware has "WDOGCLK", which is what the driver appears to expect
>> first implicitly.
>
> Ok.
>
>>> +Examples:
>>> +
>>> + cluster1_core0_watchdog: wdt@c00 {
>>> + compatible = "arm,sp805-wdt", "arm,primecell";
>>> + reg = <0x0 0xc00 0x0 0x1000>;
>>> + interrupts = <1 12 0x8>; /* PPI, Level low type */
>>
>> I don't see how you can use PPIs here. This is not banked per CPU.
>
> I have raised this concern to my hardware team. This might be an issue
> with the documentation.
> I will change it in v2 as per their comments.
I just checked back with the hardware team. They confirm that the
WDOGINT interrupts lines
from the eight instances of the SP805 WDT are infact connected to PPI
input of the GICv3 controller.
Also this SP805 WDT IP supports 2 interrupt lines:
- WDOGINT
- WDOGRES
but the current sp805_wdt.c driver doesn't handle the WDOGINT
interrupt (irrespective of whether
it is a SPI or PPI). I could not trace a request_irq being called for
the same in the driver.
So, I would suggest the following:
I can spin a patch for sp805_wdt.c to add support to handle WDOGINT
interrupt when the WDT counter expires
as currently the cadence_wdt driver does (see [1] and [2] as reference):
[1] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L343
[2] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L254
Please suggest if this approach seems fine to you.
Regards,
Bhupesh
>
> Regards,
> Bhupesh
>
>> Mark.
>>
>>> + clocks = <&clockgen 4 3>;
>>> + clock-names = "apb_pclk";
>>> + };
>>> +
>>> --
>>> 1.7.9.5
>>>
>>>
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[PATCH 2/2] regulator: fixed: Add support for regmap
Use the device tree properties for regmap:
* Lookup the regmap phandle
* Use the enable offset and enable mask
* Reuse enable-active-high value
Use an alternative set of regulator_ops when the regmap is set,
specifying the regmap helper functions.
As syscon_regmap_lookup_by_phandle() can only return -ENODEV or -ENOSYS
as errors and -EPROBE_DEFER doesn't make sense for a register, the
specific error is never propagated.
This is required for Broadcom BCM63xx SoCs that enable power to
individual peripherals by clearing a bit in the miscIddqCtrl register.
Signed-off-by: Simon Arlott
---
drivers/regulator/fixed.c | 30 +-
include/linux/regulator/fixed.h | 9 -
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index ff62d69..5a3fa44 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
struct fixed_voltage_data {
struct regulator_desc desc;
@@ -92,6 +93,19 @@ of_get_fixed_voltage_config(struct device *dev,
if ((config->gpio == -ENODEV) || (config->gpio == -EPROBE_DEFER))
return ERR_PTR(-EPROBE_DEFER);
+ config->regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
+ if (!IS_ERR(config->regmap)) {
+ u32 val;
+
+ if (of_property_read_u32(np, "regmap-offset", &val))
+ return ERR_PTR(-EINVAL);
+ config->enable_reg = val;
+
+ if (of_property_read_u32(np, "regmap-mask", &val))
+ return ERR_PTR(-EINVAL);
+ config->enable_mask = val;
+ }
+
of_property_read_u32(np, "startup-delay-us", &config->startup_delay);
config->enable_high = of_property_read_bool(np, "enable-active-high");
@@ -107,6 +121,12 @@ of_get_fixed_voltage_config(struct device *dev,
static struct regulator_ops fixed_voltage_ops = {
};
+static struct regulator_ops fixed_voltage_regmap_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+
static int reg_fixed_voltage_probe(struct platform_device *pdev)
{
struct fixed_voltage_config *config;
@@ -140,7 +160,15 @@ static int reg_fixed_voltage_probe(struct platform_device
*pdev)
}
drvdata->desc.type = REGULATOR_VOLTAGE;
drvdata->desc.owner = THIS_MODULE;
- drvdata->desc.ops = &fixed_voltage_ops;
+ if (!IS_ERR_OR_NULL(config->regmap)) {
+ drvdata->desc.ops = &fixed_voltage_regmap_ops;
+ cfg.regmap = config->regmap;
+ drvdata->desc.enable_reg = config->enable_reg;
+ drvdata->desc.enable_mask = config->enable_mask;
+ drvdata->desc.enable_is_inverted = !config->enable_high;
+ } else {
+ drvdata->desc.ops = &fixed_voltage_ops;
+ }
drvdata->desc.enable_time = config->startup_delay;
diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h
index 48918be..7cec0d1 100644
--- a/include/linux/regulator/fixed.h
+++ b/include/linux/regulator/fixed.h
@@ -26,6 +26,10 @@ struct regulator_init_data;
* @microvolts:Output voltage of regulator
* @gpio: GPIO to use for enable control
* set to -EINVAL if not used
+ * @regmap:Regmap to use for enable control
+ * set to -ENODEV if not used
+ * @enable_reg:Register for control when using regmap
+ * @enable_mask: Mask for control when using regmap
* @startup_delay: Start-up time in microseconds
* @gpio_is_open_drain: Gpio pin is open drain or normal type.
* If it is open drain type then HIGH will be set
@@ -33,7 +37,7 @@ struct regulator_init_data;
* and low will be set as gpio-output with driven
* to low. For non-open-drain case, the gpio will
* will be in output and drive to low/high accordingly.
- * @enable_high: Polarity of enable GPIO
+ * @enable_high: Polarity of enable GPIO/regmap
* 1 = Active high, 0 = Active low
* @enabled_at_boot: Whether regulator has been enabled at
* boot or not. 1 = Yes, 0 = No
@@ -50,6 +54,9 @@ struct fixed_voltage_config {
const char *input_supply;
int microvolts;
int gpio;
+ struct regmap *regmap;
+ unsigned int enable_reg;
+ unsigned int enable_mask;
unsigned startup_delay;
unsigned gpio_is_open_drain:1;
unsigned enable_high:1;
--
2.1.4
--
Simon Arlott
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[PATCH 1/2] regulator: Add regmap support to regulator-fixed device tree binding
Add properties for regmap to the regulator-fixed device tree binding:
* Reference the regmap phandle
* Specify the enable offset and enable mask
* Reuse enable-active-high for regmap
This is required for Broadcom BCM63xx SoCs that enable power to
individual peripherals by clearing a bit in the miscIddqCtrl register.
Signed-off-by: Simon Arlott
---
.../bindings/regulator/fixed-regulator.txt | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
index 4fae41d..b499a65 100644
--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -5,13 +5,18 @@ Required properties:
Optional properties:
- gpio: gpio to use for enable control
+- regmap: regmap phandle to use for enable control
+- regmap-offset: register offset when using regmap for enable control
+- regmap-mask: register enable mask when using regmap for enable control
- startup-delay-us: startup time in microseconds
-- enable-active-high: Polarity of GPIO is Active high
+- enable-active-high: Polarity of GPIO/regmap is Active high
If this property is missing, the default assumed is Active low.
- gpio-open-drain: GPIO is open drain type.
If this property is missing then default assumption is false.
-vin-supply: Input supply name.
+Only one of gpio/regmap should be specified.
+
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
However a fixed voltage regulator is expected to have the
@@ -32,3 +37,17 @@ Example:
gpio-open-drain;
vin-supply = <&parent_reg>;
};
+
+ xyz: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-supply";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regmap = <&syscon>;
+ regmap-offset = <0x4>;
+ regmap-mask = <0x200>;
+ startup-delay-us = <7>;
+ enable-active-high;
+ regulator-boot-on;
+ vin-supply = <&parent_reg>;
+ };
--
2.1.4
--
Simon Arlott
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Re: [PATCH 1/4] ARM: dt: mvebu: ix4-300d: remove whole flash partition
>On Sat, Nov 28, 2015 at 12:14:05PM +0100, Sebastian Hesselbarth wrote: > Current NAND node has an additional flash partition for the whole > flash overlapping with real partitions. Remove this partition as > the whole flash is already represented by the NAND device itself. > > Signed-off-by: Sebastian Hesselbarth Given Benoit comment Acked-by: Andrew Lunn Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] arm: boot: store ATAGs structure into DT "/chosen/linux,atags" entry
On 11/28/2015 9:34 AM, Nicolas Pitre wrote: > On Sat, 28 Nov 2015, Russell King - ARM Linux wrote: > >> On Fri, Nov 27, 2015 at 06:28:50PM -0500, Nicolas Pitre wrote: >>> On Fri, 27 Nov 2015, Arnd Bergmann wrote: >>> I don't mind creating the /proc/atags compatibility hack from the kernel for a DT based N700 kernel, as long as we limit it as much as we can to the machines that need it. Leaving a board file for the N700 in place that contains the procfs code (and not much more) seems reasonable here, as we are talking about a board specific hack and the whole point appears to be running unmodified user space. Regarding how to get the data into the kernel in the first place, my preferred choice would still be to have an intermediate bootloader such as pxa-impedance-matcher, but I won't complain if others are happy enough about putting it into the ATAGS compat code we already have, as long as it's limited to the boards we know need it. >>> >>> Assuming you have a N700 board file for special procfs code, then why >>> not getting at the atags in memory where the bootloader has put them >>> directly from that same board file? This way it'll really be limited to >>> the board we know needs it and the special exception will be contained >>> to that one file. Amongst the machine specific hooks, there is one that >>> gets invoked early during boot before those atags are overwritten. >> >> I've already suggested that. > > Good. And Arnd likes the idea too. So we might be converging at last > which is a good thing. It makes me happy too. -Frank -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] ARM: dt: mvebu: ix4-300d: remove whole flash partition
>From mobile > Le 28 nov. 2015 à 18:38, Sebastian Hesselbarth > a écrit : > >> On 28.11.2015 17:52, Andrew Lunn wrote: >>> On Sat, Nov 28, 2015 at 12:14:05PM +0100, Sebastian Hesselbarth wrote: >>> Current NAND node has an additional flash partition for the whole >>> flash overlapping with real partitions. Remove this partition as >>> the whole flash is already represented by the NAND device itself. >> >> If i remember correctly, we discussed this when the contribution was >> made. I think the stock firmware might use this for applying updates. >> Maybe Benoit can comment? > > Yes, please. >From my memory since I'm not running the stock firmware it uses the MTD device directly. This is safe to remove. I was not very contort able with this flash dts part it was copied over from a netgear mevbu device ... > >> If so, removing this will break compatibility with stock firmware. Do >> we want to do that? There are a few other mvebu dts files with a >> partition spanning the whole flash. Should we remove them as well? > > Well, there is already a mtd device that spans the whole flash so > what is the purpose of another "partition" that isn't a part but > all of the device? Actually, I doubt that a FW update will wipe > the flash as a whole, i.e. including boot loader, boot env, user > config. > > Anyway, let's see if Benoit can shed some light on this. > > FWIW, neither single partitions nor a combined partitions node > should be a direct sub-node of the _controller_ but a NAND > _device_ node instead. Luckily, multi-device systems are not that > common, so I guess we wait with it until such a system pops up for > testing. > > Sebastian > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/10] Input: synaptics-rmi4: Add device tree support for 2d sensors and F11
Hi Rob, Thanks for reviewing! I will incorporate your feedback into the next version. Andrew On 11/27/2015 01:10 PM, Rob Herring wrote: On Wed, Nov 25, 2015 at 04:09:13PM -0800, Andrew Duggan wrote: 2D sensors have several parameter which can be set in the platform data. This patch adds support for getting those values from devicetree. Signed-off-by: Andrew Duggan --- .../bindings/input/rmi4/rmi_2d_sensor.txt | 54 +++ drivers/input/rmi4/rmi_2d_sensor.c | 103 + drivers/input/rmi4/rmi_2d_sensor.h | 3 + drivers/input/rmi4/rmi_f11.c | 7 +- 4 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt diff --git a/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt b/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt new file mode 100644 index 000..bbff31b --- /dev/null +++ b/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt @@ -0,0 +1,54 @@ +Synaptics RMI4 2D Sensor Device Binding + +The Synaptics RMI4 core is able to support RMI4 devices using differnet s/differnet/different/ +transports and differnet functions. This file describes the device tree ditto. +bindings for devices which contain 2D sensors using Function 11 or +Function 12. Complete documentation for transports and other functions +can be found in: +Documentation/devicetree/bindings/input/rmi4. + +RMI4 Function 11 and Function 12 are for 2D touch position sensing. +Additional documentation for F11 can be found at: +http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf + +Optional Properties: +- syna,swap-axes: Swap X and Y positions when reporting (boolean). +- syna,flip-x: Reverse the direction of X (boolean). +- syna,flip-y: Reverse the direction of Y (boolean). We already have similar, generic properties for these. +- syna,clip-x-low: Sets a minimum value for X. +- syna,clip-y-low: Sets a minimum value for Y. +- syna,clip-x-high: Sets a maximum value for X. +- syna,clip-y-high: Sets a maximum value for Y. +- syna,offset-x: Add an offset to X. +- syna,offset_y: Add an offset to Y. Don't use "_". +- syna,delta-x-threshold: Set the minimum distance on the X axis required + to generate an interrupt in reduced reporting + mode. +- syna,delta-y-threshold: Set the minimum distance on the Y axis required + to generate an interrupt in reduced reporting + mode. +- syna,type-a: Report type A multitouch events. +- syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad. +- syna,x-mm: The length in millimeters of the X axis. +- syna,y-mm: The length in millimeters of the Y axis. I think some of these have common properties defined too. If not, we should add them. +- syna,disable-report-mask: Mask for disabling posiiton reporting. Used to + disable reporing absolute position data. +- syna,rezero-wait: Time in miliseconds to wait after issuing a rezero + command. Add -msec suffix. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] ARM: dt: mvebu: ix4-300d: move partitions to partition sub-node
On 28.11.2015 18:00, Andrew Lunn wrote:
> On Sat, Nov 28, 2015 at 12:14:06PM +0100, Sebastian Hesselbarth wrote:
>> NAND flash partitions should be part of a partitions sub-node
>> not the flash node itself. Move the partitions which will also
>> allow different bootloaders get rid of the stock partitions
>> easily by removing the partitions node.
>>
>> Signed-off-by: Sebastian Hesselbarth
>
> Humm, did not know that. Quoting
> Documentation/devicetree/bindings/mtd/partition.txt:
>
> The partition table should be a subnode of the mtd node and
> should be named 'partitions'. Partitions are defined in subnodes
> of the partitions node.
>
> For backwards compatibility partitions as direct subnodes of the
> mtd device are supported. This use is discouraged.
>
> It also looks like none of the other MVEBU maintainers know that
> either, since a quick look at the .dts files shows very few have a
> partitions node.
Me neither, Linus Walleij's latest contribution to the pogoplug
series showed it to me. And while I am working on barebox support
for the ix4, I always wanted to remove the stock partitions easily.
Barebox always uses internal registers at 0xf100 so it will
never boot that stupid stock kernel that depends on 0xd000
registers.
> Acked-by: Andrew Lunn
>
> Thanks
> Andrew
ditto ;)
Sebastian
>> ---
>> Cc: Jason Cooper
>> Cc: Andrew Lunn
>> Cc: Gregory Clement
>> Cc: Rob Herring
>> Cc: Pawel Moll
>> Cc: Mark Rutland
>> Cc: Ian Campbell
>> Cc: Kumar Gala
>> Cc: Russell King
>> Cc: Benoit Masson
>> Cc: linux-arm-ker...@lists.infradead.org
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-ker...@vger.kernel.org
>> ---
>> arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 67
>> +
>> 1 file changed, 36 insertions(+), 31 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
>> b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
>> index 30a0a6eac645..76781fd18624 100644
>> --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
>> +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
>> @@ -151,37 +151,42 @@
>> marvell,nand-enable-arbiter;
>> nand-on-flash-bbt;
>>
>> -partition@0 {
>> -label = "u-boot";
>> -reg = <0x000 0xe>;
>> -read-only;
>> -};
>> -
>> -partition@e {
>> -label = "u-boot-env";
>> -reg = <0xe 0x2>;
>> -read-only;
>> -};
>> -
>> -partition@10 {
>> -label = "u-boot-env2";
>> -reg = <0x10 0x2>;
>> -read-only;
>> -};
>> -
>> -partition@12 {
>> -label = "zImage";
>> -reg = <0x12 0x40>;
>> -};
>> -
>> -partition@52 {
>> -label = "initrd";
>> -reg = <0x52 0x40>;
>> -};
>> -
>> -partition@xE0 {
>> -label = "boot";
>> -reg = <0xE0 0x3F20>;
>> +partitions {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +
>> +partition@0 {
>> +label = "u-boot";
>> +reg = <0x000 0xe>;
>> +read-only;
>> +};
>> +
>> +partition@e {
>> +label = "u-boot-env";
>> +reg = <0xe 0x2>;
>> +read-only;
>> +};
>> +
>> +partition@10 {
>> +label = "u-boot-env2";
>> +reg = <0x10 0x2>;
>> +read-only;
>> +};
>> +
>> +partition@12 {
>> +label = "zImage";
>> +reg = <0x12 0x40>;
>> +
Re: [PATCH 1/4] ARM: dt: mvebu: ix4-300d: remove whole flash partition
On 28.11.2015 17:52, Andrew Lunn wrote: > On Sat, Nov 28, 2015 at 12:14:05PM +0100, Sebastian Hesselbarth wrote: >> Current NAND node has an additional flash partition for the whole >> flash overlapping with real partitions. Remove this partition as >> the whole flash is already represented by the NAND device itself. > > If i remember correctly, we discussed this when the contribution was > made. I think the stock firmware might use this for applying updates. > Maybe Benoit can comment? Yes, please. > If so, removing this will break compatibility with stock firmware. Do > we want to do that? There are a few other mvebu dts files with a > partition spanning the whole flash. Should we remove them as well? Well, there is already a mtd device that spans the whole flash so what is the purpose of another "partition" that isn't a part but all of the device? Actually, I doubt that a FW update will wipe the flash as a whole, i.e. including boot loader, boot env, user config. Anyway, let's see if Benoit can shed some light on this. FWIW, neither single partitions nor a combined partitions node should be a direct sub-node of the _controller_ but a NAND _device_ node instead. Luckily, multi-device systems are not that common, so I guess we wait with it until such a system pops up for testing. Sebastian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] arm: boot: store ATAGs structure into DT "/chosen/linux,atags" entry
On Sat, 28 Nov 2015, Russell King - ARM Linux wrote: > On Fri, Nov 27, 2015 at 06:28:50PM -0500, Nicolas Pitre wrote: > > On Fri, 27 Nov 2015, Arnd Bergmann wrote: > > > > > I don't mind creating the /proc/atags compatibility hack from the kernel > > > for a DT based N700 kernel, as long as we limit it as much as we can > > > to the machines that need it. Leaving a board file for the N700 in place > > > that contains the procfs code (and not much more) seems reasonable > > > here, as we are talking about a board specific hack and the whole point > > > appears to be running unmodified user space. > > > > > > Regarding how to get the data into the kernel in the first place, my > > > preferred choice would still be to have an intermediate bootloader > > > such as pxa-impedance-matcher, but I won't complain if others are > > > happy enough about putting it into the ATAGS compat code we already > > > have, as long as it's limited to the boards we know need it. > > > > Assuming you have a N700 board file for special procfs code, then why > > not getting at the atags in memory where the bootloader has put them > > directly from that same board file? This way it'll really be limited to > > the board we know needs it and the special exception will be contained > > to that one file. Amongst the machine specific hooks, there is one that > > gets invoked early during boot before those atags are overwritten. > > I've already suggested that. Good. And Arnd likes the idea too. So we might be converging at last which is a good thing. Nicolas -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/4] ARM: dt: mvebu: ix4-300d: Add ECC properties to NAND flash
On Sat, Nov 28, 2015 at 12:14:08PM +0100, Sebastian Hesselbarth wrote: > The NAND device found on Lenovo ix4-300d uses 4-bit BCH ECC protection. > Add the corresponding properties to the NAND node. > > Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] ARM: dt: mvebu: ix4-300d: Cleanup NAND partition ranges
On Sat, Nov 28, 2015 at 12:14:07PM +0100, Sebastian Hesselbarth wrote:
> Prefix all partition reg properties to 32-bit to ease readability.
> While at it, also remove a stale x in front of boot partition
> offset and make some upper-case hex numbers lower-case.
>
> Signed-off-by: Sebastian Hesselbarth
Acked-by: Andrew Lunn
Andrew
> ---
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Gregory Clement
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: Russell King
> Cc: Benoit Masson
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org
> ---
> arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> index 76781fd18624..13cf69a8d0fb 100644
> --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> @@ -157,35 +157,35 @@
>
> partition@0 {
> label = "u-boot";
> - reg = <0x000 0xe>;
> + reg = <0x 0x000e>;
> read-only;
> };
>
> partition@e {
> label = "u-boot-env";
> - reg = <0xe 0x2>;
> + reg = <0x000e 0x0002>;
> read-only;
> };
>
> partition@10 {
> label = "u-boot-env2";
> - reg = <0x10 0x2>;
> + reg = <0x0010 0x0002>;
> read-only;
> };
>
> partition@12 {
> label = "zImage";
> - reg = <0x12 0x40>;
> + reg = <0x0012 0x0040>;
> };
>
> partition@52 {
> label = "initrd";
> - reg = <0x52 0x40>;
> + reg = <0x0052 0x0040>;
> };
>
> - partition@xE0 {
> + partition@e0 {
> label = "boot";
> - reg = <0xE0 0x3F20>;
> + reg = <0x00e0 0x3f20>;
> };
> };
> };
> --
> 2.1.4
>
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Re: [PATCH 2/4] ARM: dt: mvebu: ix4-300d: move partitions to partition sub-node
On Sat, Nov 28, 2015 at 12:14:06PM +0100, Sebastian Hesselbarth wrote:
> NAND flash partitions should be part of a partitions sub-node
> not the flash node itself. Move the partitions which will also
> allow different bootloaders get rid of the stock partitions
> easily by removing the partitions node.
>
> Signed-off-by: Sebastian Hesselbarth
Humm, did not know that. Quoting
Documentation/devicetree/bindings/mtd/partition.txt:
The partition table should be a subnode of the mtd node and
should be named 'partitions'. Partitions are defined in subnodes
of the partitions node.
For backwards compatibility partitions as direct subnodes of the
mtd device are supported. This use is discouraged.
It also looks like none of the other MVEBU maintainers know that
either, since a quick look at the .dts files shows very few have a
partitions node.
Acked-by: Andrew Lunn
Thanks
Andrew
> ---
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Gregory Clement
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: Russell King
> Cc: Benoit Masson
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org
> ---
> arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 67
> +
> 1 file changed, 36 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> index 30a0a6eac645..76781fd18624 100644
> --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
> @@ -151,37 +151,42 @@
> marvell,nand-enable-arbiter;
> nand-on-flash-bbt;
>
> - partition@0 {
> - label = "u-boot";
> - reg = <0x000 0xe>;
> - read-only;
> - };
> -
> - partition@e {
> - label = "u-boot-env";
> - reg = <0xe 0x2>;
> - read-only;
> - };
> -
> - partition@10 {
> - label = "u-boot-env2";
> - reg = <0x10 0x2>;
> - read-only;
> - };
> -
> - partition@12 {
> - label = "zImage";
> - reg = <0x12 0x40>;
> - };
> -
> - partition@52 {
> - label = "initrd";
> - reg = <0x52 0x40>;
> - };
> -
> - partition@xE0 {
> - label = "boot";
> - reg = <0xE0 0x3F20>;
> + partitions {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0x000 0xe>;
> + read-only;
> + };
> +
> + partition@e {
> + label = "u-boot-env";
> + reg = <0xe 0x2>;
> + read-only;
> + };
> +
> + partition@10 {
> + label = "u-boot-env2";
> + reg = <0x10 0x2>;
> + read-only;
> + };
> +
> + partition@12 {
> + label = "zImage";
> + reg = <0x12 0x40>;
> + };
> +
> + partition@52 {
> + label = "initrd";
> + reg = <0x52 0x40>;
> + };
> +
> + partition@xE0 {
> + label = "boot";
> + reg = <0xE0 0x3F20
Re: [PATCH 1/4] ARM: dt: mvebu: ix4-300d: remove whole flash partition
On Sat, Nov 28, 2015 at 12:14:05PM +0100, Sebastian Hesselbarth wrote: > Current NAND node has an additional flash partition for the whole > flash overlapping with real partitions. Remove this partition as > the whole flash is already represented by the NAND device itself. If i remember correctly, we discussed this when the contribution was made. I think the stock firmware might use this for applying updates. Maybe Benoit can comment? If so, removing this will break compatibility with stock firmware. Do we want to do that? There are a few other mvebu dts files with a partition spanning the whole flash. Should we remove them as well? Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 04/10] drm/hisilicon: Add crtc funcs for ADE
use_maskOn 28 November 2015 at 10:38, Xinliang Liu
wrote:
> Add crtc funcs and helper funcs for ADE.
>
> Signed-off-by: Xinliang Liu
> Signed-off-by: Xinwei Kong
> Signed-off-by: Andy Green
> ---
> --- /dev/null
> +++ b/drivers/gpu/drm/hisilicon/hisi_ade_reg.h
> +#define ADE_CTRL (0x4)
> +#define ADE_CTRL1 (0x8C)
> +#define ADE_ROT_SRC_CFG(0x10)
> +#define ADE_DISP_SRC_CFG (0x18)
> +#define ADE_WDMA2_SRC_CFG (0x1C)
> +#define ADE_SEC_OVLY_SRC_CFG (0x20)
> +#define ADE_WDMA3_SRC_CFG (0x24)
> +#define ADE_OVLY1_TRANS_CFG(0x2C)
> +#define ADE_EN (0x100)
> +#define INTR_MASK_CPU_0(0xC10)
> +#define INTR_MASK_CPU_1(0xC14)
> +#define ADE_FRM_DISGARD_CTRL (0xA4)
> +/* reset and reload regs */
> +#define ADE_SOFT_RST_SEL0 (0x78)
> +#define ADE_SOFT_RST_SEL1 (0x7C)
> +#define ADE_RELOAD_DIS0(0xAC)
> +#define ADE_RELOAD_DIS1(0xB0)
> +#define ADE_CH_RDMA_BIT_OFST (0)
> +#define ADE_CLIP_BIT_OFST (15)
> +#define ADE_SCL_BIT_OFST (21)
> +#define ADE_CTRAN_BIT_OFST (24)
> +#define ADE_OVLY_BIT_OFST (37) /* 32+5 */
Don't think we have any cases in drm where constants are wrapped in
brackets. Is there any benefit of doing that here ?
> +/* channel regs */
> +#define RD_CH_PE(x)(0x1000 + (x) * 0x80)
... and I'm not talking about cases where the macros such as this one.
> +union U_LDI_CTRL {
> +struct {
> + unsigned intldi_en:1;
> + unsigned intdisp_mode_buf :1;
> + unsigned intdate_gate_en :1;
> + unsigned intbpp :2;
> + unsigned intwait_vsync_en :1;
> + unsigned intcorlorbar_width :7;
> + unsigned intbgr :1;
> + unsigned intcolor_mode:1;
> + unsigned intshutdown :1;
> + unsigned intvactive_line :12;
> + unsigned intldi_en_self_clr :1;
> + unsigned intreserved_573 :3;
> + } bits;
> + unsigned intu32;
> +};
> +
> +union U_LDI_WORK_MODE {
> +struct {
> + unsigned intwork_mode :1;
> + unsigned intwback_en :1;
> + unsigned intcolorbar_en :1;
> + unsigned intreserved_577 :29;
> + } bits;
> + unsigned intu32;
> +};
> +
The struct in the above two unions is missing a level of indentation.
> --- /dev/null
> +++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
> +static void ade_ldi_set_mode(struct ade_crtc *acrtc,
> +struct drm_display_mode *mode,
> +struct drm_display_mode *adj_mode)
> +{
> + struct ade_hw_ctx *ctx = acrtc->ctx;
> + void __iomem *base = ctx->base;
> + u32 out_w = mode->hdisplay;
> + u32 out_h = mode->vdisplay;
> + u32 hfp, hbp, hsw, vfp, vbp, vsw;
> + u32 plr_flags;
> + int ret;
> +
> + plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC)
> + ? HISI_LDI_FLAG_NVSYNC : 0;
> + plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC)
> + ? HISI_LDI_FLAG_NHSYNC : 0;
> + hfp = mode->hsync_start - mode->hdisplay;
> + hbp = mode->htotal - mode->hsync_end;
> + hsw = mode->hsync_end - mode->hsync_start;
> + vfp = mode->vsync_start - mode->vdisplay;
> + vbp = mode->vtotal - mode->vsync_end;
> + vsw = mode->vsync_end - mode->vsync_start;
> + if (vsw > 15) {
> + DRM_INFO("vsw exceeded 15\n");
DRM_ERROR or DRM_DEBUG_xx perhaps ?
> + vsw = 15;
> + }
> +
> + writel((hbp << 20) | (hfp << 0), base + LDI_HRZ_CTRL0);
> + /* p3-73 6220V100 pdf:
> +* "The configured value is the actual width - 1"
> +*/
> + writel(hsw - 1, base + LDI_HRZ_CTRL1);
> + writel((vbp << 20) | (vfp << 0), base + LDI_VRT_CTRL0);
> + /* p3-74 6220V100 pdf:
> +* "The configured value is the actual width - 1"
> +*/
> + writel(vsw - 1, base + LDI_VRT_CTRL1);
> +
> + /* p3-75 6220V100 pdf:
> +* "The configured value is the actual width - 1"
> +*/
> + writel(((out_h - 1) << 20) | ((out_w - 1) << 0),
> + base + LDI_DSP_SIZE);
> + writel(plr_flags, base + LDI_PLR_CTRL);
> +
> + ret = clk_set_rate(ctx->ade_pix_clk, mode->clock * 1000);
> + /* Success should be guaranteed in aotomic_check
> +* failer shouldn't happen here
> +*/
> + if (ret)
> + DRM_ERROR("set ade_pixel_clk_rate fail\n");
DItto
> + adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
> +
Re: [PATCH v2 03/10] drm/hisilicon: Add hisilicon DRM master driver
Hi Xinliang,
On 28 November 2015 at 10:38, Xinliang Liu wrote:
> Add DRM master driver for hi6220 SoC which used in HiKey board.
> Add dumb buffer feature.
> Add prime dmabuf feature.
>
> Signed-off-by: Xinliang Liu
> Signed-off-by: Xinwei Kong
> Signed-off-by: Andy Green
Your s-o-b should be the bottom of the list. There was a presentation
(ages ago) from Greg KH, who nicely described the order as a "chain of
command" or "guilt path". Looks like the rest of the series could use
this tweak.
> ---
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/hisilicon/Kconfig| 9 ++
> drivers/gpu/drm/hisilicon/Makefile | 3 +
> drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 214
> +++
> 5 files changed, 229 insertions(+)
> create mode 100644 drivers/gpu/drm/hisilicon/Kconfig
> create mode 100644 drivers/gpu/drm/hisilicon/Makefile
> create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.c
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 8773fad..038aae8 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -274,3 +274,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig"
> source "drivers/gpu/drm/imx/Kconfig"
>
> source "drivers/gpu/drm/vc4/Kconfig"
> +
> +source "drivers/gpu/drm/hisilicon/Kconfig"
I could swear that we can a patch that sorts these alphabetically,
although it doesn't seem to have made it upstream yet :-(
> --- /dev/null
> +++ b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
> +static int hisi_drm_load(struct drm_device *dev, unsigned long flags)
> +{
The use of .load (and .unload?) callbacks is not recommended. Take a
look at Laurent Pinchart's patch [1] about the whys and hows on the
topic
> +static struct dma_buf *hisi_gem_prime_export(struct drm_device *dev,
> +struct drm_gem_object *obj,
> +int flags)
> +{
> + /* we want to be able to write in mmapped buffer */
> + flags |= O_RDWR;
Erm... something feels fishy here. Out of the existing 15 drivers
setting up the prime callbacks only one (sti) does a similar thing. So
either everyone else is missing something obvious or hisilicon and sti
can rework their inner working to remove this (dare I say it) hack.
> +static int hisi_gem_cma_dumb_create(struct drm_file *file,
> + struct drm_device *dev,
> + struct drm_mode_create_dumb *args)
> +{
> + int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> +
> + /* mali gpu need pitch 8 bytes alignment for 32bpp */
> + args->pitch = roundup(min_pitch, 8);
> +
I'm not sure you want this kind of dependency of an out of tree driver
upstream. If this is some limitation on the display engine so be it,
but tailoring things for an external module seems like a very bad
idea.
> + return drm_gem_cma_dumb_create_internal(file, dev, args);
> +}
> +static int hisi_drm_bind(struct device *dev)
> +{
> + dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
> + return drm_platform_init(&hisi_drm_driver, to_platform_device(dev));
As pointed out by the the kernel doc - drm_platform_init is deprecated.
Regards,
Emil
[1] http://lists.freedesktop.org/archives/dri-devel/2015-November/095466.html
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Re: [PATCH 5/5] arm: boot: store ATAGs structure into DT "/chosen/linux,atags" entry
On Sat, Nov 28, 2015 at 01:27:07PM +0100, Arnd Bergmann wrote: > On Friday 27 November 2015 18:28:50 Nicolas Pitre wrote: > > On Fri, 27 Nov 2015, Arnd Bergmann wrote: > > > > > I don't mind creating the /proc/atags compatibility hack from the kernel > > > for a DT based N700 kernel, as long as we limit it as much as we can > > > to the machines that need it. Leaving a board file for the N700 in place > > > that contains the procfs code (and not much more) seems reasonable > > > here, as we are talking about a board specific hack and the whole point > > > appears to be running unmodified user space. > > > > > > Regarding how to get the data into the kernel in the first place, my > > > preferred choice would still be to have an intermediate bootloader > > > such as pxa-impedance-matcher, but I won't complain if others are > > > happy enough about putting it into the ATAGS compat code we already > > > have, as long as it's limited to the boards we know need it. > > > > Assuming you have a N700 board file for special procfs code, then why > > not getting at the atags in memory where the bootloader has put them > > directly from that same board file? This way it'll really be limited to > > the board we know needs it and the special exception will be contained > > to that one file. Amongst the machine specific hooks, there is one that > > gets invoked early during boot before those atags are overwritten. > > I didn't realize this was possible, as we don't know the atags pointer > when we instead get a DTB pointer. However you are right: the board > file knows exactly that the atag_offset is 0x100, so we can grab it > from there, and that will make the implementation really easy and > contained to a single file that has access to the atags and that > can create the /proc/atags file for it. I've made several suggestions over the year or so that this problem has been around, and solving this problem appears to be getting nowhere... (because we _still_ have the problem today.) When the same suggestions start to be made by other people, I think there's not much more that can be done to help resolve the situation. It's probably time to walk away from the problem, and let those who are supposedly motivated to use these troublesome platforms just get on with it. I'm not sure what Tony does at this point: if he rips out the non-DT OMAP code, it'll cause a regression, but at the same time, it provides additional motivation to get the problem resolved. I can quite well see Pavel going off and whinging at Linus, Linus getting stressed at us for intentionally breaking something that used to work, and telling everyone that they shouldn't be working on the kernel, in his usual friendly way. So, I think if the non-DT OMAP stuff is getting in the way of further OMAP development, then the only solution is to put pressure on those who are holding it up: in other words, put pressure on those to get this damned problem solved. The only thing I can think of doing is to give the N900 people notice that they're causing a problem here, explaining exactly why - maybe explaining that it's been causing a problem however long it has and that the only option is going to be to fork mainline and effectively leave the code in mainline unmaintained because of this. Then, of course, those who have caused this situation then get the fun job of maintaining _all_ the OMAP code in mainline on their own, which I think would bury them under such a huge mountain that the code would end up being terminally broken, and ripe for deletion. At which point, it'd make sense to merge the maintained fork back into mainline, which of course wouldn't have the troublesome code platforms by that time. :) Yes, it's not particularly nice, but I don't see this problem getting resolved. (Maybe this email will be enough to motivate the N900 users to sort this out, but I suspect they'll prefer to spend time whinging and moaning at me in email rather than doing what needs to be done and fixing the problem.) -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] arm: boot: store ATAGs structure into DT "/chosen/linux,atags" entry
On Fri, Nov 27, 2015 at 06:28:50PM -0500, Nicolas Pitre wrote: > On Fri, 27 Nov 2015, Arnd Bergmann wrote: > > > I don't mind creating the /proc/atags compatibility hack from the kernel > > for a DT based N700 kernel, as long as we limit it as much as we can > > to the machines that need it. Leaving a board file for the N700 in place > > that contains the procfs code (and not much more) seems reasonable > > here, as we are talking about a board specific hack and the whole point > > appears to be running unmodified user space. > > > > Regarding how to get the data into the kernel in the first place, my > > preferred choice would still be to have an intermediate bootloader > > such as pxa-impedance-matcher, but I won't complain if others are > > happy enough about putting it into the ATAGS compat code we already > > have, as long as it's limited to the boards we know need it. > > Assuming you have a N700 board file for special procfs code, then why > not getting at the atags in memory where the bootloader has put them > directly from that same board file? This way it'll really be limited to > the board we know needs it and the special exception will be contained > to that one file. Amongst the machine specific hooks, there is one that > gets invoked early during boot before those atags are overwritten. I've already suggested that. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] arm: boot: store ATAGs structure into DT "/chosen/linux,atags" entry
On Friday 27 November 2015 18:28:50 Nicolas Pitre wrote: > On Fri, 27 Nov 2015, Arnd Bergmann wrote: > > > I don't mind creating the /proc/atags compatibility hack from the kernel > > for a DT based N700 kernel, as long as we limit it as much as we can > > to the machines that need it. Leaving a board file for the N700 in place > > that contains the procfs code (and not much more) seems reasonable > > here, as we are talking about a board specific hack and the whole point > > appears to be running unmodified user space. > > > > Regarding how to get the data into the kernel in the first place, my > > preferred choice would still be to have an intermediate bootloader > > such as pxa-impedance-matcher, but I won't complain if others are > > happy enough about putting it into the ATAGS compat code we already > > have, as long as it's limited to the boards we know need it. > > Assuming you have a N700 board file for special procfs code, then why > not getting at the atags in memory where the bootloader has put them > directly from that same board file? This way it'll really be limited to > the board we know needs it and the special exception will be contained > to that one file. Amongst the machine specific hooks, there is one that > gets invoked early during boot before those atags are overwritten. I didn't realize this was possible, as we don't know the atags pointer when we instead get a DTB pointer. However you are right: the board file knows exactly that the atag_offset is 0x100, so we can grab it from there, and that will make the implementation really easy and contained to a single file that has access to the atags and that can create the /proc/atags file for it. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH (v5) 3/11] MIPS: bmips: Add bcm6345-l2-timer interrupt controller
Add the BCM6345/BCM6318 timer as an interrupt controller so that it can be
used by the watchdog to warn that its timer will expire soon.
Support for clocksource/clockevents is not implemented as the timer
interrupt is not per CPU (except on the BCM6318) and the MIPS clock is
better. This could be added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
On 27/11/15 08:37, Thomas Gleixner wrote:
> Instead of having that pile of conditionals you could just define two
> functions and have a function pointer in struct bcm6345_timer which
> you initialize at init time.
Fixed.
>> +static inline void bcm6345_timer_write_control(struct bcm6345_timer *timer,
>> + unsigned int id, u32 val)
>> +{
>> + if (id >= timer->nr_timers) {
>> + WARN(1, "%s: %d >= %d", __func__, id, timer->nr_timers);
>
> Hmm?
I've now removed this.
>> +static void bcm6345_timer_unmask(struct irq_data *d)
>> +{
>> + struct bcm6345_timer *timer = irq_data_get_irq_chip_data(d);
>> + unsigned long flags;
>> + u8 val;
>> +
>> + if (d->hwirq < timer->nr_timers) {
>
> Again. You can have two different interrupt chips without that
> completely undocumented and non obvious conditional.
Fixed.
> BTW, how are those simple interrupts masked at all?
The interrupt for the watchdog can't be masked. I've now used a noop
function for irq_enable/irq_disable.
>> + timer->nr_timers = nr_timers;
>> + timer->nr_interrupts = nr_timers + 1;
>
> What is that extra interrupt about? For the casual reader this looks
> like a bug ... Comments exist for a reason.
Fixed.
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-l2-timer.c | 386 +
3 files changed, 392 insertions(+)
create mode 100644 drivers/irqchip/irq-bcm6345-l2-timer.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index d307bb3..21c3d9b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -70,6 +70,11 @@ config BCM6345_L1_IRQ
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
+config BCM6345_L2_TIMER_IRQ
+ bool
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+
config BCM7038_L1_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ded59cf..2687dea 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_XTENSA_MX) +=
irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_SOC_VF610)+= irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
+obj-$(CONFIG_BCM6345_L2_TIMER_IRQ) += irq-bcm6345-l2-timer.o
obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
diff --git a/drivers/irqchip/irq-bcm6345-l2-timer.c
b/drivers/irqchip/irq-bcm6345-l2-timer.c
new file mode 100644
index 000..f3acda7
--- /dev/null
+++ b/drivers/irqchip/irq-bcm6345-l2-timer.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Based on arch/mips/bcm63xx/timer.c:
+ * Copyright (C) 2008 Maxime Bizon
+ *
+ * Registers for SoCs with 4 timers: BCM6345, BCM6328, BCM6362, BCM6816,
+ * BCM68220,BCM63168, BCM63268
+ * 0x02: Interrupt enable (u8)
+ * 0x03: Interrupt status (u8)
+ * 0x04: Timer 0 control
+ * 0x08: Timer 1 control
+ * 0x0c: Timer 2 control
+ * 0x10: Timer 0 count
+ * 0x14: Timer 1 count
+ * 0x18: Timer 2 count
+ * 0x1c+: Watchdog registers
+ *
+ * Registers for SoCs with 5 timers: BCM6318
+ * 0x00: Interrupt enable (u32)
+ * 0x04: Interrupt status (u32)
+ * 0x08: Timer 0 control
+ * 0x0c: Timer 1 control
+ * 0x10: Timer 2 control
+ * 0x14: Timer 3 control
+ * 0x18: Timer 0 count
+ * 0x1c: Timer 1 count
+ * 0x20: Timer 2 count
+ * 0x24: Timer 3 count
+ * 0x28+: Watchdog registers
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum timer_regs {
+ /* Interrupt enable register:
+* 1 bit per timer (without the watchdog)
+*/
+ TIMER_INT_ENABLE = 0,
+
+ /* Interrupt status register:
+* 1 bit per timer (plus
Re: [PATCH V5 RESEND 2/3] iommu/hisilicon: Add hi6220-SoC smmu driver
On Sat, Nov 28, 2015 at 10:19:14AM +0800, chenfeng wrote: > On 2015/11/27 20:02, Joerg Roedel wrote: > > You need to create an iommu-group per smmu in your system and put all > > devices translated by this smmu in that group. And then you must change > > your code to allow attaching/detaching this iommu-group to different > > domains. > > > I read the code,I am confused about these concepts. > In my opinion, > IOMMU-Domain: The masters in one domain share the same iova space. Is that > right? Yes, an iommu-domain is an abstraction of a single page-table and describes one iova address space. The SMMU in your hardware supports only on page-table, so all devices behind it share a single iova address space, und must be in the same domain. But the way you implemented it there could be only one domain per SMMU. With the IOMMU-API we must support to change the domain of an SMMU. Think of one domain for DMA-API usage and another for VFIO, for example. > IOMMU-GROUP: As you mentioned up,all devices translated by this smmu > should be into one group. I can do this. But if there is only on > domain in the system, how can I attaching/detaching the group to > different domains. IOMMU-groups describe the isolation capabilities of the IOMMU between devices. If devices are in a different IOMMU-group, this means that the hardware can isolate them from each other. Attaching the devices in a group to a new domain means in your case, that you set a different page-table for them. Since you can only do that for all devices behind a SMMU, these devices must be in on IOMMU-group. Joerg -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND 1/8] arm: dts: berlin2q: add watchdog nodes
On 23.11.2015 05:59, Jisheng Zhang wrote:
> On Fri, 20 Nov 2015 21:19:46 +0100
> Sebastian Hesselbarth wrote:
>> On 20.11.2015 04:34, Jisheng Zhang wrote:
>>> On Thu, 19 Nov 2015 21:47:05 +0100
>>> Sebastian Hesselbarth wrote:
On 16.11.2015 12:09, Jisheng Zhang wrote:
> The Marvell Berlin BG2Q has 3 watchdogs which are compatible with the
> snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
> corresponding device tree nodes.
>
> Signed-off-by: Jisheng Zhang
> ---
[...]
> + wdt0: watchdog@1000 {
> + compatible = "snps,dw-wdt";
> + reg = <0x1000 0x100>;
> + clocks = <&refclk>;
> + interrupts = <0>;
> + status = "disabled";
as the watchdogs are internal and cannot be clock gated
at all, how about we remove the status = "disabled" and
make them always available?
>>>
>>> there are two issues here:
>>>
>>> 1. the dw-wdt can't support multiple variants now. I have rewrite the driver
>>> with watchdog core supplied framework, but the patch isn't sent out and
>>> may be need time to clean up and review.
>>
>> Ok.
>>
>>> 2. not all dw-wdt devices are available and functional. This depends on
>>> board design and configuration.
>>
>> I understand that "board design and configuration" may hinder the wdt
>> to issue a hard reset. But all others are able to issue a soft reset
>> or just an interrupt, right?
>>
>> So, I still don't see why we should disable wdt nodes by default
>> except for the driver issue above.
>>
>>> So IMHO status=disabled and patch5-8 is necessary, what do you think?
>>
>> No. I'd agree to enable wdt0 by default and leave wdt[1,2] disabled
>> because of the driver issue. Patches 5-8 only enable wdt0 anyway.
>
> That's fine.
Jisheng,
I amended your SoC dtsi watchdog patches accordingly. wdt0 is
now always enabled, while the others are disabled.
So, with the changes Patches 1-4 applied to berlin/dt and berlin64/dt
respectively. Patches 5-8 dropped.
>> As soon as the driver issue is resolved, we enable all wdt nodes
>> unconditionally.
>
> I will submit patch for the wdt driver and hope it will be merged
> in v4.5.
Ok. Feel free to add a patch that removes the status disabled properties
again if berlin[64]/dt has already hit mainline in the meantime.
If not, keep me posted on the DW wdt patch outcome.
Thanks,
Sebastian
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Re: [PATCH] arm: dts: berlin2q-marvell-dmp: add sdhci1 fully functionality
On 26.11.2015 14:13, Jisheng Zhang wrote:
> The sdhci1 on Marvell BG2Q DMP board is used as sdcard interface, we
> have gpios for card detection, write-protect, vqmmc and vmmc.
>
> This patch adds pinmux for this sdcard interface, then adds regulators
> for vmmc and vqmmc, lastly adds cd-gpios, wp-gpios properties.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 43
> --
> 1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
> b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
> index cdcf89b..1fdc1d7 100644
> --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
> +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
> @@ -84,12 +84,51 @@
> gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + reg_sdio1_vmmc: regulator@3 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "sdio1_vmmc";
> + enable-active-high;
> + regulator-boot-on;
> + gpio = <&portb 21 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_sdio1_vqmmc: regulator@4 {
> + compatible = "regulator-gpio";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "sdio1_vqmmc";
> + regulator-type = "voltage";
> + enable-active-high;
> + gpios = <&portb 16 GPIO_ACTIVE_HIGH>;
> + states = <330 0x1
> + 180 0x0>;
> + };
> + };
> +};
> +
> +&soc_pinctrl {
> + sd1gpio_pmux: sd1pwr-pmux {
> + groups = "G23", "G32";
> + function = "gpio";
> + };
> +
> + sd1_pmux: sd1-pmux {
> + groups = "G31";
> + function = "sd1";
Jisheng,
while having the sd1gpio_pmux in the board file, I think the
sd1_pmux is best kept in the SoC.dtsi.
> };
> };
>
> &sdhci1 {
> - broken-cd;
> - sdhci,wp-inverted;
> + vmmc-supply = <®_sdio1_vmmc>;
> + vqmmc-supply = <®_sdio1_vqmmc>;
> + cd-inverted;
> + cd-gpios = <&portc 30 GPIO_ACTIVE_HIGH>;
How about removing cd-inverted and make cd-gpio GPIO_ACTIVE_LOW
instead?
Sebastian
> + wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>;
> + pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>;
> + pinctrl-names = "default";
> status = "okay";
> };
>
>
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[PATCH 4/4] ARM: dt: mvebu: ix4-300d: Add ECC properties to NAND flash
The NAND device found on Lenovo ix4-300d uses 4-bit BCH ECC protection.
Add the corresponding properties to the NAND node.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Russell King
Cc: Benoit Masson
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 13cf69a8d0fb..e4bf83c4bd2f 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -150,6 +150,8 @@
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
partitions {
#address-cells = <1>;
--
2.1.4
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[PATCH 3/4] ARM: dt: mvebu: ix4-300d: Cleanup NAND partition ranges
Prefix all partition reg properties to 32-bit to ease readability.
While at it, also remove a stale x in front of boot partition
offset and make some upper-case hex numbers lower-case.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Russell King
Cc: Benoit Masson
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 76781fd18624..13cf69a8d0fb 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -157,35 +157,35 @@
partition@0 {
label = "u-boot";
- reg = <0x000 0xe>;
+ reg = <0x 0x000e>;
read-only;
};
partition@e {
label = "u-boot-env";
- reg = <0xe 0x2>;
+ reg = <0x000e 0x0002>;
read-only;
};
partition@10 {
label = "u-boot-env2";
- reg = <0x10 0x2>;
+ reg = <0x0010 0x0002>;
read-only;
};
partition@12 {
label = "zImage";
- reg = <0x12 0x40>;
+ reg = <0x0012 0x0040>;
};
partition@52 {
label = "initrd";
- reg = <0x52 0x40>;
+ reg = <0x0052 0x0040>;
};
- partition@xE0 {
+ partition@e0 {
label = "boot";
- reg = <0xE0 0x3F20>;
+ reg = <0x00e0 0x3f20>;
};
};
};
--
2.1.4
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[PATCH 2/4] ARM: dt: mvebu: ix4-300d: move partitions to partition sub-node
NAND flash partitions should be part of a partitions sub-node
not the flash node itself. Move the partitions which will also
allow different bootloaders get rid of the stock partitions
easily by removing the partitions node.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Russell King
Cc: Benoit Masson
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 67 +
1 file changed, 36 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 30a0a6eac645..76781fd18624 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -151,37 +151,42 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
- partition@0 {
- label = "u-boot";
- reg = <0x000 0xe>;
- read-only;
- };
-
- partition@e {
- label = "u-boot-env";
- reg = <0xe 0x2>;
- read-only;
- };
-
- partition@10 {
- label = "u-boot-env2";
- reg = <0x10 0x2>;
- read-only;
- };
-
- partition@12 {
- label = "zImage";
- reg = <0x12 0x40>;
- };
-
- partition@52 {
- label = "initrd";
- reg = <0x52 0x40>;
- };
-
- partition@xE0 {
- label = "boot";
- reg = <0xE0 0x3F20>;
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x000 0xe>;
+ read-only;
+ };
+
+ partition@e {
+ label = "u-boot-env";
+ reg = <0xe 0x2>;
+ read-only;
+ };
+
+ partition@10 {
+ label = "u-boot-env2";
+ reg = <0x10 0x2>;
+ read-only;
+ };
+
+ partition@12 {
+ label = "zImage";
+ reg = <0x12 0x40>;
+ };
+
+ partition@52 {
+ label = "initrd";
+ reg = <0x52 0x40>;
+ };
+
+ partition@xE0 {
+ label = "boot";
+ reg = <0xE0 0x3F20>;
+ };
};
};
};
--
2.1.4
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[PATCH 0/4] ARM: dt: mvebu: ix4-300d: NAND cleanup and ECC
This is a list of patches cleaning up some things I noticed while working with barebox boot loader support for NAND node of Lenovo ix4-300d. Patch 1 removes a flash partition node for the whole flash. The flash as a whole is already best represented by the NAND device itself. Patch 2 moves the stock flash partitions to a partitions sub-node. This will also ease removal of stock flash partition layout for barebox and other boot loaders. Patch 3 cleans the flash partitions ranges by prefixing them to 32-bit lower-case hex numbers. Also, a stale 'x' is removed from one partition name offset. Patch 4 finally adds ECC properties for 4-bit BCH ECC used by the ix4-300d flash. Sebastian Sebastian Hesselbarth (4): ARM: dt: mvebu: ix4-300d: remove whole flash partition ARM: dt: mvebu: ix4-300d: move partitions to partition sub-node ARM: dt: mvebu: ix4-300d: Cleanup NAND partition ranges ARM: dt: mvebu: ix4-300d: Add ECC properties to NAND flash arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 76 + 1 file changed, 39 insertions(+), 37 deletions(-) --- Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Russell King Cc: Benoit Masson Cc: linux-arm-ker...@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-ker...@vger.kernel.org -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: dt: mvebu: ix4-300d: remove whole flash partition
Current NAND node has an additional flash partition for the whole
flash overlapping with real partitions. Remove this partition as
the whole flash is already represented by the NAND device itself.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Russell King
Cc: Benoit Masson
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 58b500873bfd..30a0a6eac645 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -183,11 +183,6 @@
label = "boot";
reg = <0xE0 0x3F20>;
};
-
- partition@flash {
- label = "flash";
- reg = <0x0 0x4000>;
- };
};
};
};
--
2.1.4
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[PATCH v2 10/10] drm/hisilicon: Add support for external bridge
Add support for external HDMI bridge.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/hisi_drm_dsi.c | 51
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
index 066e08d..9e056db 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
@@ -78,6 +78,7 @@ struct dsi_hw_ctx {
struct hisi_dsi {
struct drm_encoder encoder;
+ struct drm_bridge *bridge;
struct mipi_dsi_host host;
struct drm_display_mode cur_mode;
struct dsi_hw_ctx *ctx;
@@ -671,6 +672,25 @@ static int dsi_host_init(struct device *dev, struct
hisi_dsi *dsi)
return 0;
}
+static int dsi_bridge_init(struct drm_device *dev, struct hisi_dsi *dsi)
+{
+ struct drm_encoder *encoder = &dsi->encoder;
+ struct drm_bridge *bridge = dsi->bridge;
+ int ret;
+
+ /* associate the bridge to dsi encoder */
+ encoder->bridge = bridge;
+ bridge->encoder = encoder;
+
+ ret = drm_bridge_attach(dev, bridge);
+ if (ret) {
+ DRM_ERROR("failed to attach exteranl bridge\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int dsi_bind(struct device *dev, struct device *master, void *data)
{
struct dsi_data *ddata = dev_get_drvdata(dev);
@@ -686,6 +706,10 @@ static int dsi_bind(struct device *dev, struct device
*master, void *data)
if (ret)
return ret;
+ ret = dsi_bridge_init(drm_dev, dsi);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -702,8 +726,35 @@ static const struct component_ops dsi_ops = {
static int dsi_parse_dt(struct platform_device *pdev, struct hisi_dsi *dsi)
{
struct dsi_hw_ctx *ctx = dsi->ctx;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *endpoint, *bridge_node;
+ struct drm_bridge *bridge;
struct resource *res;
+ /*
+* Get the endpoint node. In our case, dsi has one output port
+* to which the external HDMI bridge is connected.
+*/
+ endpoint = of_graph_get_next_endpoint(np, NULL);
+ if (!endpoint) {
+ DRM_ERROR("no valid endpoint node\n");
+ return -ENODEV;
+ }
+ of_node_put(endpoint);
+
+ bridge_node = of_graph_get_remote_port_parent(endpoint);
+ if (!bridge_node) {
+ DRM_ERROR("no valid bridge node\n");
+ return -ENODEV;
+ }
+ of_node_put(bridge_node);
+
+ bridge = of_drm_find_bridge(bridge_node);
+ if (!bridge) {
+ DRM_INFO("wait for external HDMI bridge driver.\n");
+ return -EPROBE_DEFER;
+ }
+ dsi->bridge = bridge;
ctx->dsi_cfg_clk = devm_clk_get(&pdev->dev, "pclk_dsi");
if (IS_ERR(ctx->dsi_cfg_clk)) {
--
1.9.1
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[PATCH v2 07/10] drm/hisilicon: Add cma fbdev and hotplug
Add cma Fbdev, Fbdev is legency and optional, you can enable/disable it by
configuring DRM_FBDEV_EMULATION.
Add hotplug.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 34
drivers/gpu/drm/hisilicon/hisi_drm_drv.h | 3 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
index 13f59aa..76eb711 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "hisi_drm_ade.h"
#include "hisi_drm_drv.h"
@@ -30,6 +31,13 @@ static int hisi_drm_unload(struct drm_device *dev)
{
struct hisi_drm_private *priv = dev->dev_private;
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+ if (priv->fbdev) {
+ drm_fbdev_cma_fini(priv->fbdev);
+ priv->fbdev = NULL;
+ }
+#endif
+ drm_kms_helper_poll_fini(dev);
drm_vblank_cleanup(dev);
drm_mode_config_cleanup(dev);
devm_kfree(dev->dev, priv);
@@ -38,8 +46,28 @@ static int hisi_drm_unload(struct drm_device *dev)
return 0;
}
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+static void hisi_fbdev_output_poll_changed(struct drm_device *dev)
+{
+ struct hisi_drm_private *priv = dev->dev_private;
+
+ if (priv->fbdev) {
+ drm_fbdev_cma_hotplug_event(priv->fbdev);
+ } else {
+ priv->fbdev = drm_fbdev_cma_init(dev, 32,
+ dev->mode_config.num_crtc,
+ dev->mode_config.num_connector);
+ if (IS_ERR(priv->fbdev))
+ priv->fbdev = NULL;
+ }
+}
+#endif
+
static const struct drm_mode_config_funcs hisi_drm_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+ .output_poll_changed = hisi_fbdev_output_poll_changed,
+#endif
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
@@ -90,6 +118,12 @@ static int hisi_drm_load(struct drm_device *dev, unsigned
long flags)
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(dev);
+ /* init kms poll for handling hpd */
+ drm_kms_helper_poll_init(dev);
+
+ /* force detection after connectors init */
+ (void)drm_helper_hpd_irq_event(dev);
+
return 0;
err_unbind_all:
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_drv.h
b/drivers/gpu/drm/hisilicon/hisi_drm_drv.h
index a10229e..984121f 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_drv.h
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_drv.h
@@ -11,6 +11,9 @@
#define __HISI_DRM_DRV_H__
struct hisi_drm_private {
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+ struct drm_fbdev_cma *fbdev;
+#endif
};
#endif /* __HISI_DRM_DRV_H__ */
--
1.9.1
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[PATCH v2 03/10] drm/hisilicon: Add hisilicon DRM master driver
Add DRM master driver for hi6220 SoC which used in HiKey board.
Add dumb buffer feature.
Add prime dmabuf feature.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/hisilicon/Kconfig| 9 ++
drivers/gpu/drm/hisilicon/Makefile | 3 +
drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 214 +++
5 files changed, 229 insertions(+)
create mode 100644 drivers/gpu/drm/hisilicon/Kconfig
create mode 100644 drivers/gpu/drm/hisilicon/Makefile
create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.c
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 8773fad..038aae8 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -274,3 +274,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig"
source "drivers/gpu/drm/imx/Kconfig"
source "drivers/gpu/drm/vc4/Kconfig"
+
+source "drivers/gpu/drm/hisilicon/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 1e9ff4c..e7efcb7 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -75,3 +75,4 @@ obj-y += i2c/
obj-y += panel/
obj-y += bridge/
obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
+obj-$(CONFIG_DRM_HISI) += hisilicon/
diff --git a/drivers/gpu/drm/hisilicon/Kconfig
b/drivers/gpu/drm/hisilicon/Kconfig
new file mode 100644
index 000..70aa8d1
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/Kconfig
@@ -0,0 +1,9 @@
+config DRM_HISI
+ tristate "DRM Support for Hisilicon SoCs Platform"
+ depends on DRM
+ select DRM_KMS_HELPER
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_CMA_HELPER
+ help
+ Choose this option if you have a hisilicon chipsets(hi6220).
+ If M is selected the module will be called hisi-drm.
diff --git a/drivers/gpu/drm/hisilicon/Makefile
b/drivers/gpu/drm/hisilicon/Makefile
new file mode 100644
index 000..7375456
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/Makefile
@@ -0,0 +1,3 @@
+hisi-drm-y := hisi_drm_drv.o
+
+obj-$(CONFIG_DRM_HISI) += hisi-drm.o
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
new file mode 100644
index 000..445e2ec
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
@@ -0,0 +1,214 @@
+/*
+ * Hisilicon SoCs drm master driver
+ *
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ * Author:
+ * Xinliang Liu
+ * Xinliang Liu
+ * Xinwei Kong
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#define DRIVER_NAME"hisi-drm"
+
+static int hisi_drm_unload(struct drm_device *dev)
+{
+ drm_mode_config_cleanup(dev);
+ return 0;
+}
+
+static const struct drm_mode_config_funcs hisi_drm_mode_config_funcs = {
+ .fb_create = drm_fb_cma_create,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void hisi_drm_mode_config_init(struct drm_device *dev)
+{
+ dev->mode_config.min_width = 0;
+ dev->mode_config.min_height = 0;
+
+ dev->mode_config.max_width = 2048;
+ dev->mode_config.max_height = 2048;
+
+ dev->mode_config.funcs = &hisi_drm_mode_config_funcs;
+}
+
+static int hisi_drm_load(struct drm_device *dev, unsigned long flags)
+{
+ int ret;
+
+ dev_set_drvdata(dev->dev, dev);
+
+ /* dev->mode_config initialization */
+ drm_mode_config_init(dev);
+ hisi_drm_mode_config_init(dev);
+
+ /* bind and init sub drivers */
+ ret = component_bind_all(dev->dev, dev);
+ if (ret) {
+ DRM_ERROR("failed to bind all component.\n");
+ goto err_mode_config_cleanup;
+ }
+
+ /* reset all the states of crtc/plane/encoder/connector */
+ drm_mode_config_reset(dev);
+
+ return 0;
+
+err_mode_config_cleanup:
+ drm_mode_config_cleanup(dev);
+
+ return ret;
+}
+
+static const struct file_operations hisi_drm_fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+ .release= drm_release,
+ .unlocked_ioctl = drm_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = drm_compat_ioctl,
+#endif
+ .poll = drm_poll,
+ .read = drm_read,
+ .llseek = no_llseek,
+ .mmap = drm_gem_cma_mmap,
+};
+
+static struct dma_buf *hisi_gem_prime_export(struct drm_device *dev,
+struct drm_gem_object *obj,
+int flags)
+{
+ /* we want to be able to write in mmapped buffer */
+ flags |= O_RDWR;
+ return drm_gem_prime_e
[PATCH v2 06/10] drm/hisilicon: Add vblank feature
Add vblank handle for ADE.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/hisi_drm_ade.c | 78
drivers/gpu/drm/hisilicon/hisi_drm_ade.h | 16 +++
drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 19 +++-
3 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_ade.h
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
index b0976c3..acb11e7 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
@@ -267,7 +267,79 @@ static void ade_power_down(struct ade_hw_ctx *ctx)
ctx->power_on = false;
}
+static struct drm_crtc *hisi_get_crtc_from_index(struct drm_device *dev,
+unsigned int index)
+{
+ unsigned int index_tmp = 0;
+ struct drm_crtc *crtc;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ if (index_tmp == index)
+ return crtc;
+
+ index_tmp++;
+ }
+
+ WARN_ON(true);
+}
+
+int ade_enable_vblank(struct drm_device *dev, int crtc_index)
+{
+ struct drm_crtc *crtc = hisi_get_crtc_from_index(dev, crtc_index);
+ struct ade_crtc *acrtc = to_ade_crtc(crtc);
+ struct ade_hw_ctx *ctx = acrtc->ctx;
+ void __iomem *base = ctx->base;
+ u32 intr_en;
+
+ DRM_INFO("enable_vblank enter.\n");
+ if (!ctx->power_on)
+ (void)ade_power_up(ctx);
+
+ intr_en = readl(base + LDI_INT_EN);
+ intr_en |= LDI_ISR_FRAME_END_INT;
+ writel(intr_en, base + LDI_INT_EN);
+ return 0;
+}
+
+void ade_disable_vblank(struct drm_device *dev, int crtc_index)
+{
+ struct drm_crtc *crtc = hisi_get_crtc_from_index(dev, crtc_index);
+ struct ade_crtc *acrtc = to_ade_crtc(crtc);
+ struct ade_hw_ctx *ctx = acrtc->ctx;
+ void __iomem *base = ctx->base;
+ u32 intr_en;
+
+ DRM_INFO("disable_vblank enter.\n");
+ if (!ctx->power_on) {
+ DRM_ERROR("power is down! vblank disable fail\n");
+ return;
+ }
+ intr_en = readl(base + LDI_INT_EN);
+ intr_en &= ~LDI_ISR_FRAME_END_INT;
+ writel(intr_en, base + LDI_INT_EN);
+}
+
+static irqreturn_t ade_irq_handler(int irq, void *data)
+{
+ struct ade_crtc *acrtc = data;
+ struct ade_hw_ctx *ctx = acrtc->ctx;
+ struct drm_crtc *crtc = &acrtc->base;
+ struct drm_device *dev = crtc->dev;
+ void __iomem *base = ctx->base;
+ u32 status;
+
+ status = readl(base + LDI_MSK_INT);
+ /* DRM_INFO("LDI IRQ: status=0x%X\n",status); */
+
+ /* vblank irq */
+ if (status & LDI_ISR_FRAME_END_INT) {
+ writel(LDI_ISR_FRAME_END_INT, base + LDI_INT_CLR);
+ drm_handle_vblank(dev, drm_crtc_index(crtc));
+ }
+
+ return IRQ_HANDLED;
+}
/*
* set modules' reset mode: by software or hardware
@@ -858,6 +930,12 @@ static int ade_bind(struct device *dev, struct device
*master, void *data)
if (ret)
return ret;
+ /* vblank irq init */
+ ret = request_irq(ctx->irq, ade_irq_handler, DRIVER_IRQ_SHARED,
+ drm_dev->driver->name, acrtc);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_ade.h
b/drivers/gpu/drm/hisilicon/hisi_drm_ade.h
new file mode 100644
index 000..d1d7b5d
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __HISI_DRM_ADE_H__
+#define __HISI_DRM_ADE_H__
+
+int ade_enable_vblank(struct drm_device *dev, int crtc_index);
+void ade_disable_vblank(struct drm_device *dev, int crtc_index);
+
+#endif
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
index d0eca80..13f59aa 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_drv.c
@@ -21,6 +21,7 @@
#include
#include
+#include "hisi_drm_ade.h"
#include "hisi_drm_drv.h"
#define DRIVER_NAME"hisi-drm"
@@ -29,6 +30,7 @@ static int hisi_drm_unload(struct drm_device *dev)
{
struct hisi_drm_private *priv = dev->dev_private;
+ drm_vblank_cleanup(dev);
drm_mode_config_cleanup(dev);
devm_kfree(dev->dev, priv);
dev->dev_private = NULL;
@@ -76,11 +78,22 @@ static int hisi_drm_load(struct drm_device *dev, unsigned
long flags)
goto err_mode_config_cleanup;
}
+ /* vblank init */
+ ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
+ if (ret)
[PATCH v2 08/10] drm/hisilicon: Add dsi encoder driver
Add dsi encoder driver for hi6220 SoC.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/Kconfig| 1 +
drivers/gpu/drm/hisilicon/Makefile | 3 +-
drivers/gpu/drm/hisilicon/hisi_drm_dsi.c | 728 +++
drivers/gpu/drm/hisilicon/hisi_dsi_reg.h | 89
4 files changed, 820 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
create mode 100644 drivers/gpu/drm/hisilicon/hisi_dsi_reg.h
diff --git a/drivers/gpu/drm/hisilicon/Kconfig
b/drivers/gpu/drm/hisilicon/Kconfig
index 70aa8d1..f1c33c2 100644
--- a/drivers/gpu/drm/hisilicon/Kconfig
+++ b/drivers/gpu/drm/hisilicon/Kconfig
@@ -4,6 +4,7 @@ config DRM_HISI
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
+ select DRM_MIPI_DSI
help
Choose this option if you have a hisilicon chipsets(hi6220).
If M is selected the module will be called hisi-drm.
diff --git a/drivers/gpu/drm/hisilicon/Makefile
b/drivers/gpu/drm/hisilicon/Makefile
index 3433c8b..5083c1f 100644
--- a/drivers/gpu/drm/hisilicon/Makefile
+++ b/drivers/gpu/drm/hisilicon/Makefile
@@ -1,4 +1,5 @@
hisi-drm-y := hisi_drm_drv.o \
- hisi_drm_ade.o
+ hisi_drm_ade.o \
+ hisi_drm_dsi.o
obj-$(CONFIG_DRM_HISI) += hisi-drm.o
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
new file mode 100644
index 000..7a6cf66
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
@@ -0,0 +1,728 @@
+/*
+ * Hisilicon hi6220 SoC dsi driver
+ *
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ * Author:
+ * Xinliang Liu
+ * Xinliang Liu
+ * Xinwei Kong
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "hisi_dsi_reg.h"
+
+#define MAX_TX_ESC_CLK(10)
+#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
+#define DEFAULT_MIPI_CLK_RATE 1920
+#define DEFAULT_MIPI_CLK_PERIOD_PS (10 / (DEFAULT_MIPI_CLK_RATE /
1000))
+#define R(x) ((u32)u64)(x) * (u64)1000 * (u64)mode->clock) / \
+ phy->lane_byte_clk_kHz)))
+
+#define encoder_to_dsi(encoder) \
+ container_of(encoder, struct hisi_dsi, encoder)
+#define host_to_dsi(host) \
+ container_of(host, struct hisi_dsi, host)
+
+struct mipi_phy_register {
+ u32 clk_t_lpx;
+ u32 clk_t_hs_prepare;
+ u32 clk_t_hs_zero;
+ u32 clk_t_hs_trial;
+ u32 clk_t_wakeup;
+ u32 data_t_lpx;
+ u32 data_t_hs_prepare;
+ u32 data_t_hs_zero;
+ u32 data_t_hs_trial;
+ u32 data_t_ta_go;
+ u32 data_t_ta_get;
+ u32 data_t_wakeup;
+ u32 hstx_ckg_sel;
+ u32 pll_fbd_div5f;
+ u32 pll_fbd_div1f;
+ u32 pll_fbd_2p;
+ u32 pll_enbwt;
+ u32 pll_fbd_p;
+ u32 pll_fbd_s;
+ u32 pll_pre_div1p;
+ u32 pll_pre_p;
+ u32 pll_vco_750M;
+ u32 pll_lpf_rs;
+ u32 pll_lpf_cs;
+ u32 clklp2hs_time;
+ u32 clkhs2lp_time;
+ u32 lp2hs_time;
+ u32 hs2lp_time;
+ u32 clk_to_data_delay;
+ u32 data_to_clk_delay;
+ u32 lane_byte_clk_kHz;
+ u32 clk_division;
+};
+
+struct dsi_hw_ctx {
+ void __iomem *base;
+ struct clk *dsi_cfg_clk;
+};
+
+struct hisi_dsi {
+ struct drm_encoder encoder;
+ struct drm_display_mode cur_mode;
+ struct dsi_hw_ctx *ctx;
+ struct mipi_phy_register phy;
+
+ u32 lanes;
+ enum mipi_dsi_pixel_format format;
+ unsigned long mode_flags;
+ bool enable;
+};
+
+struct dsi_data {
+ struct hisi_dsi dsi;
+ struct dsi_hw_ctx ctx;
+};
+
+struct dsi_phy_seq_info {
+ u32 min_range_kHz;
+ u32 max_range_kHz;
+ u32 pll_vco_750M;
+ u32 hstx_ckg_sel;
+};
+
+static const struct dsi_phy_seq_info dphy_seq_info[] = {
+ { 46000,62000, 1,7 },
+ { 62000,93000, 0,7 },
+ { 93000, 125000, 1,6 },
+ { 125000, 187000, 0,6 },
+ { 187000, 25, 1,5 },
+ { 25, 375000, 0,5 },
+ { 375000, 50, 1,4 },
+ { 50, 75, 0,4 },
+ { 75, 100, 1,0 },
+ { 100, 150, 0,0 }
+};
+
+static void set_dsi_phy_rate_equal_or_faster(u32 phy_freq_kHz,
+struct mipi_phy_register *phy)
+{
+ u32 ui = 0;
+ u32 cfg_clk_ps = DEFAULT_MIPI_CLK_PERIOD_PS;
+ u32 i = 0;
+ u32 q_pll = 1;
+ u32 m_pll = 0;
+ u32 n_pll = 0;
+ u32 r_pll = 1;
+ u32 m_n = 0;
+ u32 m_n_int = 0;
+ u64 f_kHz;
+ u6
[PATCH v2 05/10] drm/hisilicon: Add plane funcs for ADE
Add plane funcs and helper funcs for ADE.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/hisi_drm_ade.c | 479 +++
1 file changed, 479 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
index d157879..b0976c3 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
@@ -23,15 +23,22 @@
#include
#include
#include
+#include
+#include
+#include
#include "hisi_drm_drv.h"
#include "hisi_ade_reg.h"
#define FORCE_PIXEL_CLOCK_SAME_OR_HIGHER 0
+#define PRIMARY_CH (ADE_CH1)
#define to_ade_crtc(crtc) \
container_of(crtc, struct ade_crtc, base)
+#define to_ade_plane(plane) \
+ container_of(plane, struct ade_plane, base)
+
struct ade_hw_ctx {
void __iomem *base;
void __iomem *media_base;
@@ -53,11 +60,75 @@ struct ade_crtc {
u64 use_mask;
};
+struct ade_plane {
+ struct drm_plane base;
+ void *ctx;
+ u8 ch; /* channel */
+};
+
struct ade_data {
struct ade_crtc acrtc;
+ struct ade_plane aplane[ADE_CH_NUM];
struct ade_hw_ctx ctx;
};
+/* ade-format info: */
+struct ade_format {
+ u32 pixel_format;
+ enum ADE_FORMAT ade_format;
+};
+
+static const struct ade_format ade_formats[] = {
+ /* 16bpp RGB: */
+ { DRM_FORMAT_RGB565, ADE_RGB_565 },
+ { DRM_FORMAT_BGR565, ADE_BGR_565 },
+ /* 24bpp RGB: */
+ { DRM_FORMAT_RGB888, ADE_RGB_888 },
+ { DRM_FORMAT_BGR888, ADE_BGR_888 },
+ /* 32bpp [A]RGB: */
+ { DRM_FORMAT_XRGB, ADE_XRGB_ },
+ { DRM_FORMAT_XBGR, ADE_XBGR_ },
+ { DRM_FORMAT_RGBA, ADE_RGBA_ },
+ { DRM_FORMAT_BGRA, ADE_BGRA_ },
+ { DRM_FORMAT_ARGB, ADE_ARGB_ },
+ { DRM_FORMAT_ABGR, ADE_ABGR_ },
+};
+
+static const u32 channel_formats1[] = {
+ /* channel 1,2,3,4 */
+ DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888, DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBA, DRM_FORMAT_BGRA, DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR
+};
+
+u32 ade_get_channel_formats(u8 ch, const u32 **formats)
+{
+ switch (ch) {
+ case ADE_CH1:
+ *formats = channel_formats1;
+ return ARRAY_SIZE(channel_formats1);
+ default:
+ DRM_ERROR("no this channel %d\n", ch);
+ *formats = NULL;
+ return 0;
+ }
+}
+
+/* convert from fourcc format to ade format */
+static u32 ade_get_format(u32 pixel_format)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
+ if (ade_formats[i].pixel_format == pixel_format)
+ return ade_formats[i].ade_format;
+
+ /* not found */
+ DRM_ERROR("Not found pixel format!!fourcc_format= %d\n", pixel_format);
+ return ADE_FORMAT_NOT_SUPPORT;
+}
+
static void ade_init(struct ade_hw_ctx *ctx)
{
void __iomem *base = ctx->base;
@@ -377,8 +448,416 @@ static int ade_crtc_init(struct drm_device *dev, struct
drm_crtc *crtc,
return 0;
}
+static void ade_rdma_set(struct ade_crtc *acrtc, struct drm_framebuffer *fb,
+u32 ch, u32 y, u32 in_h, u32 fmt)
+{
+ u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
+ struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
+ struct ade_hw_ctx *ctx = acrtc->ctx;
+ void __iomem *base = ctx->base;
+ u32 stride = fb->pitches[0];
+ u32 addr = (u32)obj->paddr + y * stride;
+
+ DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x,",
+"addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
+ch + 1, y, in_h, stride, (u32)obj->paddr,
+addr, fb->width, fb->height,
+fmt, drm_get_format_name(fb->pixel_format));
+
+ /* get reg offset */
+ reg_ctrl = RD_CH_CTRL(ch);
+ reg_addr = RD_CH_ADDR(ch);
+ reg_size = RD_CH_SIZE(ch);
+ reg_stride = RD_CH_STRIDE(ch);
+ reg_space = RD_CH_SPACE(ch);
+ reg_en = RD_CH_EN(ch);
+
+ /*
+* TODO: set rotation
+*/
+ writel((fmt << 16) & 0x1f, base + reg_ctrl);
+ writel(addr, base + reg_addr);
+ writel((in_h << 16) | stride, base + reg_size);
+ writel(stride, base + reg_stride);
+ writel(in_h * stride, base + reg_space);
+ writel(1, base + reg_en);
+
+ acrtc->use_mask |= BIT(ADE_CH_RDMA_BIT_OFST + ch);
+}
+
+static void ade_rdma_disable(struct ade_crtc *acrtc, u32 ch)
+{
+ struct ade_hw_ctx *ctx = acrtc->ctx;
+ void __iomem *base = ctx->base;
+ u32 reg_en;
+
+ /* get reg offset */
+ reg_en = RD_CH_EN(ch);
+
+ writel(0, base + reg_en);
+ acrtc->use_mask &= ~
[PATCH v2 09/10] drm/hisilicon: Add dsi host driver
Add dsi host driver for hi6220 SoC.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/hisi_drm_dsi.c | 50
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
index 7a6cf66..066e08d 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
@@ -78,6 +78,7 @@ struct dsi_hw_ctx {
struct hisi_dsi {
struct drm_encoder encoder;
+ struct mipi_dsi_host host;
struct drm_display_mode cur_mode;
struct dsi_hw_ctx *ctx;
struct mipi_phy_register phy;
@@ -625,6 +626,51 @@ static int hisi_drm_encoder_init(struct drm_device *dev,
return 0;
}
+static int dsi_host_attach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *mdsi)
+{
+ struct hisi_dsi *dsi = host_to_dsi(host);
+
+ if (mdsi->lanes < 1 || mdsi->lanes > 4) {
+ DRM_ERROR("dsi device params invalid\n");
+ return -EINVAL;
+ }
+
+ dsi->lanes = mdsi->lanes;
+ dsi->format = mdsi->format;
+ dsi->mode_flags = mdsi->mode_flags;
+
+ return 0;
+}
+
+static int dsi_host_detach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *mdsi)
+{
+ /* do nothing */
+ return 0;
+}
+
+static struct mipi_dsi_host_ops dsi_host_ops = {
+ .attach = dsi_host_attach,
+ .detach = dsi_host_detach,
+};
+
+static int dsi_host_init(struct device *dev, struct hisi_dsi *dsi)
+{
+ struct mipi_dsi_host *host = &dsi->host;
+ int ret;
+
+ host->dev = dev;
+ host->ops = &dsi_host_ops;
+ ret = mipi_dsi_host_register(host);
+ if (ret) {
+ DRM_ERROR("failed to register dsi host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int dsi_bind(struct device *dev, struct device *master, void *data)
{
struct dsi_data *ddata = dev_get_drvdata(dev);
@@ -636,6 +682,10 @@ static int dsi_bind(struct device *dev, struct device
*master, void *data)
if (ret)
return ret;
+ ret = dsi_host_init(dev, dsi);
+ if (ret)
+ return ret;
+
return 0;
}
--
1.9.1
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[PATCH v2 00/10] Add New DRM Driver for HiSilicon hi6220 SoC
This patch set adds a new drm driver for HiSilicon hi6220 SoC. Current testing and support board is Hikey board which is one of Linaro 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. Hardware Detail --- The display subsystem of Hi6220 SoC is shown as bellow: +-+ +--+ +-+ +-+ | | | | | | | | | FB |-->| ADE|>| DSI |>| External| | | | | | | | HDMI | +-+ +--+ +-+ +-+ - ADE(Advanced Display Engine) is the display controller. It contains 7 channels, 3 overlay compositors and a LDI. - A channel looks like: DMA-->clip-->scale-->ctrans(or called csc). - Overlay compositor is response to compose planes which come from 7 channels and pass composed image to LDI. - LDI is response to generate timings and RGB data stream. - DSI converts the RGB data stream from ADE to DSI packets. - External HDMI module is connected with DSI bus. Now Hikey use a ADI's ADV7533 external HDMI chip. Change History - Changes in v2: - Remove abtraction layer of plane/crtc/encoder/connector. - Refactor atomic implementation according to Daniel Vetter's guides: http://blog.ffwll.ch/2014/11/atomic-modeset-support-for-kms-drivers.html http://blog.ffwll.ch/2015/09/xdc-2015-atomic-modesetting-for-drivers.html http://blog.ffwll.ch/2015/08/atomic-modesetting-design-overview.html - Use bridge instead of slave encoder to connect external HDMI. - Move dt binding docs to bindings/display/hisilicon directory. Xinliang Liu (10): arm64: dts: hisilicon: Add display subsystem DT nodes for hi6220. drm/hisilicon: Add device tree binding for hi6220 display subsystem drm/hisilicon: Add hisilicon DRM master driver drm/hisilicon: Add crtc funcs for ADE drm/hisilicon: Add plane funcs for ADE drm/hisilicon: Add vblank feature drm/hisilicon: Add cma fbdev and hotplug drm/hisilicon: Add dsi encoder driver drm/hisilicon: Add dsi host driver drm/hisilicon: Add support for external bridge .../bindings/display/hisilicon/hisi-ade.txt| 42 + .../bindings/display/hisilicon/hisi-drm.txt| 66 ++ .../bindings/display/hisilicon/hisi-dsi.txt| 53 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 21 + arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 44 + drivers/gpu/drm/Kconfig|2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/hisilicon/Kconfig | 10 + drivers/gpu/drm/hisilicon/Makefile |5 + drivers/gpu/drm/hisilicon/hisi_ade_reg.h | 490 + drivers/gpu/drm/hisilicon/hisi_drm_ade.c | 1068 drivers/gpu/drm/hisilicon/hisi_drm_ade.h | 16 + drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 280 + drivers/gpu/drm/hisilicon/hisi_drm_drv.h | 19 + drivers/gpu/drm/hisilicon/hisi_drm_dsi.c | 829 +++ drivers/gpu/drm/hisilicon/hisi_dsi_reg.h | 89 ++ 16 files changed, 3035 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt create mode 100644 drivers/gpu/drm/hisilicon/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/Makefile create mode 100644 drivers/gpu/drm/hisilicon/hisi_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_ade.c create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_ade.h create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.c create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.h create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_dsi.c create mode 100644 drivers/gpu/drm/hisilicon/hisi_dsi_reg.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 01/10] arm64: dts: hisilicon: Add display subsystem DT nodes for hi6220
Add ade, dsi and adv7533 DT nodes for hikey board.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 21
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 44 ++
2 files changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 8d43a0f..81236b3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -31,4 +31,25 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x4000>;
};
+
+ soc {
+ i2c2: i2c@f7102000 {
+ status = "ok";
+
+ adv7533: adv7533@39 {
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 2>;
+ pd-gpio = <&gpio0 4 0>;
+ adi,dsi-lanes = <4>;
+
+ port {
+ adv_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..2d6cf03 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,49 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ display-subsystem {
+ compatible = "hisilicon,hi6220-dss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ade: ade@f410 {
+ compatible = "hisilicon,hi6220-ade";
+ reg = <0x0 0xf410 0x0 0x7800>,
+ <0x0 0xf441 0x0 0x1000>;
+ reg-names = "ade_base",
+ "media_base";
+ interrupts = <0 115 4>; /* ldi interrupt */
+
+ clocks = <&media_ctrl HI6220_ADE_CORE>,
+<&media_ctrl HI6220_CODEC_JPEG>,
+<&media_ctrl HI6220_ADE_PIX_SRC>,
+<&media_ctrl HI6220_PLL_SYS>,
+<&media_ctrl HI6220_PLL_SYS_MEDIA>;
+ /*clock name*/
+ clock-names = "clk_ade_core",
+ "aclk_codec_jpeg_src",
+ "clk_ade_pix",
+ "clk_syspll_src",
+ "clk_medpll_src";
+ ade_core_clk_rate = <36000>;
+ media_noc_clk_rate = <28800>;
+ };
+
+ dsi: dsi@0xf4107800 {
+ compatible = "hisilicon,hi6220-dsi";
+ reg = <0x0 0xf4107800 0x0 0x100>;
+ clocks = <&media_ctrl HI6220_DSI_PCLK>;
+ clock-names = "pclk_dsi";
+
+ port {
+ dsi_out: endpoint {
+ remote-endpoint = <&adv_in>;
+ };
+ };
+
+ };
+ };
};
};
--
1.9.1
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[PATCH v2 04/10] drm/hisilicon: Add crtc funcs for ADE
Add crtc funcs and helper funcs for ADE. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong Signed-off-by: Andy Green --- drivers/gpu/drm/hisilicon/Makefile | 3 +- drivers/gpu/drm/hisilicon/hisi_ade_reg.h | 490 + drivers/gpu/drm/hisilicon/hisi_drm_ade.c | 511 +++ drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 15 + drivers/gpu/drm/hisilicon/hisi_drm_drv.h | 16 + 5 files changed, 1034 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/hisi_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_ade.c create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.h diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile index 7375456..3433c8b 100644 --- a/drivers/gpu/drm/hisilicon/Makefile +++ b/drivers/gpu/drm/hisilicon/Makefile @@ -1,3 +1,4 @@ -hisi-drm-y := hisi_drm_drv.o +hisi-drm-y := hisi_drm_drv.o \ + hisi_drm_ade.o obj-$(CONFIG_DRM_HISI) += hisi-drm.o diff --git a/drivers/gpu/drm/hisilicon/hisi_ade_reg.h b/drivers/gpu/drm/hisilicon/hisi_ade_reg.h new file mode 100644 index 000..6a7bc46 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hisi_ade_reg.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2014-2015 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __HISI_ADE_REG_H__ +#define __HISI_ADE_REG_H__ + +/* + * ADE Registers Offset + */ +#define ADE_CTRL (0x4) +#define ADE_CTRL1 (0x8C) +#define ADE_ROT_SRC_CFG(0x10) +#define ADE_DISP_SRC_CFG (0x18) +#define ADE_WDMA2_SRC_CFG (0x1C) +#define ADE_SEC_OVLY_SRC_CFG (0x20) +#define ADE_WDMA3_SRC_CFG (0x24) +#define ADE_OVLY1_TRANS_CFG(0x2C) +#define ADE_EN (0x100) +#define INTR_MASK_CPU_0(0xC10) +#define INTR_MASK_CPU_1(0xC14) +#define ADE_FRM_DISGARD_CTRL (0xA4) +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL0 (0x78) +#define ADE_SOFT_RST_SEL1 (0x7C) +#define ADE_RELOAD_DIS0(0xAC) +#define ADE_RELOAD_DIS1(0xB0) +#define ADE_CH_RDMA_BIT_OFST (0) +#define ADE_CLIP_BIT_OFST (15) +#define ADE_SCL_BIT_OFST (21) +#define ADE_CTRAN_BIT_OFST (24) +#define ADE_OVLY_BIT_OFST (37) /* 32+5 */ +/* channel regs */ +#define RD_CH_PE(x)(0x1000 + (x) * 0x80) +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x)(0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) +#define RD_CH_EN(x)(0x1020 + (x) * 0x80) +#define RD_CH_STATUS(x)(0x1024 + (x) * 0x80) +#define RD_CH_DISP_CTRL(0x1404) +#define RD_CH_DISP_ADDR(0x1408) +#define RD_CH_DISP_SIZE(0x140C) +#define RD_CH_DISP_STRIDE (0x1410) +#define RD_CH_DISP_SPACE (0x1414) +#define RD_CH_DISP_EN (0x142C) +/* clip regs */ +#define ADE_CLIP_DISABLE(x)(0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) +/* scale regs */ +#define ADE_SCL1_MUX_CFG (0xC) +#define ADE_SCL2_SRC_CFG (0x14) +#define ADE_SCL3_MUX_CFG (0x8) +#define ADE_SCL_CTRL(x)(0x3000 + (x) * 0x800) +#define ADE_SCL_HSP(x) (0x3004 + (x) * 0x800) +#define ADE_SCL_UV_HSP(x) (0x3008 + (x) * 0x800) +#define ADE_SCL_VSP(x) (0x300C + (x) * 0x800) +#define ADE_SCL_UV_VSP(x) (0x3010 + (x) * 0x800) +#define ADE_SCL_ORES(x)(0x3014 + (x) * 0x800) +#define ADE_SCL_IRES(x)(0x3018 + (x) * 0x800) +#define ADE_SCL_START(x) (0x301C + (x) * 0x800) +#define ADE_SCL_ERR(x) (0x3020 + (x) * 0x800) +#define ADE_SCL_PIX_OFST(x)(0x3024 + (x) * 0x800) +#define ADE_SCL_UV_PIX_OFST(x) (0x3028 + (x) * 0x800) +#define ADE_SCL_COEF_CLR(x)(0x3030 + (x) * 0x800) +#define ADE_SCL_HCOEF(x, m, n) (0x3100 + (x) * 0x800 + \ + 12
[PATCH v2 02/10] drm/hisilicon: Add DT binding docs for hi6220 display subsystem
Add the device tree binding documentation for hi6220 SoC display subsystem.
drm master device binding doc.
ADE display controller binding doc.
DSI controller binding doc.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
.../bindings/display/hisilicon/hisi-ade.txt| 42 ++
.../bindings/display/hisilicon/hisi-drm.txt| 66 ++
.../bindings/display/hisilicon/hisi-dsi.txt| 53 +
3 files changed, 161 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
create mode 100644
Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt
create mode 100644
Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt
diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
new file mode 100644
index 000..2777a2c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
@@ -0,0 +1,42 @@
+Device-Tree bindings for hisilicon ADE display controller driver
+
+ADE (Advanced Display Engine) is the display controller which grab image
+data from memory, do composition, do post image processing, generate RGB
+timing stream and transfer to DSI.
+
+Required properties:
+- compatible: value should be one of the following
+ "hisilicon,hi6220-ade".
+- reg: physical base address and length of the controller's registers.
+- reg-names: name of physical base.
+- interrupt: the interrupt number.
+- clocks: the clocks needed.
+- clock-names: the name of the clocks.
+- ade_core_clk_rate: ADE core clock rate.
+- media_noc_clk_rate: media noc module clock rate.
+
+
+A example of HiKey board hi6220 SoC specific DT entry:
+Example:
+
+ ade: ade@f410 {
+ compatible = "hisilicon,hi6220-ade";
+ reg = <0x0 0xf410 0x0 0x7800>,
+ <0x0 0xf441 0x0 0x1000>;
+ reg-names = "ade_base",
+ "media_base";
+ interrupts = <0 115 4>;
+
+ clocks = <&media_ctrl HI6220_ADE_CORE>,
+<&media_ctrl HI6220_CODEC_JPEG>,
+<&media_ctrl HI6220_ADE_PIX_SRC>,
+<&media_ctrl HI6220_PLL_SYS>,
+<&media_ctrl HI6220_PLL_SYS_MEDIA>;
+ clock-names = "clk_ade_core",
+ "aclk_codec_jpeg_src",
+ "clk_ade_pix",
+ "clk_syspll_src",
+ "clk_medpll_src";
+ ade_core_clk_rate = <36000>;
+ media_noc_clk_rate = <28800>;
+ };
diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt
b/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt
new file mode 100644
index 000..fd93026
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt
@@ -0,0 +1,66 @@
+Hisilicon DRM master device
+
+The Hisilicon DRM master device is a virtual device needed to list all
+the other display relevant nodes that comprise the display subsystem.
+
+
+Required properties:
+- compatible: Should be "hisilicon,-dss"
+- #address-cells: should be set to 2.
+- #size-cells: should be set to 2.
+- range: to allow probing of subdevices.
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent.
+
+Required sub nodes:
+All the device nodes of display subsystem of SoC should be the sub nodes.
+Such as display controller node, DSI node and so on.
+
+A example of HiKey board hi6220 SoC specific DT entry:
+Example:
+
+ display-subsystem {
+ compatible = "hisilicon,hi6220-dss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ ade: ade@f410 {
+ compatible = "hisilicon,hi6220-ade";
+ reg = <0x0 0xf410 0x0 0x7800>,
+ <0x0 0xf441 0x0 0x1000>;
+ reg-names = "ade_base",
+ "media_base";
+ interrupts = <0 115 4>; /* ldi interrupt */
+
+ clocks = <&media_ctrl HI6220_ADE_CORE>,
+<&media_ctrl HI6220_CODEC_JPEG>,
+<&media_ctrl HI6220_ADE_PIX_SRC>,
+<&media_ctrl HI6220_PLL_SYS>,
+<&media_ctrl HI6220_PLL_SYS_MEDIA>;
+ /*clock name*/
+ clock-names = "clk_ade_core",
+ "aclk_codec_jpeg_src",
+ "clk_ade_pix",
+ "clk_syspll_src",
+ "clk_medpll_src";
+ ade_core
RE: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
> Subject: Re: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On Friday 27 November 2015 20:32:03 Bharat Kumar Gogada wrote:
> > + do {
> > + err = nwl_pcie_link_up(pcie, PHY_RDY_LINKUP);
> > + if (err != 1) {
> > + check_link_up++;
> > + if (check_link_up > LINKUP_ITER_CHECK)
> > + return -ENODEV;
> > + mdelay(1000);
> > + }
> > + } while (!err);
>
> mdelay(1000) is not something anyone should do. Why can't you call a
> sleeping function here?
>
Agreed will use sleep function, will address it in next patch.
Regards,
Bharat
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RE: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
> Subject: Re: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On 27/11/15 15:02, Bharat Kumar Gogada wrote:
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada
> > Signed-off-by: Ravi Kiran Gummaluri
> > Acked-by: Rob Herring
> > ---
> > Changes for v10:
> > -> Changed MSI address to PCIe controller base.
> > -> Removed nwl_check_hwirq function, instead using
> > -> bitmap_find_next_zero_area
> >API to do the same.
> > ---
> > .../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 68 ++
> > drivers/pci/host/Kconfig | 10 +
> > drivers/pci/host/Makefile |1 +
> > drivers/pci/host/pcie-xilinx-nwl.c | 1068
> >
> > 4 files changed, 1147 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> > create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
> >
> > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
> > b/drivers/pci/host/pcie-xilinx-nwl.c
> > new file mode 100644
> > index 000..d070344
> > --- /dev/null
> > +++ b/drivers/pci/host/pcie-xilinx-nwl.c
>
> [...]
>
> > +#define MSI_ADDRESS0xFD48
> > +
>
> Really? Why do you bother having DT support then? You might as well
> hardcode everything, while you're at it.
>
> /me felling depressed now.
Agreed, I'm already having this parameter in nwl_pcie structure, will use it.
>
> > +struct nwl_msi { /* MSI information */
> > + struct irq_domain *msi_domain;
> > + unsigned long *bitmap;
> > + struct irq_domain *dev_domain;
> > + struct mutex lock; /* protect bitmap variable */
> > + int irq_msi0;
> > + int irq_msi1;
> > +};
> > +
> > +struct nwl_pcie {
> > + struct device *dev;
> > + void __iomem *breg_base;
> > + void __iomem *pcireg_base;
> > + void __iomem *ecam_base;
> > + u32 phys_breg_base; /* Physical Bridge Register Base */
> > + u32 phys_pcie_reg_base; /* Physical PCIe Controller
> Base */
> > + u32 phys_ecam_base; /* Physical Configuration Base */
>
> All these u32 should be phys_addr_t. Not all the world is 32bit, fortunately.
Agreed will address it next patch.
>
> > + u32 breg_size;
> [...]
>
>
> > +static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) {
> > + struct platform_device *pdev = to_platform_device(pcie->dev);
> > + u32 breg_val, ecam_val, first_busno = 0;
> > + int err;
> > + int check_link_up = 0;
> > +
> > + /* Check for BREG present bit */
> > + breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) &
> BREG_PRESENT;
> > + if (!breg_val) {
> > + dev_err(pcie->dev, "BREG is not present\n");
> > + return breg_val;
> > + }
> > + /* Write bridge_off to breg base */
> > + nwl_bridge_writel(pcie, (u32)(pcie->phys_breg_base),
> > + E_BREG_BASE_LO);
> > +
>
> I love the casting of a u32 to a u32. You have to program E_BREG_BASE_HI as
> well, once you've fixed the data type.
> Agreed, will address this in next patch.
> > + /* Enable BREG */
> > + nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
> > + E_BREG_CONTROL);
> > + /* Check for ECAM present bit */
> > + ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) &
> E_ECAM_PRESENT;
> > + if (!ecam_val) {
> > + dev_err(pcie->dev, "ECAM is not present\n");
> > + return ecam_val;
> > + }
> |
> > + /* Write phy_reg_base to ecam base */
> > + nwl_bridge_writel(pcie, (u32)pcie->phys_ecam_base,
> E_ECAM_BASE_LO);
>
> Same here.
> Agreed, will address this in next patch.
Regards,
Bharat
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Re: [PATCH 1/3] dt-bindings: add Marvell core PLL and clock divider PMU documentation
On 27.11.2015 21:39, Russell King - ARM Linux wrote:
> On Fri, Nov 27, 2015 at 02:21:14PM -0600, Rob Herring wrote:
>> On Thu, Nov 26, 2015 at 10:23:21PM +, Russell King wrote:
>>> Add documentation for the Marvell clock divider driver, which is used
>>> to source clocks for the AXI bus, video decoder, GPU and LCD blocks.
>>>
>>> Signed-off-by: Russell King
>>> ---
>>> .../bindings/clock/dove-divider-clock.txt | 28
>>> ++
>>> 1 file changed, 28 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/clock/dove-divider-clock.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
>>> b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
>>> new file mode 100644
>>> index ..0c602de279e5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
>>> @@ -0,0 +1,28 @@
>>> +PLl divider based Dove clocks
>>> +
>>> +Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
>>> +high speed clocks for a number of peripherals. These dividers are part of
>>> +the PMU, and thus this node should be a child of the PMU node.
>>
>> It seems a bit strange to just be documenting these clocks. What about
>> the rest of the SOC clocks?
>
> This is all that this pair of registers provide.
>
> The SoC has other clocks handled by other DT nodes - for Dove, we now
> have:
>
> gate_clk: clock-gating-ctrl@0038 {
> compatible = "marvell,dove-gating-clock";
> reg = <0x0038 0x4>;
> clocks = <&core_clk 0>;
> #clock-cells = <1>;
> };
> divider_clk: core-clock@0064 {
> compatible = "marvell,dove-divider-clock";
> reg = <0x0064 0x8>;
> #clock-cells = <1>;
> };
> core_clk: core-clocks@0214 {
> compatible = "marvell,dove-core-clock";
> reg = <0x0214 0x4>;
> #clock-cells = <1>;
> };
>
> and all three of these are part of the PMU register block. I'm not sure
> why the mvebu maintainers decided to minutely describe the PMU like this,
> but unfortunately that's the structure we have.
>
> What's more silly is that the "dove-core-clock" appears to disagree in
> terminology with the manual - there's a "Core PLL" which supplies the
> dividers in the "divider_clk" block, and is entirely separate from the
> CPU PLL which "core_clk" is describing.
>
> IMHO, it would've been cleaner to have these components registered
> separately from a central PMU driver (as I'm doing with the power
> domains, resets and IRQs that are part of the PMU), but my view is
> limited to Dove and not the other mvebu clocks, so there may be a good
> reason for it.
>
Rob, Russell,
the main reason why dove clocks are the way they are is that back
when we thought of the bindings for mvebu SoC clocks, CCF and DT was
in its very beginning. Looking back, some decisions shouldn't have
been made that way. Also, we tried to describe Dove and the other SoCs
similarily, but Dove is always a little odd.
>From todays point of view, I certainly agree with Russell that all
PMU related stuff is best kept in a single PMU node.
Thanks for providing the patches, I appreciate the extra work of
separating those from your working trees.
Acked-by: Sebastian Hesselbarth
Sebastian
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Re: [PATCH v7 3/4] arm64/arm, numa, dt: adding numa dt binding implementation for arm64 platforms.
On 2015/11/18 1:20, Ganapatrao Kulkarni wrote:
> +static int __init early_init_parse_memory_node(unsigned long node)
> +{
> + const __be32 *reg, *endp;
> + int length;
> + int nid;
> +
> + const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
> +
> + /* We are scanning "memory" nodes only */
> + if (type == NULL)
> + return 0;
> + else if (strcmp(type, "memory") != 0)
> + return 0;
> +
> + nid = early_init_of_get_numa_nid(node);
> +
> + if (nid == NUMA_NO_NODE)
> + return -EINVAL;
> +
> + reg = of_get_flat_dt_prop(node, "reg", &length);
> + endp = reg + (length / sizeof(__be32));
> +
> + while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
> + u64 base, size;
> + struct memblock_region *mblk;
> +
> + base = dt_mem_next_cell(dt_root_addr_cells, ®);
> + size = dt_mem_next_cell(dt_root_size_cells, ®);
> + pr_debug("NUMA-DT: base = %llx , node = %u\n",
> + base, nid);
> +
> + for_each_memblock(memory, mblk) {
> + if (mblk->base == base) {
> + if (numa_add_memblk(nid,
> + mblk->base,
> + mblk->size) < 0)
> + return -EINVAL;
> + break;
> + }
> + }
Maybe this is not right. If the memory spaces of NUMA nodes are
continuous like below:
memory@6000 {
numa-node-id = <0x1>;
reg = <0x0 0x6000 0x0 0x2000>;
device_type = "memory";
};
memory@4000 {
numa-node-id = <0x0>;
reg = <0x0 0x4000 0x0 0x2000>;
device_type = "memory";
};
There is only one memory region [0x004000-0x007fff] and
the mblk->base is 4000, so it will not add the memory node 1.
I think this should do the same thing like ACPI_NUMA but add some codes
to check if the [base, base + size] is located in some memory region.
Or don't check because numa_add_memblk will fail if the [base, base +
size] is not located in some memory region.
Thanks,
--
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Re: [PATCH v2 8/9] leds: add LM3633 driver
On 11/27/2015 12:19 PM, Jacek Anaszewski wrote:
Hi Milo,
Thanks for the update. I have few comments below.
[...]
+static u8 lm3633_led_scale_max_brightness(struct ti_lmu_led *lmu_led,
u32 imax)
+{
+u8 max_current = lm3633_led_convert_current_to_index(imax);
+const u8 max_brightness_table[] = {
+[LMU_IMAX_5mA] = 191,
+[LMU_IMAX_6mA] = 197,
+[LMU_IMAX_7mA] = 203,
+[LMU_IMAX_8mA] = 208,
+[LMU_IMAX_9mA] = 212,
+[LMU_IMAX_10mA] = 216,
+[LMU_IMAX_11mA] = 219,
+[LMU_IMAX_12mA] = 222,
+[LMU_IMAX_13mA] = 225,
+[LMU_IMAX_14mA] = 228,
+[LMU_IMAX_15mA] = 230,
+[LMU_IMAX_16mA] = 233,
+[LMU_IMAX_17mA] = 235,
+[LMU_IMAX_18mA] = 237,
+[LMU_IMAX_19mA] = 239,
+[LMU_IMAX_20mA] = 241,
+[LMU_IMAX_21mA] = 242,
+[LMU_IMAX_22mA] = 244,
+[LMU_IMAX_23mA] = 246,
+[LMU_IMAX_24mA] = 247,
+[LMU_IMAX_25mA] = 249,
+[LMU_IMAX_26mA] = 250,
+[LMU_IMAX_27mA] = 251,
+[LMU_IMAX_28mA] = 253,
+[LMU_IMAX_29mA] = 254,
+[LMU_IMAX_30mA] = 255,
+};
After analyzing the subject one more time I think that we need to
change the approach regarding max brightness issue.
At first - we shouldn't fix max current to max possible register value.
Instead we should take led-max-microamp property and write its value
to the [0x22 + bank offset] registers.
It was of course a mental shortcut. The value to write should be
calculated by transforming the formula given next to the register
documentation:
1 = 29.8 mA
0.8mA steps, FS = 5mA + code * 0.8 mA
code is here the [0x22 + bank_offset] register value.
Effectively, the formula to calculate the register value basing
on led-max-microamp value should be:
FS = led-max-microamp - 5000 / 800
E.g. for 20.2 mA:
FS = (20200 - 5000) / 800 = 19
for 29.8 mA:
FS = (29800 - 5000) / 800 = 31
for 5 mA:
FS = (5000 - 5000) / 800 = 0
From the above min, max and step values for led-max-microamp
are 5000, 29800 and 800 respectively. Please correct DT documentation
accordingly.
With this approach whole 0-255 range of brightness levels will be
valid for the driver.
In effect all LMU_IMAX* enums seem to be not needed.
--
Best Regards,
Jacek Anaszewski
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