[PATCH 4/8 v3] thermal: rcar: retern error rcar_thermal_get_temp() if no ctemp update
From: Kuninori Morimoto
Current rcar_thermal_get_temp() returns latest temperature, but it might
not be updated if some HW issue happend. This means user might get
wrong temperature. This patch solved this issue.
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- no change
drivers/thermal/rcar_thermal.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index aaedf37..52493b4 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -199,9 +199,9 @@ static int rcar_thermal_update_temp(struct
rcar_thermal_priv *priv)
dev_dbg(dev, "thermal%d %d -> %d\n", priv->id, priv->ctemp, ctemp);
- priv->ctemp = ctemp;
ret = 0;
err_out_unlock:
+ priv->ctemp = ctemp;
mutex_unlock(&priv->lock);
return ret;
}
@@ -209,6 +209,7 @@ err_out_unlock:
static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
{
struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone);
+ int tmp;
if (!rcar_has_irq_support(priv) || rcar_force_update_temp(priv)) {
int ret = rcar_thermal_update_temp(priv);
@@ -217,9 +218,18 @@ static int rcar_thermal_get_temp(struct
thermal_zone_device *zone, int *temp)
}
mutex_lock(&priv->lock);
- *temp = MCELSIUS((priv->ctemp * 5) - 65);
+ tmp = MCELSIUS((priv->ctemp * 5) - 65);
mutex_unlock(&priv->lock);
+ if ((tmp < MCELSIUS(-45)) || (tmp > MCELSIUS(125))) {
+ struct device *dev = rcar_priv_to_dev(priv);
+
+ dev_err(dev, "it couldn't measure temperature correctly\n");
+ return -EIO;
+ }
+
+ *temp = tmp;
+
return 0;
}
--
1.9.1
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[PATCH 5/8 v3] thermal: rcar: enable to use thermal-zone on DT
From: Kuninori Morimoto
This patch enables to use thermal-zone on DT if it was call as
"renesas,rcar-thermal-gen2".
Previous style is still supported by "renesas,rcar-thermal".
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- compatible "renesas,rcar-thermal-gen2" -> "renesas,rcar-gen2-thermal"
.../devicetree/bindings/thermal/rcar-thermal.txt | 37 +-
drivers/thermal/rcar_thermal.c | 44 +++---
2 files changed, 74 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 332e625..601a54d 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -1,8 +1,9 @@
* Renesas R-Car Thermal
Required properties:
-- compatible : "renesas,thermal-", "renesas,rcar-thermal"
- as fallback.
+- compatible : "renesas,thermal-",
+ "renesas,rcar-gen2-thermal" (with thermal-zone) or
+ "renesas,rcar-thermal" (without thermal-zone) as
fallback.
Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7779" (R-Car H1)
@@ -36,3 +37,35 @@ thermal@e61f {
0xe61f0300 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
};
+
+Example (with thermal-zone):
+
+thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115>;
+ hysteresis = <0>;
+ type= "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+};
+
+thermal: thermal@e61f {
+ compatible ="renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
+};
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 52493b4..a8c88f4 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -81,8 +82,10 @@ struct rcar_thermal_priv {
# define rcar_force_update_temp(priv) 0
#endif
+#define USE_OF_THERMAL 1
static const struct of_device_id rcar_thermal_dt_ids[] = {
{ .compatible = "renesas,rcar-thermal", },
+ { .compatible = "renesas,rcar-gen2-thermal", .data = (void
*)USE_OF_THERMAL },
{},
};
MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -206,9 +209,8 @@ err_out_unlock:
return ret;
}
-static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
+static int rcar_thermal_get_current_temp(struct rcar_thermal_priv *priv, int
*temp)
{
- struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone);
int tmp;
if (!rcar_has_irq_support(priv) || rcar_force_update_temp(priv)) {
@@ -233,6 +235,20 @@ static int rcar_thermal_get_temp(struct
thermal_zone_device *zone, int *temp)
return 0;
}
+static int rcar_thermal_of_get_temp(void *data, int *temp)
+{
+ struct rcar_thermal_priv *priv = data;
+
+ return rcar_thermal_get_current_temp(priv, temp);
+}
+
+static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp)
+{
+ struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone);
+
+ return rcar_thermal_get_current_temp(priv, temp);
+}
+
static int rcar_thermal_get_trip_type(struct thermal_zone_device *zone,
int trip, enum thermal_trip_type *type)
{
@@ -289,6 +305,10 @@ static int rcar_thermal_notify(struct thermal_zone_device
*zone,
return 0;
}
+static const struct thermal_zone_of_device_ops rcar_thermal_zone_of_ops = {
+ .get_temp = rcar_thermal_of_get_temp,
+};
+
static struct thermal_zone_device_ops rcar_thermal_zone_ops = {
.get_temp = rcar_thermal_get_temp,
.get_trip_type = rcar_thermal_get_trip_type,
@@ -325,14 +345,20 @@ static void rcar_thermal_work(struct work_struct *work)
priv = container_of(work, struct rcar_thermal_priv, work.work);
- rcar_thermal_get_temp(priv->zone, &cctemp);
+ ret = rcar_thermal_get_current_temp(priv, &cctemp);
+ if (ret < 0)
+ return;
+
ret = rcar_thermal_update_temp(pri
[PATCH 8/8 v3] thermal: of-thermal: of_thermal_set_trip_temp() call thermal_zone_device_update()
From: Kuninori Morimoto of_thermal_set_trip_temp() updates trip temperature. It should call thermal_zone_device_update() immediately. Signed-off-by: Kuninori Morimoto --- v2 -> v3 - no change drivers/thermal/of-thermal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index be4eedc..d59595b 100644 --- a/drivers/thermal/of-thermal.c +++ b/drivers/thermal/of-thermal.c @@ -334,6 +334,8 @@ static int of_thermal_set_trip_temp(struct thermal_zone_device *tz, int trip, /* thermal framework should take care of data->mask & (1 << trip) */ data->trips[trip].temperature = temp; + thermal_zone_device_update(tz); + return 0; } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/8 v3] thermal: rcar: move rcar_thermal_dt_ids to upside
From: Kuninori Morimoto
This patch is prepare for of-thermal support.
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- no change
drivers/thermal/rcar_thermal.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 13d01ed..96707a6 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -81,6 +81,12 @@ struct rcar_thermal_priv {
# define rcar_force_update_temp(priv) 0
#endif
+static const struct of_device_id rcar_thermal_dt_ids[] = {
+ { .compatible = "renesas,rcar-thermal", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
+
/*
* basic functions
*/
@@ -484,12 +490,6 @@ error_unregister:
return ret;
}
-static const struct of_device_id rcar_thermal_dt_ids[] = {
- { .compatible = "renesas,rcar-thermal", },
- {},
-};
-MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
-
static struct platform_driver rcar_thermal_driver = {
.driver = {
.name = "rcar_thermal",
--
1.9.1
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[PATCH 2/8 v3] thermal: rcar: check every rcar_thermal_update_temp() return value
From: Kuninori Morimoto
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- no change
drivers/thermal/rcar_thermal.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 96707a6..4d1bc2b 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -210,8 +210,11 @@ static int rcar_thermal_get_temp(struct
thermal_zone_device *zone, int *temp)
{
struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone);
- if (!rcar_has_irq_support(priv) || rcar_force_update_temp(priv))
- rcar_thermal_update_temp(priv);
+ if (!rcar_has_irq_support(priv) || rcar_force_update_temp(priv)) {
+ int ret = rcar_thermal_update_temp(priv);
+ if (ret < 0)
+ return ret;
+ }
mutex_lock(&priv->lock);
*temp = MCELSIUS((priv->ctemp * 5) - 65);
@@ -305,11 +308,15 @@ static void rcar_thermal_work(struct work_struct *work)
{
struct rcar_thermal_priv *priv;
int cctemp, nctemp;
+ int ret;
priv = container_of(work, struct rcar_thermal_priv, work.work);
rcar_thermal_get_temp(priv->zone, &cctemp);
- rcar_thermal_update_temp(priv);
+ ret = rcar_thermal_update_temp(priv);
+ if (ret < 0)
+ return;
+
rcar_thermal_irq_enable(priv);
rcar_thermal_get_temp(priv->zone, &nctemp);
@@ -447,7 +454,9 @@ static int rcar_thermal_probe(struct platform_device *pdev)
mutex_init(&priv->lock);
INIT_LIST_HEAD(&priv->list);
INIT_DELAYED_WORK(&priv->work, rcar_thermal_work);
- rcar_thermal_update_temp(priv);
+ ret = rcar_thermal_update_temp(priv);
+ if (ret < 0)
+ goto error_unregister;
priv->zone = thermal_zone_device_register("rcar_thermal",
1, 0, priv,
--
1.9.1
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[PATCH 7/8 v3] ARM: shmobile: r8a7791: enable to use thermal-zone
From: Kuninori Morimoto
This patch enables to use thermal-zone on r8a7791.
This thermal sensor can measure temperature from -4 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
9, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifing polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reached to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- compatible "renesas,rcar-thermal-gen2" -> "renesas,rcar-gen2-thermal"
arch/arm/boot/dts/r8a7791.dtsi | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1487d92..d885e5f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -69,6 +69,25 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115>;
+ hysteresis = <0>;
+ type= "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -185,12 +204,15 @@
power-domains = <&cpg_clocks>;
};
- thermal@e61f {
- compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
+ thermal: thermal@e61f {
+ compatible ="renesas,thermal-r8a7791",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
};
timer {
--
1.9.1
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[PATCH 6/8 v3] ARM: shmobile: r8a7790: enable to use thermal-zone
From: Kuninori Morimoto
This patch enables to use thermal-zone on r8a7790.
This thermal sensor can measure temperature from -4 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
9, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifing polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reached to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- compatible "renesas,rcar-thermal-gen2" -> "renesas,rcar-gen2-thermal"
arch/arm/boot/dts/r8a7790.dtsi | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 6cfd0dc..49aaa67 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -112,6 +112,25 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115>;
+ hysteresis = <0>;
+ type= "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -202,12 +221,15 @@
power-domains = <&cpg_clocks>;
};
- thermal@e61f {
- compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ thermal: thermal@e61f {
+ compatible ="renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
};
timer {
--
1.9.1
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[PATCH 3/8 v3] thermal: rcar: check irq possibility in rcar_thermal_irq_xxx()
From: Kuninori Morimoto
Current rcar thermal driver sometimes checks irq possibility when it
calls rcar_thermal_irq_enable/disable(), but sometimes not.
This patch checks it inside rcar_thermal_irq_enable/disable().
Signed-off-by: Kuninori Morimoto
---
v2 -> v3
- no change
drivers/thermal/rcar_thermal.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 4d1bc2b..aaedf37 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -297,6 +297,9 @@ static void _rcar_thermal_irq_ctrl(struct rcar_thermal_priv
*priv, int enable)
unsigned long flags;
u32 mask = 0x3 << rcar_id_to_shift(priv); /* enable Rising/Falling */
+ if (!rcar_has_irq_support(priv))
+ return;
+
spin_lock_irqsave(&common->lock, flags);
rcar_thermal_common_bset(common, INTMSK, mask, enable ? 0 : mask);
@@ -381,8 +384,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
rcar_thermal_for_each_priv(priv, common) {
- if (rcar_has_irq_support(priv))
- rcar_thermal_irq_disable(priv);
+ rcar_thermal_irq_disable(priv);
thermal_zone_device_unregister(priv->zone);
}
@@ -468,8 +470,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
goto error_unregister;
}
- if (rcar_has_irq_support(priv))
- rcar_thermal_irq_enable(priv);
+ rcar_thermal_irq_enable(priv);
list_move_tail(&priv->list, &common->head);
--
1.9.1
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[PATCH 0/8 v3] enable to use thermal-zone on r8a7790/1
Hi These are v3 of thermal-zone support for r8a7790/r8a7791. Mainly, it cares return value of get_temp() I think 8) is needed on of-thermal (?) Kuninori Morimoto (8): 1) thermal: rcar: move rcar_thermal_dt_ids to upside 2) thermal: rcar: check every rcar_thermal_update_temp() return value 3) thermal: rcar: check irq possibility in rcar_thermal_irq_xxx() 4) thermal: rcar: retern error rcar_thermal_get_temp() if no ctemp update 5) thermal: rcar: enable to use thermal-zone on DT 6) ARM: shmobile: r8a7790: enable to use thermal-zone 7) ARM: shmobile: r8a7791: enable to use thermal-zone 8) thermal: of-thermal: of_thermal_set_trip_temp() call thermal_zone_device_update() Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 37 +++-- arch/arm/boot/dts/r8a7790.dtsi | 26 -- arch/arm/boot/dts/r8a7791.dtsi | 26 -- drivers/thermal/of-thermal.c | 2 ++ drivers/thermal/rcar_thermal.c | 96 +++- 5 files changed, 160 insertions(+), 27 deletions(-) Best regards --- Kuninori Morimoto -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
On 12/07/2015 02:38 PM, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"
The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.
They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 50%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index aee3262..cd86413 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-static int exynos_dp_remove(struct platform_device *pdev)
+void analogix_dp_unbind(struct device *dev, struct device *master,
+ void *data)
{
- pm_runtime_disable(&pdev->dev);
- component_del(&pdev->dev, &exynos_dp_ops);
+ struct analogix_dp_device *dp = dev_get_drvdata(dev);
- return 0;
+ analogix_dp_bridge_disable(dp->bridge);
+ pm_runtime_disable(&pdev->dev);
}
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
Sorry to introduce an compiled error, my test 4.4-rc3 kernel have some
different with linux-next kernel, so i used to write the patches on next
kernel,
and back the changes to my 4.4 kernel to test.
I already found this error when I'm testing, but forget to reserver this
changes
to linux-next kernel, I would send a new version to fix this.
- Yakir
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[PATCH 1/2] ARM: dts: sun4i: gemei-g9: Add touchscreen (Goodix gt801x2) support
Goodix GT801 2+1 is a touchscreen controller supporting up to
10 touches.
Enable pin and wakeup pin support is currently not implemented:
- enable pin (PI16, specified in FEX) seems to be wrong
- wakeup pin needs some additional reverse engineering work
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
index 1d73a98..52e6275 100644
--- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
@@ -48,6 +48,7 @@
#include
#include
#include
+#include
/ {
model = "Gemei G9 Tablet";
@@ -65,11 +66,11 @@
/*
* TODO:
* 2x cameras via CSI
- * audio input
+ * audio input (+ ext. amplifier enable GPIO)
* AXP battery management
* NAND
* OTG
- * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48
+ * Touchscreen enable and wakeup pins
*/
&codec {
status = "okay";
@@ -114,6 +115,27 @@
};
};
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ touchscreen@55 {
+ compatible = "goodix,gt801_2plus1";
+ reg = <0x55>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */
+
+ /*
+* TODO - figure out the wakeup pin:
+* ctp_wakeup = port:PB13<1><1>
+* TODO - find correct GPIO pin, PI16 seems to be incorrect:
+* ctp_en = port:PI16<1><0>
+*/
+ };
+};
+
&lradc {
vref-supply = <®_ldo2>;
--
2.6.3
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[PATCH 2/2] input: gt801_2plus1 - Add initial support for Goodix GT801 2+1
This patch adds Goodix GT801 2+1 touchscreen controller support.
GT801 2+1 is a 10-finger touch controller consisting of
ARM controller interfacing two GT801 5-finger controllers.
Signed-off-by: Priit Laes
---
.../bindings/input/touchscreen/gt801_2plus1.txt| 23 ++
MAINTAINERS| 6 +
drivers/input/touchscreen/Kconfig | 19 +-
drivers/input/touchscreen/Makefile | 1 +
drivers/input/touchscreen/gt801_2plus1.c | 375 +
5 files changed, 421 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/input/touchscreen/gt801_2plus1.txt
create mode 100644 drivers/input/touchscreen/gt801_2plus1.c
diff --git
a/Documentation/devicetree/bindings/input/touchscreen/gt801_2plus1.txt
b/Documentation/devicetree/bindings/input/touchscreen/gt801_2plus1.txt
new file mode 100644
index 000..070ff5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/gt801_2plus1.txt
@@ -0,0 +1,23 @@
+Device tree bindings for Goodix GT801 2+1 series touchscreen controller
+
+Required properties:
+
+ - compatible : Should be "goodix,gt801_2plus1"
+ - reg : I2C address of the chip. Should be 0x55
+ - interrupt-parent: Interrupt controller to which the chip is connected
+ - interrupts : Interrupt to which the chip is connected
+
+Example:
+
+ i2c@ {
+ /* ... */
+
+ touchscreen@55 {
+ compatible = "goodix,gt801_2plus1";
+ reg = <0x55>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 0>;
+ };
+
+ /* ... */
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index cba790b..e292126 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4743,6 +4743,12 @@ L: linux-in...@vger.kernel.org
S: Maintained
F: drivers/input/touchscreen/goodix.c
+GOODIX GT801 2PLUS1 TOUCHSCREEN
+M: Priit Laes
+L: linux-in...@vger.kernel.org
+S: Maintained
+F: drivers/input/touchscreen/gt801_2plus1.c
+
GPIO SUBSYSTEM
M: Linus Walleij
M: Alexandre Courbot
diff --git a/drivers/input/touchscreen/Kconfig
b/drivers/input/touchscreen/Kconfig
index ae33da7..c7c3324 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -322,11 +322,11 @@ config TOUCHSCREEN_FUJITSU
module will be called fujitsu-ts.
config TOUCHSCREEN_GOODIX
- tristate "Goodix I2C touchscreen"
+ tristate "Goodix GT9xx I2C touchscreen"
depends on I2C
help
- Say Y here if you have the Goodix touchscreen (such as one
- installed in Onda v975w tablets) connected to your
+ Say Y here if you have one of the Goodix GT9xx touchscreens
+ (such as one installed in Onda v975w tablet) connected to your
system. It also supports 5-finger chip models, which can be
found on ARM tablets, like Wexler TAB7200 and MSI Primo73.
@@ -335,6 +335,19 @@ config TOUCHSCREEN_GOODIX
To compile this driver as a module, choose M here: the
module will be called goodix.
+config TOUCHSCREEN_GT801_2PLUS1
+ tristate "Goodix GT801 2+1 I2C touchscreen"
+ depends on I2C
+ help
+ Say Y here if you have the Goodix GT801 2+1 touchscreen.
+ This controller is found on some older ARM tablets like
+ (Gemei G9 and Zareason Zatab).
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called gt801_2plus1.
+
config TOUCHSCREEN_ILI210X
tristate "Ilitek ILI210X based touchscreen"
depends on I2C
diff --git a/drivers/input/touchscreen/Makefile
b/drivers/input/touchscreen/Makefile
index cbaa6ab..ff25d1b4 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
obj-$(CONFIG_TOUCHSCREEN_FT6236) += ft6236.o
obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o
+obj-$(CONFIG_TOUCHSCREEN_GT801_2PLUS1) += gt801_2plus1.o
obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o
obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o
diff --git a/drivers/input/touchscreen/gt801_2plus1.c
b/drivers/input/touchscreen/gt801_2plus1.c
new file mode 100644
index 000..e2be479
--- /dev/null
+++ b/drivers/input/touchscreen/gt801_2plus1.c
@@ -0,0 +1,375 @@
+/*
+ * Driver for Goodix GT801 2+1 ARM touchscreen controllers
+ *
+ * Copyright (c) 2015 Priit Laes .
+ *
+ * This code is based on goodix.c driver (c) 2014 Red Hat Inc,
+ * various Android codedumps (c) 2010 - 2012 Goodix Technology
+ * and cleanups done by Emilio López (turl) for linux-sunxi.
+ *
+ * This program is free software; you can redistribu
[PATCH 0/2] input: Driver for Goodix GT801 2+1 touchscreen
This series adds support for Goodix GT801 2+1 touchscreen controller and hooks it up on Gemei G9 tablet. Now about GT801 2+1 - I initially tried to implement this inside the existing Goodix driver, but unfortunately there are too many small bits and pieces that would make the otherwise simple driver a complicated mess: - endianness differences of coordinate readouts - totally different touch protocol - configuration layout and version information - I2C register differences (2 bytes vs single byte) To apply the patchset, you need both linux-input/next and linux-sunxi/next merged. Patch 1 (Gemei G9 devicetree bits) should go via linux-sunxi tree. Patch 2 (GT801 2+1 driver implementation) via linux-input Priit Laes (2): ARM: dts: sun4i: gemei-g9: Add touchscreen (Goodix gt801x2) support input: gt801_2plus1 - Add initial support for Goodix GT801 2+1 .../bindings/input/touchscreen/gt801_2plus1.txt| 23 ++ MAINTAINERS| 6 + arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 26 +- drivers/input/touchscreen/Kconfig | 19 +- drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/gt801_2plus1.c | 375 + 6 files changed, 445 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/gt801_2plus1.txt create mode 100644 drivers/input/touchscreen/gt801_2plus1.c -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH net-next 2/2] net: hns: enet specisies a reference to dsaf (config and documents)
On 2015/12/6 6:19, Arnd Bergmann wrote:
> On Saturday 05 December 2015 14:10:56 yankejian wrote:
>> diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
>> b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
>> index 80411b2..ecacfa4 100644
>> --- a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
>> @@ -4,8 +4,6 @@ Required properties:
>> - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
>>"hisilicon,hns-dsaf-v1" is for hip05.
>>"hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
>> -- dsa-name: dsa fabric name who provide this interface.
>> - should be "dsafX", X is the dsaf id.
>> - mode: dsa fabric mode string. only support one of dsaf modes like these:
>> "2port-64vf",
>> "6port-16rss",
>> @@ -26,9 +24,8 @@ Required properties:
>>
>> Example:
>>
>> -dsa: dsa@c700 {
>> +dsaf0: dsa@c700 {
>> compatible = "hisilicon,hns-dsaf-v1";
>> - dsa_name = "dsaf0";
>> mode = "6port-16rss";
>> interrupt-parent = <&mbigen_dsa>;
>> reg = <0x0 0xC000 0x0 0x42
>> diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
>> b/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
>> index 41d19be..e6a9d1c 100644
>> --- a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
>> @@ -4,8 +4,9 @@ Required properties:
>> - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
>>"hisilicon,hns-nic-v1" is for hip05.
>>"hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
>> -- ae-name: accelerator name who provides this interface,
>> - is simply a name referring to the name of name in the accelerator node.
>> +- ae-handle: accelerator engine handle for hns,
>> + specifies a reference to the associating hardware driver node.
>> + see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
>> - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
>>connect to 8 PHYs. Port 0 to 1 are both used for adminstration purpose.
>> They
>>are called debug ports.
>> @@ -41,7 +42,7 @@ Example:
>>
>>
> This looks like an incompatible change, as you add and remove
> required properties. Is there a way to support both the old and
> the new style?
>
> Arnd
>
> .
Hi Arnd,
Thanks for your suggestions. it must be set the same strings in dsaf node and
every enet node before.
it seems inappropriate. as Rob Herring 's suggestions, that
would solve associating
enet with a particular dsaf. so we discus the solution with Yisen Zhuang
.
we decide to use the new way instead of the old one.
Best regards,
yankejian
>
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[PATCH 4/8] ARM: dts: imx7d: cl-som-imx7: add fec1 support
Add support for the 1-st Freescale Ethernet Controller (FEC1).
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 44849ab..97e96c6 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -43,6 +43,28 @@
arm-supply = <&sw1a_reg>;
};
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <1>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
@@ -167,6 +189,25 @@
&iomuxc {
cl-som-imx7 {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO
0x3
+ MX7D_PAD_SD2_WP__ENET1_MDC
0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC
0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0
0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1
0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2
0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3
0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL
0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC
0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0
0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1
0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2
0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3
0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL
0x1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA
0x407f
--
1.9.1
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[PATCH 0/8] Add support for CL-SOM-iMX7 and SBC-iMX7
This patch series adds support for CompuLab CL-SOM-iMX7 and SBC-iMX7 boards. CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on Freescale i.MX7 ARM Cortex-A7 System-on-Chip. SBC-iMX7 is a single board computer, implemented with the CL-SOM-iMX7 System-on-Module providing most of the functions, and SB-SOM-iMX7 carrier board providing additional peripheral functions and connectors. The SBC-iMX7 provides following features: CPU:Freescale i.MX 7Dual ARM Cortex-A7, 1GHz NEON SIMD and VFPv4 or Freescale i.MX 7Solo ARM Cortex-A7, 800MHz NEON SIMD and VFPv4 RAM:DDR3, 256MB - 2GB Storage:NAND flash, 128MB - 1GB or eMMC flash, 4GB - 32GB SPI flash, 2MB Standard full-size SD socket Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY) WiFi/BT:Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 chipset) Analog Audio: Audio codec with analog stereo output, stereo input and microphone support More details can be found here: http://www.compulab.co.il/products/computer-on-modules/cl-som-imx7-freescale-i-mx-7-system-on-module/ http://www.compulab.co.il/products/sbcs/sbc-imx7-freescale-i-mx-7-single-board-computer/ This series provides basic DT support including following features: * Memory configuration * eMMC * 2x Gigabit Ethernet ports (FEC1 and FEC2) * I2C2 bus * EEPROM * PCA9555 GPIO extender * PMIC * UART1 * USB OTG port Ilya Ledvich (8): ARM: dts: imx7d: cl-som-imx7: add basic module support ARM: dts: imx7d: cl-som-imx7: add usb otg support ARM: dts: imx7d: cl-som-imx7: add eMMC support ARM: dts: imx7d: cl-som-imx7: add fec1 support ARM: dts: imx7d: cl-som-imx7: add eeprom support ARM: dts: imx7d: cl-som-imx7: add gpio extender support ARM: dts: imx7d: cl-som-imx7: add fec2 support ARM: dts: imx7d: sbc-imx7: add basic board support Documentation/devicetree/bindings/arm/fsl.txt | 8 + arch/arm/boot/dts/Makefile| 2 + arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 294 ++ arch/arm/boot/dts/imx7d-sbc-imx7.dts | 43 4 files changed, 347 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-cl-som-imx7.dts create mode 100644 arch/arm/boot/dts/imx7d-sbc-imx7.dts -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/8] ARM: dts: imx7d: cl-som-imx7: add basic module support
CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
Freescale i.MX7 System-on-Chip family.
http://www.compulab.co.il/products/computer-on-modules/cl-som-imx7-freescale-i-mx-7-system-on-module/
Add basic DT support for standalone module (without a carrier board):
* Memory configuration
* I2C2 bus
* PMIC
* UART1
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 +
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 150 ++
3 files changed, 155 insertions(+)
create mode 100644 arch/arm/boot/dts/imx7d-cl-som-imx7.dts
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
b/Documentation/devicetree/bindings/arm/fsl.txt
index 34c88b0..30b0ba1 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX7D CL-SOM-iMX7 Board
+Required root node properties:
+- compatible = "compulab,cl-som-imx7", "fsl,imx7d";
+
Generic i.MX boards
---
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..83ed521 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -350,6 +350,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
+ imx7d-cl-som-imx7.dtb \
imx7d-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
new file mode 100644
index 000..6fa6580
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -0,0 +1,150 @@
+/*
+ * Support for CompuLab CL-SOM-iMX7 System-on-Module
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Ilya Ledvich
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include
+#include "imx7d.dtsi"
+
+/ {
+ model = "CompuLab CL-SOM-iMX7";
+ compatible = "compulab,cl-som-imx7", "fsl,imx7d";
+
+ memory {
+ reg = <0x8000 0x1000>; /* 256 MB - minimal
configuration */
+ };
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic: pfuze3000@08 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ /* use sw1c_reg to align with pfuze100/pfuze200 */
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <185>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <165>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <515>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <300>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-m
[PATCH 2/8] ARM: dts: imx7d: cl-som-imx7: add usb otg support
Add support for single USB OTG port.
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 6fa6580..a8f52cf 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -21,6 +21,22 @@
memory {
reg = <0x8000 0x1000>; /* 256 MB - minimal
configuration */
};
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
};
&cpu0 {
@@ -131,6 +147,13 @@
status = "okay";
};
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
&iomuxc {
cl-som-imx7 {
pinctrl_i2c2: i2c2grp {
@@ -146,5 +169,11 @@
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX0x79
>;
};
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /*
OTG PWREN */
+ >;
+ };
};
};
--
1.9.1
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[PATCH 8/8] ARM: dts: imx7d: sbc-imx7: add basic board support
SBC-iMX7 is a single board computer designed for industrial
and embedded applications. It is based on the Freescale i.MX7
system-on-chip. SBC-iMX7 is implemented with the CL-SOM-iMX7
System-on-Module providing most of the functions, and SB-SOM-iMX7
carrier board providing additional peripheral functions and
connectors.
http://www.compulab.co.il/products/sbcs/sbc-imx7-freescale-i-mx-7-single-board-computer/
http://www.compulab.co.il/products/computer-on-modules/cl-som-imx7-freescale-i-mx-7-system-on-module/
Add basic board support, including SD card as a secondary boot and storage
device
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 +++
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/imx7d-sbc-imx7.dts | 43 +++
3 files changed, 48 insertions(+)
create mode 100644 arch/arm/boot/dts/imx7d-sbc-imx7.dts
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
b/Documentation/devicetree/bindings/arm/fsl.txt
index 30b0ba1..15307d3 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -57,6 +57,10 @@ i.MX7D CL-SOM-iMX7 Board
Required root node properties:
- compatible = "compulab,cl-som-imx7", "fsl,imx7d";
+i.MX7D SBC-iMX7 Single Board Computer
+Required root node properties:
+- compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
+
Generic i.MX boards
---
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 83ed521..72ef172 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -351,6 +351,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
+ imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7d-sbc-imx7.dts
b/arch/arm/boot/dts/imx7d-sbc-imx7.dts
new file mode 100644
index 000..3d5384a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-sbc-imx7.dts
@@ -0,0 +1,43 @@
+/*
+ * Support for CompuLab SBC-iMX7 Single Board Computer
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Ilya Ledvich
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include "imx7d-cl-som-imx7.dts"
+
+/ {
+ model = "CompuLab SBC-iMX7";
+ compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&iomuxc {
+ cl-som-imx7 {
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ MX7D_PAD_SD1_CD_B__GPIO5_IO00x59 /*
CD */
+ MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /*
WP */
+ >;
+ };
+ };
+};
--
1.9.1
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[PATCH 7/8] ARM: dts: imx7d: cl-som-imx7: add fec2 support
Add support for the 2-nd Freescale Ethernet Controller (FEC2).
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 30bbdcd..77b6587 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -62,9 +62,26 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
};
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
};
};
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <1>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
@@ -221,6 +238,23 @@
>;
};
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC
0x1
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0
0x1
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1
0x1
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2
0x1
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3
0x1
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL
0x1
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC
0x1
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0
0x1
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1
0x1
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2
0x1
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3
0x1
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL
0x1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA
0x407f
--
1.9.1
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[PATCH 5/8] ARM: dts: imx7d: cl-som-imx7: add eeprom support
Add support for the module EEPROM over I2C2 bus.
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 97e96c6..b938d9e 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -159,6 +159,12 @@
};
};
};
+
+ eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
&uart1 {
--
1.9.1
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[PATCH 6/8] ARM: dts: imx7d: cl-som-imx7: add gpio extender support
Add support for PCA9555 GPIO extender over I2C2 bus.
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index b938d9e..30bbdcd 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -160,6 +160,13 @@
};
};
+ pca9555: pca9555@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
--
1.9.1
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[PATCH 3/8] ARM: dts: imx7d: cl-som-imx7: add eMMC support
Add support for eMMC as a main storage.
Signed-off-by: Ilya Ledvich
Acked-by: Igor Grinberg
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index a8f52cf..44849ab 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -154,6 +154,17 @@
status = "okay";
};
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <4>;
+ bus-width = <8>;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
&iomuxc {
cl-som-imx7 {
pinctrl_i2c2: i2c2grp {
@@ -175,5 +186,21 @@
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /*
OTG PWREN */
>;
};
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
+ >;
+ };
};
};
--
1.9.1
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RE: [PATCH 0/2] power: Add support for TI BQ24261 charger
Hi Sebastian, > On Thu, Oct 29, 2015 at 10:07:03PM +0530, Ramakrishna Pallala wrote: > > This patch series adds the support for TI BQ24261 charger driver. > > > > TI BQ24261 charger driver relies on extcon notifications to get the > > charger cable type and based on that it will set the charging parameters. > > I wonder if there is any new version of this patchset, that I missed with the > comments from Krzysztof and Andreas being taken care of? I was bit busy lately. I will address both Krzysztof and Andreas comments and submit the new patchset in the coming few days. Thanks, Ram -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] of: fix build failure
On Sat, Dec 05, 2015 at 12:09:41PM +0100, Geert Uytterhoeven wrote: > Hi Sudip > > On Thu, Dec 3, 2015 at 9:38 AM, Sudip Mukherjee > wrote: > > We are having build failure with next-20151202 for sparc allmodconfig > > with the error messages: > > undefined reference to 'of_io_request_and_map' > > > > CONFIG_OF is defined for sparc so it is expected that we have a > > definition of of_io_request_and_map() but of/address.c is only compiled > > if it is !SPARC. > > No, it's compiled depending on CONFIG_OF_ADDRESS... yes, ofcourse. I did it looking at: config OF_ADDRESS def_bool y depends on !SPARC && HAS_IOMEM > > > Signed-off-by: Sudip Mukherjee > > --- > > +#if defined(CONFIG_OF) && !defined(CONFIG_SPARC) > > ... hence wouldn't it be better to use "#ifdef CONFIG_OF_ADDRESS" instead? > I will test with today's next and send v2. regards sudip -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 10/10] dt-bindings: Add DSIv2 documentation
On 12/02/2015 02:04 PM, Stephen Boyd wrote: On 12/02, Stephen Boyd wrote: My only thought there would be to make of_clk_set_defaults() wait until both clocks are registered before it does any parent setting. But only in the case where the assigned parents contains a clock that is provided by the node being processed. I suppose the simplest thing to do would be to skip it during the device driver probe and handle it when the clk provider is registered. Actually it looks like we already have the code for that. if (clkspec.np == node && !clk_supplier) return 0; So assigned parents should "just work"? I tried using assigned-parents and it works fine. The issue you mentioned above doesn't apply in our case, because we have two different devices for "dsi" and "dsi_phy". dsi_phy is the clock provider here and dsi is the one that wants to assign clocks. If there was only one dsi device representing both DSI and PHY, then we'd hit the condition you mentioned. Thanks, Archit -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/9] ARM: dts: add dts files for hi3519-demb board
On 2015/12/4 18:49, Arnd Bergmann wrote:
> On Friday 04 December 2015 10:27:58 xuejiancheng wrote:
>>>
+sysctrl: system-controller@1202 {
+compatible = "hisilicon,sysctrl";
+reg = <0x1202 0x1000>;
+reboot-offset = <0x4>;
+};
>>>
>>> Is this one identical to the one in hip04?
>>>
>>> If not, pick a new unique compatible string
>>
>> Yes. It's compatible with the one in hip04.
>
> Ok, we should add a compatible string for that then, as the hip04 apparently
> has a slightly different layout from hip01.
>
> Can you add a separate patch to clarify the existing hisilicon,sysctrl nodes?
>
> It look like hi3620 accidentally uses the same string as hip04 already
> but is actually a bit different.
>
> Maybe split out the sysctrl binding from
> Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt, as it has
> you already have a couple of those, and it's not clear how they relate
> to one another.
>
> If we introduce a string for all hip04 compatible sysctrl devices, we should
> document that and use it consistently, so hi3519 becomes
>
> compatible = "hisilicon,hi3519-sysctrl", "hisilicon,hip04-sysctrl",
> "hisilicon,sysctrl";
>
> but I'd clarify in the binding documentation that "hisilicon,sysctrl" should
> only be used for hip04 and hi3519 but not the others.
>
> As this seems to be a standard part, we can also think about making a
> high-level driver for in in drivers/soc rather than relying on the syscon
> driver which we tend to use more for one-off devices with random register
> layouts.
>
Sorry. I didn't understand your meaning well and maybe I gave you a wrong
description.
Please allow me to clarify it again.
The "sysctrl" nodes here is just used for the "reboot" function. It is
corresponding to
the driver "drivers/power/reset/hisi-reboot.c". The compatible string in the
driver is
"hisilicon,sysctrl".
The layout of this block is also different from the one in HiP04.
+
+crg: crg@1201 {
+compatible = "hisilicon,hi3519-crg";
>>>
>>>
>>> what is a "crg"? Is there a standard name for these?
>>
>> The "crg" means Clock and Reset Generator. It's a block which supplies clock
>> and reset signals for other modules in the chip. I used "hi3519-clock"
>> in last version patch. Rob Herring suggested that it's better to use
>> "hi3519-crg"
>> as the compatible string if it's a whole block.
>>
>> what about writing like this？
>>
>> crg: clock-reset-controller@1201 {
>> compatible = "hisilicon,hi3519-crg";
>> }
>>
>
> Ok, that's better.
>
> Arnd
>
> .
>
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[PATCH v10 03/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those as hardware limite. For example, RK3288
only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
like "link-rate = 0x0a" "lane-count = 4". (Thierry)
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 039aaab..1f66deb 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct
analogix_dp_device *dp,
/*
* For DP rev.1.1, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+* For DP rev.1.2, Maximum link rate of Main Link lanes
+* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
*/
analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct
analogix_dp_device *dp,
analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
- (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+ (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+ (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
analogix_dp_enable_enhanced_mode(dp, 1);
- analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
- analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
#define MAX_EQ_LOOP 5
enum link_rate_type {
- LINK_RATE_1_62GBPS = 0x06,
- LINK_RATE_2_70GBPS = 0x0a
+ LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+ LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+ LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
};
enum link_lane_count_type {
--
1.9.1
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[PATCH v10 09/17] phy: Add driver for rockchip Display Port PHY
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
BIT(4) -> BIT(20)
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
Changes in v7:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
Changes in v2: None
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 151 ++
3 files changed, 159 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..7355819 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..b1700cd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+=
phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 000..3cb3bf8
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct clk *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ retu
[PATCH v10 04/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof)
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfacs
would modify the original drm_display_mode timing directly (whether those
properties exists or not).
Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)
Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
struct drm_display_info. (Thierry)
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 14 +-
3 files changed, 103 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 1f66deb..5f542b7 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
return;
}
- ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-dp->video_info->link_rate);
+ ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+dp->video_info.link_rate);
if (ret) {
dev_err(dp->dev, "unable to do link train\n");
return;
@@ -1032,6 +1032,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge
*bridge)
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+ struct drm_display_mode *orig_mode,
+ struct drm_display_mode *mode)
+{
+ struct analogix_dp_device *dp = bridge->driver_private;
+ struct drm_display_info *display_info = &dp->connector->display_info;
+ struct video_info *video = &dp->video_info;
+ struct device_node *dp_node = dp->dev->of_node;
+ int vic;
+
+ /* Input video interlaces & hsync pol & vsync pol */
+ video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+ video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+ /* Input video dynamic_range & colorimetry */
+ vic = drm_match_cea_mode(mode);
+ if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+ (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+ video->dynamic_range = CEA;
+ video->ycbcr_coeff = COLOR_YCBCR601;
+ } else if (vic) {
+ video->dynamic_range = CEA;
+ video->ycbcr_coeff = COLOR_YCBCR709;
+ } else {
+ video->dynamic_range = VESA;
+ video->ycbcr_coeff = COLOR_YCBCR709;
+ }
+
+ /* Input vide bpc and color_formats */
+ switch (display_info->bpc) {
+ case 12:
+ video->color_depth = COLOR_12;
+ break;
+ case 10:
+ video->color_depth = COLOR_10;
+ break;
+ case 8:
+ video->color_depth = COLOR_8;
+ break;
+ case 6:
+ video->color_depth = COLOR_6;
+ break;
+ default:
+ video->color_depth = COLOR_8;
+ break;
+ }
+ if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+ video->color_space = COLOR_YCBCR444;
+ else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+ video->color_space = COLOR_YCBCR422;
+ else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+ video->color_space = COLOR_RGB;
+ else
+ video->color_space = COLOR_RGB;
+
+ /*
+* NOTE: those property parsing code is used for providing backward
+* compatibility for samsung platform.
+* Due to we used the "of_property_read_u32" interfaces, when this
+* property isn't present, the "video_info" can keep the original
+*
[PATCH v10 11/17] drm: rockchip: vop: add bpc and color mode setting
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
video mode, but hard code CRTC video output mode to RGBaaa.
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 ++---
4 files changed, 51 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct
drm_encoder *encoder,
static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
{
struct rockchip_dp_device *dp = to_dp(encoder);
+ struct drm_connector *cn = &dp->connector;
+ int ret = -1;
u32 val;
- int ret;
- ret = rockchip_drm_crtc_mode_config(encoder->crtc,
- DRM_MODE_CONNECTOR_eDP,
- ROCKCHIP_OUT_MODE_);
+ /*
+* FIXME(Yakir): driver should configure the CRTC output video
+* mode with the display information which indicated the monitor
+* support colorimetry.
+*
+* But don't know why the CRTC driver seems could only output the
+* RGBaaa rightly. For example, if connect the "innolux,n116bge"
+* eDP screen, EDID would indicated that screen only accepted the
+* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+* screen would show a blue picture (RGB888 show a green picture).
+* But if I configure CTRC to RGBaaa, and eDP driver still keep
+* RGB666 input video mode, then screen would works prefect.
+*/
+ if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+ ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+ DRM_MODE_CONNECTOR_eDP,
+ 10, DRM_COLOR_FORMAT_RGB444);
if (ret < 0) {
- dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+ dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
return;
}
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
drm_encoder *encoder)
static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
{
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
- ROCKCHIP_OUT_MODE_);
+ 10, DRM_COLOR_FORMAT_RGB444);
}
static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs =
{
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev,
int pipe);
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
- int out_mode);
+ int bpc, int color);
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
struct device *dev);
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
int connector_type,
- int out_mode)
+ int bpc, int color)
{
struct vop *vop = to_vop(crtc);
+ /*
+* RK32
[PATCH v10 10/17] dt-bindings: add document for rockchip dp phy
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10: None
Changes in v9: None
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in document. (Rob & Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 22 ++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 000..00902cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+
+
+Required properties:
+- compatible : should be one of the following supported values:
+- "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+};
--
1.9.1
--
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[PATCH v10 14/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: None
.../bindings/display/bridge/analogix_dp.txt| 4 ++-
.../bindings/display/exynos/exynos_dp.txt | 1 +
.../display/rockchip/analogix_dp-rockchip.txt | 1 +
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 ++
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 9 ++
6 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
index 7659a7a..74f0e80 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
from general PHY binding: Should be "dp".
Optional properties for dp-controller:
+ -analogix,need-force-hpd:
+ Indicate driver need force hpd when hpd detect failed, this
+ is used for some eDP screen which don't have hpd signal.
-hpd-gpios:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
*
Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
-
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
---
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 9905081..8800164 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding
document:
-phys (required)
-phy-names (required)
-hpd-gpios (optional)
+ -analogix,need-force-hpd (optional)
-video interfaces (optional)
Deprecated properties for DisplayPort:
diff --git
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index dae86c4..1f1e594 100644
---
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -32,6 +32,7 @@ For the below properties, please refer to Analogix DP binding
document:
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
---
Example:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a11504b..94968e4 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device
*dp)
{
int timeout_loop = 0;
- while (analogix_dp_get_plug_in_status(dp) != 0) {
+ while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+ if (analogix_dp_get_plug_in_status(dp) == 0)
+ return 0;
+
timeout_loop++;
- if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
- dev_err(dp->dev, "failed to get hpd plug status\n");
- return -ETIMEDOUT;
- }
usleep_range(10, 11);
}
+ /*
+* Some edp screen do not have hpd signal, so we can't just
+* return failed when hpd plug in detect failed, DT property
+* "need-force-hpd" would indicate whether driver need this.
+*/
+ if (!dp->need_force_hpd)
+ return -ETIMEDOUT;
+
+ /*
+* The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+* will not work, so we need to give a force hpd action to
+* set HPD_STATUS manually.
+*/
+ dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+ analogix_dp_force_hpd(dp);
+
+ if (analogix_dp_get_plug_in_status(dp) != 0) {
+ dev_err(dp
[PATCH v10 12/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12
2 files changed, 60 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
#include
#include
+#include
+
#include "analogix_dp_core.h"
#include "analogix_dp_reg.h"
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device
*dp)
reg = SEL_24M | TX_DVDD_BIT_1_0625V;
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+ if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+ writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+ writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+ writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+ writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+ writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+ }
+
reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct
analogix_dp_device *dp,
bool enable)
{
u32 reg;
+ u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+ if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+ phy_pd_addr = ANALOGIX_DP_PD;
switch (block) {
case AUX_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= AUX_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~AUX_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH0_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH0_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH0_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH1_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH1_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH1_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH2_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH2_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH2_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg,
[PATCH v10 15/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10:
- Revert parts of Gustavo Padovan's changes in commit:
drm/exynos: do not start enabling DP at bind() phase
Add dp phy poweron function in bind time.
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 94968e4..0f42d73 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = analogix_dp_detect_hpd(dp);
- if (ret) {
- /* Cable has been disconnected, we're done */
- return;
- }
-
ret = analogix_dp_handle_edid(dp);
if (ret) {
dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
{
+ struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+ if (analogix_dp_detect_hpd(dp))
+ return connector_status_disconnected;
+
return connector_status_connected;
}
EXPORT_SYMBOL_GPL(analogix_dp_detect);
@@ -1308,6 +1307,8 @@ int analogix_dp_bind(struct device *dev, struct
drm_device *drm_dev,
pm_runtime_enable(dev);
+ phy_power_on(dp->phy);
+
ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
irq_flags, "analogix-dp", dp);
if (ret) {
--
1.9.1
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[PATCH v10 16/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
power on before driver try to read edid message.
Changes in v3:
- Add edid modes parse support
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 26
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++---
2 files changed, 42 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 0f42d73..aa1a9be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char
analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
static int analogix_dp_read_edid(struct analogix_dp_device *dp)
{
- unsigned char edid[EDID_BLOCK_LENGTH * 2];
+ unsigned char *edid = dp->edid;
unsigned int extend_block = 0;
unsigned char sum;
unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = analogix_dp_handle_edid(dp);
- if (ret) {
- dev_err(dp->dev, "unable to handle edid\n");
- return;
- }
-
ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
dp->video_info.max_link_rate);
if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
int analogix_dp_get_modes(struct device *dev)
{
struct analogix_dp_device *dp = dev_get_drvdata(dev);
+ struct edid *edid = (struct edid *)dp->edid;
int num_modes = 0;
+ if (dp->plat_data && dp->plat_data->panel) {
+ if (drm_panel_prepare(dp->plat_data->panel)) {
+ DRM_ERROR("failed to setup the panel\n");
+ return -EINVAL;
+ }
+ }
+
+ if (analogix_dp_handle_edid(dp)) {
+ dev_err(dp->dev, "unable to handle edid\n");
+ return -EINVAL;
+ }
+
+ drm_mode_connector_update_edid_property(dp->connector, edid);
+ num_modes += drm_add_edid_modes(dp->connector, edid);
+
if (dp->plat_data->panel)
num_modes += drm_panel_get_modes(dp->plat_data->panel);
@@ -1309,6 +1319,8 @@ int analogix_dp_bind(struct device *dev, struct
drm_device *drm_dev,
phy_power_on(dp->phy);
+ analogix_dp_init_dp(dp);
+
ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
irq_flags, "analogix-dp", dp);
if (ret) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d3c7e0a..2bd2e0d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR 0x50
+#define I2C_E_EDID_DEVICE_ADDR 0x30
+
+#define EDID_BLOCK_LENGTH 0x80
+#define EDID_HEADER_PATTERN0x00
+#define EDID_EXTENSION_FLAG0x7e
+#define EDID_CHECKSUM 0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
+
enum link_rate_type {
LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
int dpms_mode;
int hpd_gpio;
boolneed_force_hpd;
+ unsigned char edid
[PATCH v10 13/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10:
- Remove the surplus "plat_data" check. (Heiko)
- switch (dp->plat_data && dp->plat_data->dev_type) {
+ switch (dp->plat_data->dev_type) {
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 4 +--
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 5f542b7..a11504b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device
*dp)
return;
}
- ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-dp->video_info.link_rate);
+ ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+dp->video_info.max_link_rate);
if (ret) {
dev_err(dp->dev, "unable to do link train\n");
return;
@@ -1158,16 +1158,25 @@ static int analogix_dp_dt_parse_pdata(struct
analogix_dp_device *dp)
struct device_node *dp_node = dp->dev->of_node;
struct video_info *video_info = &dp->video_info;
- if (of_property_read_u32(dp_node, "samsung,link-rate",
-&video_info->link_rate)) {
- dev_err(dp->dev, "failed to get link-rate\n");
- return -EINVAL;
- }
-
- if (of_property_read_u32(dp_node, "samsung,lane-count",
-&video_info->lane_count)) {
- dev_err(dp->dev, "failed to get lane-count\n");
- return -EINVAL;
+ switch (dp->plat_data->dev_type) {
+ case RK3288_DP:
+ /*
+* Like Rk3288 DisplayPort TRM indicate that "Main link
+* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+*/
+ video_info->max_link_rate = 0x0A;
+ video_info->max_lane_count = 0x04;
+ break;
+ case EXYNOS_DP:
+ /*
+* NOTE: those property parseing code is used for
+* providing backward compatibility for samsung platform.
+*/
+ of_property_read_u32(dp_node, "samsung,link-rate",
+&video_info->max_link_rate);
+ of_property_read_u32(dp_node, "samsung,lane-count",
+&video_info->max_lane_count);
+ break;
}
return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index e37cef6..e6f8243 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
enum color_coefficient ycbcr_coeff;
enum color_depth color_depth;
- enum link_rate_type link_rate;
- enum link_lane_count_type lane_count;
+ enum link_rate_type max_link_rate;
+ enum link_lane_count_type max_lane_count;
};
struct link_train {
--
1.9.1
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[PATCH v10 17/17] drm: bridge: analogix/dp: expand the look time for waiting AUX CH reply
After test on rockchiop platform, i found sometims driver would failed
at reading EDID message. After debugging more, i found that it's okay
to read_a byte from i2c, but it would failed at AUX transcation if we
try to ready multi-bytes from i2c.
Driver just can't received the AUX CH reply command, even no AUX error
code. I may guess that the AUX wait time is not enough, so I try to
expand the AUX wait time, and i do see this could fix the EDID read
failed at rockchip platform.
And I thought that expand the wait time won't hurt Exynos platform too
much, cause Exynos didn't have this problem, then driver would received
the reply command very soon, so no more additional wait time would bring
to Exynos platform.
Signed-off-by: Yakir Yang
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index c7e2959..dc376bd 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -482,7 +482,7 @@ int analogix_dp_start_aux_transaction(struct
analogix_dp_device *dp)
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
while (!(reg & RPLY_RECEIV)) {
timeout_loop++;
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+ if (DP_TIMEOUT_LOOP_COUNT * 10 < timeout_loop) {
dev_err(dp->dev, "AUX CH command reply failed!\n");
return -ETIMEDOUT;
}
--
1.9.1
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[PATCH v10 07/17] drm: rockchip: dp: add rockchip platform dp driver
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example DT node, and remove the regulator iomux setting
in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
and leave "sclk_edp" to analogix dp core driver which name to "dp",
and leave "pclk_edp" to rockchip dp platform driver which name to
"pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
drivers/gpu/drm/rockchip/Kconfig| 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442
include/drm/bridge/analogix_dp.h| 1 +
4 files changed, 453 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..686cb49 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_ANALOGIX_DP
+ tristate "Rockchip specific extensions for Analogix DP driver"
+ depends on DRM_ROCKCHIP
+ select DRM_ANALOGIX_DP
+ help
+ This selects support for Rockchip SoC specific extensions
+ for the Analogix Core DP driver. If you want to enable DP
+ on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan
+ * Yakir Yang
+ * Jeff Chen
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON60x025c
+#define GRF_EDP_LCD_SEL_MASKBIT(5)
+#define GRF_EDP_SEL_VOP_LIT BIT(5)
+#define GRF_EDP_SEL_VOP_BIG 0
+
+struct rockchip_dp_device {
+ struct drm_device*drm_dev;
+ struct device*dev;
+ struct drm_encoder encoder;
+ struct drm_connector connector;
+ struct drm_display_mode mode;
+
+ struct clk *pclk;
+ struct regmap*grf;
+ struct reset_control *rst;
+
+ struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+ reset_control_assert(dp->rst);
+ usleep_range(10, 20);
+ reset_control_de
[PATCH v10 08/17] dt-bindings: add document for rockchip variant of analogix_dp
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10: None
Changes in v9:
- Document more details for 'ports' property.
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../display/rockchip/analogix_dp-rockchip.txt | 91 ++
1 file changed, 91 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 000..dae86c4
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,91 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: there are 2 port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+Port 0: contained 2 endpoints, connecting to the ouput of vop.
+Port 1: contained 1 endpoint, connecting to the input of panel.
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+---
+
+Example:
+ dp-controller: dp@ff97 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff97 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 11 RK_FUNC_2
&pcfg_pull_none>;
+ };
+ };
+ };
--
1.9.1
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[PATCH v10 05/17] dt-bindings: add document for analogix display port driver
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
"analogix,color-space" & "analogix,color-depth" &
"analogix,link-rate" & "analogix,lane-count"&
"analogix,ycbcr-coeff" & "analogix,dynamic-range" &
"vsync-active-high"& "hsync-active-high" & "interlaces"
Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
Changes in v2: None
.../bindings/display/bridge/analogix_dp.txt| 50 +
.../bindings/display/exynos/exynos_dp.txt | 65 --
2 files changed, 72 insertions(+), 43 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
new file mode 100644
index 000..7659a7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+ -compatible:
+ platform specific such as:
+* "samsung,exynos5-dp"
+* "rockchip,rk3288-dp"
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+ -clocks:
+ from common clock binding: handle to dp clock.
+ -clock-names:
+ from common clock binding: Shall be "dp".
+ -interrupt-parent:
+ phandle to Interrupt combiner node.
+ -phys:
+ from general PHY binding: the phandle for the PHY device.
+ -phy-names:
+ from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+ -hpd-gpios:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug detection
+ -port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+ * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+ *
Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+---
+
+Example:
+
+ dp-controller {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b 0x1>;
+ interrupts = <10 3>;
+ interrupt-parent = <&combiner>;
+ clocks = <&clock 342>;
+ clock-names = "dp";
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+ };
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 64693f2..9905081 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
- -samsung,color-space:
- input video data format.
- COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
- -samsung,dynamic-range:
- dynamic range for input video data.
- VESA = 0, CEA = 1
- -samsung,ycbcr-coeff:
- YCbCr co-efficients for input video.
- COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
- -samsung,color-depth:
- number of bits per colour component.
- COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
- -samsung,link-rate:
- link rate supported by the panel.
-
[PATCH v10 06/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios = <&gpx2 6 0>;
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/exynos5250-arndale.dts | 2 --
arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 --
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +---
arch/arm/boot/dts/exynos5250-spring.dts | 4 +---
arch/arm/boot/dts/exynos5420-peach-pit.dts| 4 +---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 --
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +---
7 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index c000532..b1790cf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
&dp {
status = "okay";
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0f5dcd4..f30c2db 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
&dp {
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 5cb33ba..b96624b 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -236,12 +236,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts
b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
- samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
};
&ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..2f37c87 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..f67344f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -93,8 +93,6 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..363c95f 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++
[PATCH v10 02/17] drm: bridge: analogix/dp: fix some obvious code style
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit message, and
remove some controversial style (Krzysztof)
- analogix_dp_write_byte_to_dpcd(
- dp, DP_TEST_RESPONSE,
+ analogix_dp_write_byte_to_dpcd(dp,
+ DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE);
Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 72 ++--
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 124 ++--
3 files changed, 163 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index cd86413..039aaab 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device
*dp)
while (analogix_dp_get_plug_in_status(dp) != 0) {
timeout_loop++;
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+ if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "failed to get hpd plug status\n");
return -ETIMEDOUT;
}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device
*dp)
/* Read Extension Flag, Number of 128-byte EDID extension blocks */
retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
- EDID_EXTENSION_FLAG,
- &extend_block);
+ EDID_EXTENSION_FLAG,
+ &extend_block);
if (retval)
return retval;
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device
*dp)
dev_dbg(dp->dev, "EDID data includes a single extension!\n");
/* Read EDID data */
- retval = analogix_dp_read_bytes_from_i2c(dp,
I2C_EDID_DEVICE_ADDR,
+ retval = analogix_dp_read_bytes_from_i2c(dp,
+ I2C_EDID_DEVICE_ADDR,
EDID_HEADER_PATTERN,
EDID_BLOCK_LENGTH,
&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device
*dp)
}
analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
- &test_vector);
+ &test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) {
analogix_dp_write_byte_to_dpcd(dp,
DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device
*dp)
/* Read EDID data */
retval = analogix_dp_read_bytes_from_i2c(dp,
- I2C_EDID_DEVICE_ADDR,
- EDID_HEADER_PATTERN,
- EDID_BLOCK_LENGTH,
- &edid[EDID_HEADER_PATTERN]);
+ I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+ EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
if (retval != 0) {
dev_err(dp->dev, "EDID Read failed!\n");
return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct
analogix_dp_device *dp)
return -EIO;
}
- analogix_dp_read_byte_from_dpcd(dp,
- DP_TEST_REQUEST,
- &test_vector);
+ analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+ &test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) {
analogix_dp_write_byte_to_dpcd(dp,
- DP_TEST_EDID_CHECKSUM,
-
[PATCH v10 0/17] Add Analogix Core Display Port Driver
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM
But there are still three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
register).
This series have been well tested on Rockchip platform with eDP panel on
Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier@Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
BIT(4) -> BIT(20)
- Remove the surplus "plat_data" check. (Heiko)
- switch (dp->plat_data && dp->plat_data->dev_type) {
+ switch (dp->plat_data->dev_type) {
- Revert parts of Gustavo Padovan's changes in commit:
drm/exynos: do not start enabling DP at bind() phase
Add dp phy poweron function in bind time.
Changes in v9:
- Document more details for 'ports' property.
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
- Modify the commit subject name. (Heiko)
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof)
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
- Simplify the commit message. (Kishon)
Changes in v6:
- Fix the Kconfig recursive dependency (Javier)
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios = <&gpx2 6 0>;
Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
attch function. Cause once platform failed at attach, core driver should
still failed, so no need to init connector before platform attached
(Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit message, and
remove some controversial style (Krzysztof)
- analogix_dp_write_byte_to_dpcd(
- dp, DP_TEST_RESPONSE,
+ analogix_dp_write_byte_to_dpcd(dp,
+ DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfacs
would modify the original drm_display_mode timing directly (whether those
properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example DT node, and remove the regulator iomux setting
in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfac
Re: [PATCH 0/2] Add R8A7791 EtherAVB DT support
On Fri, Dec 04, 2015 at 05:00:37PM +0300, Sergei Shtylyov wrote: > Hello. > > On 12/3/2015 1:19 AM, Sergei Shtylyov wrote: > > >Here's the set of 2 patches against Simon Horman's 'renesas.git' repo, > >'renesas-devel-20151201-v4.4-rc3' tag. Here we add the EtherAVB device tree > >support for the R8A7791 SoC. The 2nd patch depends on the Simon's recent > >EtherAVB driver patches in order to work... > >Well, not exactly "work", as the node is disabled. Anyway, Simon's > patches got merged to net-next.git by Dave, so I think this series can be > merged now as well... Thanks, I have queued these up. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] arm64: dts: mt8173: Add nor flash node
On Mon, 2015-12-07 at 12:34 +0800, bayi cheng wrote:
> On Mon, 2015-12-07 at 12:09 +0800, Daniel Kurtz wrote:
> > Bayi,
> >
> > On Mon, Dec 7, 2015 at 11:53 AM, Bayi Cheng wrote:
> > > Add Mediatek nor flash node
> > >
> > > Signed-off-by: Bayi Cheng
> > > Acked-by: Brian Norris
> > > ---
> > > Previous version of this patch is
> > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/386005.html
> > > Drop flash node from mt8173.dtsi accroding review comment
> >
> > Is there a flash on mt8173-evb that can be accessed by the nor_flash ?
> > If so, can you include flash@0 node in the mt8173-evb.dts.
> >
> > -Dan
> >
> Hi Daniel, Thanks for your comments! you are right, there is a flash on
> mt8173-evb which can be accessed by the nor_flash, and I will include
> flash@0 node in mt8173-evb.dts (kernel v3.18) too.
>
> Bayi
Hi Dan, I have reworked a EVB board for spi nor verify, we replaced the
spi nand flash with spi nor flash on EVB board,
and our shipping EVB board haven't support spi nor flash, So I will not
include flash@0 node in the mt8173-evb.dts. I am sorry to made you
confused!
Bayi
> > >
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 11 +++
> > > 1 file changed, 11 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > index 4dd5f93..af08e97 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > @@ -387,6 +387,17 @@
> > > status = "disabled";
> > > };
> > >
> > > + nor_flash: spi@1100d000 {
> > > + compatible = "mediatek,mt8173-nor";
> > > + reg = <0 0x1100d000 0 0xe0>;
> > > + clocks = <&pericfg CLK_PERI_SPI>,
> > > +<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> > > + clock-names = "spi", "sf";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > i2c3: i2c@1101 {
> > > compatible = "mediatek,mt8173-i2c";
> > > reg = <0 0x1101 0 0x70>,
> > > --
> > > 1.8.1.1.dirty
> > >
>
>
>
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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Re: [PATCH] arm64: dts: mt8173: Add nor flash node
On Mon, 2015-12-07 at 12:09 +0800, Daniel Kurtz wrote:
> Bayi,
>
> On Mon, Dec 7, 2015 at 11:53 AM, Bayi Cheng wrote:
> > Add Mediatek nor flash node
> >
> > Signed-off-by: Bayi Cheng
> > Acked-by: Brian Norris
> > ---
> > Previous version of this patch is
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/386005.html
> > Drop flash node from mt8173.dtsi accroding review comment
>
> Is there a flash on mt8173-evb that can be accessed by the nor_flash ?
> If so, can you include flash@0 node in the mt8173-evb.dts.
>
> -Dan
>
Hi Daniel, Thanks for your comments! you are right, there is a flash on
mt8173-evb which can be accessed by the nor_flash, and I will include
flash@0 node in mt8173-evb.dts (kernel v3.18) too.
Bayi
> >
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 4dd5f93..af08e97 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -387,6 +387,17 @@
> > status = "disabled";
> > };
> >
> > + nor_flash: spi@1100d000 {
> > + compatible = "mediatek,mt8173-nor";
> > + reg = <0 0x1100d000 0 0xe0>;
> > + clocks = <&pericfg CLK_PERI_SPI>,
> > +<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> > + clock-names = "spi", "sf";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > i2c3: i2c@1101 {
> > compatible = "mediatek,mt8173-i2c";
> > reg = <0 0x1101 0 0x70>,
> > --
> > 1.8.1.1.dirty
> >
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Re: [PATCH] arm64: dts: mt8173: Add nor flash node
Bayi,
On Mon, Dec 7, 2015 at 11:53 AM, Bayi Cheng wrote:
> Add Mediatek nor flash node
>
> Signed-off-by: Bayi Cheng
> Acked-by: Brian Norris
> ---
> Previous version of this patch is
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/386005.html
> Drop flash node from mt8173.dtsi accroding review comment
Is there a flash on mt8173-evb that can be accessed by the nor_flash ?
If so, can you include flash@0 node in the mt8173-evb.dts.
-Dan
>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 4dd5f93..af08e97 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -387,6 +387,17 @@
> status = "disabled";
> };
>
> + nor_flash: spi@1100d000 {
> + compatible = "mediatek,mt8173-nor";
> + reg = <0 0x1100d000 0 0xe0>;
> + clocks = <&pericfg CLK_PERI_SPI>,
> +<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> i2c3: i2c@1101 {
> compatible = "mediatek,mt8173-i2c";
> reg = <0 0x1101 0 0x70>,
> --
> 1.8.1.1.dirty
>
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Re: [PATCH 1/1] stmmac: socfpga: Provide dt node to config ptp clk source.
From: Phil Reid
Date: Mon, 7 Dec 2015 09:38:40 +0800
> @@ -116,6 +118,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac
> *dwmac, struct device *
> return -EINVAL;
> }
>
> + dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "f2h_ptp_ref_clk");
> +
> +
Too many empty lines.
> np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
> if (np_splitter) {
> if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
> @@ -171,6 +176,11 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac
> *dwmac)
> ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
> ctrl |= val << reg_shift;
>
> + if(dwmac->f2h_ptp_ref_clk)
Improperly formatted, there must be a space between the 'if' and the
openning parenthesis of the condition.
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[PATCH] arm64: dts: mt8173: Add nor flash node
Add Mediatek nor flash node
Signed-off-by: Bayi Cheng
Acked-by: Brian Norris
---
Previous version of this patch is
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/386005.html
Drop flash node from mt8173.dtsi accroding review comment
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4dd5f93..af08e97 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -387,6 +387,17 @@
status = "disabled";
};
+ nor_flash: spi@1100d000 {
+ compatible = "mediatek,mt8173-nor";
+ reg = <0 0x1100d000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_SPI>,
+<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c3: i2c@1101 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x1101 0 0x70>,
--
1.8.1.1.dirty
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Re: [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
Le 05/12/2015 03:53, Kapil Hali a écrit : > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 5/5] ARM: BCM: Add SMP support for Broadcom 4708
Le 05/12/2015 03:53, Kapil Hali a écrit : > From: Jon Mason > > Add SMP support for Broadcom's 4708 SoCs. > > Signed-off-by: Jon Mason > Acked-by: Hauke Mehrtens > Tested-by: Hauke Mehrtens > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 4/5] ARM: BCM: Add SMP support for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add SMP support for Broadcom's Northstar Plus SoC > cpu enable method. This changes also consolidates > iProc family's - BCM NSP and BCM Kona, platform > SMP handling in a common file. > > Northstar Plus SoC is based on ARM Cortex-A9 > revision r3p0 which requires configuration for ARM > Errata 764369 for SMP. This change adds the needed > configuration option. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 3/5] ARM: dts: Add SMP support for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add device tree changes required for providing SMP support > for Broadcom Northstar Plus SoC. > > Signed-off-by: Kapil Hali Applied to devicetree/next; thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali Applied to devicetree/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
On 12/06/2015 06:33 PM, Rob Herring wrote: On Sun, Dec 6, 2015 at 8:21 PM, Guenter Roeck wrote: On 12/06/2015 03:54 PM, Benjamin Herrenschmidt wrote: On Sun, 2015-12-06 at 14:28 -0600, Rob Herring wrote: Do you plan to respin the OF parts at least soon? There's another problem Guenter found that of_fdt_unflatten_tree is not re-entrant due to "depth" being static and this series fixes that. So I'd rather apply this and avoid adding a mutex if possible. Gavin is on vacation until next year. That is a bit more than the timeline I am looking for. Rob, any chance to accept my patch for now ? After all, it can be reverted after the rework is complete, and it would be easier to apply to earlier kernels. Yes, will do. It's only 4.1 and later that it should be marked for stable? Yes, I think so. Earlier kernels would need a manual backport. Thanks, Guenter -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 3/7] doc: dt: mtd: partition: add on-flash format binding
On Fri, Dec 04, 2015 at 09:19:19PM -0800, Brian Norris wrote:
> The platform description (such as the type of partition formats used on
> a given flash) should be done independently of the flash driver in use.
> However, we can't reasonably have *all* partition parsers run on all
> flash (until they find a match), so let's overload the 'partitions'
> subnode to support specifying which format(s) to try in the device tree.
>
> Start by supporting Google's (Chrome OS) FMAP structure.
>
> There have been others interested in extending devicetree support to
> other parsers, like the bcm47xxpart parser:
>
> http://patchwork.ozlabs.org/patch/475986/
>
> and the AFS (ARM Flash Structure?) parser:
>
> http://patchwork.ozlabs.org/patch/537827/
>
> Signed-off-by: Brian Norris
Looks good to me. If you had lots of partitions, I'd agree with comments
that they should be separate files, but I doubt we'll have many 10s of
them. Plus all we really need here is a list of compatible strings.
Acked-by: Rob Herring
> ---
> .../devicetree/bindings/mtd/partition.txt | 75
> --
> 1 file changed, 69 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/partition.txt
> b/Documentation/devicetree/bindings/mtd/partition.txt
> index 28ae56f5c972..1bf9a7243993 100644
> --- a/Documentation/devicetree/bindings/mtd/partition.txt
> +++ b/Documentation/devicetree/bindings/mtd/partition.txt
> @@ -1,29 +1,56 @@
> -Representing flash partitions in devicetree
> +Flash partitions in device tree
> +===
>
> -Partitions can be represented by sub-nodes of an mtd device. This can be used
> +Flash devices can be partitioned into one or more functional ranges (e.g.,
> +"boot code", "nvram", and "kernel") in at least two distinct ways:
> +
> + (A) a fixed flash layout at production time or
> + (B) with an on-flash partition table, such as RedBoot, that describes the
> + geometry and naming/purpose of each functional region
> +
> +The former typically requires an operating system to learn about the
> +partitioning from some kind of metadata provided by the bootloader/firmware.
> +Such partitions can be described using the method in "Section A: Fixed
> Partitions".
> +
> +The latter is somewhat analogous to partition tables used on block devices
> +(e.g., MBR or GPT), except that there is less standardization for flash
> +devices, and it is not always safe or efficient to attempt to search for all
> of
> +them on every flash device in the system, particularly since many of them
> allow
> +their data structures to be placed anywhere on the flash, and so require
> +scanning the entire flash device to find them.
> +
> +To assist system software in locating these partition tables, we provide a
> +binding to describe which partition format(s) may be used on a given flash,
> +found below in "Section B: On-Flash Partition Tables".
> +
> +
> +Section A: Fixed Partitions
> +---
> +
> +Partitions can be represented by sub-nodes of a flash device. This can be
> used
> on platforms which have strong conventions about which portions of a flash
> are
> used for what purposes, but which don't use an on-flash partition table such
> as RedBoot.
>
> -The partition table should be a subnode of the mtd node and should be named
> +The partition table should be a subnode of the flash node and should be named
> 'partitions'. This node should have the following property:
> - compatible : (required) must be "partitions"
> Partitions are then defined in subnodes of the partitions node.
>
> -For backwards compatibility partitions as direct subnodes of the mtd device
> are
> +For backwards compatibility partitions as direct subnodes of the flash
> device are
> supported. This use is discouraged.
> NOTE: also for backwards compatibility, direct subnodes that have a
> compatible
> string are not considered partitions, as they may be used for other bindings.
>
> #address-cells & #size-cells must both be present in the partitions subnode
> of the
> -mtd device. There are two valid values for both:
> +flash device. There are two valid values for both:
> <1>: for partitions that require a single 32-bit cell to represent their
> size/address (aka the value is below 4 GiB)
> <2>: for partitions that require two 32-bit cells to represent their
> size/address (aka the value is 4 GiB or greater).
>
> Required properties:
> -- reg : The partition's offset and size within the mtd bank.
> +- reg : The partition's offset and size within the flash
>
> Optional properties:
> - label : The label / name for this partition. If omitted, the label is
> taken
> @@ -89,3 +116,39 @@ flash@2 {
> };
> };
> };
> +
> +
> +Section B: On-Flash Partition Tables
> +
> +
> +System designers use a variety of on-flash data structures to describe the
> +layout of the flash. Bec
Re: [RFC PATCH 3/7] doc: dt: mtd: partition: add on-flash format binding
On Sat, Dec 05, 2015 at 10:33:30PM +0100, Michal Suchanek wrote:
> On 5 December 2015 at 12:39, Jonas Gorski wrote:
> > On Sat, Dec 5, 2015 at 6:19 AM, Brian Norris
> > wrote:
>
> >> +
> >> +Examples:
> >> +
> >> +flash@0 {
> >> + partitions {
> >> + compatible = "google,fmap";
> >> + };
> >> +};
> >
> > I wonder if this wouldn't be better served in a separate binding doc
> > with its compatible name as the filename, like we do with
> > driver^Whardware blocks, especially if we want to add more parsers.
>
>
> I find that *very* counter productive for bindings that go to the same
> node. You have a description of a node, and then suddenly there you
> have another file with another description of the same node. Totally
> awesome.
I can't actually work out from that if you're agreeing with the
original post or the first reply.
> Also how do you plan to write partitioning schemes with parameters
> like with non-zero offset of the partition table.
Presumably with properties in the patitions node. Not seeing the
problem here.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [RFC PATCH 4/7] mtd: add of_match_mtd_parser() and of_mtd_match_mtd_parser() helpers
On Fri, Dec 4, 2015 at 11:19 PM, Brian Norris
wrote:
> Like the corresponding OF-based device/driver matching infrascture,
typo.
> let's begin to support a mtd/partition-parser matching infrastructure.
>
> Signed-off-by: Brian Norris
> ---
> drivers/of/of_mtd.c| 33 +
BTW, this file should be moved to drivers/mtd/ at some point.
> include/linux/mtd/partitions.h | 2 ++
> include/linux/of_mtd.h | 13 +
> 3 files changed, 48 insertions(+)
>
> diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
> index b7361ed70537..169d7500af5d 100644
> --- a/drivers/of/of_mtd.c
> +++ b/drivers/of/of_mtd.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> /**
> @@ -117,3 +118,35 @@ bool of_get_nand_on_flash_bbt(struct device_node *np)
> return of_property_read_bool(np, "nand-on-flash-bbt");
> }
> EXPORT_SYMBOL_GPL(of_get_nand_on_flash_bbt);
> +
> +static const struct of_device_id *of_match_mtd_parser(
This function name and the only caller's function name are very
similar. Why not just move this function inline.
> + struct mtd_part_parser *parser, struct device_node *np)
> +{
> + if (!parser || !np)
> + return NULL;
> +
> + return of_match_node(parser->of_match_table, np);
> +}
> +
> +static struct device_node *mtd_get_partitions_of_node(struct mtd_info
> *master)
> +{
> + struct device_node *np = mtd_get_of_node(master);
> +
> + if (!np)
> + return NULL;
> +
> + return of_get_child_by_name(np, "partitions");
> +}
> +
> +bool of_mtd_match_mtd_parser(struct mtd_info *mtd,
> +struct mtd_part_parser *parser)
> +{
> + struct device_node *np = mtd_get_partitions_of_node(mtd);
> + bool ret;
> +
> + ret = of_match_mtd_parser(parser, np) != NULL;
> + of_node_put(np);
> +
> + return ret;
> +}
--
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Re: [PATCH v2 PART-RESEND 0/2] berlin sdhci clock clean up
Dear Sebastian, On Sun, 6 Dec 2015 11:07:41 +0100 Sebastian Hesselbarth wrote: > On 19.11.2015 21:31, Sebastian Hesselbarth wrote: > > On 16.11.2015 11:56, Jisheng Zhang wrote: > >> Add or fix the optional clock property, then remove the CLK_IGNORE_UNUSED > >> flag for sdio clk(s). > >> > >> This is a partialy resend of > >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/379457.html > >> > >> patch3, patch4 has been merged. > > > > Great! Really! > > > > As they have been taken without my Acked-by, ignoring my request to > > _not_ remove the CLK_IGNORE_UNUSED flags _before_ these two, the > > remaining patches now become fixes. > > > > Please resend the patches with a proper description what and why they > > are fixes now. > > Is this going to be resolved anytime soon? > > If not, I am going to send a revert for the CLK_IGNORE_UNUSED patch > and we start this from the beginning. I will send patches today. Thanks a lot, Jisheng -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
On Sun, Dec 6, 2015 at 8:21 PM, Guenter Roeck wrote: > On 12/06/2015 03:54 PM, Benjamin Herrenschmidt wrote: >> >> On Sun, 2015-12-06 at 14:28 -0600, Rob Herring wrote: >>> >>> >>> Do you plan to respin the OF parts at least soon? There's another >>> problem Guenter found that of_fdt_unflatten_tree is not re-entrant due >>> to "depth" being static and this series fixes that. So I'd rather >>> apply this and avoid adding a mutex if possible. >> >> >> Gavin is on vacation until next year. >> > > That is a bit more than the timeline I am looking for. > > Rob, any chance to accept my patch for now ? After all, it can be > reverted after the rework is complete, and it would be easier > to apply to earlier kernels. Yes, will do. It's only 4.1 and later that it should be marked for stable? Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
On 12/06/2015 03:54 PM, Benjamin Herrenschmidt wrote: On Sun, 2015-12-06 at 14:28 -0600, Rob Herring wrote: Do you plan to respin the OF parts at least soon? There's another problem Guenter found that of_fdt_unflatten_tree is not re-entrant due to "depth" being static and this series fixes that. So I'd rather apply this and avoid adding a mutex if possible. Gavin is on vacation until next year. That is a bit more than the timeline I am looking for. Rob, any chance to accept my patch for now ? After all, it can be reverted after the rework is complete, and it would be easier to apply to earlier kernels. Thanks, Guenter -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/5] stmmac: Fix calculations for ptp counters when clock input = 50Mhz.
stmmac_config_sub_second_increment set the sub second increment to 20ns.
Driver is configured to use the fine adjustment method where the sub second
register is incremented when the acculumator incremented by the addend
register wraps overflows. This accumulator is update on every ptp clk
cycle. If a ptp clk with a period of greater than 20ns was used the
sub second register would not get updated correctly.
Instead set the sub sec increment to twice the period of the ptp clk.
This result in the addend register being set mid range and overflow
the accumlator every 2 clock cycles.
Signed-off-by: Phil Reid
---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 8 +---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 18 +++---
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
b/drivers/net/ethernet/stmicro/stmmac/common.h
index f4518bc..1e19c8f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -439,7 +439,7 @@ struct stmmac_ops {
/* PTP and HW Timer helpers */
struct stmmac_hwtimestamp {
void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
- void (*config_sub_second_increment) (void __iomem *ioaddr);
+ u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
int (*config_addend) (void __iomem *ioaddr, u32 addend);
int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
index 76ad214..83fa263 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
@@ -33,22 +33,24 @@ static void stmmac_config_hw_tstamping(void __iomem
*ioaddr, u32 data)
writel(data, ioaddr + PTP_TCR);
}
-static void stmmac_config_sub_second_increment(void __iomem *ioaddr)
+static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr, u32
ptp_clock)
{
u32 value = readl(ioaddr + PTP_TCR);
unsigned long data;
/* Convert the ptp_clock to nano second
-* formula = (1/ptp_clock) * 10
+* formula = (2/ptp_clock) * 10
* where, ptp_clock = 50MHz.
*/
- data = (10ULL / 5000);
+ data = (20ULL / ptp_clock);
/* 0.465ns accuracy */
if (!(value & PTP_TCR_TSCTRLSSR))
data = (data * 1000) / 465;
writel(data, ioaddr + PTP_SSIR);
+
+ return data;
}
static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3c6549a..ab8d916 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -53,6 +53,7 @@
#include "stmmac.h"
#include
#include
+#include "dwmac1000.h"
#define STMMAC_ALIGN(x)L1_CACHE_ALIGN(x)
@@ -185,7 +186,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
priv->clk_csr = STMMAC_CSR_100_150M;
else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
priv->clk_csr = STMMAC_CSR_150_250M;
- else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
+ else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
priv->clk_csr = STMMAC_CSR_250_300M;
}
}
@@ -435,6 +436,7 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev,
struct ifreq *ifr)
u32 ts_master_en = 0;
u32 ts_event_en = 0;
u32 value = 0;
+ u32 sec_inc;
if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
netdev_alert(priv->dev, "No support for HW time stamping\n");
@@ -598,24 +600,18 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev,
struct ifreq *ifr)
tstamp_all | ptp_v2 | ptp_over_ethernet |
ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
ts_master_en | snap_type_sel);
-
priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
/* program Sub Second Increment reg */
- priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
+ sec_inc =
priv->hw->ptp->config_sub_second_increment(priv->ioaddr, priv->clk_ptp_rate);
+ temp = div_u64(10ULL, sec_inc);
/* calculate default added value:
* formula is :
* addend = (2^32)/freq_div_ratio;
-* where, freq_div_ratio = clk_ptp_ref_i/50MHz
-* hence, addend = ((2^32) * 50
[PATCH v2 5/5] stmmac: socfpga: Provide dt node to config ptp clk source.
Signed-off-by: Phil Reid
---
Documentation/devicetree/bindings/net/socfpga-dwmac.txt | 2 ++
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
index 3a9d679..72d82d6 100644
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
@@ -11,6 +11,8 @@ Required properties:
designware version numbers documented in stmmac.txt
- altr,sysmgr-syscon : Should be the phandle to the system manager node that
encompasses the glue register, the register offset, and the register shift.
+ - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
+ for ptp ref clk. This affects all emacs as the clock is common.
Optional properties:
altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 401383b..3c5bc12 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -32,6 +32,7 @@
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x0003
+#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x0010
#define EMAC_SPLITTER_CTRL_REG 0x0
#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
@@ -47,6 +48,7 @@ struct socfpga_dwmac {
struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst;
void __iomem *splitter_base;
+ bool f2h_ptp_ref_clk;
};
static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
@@ -116,6 +118,8 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac
*dwmac, struct device *
return -EINVAL;
}
+ dwmac->f2h_ptp_ref_clk = of_property_read_bool(np,
"altr,f2h_ptp_ref_clk");
+
np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
if (np_splitter) {
if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
@@ -171,6 +175,11 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
+ if(dwmac->f2h_ptp_ref_clk)
+ ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
+ else
+ ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift /
2));
+
regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
return 0;
}
--
1.8.3.1
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[PATCH v2 1/5] stmmac: create of compatible mdio bus for stmacc driver
The DSA driver needs to be passed a reference to an mdio bus. Typically
the mac is configured to use a fixed link but the mdio bus still needs
to be registered so that it con configure the switch.
This patch follows the same process as the altera tse ethernet driver for
creation of the mdio bus.
Acked-by: Rob Herring
Signed-off-by: Phil Reid
---
Documentation/devicetree/bindings/net/stmmac.txt | 10 ++-
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 32 --
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +-
3 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
b/Documentation/devicetree/bindings/net/stmmac.txt
index f34fc3c..cb6288e 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -47,7 +47,8 @@ Optional properties:
- snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register.
- tx-fifo-depth: See ethernet.txt file in the same directory
- rx-fifo-depth: See ethernet.txt file in the same directory
-
+- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.
+
Examples:
gmac0: ethernet@e080 {
@@ -65,4 +66,11 @@ Examples:
tx-fifo-depth = <16384>;
clocks = <&clock>;
clock-names = "stmmaceth";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@0 {
+ };
+ };
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index bba670c..1d972e3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -29,7 +29,7 @@
#include
#include
#include
-
+#include
#include
#include "stmmac.h"
@@ -201,6 +201,25 @@ int stmmac_mdio_register(struct net_device *ndev)
struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
int addr, found;
+#ifdef CONFIG_OF
+ struct device_node *mdio_node = NULL;
+ struct device_node *child_node = NULL;
+
+ for_each_child_of_node(priv->device->of_node, child_node) {
+ if (of_device_is_compatible(child_node, "snps,dwmac-mdio")) {
+ mdio_node = child_node;
+ break;
+ }
+ }
+
+ if (mdio_node) {
+ netdev_dbg(ndev, "FOUND MDIO subnode\n");
+ } else {
+ netdev_err(ndev, "NO MDIO subnode\n");
+ return 0;
+ }
+#endif
+
if (!mdio_bus_data)
return 0;
@@ -231,7 +250,11 @@ int stmmac_mdio_register(struct net_device *ndev)
new_bus->irq = irqlist;
new_bus->phy_mask = mdio_bus_data->phy_mask;
new_bus->parent = priv->device;
+#ifdef CONFIG_OF
+ err = of_mdiobus_register(new_bus, mdio_node);
+#else
err = mdiobus_register(new_bus);
+#endif
if (err != 0) {
pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
goto bus_register_fail;
@@ -284,13 +307,6 @@ int stmmac_mdio_register(struct net_device *ndev)
}
}
- if (!found) {
- pr_warn("%s: No PHY found\n", ndev->name);
- mdiobus_unregister(new_bus);
- mdiobus_free(new_bus);
- return -ENODEV;
- }
-
priv->mii = new_bus;
return 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index d02691b..6863420 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -146,7 +146,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const
char **mac)
if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0)
dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n");
- if (plat->phy_node || plat->phy_bus_name)
+ if (plat->phy_bus_name)
plat->mdio_bus_data = NULL;
else
plat->mdio_bus_data =
--
1.8.3.1
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[PATCH 1/1] stmmac: socfpga: Provide dt node to config ptp clk source.
Signed-off-by: Phil Reid
---
Documentation/devicetree/bindings/net/socfpga-dwmac.txt | 2 ++
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
index 3a9d679..72d82d6 100644
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
@@ -11,6 +11,8 @@ Required properties:
designware version numbers documented in stmmac.txt
- altr,sysmgr-syscon : Should be the phandle to the system manager node that
encompasses the glue register, the register offset, and the register shift.
+ - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
+ for ptp ref clk. This affects all emacs as the clock is common.
Optional properties:
altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 401383b..c1bab62 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -32,6 +32,7 @@
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x0003
+#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x0010
#define EMAC_SPLITTER_CTRL_REG 0x0
#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
@@ -47,6 +48,7 @@ struct socfpga_dwmac {
struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst;
void __iomem *splitter_base;
+ bool f2h_ptp_ref_clk;
};
static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
@@ -116,6 +118,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac
*dwmac, struct device *
return -EINVAL;
}
+ dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "f2h_ptp_ref_clk");
+
+
np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
if (np_splitter) {
if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
@@ -171,6 +176,11 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
+ if(dwmac->f2h_ptp_ref_clk)
+ ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
+ else
+ ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift /
2));
+
regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
return 0;
}
--
1.8.3.1
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[PATCH v2 2/5] stmmac: Correct documentation on stmmac clocks.
devm_get_clk looks in clock-name property for matching clock. the ptp_ref_clk property is ignored. Acked-by: Rob Herring Signed-off-by: Phil Reid --- Documentation/devicetree/bindings/net/stmmac.txt | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index cb6288e..90af2e0 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@ -35,15 +35,14 @@ Optional properties: - reset-names: Should contain the reset signal name "stmmaceth", if a reset phandle is given - max-frame-size: See ethernet.txt file in the same directory -- clocks: If present, the first clock should be the GMAC main clock and - the second clock should be peripheral's register interface clock. Further - clocks may be specified in derived bindings. -- clock-names: One name for each entry in the clocks property, the - first one should be "stmmaceth" and the second one should be "pclk". -- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is - available this clock is used for programming the Timestamp Addend Register. - If not passed then the system clock will be used and this is fine on some - platforms. +- clocks: If present, the first clock should be the GMAC main clock + The optional second clock should be peripheral's register interface clock. + The third optional clock should be the ptp reference clock. + Further clocks may be specified in derived bindings. +- clock-names: One name for each entry in the clocks property. + The first one should be "stmmaceth". + The optional second one should be "pclk". + The optional third one should be "clk_ptp_ref". - snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register. - tx-fifo-depth: See ethernet.txt file in the same directory - rx-fifo-depth: See ethernet.txt file in the same directory -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/5] stmmac: Add ptp debugfs entry.
This adds a debugfs entry to view the current status of the ptp
registers.
Signed-off-by: Phil Reid
---
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 61 +++
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 5 ++
3 files changed, 67 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index 1f3b33a..d0ac1b1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -130,6 +130,7 @@ struct stmmac_priv {
struct dentry *dbgfs_dir;
struct dentry *dbgfs_rings_status;
struct dentry *dbgfs_dma_cap;
+ struct dentry *dbgfs_ptp;
#endif
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index ab8d916..f75b2f9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2657,6 +2657,57 @@ static const struct file_operations stmmac_dma_cap_fops
= {
.release = single_release,
};
+static int stmmac_sysfs_ptp_read(struct seq_file *seq, void *v)
+{
+ struct net_device *dev = seq->private;
+ struct stmmac_priv *priv = netdev_priv(dev);
+
+ if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
+ seq_printf(seq, "PTP HW features not supported\n");
+ return 0;
+ }
+
+ seq_printf(seq, "==\n");
+ seq_printf(seq, "\tPTP Status\n");
+ seq_printf(seq, "==\n");
+
+ #define DUMP_REG(x) seq_printf(seq, "%-20s %04x %08x\n", #x, x,
readl(priv->ioaddr + x));
+ DUMP_REG(GMAC_INT_STATUS);
+ DUMP_REG(GMAC_INT_MASK);
+
+ DUMP_REG(PTP_TCR);
+ DUMP_REG(PTP_SSIR);
+ DUMP_REG(PTP_STSR);
+ DUMP_REG(PTP_STNSR);
+ DUMP_REG(PTP_STSUR);
+ DUMP_REG(PTP_STNSUR);
+ DUMP_REG(PTP_TAR);
+ DUMP_REG(PTP_TTSR);
+ DUMP_REG(PTP_TTNSR);
+ DUMP_REG(PTP_STHWSR);
+ DUMP_REG(PTP_TSR);
+ DUMP_REG(PTP_PPSCTLR);
+ DUMP_REG(PTP_AUXTSTNSR);
+ DUMP_REG(PTP_AUXTSTSR);
+ DUMP_REG(PTP_PPS0INTRR);
+ DUMP_REG(PTP_PPS0WDTHR);
+
+ return 0;
+}
+
+static int stmmac_sysfs_ptp_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, stmmac_sysfs_ptp_read, inode->i_private);
+}
+
+static const struct file_operations stmmac_ptp_fops = {
+ .owner = THIS_MODULE,
+ .open = stmmac_sysfs_ptp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int stmmac_init_fs(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
@@ -2692,6 +2743,16 @@ static int stmmac_init_fs(struct net_device *dev)
if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
pr_info("ERROR creating stmmac MMC debugfs file\n");
debugfs_remove_recursive(priv->dbgfs_dir);
+ }
+
+ /* Entry to report the PTP status */
+ priv->dbgfs_ptp = debugfs_create_file("ptp", S_IRUGO,
+ priv->dbgfs_dir,
+ dev, &stmmac_ptp_fops);
+
+ if (!priv->dbgfs_ptp || IS_ERR(priv->dbgfs_ptp)) {
+ pr_info("ERROR creating stmmac PTP debugfs file\n");
+ debugfs_remove_recursive(priv->dbgfs_dir);
return -ENOMEM;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
index 4535df3..b00b005 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
@@ -37,6 +37,11 @@
#define PTP_TTNSR 0x0720 /* Target Time Nanoseconds Reg */
#definePTP_STHWSR 0x0724 /* System Time - Higher Word Seconds
Reg */
#define PTP_TSR0x0728 /* Timestamp Status */
+#define PTP_PPSCTLR0x072C /* PPS Control Reg */
+#define PTP_AUXTSTNSR 0x0730 /* Aux Timestamp - Nanoseconds Reg */
+#define PTP_AUXTSTSR 0x0734 /* Aux Timestamp - Seconds Reg */
+#define PTP_PPS0INTRR 0x0760 /* PPS0 Interval Reg */
+#define PTP_PPS0WDTHR 0x0764 /* PPS0 Width Reg */
#define PTP_STNSUR_ADDSUB_SHIFT 31
--
1.8.3.1
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[PATCH v2 0/5] stmmac: Fixed Phy & PTP fixes
Provide ability to specify a fixed phy in the device tree and retain the mdio bus if no phy is found. This is needed where a dsa is connected via a fixed phy and uses the mdio bus for config. Fixed ptp ref clock calculatins for the stmmac when ptp ref clock is running at <= 50Mhz. Also add device tree setting to config ptp clk source on socfpga platforms. Changes from V1: - Fixed mismatch doc / code for ptp_ref_clk dt node. - Remove unit address from doc example. Phil Reid (5): stmmac: create of compatible mdio bus for stmacc driver stmmac: Correct documentation on stmmac clocks. stmmac: Fix calculations for ptp counters when clock input = 50Mhz. stmmac: Add ptp debugfs entry. stmmac: socfpga: Provide dt node to config ptp clk source. .../devicetree/bindings/net/socfpga-dwmac.txt | 2 + Documentation/devicetree/bindings/net/stmmac.txt | 27 +--- drivers/net/ethernet/stmicro/stmmac/common.h | 2 +- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c| 9 +++ drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + .../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 8 ++- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 79 +++--- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 32 ++--- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 5 ++ 10 files changed, 133 insertions(+), 34 deletions(-) -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio
On 2015/12/6 6:15, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:57 yankejian wrote:
>> #size-cells = <0>;
>> compatible = "hisilicon,hns-mdio";
>> - reg = <0x0 0x803c 0x0 0x1
>> - 0x0 0x8000 0x0 0x1>;
>> + reg = <0x0 0x803c 0x0 0x1>;
>> + subctrl_vbase = <&peri_c_subctrl>;
>>
>> soc0_phy0: ethernet-phy@0 {
>> reg = <0x0>;
> I don't see the subctrl_vbase property documented in the binding. Please
> modify the binding as well.
>
> Also, please use the normal naming conventions using '-' instead of '_'
> inside of property names.
>
> Arnd
>
> .
Hi, Arnd
Thanks for your suggestions. i will fixes it later.
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Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board
On 2015/12/6 6:13, Arnd Bergmann wrote:
> On Saturday 05 December 2015 15:56:58 yankejian wrote:
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> + /* for HiP05 PCIe-SAS system */
>> + pcie_sas: system_controller@0xb000 {
>> + compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> + reg = <0xb000 0x1>;
>> + };
>>
> The compatible string in the example does not match the required properties.
>
> Arnd
>
> .
Hi, Arnd
Thanks for your suggestions. i will fixes it later.
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Re: [PATCH] extcon: arizona: Update naming for micd-timeout DT to include units
Hi Pavel, On 2015년 12월 05일 06:00, Pavel Machek wrote: > On Mon 2015-11-23 14:51:30, Charles Keepax wrote: >> Add time units of -ms (milliseconds) to wlf,micd-timeout. >> >> Signed-off-by: Charles Keepax >> --- >> .../devicetree/bindings/extcon/extcon-arizona.txt |2 +- >> drivers/extcon/extcon-arizona.c|2 +- >> 2 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/extcon/extcon-arizona.txt >> b/Documentation/devicetree/bindings/extcon/extcon-arizona.txt >> index da9813b..05d85ac 100644 >> --- a/Documentation/devicetree/bindings/extcon/extcon-arizona.txt >> +++ b/Documentation/devicetree/bindings/extcon/extcon-arizona.txt >> @@ -33,7 +33,7 @@ Optional properties: >> specified as per the ARIZONA_MICD_TIME_XXX defines. >>- wlf,micd-dbtime : Microphone detection hardware debounces specified as >> the >> number of measurements to take, valid values being 2 and 4. >> - - wlf,micd-timeout : Timeout for microphone detection, specified in >> + - wlf,micd-timeout-ms : Timeout for microphone detection, specified in >> milliseconds. >>- wlf,micd-force-micbias : Force MICBIAS continuously on during microphone >> detection. >> diff --git a/drivers/extcon/extcon-arizona.c >> b/drivers/extcon/extcon-arizona.c >> index c377030..8647533 100644 >> --- a/drivers/extcon/extcon-arizona.c >> +++ b/drivers/extcon/extcon-arizona.c >> @@ -1230,7 +1230,7 @@ static int arizona_extcon_device_get_pdata(struct >> arizona *arizona) >> device_property_read_u32(arizona->dev, "wlf,micd-dbtime", >> &pdata->micd_dbtime); >> >> -device_property_read_u32(arizona->dev, "wlf,micd-timeout", >> +device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms", >> &pdata->micd_timeout); >> >> pdata->micd_force_micbias = > device_property_read_bool(arizona->dev, > > While the change is nice, new kernel is supposed to work with old > DTS. So you'd need to check for both properties here.. This is new DT option. There are no dtbs usingt this property in latest kernel. So, ther is no issue. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] dt-bindings: regulator/mfd: Reorganize S2MPA01 bindings
On 04.12.2015 21:11, Mark Brown wrote: > On Fri, Dec 04, 2015 at 10:10:05AM +0900, Krzysztof Kozlowski wrote: >> The mfd/s2mpa01.txt duplicates some of the information about bindings >> with old mfd/s2mps11.txt. Now common part exists entirely in >> mfd/samsung,sec-core.txt so: > > Acked-by: Mark Brown > >> - add company prefix to file name (regulator/samsung,s2mpa01.txt), > > I'm not 100% convinced about these prefixes BTW, the duplication isn't > usually an issue within a subsystem. They don't do any harm either > though. > I am not convinced neither... Some of newer documents use prefixes so I had an impression that this is a more organized way. If there are objections I can drop it. Thanks for ack! Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] dt-bindings: regulator/mfd: Reorganize S2MPA01 bindings
On 05.12.2015 00:55, Rob Herring wrote: > On Fri, Dec 04, 2015 at 10:10:05AM +0900, Krzysztof Kozlowski wrote: >> The mfd/s2mpa01.txt duplicates some of the information about bindings >> with old mfd/s2mps11.txt. Now common part exists entirely in >> mfd/samsung,sec-core.txt so: >> - add company prefix to file name (regulator/samsung,s2mpa01.txt), >> - remove duplicated information, >> - reorganize the contents to match style of >>regulator/samsung,s2mps11.txt. >> >> Signed-off-by: Krzysztof Kozlowski > > Next time, use git format-patch -M option. > > Acked-by: Rob Herring > It is already used but I also changed the style and formatting to the similarity dropped below default level of 50%. I could of course first rename and then change formatting/contents but that would be a little bit too much for this simple patchset, don't you think? Anyway thanks for acks! Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
On Sun, 2015-12-06 at 14:28 -0600, Rob Herring wrote:
>
> Do you plan to respin the OF parts at least soon? There's another
> problem Guenter found that of_fdt_unflatten_tree is not re-entrant due
> to "depth" being static and this series fixes that. So I'd rather
> apply this and avoid adding a mutex if possible.
Gavin is on vacation until next year.
Cheers,
Ben.
> Rob
>
> >
> > Signed-off-by: Gavin Shan
> > ---
> > drivers/of/fdt.c | 94
> > +---
> > 1 file changed, 56 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > index 173b036..f4793d0 100644
> > --- a/drivers/of/fdt.c
> > +++ b/drivers/of/fdt.c
> > @@ -355,61 +355,82 @@ static unsigned long populate_node(const void *blob,
> > return fpsize;
> > }
> >
> > +static void reverse_nodes(struct device_node *parent)
> > +{
> > + struct device_node *child, *next;
> > +
> > + /* In-depth first */
> > + child = parent->child;
> > + while (child) {
> > + reverse_nodes(child);
> > +
> > + child = child->sibling;
> > + }
> > +
> > + /* Reverse the nodes in the child list */
> > + child = parent->child;
> > + parent->child = NULL;
> > + while (child) {
> > + next = child->sibling;
> > +
> > + child->sibling = parent->child;
> > + parent->child = child;
> > + child = next;
> > + }
> > +}
> > +
> > /**
> > * unflatten_dt_node - Alloc and populate a device_node from the flat tree
> > * @blob: The parent device tree blob
> > * @mem: Memory chunk to use for allocating device nodes and properties
> > - * @poffset: pointer to node in flat tree
> > * @dad: Parent struct device_node
> > * @nodepp: The device_node tree created by the call
> > - * @fpsize: Size of the node path up at the current depth.
> > * @dryrun: If true, do not allocate device nodes but still calculate
> > needed
> > * memory size
> > */
> > static void *unflatten_dt_node(const void *blob,
> > void *mem,
> > - int *poffset,
> > struct device_node *dad,
> > struct device_node **nodepp,
> > - unsigned long fpsize,
> > bool dryrun)
> > {
> > - struct device_node *np;
> > - static int depth;
> > - int old_depth;
> > -
> > - fpsize = populate_node(blob, *poffset, &mem, dad, fpsize, &np,
> > dryrun);
> > - if (!fpsize)
> > - return mem;
> > + struct device_node *root;
> > + int offset = 0, depth = 0;
> > + unsigned long fpsizes[64];
> > + struct device_node *nps[64];
> >
> > - old_depth = depth;
> > - *poffset = fdt_next_node(blob, *poffset, &depth);
> > - if (depth < 0)
> > - depth = 0;
> > - while (*poffset > 0 && depth > old_depth)
> > - mem = unflatten_dt_node(blob, mem, poffset, np, NULL,
> > - fpsize, dryrun);
> > + if (nodepp)
> > + *nodepp = NULL;
> > +
> > + root = dad;
> > + fpsizes[depth] = dad ? strlen(of_node_full_name(dad)) : 0;
> > + nps[depth++] = dad;
> > + while (offset >= 0 && depth < 64) {
> > + fpsizes[depth] = populate_node(blob, offset, &mem,
> > + nps[depth - 1],
> > + fpsizes[depth - 1],
> > + &nps[depth], dryrun);
> > + if (!fpsizes[depth])
> > + return mem;
> > +
> > + if (!dryrun && nodepp && !*nodepp)
> > + *nodepp = nps[depth];
> > + if (!dryrun && !root)
> > + root = nps[depth];
> > +
> > + offset = fdt_next_node(blob, offset, &depth);
> > + }
> >
> > - if (*poffset < 0 && *poffset != -FDT_ERR_NOTFOUND)
> > - pr_err("unflatten: error %d processing FDT\n", *poffset);
> > + if (offset < 0 && offset != -FDT_ERR_NOTFOUND)
> > + pr_err("%s: Error %d processing FDT\n",
> > + __func__, offset);
> >
> > /*
> > * Reverse the child list. Some drivers assumes node order matches
> > .dts
> > * node order
> > */
> > - if (!dryrun && np->child) {
> > - struct device_node *child = np->child;
> > - np->child = NULL;
> > - while (child) {
> > - struct device_node *next = child->sibling;
> > - child->sibling = np->child;
> > - np->child = child;
> > - child = next;
> > - }
> > - }
> > -
> > - if (nodepp)
> > -
[PATCH v2 1/3] dt-bindings: add Marvell PMU documentation
Add the required DT binding documentation for the Marvell PMU driver.
Acked-by: Rob Herring
Signed-off-by: Russell King
---
Who takes these patches? This never got merged when the PMU driver
itself was merged.
Documentation/devicetree/bindings/soc/dove/pmu.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt
diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt
b/Documentation/devicetree/bindings/soc/dove/pmu.txt
new file mode 100644
index ..edd40b796b74
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
@@ -0,0 +1,56 @@
+Device Tree bindings for Marvell PMU
+
+Required properties:
+ - compatible: value should be "marvell,dove-pmu".
+May also include "simple-bus" if there are child devices, in which
+case the ranges node is required.
+ - reg: two base addresses and sizes of the PM controller and PMU.
+ - interrupts: single interrupt number for the PMU interrupt
+ - interrupt-controller: must be specified as the PMU itself is an
+interrupt controller.
+ - #interrupt-cells: must be 1.
+ - #reset-cells: must be 1.
+ - domains: sub-node containing domain descriptions
+
+Optional properties:
+ - ranges: defines the address mapping for child devices, as per the
+ standard property of this name. Required when compatible includes
+ "simple-bus".
+
+Power domain descriptions are listed as child nodes of the "domains"
+sub-node. Each domain has the following properties:
+
+Required properties:
+ - #power-domain-cells: must be 0.
+
+Optional properties:
+ - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
+ - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
+ - resets: points to the reset manager (PMU node) and reset index.
+
+Example:
+
+ pmu: power-management@d {
+ compatible = "marvell,dove-pmu";
+ reg = <0xd 0x8000>, <0xd8000 0x8000>;
+ interrupts = <33>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #reset-cells = <1>;
+
+ domains {
+ vpu_domain: vpu-domain {
+ #power-domain-cells = <0>;
+ marvell,pmu_pwr_mask = <0x0008>;
+ marvell,pmu_iso_mask = <0x0001>;
+ resets = <&pmu 16>;
+ };
+
+ gpu_domain: gpu-domain {
+ #power-domain-cells = <0>;
+ marvell,pmu_pwr_mask = <0x0004>;
+ marvell,pmu_iso_mask = <0x0002>;
+ resets = <&pmu 18>;
+ };
+ };
+ };
--
2.1.0
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Re: [PATCH] of: Fix comparison of reserved memory regions
On Sun, 2015-12-06 at 14:31 -0600, Rob Herring wrote:
> On Sat, Dec 5, 2015 at 5:43 AM, Michael Ellerman
> wrote:
> > On 5 December 2015 04:07:39 GMT+11:00, Mitchel Humpherys
> > wrote:
> > > On Wed, Nov 18 2015 at 09:46:38 PM, Michael Ellerman
> > > wrote:
> > > > Fix it by just doing the standard double if and return 0 logic.
> > > >
> > > > Fixes: ae1add247bf8 ("of: Check for overlap in reserved memory
> > > regions")
> > >
> > > Woops, thanks.
> > >
> > > Tested-by: Mitchel Humpherys
> >
> > Thanks for testing.
> >
> > Rob, can we get this merged for 4.4 please?
>
> Yes. I meant to last week, but was waiting on getting another issue
> sorted out. I should get it to Linus in the next couple of days.
Sure thing. No great rush but would be nice for it to be fixed before 4.4
releases.
cheers
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[PATCH v2 3/3] ARM: dts: dove: add Dove divider clocks
Add the Dove divider clocks to the Dove dtsi file.
Acked-by: Andrew Lunn
Signed-off-by: Russell King
---
arch/arm/boot/dts/dove.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 179121630ad7..ea36a262d056 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -459,6 +459,12 @@
#clock-cells = <1>;
};
+ divider_clk: core-clock@0064 {
+ compatible =
"marvell,dove-divider-clock";
+ reg = <0x0064 0x8>;
+ #clock-cells = <1>;
+ };
+
pinctrl: pin-ctrl@0200 {
compatible = "marvell,dove-pinctrl";
reg = <0x0200 0x14>,
--
2.1.0
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[PATCH v2 1/3] dt-bindings: add Marvell core PLL and clock divider PMU documentation
Add documentation for the Marvell clock divider driver, which is used
to source clocks for the AXI bus, video decoder, GPU and LCD blocks.
Acked-by: Andrew Lunn
Acked-by: Sebastian Hesselbarth
Acked-by: Rob Herring
Signed-off-by: Russell King
---
.../bindings/clock/dove-divider-clock.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/dove-divider-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
new file mode 100644
index ..e3eb0f657c5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
@@ -0,0 +1,28 @@
+PLL divider based Dove clocks
+
+Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
+high speed clocks for a number of peripherals. These dividers are part of
+the PMU, and thus this node should be a child of the PMU node.
+
+The following clocks are provided:
+
+ID Clock
+-
+0 AXI bus clock
+1 GPU clock
+2 VMeta clock
+3 LCD clock
+
+Required properties:
+- compatible : shall be "marvell,dove-divider-clock"
+- reg : shall be the register address of the Core PLL and Clock Divider
+ Control 0 register. This will cover that register, as well as the
+ Core PLL and Clock Divider Control 1 register. Thus, it will have
+ a size of 8.
+- #clock-cells : from common clock binding; shall be set to 1
+
+divider_clk: core-clock@0064 {
+ compatible = "marvell,dove-divider-clock";
+ reg = <0x0064 0x8>;
+ #clock-cells = <1>;
+};
--
2.1.0
--
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[PATCH v2] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file
Add support for the SolidRun Armada 388 Clearfog A1 board. This board
has an Armada 388 microsom, dedicated gigabit ethernet, six switched
gigabit ethernet ports, SFP cage, two Mini-PCIe/mSATA slots, a m.2 SATA
slot, and a MikroBUS connector to allow MikroBUS modules to be added.
This DT file adds support for all board facilities with the exception
of full SFP support.
Signed-off-by: Russell King
---
v2, without the mac-address properties.
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-388-clearfog.dts | 456 +
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 115 ++
3 files changed, 572 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dts
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc3746130..7e6a0532c656 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
+ armada-388-clearfog.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-rd.dtb
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts
b/arch/arm/boot/dts/armada-388-clearfog.dts
new file mode 100644
index ..c6e180eb3b11
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -0,0 +1,456 @@
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
+
+/ {
+ model = "SolidRun Clearfog A1";
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ soc {
+ internal-regs {
+ ethernet@3 {
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+
Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
On 12/06/2015 12:28 PM, Rob Herring wrote: +Guenter On Wed, Nov 4, 2015 at 7:12 AM, Gavin Shan wrote: In current implementation, unflatten_dt_node() is called recursively to unflatten device nodes in FDT blob. It's stress to limited stack capacity. This avoids calling the function recursively, meaning the device nodes are unflattened in one call on unflatten_dt_node(): two arrays are introduced to track the parent path size and the device node of current level of depth, which will be used by the device node on next level of depth to be unflattened. Also, the parameter "poffset" and "fpsize" are unused and dropped. Do you plan to respin the OF parts at least soon? There's another problem Guenter found that of_fdt_unflatten_tree is not re-entrant due to "depth" being static and this series fixes that. So I'd rather apply this and avoid adding a mutex if possible. Hi Rob, We see this problem in 4.1, so whatever patch you accept should be back-ported to at least that release. Any idea when this patch will be accepted ? We actively see the problem in our kernel, so I'll need a solution soon. Otherwise I'll have to apply my patch to our kernel and revert it as soon as the 'real' patch has been back-ported. Thanks, Guenter -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] of/irq: optimize device node matching loop in of_irq_init()
On Tue, Nov 24, 2015 at 7:10 AM, Masahiro Yamada
wrote:
> Currently, of_irq_init() iterates over interrupt controller nodes
> with for_each_matching_node(), and then gets each init function with
> of_match_node() later.
>
> This routine can be optimized with for_each_matching_node_and_match().
> It allows to get the interrupt controller node and its init function
> at the same time, saving __of_match_node() callings.
>
> Signed-off-by: Masahiro Yamada
Applied, thanks.
Rob
> ---
>
> drivers/of/irq.c | 27 +--
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/of/irq.c b/drivers/of/irq.c
> index 902b89b..4c0da87 100644
> --- a/drivers/of/irq.c
> +++ b/drivers/of/irq.c
> @@ -472,6 +472,7 @@ EXPORT_SYMBOL_GPL(of_irq_to_resource_table);
>
> struct of_intc_desc {
> struct list_headlist;
> + of_irq_init_cb_tirq_init_cb;
> struct device_node *dev;
> struct device_node *interrupt_parent;
> };
> @@ -485,6 +486,7 @@ struct of_intc_desc {
> */
> void __init of_irq_init(const struct of_device_id *matches)
> {
> + const struct of_device_id *match;
> struct device_node *np, *parent = NULL;
> struct of_intc_desc *desc, *temp_desc;
> struct list_head intc_desc_list, intc_parent_list;
> @@ -492,10 +494,15 @@ void __init of_irq_init(const struct of_device_id
> *matches)
> INIT_LIST_HEAD(&intc_desc_list);
> INIT_LIST_HEAD(&intc_parent_list);
>
> - for_each_matching_node(np, matches) {
> + for_each_matching_node_and_match(np, matches, &match) {
> if (!of_find_property(np, "interrupt-controller", NULL) ||
> !of_device_is_available(np))
> continue;
> +
> + if (WARN(!match->data, "of_irq_init: no init function for
> %s\n",
> +match->compatible))
> + continue;
> +
> /*
> * Here, we allocate and populate an of_intc_desc with the
> node
> * pointer, interrupt-parent device_node etc.
> @@ -506,6 +513,7 @@ void __init of_irq_init(const struct of_device_id
> *matches)
> goto err;
> }
>
> + desc->irq_init_cb = match->data;
> desc->dev = of_node_get(np);
> desc->interrupt_parent = of_irq_find_parent(np);
> if (desc->interrupt_parent == np)
> @@ -525,27 +533,18 @@ void __init of_irq_init(const struct of_device_id
> *matches)
> * The assumption is that NULL parent means a root controller.
> */
> list_for_each_entry_safe(desc, temp_desc, &intc_desc_list,
> list) {
> - const struct of_device_id *match;
> int ret;
> - of_irq_init_cb_t irq_init_cb;
>
> if (desc->interrupt_parent != parent)
> continue;
>
> list_del(&desc->list);
> - match = of_match_node(matches, desc->dev);
> - if (WARN(!match->data,
> - "of_irq_init: no init function for %s\n",
> - match->compatible)) {
> - kfree(desc);
> - continue;
> - }
>
> - pr_debug("of_irq_init: init %s @ %p, parent %p\n",
> -match->compatible,
> + pr_debug("of_irq_init: init %s (%p), parent %p\n",
> +desc->dev->full_name,
> desc->dev, desc->interrupt_parent);
> - irq_init_cb = (of_irq_init_cb_t)match->data;
> - ret = irq_init_cb(desc->dev, desc->interrupt_parent);
> + ret = desc->irq_init_cb(desc->dev,
> + desc->interrupt_parent);
> if (ret) {
> kfree(desc);
> continue;
> --
> 1.9.1
>
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Re: [PATCH] of/address: fix typo in comment block of of_translate_one()
On Mon, Nov 30, 2015 at 12:22 AM, Masahiro Yamada wrote: > Remove the "not" before "cannot". > > I am fixing the comment block style while I am here. > > Signed-off-by: Masahiro Yamada Applied for 4.4. Thanks. Rob > --- > > drivers/of/address.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/of/address.c b/drivers/of/address.c > index 5289c80..91a469d 100644 > --- a/drivers/of/address.c > +++ b/drivers/of/address.c > @@ -485,9 +485,10 @@ static int of_translate_one(struct device_node *parent, > struct of_bus *bus, > int rone; > u64 offset = OF_BAD_ADDR; > > - /* Normally, an absence of a "ranges" property means we are > + /* > +* Normally, an absence of a "ranges" property means we are > * crossing a non-translatable boundary, and thus the addresses > -* below the current not cannot be converted to CPU physical ones. > +* below the current cannot be converted to CPU physical ones. > * Unfortunately, while this is very clear in the spec, it's not > * what Apple understood, and they do have things like /uni-n or > * /ht nodes with no "ranges" property and a lot of perfectly > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] of/address: replace printk(KERN_ERR ...) with pr_err(...)
On Mon, Nov 30, 2015 at 12:14 AM, Masahiro Yamada
wrote:
> A trivial change suggested by checkpatch.pl.
You might as well all levels while you are at it. Looks like that is
only one more:
drivers/of/address.c: printk(KERN_DEBUG "%s", s);
Rob
>
> Signed-off-by: Masahiro Yamada
> ---
>
> drivers/of/address.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index cd53fe4..5289c80 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -596,7 +596,7 @@ static u64 __of_translate_address(struct device_node *dev,
> pbus = of_match_bus(parent);
> pbus->count_cells(dev, &pna, &pns);
> if (!OF_CHECK_COUNTS(pna, pns)) {
> - printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
> + pr_err("prom_parse: Bad cell count for %s\n",
>of_node_full_name(dev));
> break;
> }
> --
> 1.9.1
>
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Re: [PATCH] of: Fix comparison of reserved memory regions
On Sat, Dec 5, 2015 at 5:43 AM, Michael Ellerman wrote:
>
>
> On 5 December 2015 04:07:39 GMT+11:00, Mitchel Humpherys
> wrote:
>>On Wed, Nov 18 2015 at 09:46:38 PM, Michael Ellerman
>> wrote:
>>> In order to check for overlapping reserved memory regions, we first
>>need
>>> to sort the array of memory regions. This is implemented using
>>sort(),
>>> and a custom comparison function __rmem_cmp().
>>>
>>> Unfortunatley __rmem_cmp() doesn't work in all cases. Because the two
>>> base values are phys_addr_t, they may be u64 on some platforms, in
>>which
>>> case subtracting one from the other and then (implicitly) casting to
>>int
>>> does not give us the -ve/0/+ve value we need.
>>>
>>> This leads to incorrect reports about overlaps, eg:
>>>
>>> ibm,slw-image@1ffe60 (0x001ffe60--0x001ffe70)
>>overlaps with
>>> ibm,firmware-allocs-memory@10
>>(0x0010--0x001000dc0200)
>>>
>>> Fix it by just doing the standard double if and return 0 logic.
>>>
>>> Fixes: ae1add247bf8 ("of: Check for overlap in reserved memory
>>regions")
>>> Signed-off-by: Michael Ellerman
>>> ---
>>> drivers/of/of_reserved_mem.c | 8 +++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>>Woops, thanks.
>>
>>Tested-by: Mitchel Humpherys
>
> Thanks for testing.
>
> Rob, can we get this merged for 4.4 please?
Yes. I meant to last week, but was waiting on getting another issue
sorted out. I should get it to Linus in the next couple of days.
Rob
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Re: [PATCH v7 45/50] drivers/of: Avoid recursively calling unflatten_dt_node()
+Guenter
On Wed, Nov 4, 2015 at 7:12 AM, Gavin Shan wrote:
> In current implementation, unflatten_dt_node() is called recursively
> to unflatten device nodes in FDT blob. It's stress to limited stack
> capacity.
>
> This avoids calling the function recursively, meaning the device
> nodes are unflattened in one call on unflatten_dt_node(): two arrays
> are introduced to track the parent path size and the device node of
> current level of depth, which will be used by the device node on next
> level of depth to be unflattened. Also, the parameter "poffset" and
> "fpsize" are unused and dropped.
Do you plan to respin the OF parts at least soon? There's another
problem Guenter found that of_fdt_unflatten_tree is not re-entrant due
to "depth" being static and this series fixes that. So I'd rather
apply this and avoid adding a mutex if possible.
Rob
>
> Signed-off-by: Gavin Shan
> ---
> drivers/of/fdt.c | 94
> +---
> 1 file changed, 56 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 173b036..f4793d0 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -355,61 +355,82 @@ static unsigned long populate_node(const void *blob,
> return fpsize;
> }
>
> +static void reverse_nodes(struct device_node *parent)
> +{
> + struct device_node *child, *next;
> +
> + /* In-depth first */
> + child = parent->child;
> + while (child) {
> + reverse_nodes(child);
> +
> + child = child->sibling;
> + }
> +
> + /* Reverse the nodes in the child list */
> + child = parent->child;
> + parent->child = NULL;
> + while (child) {
> + next = child->sibling;
> +
> + child->sibling = parent->child;
> + parent->child = child;
> + child = next;
> + }
> +}
> +
> /**
> * unflatten_dt_node - Alloc and populate a device_node from the flat tree
> * @blob: The parent device tree blob
> * @mem: Memory chunk to use for allocating device nodes and properties
> - * @poffset: pointer to node in flat tree
> * @dad: Parent struct device_node
> * @nodepp: The device_node tree created by the call
> - * @fpsize: Size of the node path up at the current depth.
> * @dryrun: If true, do not allocate device nodes but still calculate needed
> * memory size
> */
> static void *unflatten_dt_node(const void *blob,
>void *mem,
> - int *poffset,
>struct device_node *dad,
>struct device_node **nodepp,
> - unsigned long fpsize,
>bool dryrun)
> {
> - struct device_node *np;
> - static int depth;
> - int old_depth;
> -
> - fpsize = populate_node(blob, *poffset, &mem, dad, fpsize, &np,
> dryrun);
> - if (!fpsize)
> - return mem;
> + struct device_node *root;
> + int offset = 0, depth = 0;
> + unsigned long fpsizes[64];
> + struct device_node *nps[64];
>
> - old_depth = depth;
> - *poffset = fdt_next_node(blob, *poffset, &depth);
> - if (depth < 0)
> - depth = 0;
> - while (*poffset > 0 && depth > old_depth)
> - mem = unflatten_dt_node(blob, mem, poffset, np, NULL,
> - fpsize, dryrun);
> + if (nodepp)
> + *nodepp = NULL;
> +
> + root = dad;
> + fpsizes[depth] = dad ? strlen(of_node_full_name(dad)) : 0;
> + nps[depth++] = dad;
> + while (offset >= 0 && depth < 64) {
> + fpsizes[depth] = populate_node(blob, offset, &mem,
> + nps[depth - 1],
> + fpsizes[depth - 1],
> + &nps[depth], dryrun);
> + if (!fpsizes[depth])
> + return mem;
> +
> + if (!dryrun && nodepp && !*nodepp)
> + *nodepp = nps[depth];
> + if (!dryrun && !root)
> + root = nps[depth];
> +
> + offset = fdt_next_node(blob, offset, &depth);
> + }
>
> - if (*poffset < 0 && *poffset != -FDT_ERR_NOTFOUND)
> - pr_err("unflatten: error %d processing FDT\n", *poffset);
> + if (offset < 0 && offset != -FDT_ERR_NOTFOUND)
> + pr_err("%s: Error %d processing FDT\n",
> + __func__, offset);
>
> /*
> * Reverse the child list. Some drivers assumes node order matches
> .dts
> * node order
> */
> - if (!dryrun && np->child) {
> - struct device_node *child = np->child;
> - np->child = NULL;
> - while (child) {
> - struct device_node *next = ch
[PATCH v9 2/8] ARM: dt: Binding documentation for imx25 GCQ
The documentation describes the bindings for the imx25 GCQ unit which is
essentially a generic conversion queue using the imx25 ADC.
Signed-off-by: Markus Pargmann
---
Notes:
Changes in v9:
- Added the dt-bindings header to this patch instead of the driver
Changes in v6:
- Changed bindings to use adc-refp and adc-refn. Also a bit of cleanup in
the
setup routine.
Changes in v5:
- Fixed locking
- Removed module owner
.../devicetree/bindings/iio/adc/fsl,imx25-gcq.txt | 58 ++
include/dt-bindings/iio/adc/fsl-imx25-gcq.h| 18 +++
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
create mode 100644 include/dt-bindings/iio/adc/fsl-imx25-gcq.h
diff --git a/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
b/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
new file mode 100644
index ..b0866d36a307
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt
@@ -0,0 +1,58 @@
+Freescale i.MX25 ADC GCQ device
+
+This is a generic conversion queue device that can convert any of the
+analog inputs using the ADC unit of the i.MX25.
+
+Required properties:
+ - compatible: Should be "fsl,imx25-gcq".
+ - reg: Should be the register range of the module.
+ - interrupts: Should be the interrupt number of the module.
+ Typically this is <1>.
+ - interrupt-parent: phandle to the tsadc module of the i.MX25.
+ - #address-cells: Should be <1> (setting for the subnodes)
+ - #size-cells: Should be <0> (setting for the subnodes)
+
+Optional properties:
+ - vref-ext-supply: The regulator supplying the ADC reference voltage.
+ Required when at least one subnode uses the this reference.
+ - vref-xp-supply: The regulator supplying the ADC reference voltage on pin XP.
+ Required when at least one subnode uses this reference.
+ - vref-yp-supply: The regulator supplying the ADC reference voltage on pin YP.
+ Required when at least one subnode uses this reference.
+
+Sub-nodes:
+Optionally you can define subnodes which define the reference voltage
+for the analog inputs.
+
+Required properties for subnodes:
+ - reg: Should be the number of the analog input.
+ 0: xp
+ 1: yp
+ 2: xn
+ 3: yn
+ 4: wiper
+ 5: inaux0
+ 6: inaux1
+ 7: inaux2
+Optional properties for subnodes:
+ - fsl,adc-refp: specifies the positive reference input as defined in
+
+ - fsl,adc-refn: specifies the negative reference input as defined in
+
+
+Example:
+
+ adc: adc@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ inaux@5 {
+ reg = <5>;
+ fsl,adc-refp = ;
+ fsl,adc-refn = ;
+ };
+ };
diff --git a/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
b/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
new file mode 100644
index ..87abdd4a7674
--- /dev/null
+++ b/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for configuring the I.MX25 ADC
+ */
+
+#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+
+#define MX25_ADC_REFP_YP 0 /* YP voltage reference */
+#define MX25_ADC_REFP_XP 1 /* XP voltage reference */
+#define MX25_ADC_REFP_EXT 2 /* External voltage reference */
+#define MX25_ADC_REFP_INT 3 /* Internal voltage reference */
+
+#define MX25_ADC_REFN_XN 0 /* XN ground reference */
+#define MX25_ADC_REFN_YN 1 /* YN ground reference */
+#define MX25_ADC_REFN_NGND 2 /* Internal ground reference */
+#define MX25_ADC_REFN_NGND23 /* External ground reference */
+
+#endif
--
2.6.2
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[PATCH v9 3/8] ARM: dt: Binding documentation for imx25 touchscreen controller
This is the touchscreen conversion queue binding documentation. It uses
the shared imx25 ADC.
Signed-off-by: Markus Pargmann
---
Notes:
Changes in v9:
- Updated binding descriptions
Changes in v5:
- Fix signed/unsigned comparison
- Fix unused variable settling_time by putting it in the correct argument
list
- Use continous conversion queue with the repeat feature and a proper
repeat-wait. Previously the touchscreen caused massive number of
interrupts.
.../bindings/input/touchscreen/fsl-mx25-tcq.txt| 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt
diff --git
a/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt
b/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt
new file mode 100644
index ..d45e50872114
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt
@@ -0,0 +1,35 @@
+Freescale mx25 TS conversion queue module
+
+mx25 touchscreen conversion queue module which controls the ADC unit of the
+mx25 for attached touchscreens.
+
+Required properties:
+ - compatible: Should be "fsl,imx25-tcq".
+ - reg: Memory range of the device.
+ - interrupts: Should be the interrupt number associated with this module
within
+ the tscadc unit (<0>).
+ - interrupt-parent: Should be a phandle to the tscadc unit.
+ - fsl,wires: Should be '<4>' or '<5>'
+
+Optional properties:
+ - fsl,pen-debounce: Pen debounce time in nanoseconds.
+ - fsl,pen-threshold: Pen-down threshold for the touchscreen. This is a value
+ between 1 and 4096. It is the ratio between the internal reference voltage
+ and the measured voltage after the plate was precharged. Resistence between
+ plates and therefore the voltage decreases with pressure so that a smaller
+ value is equivalent to a higher pressure.
+ - fsl,settling-time: Settling time in nanoseconds. The settling time is before
+ the actual touch detection to wait for an even charge distribution in the
+ plate.
+
+This device includes two conversion queues which can be added as subnodes.
+The first queue is for the touchscreen, the second for general purpose ADC.
+
+Example:
+ tsc: tcq@50030400 {
+ compatible = "fsl,imx25-tcq";
+ reg = <0x50030400 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <0>;
+ fsl,wires = <4>;
+ };
--
2.6.2
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[PATCH v9 6/8] input: touchscreen: imx25 tcq driver
This is a driver for the imx25 ADC/TSC module. It controls the
touchscreen conversion queue and creates a touchscreen input device.
The driver currently only supports 4 wire touchscreens. The driver uses
a simple conversion queue of precharge, touch detection, X measurement,
Y measurement, precharge and another touch detection.
This driver uses the regmap from the parent to setup some touch specific
settings in the core driver and setup a idle configuration with touch
detection.
Signed-off-by: Markus Pargmann
Signed-off-by: Denis Carikli
[fix clock's period calculation]
[fix calculation of the 'settling' value]
Signed-off-by: Juergen Borleis
---
Notes:
Changes in v9:
- Added module description to Kconfig item
- Fixed devm_ioremap_resource() return value check to use IS_ERR()
- Removed return value of mx25_tcq_create_event_for_4wire()
- Renamed most 'ret' variables through 'error'
- Removed IRQF_ONESHOT
- Rearranged threaded handler to not mix up samples from multiple
measurements
Changes in v7:
- Moved clk_prepare_enable() and mx25_tcq_init() into mx25_tcq_open(). This
was done to be able to use devm_request_threaded_irq().
- Cleanup of the probe function through above change
- Removed mx25_tcq_remove(), not necessary now
drivers/input/touchscreen/Kconfig | 9 +
drivers/input/touchscreen/Makefile| 1 +
drivers/input/touchscreen/fsl-imx25-tcq.c | 596 ++
3 files changed, 606 insertions(+)
create mode 100644 drivers/input/touchscreen/fsl-imx25-tcq.c
diff --git a/drivers/input/touchscreen/Kconfig
b/drivers/input/touchscreen/Kconfig
index ae33da7ab51f..873bf3697e35 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -811,6 +811,15 @@ config TOUCHSCREEN_USB_COMPOSITE
To compile this driver as a module, choose M here: the
module will be called usbtouchscreen.
+config TOUCHSCREEN_MX25
+ tristate "Freescale i.MX25 touchscreen input driver"
+ depends on MFD_MX25_TSADC
+ help
+ Enable support for touchscreen connected to your i.MX25.
+
+ To compile this driver as a module, choose M here: the
+ module will be called fsl-imx25-tcq.
+
config TOUCHSCREEN_MC13783
tristate "Freescale MC13783 touchscreen input driver"
depends on MFD_MC13XXX
diff --git a/drivers/input/touchscreen/Makefile
b/drivers/input/touchscreen/Makefile
index cbaa6abb08da..77a2ac54101a 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_TOUCHSCREEN_INTEL_MID) += intel-mid-touch.o
obj-$(CONFIG_TOUCHSCREEN_IPROC)+= bcm_iproc_tsc.o
obj-$(CONFIG_TOUCHSCREEN_LPC32XX) += lpc32xx_ts.o
obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o
+obj-$(CONFIG_TOUCHSCREEN_MX25) += fsl-imx25-tcq.o
obj-$(CONFIG_TOUCHSCREEN_MC13783) += mc13783_ts.o
obj-$(CONFIG_TOUCHSCREEN_MCS5000) += mcs5000_ts.o
obj-$(CONFIG_TOUCHSCREEN_MIGOR)+= migor_ts.o
diff --git a/drivers/input/touchscreen/fsl-imx25-tcq.c
b/drivers/input/touchscreen/fsl-imx25-tcq.c
new file mode 100644
index ..d1f3d7860ea5
--- /dev/null
+++ b/drivers/input/touchscreen/fsl-imx25-tcq.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann
+ *
+ * This program is free software; you can redistribute it and/or modify it
under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ *
+ * Based on driver from 2011:
+ * Juergen Beisert, Pengutronix
+ *
+ * This is the driver for the imx25 TCQ (Touchscreen Conversion Queue)
+ * connected to the imx25 ADC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const char mx25_tcq_name[] = "mx25-tcq";
+
+enum mx25_tcq_mode {
+ MX25_TS_4WIRE,
+};
+
+struct mx25_tcq_priv {
+ struct regmap *regs;
+ struct regmap *core_regs;
+ struct input_dev *idev;
+ enum mx25_tcq_mode mode;
+ unsigned int pen_threshold;
+ unsigned int sample_count;
+ unsigned int expected_samples;
+ unsigned int pen_debounce;
+ unsigned int settling_time;
+ struct clk *clk;
+ int irq;
+ struct device *dev;
+};
+
+static struct regmap_config mx25_tcq_regconfig = {
+ .fast_io = true,
+ .max_register = 0x5c,
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static const struct of_device_id mx25_tcq_ids[] = {
+ { .compatible = "fsl,imx25-tcq", },
+ { /* Sentinel */ }
+};
+
+#define TSC_4WIRE_PRE_INDEX 0
+#define TSC_4WIRE_X_INDEX 1
+#define TSC_4WIRE_Y_INDEX 2
+#define TSC_4WIRE_POST_INDEX 3
+#define TSC_4WIRE_LEAVE 4
+
+#define MX25_TSC_DEF_THRESHOLD 80
+#define TSC_MAX_SAMPLES 16
+
+#define MX25_TSC_REPEAT_WAIT 14
+
+enum mx25_adc_configurations {
+
[PATCH v9 5/8] iio: adc: fsl,imx25-gcq driver
This is a conversion queue driver for the mx25 SoC. It uses the central
ADC which is used by two seperate independent queues. This driver
prepares different conversion configurations for each possible input.
For a conversion it creates a conversionqueue of one item with the
correct configuration for the chosen channel. It then executes the queue
once and disables the conversion queue afterwards.
The reference voltages are configurable through devicetree subnodes,
depending on the connections of the ADC inputs.
Signed-off-by: Markus Pargmann
Signed-off-by: Denis Carikli
---
Notes:
Changes in v7:
- Remove separate functions mx25_gcq_disable/enable_eoq() as they were
used at
only one position
- Enforce an external reference regulator if one of the conversions uses
it as
reference. The devm_regulator_get() call was moved into
mx25_gcq_setup_cfgs() to be able to acquire the reference regulator when
necessary.
- Store indio_dev as platform driver data instead of the private data. This
was changed in probe() and remove().
Changes in v6:
- Added defines for a complete list of references in the dt binding macros
drivers/iio/adc/Kconfig | 7 +
drivers/iio/adc/Makefile| 1 +
drivers/iio/adc/fsl-imx25-gcq.c | 415
3 files changed, 423 insertions(+)
create mode 100644 drivers/iio/adc/fsl-imx25-gcq.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 7868c744fd4b..73145c53ec2c 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -183,6 +183,13 @@ config EXYNOS_ADC
To compile this driver as a module, choose M here: the module will be
called exynos_adc.
+config FSL_MX25_ADC
+ tristate "Freescale MX25 ADC driver"
+ depends on MFD_MX25_TSADC
+ help
+ Generic Conversion Queue driver used for general purpose ADC in the
+ MX25. This driver supports single measurements using the MX25 ADC.
+
config HI8435
tristate "Holt Integrated Circuits HI-8435 threshold detector"
select IIO_TRIGGERED_EVENT
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 99b37a963a1e..2fe9b78e4b02 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
+obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
obj-$(CONFIG_HI8435) += hi8435.o
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
obj-$(CONFIG_MAX1027) += max1027.o
diff --git a/drivers/iio/adc/fsl-imx25-gcq.c b/drivers/iio/adc/fsl-imx25-gcq.c
new file mode 100644
index ..eb9570876291
--- /dev/null
+++ b/drivers/iio/adc/fsl-imx25-gcq.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann
+ *
+ * This program is free software; you can redistribute it and/or modify it
under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ *
+ * This is the driver for the imx25 GCQ (Generic Conversion Queue)
+ * connected to the imx25 ADC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MX25_GCQ_TIMEOUT (msecs_to_jiffies(2000))
+
+static const char * const driver_name = "mx25-gcq";
+
+enum mx25_gcq_cfgs {
+ MX25_CFG_XP = 0,
+ MX25_CFG_YP,
+ MX25_CFG_XN,
+ MX25_CFG_YN,
+ MX25_CFG_WIPER,
+ MX25_CFG_INAUX0,
+ MX25_CFG_INAUX1,
+ MX25_CFG_INAUX2,
+ MX25_NUM_CFGS,
+};
+
+struct mx25_gcq_priv {
+ struct regmap *regs;
+ struct completion completed;
+ struct clk *clk;
+ int irq;
+ struct regulator *vref[4];
+ u32 channel_vref_mv[MX25_NUM_CFGS];
+};
+
+#define MX25_CQG_CHAN(chan, id) {\
+ .type = IIO_VOLTAGE,\
+ .indexed = 1,\
+ .channel = chan,\
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE),\
+ .datasheet_name = id,\
+}
+
+static const struct iio_chan_spec mx25_gcq_channels[MX25_NUM_CFGS] = {
+ MX25_CQG_CHAN(MX25_CFG_XP, "xp"),
+ MX25_CQG_CHAN(MX25_CFG_YP, "yp"),
+ MX25_CQG_CHAN(MX25_CFG_XN, "xn"),
+ MX25_CQG_CHAN(MX25_CFG_YN, "yn"),
+ MX25_CQG_CHAN(MX25_CFG_WIPER, "wiper"),
+ MX25_CQG_CHAN(MX25_CFG_INAUX0, "inaux0"),
+ MX25_CQG_CHAN(MX25_CFG_INAUX1, "inaux1"),
+ MX25_CQG_CHAN(MX25_CFG_INAUX2, "inaux2"),
+};
+
+static const char * const mx25_gcq_refp_names[] = {
+ [MX25_ADC_REFP_YP] = "yp",
+ [MX25_ADC_REFP_XP] = "xp",
+ [MX25_ADC_REFP_INT] = "int",
+ [MX25_ADC_REFP_EXT] = "ext",
+};
+
+static irqreturn_t mx25_gcq_irq(int irq, void *data)
+{
+ struct mx25_gcq_priv *priv = data;
+ u32 stats;
+
+ regmap_read(priv->regs, MX25_ADCQ_SR, &st
[PATCH v9 7/8] ARM: dts: imx25: Add TSC and ADC support
From: Denis Carikli
Signed-off-by: Denis Carikli
Signed-off-by: Markus Pargmann
---
arch/arm/boot/dts/imx25.dtsi | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 677f81d9dcd5..6ac5e71d312b 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -265,13 +265,36 @@
status = "disabled";
};
- tsc: tsc@5003 {
- compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
- reg = <0x5003 0x4000>;
+ tscadc: tscadc@5003 {
+ compatible = "fsl,imx25-tsadc";
+ reg = <0x5003 0xc>;
interrupts = <46>;
clocks = <&clks 119>;
clock-names = "ipg";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
status = "disabled";
+
+ adc: adc@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ tsc: tcq@50030400 {
+ compatible = "fsl,imx25-tcq";
+ reg = <0x50030400 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <0>;
+ fsl,wires = <4>;
+ status = "disabled";
+ };
};
ssi1: ssi@50034000 {
--
2.6.2
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[PATCH v9 8/8] ARM: imx_v4_v5_defconfig: Add I.MX25 Touchscreen controller and ADC support.
From: Denis Carikli Signed-off-by: Denis Carikli Signed-off-by: Markus Pargmann --- arch/arm/configs/imx_v4_v5_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index d3a8018639de..d6754ac47788 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -88,6 +88,7 @@ CONFIG_KEYBOARD_IMX=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_MX25=y CONFIG_TOUCHSCREEN_MC13783=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=m @@ -107,6 +108,7 @@ CONFIG_HWMON=m CONFIG_SENSORS_MC13783_ADC=m CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y +CONFIG_MFD_MX25_TSADC=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -172,6 +174,8 @@ CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y CONFIG_IMX_DMA=y # CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_FSL_MX25_ADC=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 0/8] imx25 adc and touchscreen driver
Hi, another larger restructuring of the touchscreen driver and some smaller changes in other parts. The changes are noted below each patch description. Best Regards, Markus Denis Carikli (2): ARM: dts: imx25: Add TSC and ADC support ARM: imx_v4_v5_defconfig: Add I.MX25 Touchscreen controller and ADC support. Markus Pargmann (6): ARM: dt: Binding documentation for imx25 ADC/TSC ARM: dt: Binding documentation for imx25 GCQ ARM: dt: Binding documentation for imx25 touchscreen controller mfd: fsl imx25 Touchscreen ADC driver iio: adc: fsl,imx25-gcq driver input: touchscreen: imx25 tcq driver .../devicetree/bindings/iio/adc/fsl,imx25-gcq.txt | 58 ++ .../bindings/input/touchscreen/fsl-mx25-tcq.txt| 35 ++ .../devicetree/bindings/mfd/fsl-imx25-tsadc.txt| 47 ++ arch/arm/boot/dts/imx25.dtsi | 29 +- arch/arm/configs/imx_v4_v5_defconfig | 4 + drivers/iio/adc/Kconfig| 7 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/fsl-imx25-gcq.c| 415 ++ drivers/input/touchscreen/Kconfig | 9 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/fsl-imx25-tcq.c | 596 + drivers/mfd/Kconfig| 9 + drivers/mfd/Makefile | 2 + drivers/mfd/fsl-imx25-tsadc.c | 203 +++ include/dt-bindings/iio/adc/fsl-imx25-gcq.h| 18 + include/linux/mfd/imx25-tsadc.h| 140 + 16 files changed, 1571 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt create mode 100644 Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt create mode 100644 Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt create mode 100644 drivers/iio/adc/fsl-imx25-gcq.c create mode 100644 drivers/input/touchscreen/fsl-imx25-tcq.c create mode 100644 drivers/mfd/fsl-imx25-tsadc.c create mode 100644 include/dt-bindings/iio/adc/fsl-imx25-gcq.h create mode 100644 include/linux/mfd/imx25-tsadc.h -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 4/8] mfd: fsl imx25 Touchscreen ADC driver
This is the core driver for imx25 touchscreen/adc driver. The module
has one shared ADC and two different conversion queues which use the
ADC. The two queues are identical. Both can be used for general purpose
ADC but one is meant to be used for touchscreens.
This driver is the core which manages the central components and
registers of the TSC/ADC unit. It manages the IRQs and forwards them to
the correct components.
Signed-off-by: Markus Pargmann
Signed-off-by: Denis Carikli
[ensure correct ADC clock depending on the IPG clock]
Signed-off-by: Juergen Borleis
Acked-by: Jonathan Cameron
---
Notes:
Changes in v7:
- Cleanup bit defines in header files to be more readable
- Fix irq check to return with an error for irq <= 0
- Add COMPILE_TEST in Kconfig file
Changes in v5:
- Remove ifdef CONFIG_OF as this driver is only for DT usage
- Remove module owner
- Add Kconfig dependencies ARCH_MX25 and OF
drivers/mfd/Kconfig | 9 ++
drivers/mfd/Makefile| 2 +
drivers/mfd/fsl-imx25-tsadc.c | 203
include/linux/mfd/imx25-tsadc.h | 140 +++
4 files changed, 354 insertions(+)
create mode 100644 drivers/mfd/fsl-imx25-tsadc.c
create mode 100644 include/linux/mfd/imx25-tsadc.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6ef9fe..4222e202ad2b 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -271,6 +271,15 @@ config MFD_MC13XXX_I2C
help
Select this if your MC13xxx is connected via an I2C bus.
+config MFD_MX25_TSADC
+ tristate "Freescale i.MX25 integrated Touchscreen and ADC unit"
+ select REGMAP_MMIO
+ depends on (SOC_IMX25 && OF) || COMPILE_TEST
+ help
+ Enable support for the integrated Touchscreen and ADC unit of the
+ i.MX25 processors. They consist of a conversion queue for general
+ purpose ADC and a queue for Touchscreens.
+
config MFD_HI6421_PMIC
tristate "HiSilicon Hi6421 PMU/Codec IC"
depends on OF
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b81b467..5741be88c173 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -81,6 +81,8 @@ obj-$(CONFIG_TWL4030_POWER)+= twl4030-power.o
obj-$(CONFIG_MFD_TWL4030_AUDIO)+= twl4030-audio.o
obj-$(CONFIG_TWL6040_CORE) += twl6040.o
+obj-$(CONFIG_MFD_MX25_TSADC) += fsl-imx25-tsadc.o
+
obj-$(CONFIG_MFD_MC13XXX) += mc13xxx-core.o
obj-$(CONFIG_MFD_MC13XXX_SPI) += mc13xxx-spi.o
obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o
diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c
new file mode 100644
index ..77b2675cf8f5
--- /dev/null
+++ b/drivers/mfd/fsl-imx25-tsadc.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann
+ *
+ * This program is free software; you can redistribute it and/or modify it
under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct regmap_config mx25_tsadc_regmap_config = {
+ .fast_io = true,
+ .max_register = 8,
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static void mx25_tsadc_irq_handler(struct irq_desc *desc)
+{
+ struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 status;
+
+ chained_irq_enter(chip, desc);
+
+ regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
+
+ if (status & MX25_TGSR_GCQ_INT)
+ generic_handle_irq(irq_find_mapping(tsadc->domain, 1));
+
+ if (status & MX25_TGSR_TCQ_INT)
+ generic_handle_irq(irq_find_mapping(tsadc->domain, 0));
+
+ chained_irq_exit(chip, desc);
+}
+
+static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+ struct mx25_tsadc *tsadc = d->host_data;
+
+ irq_set_chip_data(irq, tsadc);
+ irq_set_chip_and_handler(irq, &dummy_irq_chip,
+handle_level_irq);
+ irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops mx25_tsadc_domain_ops = {
+ .map = mx25_tsadc_domain_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int mx25_tsadc_setup_irq(struct platform_device *pdev,
+ struct mx25_tsadc *tsadc)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int irq;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(dev, "Failed to get irq\n");
+ return irq;
+ }
+
+ tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_d
[PATCH v9 1/8] ARM: dt: Binding documentation for imx25 ADC/TSC
This documentation describes the devicetree bindings for the
ADC/Touchscreen unit of the i.MX25 SoC.
Signed-off-by: Markus Pargmann
Acked-by: Jonathan Cameron
Acked-by: Rob Herring
---
Notes:
Changes in v9:
- Fixed some style things.
Changes in v6:
- Removed adc-ref property and replaced it with refp and refn for positive
and
negative references. The properties are optional now as the default
behaviour is a positive internal reference voltage and ADC GND as
negative
reference.
.../devicetree/bindings/mfd/fsl-imx25-tsadc.txt| 47 ++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt
diff --git a/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt
b/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt
new file mode 100644
index ..b03505286997
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt
@@ -0,0 +1,47 @@
+Freescale MX25 ADC/TSC MultiFunction Device (MFD)
+
+This device combines two general purpose conversion queues one used for general
+ADC and the other used for touchscreens.
+
+Required properties:
+ - compatible: Should be "fsl,imx25-tsadc".
+ - reg:Start address and size of the memory
area of
+ the device
+ - interrupts: Interrupt for this device
+ (See:
../interrupt-controller/interrupts.txt)
+ - clocks: An 'ipg' clock (See:
../clock/clock-bindings.txt)
+ - interrupt-controller: This device is an interrupt controller. It
+ controls the interrupts of both
+ conversion queues.
+ - #interrupt-cells: Should be '<1>'.
+ - #address-cells: Should be '<1>'.
+ - #size-cells:Should be '<1>'.
+
+This device includes two conversion queues which can be added as subnodes.
+The first queue is for the touchscreen, the second for general purpose ADC.
+
+Example:
+ tscadc: tscadc@5003 {
+ compatible = "fsl,imx25-tsadc";
+ reg = <0x5003 0xc>;
+ interrupts = <46>;
+ clocks = <&clks 119>;
+ clock-names = "ipg";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ tsc: tcq@50030400 {
+ compatible = "fsl,imx25-tcq";
+ reg = <0x50030400 0x60>;
+ ...
+ };
+
+ adc: gcq@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ ...
+ };
+ };
--
2.6.2
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[PATCH] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file
Add support for the SolidRun Armada 388 Clearfog A1 board. This board
has an Armada 388 microsom, dedicated gigabit ethernet, six switched
gigabit ethernet ports, SFP cage, two Mini-PCIe/mSATA slots, a m.2 SATA
slot, and a MikroBUS connector to allow MikroBUS modules to be added.
This DT file adds support for all board facilities with the exception
of full SFP support.
Signed-off-by: Russell King
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-388-clearfog.dts | 462 +
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 115 +
3 files changed, 578 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dts
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc3746130..7e6a0532c656 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
+ armada-388-clearfog.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-rd.dtb
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts
b/arch/arm/boot/dts/armada-388-clearfog.dts
new file mode 100644
index ..fede93fda788
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -0,0 +1,462 @@
+/*
+ * Device Tree file for SolidRun Clearfog A1 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
+
+/ {
+ model = "SolidRun Clearfog A1";
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ soc {
+ internal-regs {
+ ethernet@3 {
+ mac-address = [00 50 43 02 02 02];
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
Re: [PATCH v4 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
Hi Rob, On 12/6/2015 6:22 AM, Rob Herring wrote: > On Wed, Dec 2, 2015 at 10:06 AM, Kapil Hali wrote: >> Hi Rob, >> >> On 12/2/2015 8:56 PM, Rob Herring wrote: >>> On Tue, Dec 01, 2015 at 11:24:05AM -0500, Kapil Hali wrote: Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's Northstar Plus CPU to the 32-bit ARM CPU device tree binding documentation file and create a new binding documentation for Northstar Plus CPU. Signed-off-by: Kapil Hali --- .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt new file mode 100644 index 000..bf08872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt @@ -0,0 +1,39 @@ +Broadcom Northstar Plus SoC CPU Enable Method +- +This binding defines the enable method used for starting secondary +CPUs in the following Broadcom SoCs: + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + +The enable method is specified by defining the following required +properties in the "cpus" device tree node: + - enable-method = "brcm,bcm-nsp-smp"; + - secondary-boot-reg = <...>; >>> >>> Both of these are supposed to be per cpu core. >> >> 'enable-method' if not found in 'cpu' node is looked at in the 'cpus' >> node. Except for two-three SoC families, 'enable-method' is within >> 'cpus' node. Is my interpretation incorrect? Did I miss anything here? > > I'm not sure how you counted, but it is much more than 2-3 that are > correct (including all of PPC). It is quite mixed in dts files, but it > is documented to be per cpu node, so lets follow the documentation > please. > > Rob > I looked at arch/arm/* and not other arch types. But, as you said, let us keep it how it is in documentation and I have already updated latest patch set reflecting this change. Thanks, Kapil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] spi: sh-msiof: Add support for SH-Mobile AG5
On Sat, Dec 5, 2015 at 10:49 AM, Mark Brown wrote: > On Fri, Dec 04, 2015 at 12:56:08PM -0600, Rob Herring wrote: >> On Mon, Nov 30, 2015 at 03:14:00PM +0100, Geert Uytterhoeven wrote: >> > MSIOF in SH-Mobile AG5 (sh73a0) is handled fine by the existing driver. > >> > Signed-off-by: Geert Uytterhoeven > >> Applied, thanks. > > I've already applied this to the SPI tree? Okay, I'll drop it. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/6] dt: lpc32xx: pwm: correct LPC32xx PWM device node example
The change removes '0x' from a device node address and uses lower case
hex chars.
Signed-off-by: Vladimir Zapolskiy
---
Changes from v1 to v2:
- new change
Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
index cfe1db3..1ab1abc 100644
--- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
@@ -6,7 +6,7 @@ Required properties:
Examples:
-pwm@0x4005C000 {
+pwm@4005c000 {
compatible = "nxp,lpc3220-pwm";
- reg = <0x4005C000 0x8>;
+ reg = <0x4005c000 0x8>;
};
--
2.1.4
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[PATCH v2 6/6] pwm: lpc32xx: return ERANGE, if requested period is not supported
Instead of silent acceptance of unsupported requested configuration for PWM period and setting the boundary supported value, return -ERANGE to a caller. Duty period value equal to 0 or period is still accepted to allow configuration by PWM sysfs interface, when it is set to 0 by default. For reference this is a list of restrictions on period_ns == 1/freq: | PWM parent clock | parent clock divisor | max freq | min freq | +--+--+--+--+ | HCLK == 13 MHz | 1 (min) | 50.7 KHz | 198.3 Hz | | HCLK == 13 MHz | 15 (max) | 3.38 KHz | 13.22 Hz | | RTC == 32.7 KHz | 1 (min) | 128 Hz | 0.5 Hz | | RTC == 32.7 KHz | 15 (max) | 8.533 Hz | 0.033 Hz | Note that PWM sysfs interface does not support setting of period more than NSEC_PER_SEC / MAX_INT32 ~ 2 seconds, however this PWM controller supports a period up to 30 seconds. Signed-off-by: Vladimir Zapolskiy --- Changes from v1 to v2: - none drivers/pwm/pwm-lpc32xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index 294a68f..4d470c1 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -41,9 +41,9 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* The highest acceptable divisor is 256, which is represented by 0 */ period_cycles = div64_u64(c * period_ns, (unsigned long long)NSEC_PER_SEC * 256); - if (!period_cycles) - period_cycles = 1; - if (period_cycles > 255) + if (!period_cycles || period_cycles > 256) + return -ERANGE; + if (period_cycles == 256) period_cycles = 0; /* Compute 256 x #duty/period value and care for corner cases */ -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
