[PATCH 2/3] arm64: dts: Fix interrupt active level for the generic timer on exynos7
Fix the exynos7 device tree to indicate that the arm generic timers
provide an active low interrupt output. Also, update the CPU mask to
match the number of CPUs on the SoC.
Signed-off-by: Abhilash Kesavan
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 749c4b3..c5687f9 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -10,6 +10,7 @@
*/
#include
+#include
/ {
compatible = "samsung,exynos7";
@@ -440,10 +441,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
-<1 14 0xff01>,
-<1 11 0xff01>,
-<1 10 0xff01>;
+ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+<1 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+<1 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+<1 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
pmu_system_controller: system-controller@105c {
--
2.1.0
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[PATCH 3/3] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar Signed-off-by: Abhilash Kesavan --- arch/arm64/configs/defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index be1f12a..e45f290 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -31,6 +31,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_FSL_LS2085A=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_THUNDER=y @@ -93,6 +95,8 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] Minor exynos7 device tree/config patches
Patch 1 specifies the fifo sizes for UART channels on exnyos7. Without this the 4210 compatible defaults will be picked up which are different from that on exynos7. Patch 2 is based on a patch from Liviu Dudau fixing a similar issue for arm boards. Patch 3 is needed to enable support for arm64 based exynos7 platform. Abhilash Kesavan (2): arm64: dts: add fifo size property for uart channels on exynos7 arm64: dts: Fix interrupt active level for the generic timer on exynos7 Alim Akhtar (1): arm64: Enable Exynos7 SOC in the defconfig arch/arm64/boot/dts/exynos/exynos7.dtsi | 13 + arch/arm64/configs/defconfig| 4 2 files changed, 13 insertions(+), 4 deletions(-) -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] arm64: dts: add fifo size property for uart channels on exynos7
Specify the fifo sizes of the 4 uart channels on exynos7 via dt. Signed-off-by: Abhilash Kesavan --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index d7a37c3..749c4b3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -192,6 +192,7 @@ clocks = <&clock_peric0 PCLK_UART0>, <&clock_peric0 SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; @@ -202,6 +203,7 @@ clocks = <&clock_peric1 PCLK_UART1>, <&clock_peric1 SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; status = "disabled"; }; @@ -212,6 +214,7 @@ clocks = <&clock_peric1 PCLK_UART2>, <&clock_peric1 SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <16>; status = "disabled"; }; @@ -222,6 +225,7 @@ clocks = <&clock_peric1 PCLK_UART3>, <&clock_peric1 SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
Hi Olof and Arnd On Tue, Nov 11, 2014 at 7:59 PM, Abhilash Kesavan wrote: > Hello Olof and Arnd, > > On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan > wrote: >> These were originally part of 2 patchsets[1][2] adding support for Exynos7. >> The clock and pinctrl patches are going through the respective maintainer's >> tree; hence the remaining dt related patches have been consolidated and are >> being posted here as a separate series. >> >> This patchset has build dependencies on the following patches: >> a] "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt >>bindings header. >>http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 >> b] "tty: serial: samsung: Clean-up selection of number of available UARTs" >>http://www.spinics.net/lists/linux-samsung-soc/msg37418.html >> c] "dts, kbuild: Implement support for dtb vendor subdirs"(merged in >> linux-next) >>https://lkml.org/lkml/2014/10/21/654 >> >> [1] arch: arm64: Enable support for Samsung Exynos7 SoC >> http://www.spinics.net/lists/linux-samsung-soc/msg37047.html >> [2] Add clock and DT support for a few IPs on Exynos7 >> http://www.spinics.net/lists/linux-samsung-soc/msg37973.html >> >> Changes since v6: >> - Fixed the platform ordering (exynos before thunder) in Kconfig >> file. >> - Fixed the ordering of reg and enable-method properties in cpu node >> as per Lorenzo Pieralisi's comment. > > > Do you have any comments on this patchset ? A gentle reminder regarding this patch set. Kindly review. Abhilash >> >> Abhilash Kesavan (2): >> arm64: dts: Add PMU DT node for exynos7 SoC >> arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 >> >> Alim Akhtar (2): >> arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support >> arm64: Enable Exynos7 SOC in the defconfig >> >> Naveen Krishna Ch (2): >> arm64: dts: Add initial device tree support for EXYNOS7 >> arm64: dts: Add initial pinctrl support to EXYNOS7 >> >> Pankaj Dubey (1): >> arm64: dts: add symlink >> >> .../devicetree/bindings/arm/samsung/pmu.txt| 1 + >> arch/arm64/Kconfig | 17 + >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/exynos/Makefile| 5 + >> arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ >> arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 >> + >> arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ >> arch/arm64/boot/dts/include/dt-bindings| 1 + >> arch/arm64/configs/defconfig | 4 + >> 9 files changed, 1231 insertions(+) >> create mode 100644 arch/arm64/boot/dts/exynos/Makefile >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi >> create mode 12 arch/arm64/boot/dts/include/dt-bindings >> >> -- >> 2.1.0 >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
Hello Olof and Arnd, On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan wrote: > These were originally part of 2 patchsets[1][2] adding support for Exynos7. > The clock and pinctrl patches are going through the respective maintainer's > tree; hence the remaining dt related patches have been consolidated and are > being posted here as a separate series. > > This patchset has build dependencies on the following patches: > a] "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt >bindings header. >http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 > b] "tty: serial: samsung: Clean-up selection of number of available UARTs" >http://www.spinics.net/lists/linux-samsung-soc/msg37418.html > c] "dts, kbuild: Implement support for dtb vendor subdirs"(merged in > linux-next) >https://lkml.org/lkml/2014/10/21/654 > > [1] arch: arm64: Enable support for Samsung Exynos7 SoC > http://www.spinics.net/lists/linux-samsung-soc/msg37047.html > [2] Add clock and DT support for a few IPs on Exynos7 > http://www.spinics.net/lists/linux-samsung-soc/msg37973.html > > Changes since v6: > - Fixed the platform ordering (exynos before thunder) in Kconfig file. > - Fixed the ordering of reg and enable-method properties in cpu node > as per Lorenzo Pieralisi's comment. Do you have any comments on this patchset ? Regards, Abhilash > > Abhilash Kesavan (2): > arm64: dts: Add PMU DT node for exynos7 SoC > arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 > > Alim Akhtar (2): > arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support > arm64: Enable Exynos7 SOC in the defconfig > > Naveen Krishna Ch (2): > arm64: dts: Add initial device tree support for EXYNOS7 > arm64: dts: Add initial pinctrl support to EXYNOS7 > > Pankaj Dubey (1): > arm64: dts: add symlink > > .../devicetree/bindings/arm/samsung/pmu.txt| 1 + > arch/arm64/Kconfig | 17 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/exynos/Makefile| 5 + > arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ > arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 > + > arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ > arch/arm64/boot/dts/include/dt-bindings| 1 + > arch/arm64/configs/defconfig | 4 + > 9 files changed, 1231 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/Makefile > create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts > create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi > create mode 12 arch/arm64/boot/dts/include/dt-bindings > > -- > 2.1.0 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 6/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. It also enables RTC, WDT and Pinctrl for Exynos7. Signed-off-by: Alim Akhtar Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas --- arch/arm64/Kconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 66b0b51..2b5e0b0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -143,6 +143,23 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool "ARMv8 based Samsung Exynos7" + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos7 SoC family + config ARCH_THUNDER bool "Cavium Inc. Thunder SoC Family" help -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 7/7] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar Signed-off-by: Abhilash Kesavan --- arch/arm64/configs/defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ce602c..cc2aa19 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y @@ -84,6 +86,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = &serial_2;
+ mshc0 = &mmc_0;
+ mshc2 = &mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
&serial_2 {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = <200>;
+ clock-frequency = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ clock-frequency = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8aab9f9..d7a37c3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
"dout_sclk_mfc_pll";
};
+ clock_top1: clock-controller@105e {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+<&clock_topc DOUT_SCLK_BUS1_PLL>,
+<&clock_topc DOUT_SCLK_CC_PLL>,
+<&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = "samsung,exynos7-clock-ccore";
+ reg = <0x105b 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+ clock-names = "fin_pll", "dout_aclk_ccore_133";
+ };
+
clock_peric0: clock-controller@1361 {
compatible = "samsung,exynos7-clock-peric0";
reg = <0x1361 0xd00>;
@@ -143,6 +164,27 @@
clock-names = "fin_pll", "dout_aclk_peris_66";
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = "samsung,exynos7-clock-fsys0";
+ reg = <0x10e9 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+<&clock_top1 DOUT_SCLK_MMC2>;
+ clock-names = "fin_pll", "dout_aclk_fsys0_200",
+ "dout_sclk_mmc2";
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = "samsung,exynos7-clock-fsys1";
+ reg = <0x156e 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_t
[PATCH v7 3/7] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 588
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 654 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..2eef4a2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,588 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interr
[PATCH v7 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Rob Herring
Cc: Catalin Marinas
---
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/exynos/Makefile | 5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos7.dtsi"
+
+/ {
+ model = "Samsung Exynos7 Espresso board based on EXYNOS7";
+ compatible = "samsung,exynos7-espresso", "samsung,exynos7";
+
+ aliases {
+ serial0 = &serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = &serial_2;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0x0 0xC000>;
+ };
+};
+
+&fin_pll {
+ clock-frequency = <2400>;
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..6d6a4c2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/ {
+ compatible = "samsung,exynos7";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>
[PATCH v7 4/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+ - "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 22fb71c..8aab9f9 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
<1 11 0xff01>,
<1 10 0xff01>;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x105c 0x5000>;
+ };
};
};
--
2.1.0
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[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] "tty: serial: samsung: Clean-up selection of number of available UARTs" http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Changes since v6: - Fixed the platform ordering (exynos before thunder) in Kconfig file. - Fixed the ordering of reg and enable-method properties in cpu node as per Lorenzo Pieralisi's comment. Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add symlink .../devicetree/bindings/arm/samsung/pmu.txt| 1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 + arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 +++ arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 1/7] arm64: dts: add symlink
From: Pankaj Dubey
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings")
merged in v3.10-rc1 for details.
Cc: Catalin Marinas
Signed-off-by: Pankaj Dubey
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
---
arch/arm64/boot/dts/include/dt-bindings | 1 +
1 file changed, 1 insertion(+)
create mode 12 arch/arm64/boot/dts/include/dt-bindings
diff --git a/arch/arm64/boot/dts/include/dt-bindings
b/arch/arm64/boot/dts/include/dt-bindings
new file mode 12
index 000..08c00e4
--- /dev/null
+++ b/arch/arm64/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
--
2.1.0
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[PATCH v6 6/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. It also enables RTC, WDT and Pinctrl for Exynos7. Signed-off-by: Alim Akhtar Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas --- arch/arm64/Kconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 66b0b51..8196889 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -148,6 +148,23 @@ config ARCH_THUNDER help This enables support for Cavium's Thunder Family of SoCs. +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool "ARMv8 based Samsung Exynos7" + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276 +++
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = &serial_2;
+ mshc0 = &mmc_0;
+ mshc2 = &mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
&serial_2 {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = <200>;
+ clock-frequency = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ clock-frequency = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 2bce3f3..cff0256 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
"dout_sclk_mfc_pll";
};
+ clock_top1: clock-controller@105e {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+<&clock_topc DOUT_SCLK_BUS1_PLL>,
+<&clock_topc DOUT_SCLK_CC_PLL>,
+<&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = "samsung,exynos7-clock-ccore";
+ reg = <0x105b 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+ clock-names = "fin_pll", "dout_aclk_ccore_133";
+ };
+
clock_peric0: clock-controller@1361 {
compatible = "samsung,exynos7-clock-peric0";
reg = <0x1361 0xd00>;
@@ -143,6 +164,27 @@
clock-names = "fin_pll", "dout_aclk_peris_66";
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = "samsung,exynos7-clock-fsys0";
+ reg = <0x10e9 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+<&clock_top1 DOUT_SCLK_MMC2>;
+ clock-names = "fin_pll", "dout_aclk_fsys0_200",
+ "dout_sclk_mmc2";
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = "samsung,exynos7-clock-fsys1";
+ reg = <0x156e 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_t
[PATCH v6 7/7] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar Signed-off-by: Abhilash Kesavan --- arch/arm64/configs/defconfig |4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ce602c..cc2aa19 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y @@ -84,6 +86,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/7] arm64: dts: add symlink
From: Pankaj Dubey
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings")
merged in v3.10-rc1 for details.
Cc: Catalin Marinas
Signed-off-by: Pankaj Dubey
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
---
arch/arm64/boot/dts/include/dt-bindings |1 +
1 file changed, 1 insertion(+)
create mode 12 arch/arm64/boot/dts/include/dt-bindings
diff --git a/arch/arm64/boot/dts/include/dt-bindings
b/arch/arm64/boot/dts/include/dt-bindings
new file mode 12
index 000..08c00e4
--- /dev/null
+++ b/arch/arm64/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
--
1.7.9.5
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[PATCH v6 4/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi|5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+ - "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index c38567a..2bce3f3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
<1 11 0xff01>,
<1 10 0xff01>;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x105c 0x5000>;
+ };
};
};
--
1.7.9.5
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[PATCH v6 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Rob Herring
Cc: Catalin Marinas
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183 +++
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos7.dtsi"
+
+/ {
+ model = "Samsung Exynos7 Espresso board based on EXYNOS7";
+ compatible = "samsung,exynos7-espresso", "samsung,exynos7";
+
+ aliases {
+ serial0 = &serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = &serial_2;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0x0 0xC000>;
+ };
+};
+
+&fin_pll {
+ clock-frequency = <2400>;
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c4cabc6
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/ {
+ compatible = "samsung,exynos7";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>
[PATCH v6 0/7] Enable support for Samsung Exynos7 SoC
Exynos7 is a System-On-Chip that is based on 64-bit ARMv8 RISC processor (Cortex-A57). This patchset adds arch/device tree support for Exynos7. These were originally part of 2 patchsets[1][2] adding support for Exynos7. The clock and pinctrl patches are going through the respective maintainer's tree; hence the remaining dt related patches have been consolidated and are being posted here as a separate series. This patchset has build dependencies on the following patches: a] "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 b] "tty: serial: samsung: Clean-up selection of number of available UARTs" http://www.spinics.net/lists/linux-samsung-soc/msg37418.html c] "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 [1] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html [2] Add clock and DT support for a few IPs on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37973.html Abhilash Kesavan (2): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (2): arm64: dts: Add initial device tree support for EXYNOS7 arm64: dts: Add initial pinctrl support to EXYNOS7 Pankaj Dubey (1): arm64: dts: add symlink .../devicetree/bindings/arm/samsung/pmu.txt|1 + arch/arm64/Kconfig | 17 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/Makefile|5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 84 +++ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 588 arch/arm64/boot/dts/exynos/exynos7.dtsi| 530 ++ arch/arm64/boot/dts/include/dt-bindings|1 + arch/arm64/configs/defconfig |4 + 9 files changed, 1231 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 3/7] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 588 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 654 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..2eef4a2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,588 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interr
Re: [PATCH v2 3/7] clk: samsung: exynos7: add clocks for RTC block
Hello Sylwester, On Mon, Oct 27, 2014 at 10:01 PM, Sylwester Nawrocki wrote: > Hi, > > On 21/10/14 07:43, Abhilash Kesavan wrote: >> From: Naveen Krishna Ch >> >> Add clock support for the RTC block in Exynos7. >> >> Signed-off-by: Naveen Krishna Ch >> Signed-off-by: Abhilash Kesavan >> --- >> .../devicetree/bindings/clock/exynos7-clock.txt|5 ++ >> drivers/clk/samsung/clk-exynos7.c | 54 >> >> include/dt-bindings/clock/exynos7-clk.h| 17 +++--- >> 3 files changed, 70 insertions(+), 6 deletions(-) > [...] >> diff --git a/include/dt-bindings/clock/exynos7-clk.h >> b/include/dt-bindings/clock/exynos7-clk.h >> index ff63c4e..3227679 100644 >> --- a/include/dt-bindings/clock/exynos7-clk.h >> +++ b/include/dt-bindings/clock/exynos7-clk.h >> @@ -11,12 +11,13 @@ >> #define _DT_BINDINGS_CLOCK_EXYNOS7_H >> >> /* TOPC */ >> -#define DOUT_ACLK_PERIS 1 >> -#define DOUT_SCLK_BUS0_PLL 2 >> -#define DOUT_SCLK_BUS1_PLL 3 >> -#define DOUT_SCLK_CC_PLL 4 >> -#define DOUT_SCLK_MFC_PLL5 >> -#define TOPC_NR_CLK 6 >> +#define DOUT_ACLK_CCORE_133 1 >> +#define DOUT_ACLK_PERIS 2 >> +#define DOUT_SCLK_BUS0_PLL 3 >> +#define DOUT_SCLK_BUS1_PLL 4 >> +#define DOUT_SCLK_CC_PLL 5 >> +#define DOUT_SCLK_MFC_PLL6 >> +#define TOPC_NR_CLK 7 > > Please don't do that, don't change the meaning of already defined > clock identifiers. We should carefully assign the clock identifiers > based on the SoC documentation beforehand, not at will when we see > fit for development of the Linux driver. Please either add > DOUT_ACLK_CCORE_133 at the end of list or move this change to the > first patch in your series adding initial support for Exynos7 SoC. Thanks for reviewing this series and picking up the initial patchset. I will re-post this patchset with the ccore clock at the end of the list. All the future clock id entries will be added at the bottom of the list. Regards, Abhilash > > -- > Thanks, > Sylwester > > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
+Sylwester On Wed, Oct 8, 2014 at 11:18 AM, Abhilash Kesavan wrote: > Hi Tomasz, > > On Tue, Oct 7, 2014 at 9:46 AM, Kukjin Kim wrote: >> Tomasz Figa wrote: >>> >>> On 30.09.2014 17:12, Abhilash Kesavan wrote: >>> > Hi Tomasz, >>> > >>> > On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa >>> > wrote: >>> >> Hi Abhilash, >>> >> >>> >> On 22.09.2014 06:47, Abhilash Kesavan wrote: >>> >>> Changes since v4: >>> >>> - Fixed comments from Tomasz Figa: >>> >>> - Changed the namespace prefix from exynos to samsung >>> >>> - Defined bindings to take all input clocks >>> >>> - Sorted the Kconfig entries alphabetically in clock Makefile >>> >>> - Used consistent 1 tab line breaks across the clock file >>> >>> - Statically initialized the samsung_cmu_info struct >>> >>> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' >>> >>> comment. >>> >>> - Added Kukjin Kim's ack along with Thomas Abraham's tested and >>> >>> reviewed tags. >>> >>> >>> >> >>> >> The clock patches look good to me, but since they are doing quite a lot >>> >> of code moving I'd prefer to take them through clk tree. Based on the >>> >> fact that there are no code dependencies between clock patches and >>> >> remaining ones and Exynos7 is a new material for 3.18, I'm inclined to >>> >> apply them to my tree if nobody minds. >>> > >>> > Will you be picking up the clock changes soon ? >>> >>> I'd like to do so. Kukjin, since clock changes are a part of this >>> series, might I have your Ack for them to be applied separately? >>> >> Sure, I'm fine so please go ahead with my ack on the changes. >> >> Acked-by: Kukjin Kim >> >> Thanks for your asking. > > Can you please pick up the clock changes now that Kukjin has ack'ed it. Sylwester, you mentioned in another thread that Tomasz might not be available for the next few days. Could you please consider applying the clock changes in this series to samsung clk-next if they look OK ? Please take a look at clock changes at http://www.spinics.net/lists/arm-kernel/msg370673.html too. Regards, Abhilash -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Fri, Oct 24, 2014 at 5:31 PM, Linus Walleij wrote: > On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan > wrote: > >> Can you please pick this series up. > > Yes, sorry for the delay. I've applied patches > 1,2,3,4. The patches to the DTS files should be taken > through whatever tree funnels arm64 dts files. Thank you for applying my patches. However, this version (v5) was based on Tomasz's clean-up series and makes use of structures such as "samsung_pin_bank_data" introduced by his series. It also marks the samsung_pin_ctrl instance as __initconst. Thus, patch 4 would cause compilation issues if Tomasz's clean-up patches have not been applied before it. My v4 version was independent of Tomasz's patch series and could be applied directly. Regards, Abhilash > > I hope Tomasz can rebase his nice > clean-up patches on top of this now. > > Yours, > Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
Hi Alim and Tomasz,
Thanks for the review.
On Wed, Oct 22, 2014 at 3:05 AM, Alim Akhtar wrote:
> Hi Tomasz,
>
> On Tue, Oct 21, 2014 at 7:30 PM, Tomasz Figa wrote:
>> On 21.10.2014 15:52, Alim Akhtar wrote:
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
>>> Please use mmc_hs200-1_8v instead.
>>
>> I guess you mean "mmc-hs200-1_8v" (with a hyphen between mmc and hs200).
>>
> Yes, right, that was a typo. Thanks.
Will modify it to "mmc-hs200-1_8v".
+ supports-highspeed;
>>> As per synopsys-dw-mshc DT binding documentation, supports-highspeed
>>> property is deprecated, so please use common DT binding for this,
>>> which is "cap-mmc-highspeed".
+ non-removable;
+ card-detect-delay = <200>;
+ clock-frequency = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
&sd0_bus8>;
+ bus-width = <8>;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
>>> Here also common DT binding please "cap-sd-highspeed"
>>
>> Above you suggest "cap-mmc-highspeed" to replace the same deprecated
>> property, but here "cap-sd-highspeed". What is the rationale behind
>> using only one particular new property and not both for both controllers?
>>
> Well, on this particular board dw_mmc channels are dedicated to use
> only one kind of card. e.g. mmc_0 is for eMMC and which is
> non-removable and mmc_2 is for SD cards. Although controller supports
> both the properties on all channel on this SoC.
Will use "cap-sd/mmc-highspeed" instead of "supports-highspeed".
Regards,
Abhilash
>
>> Best regards,
>> Tomasz
>
>
>
> --
> Regards,
> Alim
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH v2 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
Enable rtc and watchdog support for exynos7 SoCs. Signed-off-by: Abhilash Kesavan --- arch/arm64/Kconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 238acff..9bb4e02 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -158,6 +158,9 @@ config ARCH_EXYNOS7 select COMMON_CLK_SAMSUNG select PINCTRL select PINCTRL_EXYNOS + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi|5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+ - "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..6db8c78 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
<1 11 0xff01>,
<1 10 0xff01>;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x105c 0x5000>;
+ };
};
};
--
1.7.9.5
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[PATCH v2 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, and watchdog
on Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 41
arch/arm64/boot/dts/exynos/exynos7.dtsi | 256 +++
2 files changed, 297 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..d081c26 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = &serial_2;
+ mshc0 = &mmc_0;
+ mshc2 = &mmc_2;
};
chosen {
@@ -37,3 +39,42 @@
&serial_2 {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = <200>;
+ clock-frequency = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ clock-frequency = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6db8c78..1300ded 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
"dout_sclk_mfc_pll";
};
+ clock_top1: clock-controller@105e {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+<&clock_topc DOUT_SCLK_BUS1_PLL>,
+<&clock_topc DOUT_SCLK_CC_PLL>,
+<&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = "samsung,exynos7-clock-ccore";
+ reg = <0x105b 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+ clock-names = "fin_pll", "dout_aclk_ccore_133";
+ };
+
clock_peric0: clock-controller@1361 {
compatible = "samsung,exynos7-clock-peric0";
reg = <0x1361 0xd00>;
@@ -143,6 +164,27 @@
clock-names = "fin_pll", "dout_aclk_peris_66";
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = "samsung,exynos7-clock-fsys0";
+ reg = <0x10e9 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+<&clock_top1 DOUT_SCLK_MMC2>;
+ clock-names = "fin_pll", "dout_aclk_fsys0_200",
+ "dout_sclk_mmc2";
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = "samsung,exynos7-clock-fsys1";
+ reg = <0x156e 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
+<&
[PATCH v2 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
"samsung,exynos7-clock-peric1",
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll",
"dout_aclk_peris_66" };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
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[PATCH v2 3/7] clk: samsung: exynos7: add clocks for RTC block
From: Naveen Krishna Ch
Add clock support for the RTC block in Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos7-clock.txt|5 ++
drivers/clk/samsung/clk-exynos7.c | 54
include/dt-bindings/clock/exynos7-clk.h| 17 +++---
3 files changed, 70 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index b29cb50..6d3d5f8 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
- "samsung,exynos7-clock-top1"
+ - "samsung,exynos7-clock-ccore"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
@@ -60,6 +61,10 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for ccore clock controller:
+ - fin_pll
+ - dout_aclk_ccore_133
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
#define AUD_PLL_CON0 0x0140
#define MUX_SEL_TOPC0 0x0200
#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC2 0x0208
#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
AUD_PLL_CON0,
MUX_SEL_TOPC0,
MUX_SEL_TOPC1,
+ MUX_SEL_TOPC2,
MUX_SEL_TOPC3,
+ DIV_TOPC0,
DIV_TOPC1,
DIV_TOPC3,
};
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[]
__initdata = {
MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
};
static struct samsung_div_clock topc_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+ DIV_TOPC0, 4, 4),
+
DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
DIV_TOPC1, 24, 4),
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_CCORE (0x105B) */
+#define MUX_SEL_CCORE 0x0200
+#define DIV_CCORE 0x0600
+#define ENABLE_ACLK_CCORE0 0x0800
+#define ENABLE_ACLK_CCORE1 0x0804
+#define ENABLE_PCLK_CCORE 0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+ MUX_SEL_CCORE,
+ ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+ MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+ MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+ GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+ ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+ .mux_clks = ccore_mux_clks,
+ .nr_mux_clks= ARRAY_SIZE(ccore_mux_clks),
+ .gate_clks = ccore_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
+ .nr_clk_ids = CCORE_NR_CLK,
+ .clk_regs = ccore_clk_regs,
+ .nr_clk_regs= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+ exynos7_clk_ccore_init);
+
/* Register Offset definitions for CMU_PERIC0 (0x1361) */
#define MUX_SEL_PERIC0 0x0200
#define ENABLE_PCLK_PERIC0 0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
inde
[PATCH v2 2/7] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos7-clock.txt| 21 ++
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 265 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
+ - "samsung,exynos7-clock-top1"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
+ - "samsung,exynos7-clock-fsys0"
+ - "samsung,exynos7-clock-fsys1"
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)= { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+ "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+ "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+ "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+ "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+ "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+ "mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4
[PATCH v2 1/7] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
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[PATCH v2 0/7] Add clock and DT support for a few IPs on Exynos7
Changes since v1: - Added documentation for input clocks of the newly added CMUs Following are the dependencies: 1) dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 2) arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html 3) Serial clean-up patches for Exynos7 http://www.spinics.net/lists/arm-kernel/msg367348.html http://www.spinics.net/lists/arm-kernel/msg367349.html 4) Add initial support for pinctrl on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37708.html For testing I have applied the following: 1) mmc: dw_mmc: Add IDMAC 64-bit address mode support http://www.spinics.net/lists/kernel/msg1842300.html 2) mmc: dw_mmc: Reset DMA before enabling IDMAC http://www.gossamer-threads.com/lists/linux/kernel/2021576?page=last 3) drivers: rtc: fix s3c-rtc initialization failure without rtc source clock https://lkml.org/lkml/2014/10/15/210 4) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 5) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 6) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. 7) watchdog: s3c2410_wdt: Fix the mask bit offset for Exynos7 http://www.spinics.net/lists/linux-watchdog/msg05292.html Abhilash Kesavan (3): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7 arm64: exynos: Enable rtc and watchdog support for Exynos7 Naveen Krishna Ch (4): clk: samsung: exynos7: add clocks for I2C block clk: samsung: exynos7: add clocks for MMC block clk: samsung: exynos7: add clocks for RTC block clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks .../devicetree/bindings/arm/samsung/pmu.txt|1 + .../devicetree/bindings/clock/exynos7-clock.txt| 26 ++ arch/arm64/Kconfig |3 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 41 +++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 261 drivers/clk/samsung/clk-exynos7.c | 316 include/dt-bindings/clock/exynos7-clk.h| 60 +++- 7 files changed, 699 insertions(+), 9 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Sun, Oct 12, 2014 at 12:27 AM, Tomasz Figa wrote: > Abhilash, Linus, > > On 09.10.2014 15:54, Abhilash Kesavan wrote: >> Changes since v4: >> - Rebased over Tomasz Figa's pinctrl clean-up patches[1] >> >> Changes since v3: >> - Changed variable name from exynos_wkup_irq_chip to irq_chip >> - Added acked-by tag from Tomasz Figa >> >> Changes since v2: >> - Added a .irq_chip field to the samsung_pin_bank struct >> - Consolidated the wakeup and gpio irqd_ops >> >> Changes since v1: >> - Marked the newly created irq_chip instances as __initdata >> - Used kmemdup to keep a copy of the irq_chip >> - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM >> - Moved the pinctrl enablement for exynos7 into a separate patch >> - Added tested-by and reviewed-by tags from Thomas Abraham >> >> This series has been tested on linux-next (20141008) >> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ with >> the following dependencies and [1]. >> >> a) Samsung Serial symbol clean-up for exynos7 serial driver enablement (v2) >>http://www.spinics.net/lists/arm-kernel/msg366947.html >>http://www.spinics.net/lists/arm-kernel/msg366948.html >> b) "dts, kbuild: Implement support for dtb vendor subdirs" patchset - rebased >>http://comments.gmane.org/gmane.linux.kbuild.devel/12131 >> c) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) - >> rebased >>http://www.spinics.net/lists/arm-kernel/msg364014.html >> >> [1] https://lkml.org/lkml/2014/10/2/476 >> >> Abhilash Kesavan (3): >> pinctrl: exynos: Generalize the eint16_31 demux code >> pinctrl: exynos: Consolidate irq domain callbacks >> pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts >> >> Naveen Krishna Ch (3): >> pinctrl: exynos: Add initial driver data for Exynos7 >> arm64: dts: Add initial pinctrl support to EXYNOS7 >> arm64: exynos: Enable pinctrl support for Exynos7 >> >> .../bindings/pinctrl/samsung-pinctrl.txt |3 + >> arch/arm64/Kconfig |2 + >> arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 >> >> arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ >> drivers/pinctrl/samsung/pinctrl-exynos.c | 188 +-- >> drivers/pinctrl/samsung/pinctrl-exynos.h |3 + >> drivers/pinctrl/samsung/pinctrl-samsung.c |2 + >> drivers/pinctrl/samsung/pinctrl-samsung.h |3 + >> 8 files changed, 791 insertions(+), 36 deletions(-) >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi >> > > No further comments from me. Thanks Abhilash for addressing all of them. > > Linus, feel free to apply this series with my ACK (which seems to be > already present in all patches). Can you please pick this series up. Thanks, Abhilash > > Best regards, > Tomasz > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
Hi Vivek,
On Mon, Oct 20, 2014 at 3:19 PM, Vivek Gautam wrote:
> Hi Abhilash,
>
>
> On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan
> wrote:
>> From: Naveen Krishna Ch
>>
>> Exynos7 supports 3 MMC channels, add the MMC gate clocks to
>> support them.
>>
>> Signed-off-by: Naveen Krishna Ch
>> Signed-off-by: Abhilash Kesavan
>> ---
>> .../devicetree/bindings/clock/exynos7-clock.txt|3 +
>> drivers/clk/samsung/clk-exynos7.c | 224
>>
>> include/dt-bindings/clock/exynos7-clk.h| 20 ++
>> 3 files changed, 247 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> index 789f761..4c69b66 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
>> @@ -27,9 +27,12 @@ Required Properties for Clock Controller:
>>
>> - "samsung,exynos7-clock-topc"
>> - "samsung,exynos7-clock-top0"
>> + - "samsung,exynos7-clock-top1"
>> - "samsung,exynos7-clock-peric0"
>> - "samsung,exynos7-clock-peric1"
>> - "samsung,exynos7-clock-peris"
>> + - "samsung,exynos7-clock-fsys0"
>> + - "samsung,exynos7-clock-fsys1"
>
> same here, the input clocks for top1, fsys0 and fsys1 block need to be
> mentioned in this doc.
Thanks for the review. I missed adding these, will fix in the next version.
Regards,
Abhilash
>
>>
>> - reg: physical base address of the controller and the length of
>> memory mapped region.
>> diff --git a/drivers/clk/samsung/clk-exynos7.c
>> b/drivers/clk/samsung/clk-exynos7.c
>> index c700f65..f5e43fa 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
>> device_node *np)
>> CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>> exynos7_clk_top0_init);
>>
>> +/* Register Offset definitions for CMU_TOP1 (0x105E) */
>> +#define MUX_SEL_TOP10 0x0200
>> +#define MUX_SEL_TOP11 0x0204
>> +#define MUX_SEL_TOP13 0x020C
>> +#define MUX_SEL_TOP1_FSYS0 0x0224
>> +#define MUX_SEL_TOP1_FSYS1 0x0228
>> +#define DIV_TOP13 0x060C
>> +#define DIV_TOP1_FSYS0 0x0624
>> +#define DIV_TOP1_FSYS1 0x0628
>> +#define ENABLE_ACLK_TOP13 0x080C
>> +#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
>> +#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
>> +
>> +/* List of parent clocks for Muxes in CMU_TOP1 */
>> +PNAME(mout_top1_bus0_pll_p)= { "fin_pll", "dout_sclk_bus0_pll" };
>> +PNAME(mout_top1_bus1_pll_p)= { "fin_pll", "dout_sclk_bus1_pll_b" };
>> +PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
>> +PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
>> +
>> +PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
>> + "ffac_top1_bus0_pll_div2"};
>> +PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
>> + "ffac_top1_bus1_pll_div2"};
>> +PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
>> + "ffac_top1_cc_pll_div2"};
>> +PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
>> + "ffac_top1_mfc_pll_div2"};
>> +
>> +PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
>> + "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
>> + "mout_top1_half_mfc_pll"};
>> +
>> +static unsigned long top1_clk_regs[] __initdata = {
>> + MUX_SEL_TOP10,
>> + MUX_SEL_TOP11,
>> + MUX_SEL_TOP13,
>> + MUX_SEL_TOP1_FSYS0,
>> + MUX_SEL_TOP1_FSYS1,
>> + DIV_TOP13,
>> + DIV_TOP1_FSYS0,
>> + DIV_TOP1_FSYS1,
>> + ENABLE_ACLK_TOP13,
>> + ENABLE_SCLK_TOP1_FSYS0,
>> + ENABLE_SCLK_TOP1_FSYS1,
>> +};
>> +
>> +static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>> + MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4,
>> 1),
>> +
Re: [GIT PULL] dts, kbuild: Implement support for dtb vendor subdirs
Hello Robert,
On Thu, Oct 2, 2014 at 8:38 PM, Robert Richter wrote:
> On 23.09.14 13:26:19, Robert Richter wrote:
>> On 19.09.14 15:08:56, Catalin Marinas wrote:
>> > On Fri, Sep 19, 2014 at 01:30:56PM +0100, Robert Richter wrote:
>> > > On 16.09.14 20:49:18, Andrew Bresticker wrote:
>> > > > > Robert Richter (6):
>> > > > > dts, arm64: Add dtbs_install make target
>> > > > > dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
>> > > > > dts, arm/arm64: Remove dtbs build rules in sub-makes
>> > > > > dts, kbuild: Implement support for dtb vendor subdirs
>> > > > > dts, arm64: Move dts files to vendor subdirs
>> > > > > dts, arm: Remove $(MACHINE) variable from dtbs make recipes
>> > > >
>> > > > I've tested this for arm64 and by adding a vendor sub-directory
>> > > > locally for arm. This series is also the base for my MIPS DT vendor
>> > > > sub-directory series
>> > > > (http://www.linux-mips.org/archives/linux-mips/2014-09/msg00217.html).
>> > > > So, for the entire series,
>> > > >
>> > > > Tested-by: Andrew Bresticker
>> > >
>> > > Andrew, thanks for testing and great this also works on mips.
>> > >
>> > > Anyone willing to take the patches for 3.18? Are any further acks
>> > > needed?
>> >
>> > For the arm64 bits in this series:
>> >
>> > Acked-by: Catalin Marinas
>> >
>> > I think the patches can be merged via arm-soc.
>>
>> Olof,
>>
>> please apply the patches.
>
> Olof, Arnd,
>
> you may want to pull from here alternatively.
I have been using your patchset as the base for my new arm64 SoC
support (http://www.spinics.net/lists/linux-samsung-soc/msg37047.html).
Are you planning to rebase and send this again as some of the patches
did not apply cleanly for me on linux-next.
Regards,
Abhilash
>
> Thanks,
>
> -Robert
>
>
> The following changes since commit a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee:
>
> Linux 3.16-rc2 (2014-06-21 19:02:54 -1000)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/rric/linux.git
> tags/dts-subdirs-for-arm-soc-v3.18
>
> for you to fetch changes up to 87bdf4d8625e50d99b56aa2590a2261049a5fd48:
>
> dts, arm: Remove $(MACHINE) variable from dtbs make recipes (2014-09-03
> 21:46:49 +0200)
>
>
> dts, kbuild: Implement support for dtb vendor subdirs
>
>
> Robert Richter (6):
> dts, arm64: Add dtbs_install make target
> dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
> dts, arm/arm64: Remove dtbs build rules in sub-makes
> dts, kbuild: Implement support for dtb vendor subdirs
> dts, arm64: Move dts files to vendor subdirs
> dts, arm: Remove $(MACHINE) variable from dtbs make recipes
>
> arch/arm/Makefile | 8 +++-
> arch/arm/boot/dts/Makefile | 12 +-
> arch/arm64/Makefile| 10 -
> arch/arm64/boot/dts/Makefile | 13 +++---
> arch/arm64/boot/dts/apm/Makefile | 5 +++
> arch/arm64/boot/dts/{ => apm}/apm-mustang.dts | 0
> arch/arm64/boot/dts/{ => apm}/apm-storm.dtsi | 0
> arch/arm64/boot/dts/arm/Makefile | 6 +++
> arch/arm64/boot/dts/{ => arm}/foundation-v8.dts| 0
> arch/arm64/boot/dts/{ => arm}/rtsm_ve-aemv8a.dts | 0
> .../boot/dts/{ => arm}/rtsm_ve-motherboard.dtsi| 0
> scripts/Kbuild.include | 6 +++
> scripts/Makefile.dtbinst | 50
> ++
> scripts/Makefile.lib | 12 --
> 14 files changed, 88 insertions(+), 34 deletions(-)
> create mode 100644 arch/arm64/boot/dts/apm/Makefile
> rename arch/arm64/boot/dts/{ => apm}/apm-mustang.dts (100%)
> rename arch/arm64/boot/dts/{ => apm}/apm-storm.dtsi (100%)
> create mode 100644 arch/arm64/boot/dts/arm/Makefile
> rename arch/arm64/boot/dts/{ => arm}/foundation-v8.dts (100%)
> rename arch/arm64/boot/dts/{ => arm}/rtsm_ve-aemv8a.dts (100%)
> rename arch/arm64/boot/dts/{ => arm}/rtsm_ve-motherboard.dtsi (100%)
> create mode 100644 scripts/Makefile.dtbinst
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[PATCH 0/7] Add clock and DT support for a few IPs on Exynos7
This series adds clock support for I2C, MMC, RTC, Watchdog, TMU and PWM. It also adds the device nodes for I2C, RTC, WDT, MMC and PMU. The patchset has been tested on linux-next (20141017) on an Exynos7 Espresso board. Following are the dependencies: 1) dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 2) arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html 3) Serial clean-up patches for Exynos7 http://www.spinics.net/lists/arm-kernel/msg367348.html http://www.spinics.net/lists/arm-kernel/msg367349.html 4) Add initial support for pinctrl on Exynos7 http://www.spinics.net/lists/linux-samsung-soc/msg37708.html For testing I have applied the following: 1) mmc: dw_mmc: Add IDMAC 64-bit address mode support http://www.spinics.net/lists/kernel/msg1842300.html 2) mmc: dw_mmc: Reset DMA before enabling IDMAC http://www.gossamer-threads.com/lists/linux/kernel/2021576?page=last 3) mmc: dw_mmc: exynos: Add support for exynos7 http://www.spinics.net/lists/linux-mmc/msg28294.html 4) mfd: sec: add S2MPS15 PMIC support https://lkml.org/lkml/2014/10/14/50 5) drivers: rtc: fix s3c-rtc initialization failure without rtc source clock https://lkml.org/lkml/2014/10/15/210 6) regulator: s2mps11: add support for S2MPS15 regulators https://lkml.org/lkml/2014/10/14/52 7) Regulators dt nodes were added in the espresso dts file and I2C channel 4 which has the PMIC on it was tested. Abhilash Kesavan (3): arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7 arm64: exynos: Enable rtc and watchdog support for Exynos7 Naveen Krishna Ch (4): clk: samsung: exynos7: add clocks for I2C block clk: samsung: exynos7: add clocks for MMC block clk: samsung: exynos7: add clocks for RTC block clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks .../devicetree/bindings/arm/samsung/pmu.txt|1 + .../devicetree/bindings/clock/exynos7-clock.txt|4 + arch/arm64/Kconfig |3 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 41 +++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 261 drivers/clk/samsung/clk-exynos7.c | 316 include/dt-bindings/clock/exynos7-clk.h| 60 +++- 7 files changed, 677 insertions(+), 9 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
Enable rtc and watchdog support for exynos7 SoCs. Signed-off-by: Abhilash Kesavan --- arch/arm64/Kconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 238acff..9bb4e02 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -158,6 +158,9 @@ config ARCH_EXYNOS7 select COMMON_CLK_SAMSUNG select PINCTRL select PINCTRL_EXYNOS + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] clk: samsung: exynos7: add clocks for RTC block
From: Naveen Krishna Ch
Add clock support for the RTC block in Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos7-clock.txt|1 +
drivers/clk/samsung/clk-exynos7.c | 54
include/dt-bindings/clock/exynos7-clk.h| 17 +++---
3 files changed, 66 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 4c69b66..aff6fd2 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
- "samsung,exynos7-clock-top1"
+ - "samsung,exynos7-clock-ccore"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index f5e43fa..3a30f43 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -29,7 +29,9 @@
#define AUD_PLL_CON0 0x0140
#define MUX_SEL_TOPC0 0x0200
#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC2 0x0208
#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = {
AUD_PLL_CON0,
MUX_SEL_TOPC0,
MUX_SEL_TOPC1,
+ MUX_SEL_TOPC2,
MUX_SEL_TOPC3,
+ DIV_TOPC0,
DIV_TOPC1,
DIV_TOPC3,
};
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[]
__initdata = {
MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
};
static struct samsung_div_clock topc_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+ DIV_TOPC0, 4, 4),
+
DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
DIV_TOPC1, 24, 4),
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_CCORE (0x105B) */
+#define MUX_SEL_CCORE 0x0200
+#define DIV_CCORE 0x0600
+#define ENABLE_ACLK_CCORE0 0x0800
+#define ENABLE_ACLK_CCORE1 0x0804
+#define ENABLE_PCLK_CCORE 0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+ MUX_SEL_CCORE,
+ ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+ MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+ MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+ GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+ ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+ .mux_clks = ccore_mux_clks,
+ .nr_mux_clks= ARRAY_SIZE(ccore_mux_clks),
+ .gate_clks = ccore_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
+ .nr_clk_ids = CCORE_NR_CLK,
+ .clk_regs = ccore_clk_regs,
+ .nr_clk_regs= ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+ exynos7_clk_ccore_init);
+
/* Register Offset definitions for CMU_PERIC0 (0x1361) */
#define MUX_SEL_PERIC0 0x0200
#define ENABLE_PCLK_PERIC0 0x0900
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index ff63c4e..3227679 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -11,12 +11,13 @@
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
/* TOPC */
-#define DOUT_ACLK_PERIS1
-#define DOUT_SCLK_BUS0_PLL 2
-#define DOUT_SCLK_B
[PATCH 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, and watchdog
on Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 41
arch/arm64/boot/dts/exynos/exynos7.dtsi | 256 +++
2 files changed, 297 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..d081c26 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = &serial_2;
+ mshc0 = &mmc_0;
+ mshc2 = &mmc_2;
};
chosen {
@@ -37,3 +39,42 @@
&serial_2 {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = <200>;
+ clock-frequency = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ clock-frequency = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6db8c78..1300ded 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
"dout_sclk_mfc_pll";
};
+ clock_top1: clock-controller@105e {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+<&clock_topc DOUT_SCLK_BUS1_PLL>,
+<&clock_topc DOUT_SCLK_CC_PLL>,
+<&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = "samsung,exynos7-clock-ccore";
+ reg = <0x105b 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
+ clock-names = "fin_pll", "dout_aclk_ccore_133";
+ };
+
clock_peric0: clock-controller@1361 {
compatible = "samsung,exynos7-clock-peric0";
reg = <0x1361 0xd00>;
@@ -143,6 +164,27 @@
clock-names = "fin_pll", "dout_aclk_peris_66";
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = "samsung,exynos7-clock-fsys0";
+ reg = <0x10e9 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
+<&clock_top1 DOUT_SCLK_MMC2>;
+ clock-names = "fin_pll", "dout_aclk_fsys0_200",
+ "dout_sclk_mmc2";
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = "samsung,exynos7-clock-fsys1";
+ reg = <0x156e 0xd00>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
+<&
[PATCH 1/7] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
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[PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos7-clock.txt|3 +
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
+ - "samsung,exynos7-clock-top1"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
+ - "samsung,exynos7-clock-fsys0"
+ - "samsung,exynos7-clock-fsys1"
- reg: physical base address of the controller and the length of
memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)= { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+ "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+ "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+ "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+ "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+ "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+ "mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+ MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+ MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+ MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+ MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_T
[PATCH 5/7] arm64: dts: Add PMU DT node for exynos7 SoC
Adds PMU DT node for exynos7 SoC.
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm64/boot/dts/exynos/exynos7.dtsi|5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..67b2113 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+ - "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..6db8c78 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -243,6 +243,11 @@
<1 11 0xff01>,
<1 10 0xff01>;
};
+
+ pmu_system_controller: system-controller@105c {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x105c 0x5000>;
+ };
};
};
--
1.7.9.5
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[PATCH 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
"samsung,exynos7-clock-peric1",
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll",
"dout_aclk_peris_66" };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
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[PATCH v5 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Acked-by: Tomasz Figa Cc: Rob Herring Cc: Catalin Marinas Cc: Linus Walleij --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 56e5b7c..f9c42fa 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -155,6 +155,8 @@ config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 5/6] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add initial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..c7c41c1
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interr
[PATCH v5 4/6] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Ch
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 105
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 109 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index e8f8f16..fbeff99 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1164,3 +1164,108 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[]
__initconst = {
.eint_gpio_init = exynos_eint_gpio_init,
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init
[PATCH v5 3/6] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 45 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index f7ac9c7..e8f8f16 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static const struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -384,9 +378,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -400,6 +394,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -468,12 +487,18 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
struct exynos_muxed_weint_data *muxed_data;
+ struct exynos_irq_chip *irq_chip;
unsigned int muxed_banks = 0;
unsigned int i;
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ irq_chip = kmemdup(match->data,
+ sizeof(*irq_chip), GFP_KERNEL);
wkup_np = np;
break;
}
@@ -493,7 +518,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
[PATCH v5 2/6] pinctrl: exynos: Consolidate irq domain callbacks
Adding a irq_chip field to the samsung_pin_bank struct helps in
consolidating the irq domain callbacks for external gpio and wakeup
interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops
have now been merged into a single exynos_eint_irqd_ops.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 32 ++
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 0cca117..f7ac9c7 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -254,7 +254,7 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
};
-static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *b = h->host_data;
@@ -267,10 +267,10 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
}
/*
- * irq domain callbacks for external gpio interrupt controller.
+ * irq domain callbacks for external gpio and wakeup interrupt controllers.
*/
-static const struct irq_domain_ops exynos_gpio_irqd_ops = {
- .map= exynos_gpio_irq_map,
+static const struct irq_domain_ops exynos_eint_irqd_ops = {
+ .map= exynos_eint_irq_map,
.xlate = irq_domain_xlate_twocell,
};
@@ -329,7 +329,7 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_gpio_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
ret = -ENXIO;
@@ -456,26 +456,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- struct samsung_pin_bank *b = h->host_data;
-
- irq_set_chip_and_handler(virq, &b->irq_chip->chip,
- handle_level_irq);
- irq_set_chip_data(virq, h->host_data);
- set_irq_flags(virq, IRQF_VALID);
- return 0;
-}
-
-/*
- * irq domain callbacks for external wakeup interrupt controller.
- */
-static const struct irq_domain_ops exynos_wkup_irqd_ops = {
- .map= exynos_wkup_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
/*
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -507,7 +487,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_wkup_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
--
1.7.9.5
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[PATCH v5 1/6] pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure. This is done by adding a
irq_chip field to the samsung_pin_bank struct.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++
drivers/pinctrl/samsung/pinctrl-samsung.h |2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 6190106..0cca117 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
struct samsung_pin_bank *b = h->host_data;
irq_set_chip_data(virq, b);
- irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
return 0;
@@ -343,6 +343,8 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
ret = -ENOMEM;
goto err_domains;
}
+
+ bank->irq_chip = &exynos_gpio_irq_chip;
}
return 0;
@@ -444,9 +446,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
- pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
+ pend = readl(d->virt_base + b->irq_chip->eint_pend
+ b->eint_offset);
- mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
+ mask = readl(d->virt_base + b->irq_chip->eint_mask
+ b->eint_offset);
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
@@ -457,7 +459,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
+ struct samsung_pin_bank *b = h->host_data;
+
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
irq_set_chip_data(virq, h->host_data);
set_irq_flags(virq, IRQF_VALID);
@@ -509,6 +513,8 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
return -ENXIO;
}
+ bank->irq_chip = &exynos_wkup_irq_chip;
+
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
bank->eint_type = EINT_TYPE_WKUP_MUX;
++muxed_banks;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h
b/drivers/pinctrl/samsung/pinctrl-samsung.h
index ec43b7d..3076b8b 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -151,6 +151,7 @@ struct samsung_pin_bank_data {
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
+ * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
@@ -171,6 +172,7 @@ struct samsung_pin_bank {
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
+ struct exynos_irq_chip *irq_chip;
spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
--
1.7.9.5
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[PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Changes since v4: - Rebased over Tomasz Figa's pinctrl clean-up patches[1] Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham This series has been tested on linux-next (20141008) https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ with the following dependencies and [1]. a) Samsung Serial symbol clean-up for exynos7 serial driver enablement (v2) http://www.spinics.net/lists/arm-kernel/msg366947.html http://www.spinics.net/lists/arm-kernel/msg366948.html b) "dts, kbuild: Implement support for dtb vendor subdirs" patchset - rebased http://comments.gmane.org/gmane.linux.kbuild.devel/12131 c) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) - rebased http://www.spinics.net/lists/arm-kernel/msg364014.html [1] https://lkml.org/lkml/2014/10/2/476 Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 188 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 791 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Wed, Oct 8, 2014 at 3:52 PM, Linus Walleij wrote: > On Mon, Oct 6, 2014 at 5:42 AM, Abhilash Kesavan > wrote: >> On Tue, Sep 30, 2014 at 8:00 PM, Abhilash Kesavan >> wrote: >>> Changes since v3: >>> - Changed variable name from exynos_wkup_irq_chip to irq_chip >>> - Added acked-by tag from Tomasz Figa >>> >>> Changes since v2: >>> - Added a .irq_chip field to the samsung_pin_bank struct >>> - Consolidated the wakeup and gpio irqd_ops >>> >>> Changes since v1: >>> - Marked the newly created irq_chip instances as __initdata >>> - Used kmemdup to keep a copy of the irq_chip >>> - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM >>> - Moved the pinctrl enablement for exynos7 into a separate patch >>> - Added tested-by and reviewed-by tags from Thomas Abraham > > OK... > >> Does this series look OK to you ? > > I'm waiting for review comments form Tomasz Figa. Tomasz had ack'ed my v3 patchset (http://www.spinics.net/lists/linux-samsung-soc/msg37387.html). This version fixed the minor issues raised by Tomasz in v3 as well. > > I have just applied his 5 refactoring patches as the first base > for v3.19, I don't know if this stuff will fit nicely on top of these > or not, expect to find out during review. Tomasz patches have > priority since they have been in-flight for a while and he is listed > as maintainer for this driver. > > So could you make sure to get Tomasz review tag and make > sure that these patches work on top of his patches? His > patches are on my "devel" branch in the pin control tree, but > will not be pushed to linux-next until the merge window ends. I will re-base this series on your "devel" branch and post a new version after testing. Regards, Abhilash -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Hi Tomasz, On Tue, Oct 7, 2014 at 9:46 AM, Kukjin Kim wrote: > Tomasz Figa wrote: >> >> On 30.09.2014 17:12, Abhilash Kesavan wrote: >> > Hi Tomasz, >> > >> > On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa wrote: >> >> Hi Abhilash, >> >> >> >> On 22.09.2014 06:47, Abhilash Kesavan wrote: >> >>> Changes since v4: >> >>> - Fixed comments from Tomasz Figa: >> >>> - Changed the namespace prefix from exynos to samsung >> >>> - Defined bindings to take all input clocks >> >>> - Sorted the Kconfig entries alphabetically in clock Makefile >> >>> - Used consistent 1 tab line breaks across the clock file >> >>> - Statically initialized the samsung_cmu_info struct >> >>> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. >> >>> - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed >> >>> tags. >> >>> >> >> >> >> The clock patches look good to me, but since they are doing quite a lot >> >> of code moving I'd prefer to take them through clk tree. Based on the >> >> fact that there are no code dependencies between clock patches and >> >> remaining ones and Exynos7 is a new material for 3.18, I'm inclined to >> >> apply them to my tree if nobody minds. >> > >> > Will you be picking up the clock changes soon ? >> >> I'd like to do so. Kukjin, since clock changes are a part of this >> series, might I have your Ack for them to be applied separately? >> > Sure, I'm fine so please go ahead with my ack on the changes. > > Acked-by: Kukjin Kim > > Thanks for your asking. Can you please pick up the clock changes now that Kukjin has ack'ed it. Thanks, Abhilash > > - Kukjin > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Hi Arnd and Olof, On Tue, Sep 30, 2014 at 9:20 PM, Catalin Marinas wrote: > On Tue, Sep 30, 2014 at 04:15:21PM +0100, Abhilash Kesavan wrote: >> On Tue, Sep 23, 2014 at 2:18 PM, Abhilash Kesavan >> wrote: >> >>> This patchset supports the new Exynos7 Samsung SoC based on Cortex-A57. >> >>> Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC >> >>> processor. >> >>> >> >>> The following patches are tested based on linux-next tree (20140919). >> >>> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ >> >>> >> >>> Following patches are required for this series: >> >>> 1- "tty/serial: fix config dependencies for samsung serial" >> >>> >> >>> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html >> >>> 2- "dts, kbuild: Implement support for dtb vendor subdirs" patchset >> >>>http://comments.gmane.org/gmane.linux.kbuild.devel/12131 >> > >> > Thanks for your comments. I have mentioned Robert's patchset as being >> > a dependency for my series here. >> >> Do you have any comments on the arch and dts changes ? > > The arch changes look fine to me (not much in there, just Kconfig, > defconfig, Makefile). Regarding the dts, I'd like to see some acks from > the DT or arm-soc maintainers. > > BTW, the arch/arm64/ patches in your series should be merged via the > arm-soc tree (Arnd/Olof, cc'ing them now). Do you have any comments on this series ? Abhilash > > -- > Catalin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Tue, Sep 30, 2014 at 8:00 PM, Abhilash Kesavan wrote: > Changes since v3: > - Changed variable name from exynos_wkup_irq_chip to irq_chip > - Added acked-by tag from Tomasz Figa > > Changes since v2: > - Added a .irq_chip field to the samsung_pin_bank struct > - Consolidated the wakeup and gpio irqd_ops > > Changes since v1: > - Marked the newly created irq_chip instances as __initdata > - Used kmemdup to keep a copy of the irq_chip > - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM > - Moved the pinctrl enablement for exynos7 into a separate patch > - Added tested-by and reviewed-by tags from Thomas Abraham > > Following patches have been tested on linux-next (20140926). > https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ > > Following patches are required for this series: > 1) "tty/serial: fix config dependencies for samsung serial" > > https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html > 2) "dts, kbuild: Implement support for dtb vendor subdirs" patchset >http://comments.gmane.org/gmane.linux.kbuild.devel/12131 > 3) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) >http://www.spinics.net/lists/arm-kernel/msg364014.html > > Abhilash Kesavan (3): > pinctrl: exynos: Generalize the eint16_31 demux code > pinctrl: exynos: Consolidate irq domain callbacks > pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts > > Naveen Krishna Ch (3): > pinctrl: exynos: Add initial driver data for Exynos7 > arm64: dts: Add initial pinctrl support to EXYNOS7 > arm64: exynos: Enable pinctrl support for Exynos7 > > .../bindings/pinctrl/samsung-pinctrl.txt |3 + > arch/arm64/Kconfig |2 + > arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 > > arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- > drivers/pinctrl/samsung/pinctrl-exynos.h |3 + > drivers/pinctrl/samsung/pinctrl-samsung.c |2 + > drivers/pinctrl/samsung/pinctrl-samsung.h |3 + > 8 files changed, 799 insertions(+), 36 deletions(-) > create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi Does this series look OK to you ? Regards, Abhilash > > -- > 1.7.9.5 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Hi Catalin, On Tue, Sep 23, 2014 at 2:18 PM, Abhilash Kesavan wrote: > Hi Chanho, > > On Tue, Sep 23, 2014 at 1:20 PM, Chanho Park > wrote: >> Hi, >> >>> -Original Message- >>> From: linux-arm-kernel [mailto:linux-arm-kernel- >>> boun...@lists.infradead.org] On Behalf Of Abhilash Kesavan >>> Sent: Monday, September 22, 2014 1:47 PM >>> To: linux-samsung-...@vger.kernel.org; linux-arm- >>> ker...@lists.infradead.org; devicetree@vger.kernel.org; >>> catalin.mari...@arm.com >>> Cc: naveenkrishna...@gmail.com; kesavan.abhil...@gmail.com; >>> tomasz.f...@gmail.com >>> Subject: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 >>> SoC >>> >>> Changes since v4: >>> - Fixed comments from Tomasz Figa: >>> - Changed the namespace prefix from exynos to samsung >>> - Defined bindings to take all input clocks >>> - Sorted the Kconfig entries alphabetically in clock Makefile >>> - Used consistent 1 tab line breaks across the clock file >>> - Statically initialized the samsung_cmu_info struct >>> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. >>> - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed >>> tags. >>> >>> Changes since v3: >>> - Removed aliases for serial controllers from dtsi file and moved it >>> into board specific dts file as suggested by Arnd. >>> - Based this series on Robert Richter's patches for adding vendor >>> device tree sub-directories for arm64. >>> http://comments.gmane.org/gmane.linux.kbuild.devel/12131 >>> >>> This patchset supports the new Exynos7 Samsung SoC based on Cortex-A57. >>> Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC >>> processor. >>> >>> The following patches are tested based on linux-next tree (20140919). >>> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ >>> >>> Following patches are required for this series: >>> 1- "tty/serial: fix config dependencies for samsung serial" >>>https://www.mail-archive.com/linux-samsung-soc >>> vger.kernel.org/msg36208.html >>> 2- "dts, kbuild: Implement support for dtb vendor subdirs" patchset >>>http://comments.gmane.org/gmane.linux.kbuild.devel/12131 > > Thanks for your comments. I have mentioned Robert's patchset as being > a dependency for my series here. Do you have any comments on the arch and dts changes ? Regards, Abhilash > > Regards, > Abhilash > >> >> Maybe you make this patch on top of the Robert's patch. >> As I know, Robert's patch is not yet merged in mainline. >> You should specify this dependency in mail thread. >> >> [1]: https://lkml.org/lkml/2014/9/5/64 >> >> Best Regards, >> Chanho Park >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Hi Tomasz, On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa wrote: > Hi Abhilash, > > On 22.09.2014 06:47, Abhilash Kesavan wrote: >> Changes since v4: >> - Fixed comments from Tomasz Figa: >> - Changed the namespace prefix from exynos to samsung >> - Defined bindings to take all input clocks >> - Sorted the Kconfig entries alphabetically in clock Makefile >> - Used consistent 1 tab line breaks across the clock file >> - Statically initialized the samsung_cmu_info struct >> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. >> - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed >> tags. >> > > The clock patches look good to me, but since they are doing quite a lot > of code moving I'd prefer to take them through clk tree. Based on the > fact that there are no code dependencies between clock patches and > remaining ones and Exynos7 is a new material for 3.18, I'm inclined to > apply them to my tree if nobody minds. Will you be picking up the clock changes soon ? Regards, Abhilash > > Best regards, > Tomasz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 5/6] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..c7c41c1
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interr
[PATCH v4 0/6] Add initial support for pinctrl on Exynos7
Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Acked-by: Tomasz Figa Cc: Rob Herring Cc: Catalin Marinas Cc: Linus Walleij --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5285f9c..e8ddd84 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -145,6 +145,8 @@ config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/6] pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure. This is done by adding a
irq_chip field to the samsung_pin_bank struct.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++
drivers/pinctrl/samsung/pinctrl-samsung.h |2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed..14b9b44 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
struct samsung_pin_bank *b = h->host_data;
irq_set_chip_data(virq, b);
- irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
return 0;
@@ -344,6 +344,8 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
ret = -ENOMEM;
goto err_domains;
}
+
+ bank->irq_chip = &exynos_gpio_irq_chip;
}
return 0;
@@ -445,9 +447,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
- pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
+ pend = readl(d->virt_base + b->irq_chip->eint_pend
+ b->eint_offset);
- mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
+ mask = readl(d->virt_base + b->irq_chip->eint_mask
+ b->eint_offset);
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
@@ -458,7 +460,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
+ struct samsung_pin_bank *b = h->host_data;
+
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
irq_set_chip_data(virq, h->host_data);
set_irq_flags(virq, IRQF_VALID);
@@ -510,6 +514,8 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
return -ENXIO;
}
+ bank->irq_chip = &exynos_wkup_irq_chip;
+
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
bank->eint_type = EINT_TYPE_WKUP_MUX;
++muxed_banks;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h
b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 5cedc9d..d2c38c8 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -127,6 +127,7 @@ struct samsung_pin_bank_type {
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
+ * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
@@ -146,6 +147,7 @@ struct samsung_pin_bank {
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
+ struct exynos_irq_chip *irq_chip;
spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
--
1.7.9.5
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[PATCH v4 3/6] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 45 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 54ebcb6..771e821 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -385,9 +379,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -401,6 +395,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -469,12 +488,18 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
struct exynos_muxed_weint_data *muxed_data;
+ struct exynos_irq_chip *irq_chip;
unsigned int muxed_banks = 0;
unsigned int i;
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ irq_chip = kmemdup(match->data,
+ sizeof(*irq_chip), GFP_KERNEL);
wkup_np = np;
break;
}
@@ -494,7 +519,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
[PATCH v4 4/6] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Ch
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 113
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 771e821..bd2fd9b 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1189,3 +1189,116 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = "exynos5420-gpio-ctrl4",
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static struct samsung_pin_bank exynos7_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+struct samsung_pin_ctrl exynos7_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos7-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 BUS0 data */
+ .pin_banks = exynos7_
[PATCH v4 2/6] pinctrl: exynos: Consolidate irq domain callbacks
Adding a irq_chip field to the samsung_pin_bank struct helps in
consolidating the irq domain callbacks for external gpio and wakeup
interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops
have now been merged into a single exynos_eint_irqd_ops.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 32 ++
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 14b9b44..54ebcb6 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -254,7 +254,7 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
};
-static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *b = h->host_data;
@@ -267,10 +267,10 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
}
/*
- * irq domain callbacks for external gpio interrupt controller.
+ * irq domain callbacks for external gpio and wakeup interrupt controllers.
*/
-static const struct irq_domain_ops exynos_gpio_irqd_ops = {
- .map= exynos_gpio_irq_map,
+static const struct irq_domain_ops exynos_eint_irqd_ops = {
+ .map= exynos_eint_irq_map,
.xlate = irq_domain_xlate_twocell,
};
@@ -330,7 +330,7 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_gpio_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
ret = -ENXIO;
@@ -457,26 +457,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- struct samsung_pin_bank *b = h->host_data;
-
- irq_set_chip_and_handler(virq, &b->irq_chip->chip,
- handle_level_irq);
- irq_set_chip_data(virq, h->host_data);
- set_irq_flags(virq, IRQF_VALID);
- return 0;
-}
-
-/*
- * irq domain callbacks for external wakeup interrupt controller.
- */
-static const struct irq_domain_ops exynos_wkup_irqd_ops = {
- .map= exynos_wkup_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
/*
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -508,7 +488,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_wkup_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
--
1.7.9.5
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Re: [PATCH v3 3/6] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Tomasz,
On Tue, Sep 30, 2014 at 4:16 AM, Tomasz Figa wrote:
> Hi Abhilash,
>
> Just two minor issues inline. I leave them up to Linus to decide.
>
> Linus, if you don't mind them, feel free to apply this patch with my Ack.
>
> On 29.09.2014 07:15, Abhilash Kesavan wrote:
>> Exynos7 uses different offsets for wakeup interrupt configuration registers.
>> So a new irq_chip instance for Exynos7 wakeup interrupts is added. The
>> irq_chip
>> selection is now based on the wakeup interrupt controller compatible string.
>
> [snip]
>
>> @@ -469,12 +488,18 @@ static int exynos_eint_wkup_init(struct
>> samsung_pinctrl_drv_data *d)
>> struct samsung_pin_bank *bank;
>> struct exynos_weint_data *weint_data;
>> struct exynos_muxed_weint_data *muxed_data;
>> + struct exynos_irq_chip *exynos_wkup_irq_chip;
>
> Quite an awful name for a local variable. "irq_chip" alone would be enough.
>
>> unsigned int muxed_banks = 0;
>> unsigned int i;
>> int idx, irq;
>>
>> for_each_child_of_node(dev->of_node, np) {
>> - if (of_match_node(exynos_wkup_irq_ids, np)) {
>> + const struct of_device_id *match;
>> +
>> + match = of_match_node(exynos_wkup_irq_ids, np);
>> + if (match) {
>> + exynos_wkup_irq_chip = kmemdup(match->data,
>> + sizeof(struct exynos_irq_chip), GFP_KERNEL);
>
> sizeof(*exynos_wkup_irq_chip) (or irq_chip considering my comment above)
> could be used instead.
Thanks for the acks. Will post a new version with these nits fixed.
>
> Best regards,
> Tomasz
>
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Re: [PATCH v2 2/5] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Tomasz,
On Tue, Sep 23, 2014 at 8:19 PM, Tomasz Figa wrote:
> On 23.09.2014 10:16, Abhilash Kesavan wrote:
> [snip]
>> @@ -383,9 +377,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
>> *irqd, unsigned int on)
>> /*
>> * irq_chip for wakeup interrupts
>> */
>> -static struct exynos_irq_chip exynos_wkup_irq_chip = {
>> +static struct exynos_irq_chip *exynos_wkup_irq_chip;
>> +
> [snip]
>> @@ -459,7 +480,7 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
>> struct irq_desc *desc)
>> static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
>> irq_hw_number_t hw)
>> {
>> - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
>> + irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip->chip,
>> handle_level_irq);
>> irq_set_chip_data(virq, h->host_data);
>> set_irq_flags(virq, IRQF_VALID);
>> @@ -491,7 +512,12 @@ static int exynos_eint_wkup_init(struct
>> samsung_pinctrl_drv_data *d)
>> int idx, irq;
>>
>> for_each_child_of_node(dev->of_node, np) {
>> - if (of_match_node(exynos_wkup_irq_ids, np)) {
>> + const struct of_device_id *match;
>> +
>> + match = of_match_node(exynos_wkup_irq_ids, np);
>> + if (match) {
>> + exynos_wkup_irq_chip = kmemdup(match->data,
>> + sizeof(struct exynos_irq_chip), GFP_KERNEL);
>
> That's not exactly what I had in my mind.
>
> You just changed the code to write to another global variable. This is
> not the best practice and might cause hard to track issues in future,
> when extending the driver.
>
> From what I can see, the best solution would be to add .irq_chip field
> to samsung_pin_bank struct. Then exynos_wkup_irq_map() could access it
> through h->host_data pointer and exynos_irq_demux_eint16_31() could also
> retrieve the irq chip through bank struct without the need too add chip
> field to exynos_muxed_weint_data struct.
>
> As a side effect, it would be possible to consolidate
> exynos_wkup_irqd_ops with exynos_gpio_irqd_ops, which currently only
> differ in irq chip passed as argument to irq_set_chip_and_handler() in
> .map() callback.
I have posted v3 adding a new irq_chip field to the samsung_pin_bank
structure as per your suggestion. Please take a look.
Regards,
Abhilash
>
> Best regards,
> Tomasz
>
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[PATCH v3 2/6] pinctrl: exynos: Consolidate irq domain callbacks
Adding a irq_chip field to the samsung_pin_bank struct helps in
consolidating the irq domain callbacks for external gpio and wakeup
interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops
have now been merged into a single exynos_eint_irqd_ops.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 32 ++
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 14b9b44..54ebcb6 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -254,7 +254,7 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
};
-static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct samsung_pin_bank *b = h->host_data;
@@ -267,10 +267,10 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
}
/*
- * irq domain callbacks for external gpio interrupt controller.
+ * irq domain callbacks for external gpio and wakeup interrupt controllers.
*/
-static const struct irq_domain_ops exynos_gpio_irqd_ops = {
- .map= exynos_gpio_irq_map,
+static const struct irq_domain_ops exynos_eint_irqd_ops = {
+ .map= exynos_eint_irq_map,
.xlate = irq_domain_xlate_twocell,
};
@@ -330,7 +330,7 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_gpio_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "gpio irq domain add failed\n");
ret = -ENXIO;
@@ -457,26 +457,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- struct samsung_pin_bank *b = h->host_data;
-
- irq_set_chip_and_handler(virq, &b->irq_chip->chip,
- handle_level_irq);
- irq_set_chip_data(virq, h->host_data);
- set_irq_flags(virq, IRQF_VALID);
- return 0;
-}
-
-/*
- * irq domain callbacks for external wakeup interrupt controller.
- */
-static const struct irq_domain_ops exynos_wkup_irqd_ops = {
- .map= exynos_wkup_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
/*
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -508,7 +488,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
continue;
bank->irq_domain = irq_domain_add_linear(bank->of_node,
- bank->nr_pins, &exynos_wkup_irqd_ops, bank);
+ bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
return -ENXIO;
--
1.7.9.5
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[PATCH v3 3/6] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 45 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 54ebcb6..4ec2d3d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -385,9 +379,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -401,6 +395,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -469,12 +488,18 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
struct exynos_muxed_weint_data *muxed_data;
+ struct exynos_irq_chip *exynos_wkup_irq_chip;
unsigned int muxed_banks = 0;
unsigned int i;
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ exynos_wkup_irq_chip = kmemdup(match->data,
+ sizeof(struct exynos_irq_chip), GFP_KERNEL);
wkup_np = np;
break;
}
@@ -494,7 +519,7 @@ static int exynos_eint_wkup_init(
[PATCH v3 5/6] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Tomasz Figa
Cc: Linus Walleij
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..c7c41c1
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-c
[PATCH v3 4/6] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Ch
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 113
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 4ec2d3d..29e6070 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1189,3 +1189,116 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = "exynos5420-gpio-ctrl4",
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static struct samsung_pin_bank exynos7_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+struct samsung_pin_ctrl exynos7_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos7-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 BUS0 data */
+ .pin_banks = exynos7_
[PATCH v3 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas Cc: Tomasz Figa Cc: Linus Walleij --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1874e1a..4ee1250 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,8 @@ config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/6] pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure. This is done by adding a
irq_chip field to the samsung_pin_bank struct.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++
drivers/pinctrl/samsung/pinctrl-samsung.h |2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed..14b9b44 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h,
unsigned int virq,
struct samsung_pin_bank *b = h->host_data;
irq_set_chip_data(virq, b);
- irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
return 0;
@@ -344,6 +344,8 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
ret = -ENOMEM;
goto err_domains;
}
+
+ bank->irq_chip = &exynos_gpio_irq_chip;
}
return 0;
@@ -445,9 +447,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
- pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
+ pend = readl(d->virt_base + b->irq_chip->eint_pend
+ b->eint_offset);
- mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
+ mask = readl(d->virt_base + b->irq_chip->eint_mask
+ b->eint_offset);
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
@@ -458,7 +460,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
+ struct samsung_pin_bank *b = h->host_data;
+
+ irq_set_chip_and_handler(virq, &b->irq_chip->chip,
handle_level_irq);
irq_set_chip_data(virq, h->host_data);
set_irq_flags(virq, IRQF_VALID);
@@ -510,6 +514,8 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
return -ENXIO;
}
+ bank->irq_chip = &exynos_wkup_irq_chip;
+
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
bank->eint_type = EINT_TYPE_WKUP_MUX;
++muxed_banks;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h
b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 5cedc9d..d2c38c8 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -127,6 +127,7 @@ struct samsung_pin_bank_type {
* @irq_domain: IRQ domain of the bank.
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
+ * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
* @slock: spinlock protecting bank registers
* @pm_save: saved register values during suspend
*/
@@ -146,6 +147,7 @@ struct samsung_pin_bank {
struct irq_domain *irq_domain;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
+ struct exynos_irq_chip *irq_chip;
spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
--
1.7.9.5
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[PATCH v3 0/6] Add initial support for pinctrl on Exynos7
Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 8/8] arm64: dts: add symlink
Hi Chanho,
On Tue, Sep 23, 2014 at 1:16 PM, Chanho Park wrote:
> Hi,
>
>> -Original Message-
>> From: linux-arm-kernel [mailto:linux-arm-kernel-
>> boun...@lists.infradead.org] On Behalf Of Abhilash Kesavan
>> Sent: Monday, September 22, 2014 1:47 PM
>> To: linux-samsung-...@vger.kernel.org; linux-arm-
>> ker...@lists.infradead.org; devicetree@vger.kernel.org;
>> catalin.mari...@arm.com
>> Cc: naveenkrishna...@gmail.com; kesavan.abhil...@gmail.com;
>> tomasz.f...@gmail.com
>> Subject: [PATCH v5 8/8] arm64: dts: add symlink
>>
>> From: Pankaj Dubey
>>
>> Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
>> match the ones in ARM architectures so that preprocessed device
>> tree files can include various useful constant definitions.
>>
>> See commit c58299aa8754 ("kbuild: create an "include chroot" for DT
>> bindings")
>> merged in v3.10-rc1 for details.
>>
>> CC: Catalin Marinas
>> Signed-off-by: Pankaj Dubey
>> Signed-off-by: Abhilash Kesavan
>> Reviewed-by: Thomas Abraham
>> Tested-by: Thomas Abraham
>> ---
>> arch/arm64/boot/dts/include/dt-bindings | 1 +
>> 1 file changed, 1 insertion(+)
>> create mode 12 arch/arm64/boot/dts/include/dt-bindings
>>
>> diff --git a/arch/arm64/boot/dts/include/dt-bindings
>> b/arch/arm64/boot/dts/include/dt-bindings
>> new file mode 12
>> index 000..1e89bce
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/include/dt-bindings
>> @@ -0,0 +1 @@
>> +../../../../../include/dt-bindings/
>> \ No newline at end of file
> ^
> It generates incorrect symlink. Please remove last line like below:
>
> diff --git a/arch/arm64/boot/dts/include/dt-bindings
> b/arch/arm64/boot/dts/include/dt-bindings
> new file mode 12
> index 000..499472b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../../include/dt-bindings/
I just re-checked this patch and it seems to be working fine. I did
find a thread where patchwork appeared to be changing the patch
causing issues [1]. Are you downloading this via patchwork ?
[1] http://www.spinics.net/lists/linux-kbuild/msg08656.html
Regards,
Abhilash
> --
>
> Best Regards,
> Chanho Park
>
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Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Hi Chanho, On Tue, Sep 23, 2014 at 1:20 PM, Chanho Park wrote: > Hi, > >> -Original Message- >> From: linux-arm-kernel [mailto:linux-arm-kernel- >> boun...@lists.infradead.org] On Behalf Of Abhilash Kesavan >> Sent: Monday, September 22, 2014 1:47 PM >> To: linux-samsung-...@vger.kernel.org; linux-arm- >> ker...@lists.infradead.org; devicetree@vger.kernel.org; >> catalin.mari...@arm.com >> Cc: naveenkrishna...@gmail.com; kesavan.abhil...@gmail.com; >> tomasz.f...@gmail.com >> Subject: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 >> SoC >> >> Changes since v4: >> - Fixed comments from Tomasz Figa: >> - Changed the namespace prefix from exynos to samsung >> - Defined bindings to take all input clocks >> - Sorted the Kconfig entries alphabetically in clock Makefile >> - Used consistent 1 tab line breaks across the clock file >> - Statically initialized the samsung_cmu_info struct >> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. >> - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed >> tags. >> >> Changes since v3: >> - Removed aliases for serial controllers from dtsi file and moved it >> into board specific dts file as suggested by Arnd. >> - Based this series on Robert Richter's patches for adding vendor >> device tree sub-directories for arm64. >> http://comments.gmane.org/gmane.linux.kbuild.devel/12131 >> >> This patchset supports the new Exynos7 Samsung SoC based on Cortex-A57. >> Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC >> processor. >> >> The following patches are tested based on linux-next tree (20140919). >> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ >> >> Following patches are required for this series: >> 1- "tty/serial: fix config dependencies for samsung serial" >>https://www.mail-archive.com/linux-samsung-soc >> vger.kernel.org/msg36208.html >> 2- "dts, kbuild: Implement support for dtb vendor subdirs" patchset >>http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Thanks for your comments. I have mentioned Robert's patchset as being a dependency for my series here. Regards, Abhilash > > Maybe you make this patch on top of the Robert's patch. > As I know, Robert's patch is not yet merged in mainline. > You should specify this dependency in mail thread. > > [1]: https://lkml.org/lkml/2014/9/5/64 > > Best Regards, > Chanho Park > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/5] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 48 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index b5e1cd4..7072bfa 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -383,9 +377,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip *exynos_wkup_irq_chip;
+
+static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -399,6 +395,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -459,7 +480,7 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
+ irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip->chip,
handle_level_irq);
irq_set_chip_data(virq, h->host_data);
set_irq_flags(virq, IRQF_VALID);
@@ -491,7 +512,12 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+
[PATCH v2 0/5] Add initial support for pinctrl on Exynos7
Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140922). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) "arch: arm64: enable support for Samsung Exynos7 SoC" patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/5] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas Cc: Tomasz Figa Cc: Linus Walleij Cc: Thomas Abraham --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1874e1a..4ee1250 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,8 @@ config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/5] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Ch
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 113
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 7072bfa..25ca8e8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1206,3 +1206,116 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = "exynos5420-gpio-ctrl4",
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static struct samsung_pin_bank exynos7_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+struct samsung_pin_ctrl exynos7_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos7-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 BUS0 data */
+
[PATCH v2 1/5] pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which have these registers at different offsets. So generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure.
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c |6 --
drivers/pinctrl/samsung/pinctrl-exynos.h |1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed..b5e1cd4 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -444,10 +444,11 @@ static void exynos_irq_demux_eint16_31(unsigned int irq,
struct irq_desc *desc)
chained_irq_enter(chip, desc);
for (i = 0; i < eintd->nr_banks; ++i) {
+ struct exynos_irq_chip *our_chip = eintd->chip;
struct samsung_pin_bank *b = eintd->banks[i];
- pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
+ pend = readl(d->virt_base + our_chip->eint_pend
+ b->eint_offset);
- mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
+ mask = readl(d->virt_base + our_chip->eint_mask
+ b->eint_offset);
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
@@ -565,6 +566,7 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
muxed_data->banks[idx++] = bank;
}
muxed_data->nr_banks = muxed_banks;
+ muxed_data->chip = &exynos_wkup_irq_chip;
return 0;
}
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h
b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 3c91c35..e060722 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -94,6 +94,7 @@ struct exynos_weint_data {
* @banks: array of banks being part of the mux
*/
struct exynos_muxed_weint_data {
+ struct exynos_irq_chip *chip;
unsigned int nr_banks;
struct samsung_pin_bank *banks[];
};
--
1.7.9.5
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[PATCH v2 4/5] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Ch
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Tomasz Figa
Cc: Linus Walleij
Cc: Thomas Abraham
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..c7c41c1
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd7: gpd7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd8: gpd8 {
+ gpio-controller;
+ #gpio-cells = <2&
Re: [PATCH 2/4] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Tomasz,
On Mon, Sep 22, 2014 at 1:25 PM, Tomasz Figa wrote:
> On 22.09.2014 08:17, Abhilash Kesavan wrote:
>> Hi Tomasz,
>>
>> On Sat, Sep 13, 2014 at 4:57 PM, Tomasz Figa wrote:
>>> Hi Abhilash,
>>>
>>> Please see my comments inline.
>>>
>>> On 13.09.2014 10:50, Abhilash Kesavan wrote:
>>>> Exynos7 uses different offsets for wakeup interrupt configuration
>>>> registers.
>>>> So a new irq_chip instance for Exynos7 wakeup interrupts is added. The
>>>> irq_chip
>>>> selection is now based on the wakeup interrupt controller compatible
>>>> string.
>>>
>>> [snip]
>>>
>>>> @@ -328,9 +322,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
>>>> *irqd, unsigned int on)
>>>> /*
>>>> * irq_chip for wakeup interrupts
>>>> */
>>>> -static struct exynos_irq_chip exynos_wkup_irq_chip = {
>>>> +static struct exynos_irq_chip exynos_wkup_irq_chip;
>>>> +
>>>
>>> Why do you still need this, if you have both variants below?
>>
>> After adding __initdata to the two variants, I will require to have a
>> copy of one of them.
>>
>>>
>>>> +static struct exynos_irq_chip exynos4210_wkup_irq_chip = {
>>>> .chip = {
>>>> - .name = "exynos_wkup_irq_chip",
>>>> + .name = "exynos4210_wkup_irq_chip",
>>>> .irq_unmask = exynos_irq_unmask,
>>>> .irq_mask = exynos_irq_mask,
>>>> .irq_ack = exynos_irq_ack,
>>>> @@ -342,6 +338,29 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
>>>> .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
>>>> };
>>>>
>>>> +static struct exynos_irq_chip exynos7_wkup_irq_chip = {
>>>> + .chip = {
>>>> + .name = "exynos7_wkup_irq_chip",
>>>> + .irq_unmask = exynos_irq_unmask,
>>>> + .irq_mask = exynos_irq_mask,
>>>> + .irq_ack = exynos_irq_ack,
>>>> + .irq_set_type = exynos_irq_set_type,
>>>> + .irq_set_wake = exynos_wkup_irq_set_wake,
>>>> + },
>>>> + .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
>>>> + .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
>>>> + .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
>>>> +};
>>>> +
>>>> +/* list of external wakeup controllers supported */
>>>> +static const struct of_device_id exynos_wkup_irq_ids[] = {
>>>> + { .compatible = "samsung,exynos4210-wakeup-eint",
>>>> + .data = &exynos4210_wkup_irq_chip },
>>>> + { .compatible = "samsung,exynos7-wakeup-eint",
>>>> + .data = &exynos7_wkup_irq_chip },
>>>> + { }
>>>> +};
>>>> +
>>>> /* interrupt handler for wakeup interrupts 0..15 */
>>>> static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>>>> {
>>>> @@ -434,7 +453,12 @@ static int exynos_eint_wkup_init(struct
>>>> samsung_pinctrl_drv_data *d)
>>>> int idx, irq;
>>>>
>>>> for_each_child_of_node(dev->of_node, np) {
>>>> - if (of_match_node(exynos_wkup_irq_ids, np)) {
>>>> + const struct of_device_id *match;
>>>> +
>>>> + match = of_match_node(exynos_wkup_irq_ids, np);
>>>> + if (match) {
>>>> + memcpy(&exynos_wkup_irq_chip, match->data,
>>>> + sizeof(struct exynos_irq_chip));
>>>
>>> Hmm, this doesn't look correct to me. You are modifying a static struct
>>> here. Why couldn't you simply use the exynos irq chip pointed by
>>> match->data in further registration code?
>>
>> That will not be available later once I use __initdata.
>>
>
> Then either __initdata shouldn't be necessary or kmemdup() should be
> used to allocate a copy.
Will fix this and send out a new version soon.
Regards,
Abhilash
>
>>>
>>>> wkup_np = np;
>>>> break;
>>>> }
>>>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h
>>>> b/drivers/pinctrl/samsung/pinctrl-exynos.h
>>>> index e060722..0db1
Re: [PATCH 2/4] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:57 PM, Tomasz Figa wrote:
> Hi Abhilash,
>
> Please see my comments inline.
>
> On 13.09.2014 10:50, Abhilash Kesavan wrote:
>> Exynos7 uses different offsets for wakeup interrupt configuration registers.
>> So a new irq_chip instance for Exynos7 wakeup interrupts is added. The
>> irq_chip
>> selection is now based on the wakeup interrupt controller compatible string.
>
> [snip]
>
>> @@ -328,9 +322,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
>> *irqd, unsigned int on)
>> /*
>> * irq_chip for wakeup interrupts
>> */
>> -static struct exynos_irq_chip exynos_wkup_irq_chip = {
>> +static struct exynos_irq_chip exynos_wkup_irq_chip;
>> +
>
> Why do you still need this, if you have both variants below?
After adding __initdata to the two variants, I will require to have a
copy of one of them.
>
>> +static struct exynos_irq_chip exynos4210_wkup_irq_chip = {
>> .chip = {
>> - .name = "exynos_wkup_irq_chip",
>> + .name = "exynos4210_wkup_irq_chip",
>> .irq_unmask = exynos_irq_unmask,
>> .irq_mask = exynos_irq_mask,
>> .irq_ack = exynos_irq_ack,
>> @@ -342,6 +338,29 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
>> .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
>> };
>>
>> +static struct exynos_irq_chip exynos7_wkup_irq_chip = {
>> + .chip = {
>> + .name = "exynos7_wkup_irq_chip",
>> + .irq_unmask = exynos_irq_unmask,
>> + .irq_mask = exynos_irq_mask,
>> + .irq_ack = exynos_irq_ack,
>> + .irq_set_type = exynos_irq_set_type,
>> + .irq_set_wake = exynos_wkup_irq_set_wake,
>> + },
>> + .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
>> + .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
>> + .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
>> +};
>> +
>> +/* list of external wakeup controllers supported */
>> +static const struct of_device_id exynos_wkup_irq_ids[] = {
>> + { .compatible = "samsung,exynos4210-wakeup-eint",
>> + .data = &exynos4210_wkup_irq_chip },
>> + { .compatible = "samsung,exynos7-wakeup-eint",
>> + .data = &exynos7_wkup_irq_chip },
>> + { }
>> +};
>> +
>> /* interrupt handler for wakeup interrupts 0..15 */
>> static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>> {
>> @@ -434,7 +453,12 @@ static int exynos_eint_wkup_init(struct
>> samsung_pinctrl_drv_data *d)
>> int idx, irq;
>>
>> for_each_child_of_node(dev->of_node, np) {
>> - if (of_match_node(exynos_wkup_irq_ids, np)) {
>> + const struct of_device_id *match;
>> +
>> + match = of_match_node(exynos_wkup_irq_ids, np);
>> + if (match) {
>> + memcpy(&exynos_wkup_irq_chip, match->data,
>> + sizeof(struct exynos_irq_chip));
>
> Hmm, this doesn't look correct to me. You are modifying a static struct
> here. Why couldn't you simply use the exynos irq chip pointed by
> match->data in further registration code?
That will not be available later once I use __initdata.
>
>> wkup_np = np;
>> break;
>> }
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h
>> b/drivers/pinctrl/samsung/pinctrl-exynos.h
>> index e060722..0db1e52 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
>> @@ -25,6 +25,9 @@
>> #define EXYNOS_WKUP_ECON_OFFSET 0xE00
>> #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
>> #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
>> +#define EXYNOS7_WKUP_ECON_OFFSET 0x700
>> +#define EXYNOS7_WKUP_EMASK_OFFSET0x900
>> +#define EXYNOS7_WKUP_EPEND_OFFSET0xA00
>
> Interestingly enough, the offsets look just like the normal GPIO
> interrupt controller of previous Exynos SoCs. Are you sure those are
> correct? Also if somehow the controller now resembles the normal one,
> doesn't it have the SVC register making it possible to reuse the non
> wake-up code instead?
The wakeup interrupt register offsets are the same as the GPIO
interrupt offsets in earlier Exynos SoCs. There is no SVC register for
the wakeup interrupt block.
Regards,
Abhilash
>
> Best regards,
> Tomasz
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[PATCH v5 8/8] arm64: dts: add symlink
From: Pankaj Dubey
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings")
merged in v3.10-rc1 for details.
CC: Catalin Marinas
Signed-off-by: Pankaj Dubey
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
---
arch/arm64/boot/dts/include/dt-bindings | 1 +
1 file changed, 1 insertion(+)
create mode 12 arch/arm64/boot/dts/include/dt-bindings
diff --git a/arch/arm64/boot/dts/include/dt-bindings
b/arch/arm64/boot/dts/include/dt-bindings
new file mode 12
index 000..1e89bce
--- /dev/null
+++ b/arch/arm64/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings/
\ No newline at end of file
--
2.1.0
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[PATCH v5 7/8] arm64: Enable Exynos7 SOC in the defconfig
From: Alim Akhtar Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC. Signed-off-by: Alim Akhtar Signed-off-by: Abhilash Kesavan --- arch/arm64/configs/defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d92ef3c..f6db9b2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y CONFIG_SMP=y @@ -82,6 +84,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 2/8] clk: samsung: Factor out the common code to clk.c
From: Naveen Krishna Ch
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Mike Turquette
---
drivers/clk/samsung/clk-exynos5260.c | 185 +--
drivers/clk/samsung/clk.c| 95 ++
drivers/clk/samsung/clk.h| 34 +++
3 files changed, 155 insertions(+), 159 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97..64aeadf 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -11,10 +11,8 @@
#include
#include
-#include
#include
#include
-#include
#include "clk-exynos5260.h"
#include "clk.h"
@@ -22,39 +20,6 @@
#include
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
- struct list_head node;
- void __iomem *reg_base;
- struct samsung_clk_reg_dump *rdump;
- unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
- /* list of pll clocks and respective count */
- struct samsung_pll_clock *pll_clks;
- unsigned int nr_pll_clks;
- /* list of mux clocks and respective count */
- struct samsung_mux_clock *mux_clks;
- unsigned int nr_mux_clks;
- /* list of div clocks and respective count */
- struct samsung_div_clock *div_clks;
- unsigned int nr_div_clks;
- /* list of gate clocks and respective count */
- struct samsung_gate_clock *gate_clks;
- unsigned int nr_gate_clks;
- /* list of fixed clocks and respective count */
- struct samsung_fixed_rate_clock *fixed_clks;
- unsigned int nr_fixed_clks;
- /* total number of clocks with IDs assigned*/
- unsigned int nr_clk_ids;
-
- /* list and number of clocks registers */
- unsigned long *clk_regs;
- unsigned int nr_clk_regs;
-};
-
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[]
__initdata = {
PLL_36XX_RATE(6600, 176, 2, 5, 0),
};
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, &clock_reg_cache_list, node)
- samsung_clk_save(cache->reg_base, cache->rdump,
- cache->rd_num);
-
- return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, &clock_reg_cache_list, node)
- samsung_clk_restore(cache->reg_base, cache->rdump,
- cache->rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
- .suspend = exynos5260_clk_suspend,
- .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump)
-{
- struct exynos5260_clock_reg_cache *reg_cache;
-
- reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
- GFP_KERNEL);
- if (!reg_cache)
- panic("could not allocate register cache.\n");
-
- reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
- if (!reg_cache->rdump)
- panic("could not allocate register dump storage.\n");
-
- if (list_empty(&clock_reg_cache_list))
- register_syscore_ops(&exynos5260_clk_syscore_ops);
-
- reg_cache->rd_num = nr_rdump;
- reg_cache->reg_base = reg_base;
- list_add_tail(®_cache->node, &clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
- struct exynos5260_cmu_info *cmu)
-{
- void __iomem *reg_base;
- struct samsung_clk_provider *ctx;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic("%s: failed to map registers\n", __func__);
-
- ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
-
[PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Changes since v4: - Fixed comments from Tomasz Figa: - Changed the namespace prefix from exynos to samsung - Defined bindings to take all input clocks - Sorted the Kconfig entries alphabetically in clock Makefile - Used consistent 1 tab line breaks across the clock file - Statically initialized the samsung_cmu_info struct - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags. Changes since v3: - Removed aliases for serial controllers from dtsi file and moved it into board specific dts file as suggested by Arnd. - Based this series on Robert Richter's patches for adding vendor device tree sub-directories for arm64. http://comments.gmane.org/gmane.linux.kbuild.devel/12131 This patchset supports the new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on linux-next tree (20140919). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1- "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc vger.kernel.org/msg36208.html 2- "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Ch (5): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 Pankaj Dubey (1): arm64: dts: add symlink .../devicetree/bindings/clock/exynos7-clock.txt| 67 arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 39 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 183 + arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 425 + drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ include/dt-bindings/clock/exynos7-clk.h| 49 +++ 16 files changed, 972 insertions(+), 164 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Rob Herring Cc: Catalin Marinas --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 2ca2ebd..1874e1a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -137,6 +137,18 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool "ARMv8 based Samsung Exynos7" + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" select ARCH_REQUIRE_GPIOLIB -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 5/8] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Acked-by: Kukjin Kim
Cc: Rob Herring
Cc: Catalin Marinas
---
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/exynos/Makefile | 5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 309c3dc..b13bf21 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += apm
dts-dirs += arm
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos7.dtsi"
+
+/ {
+ model = "Samsung Exynos7 Espresso board based on EXYNOS7";
+ compatible = "samsung,exynos7-espresso", "samsung,exynos7";
+
+ aliases {
+ serial0 = &serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = &serial_2;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0x0 0xC000>;
+ };
+};
+
+&fin_pll {
+ clock-frequency = <2400>;
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..a326fbf
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/ {
+ compatible = "samsung,exynos7";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>
[PATCH v5 1/8] clk: samsung: add support for 145xx and 1460x PLLs
From: Naveen Krishna Ch
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Mike Turquette
---
drivers/clk/samsung/clk-pll.c | 25 -
drivers/clk/samsung/clk-pll.h | 4
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2..9d70e5c 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
pll_con0 = __raw_readl(pll->con_reg);
pll_con1 = __raw_readl(pll->con_reg + 4);
- mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+ mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
pll_con1 & PLL46XX_KDIV_MASK;
- shift = pll->type == pll_4600 ? 16 : 10;
+ shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
fvco *= (mdiv << shift) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,
unsigned long drate,
lock = 0x;
/* Set PLL PMS and VSEL values. */
- con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+ if (pll->type == pll_1460x) {
+ con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+ } else {
+ con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
(PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+ con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
+ }
+
con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
(rate->pdiv << PLL46XX_PDIV_SHIFT) |
- (rate->sdiv << PLL46XX_SDIV_SHIFT) |
- (rate->vsel << PLL46XX_VSEL_SHIFT);
+ (rate->sdiv << PLL46XX_SDIV_SHIFT);
/* Set PLL K, MFR and MRR values. */
con1 = __raw_readl(pll->con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
/* clk_ops for 35xx and 2550 are similar */
case pll_35xx:
case pll_2550:
+ case pll_1450x:
+ case pll_1451x:
+ case pll_1452x:
if (!pll->rate_table)
init.ops = &samsung_pll35xx_clk_min_ops;
else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
case pll_4600:
case pll_4650:
case pll_4650c:
+ case pll_1460x:
if (!pll->rate_table)
init.ops = &samsung_pll46xx_clk_min_ops;
else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c0ed4d4..213de9a 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -33,6 +33,10 @@ enum samsung_pll_type {
pll_s3c2440_mpll,
pll_2550xx,
pll_2650xx,
+ pll_1450x,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
--
2.1.0
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[PATCH v5 3/8] clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
From: Naveen Krishna Ch
Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to
"struct exynos_cmu_info" to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Abhilash Kesavan
Reviewed-by: Thomas Abraham
Tested-by: Thomas Abraham
Cc: Tomasz Figa
Cc: Mike Turquette
---
drivers/clk/samsung/clk.c | 3 +++
drivers/clk/samsung/clk.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index a648236..dd1f7c9 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -402,6 +402,9 @@ void __init samsung_cmu_register_one(struct device_node *np,
if (cmu->fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
cmu->nr_fixed_clks);
+ if (cmu->fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+ cmu->nr_fixed_factor_clks);
if (cmu->clk_regs)
samsung_clk_sleep_init(reg_base, cmu->clk_regs,
cmu->nr_clk_regs);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index b3d0f4d..3f471e9 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -347,6 +347,9 @@ struct samsung_cmu_info {
/* list of fixed clocks and respective count */
struct samsung_fixed_rate_clock *fixed_clks;
unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
/* total number of clocks with IDs assigned*/
unsigned int nr_clk_ids;
--
2.1.0
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[PATCH v5 4/8] clk: samsung: add initial clock support for Exynos7 SoC
From: Naveen Krishna Ch Add initial clock support for Exynos7 SoC which is required to bring up platforms based on Exynos7. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Tomasz Figa Cc: Mike Turquette --- .../devicetree/bindings/clock/exynos7-clock.txt| 67 drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos7.c | 425 + include/dt-bindings/clock/exynos7-clk.h| 49 +++ 4 files changed, 542 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt new file mode 100644 index 000..789f761 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt @@ -0,0 +1,67 @@ +* Samsung Exynos7 Clock Controller + +Exynos7 clock controller has various blocks which are instantiated +independently from the device-tree. These clock controllers +generate and supply clocks to various hardware blocks within +the SoC. + +Each clock is assigned an identifier and client nodes can use +this identifier to specify the clock which they consume. All +available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos7-clk.h header and can be used in +device tree sources. + +External clocks: + +There are several clocks that are generated outside the SoC. It +is expected that they are defined using standard clock bindings +with following clock-output-names: + + - "fin_pll" - PLL input clock from XXTI + +Required Properties for Clock Controller: + + - compatible: clock controllers will use one of the following + compatible strings to indicate the clock controller + functionality. + + - "samsung,exynos7-clock-topc" + - "samsung,exynos7-clock-top0" + - "samsung,exynos7-clock-peric0" + - "samsung,exynos7-clock-peric1" + - "samsung,exynos7-clock-peris" + + - reg: physical base address of the controller and the length of + memory mapped region. + + - #clock-cells: should be 1. + + - clocks: list of clock identifiers which are fed as the input to + the given clock controller. Please refer the next section to + find the input clocks for a given controller. + +- clock-names: list of names of clocks which are fed as the input + to the given clock controller. + +Input clocks for top0 clock controller: + - fin_pll + - dout_sclk_bus0_pll + - dout_sclk_bus1_pll + - dout_sclk_cc_pll + - dout_sclk_mfc_pll + +Input clocks for peric0 clock controller: + - fin_pll + - dout_aclk_peric0_66 + - sclk_uart0 + +Input clocks for peric1 clock controller: + - fin_pll + - dout_aclk_peric1_66 + - sclk_uart1 + - sclk_uart2 + - sclk_uart3 + +Input clocks for peris clock controller: + - fin_pll + - dout_aclk_peris_66 diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 6fb4bc6..137bf9b 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o +obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c new file mode 100644 index 000..57712b0 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos7.c @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Naveen Krishna Ch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include +#include +#include + +#include "clk.h" +#include + +/* Register Offset definitions for CMU_TOPC (0x1057) */ +#define CC_PLL_LOCK0x +#define BUS0_PLL_LOCK 0x0004 +#define BUS1_DPLL_LOCK 0x0008 +#define MFC_PLL_LOCK 0x000C +#define AUD_PLL_LOCK 0x0010 +#define CC_PLL_CON00x0100 +#define BUS0_PLL_CON0 0x0110 +#define BUS1_DPLL_CON0 0x0120 +#define MFC_PLL_CON0 0x0130 +#define AUD_PLL_CON0 0x0140 +#define MUX_SEL_TOPC0 0x0200 +#define MUX_SEL_TOPC1 0x0204 +#define MUX_SEL_TOPC3 0x020C +#define DIV_TOPC1
[PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
Changes since v4: - Fixed comments from Tomasz Figa: - Changed the namespace prefix from exynos to samsung - Defined bindings to take all input clocks - Sorted the Kconfig entries alphabetically in clock Makefile - Used consistent 1 tab line breaks across the clock file - Statically initialized the samsung_cmu_info struct - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment. - Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags. Changes since v3: - Removed aliases for serial controllers from dtsi file and moved it into board specific dts file as suggested by Arnd. - Based this series on Robert Richter's patches for adding vendor device tree sub-directories for arm64. http://comments.gmane.org/gmane.linux.kbuild.devel/12131 This patchset supports the new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on linux-next tree (20140919). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1- "tty/serial: fix config dependencies for samsung serial" https://www.mail-archive.com/linux-samsung-soc vger.kernel.org/msg36208.html 2- "dts, kbuild: Implement support for dtb vendor subdirs" patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Alim Akhtar (2): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support arm64: Enable Exynos7 SOC in the defconfig Naveen Krishna Chatradhi (5): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 Pankaj Dubey (1): arm64: dts: add symlink .../devicetree/bindings/clock/exynos7-clock.txt| 67 arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/exynos/Makefile| 5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 39 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 183 + arch/arm64/boot/dts/include/dt-bindings| 1 + arch/arm64/configs/defconfig | 4 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 425 + drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h | 4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ include/dt-bindings/clock/exynos7-clk.h| 49 +++ 16 files changed, 972 insertions(+), 164 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
Hi Catalin, On Thu, Sep 18, 2014 at 9:48 PM, Catalin Marinas wrote: > On Fri, Sep 12, 2014 at 04:26:30PM +0100, Naveen Krishna Chatradhi wrote: >> From: Alim Akhtar >> >> This patch adds the necessary Kconfig entries to enable >> support for the ARMv8 based Exynos7 SoC. >> >> Signed-off-by: Alim Akhtar >> Signed-off-by: Naveen Krishna Chatradhi >> Cc: Rob Herring >> Cc: Catalin Marinas >> --- >> arch/arm64/Kconfig | 12 > > Please update the defconfig as well as we want the default image build > to contain all the available platforms. Will update the defconfig in the next version. Regards, Abhilash > > -- > Catalin > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/8] clk: samsung: add initial clock support for Exynos7 SoC
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:47 PM, Tomasz Figa wrote:
> Hi Naveen,
>
> Please see my comments inline.
>
> On 12.09.2014 17:26, Naveen Krishna Chatradhi wrote:
>> Add initial clock support for Exynos7 SoC which is required
>> to bring up platforms based on Exynos7.
>
> [snip]
>
>> +External clocks:
>> +
>> +There are several clocks that are generated outside the SoC. It
>> +is expected that they are defined using standard clock bindings
>> +with following clock-output-names:
>> +
>> + - "fin_pll" - PLL input clock from XXTI
>
> In addition to just relying on clock names (which I hope to finally go
> away from common clock framework some day) the binding should be defined
> to take all input clocks using generic clock bindings (i.e. clocks and
> clock-names). Even if the driver wouldn't use that yet, this would help
> with determining initialization order of clock providers.
OK, will fix.
>
>> +
>> +Required Properties for Clock Controller:
>> +
>> + - compatible: clock controllers will use one of the following
>> + compatible strings to indicate the clock controller
>> + functionality.
>> +
>> + - "samsung,exynos7-clock-topc"
>> + - "samsung,exynos7-clock-top0"
>> + - "samsung,exynos7-clock-peric0"
>> + - "samsung,exynos7-clock-peric1"
>> + - "samsung,exynos7-clock-peris"
>> +
>> + - reg: physical base address of the controller and the length of
>> + memory mapped region.
>> +
>> + - #clock-cells: should be 1.
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index 6fb4bc6..5da0ba9 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
>> obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
>> obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
>> obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
>> +obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
>
> Please keep the entries sorted alphabetically.
>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c
>> b/drivers/clk/samsung/clk-exynos7.c
>> new file mode 100644
>> index 000..3ea8d0e
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>
> [snip]
>
>> +static struct samsung_fixed_factor_clock topc_fixed_factor_clks[]
>> __initdata = {
>> + FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
>> + FFACTOR(0, "ffac_topc_bus0_pll_div4",
>> + "ffac_topc_bus0_pll_div2", 1, 2, 0),
>
> Please use a consistent way of breaking long lines. Here you have 3
> tabs, but further in the driver I can see 1 tab or 2 tabs. I'd recommend
> making them all 1 tab.
Will use 1 tab across the file.
>
>> + FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
>> + FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
>> + FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
>> +};
>
> [snip]
>
>> +static void __init exynos7_clk_topc_init(struct device_node *np)
>> +{
>> + struct exynos_cmu_info cmu = {0};
>> +
>> + cmu.pll_clks = topc_pll_clks;
>> + cmu.nr_pll_clks = ARRAY_SIZE(topc_pll_clks);
>> + cmu.mux_clks = topc_mux_clks;
>> + cmu.nr_mux_clks = ARRAY_SIZE(topc_mux_clks);
>> + cmu.div_clks = topc_div_clks;
>> + cmu.nr_div_clks = ARRAY_SIZE(topc_div_clks);
>> + cmu.fixed_factor_clks = topc_fixed_factor_clks;
>> + cmu.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks);
>> + cmu.clk_regs = topc_clk_regs;
>> + cmu.nr_clk_regs = ARRAY_SIZE(topc_clk_regs);
>
> I wonder if you couldn't simply make this struct statically initialized
> and marked as __initdata.
Will change.
>
> Otherwise looks good.
>
> Best regards,
> Tomasz
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Re: [PATCH v4 2/8] clk: samsung: Factor out the common code to clk.c
Hi Tomasz,
Naveen is no longer with Samsung, so I will be taking this patchset forward.
On Sat, Sep 13, 2014 at 4:50 PM, Tomasz Figa wrote:
> Hi Naveen,
>
> Please see my comments inline.
>
> On 12.09.2014 17:26, Naveen Krishna Chatradhi wrote:
>> While adding clock support for Exynos5260, the infrastructure to
>> register multiple clock controllers was introduced. Factor out the
>> support for registering multiple clock controller from Exynos5260
>> clock code to common samsung clock code so that it can be used by
>> other Exynos SoC which have multiple clock controllers.
>
> [snip]
>
>> @@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
>>
>> static void __init exynos5260_clk_aud_init(struct device_node *np)
>> {
>> - struct exynos5260_cmu_info cmu = {0};
>> + struct exynos_cmu_info cmu = {0};
>>
>> cmu.mux_clks = aud_mux_clks;
>> cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
>> @@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct
>> device_node *np)
>> cmu.clk_regs = aud_clk_regs;
>> cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
>>
>> - exynos5260_cmu_register_one(np, &cmu);
>> + exynos_cmu_register_one(np, &cmu);
>
> I'd suggest changing the namespace prefix from exynos to just samsung to
> be consistent with other helpers. Otherwise looks good.
Will fix this.
Regards,
Abhilash
>
> Best regards,
> Tomasz
>
> ___
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> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH 2/4] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 42 +++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 3133a1e..fe15ab8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = "samsung,exynos4210-wakeup-eint", },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -328,9 +322,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd,
unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos_wkup_irq_chip;
+
+static struct exynos_irq_chip exynos4210_wkup_irq_chip = {
.chip = {
- .name = "exynos_wkup_irq_chip",
+ .name = "exynos4210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -342,6 +338,29 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = "samsung,exynos4210-wakeup-eint",
+ .data = &exynos4210_wkup_irq_chip },
+ { .compatible = "samsung,exynos7-wakeup-eint",
+ .data = &exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -434,7 +453,12 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
int idx, irq;
for_each_child_of_node(dev->of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ memcpy(&exynos_wkup_irq_chip, match->data,
+ sizeof(struct exynos_irq_chip));
wkup_np = np;
break;
}
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h
b/drivers/pinctrl/samsung/pinctrl-exynos.h
index e060722..0db1e52 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -25,6 +25,9 @@
#define EXYNOS_WKUP_ECON_OFFSET0xE00
#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
+#define EXYNOS7_WKUP_ECON_OFFSET 0x700
+#define EXYNOS7_WKUP_EMASK_OFFSET
[PATCH 4/4] arm64: dts: Add initial pinctrl support to EXYNOS7
From: Naveen Krishna Chatradhi
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Abhilash Kesavan
Cc: Rob Herring
Cc: Catalin Marinas
Cc: Tomasz Figa
Cc: Linus Walleij
Cc: Thomas Abraham
---
arch/arm64/Kconfig |2 +
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
3 files changed, 628 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b4d1dc2..0dcf6f5 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -143,6 +143,8 @@ config ARCH_EXYNOS7
bool "ARMv8 based Samsung Exynos7"
select ARCH_EXYNOS
select COMMON_CLK_SAMSUNG
+ select PINCTRL
+ select PINCTRL_EXYNOS
help
This enables support for Samsung Exynos7 SoC family
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..d858805
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd6: gpd6 {
+
[PATCH 3/4] pinctrl: exynos: Add initial driver data for Exynos7
From: Naveen Krishna Chatradhi
This patch adds initial driver data for Exynos7 pinctrl support.
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Abhilash Kesavan
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Linus Walleij
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 113
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
4 files changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index f80519a..8425838 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
+ - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index fe15ab8..1ebd080 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1147,3 +1147,116 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = "exynos5420-gpio-ctrl4",
},
};
+
+/* pin banks of exynos7 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller - BUS0 */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
+};
+
+/* pin banks of exynos7 pin-controller - NFC */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FF */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - ESE */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS0 */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
+};
+
+/* pin banks of exynos7 pin-controller - FSYS1 */
+static struct samsung_pin_bank exynos7_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
+};
+
+struct samsung_pin_ctrl exynos7_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 Alive data */
+ .pin_banks = exynos7_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos7-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 BUS0 data */
+ .pin_banks = exynos7_pin_banks1,
+
