[PATCH v8 2/7] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Add iomuxc-lpsr usb_otg1_vbus pinctrl settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Resend
Changes for V6:
- Add wdog pinctrl group, add comments for hog2 group gpios
Changes for V7:
- Remove wdog pinctrl settings as they are not currently used
- Add pinctrl_usb_otg1_vbus settings
Changes for V8: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 88308f3..ca68a67 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -65,6 +65,8 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
gpio = < 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_usb_otg1_vbus>;
enable-active-high;
};
@@ -495,3 +497,22 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hog2grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59 /*
sensor_int_b */
+ >;
+ };
+
+ pinctrl_usb_otg1_vbus: usbotg1vbusgrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14 /*
usb_otg1_pwr */
+ >;
+ };
+ };
+};
--
2.1.4
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[PATCH v8 3/7] ARM: dts: imx: imx7d-sbd add usb_otg2_vbus pinctrl settings
Add usb_otg2_vbus pinctrl settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V7: New patch in series
Changes for V8: Rework for latest master
arch/arm/boot/dts/imx7d-sdb.dts | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index ca68a67..1962cb9 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -77,6 +77,8 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
gpio = < 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_usb_otg2_vbus>;
enable-active-high;
};
@@ -340,11 +342,16 @@
pinctrl_hog: hoggrp {
fsl,pins = <
- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34
/* bt reg on */
>;
};
+ pinctrl_usb_otg2_vbus: usbotg2vbusgrp {
+ fsl,pins = <
+ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /*
usb_otg2_pwr */
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA
0x407f
--
2.1.4
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[PATCH v8 4/7] pinctrl: freescale: imx: allow mux_reg offset zero
Allow mux_reg offset zero to be a valid pin_id, on imx7d
mux_conf reg offset is zero for iomuxc-lspr controller
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set
Changes for V5:
- Drop patch pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Allow mux_reg ZERO OFFSET as pin_id
Changes for V6: Restore ZERO_OFFSET_VALID flag
Changes for V7: Resend
Changes for V8: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 5 -
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b9c6deb..151d50d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -542,6 +542,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
@@ -550,7 +553,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a5fe72..2a592f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v8 1/7] ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't
have a dedicated can2 fixed regulator instead it shares PERI_3V3
fixed regulator (RT8070ZS) which is enabled by default (hardwired)
from pmic pfuze3000 NVCC_3V3 power rail.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V7: New patch in series
Changes for V8: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 432aaf5..88308f3 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -78,16 +78,7 @@
enable-active-high;
};
- reg_can2_3v3: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "can2-3v3";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- gpio = < 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_vref_1v8: regulator@3 {
+ reg_vref_1v8: regulator@2 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vref-1v8";
--
2.1.4
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[PATCH v8 7/7] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
Changes for V3: Add shared input select register notes
Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references of SHARE_INPUT_SELECT_REG flag
Changes for V6: Resend
Changes for V7: Resend
Changes for V8: Correct SDA pad example
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..457b2c6 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state retention capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings, it shares the input select register from main
+iomuxc controller for daisy chain settings, the fsl,input-sel property extends
+fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+};
+
+iomuxc: iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
-- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
+ "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
+ a phandle for main iomuxc controller which shares the input select register
for
+ daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x407f
+ >;
+ };
+};
--
2.1.4
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[PATCH v8 5/7] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
Changes for V4: Resend
Changes for V5:
- Remove SHARE_INPUT_SELECT_REG flag
- Use fsl,input-sel to check if shared input select register support is used
Changes for V6: Resend
Changes for V7: Resend
Changes for V8: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 151d50d..a5bb939 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -685,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret, i;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc fsl,input-sel property not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
--
2.1.4
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[PATCH v8 6/7] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
Add iomuxc-lpsr gpio group id's
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Remove flags SHARE_INPUT_SELECT_REG and ZERO_OFFSET_VALID.
Changes for V6: Restore ZERO_OFFSET_VALID flag.
Changes for V7: Resend
Changes for V8: Resend
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..16dc925 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v7 1/7] ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't
have a dedicated can2 fixed regulator instead it shares PERI_3V3
fixed regulator (RT8070ZS) which is enabled by default (hardwired)
from pmic pfuze3000 NVCC_3V3 power rail.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V7: New patch in series
arch/arm/boot/dts/imx7d-sdb.dts | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 8059458..83f0053 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -78,16 +78,7 @@
enable-active-high;
};
- reg_can2_3v3: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "can2-3v3";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- gpio = < 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_vref_1v8: regulator@3 {
+ reg_vref_1v8: regulator@2 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vref-1v8";
--
2.1.4
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[PATCH v7 5/7] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
Changes for V4: Resend
Changes for V5:
- Remove SHARE_INPUT_SELECT_REG flag
- Use fsl,input-sel to check if shared input select register support is used
Changes for V6: Resend
Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 151d50d..a5bb939 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -685,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret, i;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc fsl,input-sel property not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
--
2.1.4
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[PATCH v7 7/7] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
Changes for V3: Add shared input select register notes
Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references of SHARE_INPUT_SELECT_REG flag
Changes for V6: Resend
Changes for v7: Resend
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..aae069f 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state retention capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings, it shares the input select register from main
+iomuxc controller for daisy chain settings, the fsl,input-sel property extends
+fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+};
+
+iomuxc: iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
-- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
+ "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
+ a phandle for main iomuxc controller which shares the input select register
for
+ daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x407f
+ >;
+ };
+};
--
2.1.4
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[PATCH v7 4/7] pinctrl: freescale: imx: allow mux_reg offset zero
Allow mux_reg offset zero to be a valid pin_id, on imx7d
mux_conf reg offset is zero for iomuxc-lspr controller
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set
Changes for V5:
- Drop patch pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Allow mux_reg ZERO OFFSET as pin_id
Changes for V6: Restore ZERO_OFFSET_VALID flag
Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 5 -
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b9c6deb..151d50d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -542,6 +542,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
@@ -550,7 +553,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a5fe72..2a592f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v7 6/7] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
Add iomuxc-lpsr gpio group id's
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Remove flags SHARE_INPUT_SELECT_REG and
ZERO_OFFSET_VALID.
Changes for V6: Restore ZERO_OFFSET_VALID flag.
Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..16dc925 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v7 3/7] ARM: dts: imx: imx7d-sbd add usb_otg2_vbus pinctrl settings
Add usb_otg2_vbus pinctrl settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V7: New patch in series
arch/arm/boot/dts/imx7d-sdb.dts | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a5c7a44..96c1e1a 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -77,6 +77,8 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
gpio = < 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_usb_otg2_vbus>;
enable-active-high;
};
@@ -254,11 +256,16 @@
imx7d-sdb {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34
/* bt reg on */
>;
};
+ pinctrl_usb_otg2_vbus: usbotg2vbusgrp {
+ fsl,pins = <
+ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /*
usb_otg2_pwr */
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA
0x407f
--
2.1.4
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[PATCH v7 2/7] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Add iomuxc-lpsr usb_otg1_vbus pinctrl settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Resend
Changes for V6:
- Add wdog pinctrl group, add comments for hog2 group gpios
Changes for V7:
- Remove wdog pinctrl settings as they are not currently used
- Add pinctrl_usb_otg1_vbus settings
arch/arm/boot/dts/imx7d-sdb.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 83f0053..a5c7a44 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -65,6 +65,8 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
gpio = < 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_usb_otg1_vbus>;
enable-active-high;
};
@@ -410,3 +412,22 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hog2grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59 /*
sensor_int_b */
+ >;
+ };
+
+ pinctrl_usb_otg1_vbus: usbotg1vbusgrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14 /*
usb_otg1_pwr */
+ >;
+ };
+ };
+};
--
2.1.4
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[PATCH v6 1/6] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller, fsl,iput-sel
phandle allows to get input select register base address which is
shared from main iomuxc controller.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Add phandle to get input select register base address
Changes for V4: Resend
Changes for V5: Rename property to fsl,input-sel
Changes for V6: Resend
arch/arm/boot/dts/imx7d.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 15c2193..92ef0a9 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,12 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+ };
+
gpt1: gpt@302d {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d 0x1>;
--
2.1.4
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[PATCH v6 2/6] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Resend
Changes for V6:
- Add wdog pinctrl group, add comments for hog2 group gpios
arch/arm/boot/dts/imx7d-sdb.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 8059458..2da704a 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -419,3 +419,23 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14 /*
usb_otg1_pwr */
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59 /*
sensor_int_b */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+ };
+};
--
2.1.4
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[PATCH v6 3/6] pinctrl: freescale: imx: allow mux_reg offset zero
Allow mux_reg offset zero to be a valid pin_id, on imx7d
mux_conf reg offset is zero for iomuxc-lspr controller
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set
Changes for V5:
- Drop patch pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Allow mux_reg ZERO OFFSET as pin_id
Changes for V6: Restore ZERO_OFFSET_VALID flag
drivers/pinctrl/freescale/pinctrl-imx.c | 5 -
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b9c6deb..151d50d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -542,6 +542,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
@@ -550,7 +553,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a5fe72..2a592f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v6 5/6] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
Add iomuxc-lpsr gpio group id's
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Remove flags SHARE_INPUT_SELECT_REG and
ZERO_OFFSET_VALID.
Changes for V6: Restore ZERO_OFFSET_VALID flag.
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..16dc925 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v6 4/6] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
Changes for V4: Resend
Changes for V5:
- Remove SHARE_INPUT_SELECT_REG flag
- Use fsl,input-sel to check if shared input select register support is used
Changes for V6: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 151d50d..a5bb939 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -685,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret, i;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc fsl,input-sel property not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
--
2.1.4
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[PATCH v6 6/6] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
Changes for V3: Add shared input select register notes
Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references of SHARE_INPUT_SELECT_REG flag
Changes for v6: Resend
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..aae069f 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state retention capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings, it shares the input select register from main
+iomuxc controller for daisy chain settings, the fsl,input-sel property extends
+fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+};
+
+iomuxc: iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
-- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
+ "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
+ a phandle for main iomuxc controller which shares the input select register
for
+ daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x407f
+ >;
+ };
+};
--
2.1.4
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[PATCH v5 6/7] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
Add iomuxc-lpsr gpio group id's
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Remove flags SHARE_INPUT_SELECT_REG and
ZERO_OFFSET_VALID.
drivers/pinctrl/freescale/pinctrl-imx7d.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..e901907 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,31 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v5 5/7] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
Changes for V4: Resend
Changes for V5:
- Remove SHARE_INPUT_SELECT_REG flag
- Use fsl,input-sel to check if shared input select register support is used
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 23348d8..c7946fa 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -682,6 +689,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret, i;
@@ -712,6 +721,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc fsl,input-sel property not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
--
2.1.4
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[PATCH v5 2/7] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller, fsl,iput-sel
phandle allows to get input select register base address which is
shared from main iomuxc controller.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Add phandle to get input select register base address
Changes for V4: Resend
Changes for V5: Rename property to fsl,input-sel
arch/arm/boot/dts/imx7d.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 15c2193..92ef0a9 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,12 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+ };
+
gpt1: gpt@302d {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d 0x1>;
--
2.1.4
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[PATCH v5 4/7] pinctrl: freescale: imx: allow mux_reg offset zero
Allow mux_reg offset zero to be a valid pin_id, on imx7d mux_conf reg offset is zero for iomuxc-lspr controller Signed-off-by: Adrian Alonso <aalo...@freescale.com> --- Changes for V2: Resend Changes for V3: Resend Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set Changes for V5: - Drop patch pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag - Allow mux_reg ZERO OFFSET as pin_id drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index b9c6deb..23348d8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -550,7 +550,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, conf_reg = -1; } - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; pin_reg = >pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/7] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
From: Robin Gong <b38...@freescale.com>
Fix system chrash caused by groups whose number is smaller than the number
of groups of the last pinctl instance which is not initialized.
iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
the second instance (iomuxc) the chrash below occurs.
Uncompressing Linux... done, booting the kernel.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0-next-20150901-6-gebfa43c
(aalonso@bluefly)
[0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin
instruction cache
[0.00] Machine model: Freescale i.MX7 SabreSD Board
[0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>]
(imx_dt_node_to_map+0x58/0x208)
[0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>]
(pinctrl_dt_to_map+0x174/0x2b0)
[0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>]
(pinctrl_get+0x100/0x424)
[0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>]
(pinctrl_register+0x26c/0x480)
[0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>]
(imx_pinctrl_probe+0x580/0x6e8)
[0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>]
(platform_drv_probe+0x44/0xa4)
[0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>]
(driver_probe_device+0x174/0x2b4)
[0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>]
(__driver_attach+0x8c/0x90)
[0.728982] [<803505fc>] (__driver_attach) from [<8034e930>]
(bus_for_each_dev+0x6c/0xa0)
[0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>]
(bus_add_driver+0x148/0x1f0)
[0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>]
(driver_register+0x78/0xf8)
[0.753880] [<80350c00>] (driver_register) from [<800097d0>]
(do_one_initcall+0x8c/0x1d4)
[0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>]
(kernel_init_freeable+0x144/0x1e4)
[0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>]
(kernel_init+0x8/0xe8)
[0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>]
(ret_from_fork+0x14/0x2c)
[0.786981] Code: e352 e5e32001 1afb e12fff1e (e4d03001)
Signed-off-by: Robin Gong <b38...@freescale.com>
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Chages for V2:
- Reorder patch series
- Add platform boot up information on kernel error
- Move gpr_index to imx_pinctrl_soc_info
Changes for V3:
- Rename grp_index to group_index
Changes for V4: Resend
Changes for V5: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 3 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..b9c6deb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
- static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
@@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
- grp = >groups[grp_index++];
+ grp = >groups[info->group_index++];
imx_pinctrl_parse_groups(child, grp, info, i++);
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d3..2a5fe72 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -78,6 +78,7 @@ struct imx_pinctrl_soc_info {
struct imx_pin_reg *pin_regs;
struct imx_pin_group *groups;
unsigned int ngroups;
+ unsigned int group_index;
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
--
2.1.4
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[PATCH v5 3/7] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 8059458..c8a178c 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -419,3 +419,18 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+ };
+};
--
2.1.4
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[PATCH v5 7/7] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
Changes for V3: Add shared input select register notes
Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references of SHARE_INPUT_SELECT_REG flag
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..aae069f 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state retention capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings, it shares the input select register from main
+iomuxc controller for daisy chain settings, the fsl,input-sel property extends
+fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+};
+
+iomuxc: iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
-- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
+ "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
+ a phandle for main iomuxc controller which shares the input select register
for
+ daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ fsl,input-sel = <>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x407f
+ >;
+ };
+};
--
2.1.4
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[PATCH v4 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
Changes for V3: Add shared input select register notes
Changes for V4: Resend
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 57 ++
1 file changed, 57 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..19697bd 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,10 +1,33 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state rentetion capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings it shares the input select register from iomuxc
+for daisy chain settings, the input-sel phandle and SHARE_INPUT_SELECT_REG flag
+extends fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ input-sel = <>;
+};
+
+iomuxc: iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc-lpsr"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
@@ -25,3 +48,37 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x407f
+ >;
+ };
+};
--
2.1.4
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[PATCH v4 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
- Add iomuxc-lpsr gpio group id's
- Use flag ZERO_OFFSET_VALID and SHARE_INPUT_SELECT_REG to
properly set pads from iomuxc-lpsr domain
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
Changes for V4: Resend
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..b4d77e4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = SHARE_INPUT_SELECT_REG | ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v4 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
From: Robin Gong <b38...@freescale.com>
Fix system chrash caused by groups whose number is smaller than the number
of groups of the last pinctl instance which is not initialized.
iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
the second instance (iomuxc) the chrash below occurs.
Uncompressing Linux... done, booting the kernel.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0-next-20150901-6-gebfa43c
(aalonso@bluefly)
[0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin
instruction cache
[0.00] Machine model: Freescale i.MX7 SabreSD Board
[0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>]
(imx_dt_node_to_map+0x58/0x208)
[0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>]
(pinctrl_dt_to_map+0x174/0x2b0)
[0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>]
(pinctrl_get+0x100/0x424)
[0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>]
(pinctrl_register+0x26c/0x480)
[0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>]
(imx_pinctrl_probe+0x580/0x6e8)
[0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>]
(platform_drv_probe+0x44/0xa4)
[0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>]
(driver_probe_device+0x174/0x2b4)
[0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>]
(__driver_attach+0x8c/0x90)
[0.728982] [<803505fc>] (__driver_attach) from [<8034e930>]
(bus_for_each_dev+0x6c/0xa0)
[0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>]
(bus_add_driver+0x148/0x1f0)
[0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>]
(driver_register+0x78/0xf8)
[0.753880] [<80350c00>] (driver_register) from [<800097d0>]
(do_one_initcall+0x8c/0x1d4)
[0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>]
(kernel_init_freeable+0x144/0x1e4)
[0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>]
(kernel_init+0x8/0xe8)
[0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>]
(ret_from_fork+0x14/0x2c)
[0.786981] Code: e352 e5e32001 1afb e12fff1e (e4d03001)
Signed-off-by: Robin Gong <b38...@freescale.com>
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Chages for V2:
- Reorder patch series
- Add platform boot up information on kernel error
- Move gpr_index to imx_pinctrl_soc_info
Changes for V3:
- Rename grp_index to group_index
Changes for V4: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 3 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..b9c6deb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
- static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
@@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
- grp = >groups[grp_index++];
+ grp = >groups[info->group_index++];
imx_pinctrl_parse_groups(child, grp, info, i++);
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d3..2a5fe72 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -78,6 +78,7 @@ struct imx_pinctrl_soc_info {
struct imx_pin_reg *pin_regs;
struct imx_pin_group *groups;
unsigned int ngroups;
+ unsigned int group_index;
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
--
2.1.4
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[PATCH v4 6/8] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
Changes for V4: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 866d864..619915f 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (info->flags & SHARE_INPUT_SELECT_REG)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -687,6 +694,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
@@ -712,6 +721,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (info->flags & SHARE_INPUT_SELECT_REG) {
+ np = of_parse_phandle(dev_np, "input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc input-sel device node not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a592f6..3805476 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
+#define SHARE_INPUT_SELECT_REG 0x4
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v4 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller, iput-sel phandle
allows to get input select register base address which is shared from
iomuxc controller.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Add phandle to get input select register base address
Changes for V4: Resend
arch/arm/boot/dts/imx7d.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 15c2193..0cd7033 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,12 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ input-sel = <>;
+ };
+
gpt1: gpt@302d {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d 0x1>;
--
2.1.4
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[PATCH v4 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
offset is zero for iomuxc-lspr controller
- Do default initialization on parse group function.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set
drivers/pinctrl/freescale/pinctrl-imx.c | 20 ++--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b9c6deb..866d864 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev
*pctldev,
const struct imx_pin_reg *pin_reg = >pin_regs[pin_id];
unsigned long config;
- if (!pin_reg || pin_reg->conf_reg == -1) {
+ if (pin_reg->conf_reg == -1) {
seq_printf(s, "N/A");
return;
}
@@ -536,21 +536,26 @@ static int imx_pinctrl_parse_groups(struct device_node
*np,
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
+ u32 mux_reg;
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ mux_reg = be32_to_cpu(*list++);
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
+ if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
@@ -684,7 +689,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct imx_pinctrl *ipctl;
struct resource *res;
- int ret, i;
+ int ret;
if (!info || !info->pins || !info->npins) {
dev_err(>dev, "wrong pinctrl info\n");
@@ -702,11 +707,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!info->pin_regs)
return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- info->pin_regs[i].mux_reg = -1;
- info->pin_regs[i].conf_reg = -1;
- }
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(>dev, res);
if (IS_ERR(ipctl->base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a5fe72..2a592f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v4 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
- Add imx7 SoC GPIO1 pad iomuxc settings - Fix UART input select daisy chain setting values Signed-off-by: Adrian Alonso <aalo...@freescale.com> --- Chages for V2: Fix tab+space identation Chages for V3: Resend Chages for V4: Resend arch/arm/boot/dts/imx7d-pinfunc.h | 122 +- 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..eeda783 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO00x 0x0030 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x 0x0030 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x 0x0030 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB0x 0x0030 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO10x0004 0x0034 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK30x0004 0x0034 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK0x0004 0x0034 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO20x0008 0x0038 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK10x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK0x0008 0x0038 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO10x0008 0x0038 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO30x000C 0x003C 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK20x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK0x000C 0x003C 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO20x000C 0x003C 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO40x0010 0x0040 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO50x0014 0x0044 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO60x0018 0x0048 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO70x001C 0x004C 0x 0x0 0x0 +#
[PATCH v4 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 8059458..c8a178c 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -419,3 +419,18 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+ };
+};
--
2.1.4
--
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[PATCH v3 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller, iput-sel phandle
allows to get input select register base address which is shared from
iomuxc controller.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Add phandle to get input select register base address
arch/arm/boot/dts/imx7d.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b738ce0..9d997e0 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,12 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ input-sel = <>;
+ };
+
gpt1: gpt@302d {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d 0x1>;
--
2.1.4
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[PATCH v3 6/8] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select
base register address
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 5edbca5..b39c1a0 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (info->flags & SHARE_INPUT_SELECT_REG)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -690,6 +697,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (info->flags & SHARE_INPUT_SELECT_REG) {
+ np = of_parse_phandle(dev_np, "input-sel", 0);
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc input select base address not
found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc input-sel device node not
found\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a592f6..3805476 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
+#define SHARE_INPUT_SELECT_REG 0x4
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v3 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
- Add iomuxc-lpsr gpio group id's
- Use flag ZERO_OFFSET_VALID and SHARE_INPUT_SELECT_REG to
properly set pads from iomuxc-lpsr domain
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
Changes for V3: Resend
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..b4d77e4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = SHARE_INPUT_SELECT_REG | ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v3 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
From: Robin Gong <b38...@freescale.com>
Fix system chrash caused by groups whose number is smaller than the number
of groups of the last pinctl instance which is not initialized.
iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
the second instance (iomuxc) the chrash below occurs.
Uncompressing Linux... done, booting the kernel.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0-next-20150901-6-gebfa43c
(aalonso@bluefly)
[0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin
instruction cache
[0.00] Machine model: Freescale i.MX7 SabreSD Board
[0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>]
(imx_dt_node_to_map+0x58/0x208)
[0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>]
(pinctrl_dt_to_map+0x174/0x2b0)
[0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>]
(pinctrl_get+0x100/0x424)
[0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>]
(pinctrl_register+0x26c/0x480)
[0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>]
(imx_pinctrl_probe+0x580/0x6e8)
[0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>]
(platform_drv_probe+0x44/0xa4)
[0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>]
(driver_probe_device+0x174/0x2b4)
[0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>]
(__driver_attach+0x8c/0x90)
[0.728982] [<803505fc>] (__driver_attach) from [<8034e930>]
(bus_for_each_dev+0x6c/0xa0)
[0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>]
(bus_add_driver+0x148/0x1f0)
[0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>]
(driver_register+0x78/0xf8)
[0.753880] [<80350c00>] (driver_register) from [<800097d0>]
(do_one_initcall+0x8c/0x1d4)
[0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>]
(kernel_init_freeable+0x144/0x1e4)
[0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>]
(kernel_init+0x8/0xe8)
[0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>]
(ret_from_fork+0x14/0x2c)
[0.786981] Code: e352 e5e32001 1afb e12fff1e (e4d03001)
Signed-off-by: Robin Gong <b38...@freescale.com>
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Chages for V2:
- Reorder patch series
- Add platform boot up information on kernel error
- Move gpr_index to imx_pinctrl_soc_info
Changes for V3:
- Rename grp_index to group_index
drivers/pinctrl/freescale/pinctrl-imx.c | 3 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..b9c6deb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
- static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
@@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
- grp = >groups[grp_index++];
+ grp = >groups[info->group_index++];
imx_pinctrl_parse_groups(child, grp, info, i++);
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d3..2a5fe72 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -78,6 +78,7 @@ struct imx_pinctrl_soc_info {
struct imx_pin_reg *pin_regs;
struct imx_pin_group *groups;
unsigned int ngroups;
+ unsigned int group_index;
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
--
2.1.4
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[PATCH v3 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
offset is zero for iomuxc-lspr controller
- Do default initialization on parse group function.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
Changes for V3: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 23 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b9c6deb..5edbca5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev
*pctldev,
const struct imx_pin_reg *pin_reg = >pin_regs[pin_id];
unsigned long config;
- if (!pin_reg || pin_reg->conf_reg == -1) {
+ if (pin_reg->conf_reg == -1) {
seq_printf(s, "N/A");
return;
}
@@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node
*np,
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
+ u32 mux_reg;
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ mux_reg = be32_to_cpu(*list++);
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
+ if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ if (info->flags & ZERO_OFFSET_VALID)
+ pin_id = mux_reg / 4;
+ else
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
@@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct imx_pinctrl *ipctl;
struct resource *res;
- int ret, i;
+ int ret;
if (!info || !info->pins || !info->npins) {
dev_err(>dev, "wrong pinctrl info\n");
@@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!info->pin_regs)
return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- info->pin_regs[i].mux_reg = -1;
- info->pin_regs[i].conf_reg = -1;
- }
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(>dev, res);
if (IS_ERR(ipctl->base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a5fe72..2a592f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v2 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
- Add iomuxc-lpsr gpio group id's
- Use flag ZERO_OFFSET_VALID and SHARE_INPUT_SELECT_REG to
properly set pads from iomuxc-lpsr domain
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..b4d77e4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = SHARE_INPUT_SELECT_REG | ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = _pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data =
_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
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[PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 9f019be..597319d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (info->flags & SHARE_INPUT_SELECT_REG)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -690,6 +697,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (info->flags & SHARE_INPUT_SELECT_REG) {
+ np = of_get_child_by_name(dev_np->parent, "iomuxc");
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(>dev,
+ "iomuxc base address not found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(>dev, "iomuxc device node not foud\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(>dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 67c07c2..d11a827 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
+#define SHARE_INPUT_SELECT_REG 0x4
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v2 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index fdd1d7c..63af4ea 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -406,3 +406,18 @@
};
};
+
+_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+ };
+};
--
2.1.4
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[PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 43 ++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..c7310fc 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,10 +1,19 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state rentetion capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0).
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl-imx7d-iomuxc-lpsr"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
@@ -25,3 +34,37 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c1_1 _i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x407f
+ >;
+ };
+};
+
+iomuxc@3033 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x3033 0x1>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x407f
+ >;
+ };
+};
--
2.1.4
--
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[PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
offset is zero for iomuxc-lspr controller
- Do default initialization on parse group function.
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 23 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 95db9e8..9f019be 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev
*pctldev,
const struct imx_pin_reg *pin_reg = >pin_regs[pin_id];
unsigned long config;
- if (!pin_reg || pin_reg->conf_reg == -1) {
+ if (pin_reg->conf_reg == -1) {
seq_printf(s, "N/A");
return;
}
@@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node
*np,
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
+ u32 mux_reg;
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = >pins[i];
+ mux_reg = be32_to_cpu(*list++);
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
+ if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ if (info->flags & ZERO_OFFSET_VALID)
+ pin_id = mux_reg / 4;
+ else
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+
pin_reg = >pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
@@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct imx_pinctrl *ipctl;
struct resource *res;
- int ret, i;
+ int ret;
if (!info || !info->pins || !info->npins) {
dev_err(>dev, "wrong pinctrl info\n");
@@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!info->pin_regs)
return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- info->pin_regs[i].mux_reg = -1;
- info->pin_regs[i].conf_reg = -1;
- }
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(>dev, res);
if (IS_ERR(ipctl->base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 26f8f1c..67c07c2 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH v2 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Changes for V2: Resend
arch/arm/boot/dts/imx7d.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b738ce0..00f70db 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,11 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c 0x1>;
+ };
+
gpt1: gpt@302d {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d 0x1>;
--
2.1.4
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[PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
- Add imx7 SoC GPIO1 pad iomuxc settings - Fix UART input select daisy chain setting values Signed-off-by: Adrian Alonso <aalo...@freescale.com> --- Chages for V2: Fix tab+space identation arch/arm/boot/dts/imx7d-pinfunc.h | 122 +- 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..eeda783 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO00x 0x0030 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x 0x0030 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x 0x0030 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB0x 0x0030 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO10x0004 0x0034 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK30x0004 0x0034 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK0x0004 0x0034 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO20x0008 0x0038 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK10x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK0x0008 0x0038 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO10x0008 0x0038 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO30x000C 0x003C 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK20x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK0x000C 0x003C 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO20x000C 0x003C 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO40x0010 0x0040 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO50x0014 0x0044 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO60x0018 0x0048 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO70x001C 0x004C 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C
[PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
From: Robin Gong <b38...@freescale.com>
Fix system chrash caused by groups whose number is smaller than the number
of groups of the last pinctl instance which is not initialized.
iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
the second instance (iomuxc) the chrash below occurs.
Uncompressing Linux... done, booting the kernel.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0-next-20150901-6-gebfa43c
(aalonso@bluefly)
[0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin
instruction cache
[0.00] Machine model: Freescale i.MX7 SabreSD Board
[0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>]
(imx_dt_node_to_map+0x58/0x208)
[0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>]
(pinctrl_dt_to_map+0x174/0x2b0)
[0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>]
(pinctrl_get+0x100/0x424)
[0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>]
(pinctrl_register+0x26c/0x480)
[0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>]
(imx_pinctrl_probe+0x580/0x6e8)
[0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>]
(platform_drv_probe+0x44/0xa4)
[0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>]
(driver_probe_device+0x174/0x2b4)
[0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>]
(__driver_attach+0x8c/0x90)
[0.728982] [<803505fc>] (__driver_attach) from [<8034e930>]
(bus_for_each_dev+0x6c/0xa0)
[0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>]
(bus_add_driver+0x148/0x1f0)
[0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>]
(driver_register+0x78/0xf8)
[0.753880] [<80350c00>] (driver_register) from [<800097d0>]
(do_one_initcall+0x8c/0x1d4)
[0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>]
(kernel_init_freeable+0x144/0x1e4)
[0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>]
(kernel_init+0x8/0xe8)
[0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>]
(ret_from_fork+0x14/0x2c)
[0.786981] Code: e352 e5e32001 1afb e12fff1e (e4d03001)
Signed-off-by: Robin Gong <b38...@freescale.com>
Signed-off-by: Adrian Alonso <aalo...@freescale.com>
---
Chages for V2:
- Reorder patch series
- Add platform boot up information on kernel error
- Move gpr_index to imx_pinctrl_soc_info
drivers/pinctrl/freescale/pinctrl-imx.c | 3 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..95db9e8 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
- static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
@@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node
*np,
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
- grp = >groups[grp_index++];
+ grp = >groups[info->grp_index++];
imx_pinctrl_parse_groups(child, grp, info, i++);
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d3..26f8f1c 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -81,6 +81,7 @@ struct imx_pinctrl_soc_info {
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
+ u32 grp_index;
};
#define SHARE_MUX_CONF_REG 0x1
--
2.1.4
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[PATCH 5/8] pinctrl: freescale: imx: add shared input select reg support
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++-
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index 0440b0b..1009b52 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include linux/module.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_address.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
#include linux/pinctrl/pinctrl.h
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags SHARE_INPUT_SELECT_REG)
+ writel(pin-input_val, ipctl-input_sel_base +
+ pin-input_reg);
+ else
+ writel(pin-input_val, ipctl-base +
+ pin-input_reg);
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -691,6 +698,8 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev-dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
@@ -716,6 +725,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl-base))
return PTR_ERR(ipctl-base);
+ if (info-flags SHARE_INPUT_SELECT_REG) {
+ np = of_get_child_by_name(dev_np-parent, iomuxc);
+ if (np) {
+ ipctl-input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl-input_sel_base)) {
+ of_node_put(np);
+ dev_err(pdev-dev,
+ iomuxc base address not found\n);
+ return PTR_ERR(ipctl-input_sel_base);
+ }
+ } else {
+ dev_err(pdev-dev, iomuxc device node not foud\n);
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(pdev-dev);
imx_pinctrl_desc.pins = info-pins;
imx_pinctrl_desc.npins = info-npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index d22b8f6..85c701b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
+#define SHARE_INPUT_SELECT_REG 0x4
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
--
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[PATCH 1/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
- Add imx7 SoC GPIO1 pad iomuxc settings mux_reg conf_reg input_reg mux_mode input_val - Fix UART input select daisy chain setting values Signed-off-by: Adrian Alonso aalo...@freescale.com --- arch/arm/boot/dts/imx7d-pinfunc.h | 122 +- 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..22f849c 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT0x0018 0x0048 0x 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW40x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x 0x0 0x0 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR0x001C 0x004C
[PATCH 2/8] ARM: dts: imx: imx7d add iomuxc lpsr device node
Add device tree node to support iomuxc-lpsr controller
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
arch/arm/boot/dts/imx7d.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b738ce0..00f70db 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,11 @@
status = disabled;
};
+ iomuxc_lpsr: iomuxc-lpsr@302c {
+ compatible = fsl,imx7d-iomuxc-lpsr;
+ reg = 0x302c 0x1;
+ };
+
gpt1: gpt@302d {
compatible = fsl,imx7d-gpt, fsl,imx6sx-gpt;
reg = 0x302d 0x1;
--
2.1.4
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[PATCH 3/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
arch/arm/boot/dts/imx7d-sdb.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index fdd1d7c..63af4ea 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -406,3 +406,18 @@
};
};
+
+iomuxc_lpsr {
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_hog_2;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins =
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO50x14
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO70x59
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ ;
+ };
+ };
+};
--
2.1.4
--
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[PATCH 4/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
offset is zero for iomuxc-lspr controller
- Do default initialization on parse group function.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx.c | 23 +--
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..0440b0b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev
*pctldev,
const struct imx_pin_reg *pin_reg = info-pin_regs[pin_id];
unsigned long config;
- if (!pin_reg || pin_reg-conf_reg == -1) {
+ if (pin_reg-conf_reg == -1) {
seq_printf(s, N/A);
return;
}
@@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node
*np,
return -ENOMEM;
for (i = 0; i grp-npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
+ u32 mux_reg;
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = grp-pins[i];
+ mux_reg = be32_to_cpu(*list++);
+ if (!(info-flags ZERO_OFFSET_VALID) !mux_reg)
+ mux_reg = -1;
+
if (info-flags SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
+ if (!(info-flags ZERO_OFFSET_VALID) !conf_reg)
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ if (info-flags ZERO_OFFSET_VALID)
+ pin_id = mux_reg / 4;
+ else
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+
pin_reg = info-pin_regs[pin_id];
pin-pin = pin_id;
grp-pin_ids[i] = pin_id;
@@ -685,7 +693,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct imx_pinctrl *ipctl;
struct resource *res;
- int ret, i;
+ int ret;
if (!info || !info-pins || !info-npins) {
dev_err(pdev-dev, wrong pinctrl info\n);
@@ -703,11 +711,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!info-pin_regs)
return -ENOMEM;
- for (i = 0; i info-npins; i++) {
- info-pin_regs[i].mux_reg = -1;
- info-pin_regs[i].conf_reg = -1;
- }
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl-base = devm_ioremap_resource(pdev-dev, res);
if (IS_ERR(ipctl-base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d3..d22b8f6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -84,6 +84,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
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[PATCH 6/8] pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
- Add iomuxc-lpsr gpio group id's
- Use flag ZERO_OFFSET_VALID and SHARE_INPUT_SELECT_REG to
properly set pads from iomuxc-lpsr domain
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..a347c22 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -172,6 +172,14 @@ enum imx7d_pads {
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
};
/* Pad names for the pinmux subsystem */
@@ -333,13 +341,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = SHARE_INPUT_SELECT_REG | ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = fsl,imx7d-iomuxc, .data = imx7d_pinctrl_info, },
+ { .compatible = fsl,imx7d-iomuxc-lpsr, .data =
imx7d_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
--
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[PATCH 8/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
From: Robin Gong b38...@freescale.com Remove 'static' for 'grp_index', otherwise, it cause the groups whose number is smaller than the number of groups of the last pinctl instance never to be intialized, thus cause system crash as below [0.661012] [802a6cb0] (strcmp) from [802cc80c] (imx_dt_node_to_map+0x58/0x208) [0.668879] [802cc80c] (imx_dt_node_to_map) from [802cbe24] (pinctrl_dt_to_map+0x174/0x2b0) [0.677654] [802cbe24] (pinctrl_dt_to_map) from [802c8f18] (pinctrl_get+0x100/0x424) [0.685878] [802c8f18] (pinctrl_get) from [802c9510] (pinctrl_register+0x26c/0x480) [0.694104] [802c9510] (pinctrl_register) from [802ccf3c] (imx_pinctrl_probe+0x580/0x6e8) [0.702706] [802ccf3c] (imx_pinctrl_probe) from [80351b58] (platform_drv_probe+0x44/0xa4) [0.711455] [80351b58] (platform_drv_probe) from [803503ec] (driver_probe_device+0x174/0x2b4) [0.720405] [803503ec] (driver_probe_device) from [803505fc] (__driver_attach+0x8c/0x90) [0.728982] [803505fc] (__driver_attach) from [8034e930] (bus_for_each_dev+0x6c/0xa0) [0.737381] [8034e930] (bus_for_each_dev) from [8034fb88] (bus_add_driver+0x148/0x1f0) [0.745804] [8034fb88] (bus_add_driver) from [80350c00] (driver_register+0x78/0xf8) [0.753880] [80350c00] (driver_register) from [800097d0] (do_one_initcall+0x8c/0x1d4) [0.762282] [800097d0] (do_one_initcall) from [80987dac] (kernel_init_freeable+0x144/0x1e4) [0.771061] [80987dac] (kernel_init_freeable) from [806d9c7c] (kernel_init+0x8/0xe8) [0.779285] [806d9c7c] (kernel_init) from [8000f628] (ret_from_fork+0x14/0x2c) [0.786981] Code: e352 e5e32001 1afb e12fff1e (e4d03001) Signed-off-by: Robin Gong b38...@freescale.com Signed-off-by: Adrian Alonso aalo...@freescale.com --- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 3e02887..cdb5463 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -595,7 +595,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct imx_pmx_func *func; struct imx_pin_group *grp; - static u32 grp_index; + u32 grp_index = 0; u32 i = 0; dev_dbg(info-dev, parse function(%d): %s\n, index, np-name); -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/8] pinctrl: freescale: imx: fix flat functions default return
Fix imx pinctrl dt flat functions default return value. If property fsl,pins is not found in function_np and pinctrl_np return false to indicate that DT is not using flat functions. Signed-off-by: Adrian Alonso aalo...@freescale.com --- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 1009b52..3e02887 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -641,7 +641,7 @@ static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) } } - return true; + return false; } static int imx_pinctrl_probe_dt(struct platform_device *pdev, -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4][v4] ARM: dts: imx: imx7d add iomuxc lpsr register base address
* Add iomuxc lpsr register base address to extend
pinctrl-imx driver to support the iomux settings for pins
that support LPSR operation mode.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
- Version 2: Resend
- Version 3: Resend
- Version 4: Resend
arch/arm/boot/dts/imx7d.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 9014b80..7edfa42 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -487,7 +487,7 @@
iomuxc: iomuxc@3033 {
compatible = fsl,imx7d-iomuxc;
- reg = 0x3033 0x1;
+ reg = 0x3033 0x1, 0x302c
0x1;
};
gpr: iomuxc-gpr@3034 {
--
2.1.4
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[PATCH 3/4][v4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
* Change from v1 to v2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
* Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr
base register address.
* Version 4: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..aef4ca3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -38,7 +38,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with normal
iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg |= 0x2;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel
[PATCH 4/4][v4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids
* Add imx7d SoC iomuxc-lpsr gpio group id's
* Add IOMUXC_LPSR_SUPPORT flag for pinctrl-imx driver to
support iomuxc-lpsr controller.
* Add fsl,imx7d-pinctrl.txt documentation for encoded
pad groupd is for iomux-lpsr GPIO1.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
- Version 4: Add devicetreee bindings fsl,imx7d-pinctrl.txt documentation for
encoded pad groupd is for iomux-lpsr GPIO1.
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 26 ++
drivers/pinctrl/freescale/pinctrl-imx7d.c | 17 ++
2 files changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..9c48ce9 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -25,3 +25,29 @@ PAD_CTL_DSE_X1 (0 0)
PAD_CTL_DSE_X2 (1 0)
PAD_CTL_DSE_X3 (2 0)
PAD_CTL_DSE_X4 (3 0)
+
+IOMUXC-LPSR controller:
+i.MX7D supports two iomux controllers iomuxc and iomuxc-lpsr; LPSR is a power
mode
+where NVCC_GPIO1 power rail remains on and GPIO1 under LPSR mode can retain the
+state of GPIO1 pads (GPIO1_07 to GPIO1_00).
+
+To support both controllers fsl,imx7d-iomuxc is extended to include the pad
group
+id's for GPIO1 and these are encoded in input_val integer so pinctrl parse
groups
+can be created for all imx7d_pads.
+
+For example pad group id for GPIO1_IO00 correspod to 155
+
+drivers/pinctrl/freescale/pinctrl-imx7d.c
+enum imx7d_pads {
+ ...
+ MX7D_PAD_GPIO1_IO00 = 155,
+ ...
+};
+
+In pad definition for GPIO1_IO00 the group id is encoded as 0x009B, while the
lower 16 bit
+correspond to input_val.
+
+arch/arm/boot/dts/imx7d-pinfunc.h
+#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x009B
+#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x 0x0030 0x 0x1 0x009B
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x009B
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..cf89275 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -172,6 +172,14 @@ enum imx7d_pads {
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
+ MX7D_PAD_GPIO1_IO00 = 155,
+ MX7D_PAD_GPIO1_IO01 = 156,
+ MX7D_PAD_GPIO1_IO02 = 157,
+ MX7D_PAD_GPIO1_IO03 = 158,
+ MX7D_PAD_GPIO1_IO04 = 159,
+ MX7D_PAD_GPIO1_IO05 = 160,
+ MX7D_PAD_GPIO1_IO06 = 161,
+ MX7D_PAD_GPIO1_IO07 = 162,
};
/* Pad names for the pinmux subsystem */
@@ -331,11 +339,20 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+ .flags = IOMUXC_LPSR_SUPPORT,
};
static struct of_device_id imx7d_pinctrl_of_match[] = {
--
2.1.4
--
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[PATCH 1/4][v4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
* Add iMX7D SoC imx7d-pinfunc gpio pad settings mux_reg conf_reg input_reg mux_mode input_val * iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most significant bits of input_val to avoid group id overlap bweeten iomuxc and iomuxc-lpsr. Signed-off-by: Adrian Alonso aalo...@freescale.com --- - Version 2: Use input_val upper 16 bits to represent pad group id - Version 3: Resend - Version 4: Resend arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++ 1 file changed, 116 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..9460d5c 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x009B +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x009B +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x009C +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x009C +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x009C +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x009C +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x009C +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x009C +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x009D +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x009D0003 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x009D +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x009D +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x009D0003 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x009E +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x009E0003 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x009E +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x009E +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x009E0003 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x009F +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x009F0004 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x009F0002 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x009F +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0x00A0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0x00A0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x00A1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x00A5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0x00A2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0x00A0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0x00A1 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x00A10001 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x00A10001 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018
[PATCH 4/4][v3] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids
* Add imx7d SoC iomuxc-lpsr gpio group id's
* Add IOMUXC_LPSR_SUPPORT flag for pinctrl-imx driver to
support iomuxc-lpsr controller.
Signed-off-by: Adrian Alonso aalo...@freescale.com
- Change v1 to v3: resend patch
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..cf89275 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -172,6 +172,14 @@ enum imx7d_pads {
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
+ MX7D_PAD_GPIO1_IO00 = 155,
+ MX7D_PAD_GPIO1_IO01 = 156,
+ MX7D_PAD_GPIO1_IO02 = 157,
+ MX7D_PAD_GPIO1_IO03 = 158,
+ MX7D_PAD_GPIO1_IO04 = 159,
+ MX7D_PAD_GPIO1_IO05 = 160,
+ MX7D_PAD_GPIO1_IO06 = 161,
+ MX7D_PAD_GPIO1_IO07 = 162,
};
/* Pad names for the pinmux subsystem */
@@ -331,11 +339,20 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+ .flags = IOMUXC_LPSR_SUPPORT,
};
static struct of_device_id imx7d_pinctrl_of_match[] = {
--
2.1.4
--
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[PATCH][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
* Change from v1 to v2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
* Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr
base register address.
---
drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..aef4ca3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -38,7 +38,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with normal
iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg |= 0x2;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base
[PATCH 2/4][v3] ARM: dts: imx: imx7d add iomuxc lpsr register base address
* Add iomuxc lpsr register base address to extend
pinctrl-imx driver to support the iomux settings for pins
that support LPSR operation mode.
Signed-off-by: Adrian Alonso aalo...@freescale.com
- Change v1 to v3: resend patch
---
arch/arm/boot/dts/imx7d.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index c42cf8d..294a6c6 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -253,7 +253,7 @@
iomuxc: iomuxc@3033 {
compatible = fsl,imx7d-iomuxc;
- reg = 0x3033 0x1;
+ reg = 0x3033 0x1, 0x302c
0x1;
};
gpr: iomuxc-gpr@3034 {
--
2.1.4
--
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[PATCH 1/4][v3] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
* Add iMX7D SoC imx7d-pinfunc gpio pad settings mux_reg conf_reg input_reg mux_mode input_val * iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most significant bits of input_val to avoid group id overlap bweeten iomuxc and iomuxc-lpsr. Signed-off-by: Adrian Alonso aalo...@freescale.com - Change v1 to v2: Use input_val upper 16 bits to represent pad group id - Change v2 to v3: Resend patch --- arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++ 1 file changed, 116 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..9460d5c 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x009B +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x009B +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x009C +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x009C +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x009C +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x009C +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x009C +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x009C +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x009D +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x009D0003 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x009D +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x009D +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x009D0003 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x009E +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x009E0003 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x009E +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x009E +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x009E0003 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x009F +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x009F0004 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x009F0002 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x009F +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0x00A0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0x00A0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x00A1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x00A5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0x00A2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0x00A0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0x00A1 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x00A10001 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x00A10001 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018
[PATCH 3/4][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
- Change from v1 to v2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
- Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr
base register address.
---
drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..aef4ca3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -38,7 +38,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with normal
iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg |= 0x2;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base
[PATCH 4/4][v2] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids
* Add imx7d SoC iomuxc-lpsr gpio group id's
* Add IOMUXC_LPSR_SUPPORT flag for pinctrl-imx driver to
support iomuxc-lpsr controller.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..cf89275 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -172,6 +172,14 @@ enum imx7d_pads {
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
+ MX7D_PAD_GPIO1_IO00 = 155,
+ MX7D_PAD_GPIO1_IO01 = 156,
+ MX7D_PAD_GPIO1_IO02 = 157,
+ MX7D_PAD_GPIO1_IO03 = 158,
+ MX7D_PAD_GPIO1_IO04 = 159,
+ MX7D_PAD_GPIO1_IO05 = 160,
+ MX7D_PAD_GPIO1_IO06 = 161,
+ MX7D_PAD_GPIO1_IO07 = 162,
};
/* Pad names for the pinmux subsystem */
@@ -331,11 +339,20 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+ .flags = IOMUXC_LPSR_SUPPORT,
};
static struct of_device_id imx7d_pinctrl_of_match[] = {
--
2.1.4
--
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[PATCH 3/4][v2] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
* Version 2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx.c | 73 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..8de1790 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -18,6 +18,7 @@
#include linux/module.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_address.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
#include linux/pinctrl/pinctrl.h
@@ -38,7 +39,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +212,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +245,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with normal
iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +332,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +360,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg
[PATCH 1/4][v2] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
* Add iMX7D SoC imx7d-pinfunc gpio pad settings mux_reg conf_reg input_reg mux_mode input_val * iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most significant bits of input_val to avoid group id overlap bweeten iomuxc and iomuxc-lpsr. * Version 2: Use input_val upper 16 bits to represent pad group id Signed-off-by: Adrian Alonso aalo...@freescale.com ARM: imx: imx7d-pinfunc: add gpio merge me Signed-off-by: Adrian Alonso aalo...@freescale.com --- arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++ 1 file changed, 116 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..9460d5c 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x009B +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x009B +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x009B +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x009C +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x009C +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x009C +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x009C +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x009C +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x009C +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x009D +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x009D0003 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x009D +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x009D +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x009D +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x009D0003 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x009E +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x009E0003 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x009E +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x009E +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x009E +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x009E0003 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x009F +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x009F0001 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x009F0004 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x009F0002 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x009F +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0x00A0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0x00A0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x00A1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x00A5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0x00A2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0x00A0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0x00A1 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x00A10001 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x00A10001 +#define
[PATCH 2/4][v2] ARM: dts: imx: imx7d add iomuxc lpsr register base address
* Add iomuxc lpsr register base address to extend
pinctrl-imx driver to support the iomux settings for pins
that support LPSR operation mode.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
arch/arm/boot/dts/imx7d.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index c42cf8d..294a6c6 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -253,7 +253,7 @@
iomuxc: iomuxc@3033 {
compatible = fsl,imx7d-iomuxc;
- reg = 0x3033 0x1;
+ reg = 0x3033 0x1, 0x302c
0x1;
};
gpr: iomuxc-gpr@3034 {
--
2.1.4
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[PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
* Add iMX7D SoC imx7d-pinfunc gpio pad settings mux_reg conf_reg input_reg mux_mode input_val * iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most significant bits of input_val to avoid group id overlap bweeten iomuxc and iomuxc-lpsr. Signed-off-by: Adrian Alonso aalo...@freescale.com --- arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++ 1 file changed, 116 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..ae7cc1a 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x9B00 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x9B00 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x9C00 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x9C00 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x9C00 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x9C00 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x9C00 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x9C00 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x9D00 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x9D00 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x9D03 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x9D00 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x9D00 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x9D00 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x9D03 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x9E00 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x9E00 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x9E03 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x9E00 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x9E00 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x9E00 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x9E03 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x9F00 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x9F01 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x9F01 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x9F04 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x9F02 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x9F00 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0xA000 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0xA000 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0xA001 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0xA005 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0xA002 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0xA000 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0xA100 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0xA101 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0xA101 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0xA104 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL0x0018
[PATCH 4/4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids
* Add imx7d SoC iomuxc-lpsr gpio group id's
* Add IOMUXC_LPSR_SUPPORT flag for pinctrl-imx driver to
support iomuxc-lpsr controller.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c
b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..cf89275 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -172,6 +172,14 @@ enum imx7d_pads {
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
+ MX7D_PAD_GPIO1_IO00 = 155,
+ MX7D_PAD_GPIO1_IO01 = 156,
+ MX7D_PAD_GPIO1_IO02 = 157,
+ MX7D_PAD_GPIO1_IO03 = 158,
+ MX7D_PAD_GPIO1_IO04 = 159,
+ MX7D_PAD_GPIO1_IO05 = 160,
+ MX7D_PAD_GPIO1_IO06 = 161,
+ MX7D_PAD_GPIO1_IO07 = 162,
};
/* Pad names for the pinmux subsystem */
@@ -331,11 +339,20 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[]
= {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+ .flags = IOMUXC_LPSR_SUPPORT,
};
static struct of_device_id imx7d_pinctrl_of_match[] = {
--
2.1.4
--
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[PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
* Add iMX7D SoC imx7d-pinfunc gpio pad settings mux_reg conf_reg input_reg mux_mode input_val * iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most significant bits of input_val to avoid group id overlap bweeten iomuxc and iomuxc-lpsr. Signed-off-by: Adrian Alonso aalo...@freescale.com --- arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++ 1 file changed, 116 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index a8d8149..ae7cc1a 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -15,6 +15,122 @@ * mux_reg conf_reg input_reg mux_mode input_val */ +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x 0x0030 0x 0x0 0x9B00 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT0x 0x0030 0x 0x1 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x 0x0030 0x 0x2 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B0x 0x0030 0x 0x3 0x9B00 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x 0x0030 0x 0x4 0x9B00 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x 0x0 0x9C00 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT0x0004 0x0034 0x 0x1 0x9C00 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x 0x2 0x9C00 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x 0x3 0x9C00 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x 0x4 0x9C00 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT0x0004 0x0034 0x 0x6 0x9C00 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x 0x0 0x9D00 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT0x0008 0x0038 0x 0x1 0x9D00 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x9D03 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x 0x3 0x9D00 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x 0x5 0x9D00 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT0x0008 0x0038 0x 0x6 0x9D00 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x9D03 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x 0x0 0x9E00 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT0x000C 0x003C 0x 0x1 0x9E00 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x9E03 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x 0x3 0x9E00 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x 0x5 0x9E00 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT0x000C 0x003C 0x 0x6 0x9E00 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x9E03 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x 0x0 0x9F00 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x9F01 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x9F01 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x9F04 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL0x0010 0x0040 0x05D4 0x4 0x9F02 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT0x0010 0x0040 0x 0x6 0x9F00 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x 0x0 0xA000 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR0x0014 0x0044 0x 0x1 0xA000 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0xA001 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0xA005 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA0x0014 0x0044 0x05D8 0x4 0xA002 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT0x0014 0x0044 0x 0x6 0xA000 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x 0x0 0xA100 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0xA101 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0xA101 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0xA104 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL0x0018
[PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
drivers/pinctrl/freescale/pinctrl-imx.c | 75 +++--
drivers/pinctrl/freescale/pinctrl-imx.h | 6 ++-
2 files changed, 57 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..2d434ac 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -18,6 +18,7 @@
#include linux/module.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_address.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
#include linux/pinctrl/pinctrl.h
@@ -38,7 +39,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +212,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +245,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ pin-input_val 24) {
+ writel(pin-input_val, info-base +
pin-input_reg);
+ } else {
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+ }
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +332,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +360,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg |= 0x2;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -386,7 +392,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- *config = readl(ipctl-base + pin_reg
[PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address
* Add iomuxc lpsr register base address to extend
pinctrl-imx driver to support the iomux settings for pins
that support LPSR operation mode.
Signed-off-by: Adrian Alonso aalo...@freescale.com
---
arch/arm/boot/dts/imx7d.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index c42cf8d..294a6c6 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -253,7 +253,7 @@
iomuxc: iomuxc@3033 {
compatible = fsl,imx7d-iomuxc;
- reg = 0x3033 0x1;
+ reg = 0x3033 0x1, 0x302c
0x1;
};
gpr: iomuxc-gpr@3034 {
--
2.1.4
--
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