Re: [PATCH v2] arm: dts: Fix audio card detection on peach boards
Hi Javier,
On Mon, Nov 30, 2015 at 7:31 PM, Javier Martinez Canillas
wrote:
> Hello Alim,
>
> On 10/12/2015 09:37 AM, Alim Akhtar wrote:
>> Since commit 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards"),
>> sound card detection is broken on peach boards and gives below errors:
>>
>> [3.630457] max98090 7-0010: MAX98091 REVID=0x51
>> [3.634233] max98090 7-0010: use default 2.8v micbias
>> [3.640985] snow-audio sound: HiFi <-> 383.i2s mapping ok
>> [3.645307] max98090 7-0010: Invalid master clock frequency
>> [3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe()
>> failed: -22
>> [3.658914] snow-audio sound: snd_soc_register_card failed (-22)
>> [3.664366] snow-audio: probe of sound failed with error -22
>>
>> This patch adds missing assigned-clocks and assigned-clock-parents for
>> pmu_system_controller node which is used as "mclk" for audio codec.
>>
>> Signed-off-by: Alim Akhtar
>> Fixes: 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards")
>
> I found that this patch is not enough to have proper audio working
> on an Exynos5800 Peach Pi. Even playing a simple wav does not work:
>
> $ time aplay -D sysdefault /usr/share/sounds/alsa/Front_Center.wav
> Playing WAVE '/usr/share/sounds/alsa/Front_Center.wav' : Signed 16 bit Little
> Endian, Rate 48000 Hz, Mono
>
> real0m1.138s
> user0m0.005s
> sys 0m0.005s
>
> This should be ~1.5 seconds so audio is processed faster than expected.
>
Did you tried playing any other file, like 128 KHz rate files etc..?
> So something else besides making the CLKOUT to provide a valid frequency
> for the codec's master clock is needed.
>
The $SUBJECT patch actually fix the audio card detection issue, which
was failing because of the missing master clock.
> Do you know what's missing in mainline? For instance, I see that the
> sound/soc/samsung/snow.c ASoC machine driver doesn't have a hw_params
> but I'm not that familiar with ALSA to know if that makes sense or not.
>
I need to check this, currently I am out on a business travel, so
won't be able to check.
Probably we can go back to before "2fad972d45c4" and check that.
> Also, do you know if the "simple-audio-card" can be used instead for
> snow and peachs as it is used for other Exynos5 boards or a specific
> ASoC machine driver is really needed for these Chromebooks?
>
Not sure, AFAIR, I used machine driver on chromebooks (snow and peach).
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
> --
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--
Regards,
Alim
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[PATCH v3 5/5] ARM: exynos: select POWER_RESET_SYSCON and POWER_RESET_SYSCON_POWEROFF
Since we switch to use generic syscon regmap based reset/poweroff
driver for exynos SoC, lets select it from ARCH_EXYNOS instead of
enabling it from various defconfigs. This also select POWER_RESET
as SYSCON-{reset, poweroff} drivers depends on it.
Also because of the above changes we don't need special handling
for reboot/poweroff in exynos pmu driver. This patch also removes
the same from exynos pmu driver to keep git bisect working.
Note: This will break reboot/poweroff on boards with older dtbs
with a newer kernel.
Signed-off-by: Alim Akhtar
Reviewed-by: Javier Martinez Canillas
Acked-by: Moritz Fischer
---
arch/arm/mach-exynos/Kconfig |3 +++
arch/arm/mach-exynos/pmu.c | 43 --
2 files changed, 3 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a8317a..d279edf9b10d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,9 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+ select POWER_RESET
+ select POWER_RESET_SYSCON
+ select POWER_RESET_SYSCON_POWEROFF
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index de68938ee6aa..393c04aa727e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,9 +14,6 @@
#include
#include
#include
-#include
-#include
-
#include "exynos-pmu.h"
#include "regs-pmu.h"
@@ -681,23 +678,6 @@ static unsigned int const
exynos5420_list_disable_pmu_reg[] = {
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
};
-static void exynos_power_off(void)
-{
- unsigned int tmp;
-
- pr_info("Power down.\n");
- tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
- tmp ^= (1 << 8);
- pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
-
- /* Wait a little so we don't give a false warning below */
- mdelay(100);
-
- pr_err("Power down failed, please power off system manually.\n");
- while (1)
- ;
-}
-
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
{
u32 this_cluster;
@@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void)
pr_info("EXYNOS5420 PMU initialized\n");
}
-static int pmu_restart_notify(struct notifier_block *this,
- unsigned long code, void *unused)
-{
- pmu_raw_writel(0x1, EXYNOS_SWRESET);
-
- return NOTIFY_DONE;
-}
-
static const struct exynos_pmu_data exynos3250_pmu_data = {
.pmu_config = exynos3250_pmu_config,
.pmu_init = exynos3250_pmu_init,
@@ -940,20 +912,11 @@ static const struct of_device_id
exynos_pmu_of_device_ids[] = {
{ /*sentinel*/ },
};
-/*
- * Exynos PMU restart notifier, handles restart functionality
- */
-static struct notifier_block pmu_restart_handler = {
- .notifier_call = pmu_restart_notify,
- .priority = 128,
-};
-
static int exynos_pmu_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmu_base_addr = devm_ioremap_resource(dev, res);
@@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pmu_context);
- ret = register_restart_handler(&pmu_restart_handler);
- if (ret)
- dev_warn(dev, "can't register restart handler err=%d\n", ret);
-
- pm_power_off = exynos_power_off;
-
dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
--
1.7.10.4
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[PATCH v3 4/5] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5410 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos5410.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
index 731eefd23fa9..fad0779b1b6e 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -102,6 +102,20 @@
reg = <0x1004 0x5000>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
mct: mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0xB00>;
--
1.7.10.4
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[PATCH v3 3/5] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos5.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 110dbd4fb884..e2439e87ee4a 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -88,6 +88,20 @@
status = "disabled";
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
fimd: fimd@1440 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
--
1.7.10.4
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[PATCH v3 2/5] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos4 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Tested-by: Tobias Jakobi
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos4.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3184e10f260a..07e10ee60bd8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -158,6 +158,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
dsi_0: dsi@11C8 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C8 0x1>;
--
1.7.10.4
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[PATCH v3 1/5] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos3250.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2f30d632f1cc..18e3deffbf48 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* Reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
--
1.7.10.4
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[PATCH v3 0/5] Switch to generic syscon regmap based drivers
Now we have a nice way to reboot/poweroff system using a generic
syscon regmap based drivers, this series moves exynos SoCs to
make use of the same.
Changes since v2:
* Merged patch 5 and 6 to keep git bisect happy
Changes since v1:
* Added a comment about the register information
* Droped defconfig changes as disscussed
* Collected various Reviewed-by, Tested-by and Acked-by tags
* Added SYSCON-{RESET, POWEROFF} to select from Kconfig
Alim Akhtar (5):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos: select POWER_RESET_SYSCON and
POWER_RESET_SYSCON_POWEROFF
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/mach-exynos/Kconfig |3 +++
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 59 insertions(+), 43 deletions(-)
--
1.7.10.4
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Krzysztof,
On 11/20/2015 06:16 AM, Krzysztof Kozlowski wrote:
On 20.11.2015 03:06, Alim Akhtar wrote:
Hi Krzysztof/Ulf/Kukjin
On Thu, Oct 22, 2015 at 5:47 AM, Krzysztof Kozlowski
wrote:
On 22.10.2015 00:01, Alim Akhtar wrote:
On Wed, Oct 21, 2015 at 8:25 PM, Javier Martinez Canillas
wrote:
Hello Alim,
On 10/21/2015 04:50 PM, Alim Akhtar wrote:
[snip]
[0]:
From c9b250ee03bae338339b70693e906145c719f783 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas
Date: Wed, 21 Oct 2015 11:59:44 +0200
Subject: [RFT PATCH] mmc: pwrseq: Use highest priority for eMMC restart
handler
The pwrseq_emmc driver does a eMMC card reset before a system reboot to
allow broken or limited ROM boot-loaders, that don't have an eMMC reset
logic, to be able to read the second stage from the eMMC.
But this has to be called before a system reboot handler and while most
of them use the priority 128, there are other restart handlers (such as
the syscon-reboot one) that use a higher priority. So, use the highest
priority to make sure that the eMMC hw is reset before a system reboot.
Signed-off-by: Javier Martinez Canillas
---
Looks good.
Reviewed-by: Alim Akhtar
+Cc Ulf,
Javier,
First of all, thanks Javier for digging into the issue. Actually I have
Odroid U3 but because of user-space limitations (which I need for other
work) I cannot test all of mainline patches there.
Thanks, should I post it as a proper patch or are adding it to your
series?
Suggest you to post as a patch collecting {Tested, Reviewed}-by (easy
for maintainers to pickup ) and probably CCing Ulf for his feedback.
I think the latter is more reasonable so with an ack from Ulf,
all patches can go through the linux-samsung tree.
yes, that is reasonable, as I said, let Krzysztof and Ulf take a call here.
Javier, Alim, Ulf,
I am not grabbing any more patches for v4.4 because I doubt that they
could be merged to arm-soc for this cycle. My last pull requests for
v4.4 is still pending...
This means that I plan to pick up these series for v4.5, after closing
v4.4 merge window (unless Kukjin picks it also). Because of that, we
have plenty of time, so my idea is:
1. Wait for some comments from Ulf on Javier's fix.
2. If the fix goes into v4.4, then problem solved.
3. If not and it get acked, then it can go with this set.
4. If not and it get applied by Ulf for v4.5, then a tag from him would
be a nice way to solve dependency.
Either way we don't have to hurry, I think.
Is It the right time to get this series in?
Thanks!!
I started applying it but stopped at #5. It should be squashed with #6
to get rid of (not important) conflict between syscon reboot and
existing Exynos restart handler:
syscon-poweroff syscon-poweroff: pm_power_off already claimed c001e52c
exynos_power_off
syscon-poweroff: probe of syscon-poweroff failed with error -16
The conflict is not really an issue because of ordering of init calls
the Exynos will register itself before syscon. Nevertheless splitting
the patches does not really make sense... so please merge #5 with #6.
Hmm...nice catch..will send v3 shortly after merging patch #5 and #6.
Best regards,
Krzysztof
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Krzysztof/Ulf/Kukjin
On Thu, Oct 22, 2015 at 5:47 AM, Krzysztof Kozlowski
wrote:
> On 22.10.2015 00:01, Alim Akhtar wrote:
>> On Wed, Oct 21, 2015 at 8:25 PM, Javier Martinez Canillas
>> wrote:
>>> Hello Alim,
>>>
>>> On 10/21/2015 04:50 PM, Alim Akhtar wrote:
>>>
>>> [snip]
>>>
>>>>>
>>>>> [0]:
>>>>> From c9b250ee03bae338339b70693e906145c719f783 Mon Sep 17 00:00:00 2001
>>>>> From: Javier Martinez Canillas
>>>>> Date: Wed, 21 Oct 2015 11:59:44 +0200
>>>>> Subject: [RFT PATCH] mmc: pwrseq: Use highest priority for eMMC restart
>>>>> handler
>>>>>
>>>>> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
>>>>> allow broken or limited ROM boot-loaders, that don't have an eMMC reset
>>>>> logic, to be able to read the second stage from the eMMC.
>>>>>
>>>>> But this has to be called before a system reboot handler and while most
>>>>> of them use the priority 128, there are other restart handlers (such as
>>>>> the syscon-reboot one) that use a higher priority. So, use the highest
>>>>> priority to make sure that the eMMC hw is reset before a system reboot.
>>>>>
>>>>> Signed-off-by: Javier Martinez Canillas
>>>>> ---
>>>> Looks good.
>>>> Reviewed-by: Alim Akhtar
>>>>
>>>
>
> +Cc Ulf,
>
> Javier,
>
> First of all, thanks Javier for digging into the issue. Actually I have
> Odroid U3 but because of user-space limitations (which I need for other
> work) I cannot test all of mainline patches there.
>
>
>>> Thanks, should I post it as a proper patch or are adding it to your
>>> series?
>> Suggest you to post as a patch collecting {Tested, Reviewed}-by (easy
>> for maintainers to pickup ) and probably CCing Ulf for his feedback.
>>
>>> I think the latter is more reasonable so with an ack from Ulf,
>>> all patches can go through the linux-samsung tree.
>>>
>> yes, that is reasonable, as I said, let Krzysztof and Ulf take a call here.
>
> Javier, Alim, Ulf,
>
> I am not grabbing any more patches for v4.4 because I doubt that they
> could be merged to arm-soc for this cycle. My last pull requests for
> v4.4 is still pending...
>
> This means that I plan to pick up these series for v4.5, after closing
> v4.4 merge window (unless Kukjin picks it also). Because of that, we
> have plenty of time, so my idea is:
> 1. Wait for some comments from Ulf on Javier's fix.
> 2. If the fix goes into v4.4, then problem solved.
> 3. If not and it get acked, then it can go with this set.
> 4. If not and it get applied by Ulf for v4.5, then a tag from him would
> be a nice way to solve dependency.
>
> Either way we don't have to hurry, I think.
>
Is It the right time to get this series in?
Thanks!!
> Best regards,
> Krzysztof
--
Regards,
Alim
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Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi
Thanks again for looking into this.
On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 +
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 85 +
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+=
phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
This is similar to the first version of your patch without EXPORT_SYMBOL.
I think you have to create a new generic PHY_OPS for calibrate PHY while making
sure that it is as generic as possible (which means calibrate_phy shouldn't
have tag and pwr arguments or a strong justification as to why those arguments
are required in a generic API).
I don't see the advantage to making this a generic phy_ops, this is
exynos specific ufs-phy, please have a look at other implementations
drivers/phy/phy-qcom-ufs.c (which I belive mereged recently)
may be other vendors might come with th
Re: [PATCH v5 00/11] exynos-ufs: add support for Exynos
Hi Kishon,
Any more concern on the PHY part of this series?
Thanks!
On Mon, Nov 9, 2015 at 10:56 AM, Alim Akhtar wrote:
> This patch-set introduces UFS (Universal Flash Storage) host support
> for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific
> driver.
> And it also contains some quirks handling for Exynos.
>
> NOTE: ** This series has a dependency on [4]. **
>
> -Changes since v4:
> * Removed platform specific PHY ops as suggested by Kishon
> * Rebased on the top of Yaniv Gardi's work [4]
> * make use of newly introduce ufshcd_{get,set}_variant
> * other small changes and improvements.
> * rebased on the top of linux next-20151109
>
> -Changes since v3:
> * Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
> * Restructure the driver to make it as a platform driver, rebased on top of
> [4].
> * Addressed review comments from Arnd Bergmann[5].
> * Other misc changes and improvements.
>
> -Changes since v2:
> * Addressed review comments from Kishon[1] and Rob Herring [2]
> * Splited ufs dt binding documetation from ufs driver patch
>
> -Changes since v1:
> * Addressed review comments from Alexey[3] and various review comments from
> Amit.
> * Updated email id of Seungwon as his samsung id is void now.
> * Added ufs platform data
>
> [1]-> https://lkml.org/lkml/2015/9/18/29
> [2]-> https://lkml.org/lkml/2015/9/21/668
> [3]-> https://lkml.org/lkml/2015/8/23/124
> [4]-> https://lkml.org/lkml/2015/10/28/271
> [5]-> https://lkml.org/lkml/2015/10/1/402
>
> This patch set is tested on exynos7-espresso board.
>
>
> Alim Akhtar (1):
> Documentation: samsung-phy: Add dt bindings for UFS
>
> Seungwon Jeon (10):
> phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
> scsi: ufs: add quirk to contain unconformable utrd field
> scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
> scsi: ufs: add quirk not to allow reset of interrupt aggregation
> scsi: ufs: add quirk to enable host controller without hce
> scsi: ufs: add specific callback for nexus type
> scsi: ufs: add add specific callback for hibern8
> scsi: ufs: make ufshcd_config_pwr_mode of non-static func
> Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
> controller
> scsi: ufs-exynos: add UFS host support for Exynos SoCs
>
> .../devicetree/bindings/phy/samsung-phy.txt| 22 +
> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
> drivers/phy/Kconfig|7 +
> drivers/phy/Makefile |1 +
> drivers/phy/phy-exynos-ufs.c | 241
> drivers/phy/phy-exynos-ufs.h | 85 ++
> drivers/phy/phy-exynos7-ufs.h | 89 ++
> drivers/scsi/ufs/Kconfig | 12 +
> drivers/scsi/ufs/Makefile |1 +
> drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
> drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
> drivers/scsi/ufs/ufs-exynos.c | 1304
>
> drivers/scsi/ufs/ufs-exynos.h | 247
> drivers/scsi/ufs/ufshcd.c | 168 ++-
> drivers/scsi/ufs/ufshcd.h | 54 +
> drivers/scsi/ufs/ufshci.h | 26 +-
> drivers/scsi/ufs/unipro.h | 47 +
> include/linux/phy/phy-exynos-ufs.h | 85 ++
> 18 files changed, 2647 insertions(+), 20 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> create mode 100644 drivers/phy/phy-exynos-ufs.c
> create mode 100644 drivers/phy/phy-exynos-ufs.h
> create mode 100644 drivers/phy/phy-exynos7-ufs.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
> create mode 100644 include/linux/phy/phy-exynos-ufs.h
>
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Regards,
Alim
--
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Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
Hi Rob, On 11/09/2015 09:53 PM, Rob Herring wrote: On Mon, Nov 09, 2015 at 10:56:26AM +0530, Alim Akhtar wrote: From: Seungwon Jeon This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- .../devicetree/bindings/ufs/ufs-exynos.txt | 104 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt new file mode 100644 index ..08e2d1497b1b --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt @@ -0,0 +1,104 @@ +* Exynos Universal Flash Storage (UFS) Host Controller + +UFSHC nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. + +Required properties: +- compatible: compatible name, contains "samsung,exynos7-ufs" +- interrupts: +- reg : Should contain HCI, vendor specific, UNIPRO and + UFS protector address space +- reg-names: "hci", "vs_hci", "unipro", "ufsp"; No phy for MPHY? ufs-phy is documented, see 01/11 of this series. + +Optional properties: +- vdd-hba-supply: phandle to UFS host controller supply regulator node +- vcc-supply: phandle to VCC supply regulator node +- vccq-supply : phandle to VCCQ supply regulator node +- vccq2-supply : phandle to VCCQ2 supply regulator node +- vcc-supply-1p8: For embedded UFS devices, valid VCC range is 1.7-1.95V + or 2.7-3.6V. This boolean property when set, specifies + to use low voltage range of 1.7-1.95V. Note for external + UFS cards this property is invalid and valid VCC range is + always 2.7-3.6V. +- vcc-max-microamp : specifies max. load that can be drawn from vcc supply +- vccq-max-microamp : specifies max. load that can be drawn from vccq supply +- vccq2-max-microamp: specifies max. load that can be drawn from vccq2 supply Some of these are supplies to the flash chip, so you should make these common properties (in a common doc). Ah, yes these are duplicated, already documented in common ufshcd file Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt What is the recommended way, do I need to include it here as well? or just mentioning that "same as documented in ufshcd-pltfrm.txt"? +- -fixed-regulator : boolean property specifying that -supply is a fixed regulator This should be determined from the regulator. Same as above already documented as part of ufshcd-pltfrm binding. + +- clocks: List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. + "core", "sclk_unipro_main", "ref" and ref_parent + +- freq-table-hz: Array of operating frequencies stored in the same + order as the clocks property. If this property is not + defined or a value in the array is "0" then it is assumed + that the frequency is set by the parent clock or a + fixed rate clock source. +- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock +- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are + "FAST", "SLOW", "FAST_auto" and "SLOW_auto" ufs is not a vendor. Use a '-' rather than ','. Ok will change. +- ufs,pwr-attr-lane : specifies lane count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-gear : specifies gear count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change + can be one of "HS_rate_b" or "HS_rate_a" +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values + 3 timers supported + +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values + 3 timers supported + +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY, + this is a boolean property. +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY, + allowed step size is 0 to 3 +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY +
Re: [rtc-linux] Re: [PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
Hi Krzysztof, On 11/07/2015 08:39 AM, Krzysztof Kozlowski wrote: W dniu 07.11.2015 o 07:33, Rob Herring pisze: On Fri, Oct 30, 2015 at 11:55:31AM +0530, Alim Akhtar wrote: From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. This also supports RTC and three 32.768KHz clock outputs. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..4c0543ceec25 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 s5m8767 doesn't seem to be documented. Can you please fix or remove. What exactly do you have in mind? The s5m8767-clk is already documented as part of clk-s2mps11.c driver: Documentation/devicetree/bindings/mfd/s2mps11.txt The main s5m8767 MFD driver is documented as part of regulator driver: Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt Yes, this may be confusing... They S2M and S5M family devices share: - main mfd driver, - rtc driver, - clk driver. but regulator drivers are separate. Indeed things are documented but in very confusing manners, e.g. compatible name "samsung,s5m8767-pmic" belongs to MFD not regulator. It should have being in */bindings/mfd/s2mps11.txt Not sure if it make sense to change it though. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1304 ++
drivers/scsi/ufs/ufs-exynos.h| 247
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1810 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
+
+static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct
[PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
From: Seungwon Jeon
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index ..08e2d1497b1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,104 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible name, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg : Should contain HCI, vendor specific, UNIPRO and
+ UFS protector address space
+- reg-names: "hci", "vs_hci", "unipro", "ufsp";
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ "core", "sclk_unipro_main", "ref" and ref_parent
+
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change, possible
values are
+ "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+ can be one of "HS_rate_b" or "HS_rate_a"
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
+ allowed step size is 0 to 3
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+range is 1 to 9
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+
[PATCH v5 08/11] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 33 +
drivers/scsi/ufs/ufshcd.h | 10 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index eeb7835c52ab..075b7bf13080 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2394,7 +2403,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2403,7 +2412,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2418,6 +2427,22 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ ufshcd_vops_hibern8_notify(hba, en, PRE_CHANGE);
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ ufshcd_vops_hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index b3dd08420100..9c69dd2f3672 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -283,6 +285,7 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
@@ -830,4 +833,11 @@ static inline void
ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
if (hba->vops && hba->vops->specify_nexus_t_tm_req)
hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
}
+
+static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
+ bool en, enum ufs_notify_change_status status)
+{
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, status);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v5 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 075b7bf13080..358d9114a1a5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2592,7 +2590,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2608,6 +2606,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9c69dd2f3672..8cad52c072d4 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -666,6 +666,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v5 07/11] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 +++
drivers/scsi/ufs/ufshcd.h | 19 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e8b96ec65987..eeb7835c52ab 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1579,7 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3842,6 +3844,7 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ ufshcd_vops_specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 500e137bf68a..b3dd08420100 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -259,6 +259,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -280,6 +283,9 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void(*dbg_register_dump)(struct ufs_hba *hba);
@@ -811,4 +817,17 @@ static inline void ufshcd_vops_dbg_register_dump(struct
ufs_hba *hba)
hba->vops->dbg_register_dump(hba);
}
+static inline void ufshcd_vops_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+ int tag, struct ufshcd_lrb *lrbp)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
+}
+
+static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
+ int free_slot, u8 tm_function)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v5 06/11] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 75 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ca7483cd899e..e8b96ec65987 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2715,6 +2761,31 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 4ae32e9316de..500e137bf68a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -485,6 +485,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 05/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2b16eb363203..ca7483cd899e 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3199,7 +3199,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index d625d01110b0..4ae32e9316de 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -479,6 +479,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 587a9c8fbfe9..2b16eb363203 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -356,7 +356,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3685,7 +3702,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6cd542a803d5..d625d01110b0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -474,6 +474,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 03/11] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 131c72038bf8..587a9c8fbfe9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2570d9477b37..6cd542a803d5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -467,6 +467,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
+* word, but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 +
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 85 +
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+=
phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+void exynos_u
[PATCH v5 01/11] Documentation: samsung-phy: Add dt bindings for UFS
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/phy/samsung-phy.txt| 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 0289d3b07853..565200d72e91 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -177,3 +177,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
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[PATCH v5 00/11] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support
for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver.
And it also contains some quirks handling for Exynos.
NOTE: ** This series has a dependency on [4]. **
-Changes since v4:
* Removed platform specific PHY ops as suggested by Kishon
* Rebased on the top of Yaniv Gardi's work [4]
* make use of newly introduce ufshcd_{get,set}_variant
* other small changes and improvements.
* rebased on the top of linux next-20151109
-Changes since v3:
* Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
* Restructure the driver to make it as a platform driver, rebased on top of [4].
* Addressed review comments from Arnd Bergmann[5].
* Other misc changes and improvements.
-Changes since v2:
* Addressed review comments from Kishon[1] and Rob Herring [2]
* Splited ufs dt binding documetation from ufs driver patch
-Changes since v1:
* Addressed review comments from Alexey[3] and various review comments from
Amit.
* Updated email id of Seungwon as his samsung id is void now.
* Added ufs platform data
[1]-> https://lkml.org/lkml/2015/9/18/29
[2]-> https://lkml.org/lkml/2015/9/21/668
[3]-> https://lkml.org/lkml/2015/8/23/124
[4]-> https://lkml.org/lkml/2015/10/28/271
[5]-> https://lkml.org/lkml/2015/10/1/402
This patch set is tested on exynos7-espresso board.
Alim Akhtar (1):
Documentation: samsung-phy: Add dt bindings for UFS
Seungwon Jeon (10):
phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
scsi: ufs: add quirk to contain unconformable utrd field
scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
scsi: ufs: add quirk not to allow reset of interrupt aggregation
scsi: ufs: add quirk to enable host controller without hce
scsi: ufs: add specific callback for nexus type
scsi: ufs: add add specific callback for hibern8
scsi: ufs: make ufshcd_config_pwr_mode of non-static func
Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
controller
scsi: ufs-exynos: add UFS host support for Exynos SoCs
.../devicetree/bindings/phy/samsung-phy.txt| 22 +
.../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 ++
drivers/phy/phy-exynos7-ufs.h | 89 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile |1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1304
drivers/scsi/ufs/ufs-exynos.h | 247
drivers/scsi/ufs/ufshcd.c | 168 ++-
drivers/scsi/ufs/ufshcd.h | 54 +
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
include/linux/phy/phy-exynos-ufs.h | 85 ++
18 files changed, 2647 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
--
1.7.10.4
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Re: [PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
Hi Rob, On Sat, Nov 7, 2015 at 4:03 AM, Rob Herring wrote: > On Fri, Oct 30, 2015 at 11:55:31AM +0530, Alim Akhtar wrote: >> From: Thomas Abraham >> >> Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device >> is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. >> This also supports RTC and three 32.768KHz clock outputs. >> >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Thomas Abraham >> Signed-off-by: Alim Akhtar >> --- >> Documentation/devicetree/bindings/mfd/s2mps11.txt | 21 >> ++--- >> 1 file changed, 14 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt >> b/Documentation/devicetree/bindings/mfd/s2mps11.txt >> index 890f0b0e1643..4c0543ceec25 100644 >> --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt >> +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt >> @@ -1,5 +1,5 @@ >> >> -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current >> Regulator >> +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator >> >> The Samsung S2MPS11 is a multi-function device which includes voltage and >> current regulators, RTC, charger controller and other sub-blocks. It is >> @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. >> Each sub-block is >> addressed by the host system using different I2C slave addresses. >> >> Required properties: >> -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" >> - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". >> +- compatible: Should be one of the following >> + - "samsung,s2mps11-pmic" >> + - "samsung,s2mps13-pmic" >> + - "samsung,s2mps14-pmic" >> + - "samsung,s2mps15-pmic" >> + - "samsung,s2mpu02-pmic". >> - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. >> >> Optional properties: >> @@ -24,7 +28,7 @@ Optional properties: >>unwanted buck warm reset (setting buck voltages to default values). >> >> Optional nodes: >> -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered >> 32.768 >> +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) >> buffered 32.768 > > s5m8767 doesn't seem to be documented. Can you please fix or remove. > Ok, will take a look. > Rob > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] arm64: dts: exynos7: Add pmic s2mps15 device tree node
Hi Krzysztof
On 11/02/2015 07:22 PM, Krzysztof Kozlowski wrote:
2015-11-02 22:01 GMT+09:00 Alim Akhtar :
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 349
+++
1 file changed, 349 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 838a3626dac1..8ce04a0ec928 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -53,6 +53,355 @@
status = "okay";
};
+&hsi2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20>;
+ status = "okay";
+
+ s2mps15_pmic@66 {
+ compatible = "samsung,s2mps15-pmic";
+ reg = <0x66>;
+ interrupts = <2 0>;
+ interrupt-parent = <&gpa0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq>;
+ wakeup-source;
+
+ s2mps15_osc: clocks {
+ compatible = "samsung,s2mps13-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps13_ap", "s2mps13_cp",
+ "s2mps13_bt";
+ };
Don't you want to use one of these clocks for s3c-rtc (&rtc node)?
yes, you are right, rtc on this board is currently broken, mainly because of
the introduction of rtc_src clock in the s3c-rtc driver.
That is on my do list next. will take a look.
Are you suggesting to remove this -clk node now and add along with rtc
changes? I feel this should go in along with this patch.
Just add it in consecutive patch in this series. You added here some
providers (clock and regulators) without consumers. This of course
looks good as a way of providing full description of the board but:
1. For regulators always on: may be meaningless for kernel. Kernel
does not use it. Existence of regulator subnode will fulfill driver's
needs for probe.
2. For clocks: actually will disable these clocks because of lack of
consumers... which is fine but probably not what you wanted.
The standard approach is to add such providers when they are needed -
there are some consumers using them.
OK. for now will keep the pmic clock added as clock will be in disabled
state, so it wont harm.
- will keep system related regulator like supply to arm,mif,int etc ..
will remove supplies to other peripherals IPs. Hope thats fine.
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_ldo1";
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <90>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
(...)
+
+ buck10_reg: BUCK10 {
+ regulator-name = "vdd_buck10";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <300>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <25000>;
+ regulator-enable-ramp-delay = <250>;
+ };
All of these ldo3 and bucks in vendor tree for Espresso board have
ramp delay of 12000. Also they don't have enable-ramp-delay set and
voltages sometimes differ. I don't have S2MPS15 datasheet so I don't
know what is the true value... I'll leave it up to you but it looks
suspicious.
These values generally comes from our board design team, so I cann't really
comment on that, it may vary from board revision etc.
I will check if we have any updated version of recommended value and update
accordingly.
Okay, just pointing the difference. I cannot verify them.
+ };
+ };
+};
What will be the benefit of defining all of these regulators if they
are always on and without consumers? No one will disable them, no one
will change the voltage. Please provide some consumers.
As many drivers are not yet enabled in arm64 defconfig, that is one of the
reason why we are not seeing many consumer for these nodes.
That is not a problem. Please send a patch changing the defconfig.
Usually defconfig (for armv7 this would be exynos and multi_v7) should
provide bootable and working environment for all of our supported
boards.
This is the ground work being done for enabling those. If you insist will
try to reduce what is being used now. Moreover this was used to verify
functionality of pmic driver as well.
Actually as
Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Kishon,
Thanks for your time.
On 10/28/2015 06:23 PM, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 25 October 2015 05:34 PM, Alim Akhtar wrote:
Hi Kishon
Thanks again for you review.
On Fri, Oct 23, 2015 at 8:48 PM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 October 2015 08:38 AM, Alim Akhtar wrote:
+CCing kishon Vijay,
On 10/14/2015 06:25 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317
++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
.
.
.
.
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c
b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
.
.
.
.
+
+#define PWR_MODE_STR_LEN64
+static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
+struct ufs_pa_layer_attr *pwr_max,
+struct ufs_pa_layer_attr *pwr_req)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+struct exynos_ufs_phy_info *phy_info = phy_get_drvdata(ufs->phy);
This is abusing the interface. phy_get_drvdata is meant to be used only
by the PHY driver.
+struct exynos_ufs_phy_specific_ops *phy_ops =
+phy_info->phy_specific_ops;
I'm really not happy about having platform specific ops for PHY. We have
to see if existing PHY ops can be used for this or in worst case add new
PHY ops.
Well you said you like the controller driver to use only PHY ops[1], I
am sorry If I misunderstood that point, can you please help me to
understand that?
I meant PHY generic ops and not PHY ops.
Ok, got it, will use only generic phy here in controller driver.
- Will remove the platform specific PHY ops from phy driver introduce in
this series (patch 02/11)
[1]-> https://lkml.org/lkml/2015/9/18/29
+struct uic_pwr_mode *pwr = &ufs->pwr_act;
+char pwr_str[PWR_MODE_STR_LEN] = "";
+int ret = 0;
+
+if (ufs->drv_data->post_pwr_change)
+ufs->drv_data->post_pwr_change(ufs, pwr);
+
+if (IS_UFS_PWR_MODE_HS(pwr->mode)) {
+switch (pwr->hs_series) {
+case PA_HS_MODE_A:
+case PA_HS_MODE_B:
+phy_ops->calibrate_phy(ufs->phy, CFG_POST_PWR_HS,
+PWR_MODE_HS(pwr->gear, pwr->hs_series));
+break;
+}
+
+ret = phy_ops->wait_for_lock_acq(ufs->phy);
+snprintf(pwr_str, sizeof(pwr_str), "Fast%s series_%s G_%d L_%d",
+pwr->mode == FASTAUTO_MODE ? "_Auto" : "",
+pwr->hs_series == PA_HS_MODE_A ? "A" : "B",
+pwr->gear, pwr->lane);
+} else if (IS_UFS_PWR_MODE_PWM(pwr->mode)) {
+snprintf(pwr_str, sizeof(pwr_str), "Slow%s G_%d L_%d",
+pwr->mode == SLOWAUTO_MODE ? "_Auto" : "",
+pwr->gear, pwr->lane);
+}
+
+dev_info(hba->dev, "Power mode change %d : %s\n", ret, pwr_str);
+return ret;
+}
+
+static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+int tag, struct scsi_cmnd *cmd)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+u32 type;
+
+type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
+
+if (cmd)
+hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
+else
+hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
+}
+
+static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
+int tag, u8 func)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+u32 type;
+
+type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
+
+switch (func) {
+case UFS_ABORT_TASK:
+case UFS_QUERY_TASK:
+hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
+break;
+case UFS_ABORT_TASK_SET:
+case UFS_CLEAR_TASK_SET:
+case UFS_LOGICAL_RESET:
+case UFS_QUERY_TASK_SET:
+hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
+break;
+}
+}
+
+static void exynos_ufs_phy_init(struct exynos_ufs
Re: [PATCH 1/2] arm64: dts: exynos7: Add pmic s2mps15 device tree node
On 11/02/2015 05:55 PM, Krzysztof Kozlowski wrote:
2015-11-02 19:04 GMT+09:00 Alim Akhtar :
This patch add pmic (s2mps15) node of espresso board,
This patch adds PMIC (S2MPS15)...
which includes addition of regulators and pmic-clk sub-nodes.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Alim Akhtar
---
This patch should go in after driver side changes [1] lands.
[1]->
https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg47736.html
Eh? Why? Usually there is not such requirement.
Got it, I just thought without driver changes these dts modification
does not make sense. Thanks for clarification.
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 349 +++
1 file changed, 349 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 838a3626dac1..8ce04a0ec928 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -53,6 +53,355 @@
status = "okay";
};
+&hsi2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20>;
+ status = "okay";
+
+ s2mps15_pmic@66 {
+ compatible = "samsung,s2mps15-pmic";
+ reg = <0x66>;
+ interrupts = <2 0>;
+ interrupt-parent = <&gpa0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq>;
+ wakeup-source;
+
+ s2mps15_osc: clocks {
+ compatible = "samsung,s2mps13-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps13_ap", "s2mps13_cp",
+ "s2mps13_bt";
+ };
Don't you want to use one of these clocks for s3c-rtc (&rtc node)?
yes, you are right, rtc on this board is currently broken, mainly
because of the introduction of rtc_src clock in the s3c-rtc driver.
That is on my do list next. will take a look.
Are you suggesting to remove this -clk node now and add along with rtc
changes? I feel this should go in along with this patch.
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_ldo1";
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <90>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "vdd_ldo2";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <330>;
+ regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "vdd_ldo3";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "vdd_ldo4";
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <111>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "vdd_ldo5";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "vdd_ldo6";
+ regulator-min-microvolt = <225>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo7_reg: LDO7 {
+
Re: [PATCH 2/2] arm64: dts: exynos7: Enable HS200 mode operation
Hi Krzysztof,
On 11/02/2015 05:28 PM, Krzysztof Kozlowski wrote:
Subject - name of the board at the end (not the name of the SoC):
arm64: dts: Enable HS200 mode operation on exynos7-espresso
2015-11-02 19:04 GMT+09:00 Alim Akhtar :
This patch enables HS200 mode operation on exynos7 based
espresso board.
This also remove _broken-cd_ property as per mmc binding documentation
s/remove/removes/
which say one of the properties between broken-cd and non-removable
s/say/says/
should be used. And we already use _non-removable_ as emmc mounted
on board which is a non-removable device.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 8ce04a0ec928..7f19b99fc85b 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -405,8 +405,8 @@
&mmc_0 {
status = "okay";
num-slots = <1>;
- broken-cd;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
The "mmc-ddr-1_8v" should also be supported but I guess you did not
add it on purpose?
Well, I have not tested it, that why didn't added. Will check if this
works then will add.
Thanks for your comments.
Best regards,
Krzysztof
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Re: [PATCH 1/2] arm64: dts: exynos7: Add pmic s2mps15 device tree node
On 11/02/2015 05:00 PM, Javier Martinez Canillas wrote:
Hello Alim,
This patch looks mostly good to me, I just have two comments below:
On 11/02/2015 11:04 AM, Alim Akhtar wrote:
This patch add pmic (s2mps15) node of espresso board,
which includes addition of regulators and pmic-clk sub-nodes.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Alim Akhtar
---
This patch should go in after driver side changes [1] lands.
[1]->
https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg47736.html
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 349 +++
1 file changed, 349 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 838a3626dac1..8ce04a0ec928 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -53,6 +53,355 @@
status = "okay";
};
+&hsi2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20>;
+ status = "okay";
+
+ s2mps15_pmic@66 {
+ compatible = "samsung,s2mps15-pmic";
+ reg = <0x66>;
+ interrupts = <2 0>;
Maybe using IRQ_TYPE_NONE instead of 0?
Ok will check
+ interrupt-parent = <&gpa0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq>;
+ wakeup-source;
+
+ s2mps15_osc: clocks {
+ compatible = "samsung,s2mps13-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps13_ap", "s2mps13_cp",
+ "s2mps13_bt";
+ };
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_ldo1";
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <90>;
+ regulator-always-on;
I see that all regulators are marked as regulator-always-on but that will
prevent the regulator subsystem to disable unused regulators. Can you please
double check which regulators should really be always on and which ones can
be disabled if are not used?
I kept it on always, as I am still in a process for validating all IPs
on board. Will see if I can remove some of them, which I feel can be done.
After those two changes:
Reviewed-by: Javier Martinez Canillas
Thanks!
Best regards,
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[PATCH 1/2] arm64: dts: exynos7: Add pmic s2mps15 device tree node
This patch add pmic (s2mps15) node of espresso board,
which includes addition of regulators and pmic-clk sub-nodes.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Alim Akhtar
---
This patch should go in after driver side changes [1] lands.
[1]->
https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg47736.html
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 349 +++
1 file changed, 349 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 838a3626dac1..8ce04a0ec928 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -53,6 +53,355 @@
status = "okay";
};
+&hsi2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20>;
+ status = "okay";
+
+ s2mps15_pmic@66 {
+ compatible = "samsung,s2mps15-pmic";
+ reg = <0x66>;
+ interrupts = <2 0>;
+ interrupt-parent = <&gpa0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq>;
+ wakeup-source;
+
+ s2mps15_osc: clocks {
+ compatible = "samsung,s2mps13-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps13_ap", "s2mps13_cp",
+ "s2mps13_bt";
+ };
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_ldo1";
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <90>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "vdd_ldo2";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <330>;
+ regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "vdd_ldo3";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "vdd_ldo4";
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <111>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "vdd_ldo5";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "vdd_ldo6";
+ regulator-min-microvolt = <225>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "vdd_ldo7";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <115>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <125>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "vdd_ldo8";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <100>;
+
[PATCH 2/2] arm64: dts: exynos7: Enable HS200 mode operation
This patch enables HS200 mode operation on exynos7 based
espresso board.
This also remove _broken-cd_ property as per mmc binding documentation
which say one of the properties between broken-cd and non-removable
should be used. And we already use _non-removable_ as emmc mounted
on board which is a non-removable device.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 8ce04a0ec928..7f19b99fc85b 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -405,8 +405,8 @@
&mmc_0 {
status = "okay";
num-slots = <1>;
- broken-cd;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
non-removable;
card-detect-delay = <200>;
clock-frequency = <8>;
--
1.7.10.4
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Re: [PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
On 10/30/2015 01:12 PM, Krzysztof Kozlowski wrote: On 30.10.2015 15:25, Alim Akhtar wrote: From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. This also supports RTC and three 32.768KHz clock outputs. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) Reviewed-by: Krzysztof Kozlowski Thanks Krzysztof. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. This also supports RTC and three 32.768KHz clock outputs. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..4c0543ceec25 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", "samsung,s2mps14-clk", "samsung,s5m8767-clk" +The s2msp15 uses the same compatible as s2mps13, as both provides similar clocks. - regulators: The regulators of s2mps11 that have to be instantiated should be included in a sub-node named 'regulators'. Regulator nodes included in this @@ -90,6 +95,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 38 - S2MPS13: 1 to 40 - S2MPS14: 1 to 25 + - S2MPS15: 1 to 27 - S2MPU02: 1 to 28 - Example: LDO1, LDO2, LDO28 - BUCKn @@ -97,6 +103,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 10 - S2MPS13: 1 to 10 - S2MPS14: 1 to 5 + - S2MPS15: 1 to 10 - S2MPU02: 1 to 7 - Example: BUCK1, BUCK2, BUCK9 -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
On 10/29/2015 11:27 AM, Krzysztof Kozlowski wrote: On 29.10.2015 13:58, Alim Akhtar wrote: From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Acked-by: Lee Jones --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 23 ++--- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..c0427c9d0886 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" + "samsung,s2mps14-clk", "samsung,s2mps15-clk", + "samsung,s5m8767-clk" N. Why "samsung,s2mps15-clk"? Adding a new compatible to bindings is a major change so my review tag (from v1 where there was no such compatible) should be dropped. Please drop it. My bad, will drop it. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Acked-by: Lee Jones --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 23 ++--- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..c0427c9d0886 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" + "samsung,s2mps14-clk", "samsung,s2mps15-clk", + "samsung,s5m8767-clk" - regulators: The regulators of s2mps11 that have to be instantiated should be included in a sub-node named 'regulators'. Regulator nodes included in this @@ -90,6 +95,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 38 - S2MPS13: 1 to 40 - S2MPS14: 1 to 25 + - S2MPS15: 1 to 27 - S2MPU02: 1 to 28 - Example: LDO1, LDO2, LDO28 - BUCKn @@ -97,6 +103,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 10 - S2MPS13: 1 to 10 - S2MPS14: 1 to 5 + - S2MPS15: 1 to 10 - S2MPU02: 1 to 7 - Example: BUCK1, BUCK2, BUCK9 -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/5] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Acked-by: Lee Jones --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 23 ++--- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..c0427c9d0886 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" + "samsung,s2mps14-clk", "samsung,s2mps15-clk", + "samsung,s5m8767-clk" - regulators: The regulators of s2mps11 that have to be instantiated should be included in a sub-node named 'regulators'. Regulator nodes included in this @@ -90,6 +95,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 38 - S2MPS13: 1 to 40 - S2MPS14: 1 to 25 + - S2MPS15: 1 to 27 - S2MPU02: 1 to 28 - Example: LDO1, LDO2, LDO28 - BUCKn @@ -97,6 +103,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 10 - S2MPS13: 1 to 10 - S2MPS14: 1 to 5 + - S2MPS15: 1 to 10 - S2MPU02: 1 to 7 - Example: BUCK1, BUCK2, BUCK9 -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
On 10/26/2015 04:39 PM, Lee Jones wrote: On Mon, 26 Oct 2015, Alim Akhtar wrote: From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 23 ++--- 1 file changed, 15 insertions(+), 8 deletions(-) Nothing to controversial here. For my own reference: Acked-by: Lee Jones Thanks, will send v3 of this series. diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..c0427c9d0886 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" + "samsung,s2mps14-clk", "samsung,s2mps15-clk", + "samsung,s5m8767-clk" - regulators: The regulators of s2mps11 that have to be instantiated should be included in a sub-node named 'regulators'. Regulator nodes included in this @@ -90,6 +95,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 38 - S2MPS13: 1 to 40 - S2MPS14: 1 to 25 + - S2MPS15: 1 to 27 - S2MPU02: 1 to 28 - Example: LDO1, LDO2, LDO28 - BUCKn @@ -97,6 +103,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 10 - S2MPS13: 1 to 10 - S2MPS14: 1 to 5 + - S2MPS15: 1 to 10 - S2MPU02: 1 to 7 - Example: BUCK1, BUCK2, BUCK9 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Abraham Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/s2mps11.txt | 23 ++--- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index 890f0b0e1643..c0427c9d0886 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt @@ -1,5 +1,5 @@ -* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator +* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator The Samsung S2MPS11 is a multi-function device which includes voltage and current regulators, RTC, charger controller and other sub-blocks. It is @@ -7,8 +7,12 @@ interfaced to the host controller using an I2C interface. Each sub-block is addressed by the host system using different I2C slave addresses. Required properties: -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" - or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". +- compatible: Should be one of the following + - "samsung,s2mps11-pmic" + - "samsung,s2mps13-pmic" + - "samsung,s2mps14-pmic" + - "samsung,s2mps15-pmic" + - "samsung,s2mpu02-pmic". - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. Optional properties: @@ -24,7 +28,7 @@ Optional properties: unwanted buck warm reset (setting buck voltages to default values). Optional nodes: -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz outputs, so to register these as clocks with common clock framework instantiate a sub-node named "clocks". It uses the common clock binding documented in : @@ -37,12 +41,13 @@ Optional nodes: the clock which they consume. Clock ID Devices -- -32KhzAP0S2MPS11, S2MPS13, S2MPS14, S5M8767 -32KhzCP1S2MPS11, S2MPS13, S5M8767 -32KhzBT2S2MPS11, S2MPS13, S2MPS14, S5M8767 +32KhzAP0S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 +32KhzCP1S2MPS11, S2MPS13, S2MPS15, S5M8767 +32KhzBT2S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" + "samsung,s2mps14-clk", "samsung,s2mps15-clk", + "samsung,s5m8767-clk" - regulators: The regulators of s2mps11 that have to be instantiated should be included in a sub-node named 'regulators'. Regulator nodes included in this @@ -90,6 +95,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 38 - S2MPS13: 1 to 40 - S2MPS14: 1 to 25 + - S2MPS15: 1 to 27 - S2MPU02: 1 to 28 - Example: LDO1, LDO2, LDO28 - BUCKn @@ -97,6 +103,7 @@ as per the datasheet of s2mps11. - S2MPS11: 1 to 10 - S2MPS13: 1 to 10 - S2MPS14: 1 to 5 + - S2MPS15: 1 to 10 - S2MPU02: 1 to 7 - Example: BUCK1, BUCK2, BUCK9 -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Kishon
Thanks again for you review.
On Fri, Oct 23, 2015 at 8:48 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 15 October 2015 08:38 AM, Alim Akhtar wrote:
>> +CCing kishon Vijay,
>>
>> On 10/14/2015 06:25 PM, Alim Akhtar wrote:
>>> From: Seungwon Jeon
>>>
>>> This patch introduces Exynos UFS host controller driver,
>>> which mainly handles vendor-specific operations including
>>> link startup, power mode change and hibernation/unhibernation.
>>>
>>> Signed-off-by: Seungwon Jeon
>>> Signed-off-by: Alim Akhtar
>>> ---
>>> drivers/scsi/ufs/Kconfig | 12 +
>>> drivers/scsi/ufs/Makefile|1 +
>>> drivers/scsi/ufs/ufs-exynos-hw.c | 131
>>> drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
>>> drivers/scsi/ufs/ufs-exynos.c| 1317
>>> ++
>>> drivers/scsi/ufs/ufs-exynos.h| 247 +++
>>> drivers/scsi/ufs/ufshci.h| 26 +-
>>> drivers/scsi/ufs/unipro.h| 47 ++
>>> 8 files changed, 1823 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
>>>
> .
> .
>
> .
> .
>>> diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c
>>> b/drivers/scsi/ufs/ufs-exynos-hw.c
>>> new file mode 100644
>>> index ..be6c61541a8f
>>> --- /dev/null
>>> +++ b/drivers/scsi/ufs/ufs-exynos-hw.c
>>> @@ -0,0 +1,131 @@
> .
> .
>
> .
> .
>>> +
>>> +#define PWR_MODE_STR_LEN64
>>> +static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
>>> +struct ufs_pa_layer_attr *pwr_max,
>>> +struct ufs_pa_layer_attr *pwr_req)
>>> +{
>>> +struct exynos_ufs *ufs = to_exynos_ufs(hba);
>>> +struct exynos_ufs_phy_info *phy_info = phy_get_drvdata(ufs->phy);
>
> This is abusing the interface. phy_get_drvdata is meant to be used only
> by the PHY driver.
>>> +struct exynos_ufs_phy_specific_ops *phy_ops =
>>> +phy_info->phy_specific_ops;
>
> I'm really not happy about having platform specific ops for PHY. We have
> to see if existing PHY ops can be used for this or in worst case add new
> PHY ops.
Well you said you like the controller driver to use only PHY ops[1], I
am sorry If I misunderstood that point, can you please help me to
understand that?
[1]-> https://lkml.org/lkml/2015/9/18/29
>>> +struct uic_pwr_mode *pwr = &ufs->pwr_act;
>>> +char pwr_str[PWR_MODE_STR_LEN] = "";
>>> +int ret = 0;
>>> +
>>> +if (ufs->drv_data->post_pwr_change)
>>> +ufs->drv_data->post_pwr_change(ufs, pwr);
>>> +
>>> +if (IS_UFS_PWR_MODE_HS(pwr->mode)) {
>>> +switch (pwr->hs_series) {
>>> +case PA_HS_MODE_A:
>>> +case PA_HS_MODE_B:
>>> +phy_ops->calibrate_phy(ufs->phy, CFG_POST_PWR_HS,
>>> +PWR_MODE_HS(pwr->gear, pwr->hs_series));
>>> +break;
>>> +}
>>> +
>>> +ret = phy_ops->wait_for_lock_acq(ufs->phy);
>>> +snprintf(pwr_str, sizeof(pwr_str), "Fast%s series_%s G_%d L_%d",
>>> +pwr->mode == FASTAUTO_MODE ? "_Auto" : "",
>>> +pwr->hs_series == PA_HS_MODE_A ? "A" : "B",
>>> +pwr->gear, pwr->lane);
>>> +} else if (IS_UFS_PWR_MODE_PWM(pwr->mode)) {
>>> +snprintf(pwr_str, sizeof(pwr_str), "Slow%s G_%d L_%d",
>>> +pwr->mode == SLOWAUTO_MODE ? "_Auto" : "",
>>> +pwr->gear, pwr->lane);
>>> +}
>>> +
>>> +dev_info(hba->dev, "Power mode change %d : %s\n", ret, pwr_str);
>>> +return ret;
>>> +}
>>> +
>>> +static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
>>> +int tag, struct scsi_cmnd *cmd)
>>> +{
>>> +struct exynos_ufs *ufs = to_exynos_ufs(hba);
>>> +u32 type;
>>> +
>>> +type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
>>> +
>>> +if (cmd)
>>> +hci_writel(ufs, type | (1 <
Re: [PATCH v4 00/11] exynos-ufs: add support for Exynos
A Gentle Reminder !! On 10/14/2015 06:25 PM, Alim Akhtar wrote: This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. NOTE: ** This series has a dependency on [4]. ** -Changes since v3: * Fixed compilation warrings as reported by "Kbuild Test Robot"[5]. * Restructure the driver to make it as a platform driver, rebased on top of [4]. * Addressed review comments from Arnd Bergmann[5]. * Other misc changes and improvements. -Changes since v2: * Addressed review comments from Kishon[1] and Rob Herring [2] * Splited ufs dt binding documetation from ufs driver patch -Changes since v1: * Addressed review comments from Alexey[3] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/9/18/29 [2]-> https://lkml.org/lkml/2015/9/21/668 [3]-> https://lkml.org/lkml/2015/8/23/124 [4]-> https://lkml.org/lkml/2015/9/2/364 [5]-> https://lkml.org/lkml/2015/10/1/402 This patch set is tested on exynos7-espresso board. Alim Akhtar (1): Documentation: samsung-phy: Add dt bindings for UFS Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 257 drivers/phy/phy-exynos-ufs.h | 88 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1317 drivers/scsi/ufs/ufs-exynos.h | 247 drivers/scsi/ufs/ufshcd.c | 168 ++- drivers/scsi/ufs/ufshcd.h | 54 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 101 ++ 18 files changed, 2695 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
On 10/22/2015 05:47 AM, Krzysztof Kozlowski wrote:
On 22.10.2015 00:01, Alim Akhtar wrote:
On Wed, Oct 21, 2015 at 8:25 PM, Javier Martinez Canillas
wrote:
Hello Alim,
On 10/21/2015 04:50 PM, Alim Akhtar wrote:
[snip]
[0]:
From c9b250ee03bae338339b70693e906145c719f783 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas
Date: Wed, 21 Oct 2015 11:59:44 +0200
Subject: [RFT PATCH] mmc: pwrseq: Use highest priority for eMMC restart
handler
The pwrseq_emmc driver does a eMMC card reset before a system reboot to
allow broken or limited ROM boot-loaders, that don't have an eMMC reset
logic, to be able to read the second stage from the eMMC.
But this has to be called before a system reboot handler and while most
of them use the priority 128, there are other restart handlers (such as
the syscon-reboot one) that use a higher priority. So, use the highest
priority to make sure that the eMMC hw is reset before a system reboot.
Signed-off-by: Javier Martinez Canillas
---
Looks good.
Reviewed-by: Alim Akhtar
+Cc Ulf,
Javier,
First of all, thanks Javier for digging into the issue. Actually I have
Odroid U3 but because of user-space limitations (which I need for other
work) I cannot test all of mainline patches there.
Thanks, should I post it as a proper patch or are adding it to your
series?
Suggest you to post as a patch collecting {Tested, Reviewed}-by (easy
for maintainers to pickup ) and probably CCing Ulf for his feedback.
I think the latter is more reasonable so with an ack from Ulf,
all patches can go through the linux-samsung tree.
yes, that is reasonable, as I said, let Krzysztof and Ulf take a call here.
Javier, Alim, Ulf,
I am not grabbing any more patches for v4.4 because I doubt that they
could be merged to arm-soc for this cycle. My last pull requests for
v4.4 is still pending...
This means that I plan to pick up these series for v4.5, after closing
v4.4 merge window (unless Kukjin picks it also). Because of that, we
have plenty of time, so my idea is:
1. Wait for some comments from Ulf on Javier's fix.
2. If the fix goes into v4.4, then problem solved.
3. If not and it get acked, then it can go with this set.
4. If not and it get applied by Ulf for v4.5, then a tag from him would
be a nice way to solve dependency.
Either way we don't have to hurry, I think.
I am fine, no hurry, lets give these a bit more time to hear from other.
Thanks
Best regards,
Krzysztof
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
On Wed, Oct 21, 2015 at 8:25 PM, Javier Martinez Canillas
wrote:
> Hello Alim,
>
> On 10/21/2015 04:50 PM, Alim Akhtar wrote:
>
> [snip]
>
>>>
>>> [0]:
>>> From c9b250ee03bae338339b70693e906145c719f783 Mon Sep 17 00:00:00 2001
>>> From: Javier Martinez Canillas
>>> Date: Wed, 21 Oct 2015 11:59:44 +0200
>>> Subject: [RFT PATCH] mmc: pwrseq: Use highest priority for eMMC restart
>>> handler
>>>
>>> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
>>> allow broken or limited ROM boot-loaders, that don't have an eMMC reset
>>> logic, to be able to read the second stage from the eMMC.
>>>
>>> But this has to be called before a system reboot handler and while most
>>> of them use the priority 128, there are other restart handlers (such as
>>> the syscon-reboot one) that use a higher priority. So, use the highest
>>> priority to make sure that the eMMC hw is reset before a system reboot.
>>>
>>> Signed-off-by: Javier Martinez Canillas
>>> ---
>> Looks good.
>> Reviewed-by: Alim Akhtar
>>
>
> Thanks, should I post it as a proper patch or are adding it to your
> series?
Suggest you to post as a patch collecting {Tested, Reviewed}-by (easy
for maintainers to pickup ) and probably CCing Ulf for his feedback.
> I think the latter is more reasonable so with an ack from Ulf,
> all patches can go through the linux-samsung tree.
>
yes, that is reasonable, as I said, let Krzysztof and Ulf take a call here.
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
--
Regards,
Alim
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Javier,
On Wed, Oct 21, 2015 at 6:53 PM, Javier Martinez Canillas
wrote:
> Hello Alim,
>
> On 10/21/2015 12:44 PM, Alim Akhtar wrote:
>
> [snip]
>
>>>
>>> Can you please test following patch [0] on top of Alim's series? If that
>>> works then it should either be part of Alim's series or the patches will
>>> have to wait until that patch lands into mainline. I don't have an eMMC
>>> to test it in XU4 but I'm pretty confident that it will solve the issue.
>>>
>> I am fine with including this with my series or lowering
>> syscon_restart_handler priority to 128.
>
> Yes, I also considered changing the syscon-reboot handler priority to 128 but
> then I noticed this commit:
>
> b81180b3fd48 ("power: reset: adjust priority of simple syscon reboot driver").
>
> So as you can see, it was 128 before but was bumped to 192 so it was called
> before restart handlers registered by watchdogs. So, changing to 128 would
> break other people use cases.
>
> Now, I don't know if that is the right fix since register_restart_handler()
> explanation about the policy used for restart handler priority numbers is
> scarce. It only mentions 0, 128 and 255 so probably the correct thing to do
> is to change all watchdog restart handler to 0 but that is a separate issue.
>
>> It also make sense to increase eMMC priority as you suggested as before
>> system reboot, devices should have reseted itself.
>
> That was my rationale as well and is why I think the handler for devices
> should use the highest priority regardless if the syscon-reboot is later
> changed to prio 128 and the watchdog handlers to 0.
>
I agree, in any case dumping up eMMC reset priority make sense.
If all is good here, over to Krzysztof and Ulf to handle these patches.
Thanks.
> Best regards,
>
> [0]: http://lxr.free-electrons.com/source/kernel/reboot.c#L113
>
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
--
Regards,
Alim
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Javier, On Wed, Oct 21, 2015 at 3:46 PM, Javier Martinez Canillas wrote: > Hello Alim, > > On 10/21/2015 08:09 AM, Alim Akhtar wrote: > > [snip] > >>>>>> >>>>>> Hi Alim, >>>>>> >>>>>> I have installed your patch set above with git am on top of >>>>>> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today >>>>>> with make exynos_defconfig on Odroid U3. >>>>>> >>>>> which exynos soc Odroid U3 uses? >>>>> >>>> OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does >>>> include exynos4.dtsi, >>>> so these should have worked. >>>> >>>>>> "halt -p" worked (power 0.0W). >>>>>> "reboot" got stuck at 0.5W. >>>>>> >>>>> reboot stuck mean system does not reboot any more? >>> >>> It freezes when going for reboot. >>> Have to power off/on to boot again. >>> >>> Btw I use an mmc, not an sd-card. >>> No other HW connected, just LAN-cable. >>> Bootloader is u-boot v2015.10. >>> o >> Have checked on 4.3.0-rc6-6-gd03c139e7e77, still works on peach boards. >> Sorry I don't have Odroid U3 with me, may be Javier or Krzysztof might help >> here to check whats wrong. To me its looks more of a board specific issue >> for now. >> > > Krzysztof has an Odroid XU3 lite and I have an Odroid XU4, both uses an > Exynos5422 so we can't check what's wrong with Odroid U3 (Exynos4412). > > Having said that I think I know what is the issue here. Markus said that > he is using an eMMC instead of an uSD (which is what I used and my guess > is that Krzysztof did too). > > Now, there is a subtle difference between the old PMU restart handler > and the syscon-reboot one, and that is the restart handler priorities: > > notifierpriority > > pmu_restart_notify 128 > mmc_pwrseq_emmc_reset_nb129 > syscon_restart_handle 192 > > So, without Alim's patches, first the eMMC reset handler will be called > and then the PMU restart handler but after his series, the syscon reset > handler has a higher priority so the eMMC reset will never be called. > > But the problem is that the eMMC card has to be properly reset on system > restart to allow the SoC iROM to be able to read the bootloader from the > eMMC since the iROM doesn't have restart logic and the card shouldn't be > left in an unknown state. > > So the problem here is not that the system is not being reset (that I > think that works) but that on reboot, the system is not able to boot > again since the ROM is not able to read the second stage bootloader. > > Markus, > > Can you please test following patch [0] on top of Alim's series? If that > works then it should either be part of Alim's series or the patches will > have to wait until that patch lands into mainline. I don't have an eMMC > to test it in XU4 but I'm pretty confident that it will solve the issue. > > Best regards, > -- > Javier Martinez Canillas > Open Source Group > Samsung Research America > > [0]: > From c9b250ee03bae338339b70693e906145c719f783 Mon Sep 17 00:00:00 2001 > From: Javier Martinez Canillas > Date: Wed, 21 Oct 2015 11:59:44 +0200 > Subject: [RFT PATCH] mmc: pwrseq: Use highest priority for eMMC restart > handler > > The pwrseq_emmc driver does a eMMC card reset before a system reboot to > allow broken or limited ROM boot-loaders, that don't have an eMMC reset > logic, to be able to read the second stage from the eMMC. > > But this has to be called before a system reboot handler and while most > of them use the priority 128, there are other restart handlers (such as > the syscon-reboot one) that use a higher priority. So, use the highest > priority to make sure that the eMMC hw is reset before a system reboot. > > Signed-off-by: Javier Martinez Canillas > --- Looks good. Reviewed-by: Alim Akhtar > drivers/mmc/core/pwrseq_emmc.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/core/pwrseq_emmc.c b/drivers/mmc/core/pwrseq_emmc.c > index 137c97fb7aa8..ad4f94ec7e8d 100644 > --- a/drivers/mmc/core/pwrseq_emmc.c > +++ b/drivers/mmc/core/pwrseq_emmc.c > @@ -84,11 +84,11 @@ struct mmc_pwrseq *mmc_pwrseq_emmc_alloc(struct mmc_host > *host, > > /* > * register reset handler to ensure emmc reset also from > -* emergency_reboot(), priority 129 schedules it just before > -* system reboot > +* emergency_reboot(), priority 255 is the highest priority > +* so it will be executed before any system reboot handler. > */ > pwrseq->reset_nb.notifier_call = mmc_pwrseq_emmc_reset_nb; > - pwrseq->reset_nb.priority = 129; > + pwrseq->reset_nb.priority = 255; > register_restart_handler(&pwrseq->reset_nb); > > pwrseq->pwrseq.ops = &mmc_pwrseq_emmc_ops; > -- > 2.4.3 -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
On 10/21/2015 04:12 PM, Markus Reichl wrote: Am 21.10.2015 um 12:16 schrieb Javier Martinez Canillas: Hello Alim, On 10/21/2015 08:09 AM, Alim Akhtar wrote: [snip] Hi Alim, I have installed your patch set above with git am on top of 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today with make exynos_defconfig on Odroid U3. which exynos soc Odroid U3 uses? OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does include exynos4.dtsi, so these should have worked. "halt -p" worked (power 0.0W). "reboot" got stuck at 0.5W. reboot stuck mean system does not reboot any more? It freezes when going for reboot. Have to power off/on to boot again. Btw I use an mmc, not an sd-card. No other HW connected, just LAN-cable. Bootloader is u-boot v2015.10. o Have checked on 4.3.0-rc6-6-gd03c139e7e77, still works on peach boards. Sorry I don't have Odroid U3 with me, may be Javier or Krzysztof might help here to check whats wrong. To me its looks more of a board specific issue for now. Krzysztof has an Odroid XU3 lite and I have an Odroid XU4, both uses an Exynos5422 so we can't check what's wrong with Odroid U3 (Exynos4412). Having said that I think I know what is the issue here. Markus said that he is using an eMMC instead of an uSD (which is what I used and my guess is that Krzysztof did too). Now, there is a subtle difference between the old PMU restart handler and the syscon-reboot one, and that is the restart handler priorities: notifierpriority pmu_restart_notify 128 mmc_pwrseq_emmc_reset_nb129 syscon_restart_handle 192 So, without Alim's patches, first the eMMC reset handler will be called and then the PMU restart handler but after his series, the syscon reset handler has a higher priority so the eMMC reset will never be called. But the problem is that the eMMC card has to be properly reset on system restart to allow the SoC iROM to be able to read the bootloader from the eMMC since the iROM doesn't have restart logic and the card shouldn't be left in an unknown state. So the problem here is not that the system is not being reset (that I think that works) but that on reboot, the system is not able to boot again since the ROM is not able to read the second stage bootloader. Markus, Can you please test following patch [0] on top of Alim's series? If that works then it should either be part of Alim's series or the patches will have to wait until that patch lands into mainline. I don't have an eMMC to test it in XU4 but I'm pretty confident that it will solve the issue. Hi Javier, your patch fixes the issue, reboot works now on U3. Good to know that. Thanks Tested-by: Markus Reichl Thanks, -- Markus Best regards, -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Javier, On 10/21/2015 03:46 PM, Javier Martinez Canillas wrote: Hello Alim, On 10/21/2015 08:09 AM, Alim Akhtar wrote: [snip] Hi Alim, I have installed your patch set above with git am on top of 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today with make exynos_defconfig on Odroid U3. which exynos soc Odroid U3 uses? OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does include exynos4.dtsi, so these should have worked. "halt -p" worked (power 0.0W). "reboot" got stuck at 0.5W. reboot stuck mean system does not reboot any more? It freezes when going for reboot. Have to power off/on to boot again. Btw I use an mmc, not an sd-card. No other HW connected, just LAN-cable. Bootloader is u-boot v2015.10. o Have checked on 4.3.0-rc6-6-gd03c139e7e77, still works on peach boards. Sorry I don't have Odroid U3 with me, may be Javier or Krzysztof might help here to check whats wrong. To me its looks more of a board specific issue for now. Krzysztof has an Odroid XU3 lite and I have an Odroid XU4, both uses an Exynos5422 so we can't check what's wrong with Odroid U3 (Exynos4412). Having said that I think I know what is the issue here. Markus said that he is using an eMMC instead of an uSD (which is what I used and my guess is that Krzysztof did too). Now, there is a subtle difference between the old PMU restart handler and the syscon-reboot one, and that is the restart handler priorities: notifierpriority pmu_restart_notify 128 mmc_pwrseq_emmc_reset_nb129 syscon_restart_handle 192 So, without Alim's patches, first the eMMC reset handler will be called and then the PMU restart handler but after his series, the syscon reset handler has a higher priority so the eMMC reset will never be called. But the problem is that the eMMC card has to be properly reset on system restart to allow the SoC iROM to be able to read the bootloader from the eMMC since the iROM doesn't have restart logic and the card shouldn't be left in an unknown state. So the problem here is not that the system is not being reset (that I think that works) but that on reboot, the system is not able to boot again since the ROM is not able to read the second stage bootloader. Thanks for nailing it down, this make lots of sense and probably the main cause of Odroid U3 reboot failure. I was going to suggest Markus to try a uSD boot. But looks like your suggested patch will do the trick for him. Markus, Can you please test following patch [0] on top of Alim's series? If that works then it should either be part of Alim's series or the patches will have to wait until that patch lands into mainline. I don't have an eMMC to test it in XU4 but I'm pretty confident that it will solve the issue. I am fine with including this with my series or lowering syscon_restart_handler priority to 128. It also make sense to increase eMMC priority as you suggested as before system reboot, devices should have reseted itself. Thanks! Best regards, -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
On 10/20/2015 10:53 PM, Markus Reichl wrote:
Am Dienstag, 20. Oktober 2015, 21:22:05 schrieb Alim Akhtar:
On Tue, Oct 20, 2015 at 9:17 PM, Alim Akhtar wrote:
Hi Markus,
On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl wrote:
Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
Now we have a nice way to reboot/poweroff system using a generic
syscon regmap based drivers, this series moves exynos SoCs to
make use of the same.
Changes since v1:
* Added a comment about the register information
* Droped defconfig changes as disscussed
* Collected various Reviewed-by, Tested-by and Acked-by tags
* Added SYSCON-{RESET, POWEROFF} to select from Kconfig
Alim Akhtar (6):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos: select POWER_RESET_SYSCON and
POWER_RESET_SYSCON_POWEROFF
ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/mach-exynos/Kconfig |3 +++
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 59 insertions(+), 43 deletions(-)
Hi Alim,
I have installed your patch set above with git am on top of
4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
with make exynos_defconfig on Odroid U3.
which exynos soc Odroid U3 uses?
OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does
include exynos4.dtsi,
so these should have worked.
"halt -p" worked (power 0.0W).
"reboot" got stuck at 0.5W.
reboot stuck mean system does not reboot any more?
It freezes when going for reboot.
Have to power off/on to boot again.
Btw I use an mmc, not an sd-card.
No other HW connected, just LAN-cable.
Bootloader is u-boot v2015.10.
o
Have checked on 4.3.0-rc6-6-gd03c139e7e77, still works on peach boards.
Sorry I don't have Odroid U3 with me, may be Javier or Krzysztof might
help here to check whats wrong. To me its looks more of a board specific
issue for now.
As far as I can see there in __no__ functional changes that my patch introduce.
So ideally it should have work. My patches are based on the top on
vanilla v4.3-rc5.
(25cb62b Linux 4.3-rc5), can you check at this commit?
Will try tomorrow.
Will check with the commit mentioned by you tomorrow.
Without your patch set reboot worked.
Thanks,
--
Markus Reichl
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Regards,
Alim
Thanks,
--
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
Hi Markus,
On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl wrote:
> Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
>> Now we have a nice way to reboot/poweroff system using a generic
>> syscon regmap based drivers, this series moves exynos SoCs to
>> make use of the same.
>>
>> Changes since v1:
>> * Added a comment about the register information
>> * Droped defconfig changes as disscussed
>> * Collected various Reviewed-by, Tested-by and Acked-by tags
>> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
>>
>> Alim Akhtar (6):
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>> ARM: exynos: select POWER_RESET_SYSCON and
>> POWER_RESET_SYSCON_POWEROFF
>> ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>
>> arch/arm/boot/dts/exynos3250.dtsi | 14
>> arch/arm/boot/dts/exynos4.dtsi| 14
>> arch/arm/boot/dts/exynos5.dtsi| 14
>> arch/arm/boot/dts/exynos5410.dtsi | 14
>> arch/arm/mach-exynos/Kconfig |3 +++
>> arch/arm/mach-exynos/pmu.c| 43
>> -
>> 6 files changed, 59 insertions(+), 43 deletions(-)
>>
>
> Hi Alim,
>
> I have installed your patch set above with git am on top of
> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
> with make exynos_defconfig on Odroid U3.
>
which exynos soc Odroid U3 uses?
> "halt -p" worked (power 0.0W).
> "reboot" got stuck at 0.5W.
>
reboot stuck mean system does not reboot any more?
As far as I can see there in __no__ functional changes that my patch introduce.
So ideally it should have work. My patches are based on the top on
vanilla v4.3-rc5.
(25cb62b Linux 4.3-rc5), can you check at this commit?
Will check with the commit mentioned by you tomorrow.
>
> Without your patch set reboot worked.
>
>
> Thanks,
> --
> Markus Reichl
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Regards,
Alim
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers
On Tue, Oct 20, 2015 at 9:17 PM, Alim Akhtar wrote:
> Hi Markus,
>
> On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl wrote:
>> Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
>>> Now we have a nice way to reboot/poweroff system using a generic
>>> syscon regmap based drivers, this series moves exynos SoCs to
>>> make use of the same.
>>>
>>> Changes since v1:
>>> * Added a comment about the register information
>>> * Droped defconfig changes as disscussed
>>> * Collected various Reviewed-by, Tested-by and Acked-by tags
>>> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
>>>
>>> Alim Akhtar (6):
>>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>>> ARM: exynos: select POWER_RESET_SYSCON and
>>> POWER_RESET_SYSCON_POWEROFF
>>> ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>>
>>> arch/arm/boot/dts/exynos3250.dtsi | 14
>>> arch/arm/boot/dts/exynos4.dtsi| 14
>>> arch/arm/boot/dts/exynos5.dtsi| 14
>>> arch/arm/boot/dts/exynos5410.dtsi | 14
>>> arch/arm/mach-exynos/Kconfig |3 +++
>>> arch/arm/mach-exynos/pmu.c| 43
>>> -
>>> 6 files changed, 59 insertions(+), 43 deletions(-)
>>>
>>
>> Hi Alim,
>>
>> I have installed your patch set above with git am on top of
>> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
>> with make exynos_defconfig on Odroid U3.
>>
> which exynos soc Odroid U3 uses?
>
OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does
include exynos4.dtsi,
so these should have worked.
>> "halt -p" worked (power 0.0W).
>> "reboot" got stuck at 0.5W.
>>
> reboot stuck mean system does not reboot any more?
> As far as I can see there in __no__ functional changes that my patch
> introduce.
> So ideally it should have work. My patches are based on the top on
> vanilla v4.3-rc5.
> (25cb62b Linux 4.3-rc5), can you check at this commit?
>
> Will check with the commit mentioned by you tomorrow.
>
>>
>> Without your patch set reboot worked.
>>
>>
>> Thanks,
>> --
>> Markus Reichl
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
>> in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim
--
Regards,
Alim
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[PATCH v2 6/6] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
Now we can use the generic syscon-{reboot/poweroff} drivers,
so we don't need special handling for reboot/poweroff in
exynos pmu driver. This patch remove the same.
Note: This will break reboot/poweroff on boards with older dtbs
with a newer kernel.
Signed-off-by: Alim Akhtar
Reviewed-by: Javier Martinez Canillas
Acked-by: Moritz Fischer
---
arch/arm/mach-exynos/pmu.c | 43 ---
1 file changed, 43 deletions(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index de68938ee6aa..393c04aa727e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,9 +14,6 @@
#include
#include
#include
-#include
-#include
-
#include "exynos-pmu.h"
#include "regs-pmu.h"
@@ -681,23 +678,6 @@ static unsigned int const
exynos5420_list_disable_pmu_reg[] = {
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
};
-static void exynos_power_off(void)
-{
- unsigned int tmp;
-
- pr_info("Power down.\n");
- tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
- tmp ^= (1 << 8);
- pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
-
- /* Wait a little so we don't give a false warning below */
- mdelay(100);
-
- pr_err("Power down failed, please power off system manually.\n");
- while (1)
- ;
-}
-
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
{
u32 this_cluster;
@@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void)
pr_info("EXYNOS5420 PMU initialized\n");
}
-static int pmu_restart_notify(struct notifier_block *this,
- unsigned long code, void *unused)
-{
- pmu_raw_writel(0x1, EXYNOS_SWRESET);
-
- return NOTIFY_DONE;
-}
-
static const struct exynos_pmu_data exynos3250_pmu_data = {
.pmu_config = exynos3250_pmu_config,
.pmu_init = exynos3250_pmu_init,
@@ -940,20 +912,11 @@ static const struct of_device_id
exynos_pmu_of_device_ids[] = {
{ /*sentinel*/ },
};
-/*
- * Exynos PMU restart notifier, handles restart functionality
- */
-static struct notifier_block pmu_restart_handler = {
- .notifier_call = pmu_restart_notify,
- .priority = 128,
-};
-
static int exynos_pmu_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmu_base_addr = devm_ioremap_resource(dev, res);
@@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pmu_context);
- ret = register_restart_handler(&pmu_restart_handler);
- if (ret)
- dev_warn(dev, "can't register restart handler err=%d\n", ret);
-
- pm_power_off = exynos_power_off;
-
dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
--
1.7.10.4
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[PATCH v2 3/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos5.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 110dbd4fb884..e2439e87ee4a 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -88,6 +88,20 @@
status = "disabled";
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
fimd: fimd@1440 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
--
1.7.10.4
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[PATCH v2 4/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5410 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos5410.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
index 731eefd23fa9..fad0779b1b6e 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -102,6 +102,20 @@
reg = <0x1004 0x5000>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
mct: mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0xB00>;
--
1.7.10.4
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[PATCH v2 1/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos3250.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def482fc3..46d469aa75a7 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* Reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
--
1.7.10.4
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[PATCH v2 5/6] ARM: exynos: select POWER_RESET_SYSCON and POWER_RESET_SYSCON_POWEROFF
Since we switch to use generic syscon regmap based reset/poweroff
driver for exynos SoC, lets select it from ARCH_EXYNOS instead of
enabling it from various defconfigs. This also select POWER_RESET
as SYSCON-{reset, poweroff} drivers depends on it.
Signed-off-by: Alim Akhtar
---
Have run make for allyes, allmod, multi_v7 and exynos defconfigs
no error/warrning reported.
arch/arm/mach-exynos/Kconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a8317a..d279edf9b10d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,9 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+ select POWER_RESET
+ select POWER_RESET_SYSCON
+ select POWER_RESET_SYSCON_POWEROFF
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
--
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[PATCH v2 2/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos4 SoC.
Signed-off-by: Alim Akhtar
Reviewed-by: Pankaj Dubey
Reviewed-by: Javier Martinez Canillas
Tested-by: Tobias Jakobi
Acked-by: Moritz Fischer
---
arch/arm/boot/dts/exynos4.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 98c0a368b777..1622f487e269 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -158,6 +158,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>; /* PS_HOLD_CONTROL */
+ mask = <0x5200>; /* reset value */
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>; /* SWRESET */
+ mask = <0x1>;
+ };
+
dsi_0: dsi@11C8 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C8 0x1>;
--
1.7.10.4
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[PATCH v2 0/6] Switch to generic syscon regmap based drivers
Now we have a nice way to reboot/poweroff system using a generic
syscon regmap based drivers, this series moves exynos SoCs to
make use of the same.
Changes since v1:
* Added a comment about the register information
* Droped defconfig changes as disscussed
* Collected various Reviewed-by, Tested-by and Acked-by tags
* Added SYSCON-{RESET, POWEROFF} to select from Kconfig
Alim Akhtar (6):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos: select POWER_RESET_SYSCON and
POWER_RESET_SYSCON_POWEROFF
ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/mach-exynos/Kconfig |3 +++
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 59 insertions(+), 43 deletions(-)
--
1.7.10.4
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Re: [PATCH 1/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
Hi Javier,
On 10/19/2015 06:33 PM, Javier Martinez Canillas wrote:
Hello Alim,
On 10/19/2015 08:03 AM, Alim Akhtar wrote:
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.
Signed-off-by: Alim Akhtar
---
arch/arm/boot/dts/exynos3250.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def482fc3..af5d9ad4c7b7 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>;
+ mask = <0x5200>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
I don't have a Exynos3250 manual but I guess 0x330C is also named
PS_HOLD_CONTROL and 0x400 is SWRESET as the other Exynos SoCs.
I wonder if a macro could be used instead of magic numbers or at
least have a comment next to the offset field.
The patch looks good to me though and a comment can be added as
a follow up so:
Will add a comment about register offset next to it.
Reviewed-by: Javier Martinez Canillas
Thanks!
Best regards,
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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers
Hi Moritz,
On 10/20/2015 02:48 AM, Moritz Fischer wrote:
On Sun, Oct 18, 2015 at 11:03 PM, Alim Akhtar wrote:
Alim Akhtar (7):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos_defconfig: Normalize exynos defconfig
ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
drivers
ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/configs/exynos_defconfig | 11 +-
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 61 insertions(+), 49 deletions(-)
--
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Feel free to add Acked-By: Moritz Fischer
to the patches in your series
Thanks!
Moritz
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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers
Hi Tobias,
On Mon, Oct 19, 2015 at 9:38 PM, Tobias Jakobi
wrote:
> Hello Alim,
>
> I tested the Exynos4 bits on a Odroid-X2 and I can confirm that
> poweroff/reboot (still) work.
>
Thanks for helping out in testing, will add your Tested-by of patch 2/7.
> With best wishes,
> Tobias
>
>
> Alim Akhtar wrote:
>> Alim Akhtar (7):
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>> arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>> ARM: exynos_defconfig: Normalize exynos defconfig
>> ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
>> drivers
>> ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>
>> arch/arm/boot/dts/exynos3250.dtsi | 14
>> arch/arm/boot/dts/exynos4.dtsi| 14
>> arch/arm/boot/dts/exynos5.dtsi| 14
>> arch/arm/boot/dts/exynos5410.dtsi | 14
>> arch/arm/configs/exynos_defconfig | 11 +-
>> arch/arm/mach-exynos/pmu.c| 43
>> -
>> 6 files changed, 61 insertions(+), 49 deletions(-)
>>
>
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Re: [PATCH 7/7] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
Hi Javier,
On Mon, Oct 19, 2015 at 7:37 PM, Javier Martinez Canillas
wrote:
> Hello Krzysztof,
>
> On 10/19/2015 03:28 PM, Krzysztof Kozlowski wrote:
>> 2015-10-19 18:56 GMT+09:00 Javier Martinez Canillas :
>>> Hello,
>>>
>>> On 10/19/2015 09:00 AM, Krzysztof Kozlowski wrote:
>>>> On 19.10.2015 15:03, Alim Akhtar wrote:
>>>>> Now we can use the generic syscon-{reboot/poweroff} drivers,
>>>>> so we don't need special handling for reboot/poweroff in
>>>>> exynos pmu driver. This patch remove the same.
>>>>>
>>>>> Signed-off-by: Alim Akhtar
>>>>> ---
>>>>> arch/arm/mach-exynos/pmu.c | 43
>>>>> ---
>>>>> 1 file changed, 43 deletions(-)
>>>>
>>>> I think that removal of this stuff will effectively remove the
>>>> restart/poweroff handlers from:
>>>> 1. Other defconfigs, like multi_v7
>>>> 2. Custom configs.
>>>>
>>>
>>> This will also break old DTBs that don't have a "syscon-poweroff" device
>>> node that contains the necessary PMU regmap, offset and mask information.
>>
>> I am not sure whether this is ABI break issue. There was no compatible
>> mentioning that "reset works" which now would be replaced. The
>> existing PMU compatible (like samsung,exynos4412-pmu) does not mention
>> "reset" as a feature coming with this compatible.
>>
>> So no ABI break.
>>
>>
>
> I deliberately didn't use the "DT ABI break" expression since as you said is
> not part of the documented DT bindings. But what I said is that this change
> will break old DTBs with newer kernels since reboot and power off will stop
> working after $SUBJECT.
>
> I'm not a particular fan of the stable DT idea since in practice it seems to
> do more harm than good but since that was decided, the expectation for users
> is that booting a new kernel with an old DT should not cause any regression.
>
> So I think that at least a comment in the commit message is needed so if
> there are people really using old DTs with newer kernels on Exynos boards,
> they can know that the commit causes such an issue instead of having to
> figure it out themselves.
>
Agree, will add a comment about this in commit message.
>>>
>>>> Previously this code was always compiled in for ARCH_EXYNOS. Now it is
>>>> not so I am thinking about selecting necessary drivers from main exynos
>>>> Kconfig symbol. That could be tricky though, because "select" should be
>>>> used only for non-visible symbols.
>>>>
>>>> Any ideas how to solve that?
>>>>
>>>
>>> Is true that select should only be used for non-visible symbols but there
>>> are others user visible symbols that are selected by ARCH_EXYNOS such as
>>> EXYNOS_THERMAL. So I think selecting the regmap syscon reset stuff there
>>> is a sensible option.
>>
>> Selecting from defconfig is not sufficient... since I do not have
>> other idea than selecting then ovak, but Alim please check it whether
>> it does not create circular dependencies on various configs.
>>
>
> Agreed, Kconfig circular dependencies is the reason why select is avoided.
> Fortunately now the 0-day bot analyzes even posted patches so it's possible
> that such an issue could be found even before these patches are merged.
>
ok..will select it from mach-exynos/Kconfig.
Thanks.
>> Best regards,
>> Krzysztof
>>
>
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
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Alim
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Re: [PATCH 7/7] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
Hi krzysztof,
On Mon, Oct 19, 2015 at 6:58 PM, Krzysztof Kozlowski
wrote:
> 2015-10-19 18:56 GMT+09:00 Javier Martinez Canillas :
>> Hello,
>>
>> On 10/19/2015 09:00 AM, Krzysztof Kozlowski wrote:
>>> On 19.10.2015 15:03, Alim Akhtar wrote:
>>>> Now we can use the generic syscon-{reboot/poweroff} drivers,
>>>> so we don't need special handling for reboot/poweroff in
>>>> exynos pmu driver. This patch remove the same.
>>>>
>>>> Signed-off-by: Alim Akhtar
>>>> ---
>>>> arch/arm/mach-exynos/pmu.c | 43
>>>> ---
>>>> 1 file changed, 43 deletions(-)
>>>
>>> I think that removal of this stuff will effectively remove the
>>> restart/poweroff handlers from:
>>> 1. Other defconfigs, like multi_v7
>>> 2. Custom configs.
>>>
>>
>> This will also break old DTBs that don't have a "syscon-poweroff" device
>> node that contains the necessary PMU regmap, offset and mask information.
>
> I am not sure whether this is ABI break issue. There was no compatible
> mentioning that "reset works" which now would be replaced. The
> existing PMU compatible (like samsung,exynos4412-pmu) does not mention
> "reset" as a feature coming with this compatible.
>
> So no ABI break.
>
You are right, there is no DT ABI break here.
>
>>
>>> Previously this code was always compiled in for ARCH_EXYNOS. Now it is
>>> not so I am thinking about selecting necessary drivers from main exynos
>>> Kconfig symbol. That could be tricky though, because "select" should be
>>> used only for non-visible symbols.
>>>
>>> Any ideas how to solve that?
>>>
>>
>> Is true that select should only be used for non-visible symbols but there
>> are others user visible symbols that are selected by ARCH_EXYNOS such as
>> EXYNOS_THERMAL. So I think selecting the regmap syscon reset stuff there
>> is a sensible option.
>
> Selecting from defconfig is not sufficient... since I do not have
> other idea than selecting then ovak, but Alim please check it whether
> it does not create circular dependencies on various configs.
>
I checked in multi_v7_defconfig SYSCON_RESET is already enabled by
default. so I doubt we are going to run into any circular
dependencies, will check again..thanks.
> Best regards,
> Krzysztof
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--
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Alim
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Re: [PATCH 5/7] ARM: exynos_defconfig: Normalize exynos defconfig
Hi Javier, On Mon, Oct 19, 2015 at 6:55 PM, Javier Martinez Canillas wrote: > Hello Alim, > > On 10/19/2015 08:03 AM, Alim Akhtar wrote: >> make savedefconfig result in some difference, lets normalize the >> defconfig. >> >> Signed-off-by: Alim Akhtar >> --- > > Did you make savedefconfig against v4.3-rc6 or tot linux-next? > These are based on v4.3-rc5. > I remember we had issues in the past due savedefconfig made against > linux-next but then some of the patches in linux-next not making it > to the next release. So I think it should be good to mention what's > the base used for this patch. > Ah, ok I didn't follow that, will check again on Linux-next as well as on 4.3-rc5 >> arch/arm/configs/exynos_defconfig |8 ++-- >> 1 file changed, 2 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm/configs/exynos_defconfig >> b/arch/arm/configs/exynos_defconfig >> index 1ff2bfa2e183..3349713e6c63 100644 >> --- a/arch/arm/configs/exynos_defconfig >> +++ b/arch/arm/configs/exynos_defconfig >> @@ -99,10 +99,8 @@ CONFIG_SENSORS_LM90=y >> CONFIG_SENSORS_NTC_THERMISTOR=y >> CONFIG_SENSORS_PWM_FAN=y >> CONFIG_SENSORS_INA2XX=y >> -CONFIG_THERMAL=y >> CONFIG_CPU_THERMAL=y >> CONFIG_THERMAL_EMULATION=y >> -CONFIG_EXYNOS_THERMAL=y > > I would prefer to split all the changes that removes symbols into a > separate patch explaining why these are not needed anymore (i.e: it > is selected now by symbol $foo). > Ok ..let me rebase my patches and check these config changes again >> CONFIG_WATCHDOG=y >> CONFIG_S3C2410_WATCHDOG=y >> CONFIG_MFD_CROS_EC=y >> @@ -127,14 +125,14 @@ CONFIG_REGULATOR_S2MPS11=y >> CONFIG_REGULATOR_S5M8767=y >> CONFIG_REGULATOR_TPS65090=y >> CONFIG_DRM=y >> -CONFIG_DRM_NXP_PTN3460=y >> -CONFIG_DRM_PARADE_PS8622=y >> CONFIG_DRM_EXYNOS=y >> CONFIG_DRM_EXYNOS_FIMD=y >> CONFIG_DRM_EXYNOS_DSI=y >> CONFIG_DRM_EXYNOS_HDMI=y >> CONFIG_DRM_PANEL_SIMPLE=y >> CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y >> +CONFIG_DRM_NXP_PTN3460=y >> +CONFIG_DRM_PARADE_PS8622=y > > Moving these DRM bridge symbols to match savedefconfig is ok IMHO. > >> CONFIG_FB_SIMPLE=y >> CONFIG_EXYNOS_VIDEO=y >> CONFIG_EXYNOS_MIPI_DSI=y >> @@ -175,7 +173,6 @@ CONFIG_RTC_DRV_S5M=y >> CONFIG_RTC_DRV_S3C=y >> CONFIG_DMADEVICES=y >> CONFIG_PL330_DMA=y >> -CONFIG_CHROME_PLATFORMS=y >> CONFIG_CROS_EC_CHARDEV=y >> CONFIG_COMMON_CLK_MAX77686=y >> CONFIG_COMMON_CLK_MAX77802=y >> @@ -190,7 +187,6 @@ CONFIG_PWM_SAMSUNG=y >> CONFIG_PHY_EXYNOS5250_SATA=y >> CONFIG_EXT2_FS=y >> CONFIG_EXT3_FS=y >> -CONFIG_EXT4_FS=y >> CONFIG_MSDOS_FS=y >> CONFIG_VFAT_FS=y >> CONFIG_TMPFS=y >> > > Same comment than above, I would prefer these to be split. > > Best regards, > -- > Javier Martinez Canillas > Open Source Group > Samsung Research America > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/7] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
On 10/19/2015 03:26 PM, Javier Martinez Canillas wrote:
Hello,
On 10/19/2015 09:00 AM, Krzysztof Kozlowski wrote:
On 19.10.2015 15:03, Alim Akhtar wrote:
Now we can use the generic syscon-{reboot/poweroff} drivers,
so we don't need special handling for reboot/poweroff in
exynos pmu driver. This patch remove the same.
Signed-off-by: Alim Akhtar
---
arch/arm/mach-exynos/pmu.c | 43 ---
1 file changed, 43 deletions(-)
I think that removal of this stuff will effectively remove the
restart/poweroff handlers from:
1. Other defconfigs, like multi_v7
2. Custom configs.
This will also break old DTBs that don't have a "syscon-poweroff" device
node that contains the necessary PMU regmap, offset and mask information.
Previously this code was always compiled in for ARCH_EXYNOS. Now it is
not so I am thinking about selecting necessary drivers from main exynos
Kconfig symbol. That could be tricky though, because "select" should be
used only for non-visible symbols.
Any ideas how to solve that?
Is true that select should only be used for non-visible symbols but there
are others user visible symbols that are selected by ARCH_EXYNOS such as
EXYNOS_THERMAL. So I think selecting the regmap syscon reset stuff there
is a sensible option.
Yes, another example is MFD_SYSYCON which is selected from Kconfig.
Also CONFIG_POWER_RESET_SYSCON is enable in arch/arm64/config/defconfig.
So both approaches are taken here.
will go with maintainer suggestion here.
Best regards,
Krzysztof
Best regards,
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[PATCH] arm64: dts: Add reboot node for exynos7
This patch add syscon-reboot node to reboot exynos7 based SoCs.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 4d132692996f..1bc8e15363e8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -450,6 +450,13 @@
reg = <0x105c 0x5000>;
};
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
rtc: rtc@1059 {
compatible = "samsung,s3c6410-rtc";
reg = <0x1059 0x100>;
--
1.7.10.4
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Re: [PATCH 7/7] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
Hello Krzysztof,
On 10/19/2015 12:30 PM, Krzysztof Kozlowski wrote:
On 19.10.2015 15:03, Alim Akhtar wrote:
Now we can use the generic syscon-{reboot/poweroff} drivers,
so we don't need special handling for reboot/poweroff in
exynos pmu driver. This patch remove the same.
Signed-off-by: Alim Akhtar
---
arch/arm/mach-exynos/pmu.c | 43 ---
1 file changed, 43 deletions(-)
I think that removal of this stuff will effectively remove the
restart/poweroff handlers from:
1. Other defconfigs, like multi_v7
2. Custom configs.
Well, I did have a plan to enable it on multi_v7
Not sure about other custom configs, if there are some, they should also
enable it I feel.
Previously this code was always compiled in for ARCH_EXYNOS. Now it is
not so I am thinking about selecting necessary drivers from main exynos
Kconfig symbol. That could be tricky though, because "select" should be
used only for non-visible symbols.
Probably adding these to mach-exynos/Kconfig as a "select" will do.
Any ideas how to solve that?
Best regards,
Krzysztof
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index de68938ee6aa..393c04aa727e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,9 +14,6 @@
#include
#include
#include
-#include
-#include
-
#include "exynos-pmu.h"
#include "regs-pmu.h"
@@ -681,23 +678,6 @@ static unsigned int const
exynos5420_list_disable_pmu_reg[] = {
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
};
-static void exynos_power_off(void)
-{
- unsigned int tmp;
-
- pr_info("Power down.\n");
- tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
- tmp ^= (1 << 8);
- pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
-
- /* Wait a little so we don't give a false warning below */
- mdelay(100);
-
- pr_err("Power down failed, please power off system manually.\n");
- while (1)
- ;
-}
-
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
{
u32 this_cluster;
@@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void)
pr_info("EXYNOS5420 PMU initialized\n");
}
-static int pmu_restart_notify(struct notifier_block *this,
- unsigned long code, void *unused)
-{
- pmu_raw_writel(0x1, EXYNOS_SWRESET);
-
- return NOTIFY_DONE;
-}
-
static const struct exynos_pmu_data exynos3250_pmu_data = {
.pmu_config = exynos3250_pmu_config,
.pmu_init = exynos3250_pmu_init,
@@ -940,20 +912,11 @@ static const struct of_device_id
exynos_pmu_of_device_ids[] = {
{ /*sentinel*/ },
};
-/*
- * Exynos PMU restart notifier, handles restart functionality
- */
-static struct notifier_block pmu_restart_handler = {
- .notifier_call = pmu_restart_notify,
- .priority = 128,
-};
-
static int exynos_pmu_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmu_base_addr = devm_ioremap_resource(dev, res);
@@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pmu_context);
- ret = register_restart_handler(&pmu_restart_handler);
- if (ret)
- dev_warn(dev, "can't register restart handler err=%d\n", ret);
-
- pm_power_off = exynos_power_off;
-
dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers
On 10/19/2015 12:24 PM, Krzysztof Kozlowski wrote:
On 19.10.2015 15:03, Alim Akhtar wrote:
...
Hi,
I am happy to see more contributions from your side! Keep it up. :)
Thank you! will keep finding time and doing it.
However this empty space in your cover letter is the place for
description of the patchset. What do you want to achieve here? What kind
of problem are you solving? What features are you adding? Any dependencies?
Ah, my bad, I used --compose option with git-send-email and did composed
the message, somehow it got missed. Will take care.
The motivation came when I tried to used reboot/poweroff on exynos7, and
since exynos7 has not added/enabled PMU and does not have access to
arch/arm/mach-exynos, so option are to have a reboot/restart driver or
we move pmu.c out of mach-exynos. I know there where some effort in past
to move pmu.c to drivers, but I feel that is still WIP.
And then I came across this generic syscon regmap based driver which are
already in place, so just used it.
Hope that helps.
Best regards,
Krzysztof
Alim Akhtar (7):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos_defconfig: Normalize exynos defconfig
ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
drivers
ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/configs/exynos_defconfig | 11 +-
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 61 insertions(+), 49 deletions(-)
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[PATCH 7/7] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
Now we can use the generic syscon-{reboot/poweroff} drivers,
so we don't need special handling for reboot/poweroff in
exynos pmu driver. This patch remove the same.
Signed-off-by: Alim Akhtar
---
arch/arm/mach-exynos/pmu.c | 43 ---
1 file changed, 43 deletions(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index de68938ee6aa..393c04aa727e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,9 +14,6 @@
#include
#include
#include
-#include
-#include
-
#include "exynos-pmu.h"
#include "regs-pmu.h"
@@ -681,23 +678,6 @@ static unsigned int const
exynos5420_list_disable_pmu_reg[] = {
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
};
-static void exynos_power_off(void)
-{
- unsigned int tmp;
-
- pr_info("Power down.\n");
- tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
- tmp ^= (1 << 8);
- pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
-
- /* Wait a little so we don't give a false warning below */
- mdelay(100);
-
- pr_err("Power down failed, please power off system manually.\n");
- while (1)
- ;
-}
-
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
{
u32 this_cluster;
@@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void)
pr_info("EXYNOS5420 PMU initialized\n");
}
-static int pmu_restart_notify(struct notifier_block *this,
- unsigned long code, void *unused)
-{
- pmu_raw_writel(0x1, EXYNOS_SWRESET);
-
- return NOTIFY_DONE;
-}
-
static const struct exynos_pmu_data exynos3250_pmu_data = {
.pmu_config = exynos3250_pmu_config,
.pmu_init = exynos3250_pmu_init,
@@ -940,20 +912,11 @@ static const struct of_device_id
exynos_pmu_of_device_ids[] = {
{ /*sentinel*/ },
};
-/*
- * Exynos PMU restart notifier, handles restart functionality
- */
-static struct notifier_block pmu_restart_handler = {
- .notifier_call = pmu_restart_notify,
- .priority = 128,
-};
-
static int exynos_pmu_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmu_base_addr = devm_ioremap_resource(dev, res);
@@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pmu_context);
- ret = register_restart_handler(&pmu_restart_handler);
- if (ret)
- dev_warn(dev, "can't register restart handler err=%d\n", ret);
-
- pm_power_off = exynos_power_off;
-
dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
}
--
1.7.10.4
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[PATCH 6/7] ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff} drivers
Enable CONFIG_POWER_RESET_SYSCON and CONFIG_POWER_RESET_SYSCON_POWEROFF to allow exynos SoC to make use of generic syscon based reboot/poweroff drivers. Signed-off-by: Alim Akhtar --- arch/arm/configs/exynos_defconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 3349713e6c63..cbc2e96b76a3 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -95,6 +95,9 @@ CONFIG_BATTERY_MAX17042=y CONFIG_CHARGER_MAX14577=y CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_TPS65090=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_NTC_THERMISTOR=y CONFIG_SENSORS_PWM_FAN=y -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5410 SoC.
Signed-off-by: Alim Akhtar
---
arch/arm/boot/dts/exynos5410.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
index 731eefd23fa9..b9bef8b5ffc9 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -102,6 +102,20 @@
reg = <0x1004 0x5000>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>;
+ mask = <0x5200>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
mct: mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0xB00>;
--
1.7.10.4
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[PATCH 5/7] ARM: exynos_defconfig: Normalize exynos defconfig
make savedefconfig result in some difference, lets normalize the defconfig. Signed-off-by: Alim Akhtar --- arch/arm/configs/exynos_defconfig |8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 1ff2bfa2e183..3349713e6c63 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -99,10 +99,8 @@ CONFIG_SENSORS_LM90=y CONFIG_SENSORS_NTC_THERMISTOR=y CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_INA2XX=y -CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y -CONFIG_EXYNOS_THERMAL=y CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_CROS_EC=y @@ -127,14 +125,14 @@ CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_DRM=y -CONFIG_DRM_NXP_PTN3460=y -CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_EXYNOS=y CONFIG_DRM_EXYNOS_FIMD=y CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y +CONFIG_DRM_NXP_PTN3460=y +CONFIG_DRM_PARADE_PS8622=y CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y @@ -175,7 +173,6 @@ CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y -CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC_CHARDEV=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_MAX77802=y @@ -190,7 +187,6 @@ CONFIG_PWM_SAMSUNG=y CONFIG_PHY_EXYNOS5250_SATA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_EXT4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs.
Signed-off-by: Alim Akhtar
---
arch/arm/boot/dts/exynos5.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 110dbd4fb884..1313777618b7 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -88,6 +88,20 @@
status = "disabled";
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>;
+ mask = <0x5200>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
fimd: fimd@1440 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
--
1.7.10.4
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[PATCH 2/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos4 SoC.
Signed-off-by: Alim Akhtar
---
arch/arm/boot/dts/exynos4.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 98c0a368b777..79015320cdb6 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -158,6 +158,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>;
+ mask = <0x5200>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
dsi_0: dsi@11C8 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C8 0x1>;
--
1.7.10.4
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[PATCH 1/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.
Signed-off-by: Alim Akhtar
---
arch/arm/boot/dts/exynos3250.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def482fc3..af5d9ad4c7b7 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <&gic>;
};
+ poweroff: syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmu_system_controller>;
+ offset = <0x330C>;
+ mask = <0x5200>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x0400>;
+ mask = <0x1>;
+ };
+
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
--
1.7.10.4
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[PATCH 0/7] Switch to generic syscon regmap based drivers
Alim Akhtar (7):
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
ARM: exynos_defconfig: Normalize exynos defconfig
ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
drivers
ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
arch/arm/boot/dts/exynos3250.dtsi | 14
arch/arm/boot/dts/exynos4.dtsi| 14
arch/arm/boot/dts/exynos5.dtsi| 14
arch/arm/boot/dts/exynos5410.dtsi | 14
arch/arm/configs/exynos_defconfig | 11 +-
arch/arm/mach-exynos/pmu.c| 43 -
6 files changed, 61 insertions(+), 49 deletions(-)
--
1.7.10.4
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Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
+CCing kishon Vijay,
On 10/14/2015 06:25 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317 ++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
Re: [PATCH v4 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi,
On Wed, Oct 14, 2015 at 9:31 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 14 October 2015 06:25 PM, Alim Akhtar wrote:
>> From: Seungwon Jeon
>>
>> This patch introduces Exynos UFS PHY driver. This driver
>> supports to deal with phy calibration and power control
>> according to UFS host driver's behavior.
>>
>> Signed-off-by: Seungwon Jeon
>> Signed-off-by: Alim Akhtar
>> Cc: Kishon Vijay Abraham I
>> ---
>> drivers/phy/Kconfig|7 +
>> drivers/phy/Makefile |1 +
>> drivers/phy/phy-exynos-ufs.c | 257
>>
>> drivers/phy/phy-exynos-ufs.h | 88
>> drivers/phy/phy-exynos7-ufs.h | 89 +
>> include/linux/phy/phy-exynos-ufs.h | 101 ++
>> 6 files changed, 543 insertions(+)
>> create mode 100644 drivers/phy/phy-exynos-ufs.c
>> create mode 100644 drivers/phy/phy-exynos-ufs.h
>> create mode 100644 drivers/phy/phy-exynos7-ufs.h
>> create mode 100644 include/linux/phy/phy-exynos-ufs.h
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573d0bab..499eec4a967c 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -371,4 +371,11 @@ config PHY_BRCMSTB_SATA
>> Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
>> Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>>
>> +config PHY_EXYNOS_UFS
>> + tristate "EXYNOS SoC series UFS PHY driver"
>> + depends on OF && ARCH_EXYNOS || COMPILE_TEST
>> + select GENERIC_PHY
>> + help
>> + Support for UFS PHY on Samsung EXYNOS chipsets.
>> +
>> endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c18fc12..2a312ca20795 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
>> obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
>> obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
>> obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
>> +obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
>> diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
>> new file mode 100644
>> index ..77330b85e3f8
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-ufs.c
>> @@ -0,0 +1,257 @@
>> +/*
>> + * UFS PHY driver for Samsung EXYNOS SoC
>> + *
>> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
>> + * Author: Seungwon Jeon
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "phy-exynos-ufs.h"
>> +
>> +#define for_each_phy_lane(phy, i) \
>> + for (i = 0; i < (phy)->lane_cnt; i++)
>> +#define for_each_phy_cfg(cfg) \
>> + for (; (cfg)->id; (cfg)++)
>> +
>> +#define PHY_DEF_LANE_CNT 1
>> +
>> +static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
>> + const struct exynos_ufs_phy_cfg *cfg, u8 lane)
>> +{
>> + enum {LANE_0, LANE_1}; /* lane index */
>> +
>> + switch (lane) {
>> + case LANE_0:
>> + writel(cfg->val, (phy)->reg_pma + cfg->off_0);
>> + break;
>> + case LANE_1:
>> + if (cfg->id == PHY_TRSV_BLK)
>> + writel(cfg->val, (phy)->reg_pma + cfg->off_1);
>> + break;
>> + }
>> +}
>> +
>> +static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
>> +{
>> + if (IS_PWR_MODE_ANY(desc))
>> + return true;
>> +
>> + if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
>> + return true;
>> +
>> + if (COMP_PWR_MODE(required_pwr, desc))
>> + return true;
>> +
>> + if (COMP_PWR_MODE_MD(required_pwr, desc) &&
>> + COMP_PWR_MODE_GEAR(required_pwr, desc) &&
>> + COMP_PWR_MODE
[PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317 ++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
+
+static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct
[PATCH v4 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
From: Seungwon Jeon
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index ..042dedf4e323
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,104 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible name, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg : Should contain HCI, vendor specific, UNIPRO and
+ UFS protector address space
+- reg-names: "hci", "vs_hci", "unipro", "ufsp";
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ "core", "sclk_unipro_main", "ref" and ref_parent
+
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change, possible
values are
+ "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+ can be one of "HS_rate_b" or "HS_rate_a"
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
+ allowed step size is 0 to 3
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+range is 1 to 9
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+
[PATCH v4 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 075b7bf13080..358d9114a1a5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2592,7 +2590,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2608,6 +2606,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9c69dd2f3672..8cad52c072d4 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -666,6 +666,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v4 08/11] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 33 +
drivers/scsi/ufs/ufshcd.h | 10 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index eeb7835c52ab..075b7bf13080 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2394,7 +2403,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2403,7 +2412,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2418,6 +2427,22 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ ufshcd_vops_hibern8_notify(hba, en, PRE_CHANGE);
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ ufshcd_vops_hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index b3dd08420100..9c69dd2f3672 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -283,6 +285,7 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
@@ -830,4 +833,11 @@ static inline void
ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
if (hba->vops && hba->vops->specify_nexus_t_tm_req)
hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
}
+
+static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
+ bool en, enum ufs_notify_change_status status)
+{
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, status);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v4 07/11] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 +++
drivers/scsi/ufs/ufshcd.h | 19 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e8b96ec65987..eeb7835c52ab 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1579,7 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3842,6 +3844,7 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ ufshcd_vops_specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 500e137bf68a..b3dd08420100 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -259,6 +259,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -280,6 +283,9 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void(*dbg_register_dump)(struct ufs_hba *hba);
@@ -811,4 +817,17 @@ static inline void ufshcd_vops_dbg_register_dump(struct
ufs_hba *hba)
hba->vops->dbg_register_dump(hba);
}
+static inline void ufshcd_vops_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+ int tag, struct ufshcd_lrb *lrbp)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
+}
+
+static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
+ int free_slot, u8 tm_function)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v4 05/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2b16eb363203..ca7483cd899e 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3199,7 +3199,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index d625d01110b0..4ae32e9316de 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -479,6 +479,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 06/11] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 75 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ca7483cd899e..e8b96ec65987 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2715,6 +2761,31 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 4ae32e9316de..500e137bf68a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -485,6 +485,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 587a9c8fbfe9..2b16eb363203 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -356,7 +356,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3685,7 +3702,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6cd542a803d5..d625d01110b0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -474,6 +474,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 03/11] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 131c72038bf8..587a9c8fbfe9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2570d9477b37..6cd542a803d5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -467,6 +467,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
+* word, but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 01/11] Documentation: samsung-phy: Add dt bindings for UFS
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/phy/samsung-phy.txt| 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a633e0..c92ce537ceec 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
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[PATCH v4 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 257
drivers/phy/phy-exynos-ufs.h | 88
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 101 ++
6 files changed, 543 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573d0bab..499eec4a967c 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -371,4 +371,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c18fc12..2a312ca20795 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..77330b85e3f8
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,257 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+static int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+static void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+
+ ufs_phy->lane_cnt = lan
[PATCH v4 00/11] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. NOTE: ** This series has a dependency on [4]. ** -Changes since v3: * Fixed compilation warrings as reported by "Kbuild Test Robot"[5]. * Restructure the driver to make it as a platform driver, rebased on top of [4]. * Addressed review comments from Arnd Bergmann[5]. * Other misc changes and improvements. -Changes since v2: * Addressed review comments from Kishon[1] and Rob Herring [2] * Splited ufs dt binding documetation from ufs driver patch -Changes since v1: * Addressed review comments from Alexey[3] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/9/18/29 [2]-> https://lkml.org/lkml/2015/9/21/668 [3]-> https://lkml.org/lkml/2015/8/23/124 [4]-> https://lkml.org/lkml/2015/9/2/364 [5]-> https://lkml.org/lkml/2015/10/1/402 This patch set is tested on exynos7-espresso board. Alim Akhtar (1): Documentation: samsung-phy: Add dt bindings for UFS Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 257 drivers/phy/phy-exynos-ufs.h | 88 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1317 drivers/scsi/ufs/ufs-exynos.h | 247 drivers/scsi/ufs/ufshcd.c | 168 ++- drivers/scsi/ufs/ufshcd.h | 54 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 101 ++ 18 files changed, 2695 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
On Wed, Oct 14, 2015 at 7:50 AM, Krzysztof Kozlowski wrote: > On 14.10.2015 11:13, Alim Akhtar wrote: >> On Wed, Oct 14, 2015 at 6:45 AM, Krzysztof Kozlowski >> wrote: >>> On 14.10.2015 10:06, Alim Akhtar wrote: >>>> +Doug >>>> Hello, >>>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>>> and SDR104 modes. >>>> >>>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>>> >>>> What I remember is, one need to set "broken-cd" property also in order >>>> to make it work because of the vqmmc and vmmc connection on board. I >>>> didn't find the link right now, but you can search on the web, there >>>> was a long discussion about handling this. >>>> Have not checked it recently, so not sure if this got broken somehow. >>>> >>> >>> Please, don't top post. >>> >> I am sorry, but I didn't get this, what is the guide line here??? > > I mean reply inline, under the other person's quote, not above it. > > And some old, really old joke: > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing in e-mail? > > :) > I see..got it..thanks for clarification. > Best regards, > Krzysztof > -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
On Wed, Oct 14, 2015 at 6:45 AM, Krzysztof Kozlowski wrote: > On 14.10.2015 10:06, Alim Akhtar wrote: >> +Doug >> Hello, >> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >> and SDR104 modes. >> >> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >> >> What I remember is, one need to set "broken-cd" property also in order >> to make it work because of the vqmmc and vmmc connection on board. I >> didn't find the link right now, but you can search on the web, there >> was a long discussion about handling this. >> Have not checked it recently, so not sure if this got broken somehow. >> > > Please, don't top post. > I am sorry, but I didn't get this, what is the guide line here??? > I am not a SD/MMC specialist (I do not feel enough confident in its > internals) but the datasheet for 5422 does not mention UHS. However it > mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This > does not look like UHS... > https://www.sdcard.org/developers/overview/bus_speed/ > This of course is not a definite proof that 5422 does not support UHS. I > am just saying that I couldn't find any information that *it does*. > > Best regards, > Krzysztof > -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
On Wed, Oct 14, 2015 at 7:22 AM, Krzysztof Kozlowski wrote: > On 14.10.2015 10:40, Jaehoon Chung wrote: >> On 10/14/2015 10:15 AM, Krzysztof Kozlowski wrote: >>> On 14.10.2015 10:06, Alim Akhtar wrote: >>>> +Doug >>>> Hello, >>>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 >>>> and SDR104 modes. >>>> >>>> [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html >>>> >>>> What I remember is, one need to set "broken-cd" property also in order >>>> to make it work because of the vqmmc and vmmc connection on board. I >>>> didn't find the link right now, but you can search on the web, there >>>> was a long discussion about handling this. >>>> Have not checked it recently, so not sure if this got broken somehow. >>>> >>> >>> Please, don't top post. >>> >>> I am not a SD/MMC specialist (I do not feel enough confident in its >>> internals) but the datasheet for 5422 does not mention UHS. However it >>> mentions "High Speed DDR Mode with 200 MHz clock rate (HS400)". This >>> does not look like UHS... >> >> You're right. It's not UHS mode. it mentions eMMC's HS400 mode. >> UHS and HS400 are difference mode. >> >> eMMC mode are supported >> >>> https://www.sdcard.org/developers/overview/bus_speed/ >>> This of course is not a definite proof that 5422 does not support UHS. I >>> am just saying that I couldn't find any information that *it does*. >> >> Well, I think you want to know whether it supported or not. >> Then you can find the information at User manual. >> In mobile storage part of User manual, it described the overview. >> Mobile storage host supports these specification: >> - Secure Digital memory (SD memory version 3.0) >> - Secure Digital I/O SDIO (SDIO version 3.0) >> - etc... >> >> SD3.0 is supported UHS-I mode. >> If user manual of exynos5422 is mentioned this specification, it should be >> supported UHS-I mode. > > Thanks! Indeed datasheet mentions that supported SD and SDIO is version > 3.0 (not 3.01... which seems irrelevant because 3.0 introduced UHS-I, > right?). > Yes, your understanding is right. SD3.0 does includes UHS-I. > Best regards, > Krzysztof -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support
+Doug Hello, AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 and SDR104 modes. [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html What I remember is, one need to set "broken-cd" property also in order to make it work because of the vqmmc and vmmc connection on board. I didn't find the link right now, but you can search on the web, there was a long discussion about handling this. Have not checked it recently, so not sure if this got broken somehow. Regards, Alim On Wed, Oct 14, 2015 at 5:29 AM, Krzysztof Kozlowski wrote: > On 14.10.2015 01:27, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 09:13, Krzysztof Kozlowski >> wrote: >>> >>> On 13.10.2015 12:08, Anand Moon wrote: Hi Krzysztof, On 13 October 2015 at 05:44, Krzysztof Kozlowski wrote: > On 13.10.2015 00:32, Anand Moon wrote: >> Hi Krzysztof, >> >> On 12 October 2015 at 11:14, Krzysztof Kozlowski >> wrote: >>> On 12.10.2015 00:46, Anand Moon wrote: Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>> >>> This description is not entirely correct. The MMC driver already >>> supports these UHS speeds (you did not any code) so you rather enabled >>> it (description of bindings says "is supported"). >>> >>> You mentioned DDR50 but I don't see respective property below. >>> >>> How do you know that these modes are really supported? I don't know. Can >>> you convince me? >> >> Setting this DDR50 capability give me this error. That's the reason to >> drop this capability. > > But you mentioned it in commit message! "Added support for UHS-I ... > (DDR50)" > > In the same time dropping DDR50 is not an sufficient proof that "SDR50 > and SDR104 are really supported". > These changes are related to the microSD card capabilities. So SDR50 have better frequency over DDR50. On the same Sandisk card. When the card select the capability for DDR50 --- [4.001477] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot req 5000Hz, actual 5000HZ div = 0) [4.001604] mmc1: new ultra high speed DDR50 SDHC card at address [4.004505] mmcblk0: mmc1: SL32G 29.7 GiB [4.009179] mmcblk0: error -110 sending status command, retrying [4.009271] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0x900 [4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [4.025563] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot req 40Hz, actual 396825HZ div = 63) [4.067770] Console: switching to colour frame buffer device 274x77 [4.098782] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot req 5000Hz, actual 5000HZ div = 0) [4.099692] mmc1: tried to reset card [4.101332] mmcblk0: p1 p2 When the card select the capability for SDR50 - [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 1Hz (slot req 1Hz, actual 1HZ div = 0) [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address [ 2.455984] mmcblk0: mmc1: SL32G 29.7 GiB [ 2.461743] mmcblk0: p1 p2 Which will relate to better read/write speed. >>> >>> Which is not an answer to my question. To none of my previous questions. >>> >> >> Basically UHS-I capability (sd-uhs-sdr12, sd-uhs-sdr25, sd-uhs-sdr50, >> sd-uhs-sdr104) help tune speed supported for mmc >> >> I have tired to compare the speed on high speed UHS-I vs ultra high >> speed UHS-I using izone utility. >> >> [2.572469] mmc_host mmc1: Bus speed (slot 0) = 5000Hz (slot >> req 5000Hz, actual 5000HZ div = 0) >> [2.572609] mmc1: new high speed SDHC card at address >> >> Command line used: ./iozone -L64 -S32 -azecwI -+n -r4k -r64k >> -r128k -s10M -i0 -i1 -i2 -f datafile -Rb out.xls >> Output is in kBytes/sec >> Time Resolution = 0.01 seconds. >> Processor cache size set to 32 kBytes. >> Processor cache line size set to 64 bytes. >> File stride size set to 17 * record size. >> random >> random bkwdrecordstride >> kB reclenwrite rewritereadrereadread >> write read rewrite read fwrite frewritefread >> freread >>10240 4 16310 65560 5538 >> 982 >>10240 64 8828018897017994 >> 303 >>10240 128 6269020670020128 >> 1096 >>
Re: [PATCH v3 12/13] scsi: ufs-exynos: add UFS host support for Exynos SoCs
On 10/13/2015 05:08 PM, Arnd Bergmann wrote: On Tuesday 13 October 2015 16:49:39 Alim Akhtar wrote: diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h new file mode 100644 index 000..58aa714 --- /dev/null +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -0,0 +1,463 @@ +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _UFS_EXYNOS_H_ +#define _UFS_EXYNOS_H_ You have a lot of things in this header that are only used in one of the .c files, so just move them there and make the header as small as possible. hmm..these are mostly the registers defines, will removes the one which are not being used as of now. Do you think I should sill move them to .c file? Yes. No need to remove the unused register definitions, just don't put them into a separate header if they are only used in one place. Ok will do that in v4. Thanks. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] phy: exynos-ufs: exynos_ufs_phy_calibrate() can be static
HI
How I am support to handle this patch? Should I just fix these warnings
in my patch or I just add this as a separate patch on the top of the series?
On 10/01/2015 04:34 PM, kbuild test robot wrote:
Signed-off-by: Fengguang Wu
---
phy-exynos-ufs.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
index 343fcaf..835ee78 100644
--- a/drivers/phy/phy-exynos-ufs.c
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -66,7 +66,7 @@ static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
return false;
}
-int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8 pwr)
+static int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8
pwr)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
@@ -93,14 +93,14 @@ out:
return 0;
}
-void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+static void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
ufs_phy->lane_cnt = lane_cnt;
}
-int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
+static int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
const unsigned int timeout_us = 10;
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Re: [PATCH v3 11/13] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
Hi Arnd, On 10/01/2015 05:07 PM, Arnd Bergmann wrote: On Thursday 01 October 2015 13:39:28 Alim Akhtar wrote: From: Seungwon Jeon This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- .../devicetree/bindings/ufs/ufs-exynos.txt | 93 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt new file mode 100644 index 000..00df72e --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt @@ -0,0 +1,93 @@ +* Exynos Universal Flash Storage (UFS) Host Controller + +UFSHC nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. + +Required properties: +- compatible: compatible name, contains "samsung,exynos7-ufs" +- interrupts: +- reg : This needs a list of all the register ranges, which order they are in and what the respective strings must be. will add the details +- clocks: List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. You need to list the names you require here. Also the 'clock specifier' includes the phandle, it's not a pair but just a list of specifiers. ok will add +- ufs,pwr-attr-mode : specifies mode value for power mode change +- ufs,pwr-attr-lane : specifies lane count value for power mode change +- ufs,pwr-attr-gear : specifies gear count value for power mode change +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values + +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values + +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY, + this is a boolean property. +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY +- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time +- ufs-pa-tacctivate : specifies time wake-up remote M-RX +- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state These all require a specification of what the allowed values are and/or the units for the numbers. will update the specifications above + + clocks = <&core 0>, <&ref 0>, <&iface 0>; + clock-names = "core_clk", "ref_clk", "iface_clk"; Better rename them to "core", "ref" and "iface", no point requiring to spell out "clk" here. + ufs,pwr-attr-mode = "FAST"; A string is rather unusual here, what are the allowed values? Could you use a boolean property instead? will update the binding, supported modes are FAST, SLOW, FAST_auto etc, so kept the string for more readability + ufs,pwr-attr-lane = /bits/ 8 <2>; + ufs,pwr-attr-gear = /bits/ 8 <2>; Why the "/bits/ 8" ? I am using of_property_read_u8() to read 8 bit value from property. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 12/13] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Arnd,
On 10/01/2015 05:42 PM, Arnd Bergmann wrote:
On Thursday 01 October 2015 13:39:29 Alim Akhtar wrote:
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ int ret;
+ const char *const clks[] = {
+ "mout_sclk_combo_phy_embedded",
+ "top_sclk_phy_fsys1_26m",
+ };
+
These clocks are neither in the binding nor in the example.
ok, I am cleaning this a bit, this will come from DT.
+struct exynos_ufs_drv_data exynos_ufs_drvs[] = {
+{
+ .compatible = "samsung,exynos7-ufs",
+ .uic_attr = &exynos7_uic_attr,
+ .quirks = UFSHCI_QUIRK_BYTE_ALIGN_UTRD |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCI_QUIRK_BROKEN_HCE |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+ .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+ .drv_init = exynos7_ufs_drv_init,
+ .pre_link = exynos7_ufs_pre_link,
+ .post_link = exynos7_ufs_post_link,
+ .pre_pwr_change = exynos7_ufs_pre_pwr_change,
+ .post_pwr_change= exynos7_ufs_post_pwr_change,
+}, {
+}, };
The indentation is a bit unusual here.
hmm..ok will change
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.h b/drivers/scsi/ufs/ufs-exynos-hw.h
new file mode 100644
index 000..8464ec8
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.h
@@ -0,0 +1,43 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _UFS_EXYNOS_HW_H_
+#define _UFS_EXYNOS_HW_H_
+
+#include "ufs-exynos.h"
+#include "unipro.h"
+
+static struct exynos_ufs_uic_attr exynos7_uic_attr = {
You cannot put 'static' variables into a header file.
will remove
+
+/**
+ * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
+ * Control should be disabled in the below cases
+ * - Before host controller S/W reset
+ * - Access to UFS protector's register
+ */
+static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
+{
+ u32 misc = hci_readl(ufs, HCI_MISC);
+
+ if (en)
+ hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
+ else
+ hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
Does this need a spinlock to ensure the change is done atomically?
will check and if needed will add,
+}
+
+static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
+{
+ u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
+ u32 misc = hci_readl(ufs, HCI_MISC);
+
+ if (en) {
+ hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
+ hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
+ } else {
+ hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
+ hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
+ }
same here.
+
+static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ struct list_head *head = &hba->clk_list_head;
+ struct ufs_clk_info *clki;
+ u32 pclk_rate;
+ u32 f_min, f_max;
+ u8 div = 0;
+ int ret = 0;
+
+ if (!head || list_empty(head))
+ goto out;
+
+ list_for_each_entry(clki, head, list) {
+ if (!IS_ERR_OR_NULL(clki->clk)) {
+ if (!strcmp(clki->name, "aclk_ufs"))
+ ufs->clk_hci_core = clki->clk;
+ else if (!strcmp(clki->name, "sclk_unipro_apb"))
+ ufs->clk_apb = clki->clk;
+ else if (!strcmp(clki->name, "sclk_unipro_main"))
+ ufs->clk_unipro_main = clki->clk;
+ }
+ }
Using IS_ERR_OR_NULL is normally a bug. Also the list/loop can likely be
replaced with another way to express this.
ok
+ do {
+ delta = h8_time - ktime_us_delta(ktime_get(),
+ ufs->entry_hibern8_t);
+ if (delta <= 0)
+ break;
+
+ us = min_t(s64, delta, USEC_PER_MSEC);
+ if (us >
[PATCH v2] arm: dts: Fix audio card detection on peach boards
Since commit 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards"),
sound card detection is broken on peach boards and gives below errors:
[3.630457] max98090 7-0010: MAX98091 REVID=0x51
[3.634233] max98090 7-0010: use default 2.8v micbias
[3.640985] snow-audio sound: HiFi <-> 383.i2s mapping ok
[3.645307] max98090 7-0010: Invalid master clock frequency
[3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe()
failed: -22
[3.658914] snow-audio sound: snd_soc_register_card failed (-22)
[3.664366] snow-audio: probe of sound failed with error -22
This patch adds missing assigned-clocks and assigned-clock-parents for
pmu_system_controller node which is used as "mclk" for audio codec.
Signed-off-by: Alim Akhtar
Fixes: 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards")
Cc:
---
Changes since v1:
Addressed Krzysztof's review comments.
arch/arm/boot/dts/exynos5420-peach-pit.dts |5 +
arch/arm/boot/dts/exynos5800-peach-pi.dts |5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c5e11c..1b95da79293c 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -915,6 +915,11 @@
};
};
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_FIN_PLL>;
+};
+
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386b5ae6..8f40c7e549bd 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -878,6 +878,11 @@
};
};
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_FIN_PLL>;
+};
+
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
--
1.7.10.4
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Re: [PATCH] arm: dts: Fix audio card detection on peach boards
Hello Kezysztof
Thanks for your review.
On 10/12/2015 12:17 PM, Krzysztof Kozlowski wrote:
On 12.10.2015 15:26, Alim Akhtar wrote:
Since the merge of 2fad972 ("ARM: dts: Add mclk entry for Peach boards"),
Please switch to longer SHA abbreviation:
$ git config core.abbrev 12
ok, will do thanks
sound card detection is broken on peach boards and gives below errors:
[3.630457] max98090 7-0010: MAX98091 REVID=0x51
[3.634233] max98090 7-0010: use default 2.8v micbias
[3.640985] snow-audio sound: HiFi <-> 383.i2s mapping ok
[3.645307] max98090 7-0010: Invalid master clock frequency
[3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe()
failed: -22
[3.658914] snow-audio sound: snd_soc_register_card failed (-22)
[3.664366] snow-audio: probe of sound failed with error -22
This patch adds missing assigned-clocks and assigned-clock-parents for
pmu_system_controller node which is used as "mclk" for audio codec.
Signed-off-by: Alim Akhtar
Fixes: 2fad972 ("ARM: dts: Add mclk entry for Peach boards")
Cc:
---
arch/arm/boot/dts/exynos5420-peach-pit.dts |5 +
arch/arm/boot/dts/exynos5800-peach-pi.dts |5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..525a93a 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -1056,5 +1056,10 @@
timeout-sec = <32>;
};
+&pmu_system_controller {
Please put the node in alphabetical order.
ok
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_FIN_PLL>;
I might be missing something here but isn't the first clock of
pmu_system_controller already a CLK_FIN_PLL? So you are reparenting the
FIN_PLL to FIN_PLL?
In the same time there is doubled space character after '='.
will remove
+};
+
#include "cros-ec-keyboard.dtsi"
#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..411de8f 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -1019,5 +1019,10 @@
timeout-sec = <32>;
};
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_FIN_PLL>;
Ditto.
Best regards,
Krzysztof
+};
+
#include "cros-ec-keyboard.dtsi"
#include "cros-adc-thermistors.dtsi"
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