[PATCH v7 0/5] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM driver. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel chrome_v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> According to the suggestion from Thierry, I have get rid of the bridge, and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. After backport below patches from linux-next, I can merge this serial into Dave's drm-next branch. 94d5d6a0fbf3 clk: rockchip: add an id for rk3288 crypto clk c6d49fbcfcc4 clk: rockchip: add id for mipidsi sclk on rk3288 a2f4c560f18e clk: rockchip: add mipidsi clock on rk3288 69c923743640 ARM: dts: rockchip: correct the name of REG8 for rk3288-evb-act8846 662513a14c9d ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846 b04061e6599b ARM: dts: rockchip: move the public part to rk3288-evb common Changes in v7: - modify the config to tristate for modules build (Mark Yao) - Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao) - Move the lcd_en control to act8846 dts Changes in v6: - update the document, since the bridge device has been deleted. - move the mipi_en gate to ockchip_drm_crtc_mode_config - Remove the atomic feature check (Mark Yao) - Add atomic API support (Heiko Stübne) - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Chris Zhong (5): drm/rockchip: return a true clock rate to adjusted_mode Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver drm: rockchip: Support Synopsys DW MIPI DSI ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + arch/arm/boot/dts/rk3288-evb-act8846.dts |2 + arch/arm/boot/dts/rk3288-evb.dtsi | 12 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1196 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + 8 files changed, 1327 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/5] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v7: None
Changes in v6:
- update the document, since the bridge device has been deleted.
Changes in v5: None
Changes in v4: None
Changes in v3:
- move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..1753f0c
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,60 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- reg: Represent the physical address range of the controller.
+- interrupts: Represent the controller's interrupt to the CPU(s).
+- clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref) and APB clock(pclk), as described in [1].
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [2].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.3
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[PATCH v7 5/5] ARM: dts: rockchip: add support mipi panel tv080wum-nl0
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v7:
- Move the lcd_en control to act8846 dts
Changes in v6: None
Changes in v5:
- add a blank line befor lcd_en
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb-act8846.dts | 2 ++
arch/arm/boot/dts/rk3288-evb.dtsi| 12 +++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index e662147..7d5475b 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -50,6 +50,8 @@
gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
+ regulator-always-on;
+ regulator-boot-on;
regulator-name = "vcc_lcd";
vin-supply = <&vcc_io>;
};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4faabdb..0c91858 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -183,6 +183,16 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
--
2.6.3
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[PATCH v7 4/5] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- modify the clk name to SCLK_MIPIDSI_24M
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 04ea209..6b21a87 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -800,6 +800,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -833,6 +837,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -873,6 +881,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
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Re: [PATCH v6 0/6] Add mipi dsi support for rk3288
Hi Heiko Thanks for your reminder. I have post the v6.1 mipi patch with the atomic support. <https://patchwork.kernel.org/patch/7881781/> On 12/17/2015 05:29 PM, Heiko Stübner wrote: Hi Chris, Am Mittwoch, 16. Dezember 2015, 18:10:10 schrieb Chris Zhong: The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM driver. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel chrome_v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> According to the suggestion from Thierry, I have get rid of the bridge, and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. from my point it looks good (although I cannot really speak on the drm-related internals). But I do think we'll be doing atomic modesetting conversion first (last version posted from Mark today), so you should probably make sure your dsi driver still works after that conversion and make changes if needed. Heiko Changes in v6: - update the document, since the bridge device has been deleted. - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Chris Zhong (5): drm/rockchip: return a true clock rate to adjusted_mode Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver drm: rockchip: Support Synopsys DW MIPI DSI ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 Liu Ying (1): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 8 + include/drm/drm_mipi_dsi.h | 14 + 8 files changed, 1351 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 3/6] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6:
- update the document, since the bridge device has been deleted.
Changes in v5: None
Changes in v4: None
Changes in v3:
- move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..1753f0c
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,60 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- reg: Represent the physical address range of the controller.
+- interrupts: Represent the controller's interrupt to the CPU(s).
+- clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref) and APB clock(pclk), as described in [1].
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [2].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.3
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[PATCH v6 5/6] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5:
- modify the clk name to SCLK_MIPIDSI_24M
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index a9270f7..1086761 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -817,6 +817,10 @@
reg = <1>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -853,6 +857,10 @@
reg = <1>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -954,6 +962,37 @@
status = "disabled";
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
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[PATCH v6 6/6] ARM: dts: rockchip: add support mipi panel tv080wum-nl0
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5:
- add a blank line befor lcd_en
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..2014992 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,20 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +261,10 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.3
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[PATCH v6 0/6] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM driver. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel chrome_v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> According to the suggestion from Thierry, I have get rid of the bridge, and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. Changes in v6: - update the document, since the bridge device has been deleted. - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Chris Zhong (5): drm/rockchip: return a true clock rate to adjusted_mode Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver drm: rockchip: Support Synopsys DW MIPI DSI ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 Liu Ying (1): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/drm_mipi_dsi.h | 14 + 8 files changed, 1351 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] arm: dts: rockchip: move the public part to rk3288-evb common
Rk3288-evb-act8846 and rk3288-evb-rk808 are the power boards of
rk3288-evb, they provide the same power supply interface to the
motherboard. Sort out them, put the public part to rk3288-evb.dtsi,
such as gmac and cpu-supply, leaving only the power section.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4
arch/arm/boot/dts/rk3288-evb-rk808.dts | 27 ---
arch/arm/boot/dts/rk3288-evb.dtsi| 37 +++-
3 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 7b768b7..e662147 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -65,10 +65,6 @@
};
};
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
-};
-
&i2c0 {
clock-frequency = <40>;
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 18eb6cb..736b08b 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -43,17 +43,6 @@
/ {
compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
-
- ext_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <12500>;
- clock-output-names = "ext_gmac";
- #clock-cells = <0>;
- };
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
};
&i2c0 {
@@ -244,19 +233,3 @@
};
};
};
-
-&gmac {
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 100>;
- assigned-clocks = <&cru SCLK_MAC>;
- assigned-clock-parents = <&ext_gmac>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- status = "ok";
-};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..4faabdb 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -89,6 +89,13 @@
pwms = <&pwm0 0 100 PWM_POLARITY_INVERTED>;
};
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -160,6 +167,10 @@
};
};
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+};
+
&emmc {
broken-cd;
bus-width = <8>;
@@ -172,11 +183,6 @@
status = "okay";
};
-&hdmi {
- ddc-i2c-bus = <&i2c5>;
- status = "okay";
-};
-
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -191,6 +197,27 @@
vqmmc-supply = <&vccio_sd>;
};
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "ok";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
--
2.6.3
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[PATCH 2/3] ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846
vcc_wl and vcc_lcd are 2 gpio switches for rk3288-evb-act8846 board.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 53d8b08..7b768b7 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -43,6 +43,26 @@
/ {
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
+
+ vcc_lcd: vcc-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ regulator-name = "vcc_lcd";
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_wl: vcc-wl {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pwr>;
+ regulator-name = "vcc_wl";
+ vin-supply = <&vcc_18>;
+ };
};
&cpu0 {
@@ -189,3 +209,17 @@
};
};
};
+
+&pinctrl {
+ lcd {
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_pwr: wifi-pwr {
+ rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--
2.6.3
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[PATCH 1/3] ARM: dts: rockchip: correct the name of REG8 for rk3288-evb-act8846
According to the schematic, the name of REG8 should be vcc_tp, rather
than vcca_tp.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 43949a6..53d8b08 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -152,7 +152,7 @@
regulator-always-on;
};
- vcca_tp: REG8 {
+ vcc_tp: REG8 {
regulator-name = "VCCA_TP";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
--
2.6.3
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[PATCH v5 06/11] Documentation: dt-bindings: Add bindings for DW MIPI DSI
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4:
- remove the cfg clk
- remove gpr property from example, since it is noused now.
- add the description about ports
Changes in v3:
- move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge
Changes in v2: None
.../bindings/display/bridge/dw_mipi_dsi.txt| 74 ++
1 file changed, 74 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..2e1d197
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,74 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref) and APB clock(pclk), as described in [1].
+ - port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+*
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi-rockchip.txt
+
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+example:
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.3
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[PATCH v5 11/11] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v5:
- add a blank line befor lcd_en
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..2014992 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,20 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +261,10 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.3
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[PATCH v5 09/11] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2: None
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..acd9ec9
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.3
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[PATCH v5 10/11] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v5:
- modify the clk name to SCLK_MIPIDSI_24M
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6a79c9c..c48891e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -798,6 +798,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -831,6 +835,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -871,6 +879,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
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[PATCH v5 01/11] clk: rockchip: add id for mipidsi sclk on rk3288
Adds a new id for the sclk supplying the mipidsi on rk3288 socs. Signed-off-by: Chris Zhong --- Changes in v5: - change the mipidsi clk to SCLK_MIPIDSI_24M Changes in v4: None Changes in v3: None Changes in v2: - add the mipi clk id in a single patch include/dt-bindings/clock/rk3288-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aac..14c759c 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,6 +86,7 @@ #define SCLK_USBPHY480M_SRC122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_MIPIDSI_24M 125 #define SCLK_MAC 151 #define SCLK_MACREF_OUT152 -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/11] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v5: - change the mipidsi clk to SCLK_MIPIDSI_24M - modify the mipidsi clk name to SCLK_MIPIDSI_24M Adviced by Thierry - use hyphens instead of underscore - use encoder in drm_bridge - reformatting the dptdin table - use readx_poll_timeout to check register - use msleep to wait - add a comment to explain how to program phy - change the program code to symbolic names - check this for validity of find_panel and clk_prepare_enable - eliminate the configuration clock - some optimization for coding style - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup - remove the cfg clk - remove gpr property from example, since it is noused now. - add the description about ports - eliminate some warnning Changes in v3: - move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Changes in v2: - add the mipi clk id in a single patch Chris Zhong (9): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm: bridge: allow some funcs to be optional drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for DW MIPI DSI .../bindings/display/bridge/dw_mipi_dsi.txt| 74 ++ .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw-mipi-dsi.c | 1084 drivers/gpu/drm/drm_bridge.c |6 +- drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/bridge/dw_mipi_dsi.h | 28 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 16 files changed, 1599 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw-mipi-dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
Changes in v4:
remove gpr property from example, since it is noused now.
add the description about ports
Changes in v3:
move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge
Changes in v2: None
.../bindings/display/bridge/dw_mipi_dsi.txt| 80 ++
1 file changed, 80 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..8572ab3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,80 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+ - port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+*
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi-rockchip.txt
+
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.3
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[PATCH v4 01/13] clk: rockchip: add id for mipidsi sclk on rk3288
Adds a new id for the sclk supplying the mipidsi on rk3288 socs. Signed-off-by: Chris Zhong --- Changes in v4: None Changes in v3: None Changes in v2: add the mipi clk id in a single patch include/dt-bindings/clock/rk3288-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aac..b07cdd3 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,6 +86,7 @@ #define SCLK_USBPHY480M_SRC122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_MIPI_24M 125 #define SCLK_MAC 151 #define SCLK_MACREF_OUT152 -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 08/13] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3:
move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2: None
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..acd9ec9
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.3
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[PATCH v4 12/13] drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v4: None Changes in v3: move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: As Thierry.Reding comment, add a documentation for this panel. .../devicetree/bindings/display/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 10/13] of: add vendor prefix for boe
Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 55df1d4..0f88d6f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -33,6 +33,7 @@ auo AU Optronics Corporation avago Avago Technologies avic Shanghai AVIC Optoelectronics Co., Ltd. axis Axis Communications AB +boeBOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. brcm Broadcom Corporation -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 09/13] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6a79c9c..a5c5670 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -798,6 +798,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -831,6 +835,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -871,6 +879,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
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[PATCH v4 13/13] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..d04878f 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,21 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +262,9 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.3
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[PATCH v4 0/13] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v4: use clk_round_rate to check the clock rate in vop_crtc_mode_fixup remove gpr property from example, since it is noused now. add the description about ports eliminate some warnning Alphabetically arranged the name Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: add the mipi clk id in a single patch As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (11): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes of: add vendor prefix for boe drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../bindings/display/bridge/dw_mipi_dsi.txt| 80 ++ .../bindings/display/panel/boe,tv080wum-nl0.txt|7 + .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++ .../devicetree/bindings/vendor-prefixes.txt|1 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1056 drivers/gpu/drm/panel/panel-simple.c | 34 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 18 files changed, 1615 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/12] Add mipi dsi support for rk3288
Hi Emil On 11/19/2015 10:41 PM, Emil Velikov wrote: On 19 November 2015 at 03:35, Chris Zhong wrote: The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: add the mipi clk id in a single patch As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (10): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Did you actually rewrite the patch from Liu Ying ? I modify the dw_mipi_dsi.c based on the patch from Liu Ying. Out of curiosity what was the obstacle of this work getting merged ? There are different version dw controller, and it is too hard to merge them, since most registers are different. drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding As the DT people will tell you - there is no BOE vendor in bindings/vendor-prefixes.txt. Yes, I have post a verdor patch in v2 series, <https://patchwork.kernel.org/patch/7530791/> Maybe I should add it back to series with Acked-by: Rob Herring ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver >From the above 12 patches only ~6 reached this mailing list is that intentional ? Previously I've seen people CC dri-devel for their panel/bridge DT patches. I use the patman to post the series, forgot to add you and Thierry to the to-list. I will fix in next version series. Thanks for your reply. Regards, Emil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 12/12] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..d04878f 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,21 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +262,9 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.3
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[PATCH v3 09/12] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6a79c9c..a5c5670 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -798,6 +798,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -831,6 +835,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -871,6 +879,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
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[PATCH v3 11/12] drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong --- Changes in v3: move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: As Thierry.Reding comment, add a documentation for this panel. .../devicetree/bindings/display/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 08/12] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
---
Changes in v3:
move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2: None
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..acd9ec9
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.3
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[PATCH v3 05/12] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
Changes in v3:
move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge
Changes in v2: None
.../bindings/display/bridge/dw_mipi_dsi.txt| 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..0e5c140
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.3
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[PATCH v3 00/12] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: add the mipi clk id in a single patch As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (10): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../bindings/display/bridge/dw_mipi_dsi.txt| 76 ++ .../bindings/display/panel/boe,tv080wum-nl0.txt|7 + .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 17 files changed, 1609 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 01/12] clk: rockchip: add id for mipidsi sclk on rk3288
Adds a new id for the sclk supplying the mipidsi on rk3288 socs. Signed-off-by: Chris Zhong --- Changes in v3: None Changes in v2: add the mipi clk id in a single patch include/dt-bindings/clock/rk3288-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aac..b07cdd3 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,6 +86,7 @@ #define SCLK_USBPHY480M_SRC122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_MIPI_24M 125 #define SCLK_MAC 151 #define SCLK_MACREF_OUT152 -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding
Hi Rob On 11/02/2015 11:06 PM, Rob Herring wrote: On Sat, Oct 31, 2015 at 7:56 AM, Chris Zhong wrote: Your subject should be more specific with the panel name. I'll write more specific in subject next version. This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong --- Changes in v2: As Thierry.Reding comment, add a documentation for this panel. Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt Please move to bindings/display/panel/ Okay. diff --git a/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 01/13] clk: rockchip: add id for mipidsi sclk on rk3288
Adds a new id for the sclk supplying the mipidsi on rk3288 socs. Signed-off-by: Chris Zhong --- Changes in v2: add the mipi clk id in a single patch include/dt-bindings/clock/rk3288-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aac..b07cdd3 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,6 +86,7 @@ #define SCLK_USBPHY480M_SRC122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_MIPI_24M 125 #define SCLK_MAC 151 #define SCLK_MACREF_OUT152 -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 10/13] of: add vendor prefix for boe
Signed-off-by: Chris Zhong --- Changes in v2: add vendor prefix for boe Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 8fb0590..404b798 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -33,6 +33,7 @@ auo AU Optronics Corporation avago Avago Technologies avic Shanghai AVIC Optoelectronics Co., Ltd. axis Axis Communications AB +boeBOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. brcm Broadcom Corporation -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 13/13] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..d04878f 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,21 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +262,9 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.2
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[PATCH v2 09/13] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6a79c9c..a5c5670 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -798,6 +798,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -831,6 +835,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -871,6 +879,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.2
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[PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong --- Changes in v2: As Thierry.Reding comment, add a documentation for this panel. Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
Changes in v2: None
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..bb87466
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.2
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[PATCH v2 08/13] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
---
Changes in v2: None
.../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
diff --git a/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..4dea804
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.2
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[PATCH v2 00/13] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v2: add the mipi clk id in a single patch add vendor prefix for boe As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (11): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes of: add vendor prefix for boe drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../devicetree/bindings/panel/boe,tv080wum-nl0.txt |7 + .../devicetree/bindings/vendor-prefixes.txt|1 + .../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig |9 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 18 files changed, 1608 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/10] clk: rockchip: Add sclk_mipidsi_24m for mipi dsi
On 10/17/2015 05:39 AM, Stephen Boyd wrote:
On 10/10, Chris Zhong wrote:
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
Acked-by: Stephen Boyd
drivers/clk/rockchip/clk-rk3288.c | 2 +-
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 9040878..c7d7ebf 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
__initdata = {
GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0,
RK3288_CLKGATE_CON(13), 11, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0,
RK3288_CLKGATE_CON(5), 9, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
RK3288_CLKGATE_CON(5), 10, GFLAGS),
- GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15,
GFLAGS),
+ GATE(SCLK_MIPI_24M, "sclk_mipidsi_24m", "xin24m", 0,
RK3288_CLKGATE_CON(5), 15, GFLAGS),
It would have been better to make #defines for all these clocks
even if they weren't going to be used here. Then we could have
applied this patch directly to clk tree without having a clk tree
to arm-soc dependency.
Thanks for your great suggestion, I'll defines all clocks at next
version patch serial
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[PATCH 01/10] clk: rockchip: Add sclk_mipidsi_24m for mipi dsi
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 9040878..c7d7ebf 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
__initdata = {
GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0,
RK3288_CLKGATE_CON(13), 11, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0,
RK3288_CLKGATE_CON(5), 9, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
RK3288_CLKGATE_CON(5), 10, GFLAGS),
- GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15,
GFLAGS),
+ GATE(SCLK_MIPI_24M, "sclk_mipidsi_24m", "xin24m", 0,
RK3288_CLKGATE_CON(5), 15, GFLAGS),
/* sclk_gpu gates */
GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0,
GFLAGS),
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index c719aac..b07cdd3 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -86,6 +86,7 @@
#define SCLK_USBPHY480M_SRC122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
+#define SCLK_MIPI_24M 125
#define SCLK_MAC 151
#define SCLK_MACREF_OUT152
--
2.6.1
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[PATCH 10/10] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..d04878f 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,21 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +262,9 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
buttons {
--
2.6.1
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[PATCH 08/10] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 1a7cb08..3266d11 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -783,6 +783,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
};
};
@@ -816,6 +820,10 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
+ vopl_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
};
};
@@ -856,6 +864,37 @@
};
};
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.1
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[PATCH 04/10] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..bb87466
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+<&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.1
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[PATCH 07/10] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
---
.../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
diff --git a/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..4dea804
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi@ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <&grf>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en>;
+ backlight = <&backlight>;
+ status = "okay";
+ };
+ };
--
2.6.1
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[PATCH 00/10] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from ying@freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Chris Zhong (8): clk: rockchip: Add sclk_mipidsi_24m for mipi dsi drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes drm/panel: simple: Add support for BOE TV080WUM-NL0 ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 16 files changed, 1601 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/2] mfd: dt-bindings: add the description about dvs gpio for rk808
add the description about dvs1, dvs2, and add the example. Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson --- Changes in v4: - Remove the description about dvs-ok Changes in v3: - Modify the syntax error Changes in v2: - increase description about dvs pins Documentation/devicetree/bindings/mfd/rk808.txt | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 9e6e259..4ca6aab 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -24,6 +24,10 @@ Optional properties: - vcc10-supply: The input supply for LDO_REG6 - vcc11-supply: The input supply for LDO_REG8 - vcc12-supply: The input supply for SWITCH_REG2 +- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers + for 2 host gpio's used for dvs. The format of the gpio specifier depends in + the gpio controller. If DVS GPIOs aren't present, voltage changes will happen + very quickly with no slow ramp time. Regulators: All the regulators of RK808 to be instantiated shall be listed in a child node named 'regulators'. Each regulator is represented @@ -55,7 +59,9 @@ Example: interrupt-parent = <&gpio0>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; reg = <0x1b>; rockchip,system-power-controller; wakeup-source; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/2] fixed the overshoot when adjust voltage
Hi Mark Sorry for the belated update. As you said, constantly checking dvsok pin and waiting it to active is not a good idea, so I remove the dvsok pin in latest patch. This patchset have been tested on ChromeBook, the overshoot has disappeared on the boards with dvs pin. And for the other boards without dvs pin, the overshoot alse significantly reduced to a negligible level. Changes in v4: - Remove the description about dvs-ok - remove dvsok pin - add support gradual adjustment Changes in v3: - Modify the syntax error Changes in v2: - increase description about dvs pins - modify the multiline commenting Chris Zhong (2): mfd: dt-bindings: add the description about dvs gpio for rk808 regulator: rk808: fixed the overshoot when adjust voltage Documentation/devicetree/bindings/mfd/rk808.txt | 8 +- drivers/regulator/rk808-regulator.c | 219 ++-- 2 files changed, 214 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: cros-ec-keyboard: Add support for some Japanese keys
On 05/06/2015 02:10 AM, Doug Anderson wrote: Chris, On Mon, May 4, 2015 at 7:07 PM, Chris Zhong wrote: Add support for 4 Japanese keys Signed-off-by: Chris Zhong --- arch/arm/boot/dts/cros-ec-keyboard.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi index 9c7fb0a..4e42f30c 100644 --- a/arch/arm/boot/dts/cros-ec-keyboard.dtsi +++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi @@ -22,6 +22,7 @@ MATRIX_KEY(0x00, 0x02, KEY_F1) MATRIX_KEY(0x00, 0x03, KEY_B) MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x05, KEY_RO) MATRIX_KEY(0x00, 0x06, KEY_N) MATRIX_KEY(0x00, 0x08, KEY_EQUAL) MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) @@ -34,6 +35,7 @@ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) MATRIX_KEY(0x01, 0x09, KEY_F9) MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) MATRIX_KEY(0x02, 0x01, KEY_TAB) @@ -45,6 +47,7 @@ MATRIX_KEY(0x02, 0x07, KEY_102ND) MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) MATRIX_KEY(0x02, 0x09, KEY_F8) + MATRIX_KEY(0x02, 0x0a, KEY_YEN) MATRIX_KEY(0x03, 0x01, KEY_GRAVE) MATRIX_KEY(0x03, 0x02, KEY_F2) @@ -53,6 +56,7 @@ MATRIX_KEY(0x03, 0x06, KEY_6) MATRIX_KEY(0x03, 0x08, KEY_MINUS) MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) MATRIX_KEY(0x04, 0x01, KEY_A) Since there's no clear architecture here, I'd bet Olof would be the one to take this. I added him to this email, but he might request that you resend the patch with him in the "To:" line. Other than that: Reviewed-by: Doug Anderson Thank you, I'll resend the patch with Olof. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] Support disable the wakeup event of gpio-charger
If you needn't the wakeup event of gpio-charger, this patch can help. Please set "gpio-charger,disable-wakeup" in gpio-charger node. Chris Zhong (2): dt-bindings: add disable-wakeup property for gpio-charger power: gpio-charger: support disable the wakeup event Documentation/devicetree/bindings/power_supply/gpio-charger.txt | 2 ++ drivers/power/gpio-charger.c| 5 - include/linux/power/gpio-charger.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] dt-bindings: add disable-wakeup property for gpio-charger
add disable-wakeup for gpio-charger, if you set this property, system
will not wakeup by gpio-charger.
Signed-off-by: Chris Zhong
---
Documentation/devicetree/bindings/power_supply/gpio-charger.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/power_supply/gpio-charger.txt
b/Documentation/devicetree/bindings/power_supply/gpio-charger.txt
index adbb5dc..a46e9bc 100644
--- a/Documentation/devicetree/bindings/power_supply/gpio-charger.txt
+++ b/Documentation/devicetree/bindings/power_supply/gpio-charger.txt
@@ -4,6 +4,7 @@ Required properties :
- compatible : "gpio-charger"
- gpios : GPIO indicating the charger presence.
See GPIO binding in bindings/gpio/gpio.txt .
+ - gpio-charger,disable-wakeup : Boolean, charger does not wake-up the system.
- charger-type : power supply type, one of
unknown
battery
@@ -20,6 +21,7 @@ Example:
compatible = "gpio-charger";
charger-type = "usb-sdp";
gpios = <&gpf0 2 0 0 0>;
+ gpio-charger,disable-wakeup;
}
battery {
--
1.9.1
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[PATCH v3 1/2] mfd: dt-bindings: add the description about dvs gpio for rk808
add the description about dvs1, dvs2, dvsok, and add the example. Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson --- Changes in v3: - Modify the syntax error Changes in v2: - increase description about dvs pins Documentation/devicetree/bindings/mfd/rk808.txt | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 9e6e259..9cc2941 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -24,6 +24,14 @@ Optional properties: - vcc10-supply: The input supply for LDO_REG6 - vcc11-supply: The input supply for LDO_REG8 - vcc12-supply: The input supply for SWITCH_REG2 +- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers + for 2 host gpio's used for dvs. The format of the gpio specifier depends in + the gpio controller. If DVS GPIOs aren't present, voltage changes will happen + very quickly with no slow ramp time. +- dvsok-gpios: if we use dvs gpio to control buck1/2, this gpio will be pull + high, once RK808 completed the adjustment of voltage. If the DVSOK isn't + present, we'll just delay based on whatever is specified in the regulator + constraints. Regulators: All the regulators of RK808 to be instantiated shall be listed in a child node named 'regulators'. Each regulator is represented @@ -55,7 +63,10 @@ Example: interrupt-parent = <&gpio0>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int &dvs_ok &dvs_1 &dvs_2>; + dvsok-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; reg = <0x1b>; rockchip,system-power-controller; wakeup-source; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/2] add the dvs support for rk808
rk808 has a dvs function, there are 3 pins for dvs, dvs1 & dvs2 & dvsok. Normally, the voltage of DCDC1/DCDC2 are controlled by BUCKn_ON_VSEL, when we pull dvs1/dvs2 pin to active, they would be controlled by BUCKn_DVS_VSEL. And the dvsok pin is used to indicate whether regulating has been completed. When dvs1/dvs2 pin change, dvsok would be pull down, and it would be pull up once the regulating is complete. Changes in v3: - Modify the syntax error Changes in v2: - increase description about dvs pins - modify the multiline commenting Chris Zhong (2): mfd: dt-bindings: add the description about dvs gpio for rk808 regulator: rk808: add dvs support Documentation/devicetree/bindings/mfd/rk808.txt | 13 +- drivers/regulator/rk808-regulator.c | 192 ++-- 2 files changed, 192 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
On 12/11/2014 03:06 PM, Joe Perches wrote: On Thu, 2014-12-11 at 14:52 +0800, Yunzhi Li wrote: On 2014/12/11 14:37, Joe Perches wrote: On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: [] So If I have to write something on bit 0, I have to set bit 16. If I have to write something on bit 1, I have to set bit 17. If I have to write something on bit 2, I have to set bit 18. and so on. To me it'd look better to use another << rather than a plus Like (BIT(13) << 16)? It looks strange, or could I just use ((1 << 13) << 16) to describe this bit ? Up to you. To me, the BIT(x+y) seems odd. I think BIT(29) is better, since you have described in comments. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] mfd: dt-bindings: add the description about dvs gpio for rk808
add the description about dvs1, dvs2, dvsok, and add the example. Signed-off-by: Chris Zhong --- Changes in v2: - increase description about dvs pins Documentation/devicetree/bindings/mfd/rk808.txt | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 9e6e259..923cdca 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -24,6 +24,14 @@ Optional properties: - vcc10-supply: The input supply for LDO_REG6 - vcc11-supply: The input supply for LDO_REG8 - vcc12-supply: The input supply for SWITCH_REG2 +- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers + for 2 host gpio's used for dvs. The format of the gpio specifier depends in + the gpio controller. If DVS GPIOs aren't present, voltage changes will happen + without being very quickly with no slow ramp time. +- dvsok-gpios: if we use dvs gpio to control buck1/2, this gpio will be pull + high, once RK808 completed the adjustment of voltage. If the DVSOK isn't + present, we'll just delay based on whatever is specified in the regulator + constraints. Regulators: All the regulators of RK808 to be instantiated shall be listed in a child node named 'regulators'. Each regulator is represented @@ -55,7 +63,10 @@ Example: interrupt-parent = <&gpio0>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int &dvs_ok &dvs_1 &dvs_2>; + dvsok-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; reg = <0x1b>; rockchip,system-power-controller; wakeup-source; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/2] add the dvs support for rk808
rk808 has a dvs function, there are 3 pins for dvs, dvs1 & dvs2 & dvsok. Normally, the voltage of DCDC1/DCDC2 are controlled by BUCKn_ON_VSEL, when we pull dvs1/dvs2 pin to active, they would be controlled by BUCKn_DVS_VSEL. And the dvsok pin is used to indicate whether regulating has been completed. When dvs1/dvs2 pin change, dvsok would be pull down, and it would be pull up once the regulating is complete. Changes in v2: - increase description about dvs pins - modify the multiline commenting Chris Zhong (2): mfd: dt-bindings: add the description about dvs gpio for rk808 regulator: rk808: add dvs support Documentation/devicetree/bindings/mfd/rk808.txt | 13 +- drivers/regulator/rk808-regulator.c | 192 ++-- 2 files changed, 192 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] mfd: dt-bindings: add the description about dvs gpio for rk808
add the description about dvs1, dvs2, dvsok, and add the example. Signed-off-by: Chris Zhong --- Documentation/devicetree/bindings/mfd/rk808.txt | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 9e6e259..d40131b 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -24,6 +24,11 @@ Optional properties: - vcc10-supply: The input supply for LDO_REG6 - vcc11-supply: The input supply for LDO_REG8 - vcc12-supply: The input supply for SWITCH_REG2 +- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers + for 2 host gpio's used for dvs. The format of the gpio specifier depends in + the gpio controller. +- dvsok-gpios: if we use dvs gpio to control buck1/2, this gpio will be pull + high, once RK808 completed the adjustment of voltage. Regulators: All the regulators of RK808 to be instantiated shall be listed in a child node named 'regulators'. Each regulator is represented @@ -55,7 +60,10 @@ Example: interrupt-parent = <&gpio0>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int &dvs_ok &dvs_1 &dvs_2>; + dvsok-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; reg = <0x1b>; rockchip,system-power-controller; wakeup-source; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] add the dvs support for rk808
rk808 has a dvs function, there are 3 pins for dvs, dvs1 & dvs2 & dvsok. Normally, the voltage of DCDC1/DCDC2 are controlled by BUCKn_ON_VSEL, when we pull dvs1/dvs2 pin to active, they would be controlled by BUCKn_DVS_VSEL. And the dvsok pin is used to indicate whether regulating has been completed. When dvs1/dvs2 pin change, dvsok would be pull down, and it would be pull up once the regulating is complete. Chris Zhong (2): regulator: rk808: add dvs support mfd: dt-bindings: add the description about dvs gpio for rk808 Documentation/devicetree/bindings/mfd/rk808.txt | 10 +- drivers/regulator/rk808-regulator.c | 192 ++-- 2 files changed, 189 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 0/4] This suspend patch is only support cut off the power of cpu and some external
On 12/02/2014 09:26 AM, Kevin Hilman wrote:
Doug Anderson writes:
Hi,
On Mon, Dec 1, 2014 at 2:08 PM, Doug Anderson wrote:
Hi,
On Mon, Dec 1, 2014 at 11:51 AM, Kevin Hilman wrote:
Chris Zhong writes:
devices, since we still lack power_domain driver, so the other power rail
of rk3288 need keep power on.
I have tested it on rk3288-evb board, atop next-20141112. goto suspend by type
"echo mem > /sys/power/state", vdd_cpu is about 0mv by measuring, so it can be
determined in sleep mode, then press power button to wakeup it.
I tested this on top of today's linux-next (next-20141201) and it
suspends, but doesn't wake up from any of the button presses. What
wakeup sources are configured for the rk3288-evb-rk808?
Just to close the loop (I talked with Kevin over IM about this, too):
I have a huge description of how I tested this as part of my patch at
<https://patchwork.kernel.org/patch/5414941/>. Chris: I think Kevin
has asked you several times to include information like this in your
cover letter. Please, please, please can you try to remember to do
this?
Talked to Chris offline. He said that in his tests the other patches
weren't needed, so he didn't list any other patches. Things just
worked for him. ...so I guess he did post the instructions that
worked for him. Sorry for the complaint. Possibly things are
different on "next-20141112" and that's where Chris said he tested.
This series doesn't apply cleanly to next-20141112. Manually applying
(with fuzz), it boots but I have the same results: it suspends, but none
of the buttons wake it up.
Kevin
Hi, Kevin
I have test these patches on evb board base on next-20141128 with a
defconfig[0], and with u-boot[1].
As Doug said, we need below 3 patches for resume.
1.https://patchwork.kernel.org/patch/5051881/ - clocksource:
arch_timer: Allow the device tree to specify uninitialized timer
registers
2.https://patchwork.kernel.org/patch/5363671/ - clocksource:
arch_timer: Fix code to use physical timers when requested
3.https://patchwork.kernel.org/patch/5382141/ - ARM: dts: rk3288: add
arm,cpu-registers-not-fw-configured
And it will auto wakeup, as Heiko said in v8. But I have never notice
before, since the u-boot never enable edp,
and I use the coreboot with edp display.
Actually it is a bug in rk3288, the rk3288 have not 27Mhz clock source,
but the edp initially set to this
non-existent clock. At this time, edp is working on a unknown state, and
it always bring a interrupt, this
interrupt avoid system enter suspend. So if we want to enter suspend
normally, the edp_24m_sel(bit 15) of
CRU_CLKSEL28_CON(0xff7600d0) must be set to 1.
[0]
https://github.com/mmind/linux-rockchip/blob/devel/workbench/arch/arm/configs/rk3288_defconfig
[1] https://githubremotes/origin/u-boot-rk3288
here is my local work around:
diff --git a/arch//cpu/armv7/rk32xx/clock-rk3288.c
b/arch/arm/cpu/armv7/rk32xx/clock-rk3288.c
index cfd0acd..3df0900 100755
--- a/arch/arm/cpu/armv7/rk32xx/clock-rk3288.c
+++ b/arch/arm/cpu/armv7/rk32xx/clock-rk3288.c
@@ -1233,7 +1233,6 @@ int rkclk_lcdc_clk_set(uint32 lcdc_id, uint32 dclk_hz)
}
}
-
/*
* rkplat set nandc clock div
* nandc_id: nandc id
@@ -1270,6 +1269,11 @@ int rkclk_set_nandc_div(uint32 nandc_id, uint32
pllsrc, uint32 freq)
return 0;
}
+void rkclk_init_edp_source(void)
+{
+ cru_writel(1<<15 | 1<<31, CRU_CLKSELS_CON(28));
+}
+
/*
* rkplat set sd clock src
* 0: codec pll; 1: general pll; 2: 24M
diff --git a/board/rockchip/rk32xx/rk32xx.c b/board/rockchip/rk32xx/rk32xx.c
index bfdcf0e..3e19f5d 100755
--- a/board/rockchip/rk32xx/rk32xx.c
+++ b/board/rockchip/rk32xx/rk32xx.c
@@ -114,7 +114,7 @@ void rk_backlight_ctrl(int brightness)
void rk_fb_init(unsigned int onoff)
{
-
+ rkclk_init_edp_source();
#ifdef CONFIG_OF_LIBFDT
if (lcd_node == 0) rk_lcd_parse_dt(gd->fdt_blob);
--
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Re: [PATCH v10 0/4] This suspend patch is only support cut off the power of cpu and some external
On 12/02/2014 06:08 AM, Doug Anderson wrote: Hi, On Mon, Dec 1, 2014 at 11:51 AM, Kevin Hilman wrote: Chris Zhong writes: devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep power on. I have tested it on rk3288-evb board, atop next-20141112. goto suspend by type "echo mem > /sys/power/state", vdd_cpu is about 0mv by measuring, so it can be determined in sleep mode, then press power button to wakeup it. I tested this on top of today's linux-next (next-20141201) and it suspends, but doesn't wake up from any of the button presses. What wakeup sources are configured for the rk3288-evb-rk808? Just to close the loop (I talked with Kevin over IM about this, too): I have a huge description of how I tested this as part of my patch at <https://patchwork.kernel.org/patch/5414941/>. Chris: I think Kevin has asked you several times to include information like this in your cover letter. Please, please, please can you try to remember to do this? I wrote it to v8 cover letter, but I found that they are all landed on linux-next now, so I remove they from v9, v10. Based on: [v5,1/6] ARM: rockchip: convert to regmap and use pmu syscon if available https://patchwork.kernel.org/patch/5086341/ [v5,2/6] ARM: rockchip: add option to access the pmu via a phandle in smp_operations https://patchwork.kernel.org/patch/5086441/ [v5,3/6] ARM: dts: rockchip: add pmu references to cpus nodes https://patchwork.kernel.org/patch/5086351/ [v5,4/6] ARM: rockchip: add basic smp support for rk3288 https://patchwork.kernel.org/patch/5086371/ [v5,5/6] ARM: dts: rockchip: add intmem node for rk3288 smp support https://patchwork.kernel.org/patch/5086361/ [v5,6/6] ARM: dts: rockchip: add reset for CPU nodes https://patchwork.kernel.org/patch/5086381/ [v3] usb: dwc2: add bus suspend/resume for dwc2 https://patchwork.kernel.org/patch/5266281/ But I missed this 3 patches, since I thought they just for fix timer disorder when I use coreboot. Doug said they are related to SMP and related to suspend/resume. 1. https://patchwork.kernel.org/patch/5051881/ - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers 2. https://patchwork.kernel.org/patch/5363671/ - clocksource: arch_timer: Fix code to use physical timers when requested 3. https://patchwork.kernel.org/patch/5382141/ - ARM: dts: rk3288: add arm,cpu-registers-not-fw-configured I'm not sure whether we need these 2 patches. 4. Revert (b77d439 ARM: dts: rockchip: temporarily disable smp on rk3288) 5. https://patchwork.kernel.org/patch/5325111/ - usb: dwc2: resume root hub when device detect with suspend state For those that don't want to click on my link, I'll include the relevant bits here: --- Total patches atop that version of Linux were: 1. https://patchwork.kernel.org/patch/5051881/ - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers 2. https://patchwork.kernel.org/patch/5363671/ - clocksource: arch_timer: Fix code to use physical timers when requested 3. https://patchwork.kernel.org/patch/5382141/ - ARM: dts: rk3288: add arm,cpu-registers-not-fw-configured 4. Revert (b77d439 ARM: dts: rockchip: temporarily disable smp on rk3288) 5. https://patchwork.kernel.org/patch/5325111/ - usb: dwc2: resume root hub when device detect with suspend state 6. https://patchwork.kernel.org/patch/5410611/ - ARM: rockchip: add suspend and resume for RK3288 7. https://patchwork.kernel.org/patch/5410621/ - ARM: rockchip: Add pmu-sram binding 8. https://patchwork.kernel.org/patch/5410631/ - ARM: dts: add RK3288 suspend support 9. https://patchwork.kernel.org/patch/5410641/ - ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808 It looks like my pinctrl patches might be dropped due to cross dependency problems, so tomorrow's linux-next will probably also need (https://patchwork.kernel.org/patch/5344551/ - pinctrl: rockchip: Handle wakeup pins). I've also got a local hack to the Rockchip "pm.c" to replace the usage of "PMU_ARMINT_WAKEUP_EN" with 0x0e. There seems to be some sort of ARM Interrupt waking us up all the time right when we go to sleep and the above will hack it so that only GPIOs + SDMMC Card Detect can wake us up. Someone should track down what's going on there, but for now I've used the hack to prove that the basic code actually works. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 3/4] ARM: dts: add RK3288 suspend support
On 12/01/2014 01:26 PM, Doug Anderson wrote: Chris, On Mon, Nov 24, 2014 at 11:32 PM, Chris Zhong wrote: add pmu sram node for suspend, add global_pwroff pinctrl. The pmu sram is used to store the resume code. global_pwroff is held low level at work, it would be pull to high when entering suspend. reference this in the board DTS file since some boards need it. Signed-off-by: Tony Xie Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson Tested-by: Doug Anderson --- Changes in v9: None This is untrue. v8 had more stuff than v9. See: https://patchwork.kernel.org/patch/5311621/ vs. https://patchwork.kernel.org/patch/5372911/ I prefer v8. Ah, I missed the ddr pinctrl in V9, Thank you. I have modified it, and post the V10. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 0/4] This suspend patch is only support cut off the power of cpu and some external
devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep power on. I have tested it on rk3288-evb board, atop next-20141112. goto suspend by type "echo mem > /sys/power/state", vdd_cpu is about 0mv by measuring, so it can be determined in sleep mode, then press power button to wakeup it. Changes in v10: - remove regulator-suspend-mem-enabled and regulator-suspend-mem-microvolt - enable the lcd, codec, sdmmc power during suspend Changes in v9: - fold Doug's patches - modify some print log - update the subject and description Changes in v8: - use enum for define sleep mode - move rk3288_config_bootdata to the front of sram memcpy - add ddr pinctrl for suspend - keep all except cpu&tp power rail on during suspend - add regulator-on-in-suspend before set suspend voltage - add a reference of ddrio_pwroff and ddr0_retention Changes in v7: - get rid all of unused code - add regulator-state-mem sub node for suspend Changes in v6: - get rid of the save/restore of SRAM - doing the copy of resume code once at init time - remove ROCKCHIP_ARM_OFF_LOGIC_DEEP from rk3288_fill_in_bootram - add of_platform_populate in rockchip_dt_init - change pmu_intmem@ff72 to sram@ff72 - change pmu_intmem@ff72 to sram@ff72 Changes in v5: - use rk3288_bootram_sz for memcpy size - fixed error of sram save and restore - change the size of sram in example - change size to 4k Changes in v4: - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris Zhong (4): ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808 .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16 ++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 53 - arch/arm/boot/dts/rk3288.dtsi | 23 ++ arch/arm/mach-rockchip/Makefile| 1 + arch/arm/mach-rockchip/pm.c| 260 + arch/arm/mach-rockchip/pm.h| 99 arch/arm/mach-rockchip/rockchip.c | 2 + arch/arm/mach-rockchip/sleep.S | 73 ++ 8 files changed, 526 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 3/4] ARM: dts: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v10: None
Changes in v9: None
Changes in v8:
- add ddr pinctrl for suspend
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change size to 4k
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 0f50d5d..eede3c6 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -480,6 +480,11 @@
};
};
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -703,6 +708,24 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddrio_pwroff: ddrio-pwroff {
+ rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddr0_retention: ddr0-retention {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ ddr1_retention: ddr1-retention {
+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.9.1
--
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[PATCH v10 2/4] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change the size of sram in example
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..6b42fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,16 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader). This is a common use of the "pmu-sram" because it keeps power
+even in low power states in the system.
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
--
1.9.1
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[PATCH v10 4/4] ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808
Add suspend-voltages and necessary pin-states for suspend on
rk3288-evb-rk808 boards. global_pwroff would be pulled high when
RK3288 entering suspend, this pin is a sleep signal for RK808, so
RK808 could goto sleep mode, and some regulators would be disable.
Signed-off-by: Chris Zhong
---
Changes in v10:
- remove regulator-suspend-mem-enabled and regulator-suspend-mem-microvolt
- enable the lcd, codec, sdmmc power during suspend
Changes in v9:
- update the subject and description
Changes in v8:
- keep all except cpu&tp power rail on during suspend
- add regulator-on-in-suspend before set suspend voltage
- add a reference of ddrio_pwroff and ddr0_retention
Changes in v7:
- add regulator-state-mem sub node for suspend
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb-rk808.dts | 53 +-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..d453ddd 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -31,7 +31,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -50,6 +50,9 @@
regulator-min-microvolt = <75>;
regulator-max-microvolt = <135>;
regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_gpu: DCDC_REG2 {
@@ -58,12 +61,19 @@
regulator-min-microvolt = <85>;
regulator-max-microvolt = <125>;
regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc_io: DCDC_REG4 {
@@ -72,6 +82,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vccio_pmu: LDO_REG1 {
@@ -80,6 +94,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vcc_tp: LDO_REG2 {
@@ -88,6 +106,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_10: LDO_REG3 {
@@ -96,6 +117,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+
Re: [PATCH v9 4/4] ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808
On 11/27/2014 06:52 AM, Doug Anderson wrote:
Chris,
On Mon, Nov 24, 2014 at 11:32 PM, Chris Zhong wrote:
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-suspend-mem-enabled;
The "regulator-suspend-mem-enabled" is not an upstream property and
isn't doing anything. It should be removed.
Possibly this is something Heiko could do when applying (depends on
what he wants) if no other spins are required.
vcc_18: LDO_REG7 {
@@ -128,6 +163,11 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-name = "vcc_18";
+ regulator-suspend-mem-microvolt = <180>;
Another non-upstream property: regulator-suspend-mem-microvolt
Ah, missed these two. I should remove all the regulator-suspend-mem-*,
they are from Gerrit.
Thank you.
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[PATCH 2/2] ARM: dts: rk3288: change the max clk of cpu to 1.8Ghz
The maximum cpu frequency of rk3288 can up to 1.8Ghz, and it need to set the vdd_cpu to 1.4v correspondingly. Signed-off-by: Chris Zhong --- arch/arm/boot/dts/rk3288.dtsi | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 0f50d5d..4f77a05 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -56,8 +56,10 @@ resets = <&cru SRST_CORE0>; operating-points = < /* KHzuV */ - 1608000 135 - 1512000 130 + 180 140 + 1704000 135 + 1608000 130 + 1512000 125 1416000 120 120 110 1008000 105 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] Increase the maximum cpu frequency of rk3288
The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set to 1.4v. I've tested these patches on rk3288 evb board. Chris Zhong (2): ARM: dts: rockchip: change the max voltage of cpu to 1.4v ARM: dts: rk3288: change the max clk of cpu to 1.8Ghz arch/arm/boot/dts/rk3288-evb-rk808.dts | 2 +- arch/arm/boot/dts/rk3288.dtsi | 6 -- 2 files changed, 5 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: rockchip: change the max voltage of cpu to 1.4v
If the cpu frequencies up to 1.8Ghz, we need set the vdd_cpu to 1.4v. Signed-off-by: Chris Zhong --- arch/arm/boot/dts/rk3288-evb-rk808.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index d8c775e6..d4f74dd 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -48,7 +48,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <75>; - regulator-max-microvolt = <135>; + regulator-max-microvolt = <140>; regulator-name = "vdd_arm"; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 0/4] The 1st version of suspend for RK3288.
This suspend patch is only support cut off the power of cpu and some external devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep power on. I have tested it on rk3288-evb board, atop next-20141124. goto suspend by type "echo mem > /sys/power/state", vdd_cpu is about 0mv by measuring, so it can be determined in sleep mode, then press power button to wakeup it. Changes in v9: - fold Doug's patches - modify some print log - update the subject and description Changes in v8: - use enum for define sleep mode - move rk3288_config_bootdata to the front of sram memcpy - set vdd_gpu to 1.0v during suspend - add regulator-on-in-suspend before set suspend voltage Changes in v7: - get rid all of unused code - add regulator-state-mem sub node for suspend Changes in v6: - get rid of the save/restore of SRAM - doing the copy of resume code once at init time - remove ROCKCHIP_ARM_OFF_LOGIC_DEEP from rk3288_fill_in_bootram - add of_platform_populate in rockchip_dt_init - change pmu_intmem@ff72 to sram@ff72 - change pmu_intmem@ff72 to sram@ff72 Changes in v5: - use rk3288_bootram_sz for memcpy size - fixed error of sram save and restore - change the size of sram in example - change size to 4k Changes in v4: - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris Zhong (4): ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808 .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16 ++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 51 +++- arch/arm/boot/dts/rk3288.dtsi | 11 + arch/arm/mach-rockchip/Makefile| 1 + arch/arm/mach-rockchip/pm.c| 260 + arch/arm/mach-rockchip/pm.h| 99 arch/arm/mach-rockchip/rockchip.c | 2 + arch/arm/mach-rockchip/sleep.S | 73 ++ 8 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 3/4] ARM: dts: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change size to 4k
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index d83ca93..c11b44c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -481,6 +481,11 @@
};
};
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -704,6 +709,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.9.1
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[PATCH v9 2/4] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change the size of sram in example
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..6b42fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,16 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader). This is a common use of the "pmu-sram" because it keeps power
+even in low power states in the system.
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
--
1.9.1
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[PATCH v9 4/4] ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808
Add suspend-voltages and necessary pin-states for suspend on
rk3288-evb-rk808 boards. global_pwroff would be pulled high when
RK3288 entering suspend, this pin is a sleep signal for RK808, so
RK808 could goto sleep mode, and some regulators would be disable.
Signed-off-by: Chris Zhong
---
Changes in v9:
- update the subject and description
Changes in v8:
- set vdd_gpu to 1.0v during suspend
- add regulator-on-in-suspend before set suspend voltage
Changes in v7:
- add regulator-state-mem sub node for suspend
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb-rk808.dts | 51 +-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..742bd89 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -31,7 +31,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -50,6 +50,9 @@
regulator-min-microvolt = <75>;
regulator-max-microvolt = <135>;
regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_gpu: DCDC_REG2 {
@@ -58,12 +61,20 @@
regulator-min-microvolt = <85>;
regulator-max-microvolt = <125>;
regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-suspend-mem-enabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc_io: DCDC_REG4 {
@@ -72,6 +83,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vccio_pmu: LDO_REG1 {
@@ -80,6 +95,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vcc_tp: LDO_REG2 {
@@ -88,6 +107,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_10: LDO_REG3 {
@@ -96,6 +118,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc1
[PATCH v8 3/4] ARM: dts: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
ddrio_pwroff is power switch of ddr_controller, if you want to cut off
power rail of ddr_controller during suspend, please reference it.
ddr0_retention/ddr1_retention are the retention mode switches, if you
want to use the retention mode during suspend, please reference them.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v8:
- add ddr pinctrl for suspend
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change size to 4k
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index df30437..60bccff 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -482,6 +482,11 @@
};
};
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -687,6 +692,24 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddrio_pwroff: ddrio-pwroff {
+ rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddr0_retention: ddr0-retention {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ ddr1_retention: ddr1-retention {
+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.9.1
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[PATCH v8 4/4] ARM: dts: add suspend voltage setting for RK808
global_pwroff would be pull to high when RK3288 entering suspend,
this pin is a sleep signal for RK808, so RK808 could goto sleep
mode, and some regulators would be disable.
Signed-off-by: Chris Zhong
---
Changes in v8:
- keep all except cpu&tp power rail on during suspend
- add regulator-on-in-suspend before set suspend voltage
- add a reference of ddrio_pwroff and ddr0_retention
Changes in v7:
- add regulator-state-mem sub node for suspend
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb-rk808.dts | 55 +-
arch/arm/boot/dts/rk3288-evb.dtsi | 12
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..e4a8884 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -31,7 +31,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -50,6 +50,9 @@
regulator-min-microvolt = <75>;
regulator-max-microvolt = <135>;
regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_gpu: DCDC_REG2 {
@@ -58,12 +61,20 @@
regulator-min-microvolt = <85>;
regulator-max-microvolt = <125>;
regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-suspend-mem-enabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc_io: DCDC_REG4 {
@@ -72,6 +83,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vccio_pmu: LDO_REG1 {
@@ -80,6 +95,10 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
};
vcc_tp: LDO_REG2 {
@@ -88,6 +107,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_10: LDO_REG3 {
@@ -96,6 +118,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc18_lcd: LDO
[PATCH v8 2/4] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change the size of sram in example
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..6b42fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,16 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader). This is a common use of the "pmu-sram" because it keeps power
+even in low power states in the system.
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
--
1.9.1
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[PATCH v8 0/4] This is the 1st version of suspend for RK3288.
This suspend patch is only support cut off the power of cpu and some external devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep power on. I have tested it on rk3288-evb board, atop next-20141112. goto suspend by type "echo mem > /sys/power/state", vdd_cpu is about 0mv by measuring, so it can be determined in sleep mode, then press power button to wakeup it. Based on: [v5,1/6] ARM: rockchip: convert to regmap and use pmu syscon if available https://patchwork.kernel.org/patch/5086341/ [v5,2/6] ARM: rockchip: add option to access the pmu via a phandle in smp_operations https://patchwork.kernel.org/patch/5086441/ [v5,3/6] ARM: dts: rockchip: add pmu references to cpus nodes https://patchwork.kernel.org/patch/5086351/ [v5,4/6] ARM: rockchip: add basic smp support for rk3288 https://patchwork.kernel.org/patch/5086371/ [v5,5/6] ARM: dts: rockchip: add intmem node for rk3288 smp support https://patchwork.kernel.org/patch/5086361/ [v5,6/6] ARM: dts: rockchip: add reset for CPU nodes https://patchwork.kernel.org/patch/5086381/ [v3] usb: dwc2: add bus suspend/resume for dwc2 https://patchwork.kernel.org/patch/5266281/ Changes in v8: - use enum for define sleep mode - move rk3288_config_bootdata to the front of sram memcpy - add ddr pinctrl for suspend - keep all except cpu&tp power rail on during suspend - add regulator-on-in-suspend before set suspend voltage - add a reference of ddrio_pwroff and ddr0_retention Changes in v7: - get rid all of unused code - add regulator-state-mem sub node for suspend Changes in v6: - get rid of the save/restore of SRAM - doing the copy of resume code once at init time - remove ROCKCHIP_ARM_OFF_LOGIC_DEEP from rk3288_fill_in_bootram - add of_platform_populate in rockchip_dt_init - change pmu_intmem@ff72 to sram@ff72 - change pmu_intmem@ff72 to sram@ff72 Changes in v5: - use rk3288_bootram_sz for memcpy size - fixed error of sram save and restore - change the size of sram in example - change size to 4k Changes in v4: - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris Zhong (4): ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support ARM: dts: add suspend voltage setting for RK808 .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16 ++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 55 - arch/arm/boot/dts/rk3288-evb.dtsi | 12 + arch/arm/boot/dts/rk3288.dtsi | 23 ++ arch/arm/mach-rockchip/Makefile| 1 + arch/arm/mach-rockchip/pm.c| 264 + arch/arm/mach-rockchip/pm.h| 99 arch/arm/mach-rockchip/rockchip.c | 2 + arch/arm/mach-rockchip/sleep.S | 73 ++ 9 files changed, 544 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/5] This is the 1st version of suspend for RK3288.
Hi Kevin On 11/08/2014 06:48 AM, Kevin Hilman wrote: Chris Zhong writes: RK3288 can shut down the cpu, gpu and other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin to high in the final stage of the process of suspend, pull the pin to low again when resume. The cover letter still doesn't state what this series applies to, or what its dependencies are for testing, even though it was requested in earlier reviews[1]. I discovered (again) by trial and error it applies to current linux-next. I also discovered (as was earlier discussed[2]) that it still does not resume using current upstream code, and those dependencies are not described here either. These are the kinds of things that are crucial in a cover letter in order to help reviewers and testers not have to spend time digging through the archives trying to remember from the previous round of reviews. Thank you for your review, I will perfect the cover letter in next version patches. Please, please list the out-of-tree dependencies, and how to test, including how you tested it, and on what hardware. Speaking of earlier reviews, I've noticed that after reviewing this series multiple times, you never respond to questions and/or comments. Two-way communication is important when collaborating on getting complex code this upstream, so please take some time to acknowledge the comments of reviewers and engage in discussion when questions are asked. Even if it's as simple as "OK, I'll fix it in the next version", that helps reviewers know that they're not wasting their time. OK, I'm going to respond all, even though only "Done". Kevin [1] https://lkml.org/lkml/2014/10/29/759 [2] https://lkml.org/lkml/2014/10/29/881 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 3/5] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change the size of sram in example
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..6b42fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,16 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader). This is a common use of the "pmu-sram" because it keeps power
+even in low power states in the system.
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
--
1.9.1
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[PATCH v7 5/5] ARM: dts: add suspend voltage setting for RK808
global_pwroff would be pull to high when RK3288 entering suspend,
this pin is a sleep signal for RK808, so RK808 could goto sleep
mode, and some regulators would be disable.
Signed-off-by: Chris Zhong
---
Changes in v7:
- add regulator-state-mem sub node for suspend
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb-rk808.dts | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..6145cf4 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -31,7 +31,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -50,6 +50,9 @@
regulator-min-microvolt = <75>;
regulator-max-microvolt = <135>;
regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_gpu: DCDC_REG2 {
@@ -58,12 +61,19 @@
regulator-min-microvolt = <85>;
regulator-max-microvolt = <125>;
regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-suspend-mem-enabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc_io: DCDC_REG4 {
@@ -72,6 +82,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-suspend-microvolt = <330>;
+ };
};
vccio_pmu: LDO_REG1 {
@@ -80,6 +93,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_pmu";
+ regulator-state-mem {
+ regulator-suspend-microvolt = <330>;
+ };
};
vcc_tp: LDO_REG2 {
@@ -88,6 +104,9 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_10: LDO_REG3 {
@@ -96,6 +115,9 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-suspend-microvolt = <100>;
+ };
};
vcc18_lcd: LDO_REG4 {
@@ -104,6 +126,9 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vccio_sd: LDO_REG5 {
@@ -112,6 +137,9 @@
[PATCH v7 4/5] ARM: dts: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v7: None
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change size to 4k
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cfc4378..0747c30 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -462,6 +462,11 @@
status = "disabled";
};
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -667,6 +672,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.9.1
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[PATCH v7 0/5] This is the 1st version of suspend for RK3288.
RK3288 can shut down the cpu, gpu and other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin to high in the final stage of the process of suspend, pull the pin to low again when resume. Changes in v7: - get rid all of unused code - add regulator-state-mem sub node for suspend Changes in v6: - modify comments - get rid of the save/restore of SRAM - doing the copy of resume code once at init time - remove ROCKCHIP_ARM_OFF_LOGIC_DEEP from rk3288_fill_in_bootram - add of_platform_populate in rockchip_dt_init - change pmu_intmem@ff72 to sram@ff72 - change pmu_intmem@ff72 to sram@ff72 Changes in v5: - modify comments - use rk3288_bootram_sz for memcpy size - fixed error of sram save and restore - change the size of sram in example - change size to 4k Changes in v4: - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris Zhong (5): clk: rockchip: RK3288: add suspend and resume ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support ARM: dts: add suspend voltage setting for RK808 .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16 ++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 46 +++- arch/arm/boot/dts/rk3288.dtsi | 11 + arch/arm/mach-rockchip/Makefile| 1 + arch/arm/mach-rockchip/pm.c| 264 + arch/arm/mach-rockchip/pm.h| 99 arch/arm/mach-rockchip/rockchip.c | 2 + arch/arm/mach-rockchip/sleep.S | 73 ++ drivers/clk/rockchip/clk-rk3288.c | 60 + 9 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] regulator: Document binding for regulator suspend voltage
On 11/01/2014 04:45 PM, Javier Martinez Canillas wrote: Hello Doug, On 11/01/2014 04:52 AM, Doug Anderson wrote: This patch builds upon (291d761 regulator: Document binding for regulator suspend state for PM state) to allow setting the uV in addition to the state at suspend time. Signed-off-by: Doug Anderson --- Documentation/devicetree/bindings/regulator/regulator.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index aaad615..4e7ed76 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -28,6 +28,8 @@ Optional properties: - regulator-state-[mem/disk] node has following common properties: - regulator-on-in-suspend: regulator should be on in suspend state. - regulator-off-in-suspend: regulator should be off in suspend state. + - regulator-suspend-microvolt: regulator should be set to this voltage + in suspend. The patch looks good to me: Reviewed-by: Javier Martinez Canillas On thing I wonder is if the binding should say that the suspend voltage is independent of the runtime one and it may be outside of the runtime range? Best regards, Javier Reviewed-by: Chris Zhong -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 5/7] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change the size of sram in example
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..6b42fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,16 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader). This is a common use of the "pmu-sram" because it keeps power
+even in low power states in the system.
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
--
1.7.9.5
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[PATCH v6 6/7] ARM: dts: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v6:
- change pmu_intmem@ff72 to sram@ff72
Changes in v5:
- change size to 4k
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..248c349 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -439,6 +439,11 @@
status = "disabled";
};
+ sram@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x1000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -634,6 +639,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.7.9.5
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[PATCH v6 7/7] ARM: dts: add suspend voltage setting for RK808
global_pwroff would be pull to high when RK3288 entering suspend,
this pin is a sleep signal for RK808, so RK808 could goto sleep
mode, and some regulators would be disable.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb-rk808.dts | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8..319fcb6 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -27,7 +27,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -46,6 +46,7 @@
regulator-min-microvolt = <75>;
regulator-max-microvolt = <130>;
regulator-name = "vdd_arm";
+ regulator-suspend-mem-disabled;
};
vdd_gpu: DCDC_REG2 {
@@ -54,12 +55,14 @@
regulator-min-microvolt = <85>;
regulator-max-microvolt = <125>;
regulator-name = "vdd_gpu";
+ regulator-suspend-mem-disabled;
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
+ regulator-suspend-mem-enabled;
};
vcc_io: DCDC_REG4 {
@@ -68,6 +71,7 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_io";
+ regulator-suspend-mem-microvolt = <330>;
};
vccio_pmu: LDO_REG1 {
@@ -76,6 +80,7 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_pmu";
+ regulator-suspend-mem-microvolt = <330>;
};
vcc_tp: LDO_REG2 {
@@ -84,6 +89,7 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-name = "vcc_tp";
+ regulator-suspend-mem-disabled;
};
vdd_10: LDO_REG3 {
@@ -92,6 +98,7 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd_10";
+ regulator-suspend-mem-microvolt = <100>;
};
vcc18_lcd: LDO_REG4 {
@@ -100,6 +107,7 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-name = "vcc18_lcd";
+ regulator-suspend-mem-disabled;
};
vccio_sd: LDO_REG5 {
@@ -108,6 +116,7 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <330>;
regulator-name = "vccio_sd";
+ regulator-suspend-mem-disabled;
};
vdd10_lcd: LDO_REG6 {
@@ -116,6 +125,7 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-name = "vdd10_lcd";
+ regulator-suspend-mem-disabled;
};
vcc_18: LDO_REG7 {
@@ -124,6 +134,7 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180&
[PATCH v6 0/7] This is the 1st version of suspend for RK3288.
RK3288 can shut down the cpu, gpu and other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin to high in the final stage of the process of suspend, pull the pin to low again when resume. Changes in v6: - modify comments - get rid of the save/restore of SRAM - doing the copy of resume code once at init time - remove ROCKCHIP_ARM_OFF_LOGIC_DEEP from rk3288_fill_in_bootram - add of_platform_populate in rockchip_dt_init - change pmu_intmem@ff72 to sram@ff72 - change pmu_intmem@ff72 to sram@ff72 Changes in v5: - reset-author - use "__maybe_unused" annotation - add pinctrl_force_default() in the error case - modify comments - use rk3288_bootram_sz for memcpy size - fixed error of sram save and restore - change the size of sram in example - change size to 4k Changes in v4: - use SIMPLE_DEV_PM_OPS for suspend/resume struct - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris Zhong (7): pinctrl: rockchip: add suspend/resume functions pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume clk: rockchip: RK3288: add suspend and resume ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support ARM: dts: add suspend voltage setting for RK808 .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 16 ++ arch/arm/boot/dts/rk3288-evb-rk808.dts | 16 +- arch/arm/boot/dts/rk3288.dtsi | 11 + arch/arm/mach-rockchip/Makefile|1 + arch/arm/mach-rockchip/pm.c| 278 arch/arm/mach-rockchip/pm.h| 103 arch/arm/mach-rockchip/rockchip.c |8 + arch/arm/mach-rockchip/sleep.S | 90 +++ drivers/clk/rockchip/clk-rk3288.c | 60 + drivers/pinctrl/pinctrl-rockchip.c | 46 10 files changed, 628 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 6/6] ARM: dts: add RK3288 suspend support
add pmu_intmem node for suspend, add global_pwroff pinctrl.
The pmu_intmem is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. PMICs can get this signal, then shut down
some power rails. So please reference the global_pwroff pinctrl
as part of the PMIC config.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..c52fe09 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -439,6 +439,11 @@
status = "disabled";
};
+ pmu_intmem@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x4000>;
+ };
+
pmu: power-management@ff73 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
@@ -634,6 +639,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1
&pcfg_pull_none>,
--
1.7.9.5
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[PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 000..77284c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,15 @@
+Rockchip SRAM for pmu:
+--
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader).
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ pmu_intmem@ff72 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff72 0x4000>;
+ };
--
1.7.9.5
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[PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
It's a basic version of suspend and resume for rockchip, it only support RK3288
now.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
---
Changes in v4:
- remove grf regmap
Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip
Changes in v2:
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore
arch/arm/mach-rockchip/Makefile |1 +
arch/arm/mach-rockchip/pm.c | 307 +
arch/arm/mach-rockchip/pm.h | 102
arch/arm/mach-rockchip/rockchip.c | 11 +-
arch/arm/mach-rockchip/sleep.S| 87 +++
5 files changed, 506 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-rockchip/pm.c
create mode 100644 arch/arm/mach-rockchip/pm.h
create mode 100644 arch/arm/mach-rockchip/sleep.S
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b29d8ea..5c3a9b2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,4 +1,5 @@
CFLAGS_platsmp.o := -march=armv7-a
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
new file mode 100644
index 000..c8e0091
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "pm.h"
+
+struct rockchip_pm_device_id {
+ const char *compatible;
+ const struct platform_suspend_ops *ops;
+ int (*init)(void);
+};
+
+static char bootram_save_data[SZ_4K];
+
+static void __iomem *rk3288_bootram_base;
+static phys_addr_t rk3288_bootram_phy;
+
+static struct regmap *pmu_regmap;
+static struct regmap *sgrf_regmap;
+
+static inline void rk3288_copy_data_to_sram(void)
+{
+ u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
+ (u32)rockchip_slp_cpu_resume + 4;
+
+ /* save root sram data in ddr mem */
+ memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
+ /* move resume code and data to bootsram */
+ memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
+ resume_code_size);
+}
+
+static inline void rk3288_restore_original_sram(void)
+{
+ memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
+}
+
+static inline u32 rk3288_l2_config(void)
+{
+ u32 l2ctlr;
+
+ asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
+ return l2ctlr;
+}
+
+static void rk3288_fill_in_bootram(u32 level)
+{
+ rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
+ rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+
+ rkpm_bootdata_l2ctlr_f = 1;
+ rkpm_bootdata_l2ctlr = rk3288_l2_config();
+
+ if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+ /*
+ * In this mode the SDRAM power domain will be off,
+ * so it need to be resumed,
+ * but now the sdram resume code is not ready.
+ * i have to set "rkpm_bootdata_ddr_code" 0.
+ */
+ rkpm_bootdata_ddr_code = 0;
+ } else {
+ rkpm_bootdata_ddr_code = 0;
+ }
+
+ rk3288_copy_data_to_sram();
+}
+
+static u32 rk3288_pmu_pwr_mode_con;
+static u32 rk3288_sgrf_soc_con0;
+
+static void rk3288_slp_mode_set(int level)
+{
+ u32 mode_set, mode_set1;
+
+ regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
+
+ regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+ &rk3288_pmu_pwr_mode_con);
+
+ /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
+
+ /* booting address of resuming system is from this register value */
+ regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
+rk3288_bootram_phy);
+
+ regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+PMU_ARMINT_WAKEUP_EN);
+
+ mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
+ BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
+ BIT(PMU_DDR0_GATI
[PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
save and restore some clks, which might be changed in suspend.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
drivers/clk/rockchip/clk-rk3288.c | 63 +
1 file changed, 63 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..0731b18 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include "clk.h"
@@ -762,6 +763,67 @@ static const char *rk3288_critical_clocks[] __initconst = {
"hclk_peri",
};
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+static const int rk3288_saved_cru_reg_ids[] = {
+ RK3288_MODE_CON,
+ RK3288_CLKSEL_CON(0),
+ RK3288_CLKSEL_CON(1),
+ RK3288_CLKSEL_CON(10),
+ RK3288_CLKSEL_CON(33),
+ RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+/*
+ * cru will be set in maskrom when system wake up from fastboot
+ * mode in suspend,
+ * so the operation is saving the changed regs.
+ * The apll/cpll/gpll will be set into slow mode in maskrom.
+ * It is mean that resume code run in 24m quit slowly!
+ * so we must resume these plls as soon as possible.
+ */
+static int rk3288_clk_suspend(void)
+{
+ int i, reg_id;
+
+ for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ rk3288_saved_cru_regs[i] =
+ readl_relaxed(rk3288_cru_base + reg_id);
+ }
+ return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+ int i, reg_id;
+
+ for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ writel_relaxed(rk3288_saved_cru_regs[i] | 0x,
+ rk3288_cru_base + reg_id);
+ }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+ .suspend = rk3288_clk_suspend,
+ .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+ rk3288_cru_base = reg_base;
+ register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
static void __init rk3288_clk_init(struct device_node *np)
{
void __iomem *reg_base;
@@ -810,5 +872,6 @@ static void __init rk3288_clk_init(struct device_node *np)
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+ rk3288_clk_sleep_init(reg_base);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
--
1.7.9.5
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[PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288
would modify it to sdmmc0_det, so it need to be restored to the correct
setting after resume from Maskrom.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index c4a988d..e2068fe 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1771,16 +1771,43 @@ static struct rockchip_pin_ctrl
*rockchip_pinctrl_get_soc_data(
}
#ifdef CONFIG_PM_SLEEP
+
+#define RK3288_GRF_GPIO6C_IOMUX0x64
+#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
+
+static u32 rk3288_grf_gpio6c_iomux;
+
static int rockchip_pinctrl_suspend(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = pinctrl_force_sleep(info->pctl_dev);
+
+ if (ret)
+ return ret;
+
+ /*
+* RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
+* the setting here, and restore it at resume.
+*/
+ if (info->ctrl->type == RK3288) {
+ ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ &rk3288_grf_gpio6c_iomux);
+ if (ret)
+ return ret;
+ }
- return pinctrl_force_sleep(info->pctl_dev);
+ return 0;
}
static int rockchip_pinctrl_resume(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ rk3288_grf_gpio6c_iomux |
+ GPIO6C6_SEL_WRITE_ENABLE);
+
+ if (ret)
+ return ret;
return pinctrl_force_default(info->pctl_dev);
}
--
1.7.9.5
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[PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
From: Chris
support suspend/resume of pinctrl, it allows handling sleep mode
for hogged pins in pinctrl
Signed-off-by: Chris Zhong
---
Changes in v4:
- use SIMPLE_DEV_PM_OPS for suspend/resume struct
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index 016f457..c4a988d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1770,6 +1770,25 @@ static struct rockchip_pin_ctrl
*rockchip_pinctrl_get_soc_data(
return ctrl;
}
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_pinctrl_suspend(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(info->pctl_dev);
+}
+
+static int rockchip_pinctrl_resume(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(info->pctl_dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
+rockchip_pinctrl_resume);
+
static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
@@ -1983,6 +2002,7 @@ static struct platform_driver rockchip_pinctrl_driver = {
.driver = {
.name = "rockchip-pinctrl",
.owner = THIS_MODULE,
+ .pm = &rockchip_pinctrl_dev_pm_ops,
.of_match_table = rockchip_pinctrl_dt_match,
},
};
--
1.7.9.5
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[PATCH v4 0/6] this is the 1st version of suspend. RK3288 can shut down the cpu, gpu and
other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin to high in the final stage of the process of suspend, pull the pin to low again when resume. Changes in v4: - use SIMPLE_DE_PM_OPS for suspend/resume struct - remove grf regmap Changes in v3: - move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed - add the regulator calls in prepare and finish. - add the pinmux of gpio6_c6 save and restore - put "rockchip,rk3288-pmu-sram" to first Chris (1): pinctrl: rockchip: add suspend/resume functions Chris Zhong (5): pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume clk: rockchip: RK3288: add suspend and resume ARM: rockchip: add suspend and resume for RK3288 ARM: rockchip: Add pmu-sram binding ARM: dts: add RK3288 suspend support .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 + arch/arm/boot/dts/rk3288.dtsi | 11 + arch/arm/mach-rockchip/Makefile|1 + arch/arm/mach-rockchip/pm.c| 307 arch/arm/mach-rockchip/pm.h| 102 +++ arch/arm/mach-rockchip/rockchip.c | 11 +- arch/arm/mach-rockchip/sleep.S | 87 ++ drivers/clk/rockchip/clk-rk3288.c | 63 drivers/pinctrl/pinctrl-rockchip.c | 47 +++ 9 files changed, 642 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt create mode 100644 arch/arm/mach-rockchip/pm.c create mode 100644 arch/arm/mach-rockchip/pm.h create mode 100644 arch/arm/mach-rockchip/sleep.S -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 1/2] regulator: pwm-regulator: get voltage and duty table from dts
rename st-pwm to pwm-regulator. And support getting voltage & duty table from
device tree, other platforms can also use this driver without any modify.
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v7:
Adviced by Mark Brown
- re-edit changelog
Changes in v6: None
Changes in v4:
Adviced by Doug Anderson
- improve kconfig
- add const for desc structure
Changes in v3:
Adviced by Doug Anderson
- Make Kconfig & Makefile alphabetical
- remove pwm_reg_period from pwm_regulator_data
- modify the calculation in pwm_regulator_set_voltage_sel
- add length validity check
Changes in v2:
Adviced by Lee Jones
- rename the file
- remove all the prefix st_
- add depend on PWM in Kconfig
drivers/regulator/Kconfig | 13 +-
drivers/regulator/Makefile |2 +-
drivers/regulator/{st-pwm.c => pwm-regulator.c} | 147 ---
3 files changed, 85 insertions(+), 77 deletions(-)
rename drivers/regulator/{st-pwm.c => pwm-regulator.c} (44%)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index fb32bab..b927cab 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -449,6 +449,13 @@ config REGULATOR_PFUZE100
Say y here to support the regulators found on the Freescale
PFUZE100/PFUZE200 PMIC.
+config REGULATOR_PWM
+ tristate "PWM voltage regulator"
+ depends on PWM
+ help
+ This driver supports PWM controlled voltage regulators. PWM
+ duty cycle can increase or decrease the voltage.
+
config REGULATOR_RC5T583
tristate "RICOH RC5T583 Power regulators"
depends on MFD_RC5T583
@@ -493,12 +500,6 @@ config REGULATOR_S5M8767
via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
supports DVS mode with 8bits of output voltage control.
-config REGULATOR_ST_PWM
- tristate "STMicroelectronics PWM voltage regulator"
- depends on ARCH_STI
- help
-This driver supports ST's PWM controlled voltage regulators.
-
config REGULATOR_TI_ABB
tristate "TI Adaptive Body Bias on-chip LDO"
depends on ARCH_OMAP
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 236fdbb..f3cf5a5 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
+obj-$(CONFIG_REGULATOR_PWM) += pwm-regulator.o
obj-$(CONFIG_REGULATOR_TPS51632) += tps51632-regulator.o
obj-$(CONFIG_REGULATOR_PBIAS) += pbias-regulator.o
obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
@@ -66,7 +67,6 @@ obj-$(CONFIG_REGULATOR_RK808) += rk808-regulator.o
obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
-obj-$(CONFIG_REGULATOR_ST_PWM) += st-pwm.o
obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
obj-$(CONFIG_REGULATOR_TI_ABB) += ti-abb-regulator.o
obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
diff --git a/drivers/regulator/st-pwm.c b/drivers/regulator/pwm-regulator.c
similarity index 44%
rename from drivers/regulator/st-pwm.c
rename to drivers/regulator/pwm-regulator.c
index 5ea78df..d3f55ea 100644
--- a/drivers/regulator/st-pwm.c
+++ b/drivers/regulator/pwm-regulator.c
@@ -1,5 +1,5 @@
/*
- * Regulator driver for ST's PWM Regulators
+ * Regulator driver for PWM Regulators
*
* Copyright (C) 2014 - STMicroelectronics Inc.
*
@@ -20,43 +20,40 @@
#include
#include
-#define ST_PWM_REG_PERIOD 8448
-
-struct st_pwm_regulator_pdata {
- const struct regulator_desc *desc;
- struct st_pwm_voltages *duty_cycle_table;
-};
-
-struct st_pwm_regulator_data {
- const struct st_pwm_regulator_pdata *pdata;
+struct pwm_regulator_data {
+ struct regulator_desc desc;
+ struct pwm_voltages *duty_cycle_table;
struct pwm_device *pwm;
bool enabled;
int state;
};
-struct st_pwm_voltages {
+struct pwm_voltages {
unsigned int uV;
unsigned int dutycycle;
};
-static int st_pwm_regulator_get_voltage_sel(struct regulator_dev *dev)
+static int pwm_regulator_get_voltage_sel(struct regulator_dev *dev)
{
- struct st_pwm_regulator_data *drvdata = rdev_get_drvdata(dev);
+ struct pwm_regulator_data *drvdata = rdev_get_drvdata(dev);
return drvdata->state;
}
-static int st_pwm_regulator_set_voltage_sel(struct regulator_dev *dev,
- unsigned selector)
+static int pwm_regulator_set_voltage_sel(struct regulator_dev *dev,
+unsigned selector)
{
- struct st_pwm_regulator_data *drvdata = rdev_get_drvdata(dev)
[PATCH v7 2/2] dt-bindings: add devicetree bindings for pwm regulator
Document the pwm regulator
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
---
Changes in v7:
- re-edit changelog
Changes in v6:
Adviced by Mark Rutland
- fix a spelling error
Changes in v4:
Adviced by Doug Anderson
- remove regulator-always-on and regulator-boot-on from the Example
Changes in v3:
Adviced by Doug Anderson
- update the Example
Changes in v2:
Adviced by Lee Jones
- rename the documentation
Adviced by Doug Anderson
- update the example
Adviced by Mark Rutland
- remove pwm-reg-period
.../bindings/regulator/pwm-regulator.txt | 27
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/pwm-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
new file mode 100644
index 000..ce91f61
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
@@ -0,0 +1,27 @@
+pwm regulator bindings
+
+Required properties:
+- compatible: Should be "pwm-regulator"
+- pwms: OF device-tree PWM specification (see PWM binding pwm.txt)
+- voltage-table: voltage and duty table, include 2 members in each set of
+ brackets, first one is voltage(unit: uv), the next is duty(unit: percent)
+
+Any property defined as part of the core regulator binding defined in
+regulator.txt can also be used.
+
+Example:
+ pwm_regulator {
+ compatible = "pwm-regulator;
+ pwms = <&pwm1 0 8448 0>;
+
+ voltage-table = <1114000 0>,
+ <1095000 10>,
+ <1076000 20>,
+ <1056000 30>,
+ <1036000 40>,
+ <1016000 50>;
+
+ regulator-min-microvolt = <1016000>;
+ regulator-max-microvolt = <1114000>;
+ regulator-name = "vdd_logic";
+ };
--
1.7.9.5
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