Re: [RESEND PATCH v1 0/4] Add support emac for the RK3036 SoC platform
On December 29, 2015 2:27:55 PM PST, "Heiko Stübner" wrote: >Hi Dave, > >Am Dienstag, 29. Dezember 2015, 15:53:14 schrieb David Miller: >> You have to submit this series properly, the same problem happend >twice >> now. >> >> When you submit a series you should: >> >> 1) Make it clear which tree you expect these changes to be applied >>to. Here it is completely ambiguous, do you want it to go into >>my networking tree or some other subsystem tree? >> >> 2) You MUST keep all parties informed about all patches for a series >>like this. That means you cannot drop netdev from patch #4 as >>you did both times. Doing this aggravates the situation for >>#1 even more, because if a patch is not CC:'d to netdev it does >>not enter patchwork. And if it doesn't go into patchwork, I'm >>not looking at it. > >I guess that is some unfortunate result of git send-email combined with > >get_maintainer.pl . In general I also prefer to see the whole series, >but have >gotten such partial series from other maintainers as well in the past, >so it >seems to be depending on preferences somewhat. You could run get_maintainer.pl against the individual patches in the series, merge the cc list somewhere in a file/variable and then do the actual mail submission with that full list for all patches. There could be a way to automate that with a bit of help from git send-email eventually. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] ARM: bcm2835: add rpi power domain driver
On 15/12/15 15:55, Eric Anholt wrote: > Florian Fainelli writes: > >> On 15/12/15 13:40, Eric Anholt wrote: >>> From: Alexander Aring >>> >>> This patch adds support for several power domains on Raspberry Pi, >>> including USB (so it can be enabled even if the bootloader didn't do >>> it), and graphics. >>> >>> This patch is the combined work of Eric Anholt (who wrote USB support >>> inside of the Raspberry Pi firmware driver, and wrote the non-USB >>> domain support) and Alexander Aring (who separated the original USB >>> work out from the firmware driver). >>> >>> Signed-off-by: Alexander Aring >>> Signed-off-by: Eric Anholt >>> --- >>> >>> v2: Add support for power domains other than USB, using the new >>> firmware interface, reword commit message (changes by Eric) >>> >>> v3: Restructure as a builtin driver, and drop >>> of_genpd_add_provider_onecell error handling to avoid >>> pm_genpd_exit() dependency until that API can be settled. Clean >>> up copyright header, add missing ISP initialization, and fix typo >>> in transposer's name. >>> >>> arch/arm/mach-bcm/Kconfig | 10 ++ >>> arch/arm/mach-bcm/Makefile | 1 + >>> arch/arm/mach-bcm/raspberrypi-power.c | 247 >>> >>> include/dt-bindings/arm/raspberrypi-power.h | 41 + >>> 4 files changed, 299 insertions(+) >>> create mode 100644 arch/arm/mach-bcm/raspberrypi-power.c >> >> What motivated the location of this power domain driver in >> arch/arm/mach-bcm? Should not we have this in drivers/power/ or >> somewhere in drivers/ at the very least? > > ls stronly suggests that power contains drivers for power supplies and > batteries, not power domains. There are 6 power domain drivers in > arch/arm, 3 in drivers/clk, and 3 in drivers/soc. If we ever have to support a different architecture which happens to use a similar power domain, then we want it to be in a location which makes it easy for sharing it in the first place. As it stands today, it does not seem useful to me to have this code in arch/arm/mach-bcm/ at all. Maybe there is room from a drivers/power/domains/ of some kind? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] ARM: bcm2835: add rpi power domain driver
On 15/12/15 13:40, Eric Anholt wrote: > From: Alexander Aring > > This patch adds support for several power domains on Raspberry Pi, > including USB (so it can be enabled even if the bootloader didn't do > it), and graphics. > > This patch is the combined work of Eric Anholt (who wrote USB support > inside of the Raspberry Pi firmware driver, and wrote the non-USB > domain support) and Alexander Aring (who separated the original USB > work out from the firmware driver). > > Signed-off-by: Alexander Aring > Signed-off-by: Eric Anholt > --- > > v2: Add support for power domains other than USB, using the new > firmware interface, reword commit message (changes by Eric) > > v3: Restructure as a builtin driver, and drop > of_genpd_add_provider_onecell error handling to avoid > pm_genpd_exit() dependency until that API can be settled. Clean > up copyright header, add missing ISP initialization, and fix typo > in transposer's name. > > arch/arm/mach-bcm/Kconfig | 10 ++ > arch/arm/mach-bcm/Makefile | 1 + > arch/arm/mach-bcm/raspberrypi-power.c | 247 > > include/dt-bindings/arm/raspberrypi-power.h | 41 + > 4 files changed, 299 insertions(+) > create mode 100644 arch/arm/mach-bcm/raspberrypi-power.c What motivated the location of this power domain driver in arch/arm/mach-bcm? Should not we have this in drivers/power/ or somewhere in drivers/ at the very least? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] net/macb: add support for resetting PHY using GPIO
On December 14, 2015 2:56:34 PM PST, Rob Herring wrote: >On Fri, Dec 11, 2015 at 11:34:53AM +0100, Gregory CLEMENT wrote: >> With device tree it is no more possible to reset the PHY at board >> level. Furthermore, doing in the driver allow to power down the PHY >when >> the network interface is no more used. >> >> This reset can't be done at the PHY driver level. The PHY must be >able to >> answer the to the mii bus scan to let the kernel creating a PHY >device. >> >> The patch introduces a new optional property "phy-reset-gpios" >inspired >> from the one use for the FEC. >> >> Signed-off-by: Gregory CLEMENT >> --- >> >> Since the v1, I used the gpiod functions. It allows to simplify the >> code and to not introduce any #ifdef. >> >> I also rename the property in phy-reset-gpios, even if actually the >> gpiod will match both phy-reset-gpios and phy-reset-gpio. >> >> >> Documentation/devicetree/bindings/net/macb.txt | 3 +++ >> drivers/net/ethernet/cadence/macb.c| 8 >> drivers/net/ethernet/cadence/macb.h| 1 + >> 3 files changed, 12 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/macb.txt >b/Documentation/devicetree/bindings/net/macb.txt >> index b5d7976..4a7fb6c 100644 >> --- a/Documentation/devicetree/bindings/net/macb.txt >> +++ b/Documentation/devicetree/bindings/net/macb.txt >> @@ -19,6 +19,9 @@ Required properties: >> Optional elements: 'tx_clk' >> - clocks: Phandles to input clocks. >> >> +Optional properties: >> +- phy-reset-gpios : Should specify the gpio for phy reset >> + > >This alone is simple enough, but I worry that this doesn't really >scale. >What if you need to enable clocks or regulators for the same reason? >The >mmc folks did a pwrseq binding for similar reasons. I don't think I'd >recommend that here as I think it is kind of ugly. We really need a >pre-probe/scan hook for drivers. This is also needed for USB devices >mounted on boards. In this particular case, the way Ethernet MAC drivers register their MDIO buses and therefore PHYs, there is always a good way to deassert the PHY GPIO line without requiring major core device driver changes. Worst case, there is the MDIO bus reset callback which could used for that matter. In the case of PCI, USB etc. I do agree having a way to twiddle things before scanning/probing would be awesome. I have some boards here which have GPIO controlled regulator and hacking the RC driver to deal with that is suboptimal... > >But I'm not going to hold up something simple to do all that, so: > >Acked-by: Rob Herring > >___ >linux-arm-kernel mailing list >linux-arm-ker...@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Sent from my Android device with K-9 Mail. Please excuse my brevity. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] net: emac: emac gigabit ethernet controller driver
On 14/12/15 16:19, Gilad Avidov wrote:
[snip]
> + "sgmii_irq";
> + qcom,emac-gpio-mdc = <&msmgpio 123 0>;
> + qcom,emac-gpio-mdio = <&msmgpio 124 0>;
> + qcom,emac-tstamp-en;
> + qcom,emac-ptp-frac-ns-adj = <12500 1>;
> + phy-addr = <0>;
Please use the standard Ethernet PHY and MDIO device tree bindings to
describe your MAC to PHY connection here, that includes using a
phy-connection-type property to describe the (x)MII lanes.
[snip]
> +/* EMAC_MAC_CTRL */
> +#define SINGLE_PAUSE_MODE 0x1000
> +#define DEBUG_MODE 0x800
> +#define BROAD_EN 0x400
> +#define MULTI_ALL0x200
> +#define RX_CHKSUM_EN 0x100
> +#define HUGE 0x80
> +#define SPEED_BMSK0x30
> +#define SPEED_SHFT 20
> +#define SIMR 0x8
> +#define TPAUSE 0x1
> +#define PROM_MODE 0x8000
> +#define VLAN_STRIP 0x4000
> +#define PRLEN_BMSK 0x3c00
> +#define PRLEN_SHFT 10
> +#define HUGEN0x200
> +#define FLCHK0x100
> +#define PCRCE 0x80
> +#define CRCE 0x40
> +#define FULLD 0x20
> +#define MAC_LP_EN 0x10
> +#define RXFC 0x8
> +#define TXFC 0x4
> +#define RXEN 0x2
> +#define TXEN 0x1
BIT(x)? which would avoid making this reverse christmas tree, I know
this is the time of year though.
[snip]
> +/* DMA address */
> +#define DMA_ADDR_HI_MASK 0xULL
> +#define DMA_ADDR_LO_MASK 0xULL
> +
> +#define EMAC_DMA_ADDR_HI(_addr) \
> + ((u32)(((u64)(_addr) & DMA_ADDR_HI_MASK) >> 32))
> +#define EMAC_DMA_ADDR_LO(_addr) \
> + ((u32)((u64)(_addr) & DMA_ADDR_LO_MASK))
The kernel provides helpers for that: upper_32bits and lower_32bits().
[snip]
> +struct emac_skb_cb {
> + u32 tpd_idx;
> + unsigned long jiffies;
> +};
> +
> +struct emac_tx_ts_cb {
> + u32 sec;
> + u32 ns;
> +};
> +
> +#define EMAC_SKB_CB(skb) ((struct emac_skb_cb *)(skb)->cb)
> +#define EMAC_TX_TS_CB(skb) ((struct emac_tx_ts_cb *)(skb)->cb)
Should not these two have different offsets within skb->cb in case they
both end-up being added to the same SKB?
[snip]
> +static void emac_mac_irq_enable(struct emac_adapter *adpt)
> +{
> + int i;
> +
> + for (i = 0; i < EMAC_NUM_CORE_IRQ; i++) {
> + struct emac_irq *irq = &adpt->irq[i];
> + const struct emac_irq_config*irq_cfg = &emac_irq_cfg_tbl[i];
> +
> + writel_relaxed(~DIS_INT, adpt->base + irq_cfg->status_reg);
> + writel_relaxed(irq->mask, adpt->base + irq_cfg->mask_reg);
> + }
> +
> + wmb(); /* ensure that irq and ptp setting are flushed to HW */
Would not using writel() make the appropriate thing here instead of
using _relaxed which has no barrier?
[snip]
> + mta = readl_relaxed(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
> + mta |= (0x1 << bit);
> + writel_relaxed(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
> + wmb(); /* ensure that the mac address is flushed to HW */
This is getting too much here, just use the correct I/O accessor for
your platform, period.
[snip]
> +
> + /* enable RX/TX Flow Control */
> + switch (phy->cur_fc_mode) {
> + case EMAC_FC_FULL:
> + mac |= (TXFC | RXFC);
> + break;
> + case EMAC_FC_RX_PAUSE:
> + mac |= RXFC;
> + break;
> + case EMAC_FC_TX_PAUSE:
> + mac |= TXFC;
> + break;
> + default:
> + break;
> + }
> +
> + /* setup link speed */
> + mac &= ~SPEED_BMSK;
> + switch (phy->link_speed) {
> + case EMAC_LINK_SPEED_1GB_FULL:
> + mac |= ((emac_mac_speed_1000 << SPEED_SHFT) & SPEED_BMSK);
> + csr1 |= FREQ_M
Re: [PATCH] MAINTAINERS: Add missing platform maintainers for dts files
Le 10/12/2015 15:38, Rob Herring a écrit : > Platform dts files need to be reviewed primarily by the platform > maintainers as dts files typically go in thru their trees. Add the missing > paths where there are existing maintainers listed. > > Signed-off-by: Rob Herring > --- [snip] > @@ -2300,6 +2314,7 @@ F: arch/arm/mach-bcm/ > F: arch/arm/boot/dts/bcm113* > F: arch/arm/boot/dts/bcm216* > F: arch/arm/boot/dts/bcm281* > +F: arch/arm64/boot/dts/broadcom/ > F: arch/arm/configs/bcm_defconfig > F: drivers/mmc/host/sdhci-bcm-kona.c > F: drivers/clocksource/bcm_kona_timer.c Acked-by: Florian Fainelli -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/3] ARM: dts: enable GPIO-a for Broadcom NSP
On 10/12/15 09:46, Linus Walleij wrote: > On Fri, Dec 4, 2015 at 6:12 PM, Yendapally Reddy Dhananjaya Reddy > wrote: > >> This enables the GPIO-a support for Broadcom NSP SoC >> >> Signed-off-by: Yendapally Reddy Dhananjaya Reddy > > Acked-by: Linus Walleij > > Please merge this through the ARM SoC tree or BCM upstream tree, > however that works. The same way as any other ARM-based SoCs, so I will take this one. Thanks. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH linux-next (v2) 3/3] mtd: brcmnand: Add support for the BCM6368
Le 09/12/2015 12:43, Simon Arlott a écrit :
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers.
>
> As the BCM6328, BCM6362 and BCM6368 all use v2.1 controllers, the first
> variant that will work with this driver is the BCM63268 using a v4.0
> controller.
>
> Set up the device by disabling and acking all interrupts, then handle
> the CTRL_READY interrupt.
>
> Signed-off-by: Simon Arlott
Reviewed-by: Florian Fainelli
> ---
> Changed "nand-intr-base" reg name to "nand-int-base".
>
> drivers/mtd/nand/brcmnand/Makefile | 1 +
> drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145
> +++
> 2 files changed, 146 insertions(+)
> create mode 100644 drivers/mtd/nand/brcmnand/bcm6368_nand.c
>
> diff --git a/drivers/mtd/nand/brcmnand/Makefile
> b/drivers/mtd/nand/brcmnand/Makefile
> index 3b1fbfd..b28ffb59 100644
> --- a/drivers/mtd/nand/brcmnand/Makefile
> +++ b/drivers/mtd/nand/brcmnand/Makefile
> @@ -2,5 +2,6 @@
> # more specific iproc_nand.o, for instance
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += iproc_nand.o
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm63138_nand.o
> +obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6368_nand.o
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o
> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
> diff --git a/drivers/mtd/nand/brcmnand/bcm6368_nand.c
> b/drivers/mtd/nand/brcmnand/bcm6368_nand.c
> new file mode 100644
> index 000..7f5359b
> --- /dev/null
> +++ b/drivers/mtd/nand/brcmnand/bcm6368_nand.c
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright 2015 Simon Arlott
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Derived from bcm63138_nand.c:
> + * Copyright © 2015 Broadcom Corporation
> + *
> + * Derived from
> bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
> + * Copyright 2000-2010 Broadcom Corporation
> + *
> + * Derived from
> bcm963xx_4.12L.06B_consumer/shared/opensource/flash/nandflash.c:
> + * Copyright 2000-2010 Broadcom Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "brcmnand.h"
> +
> +struct bcm6368_nand_soc {
> + struct brcmnand_soc soc;
> + void __iomem *base;
> +};
> +
> +#define BCM6368_NAND_INT 0x00
> +#define BCM6368_NAND_STATUS_SHIFT 0
> +#define BCM6368_NAND_STATUS_MASK(0xfff << BCM6368_NAND_STATUS_SHIFT)
> +#define BCM6368_NAND_ENABLE_SHIFT 16
> +#define BCM6368_NAND_ENABLE_MASK(0x << BCM6368_NAND_ENABLE_SHIFT)
> +#define BCM6368_NAND_BASE_ADDR0 0x04
> +#define BCM6368_NAND_BASE_ADDR1 0x0c
> +
> +enum {
> + BCM6368_NP_READ = BIT(0),
> + BCM6368_BLOCK_ERASE = BIT(1),
> + BCM6368_COPY_BACK = BIT(2),
> + BCM6368_PAGE_PGM= BIT(3),
> + BCM6368_CTRL_READY = BIT(4),
> + BCM6368_DEV_RBPIN = BIT(5),
> + BCM6368_ECC_ERR_UNC = BIT(6),
> + BCM6368_ECC_ERR_CORR= BIT(7),
> +};
> +
> +static bool bcm6368_nand_intc_ack(struct brcmnand_soc *soc)
> +{
> + struct bcm6368_nand_soc *priv =
> + container_of(soc, struct bcm6368_nand_soc, soc);
> + void __iomem *mmio = priv->base + BCM6368_NAND_INT;
> + u32 val = brcmnand_readl(mmio);
> +
> + if (val & (BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT)) {
> + /* Ack interrupt */
> + val &= ~BCM6368_NAND_STATUS_MASK;
> + val |= BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT;
> + brcmnand_writel(val, mmio);
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static void bcm6368_nand_intc_set(struct brcmnand_soc *soc, bool en)
> +{
> + struct bcm6368_nand_soc *priv =
> + container_of(soc, struct bcm6368_nand_soc, soc);
> + void __iomem *mmio = priv->base + BCM6368_NAND_INT;
> + u32 val = brcmnand_readl(mmio);
> +
> + /* Don't ack any interrupts */
> + val &= ~BCM6368_NAND_STATUS_MASK;
> +
> + if (en)
> + val |= BCM6368_CTRL
Re: [PATCH linux-next (v2) 2/3] mtd: brcmnand: Request and enable the clock if present
Le 09/12/2015 12:42, Simon Arlott a écrit :
> Attempt to enable a clock named "nand" as some SoCs have a clock for the
> controller that needs to be enabled.
>
> Signed-off-by: Simon Arlott
Reviewed-by: Florian Fainelli
> ---
> Resend, no changes.
>
> drivers/mtd/nand/brcmnand/brcmnand.c | 64
>
> 1 file changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
> b/drivers/mtd/nand/brcmnand/brcmnand.c
> index 190a99a..dca8162 100644
> --- a/drivers/mtd/nand/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
> @@ -11,6 +11,7 @@
> * GNU General Public License for more details.
> */
>
> +#include
> #include
> #include
> #include
> @@ -122,6 +123,9 @@ struct brcmnand_controller {
> /* Some SoCs provide custom interrupt status register(s) */
> struct brcmnand_soc *soc;
>
> + /* Some SoCs have a gateable clock for the controller */
> + struct clk *clk;
> +
> int cmd_pending;
> booldma_pending;
> struct completion done;
> @@ -2127,10 +2131,24 @@ int brcmnand_probe(struct platform_device *pdev,
> struct brcmnand_soc *soc)
> if (IS_ERR(ctrl->nand_base))
> return PTR_ERR(ctrl->nand_base);
>
> + /* Enable clock before using NAND registers */
> + ctrl->clk = devm_clk_get(dev, "nand");
> + if (!IS_ERR(ctrl->clk)) {
> + ret = clk_prepare_enable(ctrl->clk);
> + if (ret)
> + return ret;
> + } else {
> + ret = PTR_ERR(ctrl->clk);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> +
> + ctrl->clk = NULL;
> + }
> +
> /* Initialize NAND revision */
> ret = brcmnand_revision_init(ctrl);
> if (ret)
> - return ret;
> + goto err;
>
> /*
>* Most chips have this cache at a fixed offset within 'nand' block.
> @@ -2139,8 +2157,10 @@ int brcmnand_probe(struct platform_device *pdev,
> struct brcmnand_soc *soc)
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
> if (res) {
> ctrl->nand_fc = devm_ioremap_resource(dev, res);
> - if (IS_ERR(ctrl->nand_fc))
> - return PTR_ERR(ctrl->nand_fc);
> + if (IS_ERR(ctrl->nand_fc)) {
> + ret = PTR_ERR(ctrl->nand_fc);
> + goto err;
> + }
> } else {
> ctrl->nand_fc = ctrl->nand_base +
> ctrl->reg_offsets[BRCMNAND_FC_BASE];
> @@ -2150,8 +2170,10 @@ int brcmnand_probe(struct platform_device *pdev,
> struct brcmnand_soc *soc)
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
> if (res) {
> ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(ctrl->flash_dma_base))
> - return PTR_ERR(ctrl->flash_dma_base);
> + if (IS_ERR(ctrl->flash_dma_base)) {
> + ret = PTR_ERR(ctrl->flash_dma_base);
> + goto err;
> + }
>
> flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
> flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
> @@ -2160,13 +2182,16 @@ int brcmnand_probe(struct platform_device *pdev,
> struct brcmnand_soc *soc)
> ctrl->dma_desc = dmam_alloc_coherent(dev,
>sizeof(*ctrl->dma_desc),
>&ctrl->dma_pa, GFP_KERNEL);
> - if (!ctrl->dma_desc)
> - return -ENOMEM;
> + if (!ctrl->dma_desc) {
> + ret = -ENOMEM;
> + goto err;
> + }
>
> ctrl->dma_irq = platform_get_irq(pdev, 1);
> if ((int)ctrl->dma_irq < 0) {
> dev_err(dev, "missing FLASH_DMA IRQ\n");
> - return -ENODEV;
> + ret = -ENODEV;
> + goto err;
> }
>
> ret = devm_request_irq(dev, ctrl->dma_irq,
> @@ -2175,7 +2200,7 @@ int brcmnand_probe(struct platform_device *pdev, struct
> brcmnand_soc *soc)
> if (ret < 0) {
> dev_err(dev, "can't allocate IRQ %d: error %d\
Re: [PATCH linux-next (v2) 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
Le 09/12/2015 12:40, Simon Arlott a écrit :
> Add device tree binding for NAND on the BCM6368.
>
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers. It also requires a clock, so add an optional clock to the
> common brcmnand binding.
>
Reviewed-by: Florian Fainelli
> Signed-off-by: Simon Arlott
> ---
> Changed "nand-intr-base" reg name to "nand-int-base".
>
> .../devicetree/bindings/mtd/brcm,brcmnand.txt | 32
> ++
> 1 file changed, 32 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> index 4ff7128..ebfa6fc 100644
> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> @@ -45,6 +45,8 @@ Required properties:
> - #size-cells : <0>
>
> Optional properties:
> +- clock : reference to the clock for the NAND controller
> +- clock-names : "nand" (required for the above clock)
> - brcm,nand-has-wp : Some versions of this IP include a
> write-protect
>(WP) control bit. It is always available on >=
>v7.0. Use this property to describe the rare
> @@ -72,6 +74,12 @@ we define additional 'compatible' properties and
> associated register resources w
> and enable registers
> - reg-names: (required) "nand-int-base"
>
> + * "brcm,nand-bcm6368"
> + - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm6368"
> + - reg: (required) the 'NAND_INTR_BASE' register range, with combined
> status
> + and enable registers, and boot address registers
> + - reg-names: (required) "nand-int-base"
> +
> * "brcm,nand-iproc"
> - reg: (required) the "IDM" register range, for interrupt enable and APB
> bus access endianness configuration, and the "EXT" register range,
> @@ -148,3 +156,27 @@ nand@f0442800 {
> };
> };
> };
> +
> +nand@1200 {
> + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
> + "brcm,brcmnand-v4.0", "brcm,brcmnand";
> + reg = <0x1200 0x180>,
> + <0x1600 0x200>,
> + <0x10b0 0x10>;
> + reg-names = "nand", "nand-cache", "nand-intr-base";
> + interrupt-parent = <&periph_intc>;
> + interrupts = <50>;
> + clocks = <&periph_clk 20>;
> + clock-names = "nand";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nand0: nandcs@0 {
> + compatible = "brcm,nandcs";
> + reg = <0>;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <1>;
> + nand-ecc-step-size = <512>;
> + };
> +};
>
--
Florian
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Re: [PATCH net-next 1/2] net: hns: enet specisies a reference to dsaf
Subject: s/specisies/specifies/?
On 04/12/15 23:59, yankejian wrote:
> enet is associating with dasf. before this patch, the association is
> the same strings between ae-name and dsa-name. in a general way, enet
> specifies a reference to dsaf should be a good idea. so this patch
> deletes the ae-name in enet, and adds parsing the ae-handle
> from DT to set the associating with dsaf.
>
> Signed-off-by: yankejian
> ---
[snip]
> diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.c
> b/drivers/net/ethernet/hisilicon/hns/hnae.c
> index b364529..3bfe36f 100644
> --- a/drivers/net/ethernet/hisilicon/hns/hnae.c
> +++ b/drivers/net/ethernet/hisilicon/hns/hnae.c
> @@ -95,21 +95,17 @@ static struct hnae_buf_ops hnae_bops = {
> static int __ae_match(struct device *dev, const void *data)
> {
> struct hnae_ae_dev *hdev = cls_to_ae_dev(dev);
> - const char *ae_id = data;
>
> - if (!strncmp(ae_id, hdev->name, AE_NAME_SIZE))
> - return 1;
> -
> - return 0;
> + return hdev->dev->of_node == data;
> }
>
> -static struct hnae_ae_dev *find_ae(const char *ae_id)
> +static struct hnae_ae_dev *find_ae(const struct device_node *ae_node)
> {
> struct device *dev;
>
> - WARN_ON(!ae_id);
> + WARN_ON(!ae_node);
>
> - dev = class_find_device(hnae_class, NULL, ae_id, __ae_match);
> + dev = class_find_device(hnae_class, NULL, ae_node, __ae_match);
of_find_net_device_by_node might be used for this maybe?
--
Florian
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Re: [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
Le 05/12/2015 03:53, Kapil Hali a écrit : > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 5/5] ARM: BCM: Add SMP support for Broadcom 4708
Le 05/12/2015 03:53, Kapil Hali a écrit : > From: Jon Mason > > Add SMP support for Broadcom's 4708 SoCs. > > Signed-off-by: Jon Mason > Acked-by: Hauke Mehrtens > Tested-by: Hauke Mehrtens > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 4/5] ARM: BCM: Add SMP support for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add SMP support for Broadcom's Northstar Plus SoC > cpu enable method. This changes also consolidates > iProc family's - BCM NSP and BCM Kona, platform > SMP handling in a common file. > > Northstar Plus SoC is based on ARM Cortex-A9 > revision r3p0 which requires configuration for ARM > Errata 764369 for SMP. This change adds the needed > configuration option. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 3/5] ARM: dts: Add SMP support for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add device tree changes required for providing SMP support > for Broadcom Northstar Plus SoC. > > Signed-off-by: Kapil Hali Applied to devicetree/next; thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
Le 05/12/2015 03:53, Kapil Hali a écrit : > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali Applied to devicetree/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
On 04/12/15 12:23, Kapil Hali wrote:
> These changes cleans up SMP implementaion for Broadcom's
> Kona SoC which are required for handling SMP for iProc
> family of SoCs at a single place for BCM NSP and BCM Kona.
>
> Signed-off-by: Kapil Hali
> ---
> arch/arm/boot/dts/bcm11351.dtsi | 2 +-
> arch/arm/boot/dts/bcm21664.dtsi | 2 +-
> arch/arm/mach-bcm/kona_smp.c| 82
> +++--
> 3 files changed, 56 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
> index 2ddaa51..3dc7a8c 100644
> --- a/arch/arm/boot/dts/bcm11351.dtsi
> +++ b/arch/arm/boot/dts/bcm11351.dtsi
> @@ -31,7 +31,6 @@
> #address-cells = <1>;
> #size-cells = <0>;
> enable-method = "brcm,bcm11351-cpu-method";
> - secondary-boot-reg = <0x3500417c>;
I would expect the 'enable-method' to be moved as well to be consistent
with what you are adding for NSP later on.
>
> cpu0: cpu@0 {
> device_type = "cpu";
> @@ -42,6 +41,7 @@
> cpu1: cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> + secondary-boot-reg = <0x3500417c>;
> reg = <1>;
> };
--
Florian
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Re: [PATCH v5 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
On 04/12/15 12:23, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali
> ---
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39
> ++
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> 2 files changed, 40 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git
> a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 000..bf08872
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,39 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +-
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> + - enable-method = "brcm,bcm-nsp-smp";
> + - secondary-boot-reg = <...>;
That comment is not quite correct with respect to the paragraph below then?
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register which should hold the common
> +entry point for a secondary CPU. This entry is cpu node specific
> +and should be added per cpu. E.g., in case of NSP (BCM58625) which
> +is a dual core CPU SoC, this entry should be added to cpu1 node.
> +
> +
> +Example:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "brcm,bcm-nsp-smp";
Based on the requested feedback, this property should now be placed
under the cpu1 node.
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <1>;
> + secondary-boot-reg = <0x042c>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
> b/Documentation/devicetree/bindings/arm/cpus.txt
> index 3a07a87..d191554 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -190,6 +190,7 @@ nodes to be present and contain the properties described
> below.
> "allwinner,sun6i-a31"
> "allwinner,sun8i-a23"
> "arm,psci"
> + "brcm,bcm-nsp-smp"
> "brcm,brahma-b15"
> "marvell,armada-375-smp"
> "marvell,armada-380-smp"
>
--
Florian
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Re: [PATCH v4 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
On 02/12/15 08:06, Kapil Hali wrote: >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt >>> @@ -0,0 +1,39 @@ >>> +Broadcom Northstar Plus SoC CPU Enable Method >>> +- >>> +This binding defines the enable method used for starting secondary >>> +CPUs in the following Broadcom SoCs: >>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 >>> + >>> +The enable method is specified by defining the following required >>> +properties in the "cpus" device tree node: >>> + - enable-method = "brcm,bcm-nsp-smp"; >>> + - secondary-boot-reg = <...>; >> >> Both of these are supposed to be per cpu core. > > 'enable-method' if not found in 'cpu' node is looked at in the 'cpus' > node. Except for two-three SoC families, 'enable-method' is within > 'cpus' node. Is my interpretation incorrect? Did I miss anything here? So, what do we do from here? I would appreciate a timely answer from the DT maintainers here so we can decide on the fate of this patch series for 4.5. Thank you -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v6) 1/2] mtd: brcmnand: Add brcm,bcm63268-nand device tree binding
On 02/12/15 12:02, Simon Arlott wrote: > On 02/12/15 19:38, Florian Fainelli wrote: >> 2015-12-02 11:05 GMT-08:00 Brian Norris : >>> + Broadcom list + Kamal >>> >>> On Tue, Nov 24, 2015 at 08:19:37PM -, Simon Arlott wrote: >>>> Add device tree binding for NAND on the BCM63268. >>>> >>>> The BCM63268 has a NAND interrupt register with combined status and enable >>>> registers. >>>> >>>> Signed-off-by: Simon Arlott >>>> --- >>>> .../devicetree/bindings/mtd/brcm,brcmnand.txt | 35 >>>> ++ >>>> 1 file changed, 35 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >>>> b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >>>> index 4ff7128..f2a71c8 100644 >>>> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >>>> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >>>> @@ -72,6 +72,14 @@ we define additional 'compatible' properties and >>>> associated register resources w >>>> and enable registers >>>> - reg-names: (required) "nand-int-base" >>>> >>>> + * "brcm,nand-bcm63268" >>>> + - compatible: should contain "brcm,nand-bcm", >>>> "brcm,nand-bcm63268" >>> >>> Looks like you're aiming to support bcm63168? Is bcm63268 the first >>> chip to include this style of register then? The numbering seems >>> backwards, but that may just be reality. >> >> 6362 (NAND rev 2.1, ann. Sep 8, 2009), 6368 (v0.1?!?, ann. Jan 7, >> 2009) and 6328 (v2.1, can't find release date) are earlier chips that >> have an identical combined interrupt enable + status register and a >> NAND controller within the same 32-bits word, so these would qualify >> as a better compatible string for this specific addition integration >> stub here. I would gowith 6368 here then? >> > > I could change it to 6368 but there's no documented NAND_INTR_BASE for > it. Only the 63268 and 6818 have a #define for NAND_INTR_BASE. > It looks exactly the same as the 63268 layout, and double checking, this appears to be a v2.1 controller as well, it was not just properly documented as such. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v6) 1/2] mtd: brcmnand: Add brcm,bcm63268-nand device tree binding
2015-12-02 11:05 GMT-08:00 Brian Norris : > + Broadcom list + Kamal > > On Tue, Nov 24, 2015 at 08:19:37PM -, Simon Arlott wrote: >> Add device tree binding for NAND on the BCM63268. >> >> The BCM63268 has a NAND interrupt register with combined status and enable >> registers. >> >> Signed-off-by: Simon Arlott >> --- >> .../devicetree/bindings/mtd/brcm,brcmnand.txt | 35 >> ++ >> 1 file changed, 35 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >> b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >> index 4ff7128..f2a71c8 100644 >> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt >> @@ -72,6 +72,14 @@ we define additional 'compatible' properties and >> associated register resources w >> and enable registers >> - reg-names: (required) "nand-int-base" >> >> + * "brcm,nand-bcm63268" >> + - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm63268" > > Looks like you're aiming to support bcm63168? Is bcm63268 the first > chip to include this style of register then? The numbering seems > backwards, but that may just be reality. 6362 (NAND rev 2.1, ann. Sep 8, 2009), 6368 (v0.1?!?, ann. Jan 7, 2009) and 6328 (v2.1, can't find release date) are earlier chips that have an identical combined interrupt enable + status register and a NAND controller within the same 32-bits word, so these would qualify as a better compatible string for this specific addition integration stub here. I would gowith 6368 here then? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding
2015-11-30 12:52 GMT-08:00 Simon Arlott : > Add device tree binding for the BCM63xx's gated clocks. > > The BCM63xx contains clocks gated with a register. Clocks are indexed > by bits in the register and are active high. Clock gate bits are > interleaved with other status bits and configurable clocks in the same > register. > > Signed-off-by: Simon Arlott > --- > .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 > ++ > 1 file changed, 58 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > > diff --git > a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > new file mode 100644 > index 000..3f4ead1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > @@ -0,0 +1,58 @@ > +Broadcom BCM63xx clocks > + > +This binding uses the common clock binding: > + Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +The BCM63xx contains clocks gated with a register. Clocks are indexed > +by bits in the register and are active high. Clock gate bits are > +interleaved with other status bits and configurable clocks in the same > +register. Most MIPS-based BCM63xx SoCs have clock gating set of registers, these SoCs are pretty much all of them except 63381 (maybe newer ones too), this one uses the PMB interface, like 63138 to control resets and clocks fed to peripherals. > + > +Required properties: > +- compatible: Should be "brcm,bcm-gate-clk", "brcm,bcm63xx-gate-clk" I think we would want to start with the lowest common denominator here, which is either 6345 or 6348. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] clk: bcm63xx: Add BCM63xx gated clock support
2015-11-30 12:54 GMT-08:00 Simon Arlott : > The BCM63xx contains clocks gated with a register. Clocks are indexed > by bits in the register and are active high. Clock gate bits are > interleaved with other status bits and configurable clocks in the same > register. > > Enabled by default for BMIPS_GENERIC. > > Signed-off-by: Simon Arlott > --- [snip] > + > +config CLK_BCM63XX > + bool "Broadcom BCM63xx clock support" > + depends on BMIPS_GENERIC > + depends on COMMON_CLK > + default y default BMIPS_GENERIC? > + help > + Enable clock framework support for Broadcom 63xx SoCs > diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile > index 3fc9506..4f5f8ce 100644 > --- a/drivers/clk/bcm/Makefile > +++ b/drivers/clk/bcm/Makefile > @@ -8,3 +8,4 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o > obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o > obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o > obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o > +obj-$(CONFIG_CLK_BCM63XX) += clk-bcm63xx.o > diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c > new file mode 100644 > index 000..0e8cc06 > --- /dev/null > +++ b/drivers/clk/bcm/clk-bcm63xx.c There is a pending clk-bcm63xx.c implementation, covering BCM63138 in Stephen Boyd's clk/next tree, which you would want to base your patches on, it is not a huge deal to resolve the conflict, and there will be separate entry points and functions based on the compatible string anyway... > @@ -0,0 +1,187 @@ > +/* > + * Copyright 2015 Simon Arlott > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * Based on clk-gate.c: > + * Copyright (C) 2010-2011 Canonical Ltd > + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd > + */ I am not really anything very specific to 63xx chips in there, in fact, this looks like a fairly generic clk-gate driver using regmap to get its masks and offsets, would it make sense to create clk-gate-regmap.c which exposes the bulk of what you are doing and you could match using a specific compatible string? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] reset: bcm63xx: Add support for the BCM63xx soft-reset controller
2015-11-30 12:58 GMT-08:00 Simon Arlott :
> The BCM63xx contains a soft-reset controller activated by setting
> a bit (that must previously have cleared).
>
> Signed-off-by: Simon Arlott
> ---
> MAINTAINERS | 1 +
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile| 1 +
> drivers/reset/reset-bcm63xx.c | 134
> ++
> 4 files changed, 145 insertions(+)
> create mode 100644 drivers/reset/reset-bcm63xx.c
Could you create a bcm directory and then add your reset-bcm63xx.c
file there? I have a pending submission for the BCM63138 reset
controller which is not at all using the same structure and will share
nothing with your driver.
[snip]
> +static int bcm63xx_reset_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *reset_spec)
> +{
> + struct bcm63xx_reset_priv *priv = to_bcm63xx_reset_priv(rcdev);
> +
> + if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
> + return -EINVAL;
> +
> + if (reset_spec->args[0] >= rcdev->nr_resets)
> + return -EINVAL;
Should not these two things be moved to the core reset controller code
based on the #reset-cells value?
[snip]
> + if (of_property_read_u32(np, "offset", &priv->offset))
> + return -EINVAL;
> +
> + /* valid reset bits */
> + if (of_property_read_u32(np, "mask", &priv->mask))
> + priv->mask = 0x;
> +
> + priv->rcdev.owner = THIS_MODULE;
> + priv->rcdev.ops = &bcm63xx_reset_ops;
> + priv->rcdev.nr_resets = 32;
Should not that come from Device Tree, or be computed based on the
mask property, like hweight_long() or something along these lines?
> + priv->rcdev.of_node = pdev->dev.of_node;
> + priv->rcdev.of_reset_n_cells = 1;
> + priv->rcdev.of_xlate = bcm63xx_reset_xlate;
--
Florian
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Re: [PATCH v4 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
On 01/12/15 08:24, Kapil Hali wrote: > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. FWIW, I gave this patch a try on a Capri board, and this still brings-up the two CPUs successfully: MMC read: dev # 0, block # 114688, count 32768 ... 100% (32768/32768 blocks) 32768 blocks read: OK ## Starting application at 0x80008000 ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.4.0-rc1-5-ge49c96ed573e (fainelli@fainelli-desktop) (gcc version 4. 8.5 (Broadcom stbgcc-4.8-1.4) ) #605 SMP Tue Dec 1 17:53:02 PST 2015 [0.00] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: BCM28155 AP board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writealloc [0.00] PERCPU: Embedded 12 pages/cpu @ef7d3000 s18752 r8192 d22208 u49152 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260608 [0.00] Kernel command line: console=ttyS0,115200n8 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1009696K/1048576K available (6384K kernel code, 279K rwdata, 2268K rodata, 4152 K init, 218K bss, 22496K reserved, 16384K cma-reserved, 245760K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xf080 - 0xff80 ( 240 MB) [0.00] lowmem : 0xc000 - 0xf000 ( 768 MB) [0.00] pkmap : 0xbfe0 - 0xc000 ( 2 MB) [0.00] modules : 0xbf00 - 0xbfe0 ( 14 MB) [0.00] .text : 0xc0008000 - 0xc087b694 (8654 kB) [0.00] .init : 0xc087c000 - 0xc0c8a000 (4152 kB) [0.00] .data : 0xc0c8a000 - 0xc0ccfdf8 ( 280 kB) [0.00].bss : 0xc0cd2000 - 0xc0d08bac ( 219 kB) [0.00] Hierarchical RCU implementation. [0.00] Build-time adjustment of leaf fanout to 32. [0.00] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. [0.00] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2 [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] __ccu_wait_bit: slave_ccu/0x0484 bit 18 was never set [0.00] __peri_clk_init: error initializing gate for bsc3 [0.00] Broadcom slave_ccu initialization had errors [0.00] sched_clock: 32 bits at 1kHz, resolution 100ns, wraps every 214748364750ns [0.00] Console: colour dummy device 80x30 [0.006000] Calibrating delay loop... 2383.87 BogoMIPS (lpj=1191936) [0.006000] pid_max: default: 32768 minimum: 301 [0.006000] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.006000] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.006000] CPU: Testing write buffer coherency: ok [0.006000] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.006000] Setting up static identity map for 0x800082c0 - 0x80008318 [0.015000] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 [0.015000] Brought up 2 CPUs [0.015000] SMP: Total of 2 processors activated (7200.76 BogoMIPS). [0.015000] CPU: All CPU(s) started in SVC mode. [0.015000] devtmpfs: initialized [0.016000] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [0.016000] clocksource: jiffies: mask: 0x max_cycles: 0x, max_idle_ns: 19112604462 75000 ns [0.016000] pinctrl core: initialized pinctrl subsystem [0.017000] NET: Registered protocol family 16 [0.017000] DMA: preallocated 256 KiB pool for atomic coherent allocations [0.023000] cpuidle: using governor ladder [0.025000] cpuidle: using governor menu [0.026000] Kona Secure API initialized [0.026000] BCM-L2C-310 cache controller enabled, 16 ways, 512 kB [0.026000] BCM-L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x1e05 [0.026000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. [0.026000] hw-breakpoint: maximum watchpoint size is 4 bytes. [0.033000] SCSI subsystem initialized [0.033000] usbcore: registered new interface driver usbfs [0.033000] usbcore: registered new interface driver hub [0.033000] usbcore: registered new device driver usb [0.033000] Linux video capture interface: v2.00 [0.033000] pps_core: LinuxPPS API ver. 1 registered [0.033000] pps_core: Software ver. 5.3.6 - Copyright 2005-2
Re: [PATCH] Enable PCIe PHY support in Cygnus
On 01/12/15 15:18, Arnd Bergmann wrote: > On Tuesday 01 December 2015 15:12:41 Florian Fainelli wrote: >> CC lib/bitmap.o >> >> I added an #address-cells = <0> and #size-cells = <1> to fix this, since >> your reg property is a single digit. > > Did you mean #address-cells = <1> and #size-cells = <0>? Ermm, yes, thanks for catching this.. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: enable pinctrl for Broadcom NSP
On 20/11/15 09:58, Yendapally Reddy Dhananjaya Reddy wrote: > This enables the pinctrl support for Broadcom NSP SoC > > Signed-off-by: Yendapally Reddy Dhananjaya Reddy Applied to devicetree/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Enable PCIe PHY support in Cygnus
On 24/11/15 16:12, Florian Fainelli wrote: > On 18/11/15 10:16, Ray Jui wrote: >> This patch enales PCIe PHY in device tree for Broadcom Cygnus based platforms >> >> This patch is developed based on v4.4-rc1 and available here: >> https://github.com/Broadcom/cygnus-linux/tree/cygnus-pcie-phy-dt-v1 >> >> Ray Jui (1): >> ARM: dts: enable PCIe PHY support for Cygnus > > Applied to devicetree/next with Scott's Acked-by, thanks! This caused the DTC compiler to warn: Warning (reg_format): "reg" property in /axi/phy@0301d0a0/phy@0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): "reg" property in /axi/phy@0301d0a0/phy@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /axi/phy@0301d0a0/phy@0 Warning (avoid_default_addr_size): Relying on default #size-cells value for /axi/phy@0301d0a0/phy@0 Warning (avoid_default_addr_size): Relying on default #address-cells value for /axi/phy@0301d0a0/phy@1 Warning (avoid_default_addr_size): Relying on default #size-cells value for /axi/phy@0301d0a0/phy@1 CC drivers/base/power/runtime.o DTC arch/arm/boot/dts/bcm911360k.dtb CC lib/bitmap.o I added an #address-cells = <0> and #size-cells = <1> to fix this, since your reg property is a single digit. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/5] ARM: BCM: Add SMP support for Broadcom NSP
On 01/12/15 08:24, Kapil Hali wrote: > Add SMP support for Broadcom's Northstar Plus SoC > cpu enable method. This changes also consolidates > iProc family's - BCM NSP and BCM Kona, platform > SMP handling in a common file. > > Northstar Plus SoC is based on ARM Cortex-A9 > revision r3p0 which requires configuration for ARM > Errata 764369 for SMP. This change adds the needed > configuration option. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 5/5] ARM: BCM: Add SMP support for Broadcom 4708
On 01/12/15 08:24, Kapil Hali wrote: > From: Jon Mason > > Add SMP support for Broadcom's 4708 SoCs. > > Signed-off-by: Jon Mason > Acked-by: Hauke Mehrtens > Tested-by: Hauke Mehrtens > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/5] ARM: dts: Add SMP support for Broadcom NSP
On 01/12/15 08:24, Kapil Hali wrote: > Add device tree changes required for providing SMP support > for Broadcom Northstar Plus SoC. > > Signed-off-by: Kapil Hali Applied to devicetree/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
On 01/12/15 08:24, Kapil Hali wrote: > These changes cleans up SMP implementaion for Broadcom's > Kona SoC which are required for handling SMP for iProc > family of SoCs at a single place for BCM NSP and BCM Kona. > > Signed-off-by: Kapil Hali Applied to soc/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
On 01/12/15 08:24, Kapil Hali wrote: > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali Applied to devicetree/next, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Enable PCIe PHY support in Cygnus
On 18/11/15 10:16, Ray Jui wrote: > This patch enales PCIe PHY in device tree for Broadcom Cygnus based platforms > > This patch is developed based on v4.4-rc1 and available here: > https://github.com/Broadcom/cygnus-linux/tree/cygnus-pcie-phy-dt-v1 > > Ray Jui (1): > ARM: dts: enable PCIe PHY support for Cygnus Applied to devicetree/next with Scott's Acked-by, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/7] dts: define ngpios property in gpio controller's node
On 18/11/15 19:52, Pramod Kumar wrote: > Add ngpios property in cygnus ASIU, CCM and CRMU gpio controller's node > > Signed-off-by: Pramod Kumar > Reviewed-by: Ray Jui > Reviewed-by: Scott Branden Applied to devicetree/next with a more specific subject, thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: enable pinctrl for Broadcom NSP
On 20/11/15 09:58, Yendapally Reddy Dhananjaya Reddy wrote:
> This enables the pinctrl support for Broadcom NSP SoC
>
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy
Looks like a sane pinctrl node here, unless there are objections, I
would like to go ahead and apply this for v4.5, thanks!
> ---
> arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++
> arch/arm/boot/dts/bcm958625k.dts | 9 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> index b74438c..a16d743 100644
> --- a/arch/arm/boot/dts/bcm-nsp.dtsi
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -226,5 +226,12 @@
> interrupts = ;
> clock-frequency = <10>;
> };
> +
> + pinctrl: pinctrl@3f1c0 {
> + compatible = "brcm,nsp-pinmux";
> + reg = <0x3f1c0 0x04>,
> + <0x30028 0x04>,
> + <0x3f408 0x04>;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/bcm958625k.dts
> b/arch/arm/boot/dts/bcm958625k.dts
> index b966955..e298450 100644
> --- a/arch/arm/boot/dts/bcm958625k.dts
> +++ b/arch/arm/boot/dts/bcm958625k.dts
> @@ -105,3 +105,12 @@
> };
> };
> };
> +
> +&pinctrl {
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_sel>;
> + nand_sel: nand_sel {
> + function = "nand";
> + groups = "nand_grp";
> + };
> +};
>
--
Florian
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Re: [PATCH RESEND v2 0/4] SMP support for Broadcom NSP
On 06/11/15 11:49, Kapil Hali wrote:
> This is the second iteration in the series.
>
> Changes in v2:
> Removed the pen_holding method of SMP bringup for NSP SoC and
> replaced it with simple wakeup of secondary core using ARM IPI.
>
>
> This series adds SMP support for Broadcom's Northstar Plus SoC.
>
> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
> BCM NSP SoC, has a typical such mechanism - after power-on, the
> secondary core is held in a standby state, primary core provides a
> startup address for the secondary core and wakes it up. Booting of
> the secondary core is serialized using pen_release global variable.
>
> The startup address is programmed at a special register location
> which is defined in the device tree using a "secondary-boot-reg"
> property in a node whose "enable-method" property matches.
>
> The first patch adds cpu-enable-method in the device tree bindings
> documentation. It also updates ARM CPU device tree documentation
> with Broadcom Northstar Plus CPU details.
>
> The second patch adds SMP support to the BCM NSP device tree file.
>
> The third patch, enables SMP on BCM NSP. It also consolidates
> common SMP handling between BCM NSP and BCM Kona.
>
> The final patch, enables SMP on BCM 4708 and this patch is pulled
> in from Jon Mason's patch from the mailing list.
>
> This patch series is constructed based on Linux v4.3-rc2.
>
> The source code is available at GITHUB:
> https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1
Kapil, were there additional changes requested for this patch series to
be applied? The secondary-boot-reg property should probably be made part
of the CPU node, even though you are strictly following the existing
Kona SMP binding here (which was partially wrong on that subject).
Could you resubmit these patches if there is anything that needs
changing? Thanks!
>
> Jon Mason (1):
> ARM: BCM: Add SMP support for Broadcom 4708
>
> Kapil Hali (3):
> dt-bindings: add SMP enable-method for Broadcom NSP
> ARM: dts: add SMP support for Broadcom NSP
> ARM: BCM: Add SMP support for Broadcom NSP
>
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 +
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> arch/arm/boot/dts/bcm-nsp.dtsi | 33 ++---
> arch/arm/boot/dts/bcm4708.dtsi | 2 +
> arch/arm/mach-bcm/Kconfig | 3 +
> arch/arm/mach-bcm/Makefile | 11 ++-
> arch/arm/mach-bcm/bcm_nsp.h| 19 +
> arch/arm/mach-bcm/{kona_smp.c => platsmp.c}| 85
> +++---
> 8 files changed, 167 insertions(+), 23 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
> rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)
>
--
Florian
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Re: [PATCH (v2) 7/10] watchdog: bcm63xx_wdt: Add get_timeleft function
On 24/11/15 14:15, Simon Arlott wrote: > Return the remaining time from the hardware control register. > > Warn when the device is registered if the hardware watchdog is currently > running and report the remaining time left. > > Signed-off-by: Simon Arlott Reviewed-by: Florian Fainelli At some point, we should probably consider merging bcm63xx_wdt with bcm7038_wdt which are nearly 100% identical pieces of hardware (coming from the same design group originally). -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v2) 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk
On 24/11/15 14:12, Simon Arlott wrote: > Instead of using a fixed clock HZ in the driver, obtain it from the > "periph" clk that the watchdog timer uses. > > Signed-off-by: Simon Arlott Reviewed-by: Florian Fainelli -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v3) 2/10] MIPS: bmips: Add bcm6345-l2-timer interrupt controller
On 24/11/15 14:10, Simon Arlott wrote:
> Add the BCM6345/BCM6318 timer as an interrupt controller so that it can be
> used by the watchdog to warn that its timer will expire soon.
>
> Support for clocksource/clockevents is not implemented as the timer
> interrupt is not per CPU (except on the BCM6318) and the MIPS clock is
> better. This could be added later if required without changing the device
> tree binding.
>
> Signed-off-by: Simon Arlott
> ---
> Fixed the offset of the count registers, they were writing off by one which
> caused it to set the watchdog timeout to 0.
>
> drivers/irqchip/Kconfig| 5 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-bcm6345-l2-timer.c | 324
> +
> 3 files changed, 330 insertions(+)
> create mode 100644 drivers/irqchip/irq-bcm6345-l2-timer.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index d307bb3..21c3d9b 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -70,6 +70,11 @@ config BCM6345_L1_IRQ
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
>
> +config BCM6345_L2_TIMER_IRQ
> + bool
> + select GENERIC_IRQ_CHIP
> + select IRQ_DOMAIN
> +
> config BCM7038_L1_IRQ
> bool
> select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index ded59cf..2687dea 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_XTENSA_MX) +=
> irq-xtensa-mx.o
> obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
> obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
> obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
> +obj-$(CONFIG_BCM6345_L2_TIMER_IRQ) += irq-bcm6345-l2-timer.o
> obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
> obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
> obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
> diff --git a/drivers/irqchip/irq-bcm6345-l2-timer.c
> b/drivers/irqchip/irq-bcm6345-l2-timer.c
> new file mode 100644
> index 000..4e6f71b
> --- /dev/null
> +++ b/drivers/irqchip/irq-bcm6345-l2-timer.c
> @@ -0,0 +1,324 @@
> +/*
> + * Copyright 2015 Simon Arlott
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Based on arch/mips/bcm63xx/timer.c:
> + * Copyright (C) 2008 Maxime Bizon
> + *
> + * Registers for SoCs with 4 timers: BCM6345, BCM6328, BCM6362, BCM6816,
> + * BCM68220,BCM63168, BCM63268
> + * 0x02: IRQ enable (u8)
> + * 0x03: IRQ status (u8)
> + * 0x04: Timer 0 control
> + * 0x08: Timer 1 control
> + * 0x0c: Timer 2 control
> + * 0x10: Timer 0 count
> + * 0x14: Timer 1 count
> + * 0x18: Timer 2 count
> + * 0x1c+: Watchdog registers
> + *
> + * Registers for SoCs with 5 timers: BCM6318
> + * 0x00: IRQ enable (u32)
> + * 0x04: IRQ status (u32)
> + * 0x08: Timer 0 control
> + * 0x0c: Timer 1 control
> + * 0x10: Timer 2 control
> + * 0x14: Timer 3 control
> + * 0x18: Timer 0 count
> + * 0x1c: Timer 1 count
> + * 0x20: Timer 2 count
> + * 0x24: Timer 3 count
> + * 0x28+: Watchdog registers
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define REG_6345_IRQ_ENABLE 0x02
> +#define REG_6345_IRQ_STATUS 0x03
> +#define REG_6345_CONTROL_BASE0x04
> +#define REG_6345_COUNT_BASE 0x10
> +
> +#define REG_6318_IRQ_ENABLE 0x00
> +#define REG_6318_IRQ_STATUS 0x04
> +#define REG_6318_CONTROL_BASE0x08
> +#define REG_6318_COUNT_BASE 0x18
> +
> +#define NR_TIMERS_6345 4
> +#define WDT_TIMER_ID_6345(NR_TIMERS_6345 - 1)
> +
> +#define NR_TIMERS_6318 5
> +#define WDT_TIMER_ID_6318(NR_TIMERS_6318 - 1)
> +
> +/* Per-timer count register */
> +#define COUNT_MASK (0x3fff)
> +
> +/* Per-timer control register */
> +#define CONTROL_COUNTDOWN_MASK (0x3fff)
> +#define CONTROL_RSTCNTCLR_MASK (1 << 30)
> +#define CONTROL_ENABLE_MASK (1 << 31)
> +
> +enum bcm6345_timer_type {
> + TIMER_TYPE_6345,
> + TIMER_TYPE_6318,
> +};
> +
> +struct bcm6345_timer {
> + raw_spinlock_t lock;
> + void __io
Re: [PATCH (v4) 2/2] mtd: brcmnand: Add support for the BCM63268
On 24/11/15 00:12, Simon Arlott wrote: > On 23/11/15 18:22, Florian Fainelli wrote: >> On 22/11/15 14:17, Simon Arlott wrote: >>> The BCM63268 has a NAND interrupt register with combined status and enable >>> registers. It also has a clock for the NAND controller that needs to be >>> enabled. >>> >>> Set up the device by enabling the clock, disabling and acking all >>> interrupts, then handle the CTRL_READY interrupt. >>> >>> Add a "device_remove" function to struct brcmnand_soc so that the clock >>> can be disabled when the device is removed. >>> >>> Signed-off-by: Simon Arlott >>> --- >>> On 22/11/15 21:59, Rob Herring wrote: >>>>>>> + * "brcm,nand-bcm63268" >>>>>>> + - compatible: should contain "brcm,nand-bcm", >>>>>>> "brcm,nand-bcm63268" >>>>> >>>>> vendor,-device is preferred. >>> >>> The existing two bindings use brcm,nand-, but I've changed this one. >> >> Could we stick with the existing binding naming convention of using: >> >> brcm,nand- just so automated tools or other things can match this >> one too, and +1 for consistency? > > I could submit another patch renaming the existing bindings to > brcm,-nand, and add that to the drivers? Then they'd be consistent. No, let's not create unnecessary churn because of a minor mistake. So, yes we *should* have used brcm,-nand in the first place, but now that there are DTSes out there using "brcm,nand-" there is not really any point in doing this, so please update your patches so they match the existing convention. > >> Other than, that, same comment as Jonas, why do we we need the >> device_remove callback to be called from the main driver down to this one? > > I'll add a "struct brcmnand_soc *brcmnand_get_socdata(struct device *)" > instead so that I can access the soc data before calling brcmnand_remove. > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
On 29/10/15 18:23, Florian Fainelli wrote: > Add the ARM PLL controller which comes standard with the Cortex-A9 found > on the BCM63138 SoCs. This is the same controller as the one found in > the Broadcom iProc architecture, however, we have a separate compatible > string to indicate the integration difference, since the hardware is > different. > > Signed-off-by: Florian Fainelli Applied to devicetree/next with a merge commit of clk/clk-bcm63xx to resolve dependencies. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH (v4) 2/2] mtd: brcmnand: Add support for the BCM63268
On 22/11/15 14:17, Simon Arlott wrote: > The BCM63268 has a NAND interrupt register with combined status and enable > registers. It also has a clock for the NAND controller that needs to be > enabled. > > Set up the device by enabling the clock, disabling and acking all > interrupts, then handle the CTRL_READY interrupt. > > Add a "device_remove" function to struct brcmnand_soc so that the clock > can be disabled when the device is removed. > > Signed-off-by: Simon Arlott > --- > On 22/11/15 21:59, Rob Herring wrote: > + * "brcm,nand-bcm63268" > + - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm63268" >>> >>> vendor,-device is preferred. > > The existing two bindings use brcm,nand-, but I've changed this one. Could we stick with the existing binding naming convention of using: brcm,nand- just so automated tools or other things can match this one too, and +1 for consistency? Other than, that, same comment as Jonas, why do we we need the device_remove callback to be called from the main driver down to this one? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk
On 23/11/15 07:02, Jonas Gorski wrote: > Hi, > > On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott wrote: >> Instead of using a fixed clock HZ in the driver, obtain it from the >> "periph" clk that the watchdog timer uses. >> >> Signed-off-by: Simon Arlott >> --- >> drivers/watchdog/bcm63xx_wdt.c | 36 +++- >> 1 file changed, 31 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c >> index 1d2a501..eb5e551 100644 >> --- a/drivers/watchdog/bcm63xx_wdt.c >> +++ b/drivers/watchdog/bcm63xx_wdt.c >> @@ -13,6 +13,7 @@ >> >> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt >> >> +#include >> #include >> #include >> #include >> @@ -32,11 +33,13 @@ >> >> #define PFX KBUILD_MODNAME >> >> -#define WDT_HZ 5000/* Fclk */ >> +#define WDT_CLK_NAME "periph" > > @Florian: > Is this correct? The comment for the watchdog in 6358_map_part.h and > earlier claims that the clock is 40 MHz there, but the code uses 50MHz > - is this a bug in the comments or is it a bug taken over from the > original broadcom code? I'm sure that the periph clock being 50 MHz > even on the older chips is correct, else we'd have noticed that in > serial output (where it's also used). There are references to a Fbus2 clock in documentation, but I could not find any actual documentation for its actual clock frequency, I would be surprised if this chip would have diverged from the previous and future ones and used a 40Mhz clock. 6345 started with a peripheral clock running at 50Mhz, and that is true for all chips since then AFAICT. I agree we would have noticed this with the UART or SPI controllers if that was not true, so probably a code glitch here... -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support
On 20/11/15 10:46, Stephen Boyd wrote: > On 11/19, Florian Fainelli wrote: >> On 19/11/15 17:00, Florian Fainelli wrote: >>> On 29/10/15 18:23, Florian Fainelli wrote: >>>> This patch series adds support for the Broadcom BCM63138 DSL SoCs >>>> clocking framework. >>>> >>>> Since the HW is identical to the one found in Broadcom iProc SoCs, but the >>>> integration is different (obviously), there is still a new compatible >>>> string >>>> introduced just in case we happen to find issues in the future. >>>> >>>> Stephen, could you stage the two patches in a clk-bcm63xx branch that I >>>> could >>>> later utilize while doing the arm-soc DT pull request? >>> >>> Stephen, can you queue the first two patches in a topic branch for me to >>> merge as part of the commit adding the DTS changes? >> >> Well, now that I look back at the changes, you can actually merge the >> two patches in clk-next, and the DTS changes can come in before or >> after, it does not really matter, this would not cause breakage or >> anything. Sorry for the noise. > > Really? I thought if the clk patches aren't there then the dts > change would cause some clocks to be orphaned. If that's ok with > you it's ok with me. Woah, I guess I was not thinking very clearly yesterday, yes, we need to bundle these changes together, so if you are still okay with the topic branch for me to include as a merge commit, that's fine with me as well. /me needs to think twice before typing. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks
On 20/11/15 07:17, Jon Mason wrote: > Changes in v3: > Tweaked the NSP entry names, per Ray Jui > > Changes in v2: > Rebased off of outstanding NSP DT patches and tweaked the entry names > per Ray Jui > > > This patch series adds device tree support for the Broadcom Northstar, > Northstar Plus, and Northstar 2 clocks. > > Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to > the inability to merge because of the driver dependencies. Those > necessary driver changes were merged into 4.4. All comments have been > addressed and it is ready to be pulled in. Patches 1-2 applied to devicetree/next Patch 3 applied to devicetree-arm64/next Thanks Jon! > > > Jon Mason (3): > ARM: dts: enable clock support for BCM5301X > ARM: dts: enable clock support for Broadcom NSP > ARM64: dts: enable clock support for Broadcom NS2 > > arch/arm/boot/dts/bcm-nsp.dtsi| 81 -- > arch/arm/boot/dts/bcm5301x.dtsi | 92 > +++ > arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +- > 3 files changed, 216 insertions(+), 37 deletions(-) > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support
On 19/11/15 17:00, Florian Fainelli wrote: > On 29/10/15 18:23, Florian Fainelli wrote: >> This patch series adds support for the Broadcom BCM63138 DSL SoCs >> clocking framework. >> >> Since the HW is identical to the one found in Broadcom iProc SoCs, but the >> integration is different (obviously), there is still a new compatible string >> introduced just in case we happen to find issues in the future. >> >> Stephen, could you stage the two patches in a clk-bcm63xx branch that I could >> later utilize while doing the arm-soc DT pull request? > > Stephen, can you queue the first two patches in a topic branch for me to > merge as part of the commit adding the DTS changes? Well, now that I look back at the changes, you can actually merge the two patches in clk-next, and the DTS changes can come in before or after, it does not really matter, this would not cause breakage or anything. Sorry for the noise. > > Thanks! > >> >> Thank you! >> >> Florian Fainelli (3): >> clk: iproc: Extend binding to cover BCM63138 >> clk: bcm: Add BCM63138 clock support >> ARM: dts: BCM63xx: Add ARMPLL device tree nodes >> >> .../bindings/clock/brcm,iproc-clocks.txt | 5 +++ >> arch/arm/boot/dts/bcm63138.dtsi| 36 >> +- >> drivers/clk/bcm/Kconfig| 10 ++ >> drivers/clk/bcm/Makefile | 1 + >> drivers/clk/bcm/clk-bcm63xx.c | 22 + >> 5 files changed, 66 insertions(+), 8 deletions(-) >> create mode 100644 drivers/clk/bcm/clk-bcm63xx.c >> > > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support
On 29/10/15 18:23, Florian Fainelli wrote: > This patch series adds support for the Broadcom BCM63138 DSL SoCs > clocking framework. > > Since the HW is identical to the one found in Broadcom iProc SoCs, but the > integration is different (obviously), there is still a new compatible string > introduced just in case we happen to find issues in the future. > > Stephen, could you stage the two patches in a clk-bcm63xx branch that I could > later utilize while doing the arm-soc DT pull request? Stephen, can you queue the first two patches in a topic branch for me to merge as part of the commit adding the DTS changes? Thanks! > > Thank you! > > Florian Fainelli (3): > clk: iproc: Extend binding to cover BCM63138 > clk: bcm: Add BCM63138 clock support > ARM: dts: BCM63xx: Add ARMPLL device tree nodes > > .../bindings/clock/brcm,iproc-clocks.txt | 5 +++ > arch/arm/boot/dts/bcm63138.dtsi| 36 > +- > drivers/clk/bcm/Kconfig| 10 ++ > drivers/clk/bcm/Makefile | 1 + > drivers/clk/bcm/clk-bcm63xx.c | 22 + > 5 files changed, 66 insertions(+), 8 deletions(-) > create mode 100644 drivers/clk/bcm/clk-bcm63xx.c > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] ARM: dts: NSP: clean-ups and I2C support
On 17/11/15 11:55, Jon Mason wrote: > > Minor changes to the Broadcom Northstar Plus device tree to make it more > organized and clean, and adding I2C support (device tree only change > needed for support). Series applied, thanks Jon! > > > Jon Mason (2): > ARM: dts: NSP: Device Tree clean-ups > ARM: dts: NSP: Add I2C support to the DT > > arch/arm/boot/dts/bcm-nsp.dtsi | 59 > -- > 1 file changed, 34 insertions(+), 25 deletions(-) > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM64: dts: enable clock support for Broadcom NS2
On 18/11/15 16:03, Ray Jui wrote:
>
>
> On 11/18/2015 3:13 PM, Jon Mason wrote:
>> Add device tree entries for clock support for Broadcom Northstar 2 SoC
>>
>> Signed-off-by: Jon Mason
>> ---
>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 80
>> ++-
>> 1 file changed, 79 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> index 9610822..a510d3a 100644
>> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> @@ -31,6 +31,7 @@
>>*/
>>
>> #include
>> +#include
>>
>> /memreserve/ 0x84b0 0x0008;
>>
>> @@ -109,6 +110,33 @@
>><&A57_3>;
>> };
>>
>> +clocks {
>
> Is this a new convention? That is, group all clocks without a base
> register address in a node named "clocks", but at the same time, put all
> other clocks with base register address under a bus node.
I do not think that is new, lots of platforms do that. The clock
providers/controllers would typically be in the 'bus' nodes because it
has a register interface, while the synthetic clocks would be under
'clocks'.
--
Florian
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Re: [PATCH 03/11] dts: pinctrl: Add GPIO to Pinctrl pin mapping in DT
On 18/10/15 22:43, Pramod Kumar wrote: > ASIU gpio controller's pins are muxed with pin-cntroller. > Add this mapping through property "gpio-ranges". > > Signed-off-by: Pramod Kumar > Reviewed-by: Ray Jui > Reviewed-by: Scott Branden Applied to devicetree/next, since there was a bit of restructuring, I had to manually apply it, please verify the resolution looks correct to you. Thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [v4 00/10] add support SATA for BMIPS_GENERIC
On 30/10/15 07:01, Jaedon Shin wrote:
> Hi all,
>
> This patch series add support SATA for BMIPS_GENERIC.
Sorry for the lag.
Tested on 7425b2, there is a small mistake in the interrupt number for
the AHCI controller in the 7425.dtsi file (40 -> 41, see below), after
fixing that, I get both drives (external and internal ports) to be
identified successfully:
# dmesg | grep scsi
<6>[0.964097] scsi host0: brcm-ahci
<6>[0.967982] scsi host1: brcm-ahci
<5>[1.122386] scsi 0:0:0:0: Direct-Access ATA WDC
WD2500AAKX-7 1H19 PQ: 0 ANSI: 5
<5>[1.124512] sd 0:0:0:0: Attached scsi generic sg0 type 0
<5>[1.411546] scsi 1:0:0:0: Direct-Access ATA WDC
WD2500AAKX-7 1H19 PQ: 0 ANSI: 5
<5>[1.428870] sd 1:0:0:0: Attached scsi generic sg1 type 0
#
And performance looks good:
# hdparm -tT /dev/sda
/dev/sda:
[ 48.557068] random: nonblocking pool is initialized
Timing buffer-cache reads: 524 MB in 0.50 seconds = 1052111 kB/s
Timing buffered disk reads: 358 MB in 3.00 seconds = 122132 kB/s
# hdparm -tT /dev/sdb
/dev/sdb:
Timing buffer-cache reads: 528 MB in 0.50 seconds = 1060559 kB/s
Timing buffered disk reads: 374 MB in 3.00 seconds = 127496 kB/s
Tested-by: Florian Fainelli
For interrupt numbers, computing them from the HIF_CPU_INTR1 register
works like this this:
HW IRQ# = N * 32 + M
where N ranges from 0->2 and M is the bit within the 32-bits word.
Thanks!
>
> Changes in v4:
> - remove unused properties from bcm{7425,7342,7362}.dtsi
>
> Changes in v3:
> - fix typo quirk instead of quick
> - disable NCQ before initialzing SATA controller endianness
> - fix misnomer controlling phy interface
> - remove brcm,broken-ncq and brcm,broken-phy properties from devicetree
> - use compatible string for quirks
> - use list for compatible strings
> - add "Acked-by:" tags
>
> Changes in v2:
> - adds quirk for ncq
> - adds quirk for phy interface control
> - remove unused definitions in ahci_brcmstb
> - combines compatible string
>
> Jaedon Shin (10):
> ata: ahci_brcmstb: add support MIPS-based platforms
> ata: ahci_brcmstb: add quirk for broken ncq
> ata: ahci_brcmstb: add quirk for different phy
> ata: ahci_brcmstb: remove unused definitions
> phy: phy_brcmstb_sata: remove duplicate definitions
> phy: phy_brcmstb_sata: add data for phy version
> phy: phy_brcmstb_sata: add support MIPS-based platforms
> MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7425
> MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7346
> MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7362
>
> .../devicetree/bindings/ata/brcm,sata-brcmstb.txt | 4 +-
> .../bindings/phy/brcm,brcmstb-sata-phy.txt | 1 +
> arch/mips/boot/dts/brcm/bcm7346.dtsi | 40 +++
> arch/mips/boot/dts/brcm/bcm7362.dtsi | 40 +++
> arch/mips/boot/dts/brcm/bcm7425.dtsi | 40 +++
> arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 8 +++
> arch/mips/boot/dts/brcm/bcm97362svmb.dts | 8 +++
> drivers/ata/Kconfig| 2 +-
> drivers/ata/ahci_brcmstb.c | 58
> +-
> drivers/phy/Kconfig| 4 +-
> drivers/phy/phy-brcmstb-sata.c | 47 ++
> 11 files changed, 236 insertions(+), 16 deletions(-)
>
--
Florian
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Re: [PATCH RESEND v2 3/4] ARM: BCM: Add SMP support for Broadcom NSP
2015-11-09 2:09 GMT-08:00 Linus Walleij :
> On Fri, Nov 6, 2015 at 8:49 PM, Kapil Hali wrote:
>
>> Add SMP support for Broadcom's Northstar Plus SoC
>> cpu enable method. This changes also consolidates
>> iProc family's - BCM NSP and BCM Kona, platform
>> SMP handling in a common file.
>>
>> Northstar Plus SoC is based on ARM Cortex-A9
>> revision r3p0 which requires configuration for ARM
>> Errata 764369 for SMP. This change adds the needed
>> configuration option.
>>
>> Signed-off-by: Kapil Hali
>
> This version looks saner to me.
>
>> +static int nsp_write_lut(void)
>> +{
>> + void __iomem *sku_rom_lut;
>> + phys_addr_t secondary_startup_phy;
>> +
>> + if (!secondary_boot) {
>> + pr_warn("required secondary boot register not specified\n");
>> + return -EINVAL;
>> + }
>> +
>> + sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
>> + sizeof(secondary_boot));
>
> Why is this address not just taken directly from the device tree?
It comes directly from DT, that's what bcm_smp_prepare_cpus() does
read from Device Tree.
>
> If it is not in the device tree: why?
>
> Also give it a sane name, bcm_sec_boot_address or so.
> "secondary_boot" sounds like a function you call to boot
> the second core.
Agree with that, there could be a better name which better reflects
this is a variable.
--
Florian
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Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP
2015-11-08 9:31 GMT-08:00 Russell King - ARM Linux : >> Is it really how the ROM code is implemented, as a pen holding/release >> mechanism (which sounds like how this was implemented previously in the >> kernel actually) or should this be described in a more generic way as >> the physical address of the register where the secondary CPUs reset >> vector address must be written to? Or something along these lines. > > Why do people insist on using holding pens to bring their secondary CPUs > into existence? I hope the hardware people aren't being dumb and have no > way to hold in reset or power down their secondary CPUs, either of which > is a vital feature for things like kexec and the like. If they do have > a way to hold secondary CPUs in reset or powered down, why aren't they > using that at boot instead of implementing the stupid Versatile scheme, > which exists because Versatile _can't_ hold its CPUs in reset or power > them down... There are few implementations out there which suffer from this same mistake (mostly MIPS implementations) but that is not really relevant here. Most of the time this comes from not understanding software models and/or not properly taking into account a complex (too complex) reset model. > > It's times like this that I wonder what kind of drugs the hardware SoC > people are on, but I'm well aware that people contributing SMP bringup > solutions are also dumb idiots who copy the Versatile scheme with very > little thought... (as you can see, I'm not mincing my words here - if > people want to be lazy in this regard despite this having been brought > up multiple times, and the lead developers having said that the versatile > pen_release stuff should not be used, they earn themselves the right to > be called dumb idiots. Simple solution to avoid that title: don't be a > dumb idiot by copy the Versatile SMP bring up code! It's not a sane > model for any SoC sane SoC to follow.) > > Is this clear enough? The actual implementation of the SMP code in the next patches do not use a pen holding/release mechanism anymore as it used in the previous iterations of these same patches, so I would say, lesson learned. My question was whether the binding was documenting the hardware implementation (which it should) or the software implementation (which it should not). -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP
Le 06/11/2015 13:11, Kapil Hali a écrit :
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali
> ---
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36
> ++
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> 2 files changed, 37 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git
> a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +-
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> + - enable-method = "brcm,bcm-nsp-smp";
> + - secondary-boot-reg = <...>;
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.
Is it really how the ROM code is implemented, as a pen holding/release
mechanism (which sounds like how this was implemented previously in the
kernel actually) or should this be described in a more generic way as
the physical address of the register where the secondary CPUs reset
vector address must be written to? Or something along these lines.
> +
> +Example:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "brcm,bcm-nsp-smp";
Just a nit, but if NSP and NS are sharing the same mechanism, would not
a more "NS-centric" property be more appropriate because NS came before NSP?
> + secondary-boot-reg = <0x042c>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <1>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
> b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described
> below.
> "allwinner,sun8i-a23"
> "arm,psci"
> "brcm,brahma-b15"
> + "brcm,bcm-nsp-smp"
> "marvell,armada-375-smp"
> "marvell,armada-380-smp"
> "marvell,armada-390-smp"
>
--
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Re: [PATCH RESEND v2 3/4] ARM: BCM: Add SMP support for Broadcom NSP
On 06/11/15 11:57, Florian Fainelli wrote:
> On 06/11/15 11:49, Kapil Hali wrote:
>> Add SMP support for Broadcom's Northstar Plus SoC
>> cpu enable method. This changes also consolidates
>> iProc family's - BCM NSP and BCM Kona, platform
>> SMP handling in a common file.
>>
>> Northstar Plus SoC is based on ARM Cortex-A9
>> revision r3p0 which requires configuration for ARM
>> Errata 764369 for SMP. This change adds the needed
>> configuration option.
>>
>> Signed-off-by: Kapil Hali
>> ---
>
> Technically, this is not quite a RESEND, using the same git format-patch
> --subject command as before maybe?
>
> [snip]
>
>> +#ifndef __BCM_NSP_H
>> +#define __BCM_NSP_H
>> +
>> +extern void nsp_secondary_startup(void);
>
> This does not appear to be needed anymore since you use the standard
> secondary_boot entry point now.
>
>> +
>> +#endif /* __BCM_NSP_H */
>> diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
>> similarity index 75%
>> rename from arch/arm/mach-bcm/kona_smp.c
>> rename to arch/arm/mach-bcm/platsmp.c
>> index 66a0465..925402f 100644
>> --- a/arch/arm/mach-bcm/kona_smp.c
>> +++ b/arch/arm/mach-bcm/platsmp.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * Copyright (C) 2014 Broadcom Corporation
>> + * Copyright (C) 2014-2015 Broadcom Corporation
>> * Copyright 2014 Linaro Limited
>> *
>> * This program is free software; you can redistribute it and/or
>> @@ -12,16 +12,23 @@
>> * GNU General Public License for more details.
>> */
>>
>> -#include
>> +#include
>> +#include
>> #include
>> +#include
>> #include
>> +#include
>> #include
>> #include
>> +#include
>>
>> +#include
>> #include
>> #include
>> #include
>>
>> +#include "bcm_nsp.h"
>
> Likewise.
>
>> +
>> /* Size of mapped Cortex A9 SCU address space */
>> #define CORTEX_A9_SCU_SIZE 0x58
>>
>> @@ -75,6 +82,37 @@ static int __init scu_a9_enable(void)
>> return 0;
>> }
>>
>> +static int nsp_write_lut(void)
>> +{
>> +void __iomem *sku_rom_lut;
>> +phys_addr_t secondary_startup_phy;
>> +
>> +if (!secondary_boot) {
>> +pr_warn("required secondary boot register not specified\n");
>> +return -EINVAL;
>> +}
>> +
>> +sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
>> +sizeof(secondary_boot));
>
> That looks weird to me, are not you intending to get a virtual mapping
> of the SKU ROM LUT base register address here? What would
> sizeof(function) return here?
secondary_boot != secondary_startup, I read it wrong, this is fine.
--
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Re: [PATCH RESEND v2 3/4] ARM: BCM: Add SMP support for Broadcom NSP
On 06/11/15 11:49, Kapil Hali wrote:
> Add SMP support for Broadcom's Northstar Plus SoC
> cpu enable method. This changes also consolidates
> iProc family's - BCM NSP and BCM Kona, platform
> SMP handling in a common file.
>
> Northstar Plus SoC is based on ARM Cortex-A9
> revision r3p0 which requires configuration for ARM
> Errata 764369 for SMP. This change adds the needed
> configuration option.
>
> Signed-off-by: Kapil Hali
> ---
Technically, this is not quite a RESEND, using the same git format-patch
--subject command as before maybe?
[snip]
> +#ifndef __BCM_NSP_H
> +#define __BCM_NSP_H
> +
> +extern void nsp_secondary_startup(void);
This does not appear to be needed anymore since you use the standard
secondary_boot entry point now.
> +
> +#endif /* __BCM_NSP_H */
> diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
> similarity index 75%
> rename from arch/arm/mach-bcm/kona_smp.c
> rename to arch/arm/mach-bcm/platsmp.c
> index 66a0465..925402f 100644
> --- a/arch/arm/mach-bcm/kona_smp.c
> +++ b/arch/arm/mach-bcm/platsmp.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2014 Broadcom Corporation
> + * Copyright (C) 2014-2015 Broadcom Corporation
> * Copyright 2014 Linaro Limited
> *
> * This program is free software; you can redistribute it and/or
> @@ -12,16 +12,23 @@
> * GNU General Public License for more details.
> */
>
> -#include
> +#include
> +#include
> #include
> +#include
> #include
> +#include
> #include
> #include
> +#include
>
> +#include
> #include
> #include
> #include
>
> +#include "bcm_nsp.h"
Likewise.
> +
> /* Size of mapped Cortex A9 SCU address space */
> #define CORTEX_A9_SCU_SIZE 0x58
>
> @@ -75,6 +82,37 @@ static int __init scu_a9_enable(void)
> return 0;
> }
>
> +static int nsp_write_lut(void)
> +{
> + void __iomem *sku_rom_lut;
> + phys_addr_t secondary_startup_phy;
> +
> + if (!secondary_boot) {
> + pr_warn("required secondary boot register not specified\n");
> + return -EINVAL;
> + }
> +
> + sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
> + sizeof(secondary_boot));
That looks weird to me, are not you intending to get a virtual mapping
of the SKU ROM LUT base register address here? What would
sizeof(function) return here?
> + if (!sku_rom_lut) {
> + pr_warn("unable to ioremap SKU-ROM LUT register\n");
> + return -ENOMEM;
> + }
> +
> + secondary_startup_phy = virt_to_phys(secondary_startup);
> + BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
> +
> + writel_relaxed(secondary_startup_phy, sku_rom_lut);
> + /*
> + * Ensure the write is visible to the secondary core.
> + */
> + smp_wmb();
> +
> + iounmap(sku_rom_lut);
> +
> + return 0;
> +}
> +
> static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
> {
> static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
> @@ -95,11 +133,11 @@ static void __init bcm_smp_prepare_cpus(unsigned int
> max_cpus)
> /*
>* Our secondary enable method requires a "secondary-boot-reg"
>* property to specify a register address used to request the
> - * ROM code boot a secondary code. If we have any trouble
> + * ROM code boot a secondary core. If we have any trouble
>* getting this we fall back to uniprocessor mode.
>*/
> if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
> - pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
> + pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
> node->name);
> ret = -ENOENT; /* Arrange to disable SMP */
> goto out;
> @@ -115,7 +153,6 @@ out:
> of_node_put(node);
> if (ret) {
> /* Update the CPU present map to reflect uniprocessor mode */
> - BUG_ON(ret != -ENOENT);
> pr_warn("disabling SMP\n");
> init_cpu_present(&only_cpu_0);
> }
> @@ -139,7 +176,7 @@ out:
> * - Wait for the secondary boot register to be re-written, which
> * indicates the secondary core has started.
> */
> -static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> void __iomem *boot_reg;
> phys_addr_t boot_func;
> @@ -162,7 +199,7 @@ static int bcm_boot_secondary(unsigned int cpu, struct
> task_struct *idle)
> boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
> if (!boot_reg) {
> pr_err("unable to map boot register for cpu %u\n", cpu_id);
> - return -ENOSYS;
> + return -ENOMEM;
> }
>
> /*
> @@ -191,12 +228,42 @@ static int bcm_boot_secondary(unsigned int cpu, struct
> task_struct *idle)
>
> pr_err("timeout waiting for cpu
Re: [PATCH RESEND v4 0/2] ARM: dts: bcm5301x: Add SVK DT files and docs
On 02/11/15 10:34, Jon Mason wrote: > Resending due to lack of any response to the original v4 series > > Changes in v4: > * Changed bootargs to stdout-path, per Sudeep Holla > > Changes in v3: > * Updated the DT documentation compat strings > * Modified the include files and compat strings for the SVK DT files, > per Hauke Mehrtens > > Changes in v2: > * Reorder the patches to add the DT binding documentation prior to the > new DT files > * Removed the DT documentation compat strings to only the SoCs, not the > individual boards > * Fixed the compat strings in the individual device tree files > * Added the memory node and removed the "mem=" from the bootargs Series applied to devicetree/next, thanks Jon! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND 0/3] ARM: dts: NSP: Add PCI, NAND, and TWD Support to DT
On 02/11/15 10:40, Jon Mason wrote: > Resending due to lack of any response to the original series > > Add PCI, NAND, and TWD Support to the Broadcom Northstar Plus SoC device > tree file. Since no driver changes are needed to enable these pieces of > hardware, only the device tree changes are required to make them > functional. Series applied to devicetree/next, thanks Jon! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/3] clk: bcm: Add BCM63138 clock support
BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.
Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.
Signed-off-by: Florian Fainelli
---
No changes in v4
Changes in v3:
- made default depend on ARCH_BCM_63XX per Stephen Boyd's comment
Changes in v2:
- added COMPILE_TEST per Scott Branden's comment
drivers/clk/bcm/Kconfig | 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22 ++
3 files changed, 33 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb96b36..f2878459199a 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -1,3 +1,13 @@
+config CLK_BCM_63XX
+ bool "Broadcom BCM63xx clock support"
+ depends on ARCH_BCM_63XX || COMPILE_TEST
+ depends on COMMON_CLK
+ select COMMON_CLK_IPROC
+ default ARCH_BCM_63XX
+ help
+ Enable common clock framework support for Broadcom BCM63xx DSL SoCs
+ based on the ARM architecture
+
config CLK_BCM_KONA
bool "Broadcom Kona CCU clock support"
depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc95060d875..247c26750d8b 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index ..fbc17ae5ff2b
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include "clk-iproc.h"
+
+static void __init bcm63138_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
--
2.1.0
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[PATCH v4 0/3] clk: Broadcom BCM63138 support
This patch series adds support for the Broadcom BCM63138 DSL SoCs clocking framework. Since the HW is identical to the one found in Broadcom iProc SoCs, but the integration is different (obviously), there is still a new compatible string introduced just in case we happen to find issues in the future. Stephen, could you stage the two patches in a clk-bcm63xx branch that I could later utilize while doing the arm-soc DT pull request? Thank you! Florian Fainelli (3): clk: iproc: Extend binding to cover BCM63138 clk: bcm: Add BCM63138 clock support ARM: dts: BCM63xx: Add ARMPLL device tree nodes .../bindings/clock/brcm,iproc-clocks.txt | 5 +++ arch/arm/boot/dts/bcm63138.dtsi| 36 +- drivers/clk/bcm/Kconfig| 10 ++ drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-bcm63xx.c | 22 + 5 files changed, 66 insertions(+), 8 deletions(-) create mode 100644 drivers/clk/bcm/clk-bcm63xx.c -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
Add the ARM PLL controller which comes standard with the Cortex-A9 found
on the BCM63138 SoCs. This is the same controller as the one found in
the Broadcom iProc architecture, however, we have a separate compatible
string to indicate the integration difference, since the hardware is
different.
Signed-off-by: Florian Fainelli
---
Changes in v4:
- properly reflect the HW clocking and make it clear that periph_clk
is feeding into the ARM PLL clock domain
No changes in v2 or v3
arch/arm/boot/dts/bcm63138.dtsi | 36
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 34cd64051250..d0560e8cd6de 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -43,18 +43,31 @@
#address-cells = <1>;
#size-cells = <0>;
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <5>;
- };
-
+ /* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <5000>;
clock-output-names = "periph";
};
+
+ /* peripheral clock for system timer */
+ axi_clk: axi_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /* APB bus clock */
+ apb_clk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
};
/* ARM bus */
@@ -93,14 +106,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
@@ -109,6 +122,13 @@
interrupts = ;
};
+ armpll: armpll {
+ #clock-cells = <0>;
+ compatible = "brcm,bcm63138-armpll";
+ clocks = <&periph_clk>;
+ reg = <0x2 0xf00>;
+ };
+
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
--
2.1.0
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[PATCH v4 1/3] clk: iproc: Extend binding to cover BCM63138
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure as the Cygnus and iProc chips, add a dedicated compatible string and document that the ARMPLL node is a valid node for this chip. Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- No changes in v4 Changes in v3: - added Rob's Acked-by tag No changes in v2 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index ede65a55e21b..0b35e71b39e8 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -208,3 +208,8 @@ These clock IDs are defined in: ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + +BCM63138 + +PLL and leaf clock compatible strings for BCM63138 are: +"brcm,bcm63138-armpll" -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
On 27/10/15 16:56, Florian Fainelli wrote:
> Add the ARM PLL controller which comes standard with the Cortex-A9 found
> on the BCM63138 SoCs. This is the same controller as the one found in
> the Broadcom iProc architecture, however, we have a separate compatible
> string to indicate the integration difference.
>
> While at it, properly rename references to the 50Mhz clock which is in
> fact a crystal/oscillator and updates references to it.
The periph_clk is actually the correct one, and is different from the
oscillator, I will resubmit these patches shortly to better match the
chip clocking.
>
> Signed-off-by: Florian Fainelli
> ---
> No changes in v2 or v3
>
> arch/arm/boot/dts/bcm63138.dtsi | 39 +--
> 1 file changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
> index 34cd64051250..c146325eebdb 100644
> --- a/arch/arm/boot/dts/bcm63138.dtsi
> +++ b/arch/arm/boot/dts/bcm63138.dtsi
> @@ -43,17 +43,29 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - arm_timer_clk: arm_timer_clk {
> + osc: oscillator {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <5>;
> + clock-frequency = <5000>;
> + clock-output-names = "periph";
> };
>
> - periph_clk: periph_clk {
> + /* peripheral clock for system timer */
> + axi_clk: axi_clk {
> #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <5000>;
> - clock-output-names = "periph";
> + compatible = "fixed-factor-clock";
> + clocks = <&armpll>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + /* APB bus clock */
> + apb_clk: apb_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clocks = <&armpll>;
> + clock-div = <4>;
> + clock-mult = <1>;
> };
> };
>
> @@ -93,14 +105,14 @@
> compatible = "arm,cortex-a9-global-timer";
> reg = <0x1e200 0x20>;
> interrupts = ;
> - clocks = <&arm_timer_clk>;
> + clocks = <&axi_clk>;
> };
>
> local_timer: local-timer@1e600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0x1e600 0x20>;
> interrupts = ;
> - clocks = <&arm_timer_clk>;
> + clocks = <&axi_clk>;
> };
>
> twd_watchdog: watchdog@1e620 {
> @@ -109,6 +121,13 @@
> interrupts = ;
> };
>
> + armpll: armpll {
> + #clock-cells = <0>;
> + compatible = "brcm,bcm63138-armpll";
> + clocks = <&osc>;
> + reg = <0x2 0xf00>;
> + };
> +
> pmb0: reset-controller@4800c0 {
> compatible = "brcm,bcm63138-pmb";
> reg = <0x4800c0 0x10>;
> @@ -138,7 +157,7 @@
> compatible = "brcm,bcm6345-uart";
> reg = <0x600 0x1b>;
> interrupts = ;
> - clocks = <&periph_clk>;
> + clocks = <&osc>;
> clock-names = "periph";
> status = "disabled";
> };
> @@ -147,7 +166,7 @@
> compatible = "brcm,bcm6345-uart";
> reg = <0x620 0x1b>;
> interrupts = ;
> - clocks = <&periph_clk>;
> + clocks = <&osc>;
> clock-names = "periph";
> status = "disabled";
> };
>
--
Florian
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Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for NS2
On 28/10/15 09:08, Ray Jui wrote:
>
>
> On 10/28/2015 2:06 AM, Anup Patel wrote:
>>
>>
>>> -Original Message-
>>> From: Ray Jui [mailto:r...@broadcom.com]
>>> Sent: 28 October 2015 06:17
>>> To: Brian Norris
>>> Cc: Anup Patel; David Woodhouse; Linux MTD; Rob Herring; Pawel Moll;
>>> Mark
>>> Rutland; Catalin Marinas; Will Deacon; Sudeep Holla; Ian Campbell;
>>> Kumar Gala;
>>> Scott Branden; Florian Fainelli; Pramod Kumar; Vikram Prakash; Sandeep
>>> Tripathy; Linux ARM Kernel; Device Tree; Linux Kernel;
>>> bcm-kernel-feedback-list
>>> Subject: Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for
>>> NS2
>>>
>>>
>>>
>>> On 10/27/2015 5:39 PM, Brian Norris wrote:
>>>> On Tue, Oct 27, 2015 at 05:25:32PM -0700, Ray Jui wrote:
>>>>> On 10/27/2015 5:19 PM, Brian Norris wrote:
>>>>>> On Fri, Oct 23, 2015 at 10:46:13AM +0530, Anup Patel wrote:
>>>>>>> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>>>>>>> b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>>>>>>> index f603277..9610822 100644
>>>>>>> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>>>>>>> @@ -212,5 +212,19 @@
>>>>>>>compatible = "brcm,iproc-rng200";
>>>>>>>reg = <0x6622 0x28>;
>>>>>>>};
>>>>>>> +
>>>>>>> +nand: nand@6646 {
>>>>>>> +compatible = "brcm,nand-iproc", "brcm,brcmnand-
>>> v6.1";
>>>>>>
>>>>>> Technically, the binding says you should also have "brcm,brcmnand"
>>>>>> as a last resort. Otherwise (for the NAND parts):
>>>>>>
>>>>>
>>>>> I believe Anup was seeing issues when both "brcm,nand-iproc" and
>>>>> "brcm,brcmnand" are present.
>>>>>
>>>>> Note "brcm,nand-iproc" invokes 'iproc_nand_probe', which calls
>>>>> 'brcmnand_probe' in the end.
>>>>>
>>>>> "brcm,brcmnand" invokes 'brcmstb_nand_probe', which also calls
>>>>> 'brcmstb_probe', but without all the prep configuration required for
>>>>> "brcm,nand-iproc".
>>>>
>>>> Ah, I forgot about that problem. That seems like an OF infrastructure
>>>> issue that could be fixed. We could lump these drivers back together,
>>>> and make sure that "brcm,nand-iproc" gets the priority in the
>>>> of_device_id list.
>>>>
>>>> Or we could just relax the DT binding.
>>>>
>>>> But wait, wouldn't cygnus already have that problem? You're using the
>>>> binding I suggested in arch/arm/boot/dts/bcm-cygnus.dtsi.
>>>
>>> Interestingly, we do not see this problem with Cygnus or NSP, but
>>> only on NS2
>>> (arm64 based). There may be a difference between how OF devices are
>>> instantiated between arm and arm64?
>>
>> Alternately, it could be also about order in-which platform drivers
>> are matched
>> for newly created OF device.
>>
>>>
>>>>
>>>> Oh, and I see we hacked this one in drivers/mtd/nand/brcmnand/Makefile:
>>>>
>>>> # link order matters; don't link the more generic brcmstb_nand.o
>>>> before the
>>>> # more specific iproc_nand.o, for instance
>>>
>>> Yes, I see that too (after sending out my previous email, :)). Maybe
>>> Anup can help to elaborate on the problem. I'm now getting a bit
>>> confused on how the problem can surface on NS2.
>>
>> I think for a newly created OF devices the Linux device driver
>> framework will
>> match the platform drivers in the order in which they are registered
>> by module
>> init functions. Now the order of module init function calls will be
>> based how
>> the .initcall section is formed by linker and order in which objects
>> are linked.
>>
>
> Yes, what you said is my understanding as well, but then here is the
> mystery. This is the link order in brcmnand/Makefile:
>
> 1 # link order matters; don't link the more generic brcmstb_nand.o
> before the
> 2 # more specific iproc
[PATCH v3 2/3] clk: bcm: Add BCM63138 clock support
BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.
Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.
Signed-off-by: Florian Fainelli
---
Changes in v3:
- made default depend on ARCH_BCM_63XX per Stephen Boyd's comment
Changes in v2:
- added COMPILE_TEST per Scott Branden's comment
drivers/clk/bcm/Kconfig | 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22 ++
3 files changed, 33 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb96b36..f2878459199a 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -1,3 +1,13 @@
+config CLK_BCM_63XX
+ bool "Broadcom BCM63xx clock support"
+ depends on ARCH_BCM_63XX || COMPILE_TEST
+ depends on COMMON_CLK
+ select COMMON_CLK_IPROC
+ default ARCH_BCM_63XX
+ help
+ Enable common clock framework support for Broadcom BCM63xx DSL SoCs
+ based on the ARM architecture
+
config CLK_BCM_KONA
bool "Broadcom Kona CCU clock support"
depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc95060d875..247c26750d8b 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index ..fbc17ae5ff2b
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include "clk-iproc.h"
+
+static void __init bcm63138_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
--
2.1.0
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[PATCH v3 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
Add the ARM PLL controller which comes standard with the Cortex-A9 found
on the BCM63138 SoCs. This is the same controller as the one found in
the Broadcom iProc architecture, however, we have a separate compatible
string to indicate the integration difference.
While at it, properly rename references to the 50Mhz clock which is in
fact a crystal/oscillator and updates references to it.
Signed-off-by: Florian Fainelli
---
No changes in v2 or v3
arch/arm/boot/dts/bcm63138.dtsi | 39 +--
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 34cd64051250..c146325eebdb 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -43,17 +43,29 @@
#address-cells = <1>;
#size-cells = <0>;
- arm_timer_clk: arm_timer_clk {
+ osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <5>;
+ clock-frequency = <5000>;
+ clock-output-names = "periph";
};
- periph_clk: periph_clk {
+ /* peripheral clock for system timer */
+ axi_clk: axi_clk {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <5000>;
- clock-output-names = "periph";
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /* APB bus clock */
+ apb_clk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
};
@@ -93,14 +105,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
@@ -109,6 +121,13 @@
interrupts = ;
};
+ armpll: armpll {
+ #clock-cells = <0>;
+ compatible = "brcm,bcm63138-armpll";
+ clocks = <&osc>;
+ reg = <0x2 0xf00>;
+ };
+
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
@@ -138,7 +157,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
@@ -147,7 +166,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x620 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
--
2.1.0
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[PATCH v3 1/3] clk: iproc: Extend binding to cover BCM63138
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure as the Cygnus and iProc chips, add a dedicated compatible string and document that the ARMPLL node is a valid node for this chip. Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Changes in v3: - added Rob's Acked-by tag No changes in v2 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index ede65a55e21b..0b35e71b39e8 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -208,3 +208,8 @@ These clock IDs are defined in: ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + +BCM63138 + +PLL and leaf clock compatible strings for BCM63138 are: +"brcm,bcm63138-armpll" -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/3] clk: Broadcom BCM63138 support
Hi all,
This patch series adds support for the Broadcom BCM63138 DSL SoCs
clocking framework.
Since the HW is identical to the one found in Broadcom iProc SoCs, but the
integration is different (obviously), there is still a new compatible string
introduced just in case we happen to find issues in the future.
This applies on top of clk/next as of
679c51cffc3b316bd89ecc91ef92603dd6d4fc68 ("clk: Add stubs for of_clk_*() APIs
when CONFIG_OF=n")
Since there is an obvious dependency between patch 2 and 3, we can either
merge this through the Clock tree or via a future arm-soc pull requests
for Broadcom SoCs.
Florian Fainelli (3):
clk: iproc: Extend binding to cover BCM63138
clk: bcm: Add BCM63138 clock support
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
.../bindings/clock/brcm,iproc-clocks.txt | 5 +++
arch/arm/boot/dts/bcm63138.dtsi| 39 --
drivers/clk/bcm/Kconfig| 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22
5 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
--
2.1.0
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Re: [PATCH v2 0/3] clk: Broadcom BCM63138 support
On 27/10/15 14:08, Stephen Boyd wrote:
> On 10/26, Florian Fainelli wrote:
>> Hi all,
>>
>> This patch series adds support for the Broadcom BCM63138 DSL SoCs
>> clocking framework.
>>
>> Since the HW is identical to the one found in Broadcom iProc SoCs, but the
>> integration is different (obviously), there is still a new compatible string
>> introduced just in case we happen to find issues in the future.
>>
>> This applies on top of clk/next as of
>> 679c51cffc3b316bd89ecc91ef92603dd6d4fc68 ("clk: Add stubs for of_clk_*()
>> APIs when CONFIG_OF=n")
>>
>> Since there is an obvious dependency between patch 2 and 3, we can either
>> merge this through the Clock tree or via a future arm-soc pull requests
>> for Broadcom SoCs.
>
> One way to avoid the dependency would be to stage the first two
> patches in clk tree under clk-bcm63xxx and then pull that into
> your local branch via git FETCH && git checkout FETCH_HEAD and
> then apply the 3rd patch on top, tag it and send it off to
> arm-soc. This way, when arm-soc merges into linus' tree the
> dependency is taken care of and we don't take anything for dtsi
> files through the clk tree. It looks like nothing bad will happen
> if patch 2 is merged before patch 3.
Works for me, thanks!
--
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Re: [PATCH v2 2/3] clk: bcm: Add BCM63138 clock support
On 27/10/15 10:46, Stephen Boyd wrote: > On 10/26, Florian Fainelli wrote: >> diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig >> index 85260fb96b36..a0c18528b70d 100644 >> --- a/drivers/clk/bcm/Kconfig >> +++ b/drivers/clk/bcm/Kconfig >> @@ -1,3 +1,13 @@ >> +config CLK_BCM_63XX >> +bool "Broadcom BCM63xx clock support" >> +depends on ARCH_BCM_63XX || COMPILE_TEST >> +depends on COMMON_CLK >> +select COMMON_CLK_IPROC >> +default y > > perhaps default CLK_BCM_63XX? Did you mean default ARCH_BCM_63XX instead? > >> +help >> + Enable common clock framework support for Broadcom BCM63xx DSL SoCs >> + based on the ARM architecture >> + >> config CLK_BCM_KONA >> bool "Broadcom Kona CCU clock support" >> depends on ARCH_BCM_MOBILE || COMPILE_TEST >> diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c >> new file mode 100644 >> index ..b7e0469d0522 >> --- /dev/null >> +++ b/drivers/clk/bcm/clk-bcm63xx.c >> @@ -0,0 +1,22 @@ >> +/* >> + * Copyright (C) 2015 Broadcom Corporation >> + * >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation version 2. >> + * >> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any >> + * kind, whether express or implied; without even the implied warranty >> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> +#include >> +#include >> +#include > > #include ? > > I'm not sure what the kernel.h include is for. Nothing, init.h is what should be included instead. -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [v2 03/10] ata: ahci_brcmstb: add quick for broken phy
On 26/10/15 23:48, Jaedon Shin wrote:
> Add quick for broken phy. The ARM-based 28nm chipsets have four phy
> interface control registers and each port has two registers. But, The
> MIPS-based 40nm chipsets have three. and there are no information and
> documentation. The legacy version of broadcom's strict-ahci based
> initial code did not control these registers.
Qualifying this of a broken PHY is a misnomer, this is more about the
fact that the PHY control registers have a different layout and behavior
on 40nm vs 28nm chips, but more importantly, do not require any kind of
configuration.
>
> Signed-off-by: Jaedon Shin
> ---
> Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt | 1 +
> drivers/ata/ahci_brcmstb.c | 10 ++
> 2 files changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> index 488a383ce202..0f0925d58188 100644
> --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> @@ -12,6 +12,7 @@ Required properties:
>
> Optional properties:
> - brcm,broken-ncq: if present, NCQ is unusable
> +- brcm,broken-phy: if present, to control phy interface is unusable
Same comment as in patch 1, this is something that can be known based on
the compatible string, and the name of the property is misleading.
>
> Also see ahci-platform.txt.
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index e53962cb48ee..c61303f7c7dc 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -71,6 +71,7 @@
>
> enum brcm_ahci_quicks {
> BRCM_AHCI_QUICK_NONCQ = BIT(0),
> + BRCM_AHCI_QUICK_NOPHY = BIT(1),
I would use something like BRCM_AHCI_SKIP_PHY_ENABLE or something like
that to illustrate what this really is about.
> };
>
> struct brcm_ahci_priv {
> @@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv
> *priv, int port)
> void __iomem *p;
> u32 reg;
>
> + if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> + return;
> +
> /* clear PHY_DEFAULT_POWER_STATE */
> p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
> reg = brcm_sata_readreg(p);
> @@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv
> *priv, int port)
> void __iomem *p;
> u32 reg;
>
> + if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> + return;
> +
> /* power-off the PHY digital logic */
> p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
> reg = brcm_sata_readreg(p);
> @@ -297,6 +304,9 @@ static int brcm_ahci_probe(struct platform_device *pdev)
> if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
> priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
>
> + if (of_property_read_bool(dev->of_node, "brcm,broken-phy"))
> + priv->quicks |= BRCM_AHCI_QUICK_NOPHY;
> +
> brcm_sata_init(priv);
> brcm_sata_quick(pdev, priv);
>
>
--
Florian
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Re: [v2 01/10] ata: ahci_brcmstb: add quick for broken ncq
On 26/10/15 23:48, Jaedon Shin wrote:
> Add quick for bronken ncq. The chipsets (eg. BCM7439A0, BCM7445A0 and
> BCM7445B0) need a workaround disabling NCQ. and it may need the
> MIPS-based set-top box platforms.
None of these chips are production chips, so at this point, disabling
NCQ should be done based on the compatible string we probed the driver
with, not using a specific property.
There are more comments below
>
> Signed-off-by: Jaedon Shin
> ---
[snip]
>
> +static void brcm_sata_quick(struct platform_device *pdev,
> + struct brcm_ahci_priv *priv)
> +{
> + void __iomem *ahci;
> + struct resource *res;
> + u32 reg;
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
> + ahci = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(ahci))
> + return;
> +
> + if (priv->quicks & BRCM_AHCI_QUICK_NONCQ) {
> + reg = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> + reg |= OVERRIDE_HWINIT;
> + writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> +
> + /* Clear out the NCQ bit so the AHCI driver will not issue
> + * FPDMA/NCQ commands.
> + */
> + reg = readl(ahci + HOST_CAP);
> + reg &= ~HOST_CAP_NCQ;
> + writel(reg, ahci + HOST_CAP);
> +
> + reg = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> + reg &= ~OVERRIDE_HWINIT;
> + writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> + }
In the original BSP, the NCQ disabling occurs prior to initializing the
SATA controller endianess. We would want to keep doing that in the same
order, and use brcm_sata_readreg() and brcm_sata_writereg() which take
care of doing these accesses in the native endianess of the system.
Reference is here:
https://github.com/Broadcom/stblinux-3.3/blob/master/linux/drivers/brcmstb/bchip.c#L254
> +
> + devm_iounmap(&pdev->dev, ahci);
> + devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
> +}
> +
> #ifdef CONFIG_PM_SLEEP
> static int brcm_ahci_suspend(struct device *dev)
> {
> @@ -256,7 +294,11 @@ static int brcm_ahci_probe(struct platform_device *pdev)
> if (IS_ERR(priv->top_ctrl))
> return PTR_ERR(priv->top_ctrl);
>
> + if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
> + priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
> +
> brcm_sata_init(priv);
> + brcm_sata_quick(pdev, priv);
Florian
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[PATCH v2 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
Add the ARM PLL controller which comes standard with the Cortex-A9 found
on the BCM63138 SoCs. This is the same controller as the one found in
the Broadcom iProc architecture, however, we have a separate compatible
string to indicate the integration difference.
While at it, properly rename references to the 50Mhz clock which is in
fact a crystal/oscillator and updates references to it.
Signed-off-by: Florian Fainelli
---
No changes in v2
arch/arm/boot/dts/bcm63138.dtsi | 39 +--
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 34cd64051250..c146325eebdb 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -43,17 +43,29 @@
#address-cells = <1>;
#size-cells = <0>;
- arm_timer_clk: arm_timer_clk {
+ osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <5>;
+ clock-frequency = <5000>;
+ clock-output-names = "periph";
};
- periph_clk: periph_clk {
+ /* peripheral clock for system timer */
+ axi_clk: axi_clk {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <5000>;
- clock-output-names = "periph";
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /* APB bus clock */
+ apb_clk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
};
@@ -93,14 +105,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
@@ -109,6 +121,13 @@
interrupts = ;
};
+ armpll: armpll {
+ #clock-cells = <0>;
+ compatible = "brcm,bcm63138-armpll";
+ clocks = <&osc>;
+ reg = <0x2 0xf00>;
+ };
+
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
@@ -138,7 +157,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
@@ -147,7 +166,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x620 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
--
2.1.0
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[PATCH v2 2/3] clk: bcm: Add BCM63138 clock support
BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.
Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.
Signed-off-by: Florian Fainelli
---
Changes in v2:
- added COMPILE_TEST
drivers/clk/bcm/Kconfig | 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22 ++
3 files changed, 33 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb96b36..a0c18528b70d 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -1,3 +1,13 @@
+config CLK_BCM_63XX
+ bool "Broadcom BCM63xx clock support"
+ depends on ARCH_BCM_63XX || COMPILE_TEST
+ depends on COMMON_CLK
+ select COMMON_CLK_IPROC
+ default y
+ help
+ Enable common clock framework support for Broadcom BCM63xx DSL SoCs
+ based on the ARM architecture
+
config CLK_BCM_KONA
bool "Broadcom Kona CCU clock support"
depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc95060d875..247c26750d8b 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index ..b7e0469d0522
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include "clk-iproc.h"
+
+static void __init bcm63138_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
--
2.1.0
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[PATCH v2 0/3] clk: Broadcom BCM63138 support
Hi all,
This patch series adds support for the Broadcom BCM63138 DSL SoCs
clocking framework.
Since the HW is identical to the one found in Broadcom iProc SoCs, but the
integration is different (obviously), there is still a new compatible string
introduced just in case we happen to find issues in the future.
This applies on top of clk/next as of
679c51cffc3b316bd89ecc91ef92603dd6d4fc68 ("clk: Add stubs for of_clk_*() APIs
when CONFIG_OF=n")
Since there is an obvious dependency between patch 2 and 3, we can either
merge this through the Clock tree or via a future arm-soc pull requests
for Broadcom SoCs.
Florian Fainelli (3):
clk: iproc: Extend binding to cover BCM63138
clk: bcm: Add BCM63138 clock support
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
.../bindings/clock/brcm,iproc-clocks.txt | 5 +++
arch/arm/boot/dts/bcm63138.dtsi| 39 --
drivers/clk/bcm/Kconfig| 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22
5 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
--
2.1.0
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[PATCH v2 1/3] clk: iproc: Extend binding to cover BCM63138
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure as the Cygnus and iProc chips, add a dedicated compatible string and document that the ARMPLL node is a valid node for this chip. Signed-off-by: Florian Fainelli --- No changes in v2 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index ede65a55e21b..0b35e71b39e8 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -208,3 +208,8 @@ These clock IDs are defined in: ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + +BCM63138 + +PLL and leaf clock compatible strings for BCM63138 are: +"brcm,bcm63138-armpll" -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC
Le 23/10/2015 21:51, Jaedon Shin a écrit : > On Oct 23, 2015, at 1:51 PM, Florian Fainelli wrote: >> >> 2015-10-22 20:58 GMT-07:00 Tejun Heo : >>> On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote: >>>> Hi all, >>>> >>>> This patch series adds support SATA for BMIPS_GENERIC. >>>> >>>> Ralf, >>>> I request you to drop already submitted patches for NAND device nodes. >>>> It is merge conflicts with this patches. >>>> http://patchwork.linux-mips.org/patch/10577/ >>>> http://patchwork.linux-mips.org/patch/10578/ >>>> http://patchwork.linux-mips.org/patch/10579/ >>>> http://patchwork.linux-mips.org/patch/10580/ >>>> >>>> Jaedon Shin (10): >>>> ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC >>>> ata: ahch_brcmstb: add data for port offset >>>> ata: ahci_brcmstb: add support 40nm platforms >>> >>> ata part looks fine to me. Let me know when the other parts get in. >>> I'll apply the ata ones to libata/for-4.4. >> >> There are a few comments coming on the ATA and Device Tree part, and I >> also would like Brian Norris (who submitted the patches) to take a >> look at these. But overall, this looks great. >> >> I think we have a bit too many compatible strings defined, I need to >> lookup tomorrow when I am back in the office which BCM7xxx started >> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not >> sure >> > > I agree with you. If you have good opinion, I want you to tell me. Based on Kevin's feedback, we should be using 7425 as the compatible string for these AHCI controllers. Thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] clk: iproc: Extend binding to cover BCM63138
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure as the Cygnus and iProc chips, add a dedicated compatible string and document that the ARMPLL node is a valid node for this chip. Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index ede65a55e21b..0b35e71b39e8 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -208,3 +208,8 @@ These clock IDs are defined in: ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + +BCM63138 + +PLL and leaf clock compatible strings for BCM63138 are: +"brcm,bcm63138-armpll" -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: dts: BCM63xx: Add ARMPLL device tree nodes
Add the ARM PLL controller which comes standard with the Cortex-A9 found
on the BCM63138 SoCs. This is the same controller as the one found in
the Broadcom iProc architecture, however, we have a separate compatible
string to indicate the integration difference.
While at it, properly rename references to the 50Mhz clock which is in
fact a crystal/oscillator and updates references to it.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 39 +--
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 34cd64051250..c146325eebdb 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -43,17 +43,29 @@
#address-cells = <1>;
#size-cells = <0>;
- arm_timer_clk: arm_timer_clk {
+ osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <5>;
+ clock-frequency = <5000>;
+ clock-output-names = "periph";
};
- periph_clk: periph_clk {
+ /* peripheral clock for system timer */
+ axi_clk: axi_clk {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <5000>;
- clock-output-names = "periph";
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /* APB bus clock */
+ apb_clk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
};
@@ -93,14 +105,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = ;
- clocks = <&arm_timer_clk>;
+ clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
@@ -109,6 +121,13 @@
interrupts = ;
};
+ armpll: armpll {
+ #clock-cells = <0>;
+ compatible = "brcm,bcm63138-armpll";
+ clocks = <&osc>;
+ reg = <0x2 0xf00>;
+ };
+
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
@@ -138,7 +157,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
@@ -147,7 +166,7 @@
compatible = "brcm,bcm6345-uart";
reg = <0x620 0x1b>;
interrupts = ;
- clocks = <&periph_clk>;
+ clocks = <&osc>;
clock-names = "periph";
status = "disabled";
};
--
2.1.0
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[PATCH 2/3] clk: bcm: Add BCM63138 clock support
BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.
Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.
Signed-off-by: Florian Fainelli
---
drivers/clk/bcm/Kconfig | 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22 ++
3 files changed, 33 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb96b36..eb4daed6aa56 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -1,3 +1,13 @@
+config CLK_BCM_63XX
+ bool "Broadcom BCM63xx clock support"
+ depends on ARCH_BCM_63XX
+ depends on COMMON_CLK
+ select COMMON_CLK_IPROC
+ default y
+ help
+ Enable common clock framework support for Broadcom BCM63xx DSL SoCs
+ based on the ARM architecture
+
config CLK_BCM_KONA
bool "Broadcom Kona CCU clock support"
depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc95060d875..247c26750d8b 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index ..b7e0469d0522
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include "clk-iproc.h"
+
+static void __init bcm63138_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
--
2.1.0
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[PATCH 0/3] clk: Broadcom BCM63138 support
Hi all,
This patch series adds support for the Broadcom BCM63138 DSL SoCs
clocking framework.
Since the HW is identical to the one found in Broadcom iProc SoCs, but the
integration is different (obviously), there is still a new compatible string
introduced just in case we happen to find issues in the future.
This applies on top of clk/next as of
f63d19ef52aa66e97fca2425974845177ce02b0a ("Merge branch 'clk-iproc' into
clk-next")
Since there is an obvious dependency between patch 2 and 3, we can either
merge this through the Clock tree or via a future arm-soc pull requests
for Broadcom SoCs.
Thanks!
Florian Fainelli (3):
clk: iproc: Extend binding to cover BCM63138
clk: bcm: Add BCM63138 clock support
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
.../bindings/clock/brcm,iproc-clocks.txt | 5 +++
arch/arm/boot/dts/bcm63138.dtsi| 39 --
drivers/clk/bcm/Kconfig| 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22
5 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
--
2.1.0
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Re: [PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms
2015-10-22 18:44 GMT-07:00 Jaedon Shin :
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin
> ---
> drivers/phy/phy-brcmstb-sata.c | 21 ++---
> 1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 41c7535d706b..1cc80743b1b6 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -30,7 +30,8 @@
> #define MAX_PORTS 2
>
> /* Register offset between PHYs in PCB space */
> -#define SATA_MDIO_REG_SPACE_SIZE 0x1000
> +#define SATA_MDIO_REG_28NM_SPACE_SIZE 0x1000
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE 0x10
>
> struct brcm_sata_port {
> int portnum;
> @@ -47,7 +48,7 @@ struct brcm_sata_phy {
> struct brcm_sata_port phys[MAX_PORTS];
> };
>
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
> PLL_REG_BANK_0 = 0x50,
> PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
>
> @@ -85,7 +86,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank,
> u32 ofs,
> #define FMAX_VAL_DEFAULT 0x3df
> #define FMAX_VAL_SSC 0x83
>
> -static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
> +static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
> {
> void __iomem *base = brcm_sata_phy_base(port);
> struct brcm_sata_phy *priv = port->phy_priv;
> @@ -116,19 +117,25 @@ static int brcm_sata_phy_init(struct phy *phy)
> {
> struct brcm_sata_port *port = phy_get_drvdata(phy);
>
> - brcm_sata_cfg_ssc_28nm(port);
> + brcm_sata_cfg_ssc(port);
>
> return 0;
> }
>
> -static const struct phy_ops phy_ops_28nm = {
> +static const struct phy_ops phy_ops = {
> .init = brcm_sata_phy_init,
> .owner = THIS_MODULE,
> };
>
> static const struct of_device_id brcm_sata_phy_of_match[] = {
> { .compatible = "brcm,bcm7445-sata-phy",
> - .data = (void *)SATA_MDIO_REG_SPACE_SIZE },
> + .data = (void *)SATA_MDIO_REG_28NM_SPACE_SIZE },
> + { .compatible = "brcm,bcm7346-sata-phy",
> + .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> + { .compatible = "brcm,bcm7360-sata-phy",
> + .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> + { .compatible = "brcm,bcm7362-sata-phy",
> + .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
Same comment as the AHCI portion, we need to update the Device Tree
binding document to make these new compatible strings documented
there.
Thank you!
> {},
> };
> MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -185,7 +192,7 @@ static int brcm_sata_phy_probe(struct platform_device
> *pdev)
> port = &priv->phys[id];
> port->portnum = id;
> port->phy_priv = priv;
> - port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
> + port->phy = devm_phy_create(dev, child, &phy_ops);
> port->ssc_en = of_property_read_bool(child,
> "brcm,enable-ssc");
> if (IS_ERR(port->phy)) {
> dev_err(dev, "failed to create PHY\n");
> --
> 2.6.2
>
--
Florian
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Re: [PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset
2015-10-22 18:44 GMT-07:00 Jaedon Shin :
> Add data of device node for phy offset.
Similar comment to the AHCI portion, we could just omit specifying the
offset in the of_device_id.data member, and just assume the current
offset if not defined.
Acked-by: Florian Fainelli
>
> Signed-off-by: Jaedon Shin
> ---
> drivers/phy/phy-brcmstb-sata.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 0be55dafe9ea..41c7535d706b 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -42,6 +42,7 @@ struct brcm_sata_port {
> struct brcm_sata_phy {
> struct device *dev;
> void __iomem *phy_base;
> + u32 phy_offset;
>
> struct brcm_sata_port phys[MAX_PORTS];
> };
> @@ -65,7 +66,7 @@ static inline void __iomem *brcm_sata_phy_base(struct
> brcm_sata_port *port)
> {
> struct brcm_sata_phy *priv = port->phy_priv;
>
> - return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
> + return priv->phy_base + (port->portnum * priv->phy_offset);
> }
>
> static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
> @@ -126,7 +127,8 @@ static const struct phy_ops phy_ops_28nm = {
> };
>
> static const struct of_device_id brcm_sata_phy_of_match[] = {
> - { .compatible = "brcm,bcm7445-sata-phy" },
> + { .compatible = "brcm,bcm7445-sata-phy",
> + .data = (void *)SATA_MDIO_REG_SPACE_SIZE },
> {},
> };
> MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -135,6 +137,7 @@ static int brcm_sata_phy_probe(struct platform_device
> *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *dn = dev->of_node, *child;
> + const struct of_device_id *of_id = NULL;
> struct brcm_sata_phy *priv;
> struct resource *res;
> struct phy_provider *provider;
> @@ -154,6 +157,12 @@ static int brcm_sata_phy_probe(struct platform_device
> *pdev)
> if (IS_ERR(priv->phy_base))
> return PTR_ERR(priv->phy_base);
>
> + of_id = of_match_node(brcm_sata_phy_of_match, dn);
> + if (!of_id)
> + return -EINVAL;
> +
> + priv->phy_offset = (u32)of_id->data;
> +
> for_each_available_child_of_node(dn, child) {
> unsigned int id;
> struct brcm_sata_port *port;
> --
> 2.6.2
>
--
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Re: [PATCH 05/10] phy: phy_brcmstb_sata: remove unused definitions
2015-10-22 18:44 GMT-07:00 Jaedon Shin : > Remove unused definitions. > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli > --- > drivers/phy/phy-brcmstb-sata.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c > index 8a2cb16a1937..0be55dafe9ea 100644 > --- a/drivers/phy/phy-brcmstb-sata.c > +++ b/drivers/phy/phy-brcmstb-sata.c > @@ -26,8 +26,6 @@ > > #define SATA_MDIO_BANK_OFFSET 0x23c > #define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4) > -#define SATA_MDIO_REG_SPACE_SIZE 0x1000 > -#define SATA_MDIO_REG_LENGTH 0x1f00 > > #define MAX_PORTS 2 > > -- > 2.6.2 > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC
2015-10-22 18:44 GMT-07:00 Jaedon Shin : > The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI > SATA3 PHY. > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli > --- > drivers/phy/Kconfig | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 47da573d0bab..c83e48661fd7 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -364,11 +364,11 @@ config PHY_TUSB1210 > > config PHY_BRCMSTB_SATA > tristate "Broadcom STB SATA PHY driver" > - depends on ARCH_BRCMSTB > + depends on ARCH_BRCMSTB || BMIPS_GENERIC > depends on OF > select GENERIC_PHY > help > - Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs. > + Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB > SoCs. > Likely useful only with CONFIG_SATA_BRCMSTB enabled. > > endmenu > -- > 2.6.2 > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms
2015-10-22 18:44 GMT-07:00 Jaedon Shin :
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin
> ---
> drivers/ata/ahci_brcmstb.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 8cf6f7d4798f..59eb526cf4f6 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -50,7 +50,8 @@
>#define SATA_TOP_CTRL_2_SW_RST_RXBIT(2)
>#define SATA_TOP_CTRL_2_SW_RST_TXBIT(3)
>#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
> - #define SATA_TOP_CTRL_PHY_OFFS0x8
> + #define SATA_TOP_CTRL_28NM_PHY_OFFS 0x8
> + #define SATA_TOP_CTRL_40NM_PHY_OFFS 0x4
> #define SATA_TOP_MAX_PHYS 2
> #define SATA_TOP_CTRL_SATA_TP_OUT 0x1c
> #define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20
> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>
> static const struct of_device_id ahci_of_match[] = {
> {.compatible = "brcm,bcm7445-ahci",
> - .data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> + .data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7346-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7360-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7362-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
Since you are introducing new compatible strings, you also need to
update the binding document in Documentation/devicetree/bindings/ata/
We could just use the compatible string for the first 40nm chip that
started featuring such a SATA3 AHCI compliant core, which seems to be
7231. Apart from the existing known workarounds (disabling NCQ, tuning
the PHY) it seems to be largely identical across all 40nm chips.
This is fine either way, and more information cannot hurt, these are
all production chips, so we can actually look back at the history to
know everything about them.
--
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Re: [PATCH 02/10] ata: ahch_brcmstb: add data for port offset
2015-10-22 18:44 GMT-07:00 Jaedon Shin :
> Add data of device node for port offset.
Looks good to me, some minor nits below.
>
> Signed-off-by: Jaedon Shin
> ---
> drivers/ata/ahci_brcmstb.c | 25 +
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 14b7305d2ba0..8cf6f7d4798f 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -72,6 +72,7 @@
> struct brcm_ahci_priv {
> struct device *dev;
> void __iomem *top_ctrl;
> + u32 port_offset;
> u32 port_mask;
> };
>
> @@ -110,7 +111,7 @@ static inline void brcm_sata_writereg(u32 val, void
> __iomem *addr)
> static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
> {
> void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> - (port * SATA_TOP_CTRL_PHY_OFFS);
> + (port * priv->port_offset);
> void __iomem *p;
> u32 reg;
>
> @@ -139,7 +140,7 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv
> *priv, int port)
> static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
> {
> void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> - (port * SATA_TOP_CTRL_PHY_OFFS);
> + (port * priv->port_offset);
> void __iomem *p;
> u32 reg;
>
> @@ -234,6 +235,13 @@ static int brcm_ahci_resume(struct device *dev)
> }
> #endif
>
> +static const struct of_device_id ahci_of_match[] = {
> + {.compatible = "brcm,bcm7445-ahci",
> + .data = (void *)SATA_TOP_CTRL_PHY_OFFS},
We could omit having to specify explicitly the offset here.
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, ahci_of_match);
> +
> static struct scsi_host_template ahci_platform_sht = {
> AHCI_SHT(DRV_NAME),
> };
> @@ -241,6 +249,7 @@ static struct scsi_host_template ahci_platform_sht = {
> static int brcm_ahci_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> + const struct of_device_id *of_id = NULL;
> struct brcm_ahci_priv *priv;
> struct ahci_host_priv *hpriv;
> struct resource *res;
> @@ -256,6 +265,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
> if (IS_ERR(priv->top_ctrl))
> return PTR_ERR(priv->top_ctrl);
>
> + of_id = of_match_node(ahci_of_match, dev->of_node);
> + if (!of_id)
> + return -EINVAL;
> +
> + priv->port_offset = (u32)of_id->data;
And if of_id->data is NULL here, just default to
SATA_TOP_CTRL_PHY_OFFS. But I have no strong preference.
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Re: [PATCH 01/10] ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
2015-10-22 18:44 GMT-07:00 Jaedon Shin : > The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI > SATA3. > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli > --- > drivers/ata/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig > index 15e40ee62a94..8f535a88a0c7 100644 > --- a/drivers/ata/Kconfig > +++ b/drivers/ata/Kconfig > @@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM > > config AHCI_BRCMSTB > tristate "Broadcom STB AHCI SATA support" > - depends on ARCH_BRCMSTB > + depends on ARCH_BRCMSTB || BMIPS_GENERIC > help > This option enables support for the AHCI SATA3 controller found on > STB SoC's. > -- > 2.6.2 > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC
2015-10-22 20:58 GMT-07:00 Tejun Heo : > On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote: >> Hi all, >> >> This patch series adds support SATA for BMIPS_GENERIC. >> >> Ralf, >> I request you to drop already submitted patches for NAND device nodes. >> It is merge conflicts with this patches. >> http://patchwork.linux-mips.org/patch/10577/ >> http://patchwork.linux-mips.org/patch/10578/ >> http://patchwork.linux-mips.org/patch/10579/ >> http://patchwork.linux-mips.org/patch/10580/ >> >> Jaedon Shin (10): >> ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC >> ata: ahch_brcmstb: add data for port offset >> ata: ahci_brcmstb: add support 40nm platforms > > ata part looks fine to me. Let me know when the other parts get in. > I'll apply the ata ones to libata/for-4.4. There are a few comments coming on the ATA and Device Tree part, and I also would like Brian Norris (who submitted the patches) to take a look at these. But overall, this looks great. I think we have a bit too many compatible strings defined, I need to lookup tomorrow when I am back in the office which BCM7xxx started featuring a SATA3 AHCI compliant core, it might be 7420, but I am not sure Thanks! -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 9/9] MIPS: BMIPS: brcmstb: add I2C node for bcm7362
Le 20/10/2015 19:37, Jaedon Shin a écrit :
> Add I2C device nodes to BMIPS based BCM7362 platform.
>
> Signed-off-by: Jaedon Shin
Acked-by: Florian Fainelli
> ---
> arch/mips/boot/dts/brcm/bcm7362.dtsi | 52
> ++--
> arch/mips/boot/dts/brcm/bcm97362svmb.dts | 12
> 2 files changed, 62 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi
> b/arch/mips/boot/dts/brcm/bcm7362.dtsi
> index 6e65db86fc61..5f817be2553c 100644
> --- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
> @@ -87,14 +87,32 @@
> compatible = "brcm,bcm7120-l2-intc";
> reg = <0x406600 0x8>;
>
> - brcm,int-map-mask = <0x44>;
> + brcm,int-map-mask = <0x44>, <0x700>;
> brcm,int-fwd-mask = <0x7>;
>
> interrupt-controller;
> #interrupt-cells = <1>;
>
> interrupt-parent = <&periph_intc>;
> - interrupts = <56>;
> + interrupts = <56>, <54>;
> + interrupt-names = "upg_main", "upg_bsc";
> + };
> +
> + upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
> + compatible = "brcm,bcm7120-l2-intc";
> + reg = <0x408b80 0x8>;
> +
> + brcm,int-map-mask = <0x40>, <0x800>, <0x10>;
> + brcm,int-fwd-mask = <0>;
> + brcm,irq-can-wake;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&periph_intc>;
> + interrupts = <57>, <55>, <59>;
> + interrupt-names = "upg_main_aon", "upg_bsc_aon",
> + "upg_spi";
> };
>
> sun_top_ctrl: syscon@404000 {
> @@ -144,6 +162,36 @@
> status = "disabled";
> };
>
> + bsca: i2c@406200 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406200 0x58>;
> + interrupts = <24>;
> + interrupt-names = "upg_bsca";
> + status = "disabled";
> + };
> +
> + bscb: i2c@406280 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406280 0x58>;
> + interrupts = <25>;
> + interrupt-names = "upg_bscb";
> + status = "disabled";
> + };
> +
> + bscd: i2c@408980 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_aon_irq0_intc>;
> + reg = <0x408980 0x58>;
> + interrupts = <27>;
> + interrupt-names = "upg_bscd";
> + status = "disabled";
> + };
> +
> enet0: ethernet@43 {
> phy-mode = "internal";
> phy-handle = <&phy1>;
> diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
> b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
> index 739c2ef5663b..9c99bfd1e781 100644
> --- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
> +++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
> @@ -29,6 +29,18 @@
> status = "okay";
> };
>
> +&bsca {
> + status = "okay";
> +};
> +
> +&bscb {
> + status = "okay";
> +};
> +
> +&bscd {
> + status = "okay";
> +};
> +
> &enet0 {
> status = "okay";
> };
>
--
Florian
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Re: [PATCH 7/9] MIPS: BMIPS: brcmstb: add I2C node for bcm7358
Le 20/10/2015 19:36, Jaedon Shin a écrit :
> Add I2C device nodes to BMIPS based BCM7358 platform.
>
> Signed-off-by: Jaedon Shin
Acked-by: Florian Fainelli
> ---
> arch/mips/boot/dts/brcm/bcm7358.dtsi | 62
> ++--
> arch/mips/boot/dts/brcm/bcm97358svmb.dts | 16 +
> 2 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi
> b/arch/mips/boot/dts/brcm/bcm7358.dtsi
> index 277a90adc1a7..8e2501694d03 100644
> --- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
> @@ -81,14 +81,32 @@
> compatible = "brcm,bcm7120-l2-intc";
> reg = <0x406600 0x8>;
>
> - brcm,int-map-mask = <0x44>;
> + brcm,int-map-mask = <0x44>, <0x700>;
> brcm,int-fwd-mask = <0x7>;
>
> interrupt-controller;
> #interrupt-cells = <1>;
>
> interrupt-parent = <&periph_intc>;
> - interrupts = <56>;
> + interrupts = <56>, <54>;
> + interrupt-names = "upg_main", "upg_bsc";
> + };
> +
> + upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
> + compatible = "brcm,bcm7120-l2-intc";
> + reg = <0x408b80 0x8>;
> +
> + brcm,int-map-mask = <0x40>, <0x800>, <0x10>;
> + brcm,int-fwd-mask = <0>;
> + brcm,irq-can-wake;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&periph_intc>;
> + interrupts = <57>, <55>, <59>;
> + interrupt-names = "upg_main_aon", "upg_bsc_aon",
> + "upg_spi";
> };
>
> sun_top_ctrl: syscon@404000 {
> @@ -138,6 +156,46 @@
> status = "disabled";
> };
>
> + bsca: i2c@406200 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406200 0x58>;
> + interrupts = <24>;
> + interrupt-names = "upg_bsca";
> + status = "disabled";
> + };
> +
> + bscb: i2c@406280 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406280 0x58>;
> + interrupts = <25>;
> + interrupt-names = "upg_bscb";
> + status = "disabled";
> + };
> +
> + bscc: i2c@406300 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406300 0x58>;
> + interrupts = <26>;
> + interrupt-names = "upg_bscc";
> + status = "disabled";
> + };
> +
> + bscd: i2c@408980 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_aon_irq0_intc>;
> + reg = <0x408980 0x58>;
> + interrupts = <27>;
> + interrupt-names = "upg_bscd";
> + status = "disabled";
> + };
> +
> enet0: ethernet@43 {
> phy-mode = "internal";
> phy-handle = <&phy1>;
> diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
> b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
> index a8dc01e30313..02ce6b429dc4 100644
> --- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
> +++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
> @@ -29,6 +29,22 @@
> status = "okay";
> };
>
> +&bsca {
> + status = "okay";
> +};
> +
> +&bscb {
> + status = "okay";
> +};
> +
> +&bscc {
> + status = "okay";
> +};
> +
> +&bscd {
> + status = "okay";
> +};
> +
> &enet0 {
> status = "okay";
> };
>
--
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Re: [PATCH 6/9] MIPS: BMIPS: brcmstb: add I2C node for bcm7346
Le 20/10/2015 19:36, Jaedon Shin a écrit : > Add I2C device nodes to BMIPS based BCM7346 platform. > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 8/9] MIPS: BMIPS: brcmstb: add I2C node for bcm7360
Le 20/10/2015 19:37, Jaedon Shin a écrit :
> Add I2C device nodes to BMIPS based BCM7360 platform.
>
> Signed-off-by: Jaedon Shin
Acked-by: Florian Fainelli
> ---
> arch/mips/boot/dts/brcm/bcm7360.dtsi | 62
> ++--
> arch/mips/boot/dts/brcm/bcm97360svmb.dts | 16 +
> 2 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi
> b/arch/mips/boot/dts/brcm/bcm7360.dtsi
> index 9e1e571ba346..7e5f76040fb8 100644
> --- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
> @@ -81,14 +81,32 @@
> compatible = "brcm,bcm7120-l2-intc";
> reg = <0x406600 0x8>;
>
> - brcm,int-map-mask = <0x44>;
> + brcm,int-map-mask = <0x44>, <0x700>;
> brcm,int-fwd-mask = <0x7>;
>
> interrupt-controller;
> #interrupt-cells = <1>;
>
> interrupt-parent = <&periph_intc>;
> - interrupts = <56>;
> + interrupts = <56>, <54>;
> + interrupt-names = "upg_main", "upg_bsc";
> + };
> +
> + upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
> + compatible = "brcm,bcm7120-l2-intc";
> + reg = <0x408b80 0x8>;
> +
> + brcm,int-map-mask = <0x40>, <0x800>, <0x10>;
> + brcm,int-fwd-mask = <0>;
> + brcm,irq-can-wake;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&periph_intc>;
> + interrupts = <57>, <55>, <59>;
> + interrupt-names = "upg_main_aon", "upg_bsc_aon",
> + "upg_spi";
> };
>
> sun_top_ctrl: syscon@404000 {
> @@ -138,6 +156,46 @@
> status = "disabled";
> };
>
> + bsca: i2c@406200 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406200 0x58>;
> + interrupts = <24>;
> + interrupt-names = "upg_bsca";
> + status = "disabled";
> + };
> +
> + bscb: i2c@406280 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406280 0x58>;
> + interrupts = <25>;
> + interrupt-names = "upg_bscb";
> + status = "disabled";
> + };
> +
> + bscc: i2c@406300 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_irq0_intc>;
> + reg = <0x406300 0x58>;
> + interrupts = <26>;
> + interrupt-names = "upg_bscc";
> + status = "disabled";
> + };
> +
> + bscd: i2c@408980 {
> + clock-frequency = <39>;
> + compatible = "brcm,brcmstb-i2c";
> + interrupt-parent = <&upg_aon_irq0_intc>;
> + reg = <0x408980 0x58>;
> + interrupts = <27>;
> + interrupt-names = "upg_bscd";
> + status = "disabled";
> + };
> +
> enet0: ethernet@43 {
> phy-mode = "internal";
> phy-handle = <&phy1>;
> diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
> b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
> index eee8b0e32681..d48462e091f1 100644
> --- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
> +++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
> @@ -29,6 +29,22 @@
> status = "okay";
> };
>
> +&bsca {
> + status = "okay";
> +};
> +
> +&bscb {
> + status = "okay";
> +};
> +
> +&bscc {
> + status = "okay";
> +};
> +
> +&bscd {
> + status = "okay";
> +};
> +
> &enet0 {
> status = "okay";
> };
>
--
Florian
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Re: [PATCH 2/9] i2c: brcmstb: fix typo in i2c-brcmstb
Le 20/10/2015 19:36, Jaedon Shin a écrit : > Fixes the "definitions" where it is spelled "defintions". > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli > --- > drivers/i2c/busses/i2c-brcmstb.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/busses/i2c-brcmstb.c > b/drivers/i2c/busses/i2c-brcmstb.c > index 8e9637eea512..6b8bbf99880d 100644 > --- a/drivers/i2c/busses/i2c-brcmstb.c > +++ b/drivers/i2c/busses/i2c-brcmstb.c > @@ -41,7 +41,7 @@ > #define BSC_CTL_REG_INT_EN_SHIFT 6 > #define BSC_CTL_REG_DIV_CLK_MASK 0x0080 > > -/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */ > +/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ > #define BSC_IIC_EN_RESTART_MASK 0x0040 > #define BSC_IIC_EN_NOSTART_MASK 0x0020 > #define BSC_IIC_EN_NOSTOP_MASK 0x0010 > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/9] i2c: brcmstb: make the driver buildable on BMIPS_GENERIC
Le 20/10/2015 19:36, Jaedon Shin a écrit : > The BCM7xxx ARM and MIPS platforms share a similar hardware block for > I2C. > > Signed-off-by: Jaedon Shin Acked-by: Florian Fainelli > --- > drivers/i2c/busses/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig > index 08b86178e8fb..fd983c5b36f2 100644 > --- a/drivers/i2c/busses/Kconfig > +++ b/drivers/i2c/busses/Kconfig > @@ -394,7 +394,7 @@ config I2C_BCM_KONA > > config I2C_BRCMSTB > tristate "BRCM Settop I2C controller" > - depends on ARCH_BRCMSTB || COMPILE_TEST > + depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST > default y > help > If you say yes to this option, support will be included for the > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/9] i2c: brcmstb: add missing parenthesis
Le 20/10/2015 19:36, Jaedon Shin a écrit :
> Add the necessary parenthesis for NOACK condition.
>
> Signed-off-by: Jaedon Shin
Acked-by: Florian Fainelli
> ---
> drivers/i2c/busses/i2c-brcmstb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/busses/i2c-brcmstb.c
> b/drivers/i2c/busses/i2c-brcmstb.c
> index 6b8bbf99880d..2d7d155029dc 100644
> --- a/drivers/i2c/busses/i2c-brcmstb.c
> +++ b/drivers/i2c/busses/i2c-brcmstb.c
> @@ -305,7 +305,7 @@ static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev
> *dev,
> }
>
> if ((CMD_RD || CMD_WR) &&
> - bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
> + (bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK)) {
> rc = -EREMOTEIO;
> dev_dbg(dev->device, "controller received NOACK intr for %s\n",
> cmd_string[cmd]);
>
--
Florian
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Re: [PATCH net-next 1/2] drivers: net: xgene: Add support RGMII TX/RX delay configuration
On 16/10/15 13:35, Iyappan Subramanian wrote:
> Add RGMII TX/RX delay configuration support. RGMII standard requires 2ns
> delay to help the RGMII bridge receiver to sample data correctly. If the
> default value does not provide proper centering of the data sample, the
> TX/RX delay parameters can be used to adjust accordingly.
There is a standard 'phy-mode' property which can take multiple values
for RGMII: "rgmii" (no delay), "rgmii-txid" (transmit delay),
"rgmii-rxid" (receive delay) and "rgmii-id" (symetric delay). There does
not seem to be any verification of whether the rx or tx delay parameters
you introduce are going to be either sensible, or not conflicting with
the 'phy-mode' that should be configured.
>
> Signed-off-by: Iyappan Subramanian
> ---
> drivers/net/ethernet/apm/xgene/xgene_enet_hw.c | 8 +++-
> drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 1 +
> drivers/net/ethernet/apm/xgene/xgene_enet_main.c | 49
>
> drivers/net/ethernet/apm/xgene/xgene_enet_main.h | 2 +
> 4 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
> b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
> index 652f218..33850a0 100644
> --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
> +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
> @@ -461,6 +461,7 @@ static void xgene_gmac_reset(struct xgene_enet_pdata
> *pdata)
>
> static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
> {
> + struct device *dev = &pdata->pdev->dev;
> u32 value, mc2;
> u32 intf_ctl, rgmii;
> u32 icm0, icm2;
> @@ -490,7 +491,12 @@ static void xgene_gmac_init(struct xgene_enet_pdata
> *pdata)
> default:
> ENET_INTERFACE_MODE2_SET(&mc2, 2);
> intf_ctl |= ENET_GHD_MODE;
> - CFG_TXCLK_MUXSEL0_SET(&rgmii, 4);
> +
> + if (dev->of_node) {
> + CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
> + CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
> + }
> +
> xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
> value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
> xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
> diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
> b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
> index ff05bbc..6dee73c 100644
> --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
> +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
> @@ -144,6 +144,7 @@ enum xgene_enet_rm {
> #define CFG_BYPASS_UNISEC_RX BIT(1)
> #define CFG_CLE_BYPASS_EN0 BIT(31)
> #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
> +#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
>
> #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
> #define CFG_CLE_DSTQID0_SET(dst, val)xgene_set_bits(dst,
> val, 0, 12)
> diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
> b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
> index 6b1846d..ce10687 100644
> --- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
> +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
> @@ -1118,6 +1118,47 @@ static int xgene_get_port_id_dt(struct device *dev,
> struct xgene_enet_pdata *pda
> return ret;
> }
>
> +static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
> +{
> + struct device *dev = &pdata->pdev->dev;
> + int delay, ret;
> +
> + ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
> + if (ret) {
> + pdata->tx_delay = 4;
> + return 0;
> + }
> +
> + if (delay < 0 || delay > 7) {
> + dev_err(dev, "Invalid tx-delay specified\n");
> + return -EINVAL;
> + }
> +
> + pdata->tx_delay = delay;
> +
> + return 0;
> +}
> +
> +static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
> +{
> + struct device *dev = &pdata->pdev->dev;
> + int delay, ret;
> +
> + ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
> + if (ret) {
> + pdata->rx_delay = 2;
> + return 0;
> + }
> +
> + if (delay < 0 || delay > 7) {
> + dev_err(dev, "Invalid rx-delay specified\n");
> + return -EINVAL;
> + }
> +
> + pdata->rx_delay = delay;
> +
> + return 0;
> +}
>
> static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
> {
> @@ -1194,6 +1235,14 @@ static int xgene_enet_get_resources(struct
> xgene_enet_pdata *pdata)
> return -ENODEV;
> }
>
> + ret = xgene_get_tx_delay(pdata);
> + if (ret)
> + return ret;
> +
> + ret = xgene_get_rx_delay(pdata);
> + if (ret)
> + return ret;
> +
> ret = platform_get_irq(pdev, 0);
> if (ret <= 0) {
> dev_err(dev, "Unable to get ENET Rx IRQ\n");
> diff --git a/d
Re: [PATCH v2 2/4] mtd: nand: Allow MTD_NAND_BRCMNAND to be selected for ARM64
On 16/10/15 12:25, Arnd Bergmann wrote:
> On Friday 16 October 2015 09:54:45 Brian Norris wrote:
>>> MTD_NAND_BRCMNAND uses the generic nand functions, but is currently allowed
>>> to be built without CONFIG_MTD_NAND, which results in a link error:
>>>
>>> drivers/built-in.o: In function `brcmnand_remove':
>>> coresight-replicator.c:(.text+0x17ae6c): undefined reference to
>>> `nand_release'
>>> drivers/built-in.o: In function `brcmnand_probe':
>>> coresight-replicator.c:(.text+0x17d4b4): undefined reference to
>>> `nand_scan_ident'
>>> coresight-replicator.c:(.text+0x17d948): undefined reference to
>>> `nand_scan_tail'
>>
>> How did you get this? MTD_NAND_BRCMNAND is surrounded in the
>> 'if MTD_NAND' block, which implicitly generates a MTD_NAND dependency.
>> And I can confirm that in menuconfig, I see this when I disable MTD_NAND
>> and search for BRCMNAND:
>>
>>Symbol: MTD_NAND_BRCMNAND [=n]
>>Type : tristate
>>Prompt: Broadcom STB NAND controller
>> Location:
>>-> Device Drivers
>> -> Memory Technology Device (MTD) support (MTD [=y])
>>(1) -> NAND Device Support (MTD_NAND [=n])
>> Defined at drivers/mtd/nand/Kconfig:394
>> Depends on: MTD [=y] && MTD_NAND [=n] && (ARM [=y] || ARM64 || MIPS)
>
> Sorry, can't reproduce it any more. My patch is dated June 4, so it was
> probably broken then but got fixed since. I normally try to verify that
> the patches are still needed before I send them, but this time I only
> saw the current discussion and remembered something vague about it
> and sent what I had in my backlog of the randconfig-fixes series.
It may have been a problem before this patch:
d80d942bcc8e1555a76774d20be9800cfef2d415 ("ARM: BCM: Do not select
CONFIG_MTD_NAND_BRCMNAND")
--
Florian
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Re: [PATCH] net: phy: smsc: disable energy detect mode
2015-10-13 21:17 GMT-07:00 Heiko Schocher : > Hello Florian, > > > Am 13.10.2015 um 21:26 schrieb Florian Fainelli: >> >> On 12/10/15 22:13, Heiko Schocher wrote: >>> >>> On some boards the energy enable detect mode leads in >>> trouble with some switches, so make the enabling of >>> this mode configurable through DT. >>> >>> Signed-off-by: Heiko Schocher >>> --- >>> >>> .../devicetree/bindings/net/smsc-lan87xx.txt | 19 >>> + >>> drivers/net/phy/smsc.c | 24 >>> +- >>> 2 files changed, 38 insertions(+), 5 deletions(-) >>> create mode 100644 >>> Documentation/devicetree/bindings/net/smsc-lan87xx.txt >>> >>> diff --git a/Documentation/devicetree/bindings/net/smsc-lan87xx.txt >>> b/Documentation/devicetree/bindings/net/smsc-lan87xx.txt >>> new file mode 100644 >>> index 000..39aa1dc >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/net/smsc-lan87xx.txt >>> @@ -0,0 +1,19 @@ >>> +SMSC LAN87xx Ethernet PHY >>> + >>> +Some boards require special tuning values. Configure them >>> +through an Ethernet OF device node. >>> + >>> +Optional properties: >>> + >>> +- disable-energy-detect: >>> + If set, do not enable energy detect mode for the SMSC phy. >>> + default: enable energy detect mode >> >> >> Although energy detection is something that is implemented by many PHYs, >> I am not sure a generic property is suitable here, I would prefix that >> with the SMSC vendor prefix here to make it clear this only applies to >> this PHY. > > > Hmm... but all PHYs should be able to enable, disable it in some way, or? It may not always be controlled directly at the PHY level, sometimes this is something that needs cooperation with the Ethernet MAC as well in case of integrated designs. > >> Would not you want to make it a reverse property here though, something >> like this: >> >> smsc,energy-detect: boolean, when present indicates the PHY reliably >> supports energy detection > > > Yes, that was also my first thought, but currently, on this PHYs > energy detect mode is on ... and if I introduce such a property, > it will disable it for all existing boards, because property is > missing ... so, maybe I break boards ... Fair enough, how about smsc,disabled-energy-detect or something like that then? -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
