Re: [PATCH v5 3/3] PCI: st: Provide support for the sti PCIe controller
On 6 October 2015 at 23:01, Arnd Bergmann wrote:
> On Tuesday 06 October 2015 09:56:08 Gabriel Fernandez wrote:
>> +
>> +/*
>> + * On ARM platforms, we actually get a bus error returned when the PCIe IP
>> + * returns a UR or CRS instead of an OK.
>> + */
>> +static int st_pcie_abort_handler(unsigned long addr, unsigned int fsr,
>> +struct pt_regs *regs)
>> +{
>> + return 0;
>> +}
>>
>
> I'm not sure if we discussed this already for this driver. Usually
> you should have a register in the PCI host that you can check to see
> what caused the abort.
>
> Try to make this as narrow as possible so you return nonzero for
> any abort except the one you actually try to prevent.
>
> Arnd
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Arnd,
Yes we already discussed about that:
http://www.spinics.net/lists/arm-kernel/msg393705.html
We can probably improve the abort handling once the patch below will be merged
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/366215.html
As imx6 does the same, does it sound reasonable to keep this approach
of the st driver and start discussing about generic way to handle
abort for DW pci driver ?
Best regards
Gabriel
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Re: [PATCH v5 1/3] ARM: STi: Kconfig update for PCIe support
Hi Russell no problem, i will fix it Thanks for review. BR Gabriel On 6 October 2015 at 21:01, Russell King - ARM Linux wrote: > On Tue, Oct 06, 2015 at 09:56:06AM +0200, Gabriel Fernandez wrote: >> Update Kconfig: >> - MIGHT_HAVE_PCI >> - PCI_DOMAINS >> >> Signed-off-by: Fabrice Gasnier >> --- >> arch/arm/mach-sti/Kconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig >> index 125865d..5f99e93 100644 >> --- a/arch/arm/mach-sti/Kconfig >> +++ b/arch/arm/mach-sti/Kconfig >> @@ -9,6 +9,8 @@ menuconfig ARCH_STI >> select ARCH_HAS_RESET_CONTROLLER >> select HAVE_ARM_SCU if SMP >> select ARCH_REQUIRE_GPIOLIB >> + select PCI_DOMAINS if PCI >> + select MIGHT_HAVE_PCI >> select ARM_ERRATA_754322 >> select ARM_ERRATA_764369 if SMP >> select ARM_ERRATA_775420 > > Please, alphabetical ordering for select statements. > > -- > FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up > according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
drivers/clk/st/clkgen-pll.c| 194 +
2 files changed, 195 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index e2c6db0..8f84c81 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -23,6 +23,7 @@ Required properties:
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,plls-c32-cx_0", "st,clkgen-plls-c32"
"st,plls-c32-cx_1", "st,clkgen-plls-c32"
+ "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 494848e..38f6f3a 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -44,6 +44,13 @@ DEFINE_SPINLOCK(clkgen_a9_lock);
#define C32_MAX_ODFS (4)
+/*
+ * PLL configuration register bits for PLL4600 C28
+ */
+#define C28_NDIV_MASK (0xff)
+#define C28_IDF_MASK (0x7)
+#define C28_ODF_MASK (0x3f)
+
struct clkgen_pll_data {
struct clkgen_field pdn_status;
struct clkgen_field pdn_ctrl;
@@ -68,6 +75,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
+static const struct clk_ops stm_pll4600c28_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
@@ -256,6 +264,22 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static struct clkgen_pll_data st_pll4600c28_418_a9 = {
+ /* 418 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1,0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
+ .idf= CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
+ .switch2pll_en = true,
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll4600c28_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -611,6 +635,163 @@ static unsigned long recalc_stm_pll1200c32(struct clk_hw
*hw,
return rate;
}
+/* PLL output structure
+ * FVCO >> /2 >> FVCOBY2 (no output)
+ * |> Divider (ODF) >> PHI
+ *
+ * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
+ *
+ * Rules:
+ * 4Mhz <= INFF input <= 350Mhz
+ * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
+ * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
+ * 1 <= i (register/dec value for IDF) <= 7
+ * 8 <= n (register/dec value for NDIV) <= 246
+ */
+
+static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
+ struct stm_pll *pll)
+{
+
+ unsigned long i, infin, n;
+ unsigned long deviation = ~0;
+ unsigned long new_freq, new_deviation;
+
+ /* Output clock range: 19Mhz to 3000Mhz */
+ if (output < 1900 || output > 30u)
+ return -EINVAL;
+
+ /* For better jitter, IDF should be smallest and NDIV must be maximum */
+ for (i = 1; i <= 7 && deviation; i++) {
+ /* INFIN checks */
+ infin = input / i;
+ if (infin < 400 || infin > 5000)
+ continue; /* Invalid case */
+
+ n = output / (infin * 2);
+ if (n < 8 || n > 246)
+ continue; /* Invalid case */
+ if (n < 246)
+ n++;/* To work around 'y' when n=x.y */
+
+ for (; n >= 8 && deviation; n--) {
+ new_freq = infin * 2 * n;
+
[PATCH v4 4/4] ARM: STi: DT: Add support for stih418 A9 pll
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9",
"st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
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[PATCH v4 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 60 -
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index b2a332c..092f82c 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include "clkgen.h"
@@ -43,6 +44,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
struct clkgen_pll_data {
struct clkgen_field pdn_status;
+ struct clkgen_field pdn_ctrl;
struct clkgen_field locked_status;
struct clkgen_field mdiv;
struct clkgen_field ndiv;
@@ -62,6 +64,7 @@ static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0x10,0x1,0),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -70,6 +73,7 @@ static const struct clkgen_pll_data st_pll1600c65_ax = {
static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0xC, 0x1,1),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -79,6 +83,7 @@ static const struct clkgen_pll_data st_pll800c65_ax = {
static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,0),
.locked_status = CLKGEN_FIELD(0x4, 0x1,31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
@@ -96,6 +101,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,1),
.locked_status = CLKGEN_FIELD(0x10,0x1,31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x10,C32_IDF_MASK, 0x0),
@@ -114,6 +120,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
/* 415 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x6C,0x1,0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
@@ -125,6 +132,7 @@ static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x100, 0x1,0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
@@ -137,7 +145,8 @@ static const struct clkgen_pll_data st_pll3200c32_ddr_415 =
{
};
static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
- .pdn_status = CLKGEN_FIELD(0x144, 0x1,3),
+ .pdn_status = CLKGEN_FIELD(0x4, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x4, 0x1,0),
.locked_status = CLKGEN_FIELD(0x168, 0x1,0),
.ldf= CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
@@ -149,6 +158,7 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_415 =
{
/* 416 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x
[PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3 +
drivers/clk/st/clkgen-pll.c | 221 ++--
drivers/clk/st/clkgen.h | 2 +
3 files changed, 216 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4f7f6c0..5dc5ce2 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_divmux_lock);
static DEFINE_SPINLOCK(clkgenf_lock);
@@ -576,6 +577,7 @@ static struct clkgen_mux_data stih415_a9_mux_data = {
.offset = 0,
.shift = 1,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static struct clkgen_mux_data stih416_a9_mux_data = {
.offset = 0,
@@ -586,6 +588,7 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
.shift = 0,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static const struct of_device_id mux_of_match[] = {
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 092f82c..494848e 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -23,6 +23,7 @@
#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
+DEFINE_SPINLOCK(clkgen_a9_lock);
/*
* Common PLL configuration register bits for PLL800 and PLL1600 C65
@@ -39,6 +40,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
#define C32_IDF_MASK (0x7)
#define C32_ODF_MASK (0x3f)
#define C32_LDF_MASK (0x7f)
+#define C32_CP_MASK (0x1f)
#define C32_MAX_ODFS (4)
@@ -51,15 +53,20 @@ struct clkgen_pll_data {
struct clkgen_field pdiv;
struct clkgen_field idf;
struct clkgen_field ldf;
+ struct clkgen_field cp;
unsigned int num_odfs;
struct clkgen_field odf[C32_MAX_ODFS];
struct clkgen_field odf_gate[C32_MAX_ODFS];
+ bool switch2pll_en;
+ struct clkgen_field switch2pll;
+ spinlock_t *lock;
const struct clk_ops *ops;
};
static const struct clk_ops st_pll1600c65_ops;
static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
+static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
@@ -242,7 +249,11 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.num_odfs = 1,
.odf= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
- .ops= &stm_pll3200c32_ops,
+ .switch2pll_en = true,
+ .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK,1),
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll3200c32_a9_ops,
};
/**
@@ -268,10 +279,26 @@ struct clkgen_pll {
struct clk_hw hw;
struct clkgen_pll_data *data;
void __iomem*regs_base;
+ spinlock_t *lock;
+
+ u32 ndiv;
+ u32 idf;
+ u32 odf;
+ u32 cp;
};
#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
+struct stm_pll {
+ unsigned long mdiv;
+ unsigned long ndiv;
+ unsigned long pdiv;
+ unsigned long odf;
+ unsigned long idf;
+ unsigned long ldf;
+ unsigned long cp;
+};
+
static int clkgen_pll_is_locked(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
@@ -287,7 +314,7 @@ static int clkgen_pll_is_enabled(struct clk_hw *hw)
return !poweroff;
}
-static int clkgen_pll_enable(struct clk_hw *hw)
+static int __clkgen_pll_enable(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
void __iomem *base = pll->regs_base;
@@ -303,24 +330,62 @@ static int clkgen_pll_enable(struct clk_hw *hw)
ret = readl_relaxed_poll_timeout(base + field->offset, reg,
!!((reg >> field->shift) & field->mask), 0, 1);
- if (!ret)
+ if (!ret) {
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 0);
+
pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
+ }
return ret;
}
-static void clkgen_pll_disable(struct clk_hw *hw)
+static int clkgen_pll_enable(struct clk_hw *hw)
+{
+ struct clkgen_pll *pll = to_clkgen_pll(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (pll->lock)
+ spin_lock_irqsave
[PATCH v4 0/4] ST PLL improvement
Changes in v4: - Spinlock affectation was removed unintentionally in clkgen_pll_register() since v3 Changes in v3: - reorganize patch 1 and 2 to avoid a break git bisect Changes in v2: - Add const for st_pll4600c28_418_a9 structure - Use readl_relaxed_poll_timeout macro instead Jiffies - Add patch to enable stih418 A9 pll via DT. This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 ARM: STi: DT: Add support for stih418 A9 pll .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 + arch/arm/boot/dts/stih418-clock.dtsi | 2 +- drivers/clk/st/clkgen-mux.c| 3 + drivers/clk/st/clkgen-pll.c| 469 - drivers/clk/st/clkgen.h| 2 + 5 files changed, 468 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Hi Stephen,
No there is no reason. I will fix it.
Thanks for review.
Best regards
Gabriel
On 6 October 2015 at 20:06, Stephen Boyd wrote:
> On 10/05, Gabriel Fernandez wrote:
>> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
>> static struct clk * __init clkgen_pll_register(const char *parent_name,
>> struct clkgen_pll_data *pll_data,
>> void __iomem *reg,
>> - const char *clk_name)
>> + const char *clk_name, spinlock_t *lock)
>
> Is there a reason we pass lock here but never use it in this
> function?
>
>> {
>> struct clkgen_pll *pll;
>> struct clk *clk;
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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[PATCH v5 1/3] ARM: STi: Kconfig update for PCIe support
Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 125865d..5f99e93 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -9,6 +9,8 @@ menuconfig ARCH_STI select ARCH_HAS_RESET_CONTROLLER select HAVE_ARM_SCU if SMP select ARCH_REQUIRE_GPIOLIB + select PCI_DOMAINS if PCI + select MIGHT_HAVE_PCI select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/3] PCI: st: provide support for dw pcie
This patchset is based on v4.3-rc3 and is based on [PATCH v9 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 patchset from Zhou Wang (to disable IO support) Changes in v5: - Move wait after link training completes - Minor fixes in devitree binding - Merge 'PCI: st: Provide support for the sti PCIe controller' and 'MAINTAINERS: Add pci-st.c to ARCH/STI architecture' patches. Changes in v4: - Remove pci: designware: remove my pci_common_init_dev() patch and use [PATCH v8 3/6] PCI: designware: Add ARM64 support instead. This patch is a good solution for me to disable IO support. - add __init to st_pcie_probe() and use module_init() instead device_initcall() to prevent the probe function from being deferred and to prevent module unloading. Changes in v3: - Remove power management functions (was not fully tested) - Remove configuration space range from dt binding - Remove pci_common_init_dev() call in pcie-designware.c to avoid default IO space declaration. Changes in v2: - comestic corrections in device tree binding - add pci-st.c into MAINTAINERS - remove st_pcie_ops structure to avoid another level of indirection - remove nasty busy-loop - remove useless test using virt_to_phys() - move disable io support into dw-pcie driver I don't change the st_pcie_abort_handler() function because abort handling is masked during boot. This patch-set introduces a STMicroelectronics PCIe controller. It's based on designware PCIe driver. Gabriel Fernandez (3): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++ MAINTAINERS | 1 + arch/arm/mach-sti/Kconfig | 2 + drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 587 ++ 6 files changed, 656 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt create mode 100644 drivers/pci/host/pci-st.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/3] PCI: st: Provide support for the sti PCIe controller
sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez Reviewed-by: Pratyush Anand --- MAINTAINERS | 1 + drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 587 ++ 4 files changed, 598 insertions(+) create mode 100644 drivers/pci/host/pci-st.c diff --git a/MAINTAINERS b/MAINTAINERS index 9f6685f..f616ca6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1533,6 +1533,7 @@ F:drivers/i2c/busses/i2c-st.c F: drivers/media/rc/st_rc.c F: drivers/media/platform/sti/c8sectpfe/ F: drivers/mmc/host/sdhci-st.c +F: drivers/pci/host/pci-st.c F: drivers/phy/phy-miphy28lp.c F: drivers/phy/phy-miphy365x.c F: drivers/phy/phy-stih407-usb.c diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d5e58ba..23ab538 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -145,4 +145,13 @@ config PCIE_IPROC_BCMA Say Y here if you want to use the Broadcom iProc PCIe controller through the BCMA bus interface +config PCI_ST + bool "ST PCIe controller" + depends on ARCH_STI || (ARM && COMPILE_TEST) + select PCIE_DW + help + Enable PCIe controller support on ST Socs. This controller is based + on Designware hardware and therefore the driver re-uses the + Designware core functions to implement the driver. + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 140d66f..c4024fa 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o +obj-$(CONFIG_PCI_ST) += pci-st.o diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c new file mode 100644 index 000..575a25b --- /dev/null +++ b/drivers/pci/host/pci-st.c @@ -0,0 +1,587 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PCI express Driver for sti SoCs. + * ST PCIe IPs are built around a Synopsys IP Core. + * + * Author: Fabrice Gasnier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define TRANSLATION_CONTROL0x900 +/* Controls if area is inclusive or exclusive */ +#define RC_PASS_ADDR_RANGE BIT(1) + +/* Base of area reserved for config accesses. Fixed size of 64K. */ +#define CFG_BASE_ADDRESS 0x92c +#define CFG_REGION_SIZE65536 +#define CFG_SPACE1_OFFSET 0x1000 + +/* First 4K of config space has this BDF (bus,device,function) */ +#define FUNC0_BDF_NUM 0x930 + +/* Mem regions */ +#define IN0_MEM_ADDR_START 0x964 +#define IN0_MEM_ADDR_LIMIT 0x968 +#define IN1_MEM_ADDR_START 0x974 +#define IN1_MEM_ADDR_LIMIT 0x978 + +/* This actually contains the LTSSM state machine state */ +#define PORT_LOGIC_DEBUG_REG_0 0x728 + +/* LTSSM state machine values */ +#define DEBUG_REG_0_LTSSM_MASK 0x1f +#define S_DETECT_QUIET 0x00 +#define S_DETECT_ACT 0x01 +#define S_POLL_ACTIVE 0x02 +#define S_POLL_COMPLIANCE 0x03 +#define S_POLL_CONFIG 0x04 +#define S_PRE_DETECT_QUIET 0x05 +#define S_DETECT_WAIT 0x06 +#define S_CFG_LINKWD_START 0x07 +#define S_CFG_LINKWD_ACEPT 0x08 +#define S_CFG_LANENUM_WAIT 0x09 +#define S_CFG_LANENUM_ACEPT0x0A +#define S_CFG_COMPLETE 0x0B +#define S_CFG_IDLE 0x0C +#define S_RCVRY_LOCK 0x0D +#define S_RCVRY_SPEED 0x0E +#define S_RCVRY_RCVRCFG0x0F +#define S_RCVRY_IDLE 0x10 +#define S_L0 0x11 +#define S_L0S 0x12 +#define S_L123_SEND_EIDLE 0x13 +#define S_L1_IDLE 0x14 +#define S_L2_IDLE 0x15 +#define S_L2_WAKE 0x16 +#define S_DISABLED_ENTRY 0x17 +#define S_DISABLED_IDLE0x18 +#define S_DISABLED 0x19 +#define S_LPBK_ENTRY 0x1A +#define S_LPBK_ACTIVE 0x1B +#define S_LPBK_EXIT0x1C +#define S_LPBK_EXIT_TIMEOUT0x1D +#define S_HOT_RESET_ENTRY 0x1E +#define S_HOT_R
[PATCH v5 2/3] PCI: st: Add Device Tree bindings for sti pcie
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
b/Documentation/devicetree/bindings/pci/st-pcie.txt
new file mode 100644
index 000..32e76d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
@@ -0,0 +1,56 @@
+STMicroelectronics STi PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+ - compatible: Should be "st,pcie", "snps,dw-pcie"
+
+ - reg: base address and length of the pcie controller, mem-window address
+ and length available to the controller.
+
+ - interrupts: one GIC interrupt line connected to PCI MSI interrupt line
+
+ - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
+ offset for IP configuration.
+
+ - resets: phandle to the powerdown and reset controller for the PCIe IP.
+ See ../reset/reset.txt for details.
+ - reset-names: should be "powerdown" and "softreset".
+
+ - phys: the phandle for the PHY device (used by generic PHY framework).
+ - phys-names: must be "pcie".
+
+Optional properties:
+ - reset-gpio: a GPIO spec to define which pin is connected to the bus reset.
+
+Example:
+
+pcie0: pcie@9b0 {
+ compatible = "st,pcie", "snps,dw-pcie";
+ device_type = "pci";
+ reg = <0x09b0 0x4000>, /* dbi cntrl registers */
+ <0x2fff 0x0001>, /* configuration space */
+ <0x4000 0x8000>; /* lmi mem window */
+ reg-names = "dbi", "config", "mem-window";
+ st,syscfg = <&syscfg_core 0xd8 0xe0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = ;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT
A */
+ <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT
B */
+ <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT
C */
+ <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT
D */
+
+ resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
+<&softreset STIH407_PCIE0_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ phys = <&phy_port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie";
+};
--
1.9.1
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[PATCH v3 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 60 -
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index b2a332c..092f82c 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include "clkgen.h"
@@ -43,6 +44,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
struct clkgen_pll_data {
struct clkgen_field pdn_status;
+ struct clkgen_field pdn_ctrl;
struct clkgen_field locked_status;
struct clkgen_field mdiv;
struct clkgen_field ndiv;
@@ -62,6 +64,7 @@ static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0x10,0x1,0),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -70,6 +73,7 @@ static const struct clkgen_pll_data st_pll1600c65_ax = {
static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0xC, 0x1,1),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -79,6 +83,7 @@ static const struct clkgen_pll_data st_pll800c65_ax = {
static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,0),
.locked_status = CLKGEN_FIELD(0x4, 0x1,31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
@@ -96,6 +101,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,1),
.locked_status = CLKGEN_FIELD(0x10,0x1,31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x10,C32_IDF_MASK, 0x0),
@@ -114,6 +120,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
/* 415 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x6C,0x1,0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
@@ -125,6 +132,7 @@ static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x100, 0x1,0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
@@ -137,7 +145,8 @@ static const struct clkgen_pll_data st_pll3200c32_ddr_415 =
{
};
static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
- .pdn_status = CLKGEN_FIELD(0x144, 0x1,3),
+ .pdn_status = CLKGEN_FIELD(0x4, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x4, 0x1,0),
.locked_status = CLKGEN_FIELD(0x168, 0x1,0),
.ldf= CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
@@ -149,6 +158,7 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_415 =
{
/* 416 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x
[PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3 +
drivers/clk/st/clkgen-pll.c | 220 ++--
drivers/clk/st/clkgen.h | 2 +
3 files changed, 215 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4f7f6c0..5dc5ce2 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_divmux_lock);
static DEFINE_SPINLOCK(clkgenf_lock);
@@ -576,6 +577,7 @@ static struct clkgen_mux_data stih415_a9_mux_data = {
.offset = 0,
.shift = 1,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static struct clkgen_mux_data stih416_a9_mux_data = {
.offset = 0,
@@ -586,6 +588,7 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
.shift = 0,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static const struct of_device_id mux_of_match[] = {
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 092f82c..22b6201 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -23,6 +23,7 @@
#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
+DEFINE_SPINLOCK(clkgen_a9_lock);
/*
* Common PLL configuration register bits for PLL800 and PLL1600 C65
@@ -39,6 +40,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
#define C32_IDF_MASK (0x7)
#define C32_ODF_MASK (0x3f)
#define C32_LDF_MASK (0x7f)
+#define C32_CP_MASK (0x1f)
#define C32_MAX_ODFS (4)
@@ -51,15 +53,20 @@ struct clkgen_pll_data {
struct clkgen_field pdiv;
struct clkgen_field idf;
struct clkgen_field ldf;
+ struct clkgen_field cp;
unsigned int num_odfs;
struct clkgen_field odf[C32_MAX_ODFS];
struct clkgen_field odf_gate[C32_MAX_ODFS];
+ bool switch2pll_en;
+ struct clkgen_field switch2pll;
+ spinlock_t *lock;
const struct clk_ops *ops;
};
static const struct clk_ops st_pll1600c65_ops;
static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
+static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
@@ -242,7 +249,11 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.num_odfs = 1,
.odf= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
- .ops= &stm_pll3200c32_ops,
+ .switch2pll_en = true,
+ .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK,1),
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll3200c32_a9_ops,
};
/**
@@ -268,10 +279,26 @@ struct clkgen_pll {
struct clk_hw hw;
struct clkgen_pll_data *data;
void __iomem*regs_base;
+ spinlock_t *lock;
+
+ u32 ndiv;
+ u32 idf;
+ u32 odf;
+ u32 cp;
};
#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
+struct stm_pll {
+ unsigned long mdiv;
+ unsigned long ndiv;
+ unsigned long pdiv;
+ unsigned long odf;
+ unsigned long idf;
+ unsigned long ldf;
+ unsigned long cp;
+};
+
static int clkgen_pll_is_locked(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
@@ -287,7 +314,7 @@ static int clkgen_pll_is_enabled(struct clk_hw *hw)
return !poweroff;
}
-static int clkgen_pll_enable(struct clk_hw *hw)
+static int __clkgen_pll_enable(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
void __iomem *base = pll->regs_base;
@@ -303,24 +330,62 @@ static int clkgen_pll_enable(struct clk_hw *hw)
ret = readl_relaxed_poll_timeout(base + field->offset, reg,
!!((reg >> field->shift) & field->mask), 0, 1);
- if (!ret)
+ if (!ret) {
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 0);
+
pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
+ }
return ret;
}
-static void clkgen_pll_disable(struct clk_hw *hw)
+static int clkgen_pll_enable(struct clk_hw *hw)
+{
+ struct clkgen_pll *pll = to_clkgen_pll(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (pll->lock)
+ spin_lock_irqsave
[PATCH v3 4/4] ARM: STi: DT: Add support for stih418 A9 pll
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9",
"st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
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[PATCH v3 0/4] ST PLL improvement
Changes in v3: - reorganize patch 1 and 2 to avoid a break git bisect Changes in v2: - Add const for st_pll4600c28_418_a9 structure - Use readl_relaxed_poll_timeout macro instead Jiffies - Add patch to enable stih418 A9 pll via DT. This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 ARM: STi: DT: Add support for stih418 A9 pll .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 + arch/arm/boot/dts/stih418-clock.dtsi | 2 +- drivers/clk/st/clkgen-mux.c| 3 + drivers/clk/st/clkgen-pll.c| 468 - drivers/clk/st/clkgen.h| 2 + 5 files changed, 467 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
drivers/clk/st/clkgen-pll.c| 194 +
2 files changed, 195 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index e2c6db0..8f84c81 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -23,6 +23,7 @@ Required properties:
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,plls-c32-cx_0", "st,clkgen-plls-c32"
"st,plls-c32-cx_1", "st,clkgen-plls-c32"
+ "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 22b6201..ba75cae 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -44,6 +44,13 @@ DEFINE_SPINLOCK(clkgen_a9_lock);
#define C32_MAX_ODFS (4)
+/*
+ * PLL configuration register bits for PLL4600 C28
+ */
+#define C28_NDIV_MASK (0xff)
+#define C28_IDF_MASK (0x7)
+#define C28_ODF_MASK (0x3f)
+
struct clkgen_pll_data {
struct clkgen_field pdn_status;
struct clkgen_field pdn_ctrl;
@@ -68,6 +75,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
+static const struct clk_ops stm_pll4600c28_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
@@ -256,6 +264,22 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static struct clkgen_pll_data st_pll4600c28_418_a9 = {
+ /* 418 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1,0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
+ .idf= CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
+ .switch2pll_en = true,
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll4600c28_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -611,6 +635,163 @@ static unsigned long recalc_stm_pll1200c32(struct clk_hw
*hw,
return rate;
}
+/* PLL output structure
+ * FVCO >> /2 >> FVCOBY2 (no output)
+ * |> Divider (ODF) >> PHI
+ *
+ * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
+ *
+ * Rules:
+ * 4Mhz <= INFF input <= 350Mhz
+ * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
+ * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
+ * 1 <= i (register/dec value for IDF) <= 7
+ * 8 <= n (register/dec value for NDIV) <= 246
+ */
+
+static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
+ struct stm_pll *pll)
+{
+
+ unsigned long i, infin, n;
+ unsigned long deviation = ~0;
+ unsigned long new_freq, new_deviation;
+
+ /* Output clock range: 19Mhz to 3000Mhz */
+ if (output < 1900 || output > 30u)
+ return -EINVAL;
+
+ /* For better jitter, IDF should be smallest and NDIV must be maximum */
+ for (i = 1; i <= 7 && deviation; i++) {
+ /* INFIN checks */
+ infin = input / i;
+ if (infin < 400 || infin > 5000)
+ continue; /* Invalid case */
+
+ n = output / (infin * 2);
+ if (n < 8 || n > 246)
+ continue; /* Invalid case */
+ if (n < 246)
+ n++;/* To work around 'y' when n=x.y */
+
+ for (; n >= 8 && deviation; n--) {
+ new_freq = infin * 2 * n;
+
Re: [PATCH v4 3/4] PCI: st: Provide support for the sti PCIe controller
Hi Pratyush,
Thanks for the review.
Best regards
Gabriel
On 27 August 2015 at 19:31, Pratyush Anand wrote:
> Hi Gabriel,
>
> Looks good to me.
>
> On Thu, Aug 27, 2015 at 6:04 PM, Gabriel Fernandez
> wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>
>
>> +static int st_pcie_link_up(struct pcie_port *pp)
>> +{
>> + u32 status;
>> + int link_up;
>
> nit: why not bool
i prefer to keep it as 'int' because the prototype of link_up callback
is an 'int'.
>
>> + int count = 0;
>
> [...]
>
>> +static void st_pcie_board_reset(struct pcie_port *pp)
>> +{
>> + struct st_pcie *pcie = to_st_pcie(pp);
>> +
>> + if (!gpio_is_valid(pcie->reset_gpio))
>> + return;
>> +
>> + if (gpio_direction_output(pcie->reset_gpio, 0)) {
>> + dev_err(pp->dev, "Cannot set PERST# (gpio %u) to output\n",
>> + pcie->reset_gpio);
>> + return;
>> + }
>> +
>> + /* From PCIe spec */
>> + msleep(2);
>> + gpio_direction_output(pcie->reset_gpio, 1);
>> +
>> + /*
>> +* PCIe specification states that you should not issue any config
>> +* requests until 100ms after asserting reset, so we enforce that
>> here
>> +*/
>> + msleep(100);
>
> IIRC, specification says to wait after link training completes. So
> shouldn't it be after st_pcie_enable_ltssm. Moreover, I wonder why
> others do not need it.
>
Ok i will fix it.
> Reviewed-by: Pratyush Anand
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Re: [PATCH v4 2/4] PCI: st: Add Device Tree bindings for sti pcie
Hi Rob,
Thanks for the review.
Best regards
Gabriel
On 28 August 2015 at 02:06, Rob Herring wrote:
> On Thu, Aug 27, 2015 at 7:34 AM, Gabriel Fernandez
> wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>> ---
>> Documentation/devicetree/bindings/pci/st-pcie.txt | 53
>> +++
>> 1 file changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
>> b/Documentation/devicetree/bindings/pci/st-pcie.txt
>> new file mode 100644
>> index 000..25fcab3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
>> @@ -0,0 +1,53 @@
>> +STMicroelectronics STi PCIe controller
>> +
>> +This PCIe host controller is based on the Synopsis Designware PCIe IP
>> +and thus inherits all the common properties defined in designware-pcie.txt.
>> +
>> +Required properties:
>> + - compatible: "st,stih407-pcie"
>
> What about "snps,dw-pcie" as well?
>
You are right.
>> + - reg: base address and length of the pcie controller, mem-window address
>> + and length available to the controller.
>
> What is mem-window? Seems rather large and perhaps should be under ranges.
>
No the purpose is to specify the physical memory available to the controller.
reg property is more appropriate.
>> + - interrupts: A list of interrupt outputs of the controller. Must contain
>> an
>> + entry for each entry in the interrupt-names property.
>
> Define how many interrupts.
>
ok i will fix it.
>> + - interrupt-names: Should be "msi". STi interrupt that is asserted when an
>> + MSI is received.
>
> Kind of pointless with a single interrupt.
>
ok
>> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
>> + offset for IP configuration.
>> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP.
>> + Associated names must be "powerdown" and "softreset".
>> + - phys, phy-names: the phandle for the PHY device.
>> + Associated name must be "pcie"
>
> What does this mean?
>
i will reformulate this paragraph.
>> +
>> +Optional properties:
>> + - reset-gpio: a GPIO spec to define which pin is connected to the bus
>> reset.
>> +
>> +Example:
>> +
>> +pcie0: pcie@9b0 {
>> + compatible = "st,pcie", "snps,dw-pcie";
>> + device_type = "pci";
>> + reg = <0x09b0 0x4000>, /* dbi cntrl registers */
>> + <0x2fff 0x0001>, /* configuration space */
>> + <0x4000 0x8000>; /* lmi mem window */
>> + reg-names = "dbi", "config", "mem-window";
>> + st,syscfg = <&syscfg_core 0xd8 0xe0>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
>> non-prefetchable memory */
>
> No i/o support?
>
Exactly there is no i/o support.
>> + num-lanes = <1>;
>> + interrupts = ;
>> + interrupt-names = "msi";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT A */
>> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT B */
>> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT C */
>> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /*
>> INT D */
>> +
>> + resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
>> +<&softreset STIH407_PCIE0_SOFTRESET>;
>> + reset-names = "powerdown",
>> + "softreset";
>> + phys = <&phy_port0 PHY_TYPE_PCIE>;
>> + phy-names = "pcie";
>> +};
>> --
>> 1.9.1
>>
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Re: [PATCH v4 0/4] PCI: st: provide support for dw pcie
No problem Thanks Gabriel On 17 September 2015 at 16:59, Bjorn Helgaas wrote: > Hi Gabriel, > > On Thu, Aug 27, 2015 at 02:34:13PM +0200, Gabriel Fernandez wrote: >> >> This patchset is based on v4.2-rc1 and is based on >> [PATCH v8 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 >> patchset from Zhou Wang. >> >> Changes in v4: >> - Remove pci: designware: remove my pci_common_init_dev() patch and >> use [PATCH v8 3/6] PCI: designware: Add ARM64 support instead. >> This patch is a good solution for me to disable IO support. >> - add __init to st_pcie_probe() and use module_init() instead >> device_initcall() to prevent the probe function from being >> deferred and to prevent module unloading. >> >> Changes in v3: >> - Remove power management functions (was not fully tested) >> - Remove configuration space range from dt binding >> - Remove pci_common_init_dev() call in pcie-designware.c to avoid >>default IO space declaration. >> >> Changes in v2: >> - comestic corrections in device tree binding >> - add pci-st.c into MAINTAINERS >> - remove st_pcie_ops structure to avoid another level of indirection >> - remove nasty busy-loop >> - remove useless test using virt_to_phys() >> - move disable io support into dw-pcie driver >> >> I don't change the st_pcie_abort_handler() function because abort handling >> is masked during boot. >> >> >> This patch-set introduces a STMicroelectronics PCIe controller. >> It's based on designware PCIe driver. >> >> Gabriel Fernandez (4): >> ARM: STi: Kconfig update for PCIe support >> PCI: st: Add Device Tree bindings for sti pcie >> PCI: st: Provide support for the sti PCIe controller >> MAINTAINERS: Add pci-st.c to ARCH/STI architecture > > Rob had some questions, so I'm waiting for an update that responds to > those. When you post that, can you also squash the last two patches > together? > > Thanks, > Bjorn > >> Documentation/devicetree/bindings/pci/st-pcie.txt | 53 ++ >> MAINTAINERS | 1 + >> arch/arm/mach-sti/Kconfig | 2 + >> drivers/pci/host/Kconfig | 9 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pci-st.c | 583 >> ++ >> 6 files changed, 649 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt >> create mode 100644 drivers/pci/host/pci-st.c >> >> -- >> 1.9.1 >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation
replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x" Signed-off-by: Gabriel Fernandez --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index d8b168e..e2c6db0 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -21,8 +21,8 @@ Required properties: "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" - "sst,plls-c32-cx_0","st,clkgen-plls-c32" - "sst,plls-c32-cx_1","st,clkgen-plls-c32" + "st,plls-c32-cx_0", "st,clkgen-plls-c32" + "st,plls-c32-cx_1", "st,clkgen-plls-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Correction in dts files are already done here:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x")
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 83ccf14..576cd03 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = {
},
{
.compatible = "st,stih407-quadfs660-C",
- .data = &st_fs660c32_C_407
+ .data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
- .data = &st_fs660c32_D_407
+ .data = &st_fs660c32_D
},
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 47a38a9..b2a332c 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1,24),
@@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0
= {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1,24),
@@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0,
},
{
- .compatible = "st,stih407-plls-c32-c0_0",
- .data = &st_pll3200c32_407_c0_0,
+ .compatible = "st,plls-c32-cx_0",
+ .data = &st_pll3200c32_cx_0,
},
{
- .compatible = "st,stih407-plls-c32-c0_1",
- .data = &st_pll3200c32_407_c0_1,
+ .compatible = "st,plls-c32-cx_1",
+ .data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
--
1.9.1
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[RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2
This patch set fixes a kernel crash :
[2.433152] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
4.2.0-rc7-next-20150821 #134
[2.440713] Hardware name: STiH415/416 SoC with Flattened Device Tree
[2.447173] [] (unwind_backtrace) from []
(show_stack+0x10/0x14)
[2.454914] [] (show_stack) from []
(dump_stack+0x8c/0x9c)
[2.462145] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[2.468845] [] (Ldiv0) from []
(flexgen_round_rate+0x54/0x68)
[2.476327] [] (flexgen_round_rate) from []
(clk_calc_new_rates+0x1bc/0x22c)
[2.485109] [] (clk_calc_new_rates) from []
(clk_core_set_rate_nolock+0x44/0xac)
[2.494235] [] (clk_core_set_rate_nolock) from []
(clk_set_rate+0x24/0x34)
[2.502845] [] (clk_set_rate) from []
(st_mmcss_cconfig+0x5c/0xfc)
[2.510763] [] (st_mmcss_cconfig) from []
(sdhci_st_probe+0xec/0x1fc)
[2.518946] [] (sdhci_st_probe) from []
(platform_drv_probe+0x44/0xa4)
[2.527209] [] (platform_drv_probe) from []
(driver_probe_device+0x204/0x2f0)
[2.536077] [] (driver_probe_device) from []
(__driver_attach+0x8c/0x90)
[2.544510] [] (__driver_attach) from []
(bus_for_each_dev+0x68/0x9c)
[2.552682] [] (bus_for_each_dev) from []
(bus_add_driver+0x19c/0x214)
[2.560941] [] (bus_add_driver) from []
(driver_register+0x78/0xf8)
[2.568941] [] (driver_register) from []
(do_one_initcall+0x8c/0x1d4)
[2.577115] [] (do_one_initcall) from []
(kernel_init_freeable+0x158/0x1f8)
[2.585818] [] (kernel_init_freeable) from []
(kernel_init+0x8/0xe8)
[2.593905] [] (kernel_init) from []
(ret_from_fork+0x14/0x2c)
[2.601467] Division by zero in kernel.
This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x")
Gabriel Fernandez (2):
dt-bindings: Fix tipo in st,clkgen-pll documentation
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
--
1.9.1
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Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
Hi Zhou,
You can add my Tested-by: Gabriel Fernandez
I tested your patchset with a STMicroelectronics PCIe controller.
This controller is based on designware PCIe driver and works on ARM32.
Please find my patchset here:
http://www.spinics.net/lists/kernel/msg2064266.html
Best Regards.
Gabriel.
On 25 August 2015 at 11:58, Zhou Wang wrote:
> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
> move related operations to dw_pcie_host_init.
>
> This patch also try to use of_pci_get_host_bridge_resources for ARM32 and
> ARM64
> according to the suggestion for Gabriele[1]
>
> Finally this patch reverts commit f4c55c5a3f7f "PCI: designware: Program ATU
> with untranslated address" based on 1/6 in this series. we delete *_mod_base
> in
> pcie-designware. This was discussed in [2]
>
> I have compiled the driver with multi_v7_defconfig. However, I don't have
> ARM32 PCIe related board to do test. It will be appreciated if someone could
> help to test it.
>
> Signed-off-by: Zhou Wang
> Signed-off-by: Gabriele Paoloni
> Signed-off-by: Arnd Bergmann
> Tested-By: James Morse
>
> [1] http://www.spinics.net/lists/linux-pci/msg42194.html
> [2] http://www.spinics.net/lists/arm-kernel/msg436779.html
> ---
> drivers/pci/host/pci-dra7xx.c | 14 +--
> drivers/pci/host/pci-keystone-dw.c | 2 +-
> drivers/pci/host/pcie-designware.c | 230
> +
> drivers/pci/host/pcie-designware.h | 14 +--
> 4 files changed, 90 insertions(+), 170 deletions(-)
>
> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> index 18ae7ff..ac401be 100644
> --- a/drivers/pci/host/pci-dra7xx.c
> +++ b/drivers/pci/host/pci-dra7xx.c
> @@ -141,15 +141,15 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
> {
> dw_pcie_setup_rc(pp);
>
> - if (pp->io_mod_base)
> - pp->io_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->io_base)
> + pp->io_base &= CPU_TO_BUS_ADDR;
>
> - if (pp->mem_mod_base)
> - pp->mem_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->mem_base)
> + pp->mem_base &= CPU_TO_BUS_ADDR;
>
> - if (pp->cfg0_mod_base) {
> - pp->cfg0_mod_base &= CPU_TO_BUS_ADDR;
> - pp->cfg1_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->cfg0_base) {
> + pp->cfg0_base &= CPU_TO_BUS_ADDR;
> + pp->cfg1_base &= CPU_TO_BUS_ADDR;
> }
>
> dra7xx_pcie_establish_link(pp);
> diff --git a/drivers/pci/host/pci-keystone-dw.c
> b/drivers/pci/host/pci-keystone-dw.c
> index f34892e..b1e4135 100644
> --- a/drivers/pci/host/pci-keystone-dw.c
> +++ b/drivers/pci/host/pci-keystone-dw.c
> @@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem
> *reg_virt)
> void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> {
> struct pcie_port *pp = &ks_pcie->pp;
> - u32 start = pp->mem.start, end = pp->mem.end;
> + u32 start = pp->mem->start, end = pp->mem->end;
> int i, tr_size;
>
> /* Disable BARs for inbound access */
> diff --git a/drivers/pci/host/pcie-designware.c
> b/drivers/pci/host/pcie-designware.c
> index c5d407c..e2d1898 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -11,6 +11,7 @@
> * published by the Free Software Foundation.
> */
>
> +#include
> #include
> #include
> #include
> @@ -69,16 +70,7 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> -static struct hw_pci dw_pci;
> -
> -static unsigned long global_io_offset;
> -
> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
> -{
> - BUG_ON(!sys->private_data);
> -
> - return sys->private_data;
> -}
> +static struct pci_ops dw_pcie_ops;
>
> int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
> {
> @@ -255,7 +247,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int
> irq)
> static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
> {
> int irq, pos0, i;
> - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
> + struct pcie_port *pp = desc->dev->bus->sysdata;
>
> pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
>order_base_2(no_irqs));
&g
[PATCH v4 1/4] ARM: STi: Kconfig update for PCIe support
Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 125865d..5f99e93 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -9,6 +9,8 @@ menuconfig ARCH_STI select ARCH_HAS_RESET_CONTROLLER select HAVE_ARM_SCU if SMP select ARCH_REQUIRE_GPIOLIB + select PCI_DOMAINS if PCI + select MIGHT_HAVE_PCI select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/4] PCI: st: Add Device Tree bindings for sti pcie
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
b/Documentation/devicetree/bindings/pci/st-pcie.txt
new file mode 100644
index 000..25fcab3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
@@ -0,0 +1,53 @@
+STMicroelectronics STi PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+ - compatible: "st,stih407-pcie"
+ - reg: base address and length of the pcie controller, mem-window address
+ and length available to the controller.
+ - interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+ - interrupt-names: Should be "msi". STi interrupt that is asserted when an
+ MSI is received.
+ - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
+ offset for IP configuration.
+ - resets, reset-names: the power-down and soft-reset lines of PCIe IP.
+ Associated names must be "powerdown" and "softreset".
+ - phys, phy-names: the phandle for the PHY device.
+ Associated name must be "pcie"
+
+Optional properties:
+ - reset-gpio: a GPIO spec to define which pin is connected to the bus reset.
+
+Example:
+
+pcie0: pcie@9b0 {
+ compatible = "st,pcie", "snps,dw-pcie";
+ device_type = "pci";
+ reg = <0x09b0 0x4000>, /* dbi cntrl registers */
+ <0x2fff 0x0001>, /* configuration space */
+ <0x4000 0x8000>; /* lmi mem window */
+ reg-names = "dbi", "config", "mem-window";
+ st,syscfg = <&syscfg_core 0xd8 0xe0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = ;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT
A */
+ <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT
B */
+ <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT
C */
+ <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT
D */
+
+ resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
+<&softreset STIH407_PCIE0_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ phys = <&phy_port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie";
+};
--
1.9.1
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[PATCH v4 3/4] PCI: st: Provide support for the sti PCIe controller
sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 583 ++ 3 files changed, 593 insertions(+) create mode 100644 drivers/pci/host/pci-st.c diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index c132bdd..db56b8f 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -145,4 +145,13 @@ config PCIE_IPROC_BCMA Say Y here if you want to use the Broadcom iProc PCIe controller through the BCMA bus interface +config PCI_ST + bool "ST PCIe controller" + depends on ARCH_STI || (ARM && COMPILE_TEST) + select PCIE_DW + help + Enable PCIe controller support on ST Socs. This controller is based + on Designware hardware and therefore the driver re-uses the + Designware core functions to implement the driver. + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 140d66f..c4024fa 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o +obj-$(CONFIG_PCI_ST) += pci-st.o diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c new file mode 100644 index 000..0e7aaa2 --- /dev/null +++ b/drivers/pci/host/pci-st.c @@ -0,0 +1,583 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PCI express Driver for sti SoCs. + * ST PCIe IPs are built around a Synopsys IP Core. + * + * Author: Fabrice Gasnier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define TRANSLATION_CONTROL0x900 +/* Controls if area is inclusive or exclusive */ +#define RC_PASS_ADDR_RANGE BIT(1) + +/* Base of area reserved for config accesses. Fixed size of 64K. */ +#define CFG_BASE_ADDRESS 0x92c +#define CFG_REGION_SIZE65536 +#define CFG_SPACE1_OFFSET 0x1000 + +/* First 4K of config space has this BDF (bus,device,function) */ +#define FUNC0_BDF_NUM 0x930 + +/* Mem regions */ +#define IN0_MEM_ADDR_START 0x964 +#define IN0_MEM_ADDR_LIMIT 0x968 +#define IN1_MEM_ADDR_START 0x974 +#define IN1_MEM_ADDR_LIMIT 0x978 + +/* This actually contains the LTSSM state machine state */ +#define PORT_LOGIC_DEBUG_REG_0 0x728 + +/* LTSSM state machine values */ +#define DEBUG_REG_0_LTSSM_MASK 0x1f +#define S_DETECT_QUIET 0x00 +#define S_DETECT_ACT 0x01 +#define S_POLL_ACTIVE 0x02 +#define S_POLL_COMPLIANCE 0x03 +#define S_POLL_CONFIG 0x04 +#define S_PRE_DETECT_QUIET 0x05 +#define S_DETECT_WAIT 0x06 +#define S_CFG_LINKWD_START 0x07 +#define S_CFG_LINKWD_ACEPT 0x08 +#define S_CFG_LANENUM_WAIT 0x09 +#define S_CFG_LANENUM_ACEPT0x0A +#define S_CFG_COMPLETE 0x0B +#define S_CFG_IDLE 0x0C +#define S_RCVRY_LOCK 0x0D +#define S_RCVRY_SPEED 0x0E +#define S_RCVRY_RCVRCFG0x0F +#define S_RCVRY_IDLE 0x10 +#define S_L0 0x11 +#define S_L0S 0x12 +#define S_L123_SEND_EIDLE 0x13 +#define S_L1_IDLE 0x14 +#define S_L2_IDLE 0x15 +#define S_L2_WAKE 0x16 +#define S_DISABLED_ENTRY 0x17 +#define S_DISABLED_IDLE0x18 +#define S_DISABLED 0x19 +#define S_LPBK_ENTRY 0x1A +#define S_LPBK_ACTIVE 0x1B +#define S_LPBK_EXIT0x1C +#define S_LPBK_EXIT_TIMEOUT0x1D +#define S_HOT_RESET_ENTRY 0x1E +#define S_HOT_RESET0x1F + +/* syscfg bits */ +#define PCIE_SYS_INT BIT(5) +#define PCIE_APP_REQ_RETRY_EN BIT(3) +#define PCIE_APP_LTSSM_ENABLE BIT(2) +#define PCIE_APP_INIT_RST BIT(1) +#define PCIE_DEVICE_TYPE BIT(0) +#define PCIE_DEFAULT_VAL PCIE_DEVICE_TYPE + +/* Time to wait between testing the link in msecs (hardware poll interval) */ +#define LINK_LOOP_DELAY_MS 1 +/* Total amount of time to wait for
[PATCH v4 4/4] MAINTAINERS: Add pci-st.c to ARCH/STI architecture
This patch adds the pci-st.c pci driver found on STMicroelectronics SoC's into the STI arch section of the maintainers file. Signed-off-by: Gabriel Fernandez --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8133cef..af5034f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1506,6 +1506,7 @@ F:drivers/clocksource/arm_global_timer.c F: drivers/i2c/busses/i2c-st.c F: drivers/media/rc/st_rc.c F: drivers/mmc/host/sdhci-st.c +F: drivers/pci/host/pci-st.c F: drivers/phy/phy-miphy28lp.c F: drivers/phy/phy-miphy365x.c F: drivers/phy/phy-stih407-usb.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/4] PCI: st: provide support for dw pcie
This patchset is based on v4.2-rc1 and is based on [PATCH v8 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 patchset from Zhou Wang. Changes in v4: - Remove pci: designware: remove my pci_common_init_dev() patch and use [PATCH v8 3/6] PCI: designware: Add ARM64 support instead. This patch is a good solution for me to disable IO support. - add __init to st_pcie_probe() and use module_init() instead device_initcall() to prevent the probe function from being deferred and to prevent module unloading. Changes in v3: - Remove power management functions (was not fully tested) - Remove configuration space range from dt binding - Remove pci_common_init_dev() call in pcie-designware.c to avoid default IO space declaration. Changes in v2: - comestic corrections in device tree binding - add pci-st.c into MAINTAINERS - remove st_pcie_ops structure to avoid another level of indirection - remove nasty busy-loop - remove useless test using virt_to_phys() - move disable io support into dw-pcie driver I don't change the st_pcie_abort_handler() function because abort handling is masked during boot. This patch-set introduces a STMicroelectronics PCIe controller. It's based on designware PCIe driver. Gabriel Fernandez (4): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller MAINTAINERS: Add pci-st.c to ARCH/STI architecture Documentation/devicetree/bindings/pci/st-pcie.txt | 53 ++ MAINTAINERS | 1 + arch/arm/mach-sti/Kconfig | 2 + drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 583 ++ 6 files changed, 649 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt create mode 100644 drivers/pci/host/pci-st.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] ARM: DT: STi: STiH418: Fix mmc0 clock configuration
This patch configure correctly the MMC-0 clock for STiH418 platform.
Signed-off-by: Gabriel Fernandez
Acked-by: Maxime Coquelin
---
arch/arm/boot/dts/stih418.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index 8160a75..965f881 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -99,5 +99,11 @@
phys = <&usb2_picophy2>;
phy-names = "usb";
};
+
+ mmc0: sdhci@0906 {
+ assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+ assigned-clock-parents = <&clk_s_c0_pll1 0>;
+ assigned-clock-rates = <2>;
+ };
};
};
--
1.9.1
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[PATCH v2 0/4] ST PLL improvement
Changes in v2: - Add const for st_pll4600c28_418_a9 structure - Use readl_relaxed_poll_timeout macro instead Jiffies - Add patch to enable stih418 A9 pll via DT. This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 ARM: STi: DT: Add support for stih418 A9 pll .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 + arch/arm/boot/dts/stih418-clock.dtsi | 2 +- drivers/clk/st/clkgen-mux.c| 3 + drivers/clk/st/clkgen-pll.c| 469 - drivers/clk/st/clkgen.h| 2 + 5 files changed, 468 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 92 -
1 file changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index b2a332c..7ee485d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include "clkgen.h"
@@ -43,6 +44,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
struct clkgen_pll_data {
struct clkgen_field pdn_status;
+ struct clkgen_field pdn_ctrl;
struct clkgen_field locked_status;
struct clkgen_field mdiv;
struct clkgen_field ndiv;
@@ -62,6 +64,7 @@ static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0x10,0x1,0),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -70,6 +73,7 @@ static const struct clkgen_pll_data st_pll1600c65_ax = {
static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0xC, 0x1,1),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -79,6 +83,7 @@ static const struct clkgen_pll_data st_pll800c65_ax = {
static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,0),
.locked_status = CLKGEN_FIELD(0x4, 0x1,31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
@@ -96,6 +101,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,1),
.locked_status = CLKGEN_FIELD(0x10,0x1,31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x10,C32_IDF_MASK, 0x0),
@@ -114,6 +120,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
/* 415 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x6C,0x1,0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
@@ -125,6 +132,7 @@ static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x100, 0x1,0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
@@ -137,7 +145,8 @@ static const struct clkgen_pll_data st_pll3200c32_ddr_415 =
{
};
static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
- .pdn_status = CLKGEN_FIELD(0x144, 0x1,3),
+ .pdn_status = CLKGEN_FIELD(0x4, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x4, 0x1,0),
.locked_status = CLKGEN_FIELD(0x168, 0x1,0),
.ldf= CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
@@ -149,6 +158,7 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_415 =
{
/* 416 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x
[PATCH v2 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3 +
drivers/clk/st/clkgen-pll.c | 185 ++--
drivers/clk/st/clkgen.h | 2 +
3 files changed, 182 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4f7f6c0..5dc5ce2 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_divmux_lock);
static DEFINE_SPINLOCK(clkgenf_lock);
@@ -576,6 +577,7 @@ static struct clkgen_mux_data stih415_a9_mux_data = {
.offset = 0,
.shift = 1,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static struct clkgen_mux_data stih416_a9_mux_data = {
.offset = 0,
@@ -586,6 +588,7 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
.shift = 0,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static const struct of_device_id mux_of_match[] = {
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 7ee485d..94e5a0b 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -23,6 +23,7 @@
#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
+DEFINE_SPINLOCK(clkgen_a9_lock);
/*
* Common PLL configuration register bits for PLL800 and PLL1600 C65
@@ -39,6 +40,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
#define C32_IDF_MASK (0x7)
#define C32_ODF_MASK (0x3f)
#define C32_LDF_MASK (0x7f)
+#define C32_CP_MASK (0x1f)
#define C32_MAX_ODFS (4)
@@ -51,15 +53,20 @@ struct clkgen_pll_data {
struct clkgen_field pdiv;
struct clkgen_field idf;
struct clkgen_field ldf;
+ struct clkgen_field cp;
unsigned int num_odfs;
struct clkgen_field odf[C32_MAX_ODFS];
struct clkgen_field odf_gate[C32_MAX_ODFS];
+ bool switch2pll_en;
+ struct clkgen_field switch2pll;
+ spinlock_t *lock;
const struct clk_ops *ops;
};
static const struct clk_ops st_pll1600c65_ops;
static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
+static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
@@ -242,7 +249,11 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.num_odfs = 1,
.odf= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
- .ops= &stm_pll3200c32_ops,
+ .switch2pll_en = true,
+ .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK,1),
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll3200c32_a9_ops,
};
/**
@@ -268,10 +279,26 @@ struct clkgen_pll {
struct clk_hw hw;
struct clkgen_pll_data *data;
void __iomem*regs_base;
+ spinlock_t *lock;
+
+ u32 ndiv;
+ u32 idf;
+ u32 odf;
+ u32 cp;
};
#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
+struct stm_pll {
+ unsigned long mdiv;
+ unsigned long ndiv;
+ unsigned long pdiv;
+ unsigned long odf;
+ unsigned long idf;
+ unsigned long ldf;
+ unsigned long cp;
+};
+
static int clkgen_pll_is_locked(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
@@ -303,8 +330,12 @@ static int __clkgen_pll_enable(struct clk_hw *hw)
ret = readl_relaxed_poll_timeout(base + field->offset, reg,
!!((reg >> field->shift) & field->mask), 0, 1);
- if (!ret)
+ if (!ret) {
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 0);
+
pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
+ }
return ret;
}
@@ -333,6 +364,9 @@ static void __clkgen_pll_disable(struct clk_hw *hw)
if (!clkgen_pll_is_enabled(hw))
return;
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 1);
+
CLKGEN_WRITE(pll, pdn_ctrl, 1);
pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
@@ -403,6 +437,67 @@ static unsigned long recalc_stm_pll1600c65(struct clk_hw
*hw,
return rate;
}
+static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
+ struct stm_pll
[PATCH v2 4/4] ARM: STi: DT: Add support for stih418 A9 pll
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9",
"st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
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[PATCH v2 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
drivers/clk/st/clkgen-pll.c| 194 +
2 files changed, 195 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index e2c6db0..8f84c81 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -23,6 +23,7 @@ Required properties:
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,plls-c32-cx_0", "st,clkgen-plls-c32"
"st,plls-c32-cx_1", "st,clkgen-plls-c32"
+ "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 94e5a0b..3eb4ffb 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -44,6 +44,13 @@ DEFINE_SPINLOCK(clkgen_a9_lock);
#define C32_MAX_ODFS (4)
+/*
+ * PLL configuration register bits for PLL4600 C28
+ */
+#define C28_NDIV_MASK (0xff)
+#define C28_IDF_MASK (0x7)
+#define C28_ODF_MASK (0x3f)
+
struct clkgen_pll_data {
struct clkgen_field pdn_status;
struct clkgen_field pdn_ctrl;
@@ -68,6 +75,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
+static const struct clk_ops stm_pll4600c28_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
@@ -256,6 +264,22 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static struct clkgen_pll_data st_pll4600c28_418_a9 = {
+ /* 418 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1,0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
+ .idf= CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
+ .switch2pll_en = true,
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll4600c28_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -611,6 +635,163 @@ static unsigned long recalc_stm_pll1200c32(struct clk_hw
*hw,
return rate;
}
+/* PLL output structure
+ * FVCO >> /2 >> FVCOBY2 (no output)
+ * |> Divider (ODF) >> PHI
+ *
+ * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
+ *
+ * Rules:
+ * 4Mhz <= INFF input <= 350Mhz
+ * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
+ * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
+ * 1 <= i (register/dec value for IDF) <= 7
+ * 8 <= n (register/dec value for NDIV) <= 246
+ */
+
+static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
+ struct stm_pll *pll)
+{
+
+ unsigned long i, infin, n;
+ unsigned long deviation = ~0;
+ unsigned long new_freq, new_deviation;
+
+ /* Output clock range: 19Mhz to 3000Mhz */
+ if (output < 1900 || output > 30u)
+ return -EINVAL;
+
+ /* For better jitter, IDF should be smallest and NDIV must be maximum */
+ for (i = 1; i <= 7 && deviation; i++) {
+ /* INFIN checks */
+ infin = input / i;
+ if (infin < 400 || infin > 5000)
+ continue; /* Invalid case */
+
+ n = output / (infin * 2);
+ if (n < 8 || n > 246)
+ continue; /* Invalid case */
+ if (n < 246)
+ n++;/* To work around 'y' when n=x.y */
+
+ for (; n >= 8 && deviation; n--) {
+ new_freq = infin * 2 * n;
+
[PATCH 1/1] ARM: DT: STi: STiH418: Fix mmc0 clock configuration
This patch configure correctly the MMC-0 clock for STiH418 platform.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-b2199.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stih418-b2199.dts
b/arch/arm/boot/dts/stih418-b2199.dts
index 82eee39..7a03ca6 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -85,6 +85,10 @@
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
+
+ assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+ assigned-clock-parents = <&clk_s_c0_pll1 0>;
+ assigned-clock-rates = <2>;
};
miphy28lp_phy: miphy28lp@9b22000 {
--
1.9.1
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[PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation
replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x" Signed-off-by: Gabriel Fernandez --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index d8b168e..e2c6db0 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -21,8 +21,8 @@ Required properties: "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" - "sst,plls-c32-cx_0","st,clkgen-plls-c32" - "sst,plls-c32-cx_1","st,clkgen-plls-c32" + "st,plls-c32-cx_0", "st,clkgen-plls-c32" + "st,plls-c32-cx_1", "st,clkgen-plls-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Correction in dts files are already done here:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x")
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 83ccf14..576cd03 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = {
},
{
.compatible = "st,stih407-quadfs660-C",
- .data = &st_fs660c32_C_407
+ .data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
- .data = &st_fs660c32_D_407
+ .data = &st_fs660c32_D
},
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 47a38a9..b2a332c 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1,24),
@@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0
= {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1,24),
@@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0,
},
{
- .compatible = "st,stih407-plls-c32-c0_0",
- .data = &st_pll3200c32_407_c0_0,
+ .compatible = "st,plls-c32-cx_0",
+ .data = &st_pll3200c32_cx_0,
},
{
- .compatible = "st,stih407-plls-c32-c0_1",
- .data = &st_pll3200c32_407_c0_1,
+ .compatible = "st,plls-c32-cx_1",
+ .data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
--
1.9.1
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[PATCH 0/2] ST PLL fixes for 4.3
Should be apply with
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x")
to avoid broken compatibility.
Gabriel Fernandez (2):
dt-bindings: Fix tipo in st,clkgen-pll documentation
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
--
1.9.1
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Re: [PATCH v3 0/5] PCI: st: provide support for dw pcie
Hi Bjorn, To be honest I'm wainting that Zhou patch (PCI: designware: Add ARM64 support) is accepted. Because this patch allows to remove "pci: designware: remove pci_common_init_dev()" from my patchset. I think it's more judicious to do that. I can send a v4 based on Zhou patchset ([PATCH v6 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05) if you want ? Best Regards Gabriel. On 14 August 2015 at 16:53, Bjorn Helgaas wrote: > On Fri, Apr 10, 2015 at 11:12:43AM +0200, Gabriel FERNANDEZ wrote: >> Changes in v3: >> - Remove power management functions (was not fully tested) >> - Remove configuration space range from dt binding >> - Remove pci_common_init_dev() call in pcie-designware.c to avoid >>default IO space declaration. >> >> Changes in v2: >> - comestic corrections in device tree binding >> - add pci-st.c into MAINTAINERS >> - remove st_pcie_ops structure to avoid another level of indirection >> - remove nasty busy-loop >> - remove useless test using virt_to_phys() >> - move disable io support into dw-pcie driver >> >> I don't change the st_pcie_abort_handler() function because abort handling >> is masked during boot. >> >> >> This patch-set introduces a STMicroelectronics PCIe controller. >> It's based on designware PCIe driver. >> >> Gabriel Fernandez (5): >> ARM: STi: Kconfig update for PCIe support >> PCI: st: Add Device Tree bindings for sti pcie >> PCI: st: Provide support for the sti PCIe controller >> pci: designware: remove pci_common_init_dev() >> MAINTAINERS: Add pci-st.c to ARCH/STI architecture > > Hi Gabriel, > > I lost track of where we are with this. I *think* I'm waiting for a v4 > posting, but I haven't seen it yet. Let me know if I've missed something. > > Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] drivers: clk: st: Correct the pll-type for A9 for stih418
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
drivers/clk/st/clkgen-pll.c| 195 +
2 files changed, 196 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf..19dc0ca 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -23,6 +23,7 @@ Required properties:
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 04d66ee1d..7062943 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -42,6 +42,13 @@ DEFINE_SPINLOCK(clkgen_a9_lock);
#define C32_MAX_ODFS (4)
+/*
+ * PLL configuration register bits for PLL4600 C28
+ */
+#define C28_NDIV_MASK (0xff)
+#define C28_IDF_MASK (0x7)
+#define C28_ODF_MASK (0x3f)
+
struct clkgen_pll_data {
struct clkgen_field pdn_status;
struct clkgen_field pdn_ctrl;
@@ -66,6 +73,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
+static const struct clk_ops stm_pll4600c28_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
@@ -254,6 +262,22 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static struct clkgen_pll_data st_pll4600c28_418_a9 = {
+ /* 418 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1,0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1,0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
+ .idf= CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
+ .switch2pll_en = true,
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll4600c28_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -610,6 +634,164 @@ static unsigned long recalc_stm_pll1200c32(struct clk_hw
*hw,
return rate;
}
+/* PLL output structure
+ * FVCO >> /2 >> FVCOBY2 (no output)
+ * |> Divider (ODF) >> PHI
+ *
+ * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
+ *
+ * Rules:
+ * 4Mhz <= INFF input <= 350Mhz
+ * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
+ * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
+ * 1 <= i (register/dec value for IDF) <= 7
+ * 8 <= n (register/dec value for NDIV) <= 246
+ */
+
+static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
+ struct stm_pll *pll)
+{
+
+ unsigned long i, infin, n;
+ unsigned long deviation = ~0;
+ unsigned long new_freq, new_deviation;
+
+ /* Output clock range: 19Mhz to 3000Mhz */
+ if (output < 1900 || output > 30u)
+ return -EINVAL;
+
+ /* For better jitter, IDF should be smallest
+ and NDIV must be maximum */
+ for (i = 1; i <= 7 && deviation; i++) {
+ /* INFIN checks */
+ infin = input / i;
+ if (infin < 400 || infin > 5000)
+ continue; /* Invalid case */
+
+ n = output / (infin * 2);
+ if (n < 8 || n > 246)
+ continue; /* Invalid case */
+ if (n < 246)
+ n++;/* To work around 'y' when n=x.y */
+
+ for (; n >= 8 && deviation; n--) {
+ new_freq = infin * 2 * n;
+
[PATCH 1/3] drivers: clk: st: Support for enable/disable in Clockgen PLLs
The patch adds support for enable/disable of the Clockgen PLLs
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs
+ __enable
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 93 -
1 file changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 72d1c27..bd2fcd3 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -42,6 +42,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
struct clkgen_pll_data {
struct clkgen_field pdn_status;
+ struct clkgen_field pdn_ctrl;
struct clkgen_field locked_status;
struct clkgen_field mdiv;
struct clkgen_field ndiv;
@@ -61,6 +62,7 @@ static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0x10,0x1,0),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -69,6 +71,7 @@ static const struct clkgen_pll_data st_pll1600c65_ax = {
static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,19),
+ .pdn_ctrl = CLKGEN_FIELD(0xC, 0x1,1),
.locked_status = CLKGEN_FIELD(0x0, 0x1,31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
@@ -78,6 +81,7 @@ static const struct clkgen_pll_data st_pll800c65_ax = {
static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,0),
.locked_status = CLKGEN_FIELD(0x4, 0x1,31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
@@ -95,6 +99,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1,31),
+ .pdn_ctrl = CLKGEN_FIELD(0x18,0x1,1),
.locked_status = CLKGEN_FIELD(0x10,0x1,31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
.idf= CLKGEN_FIELD(0x10,C32_IDF_MASK, 0x0),
@@ -113,6 +118,7 @@ static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
/* 415 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x6C,0x1,0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
@@ -124,6 +130,7 @@ static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x100, 0x1,0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
@@ -136,7 +143,8 @@ static const struct clkgen_pll_data st_pll3200c32_ddr_415 =
{
};
static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
- .pdn_status = CLKGEN_FIELD(0x144, 0x1,3),
+ .pdn_status = CLKGEN_FIELD(0x4, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x4, 0x1,0),
.locked_status = CLKGEN_FIELD(0x168, 0x1,0),
.ldf= CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
.idf= CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
@@ -148,6 +156,7 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_415 =
{
/* 416 specific */
static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1,0),
+ .pdn_ctrl = CLKGEN_FIELD(0x0, 0x1,0),
.locked_status = CLKGEN_FIELD(0x6C,0x1,0),
.ndiv = CLKGEN_FIELD(0x8
[PATCH 2/3] drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3 +
drivers/clk/st/clkgen-pll.c | 182 ++--
drivers/clk/st/clkgen.h | 2 +
3 files changed, 180 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 717c4a9..a75633b 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_divmux_lock);
static DEFINE_SPINLOCK(clkgenf_lock);
@@ -575,6 +576,7 @@ static struct clkgen_mux_data stih415_a9_mux_data = {
.offset = 0,
.shift = 1,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static struct clkgen_mux_data stih416_a9_mux_data = {
.offset = 0,
@@ -585,6 +587,7 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
.shift = 0,
.width = 2,
+ .lock = &clkgen_a9_lock,
};
static const struct of_device_id mux_of_match[] = {
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index bd2fcd3..04d66ee1d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -21,6 +21,7 @@
#include "clkgen.h"
static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
+DEFINE_SPINLOCK(clkgen_a9_lock);
/*
* Common PLL configuration register bits for PLL800 and PLL1600 C65
@@ -37,6 +38,7 @@ static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
#define C32_IDF_MASK (0x7)
#define C32_ODF_MASK (0x3f)
#define C32_LDF_MASK (0x7f)
+#define C32_CP_MASK (0x1f)
#define C32_MAX_ODFS (4)
@@ -49,15 +51,20 @@ struct clkgen_pll_data {
struct clkgen_field pdiv;
struct clkgen_field idf;
struct clkgen_field ldf;
+ struct clkgen_field cp;
unsigned int num_odfs;
struct clkgen_field odf[C32_MAX_ODFS];
struct clkgen_field odf_gate[C32_MAX_ODFS];
+ bool switch2pll_en;
+ struct clkgen_field switch2pll;
+ spinlock_t *lock;
const struct clk_ops *ops;
};
static const struct clk_ops st_pll1600c65_ops;
static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
+static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops st_pll1200c32_ops;
static const struct clkgen_pll_data st_pll1600c65_ax = {
@@ -240,7 +247,11 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.num_odfs = 1,
.odf= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1,28) },
- .ops= &stm_pll3200c32_ops,
+ .switch2pll_en = true,
+ .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK,1),
+ .switch2pll = CLKGEN_FIELD(0x1a4, 0x1,1),
+ .lock = &clkgen_a9_lock,
+ .ops= &stm_pll3200c32_a9_ops,
};
/**
@@ -266,10 +277,26 @@ struct clkgen_pll {
struct clk_hw hw;
struct clkgen_pll_data *data;
void __iomem*regs_base;
+ spinlock_t *lock;
+
+ u32 ndiv;
+ u32 idf;
+ u32 odf;
+ u32 cp;
};
#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
+struct stm_pll {
+ unsigned long mdiv;
+ unsigned long ndiv;
+ unsigned long pdiv;
+ unsigned long odf;
+ unsigned long idf;
+ unsigned long ldf;
+ unsigned long cp;
+};
+
static int clkgen_pll_is_locked(struct clk_hw *hw)
{
struct clkgen_pll *pll = to_clkgen_pll(hw);
@@ -304,6 +331,9 @@ static int __clkgen_pll_enable(struct clk_hw *hw)
cpu_relax();
}
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 0);
+
pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
return ret;
@@ -333,6 +363,9 @@ static void __clkgen_pll_disable(struct clk_hw *hw)
if (!clkgen_pll_is_enabled(hw))
return;
+ if (pll->data->switch2pll_en)
+ CLKGEN_WRITE(pll, switch2pll, 1);
+
CLKGEN_WRITE(pll, pdn_ctrl, 1);
pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
@@ -403,6 +436,67 @@ static unsigned long recalc_stm_pll1600c65(struct clk_hw
*hw,
return rate;
}
+static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
+ struct stm_pll *pll)
+{
+ unsigned long i, n;
+ unsigned long deviation = ~0;
+ unsigned long new_freq;
+ long new_deviation;
+ /* Charge pump table: highest ndiv value for cp=6 to 25 *
[PATCH 0/3] ST PLL improvement
This patchset adds: * Enable/Disable support for Clockgen PLLs. * A new a9 pll for stih418 platform. * PLL rate change implementation for DVFS Gabriel Fernandez (3): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 + drivers/clk/st/clkgen-mux.c| 3 + drivers/clk/st/clkgen-pll.c| 470 - drivers/clk/st/clkgen.h| 2 + 4 files changed, 468 insertions(+), 8 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/9] drivers: clk: st: Incorrect register offset used for lock_status
Incorrect register offset used for sthi407 clockgenC
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e94197f..e6d7073 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -340,7 +340,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
CLKGEN_FIELD(0x30c, 0xf, 20),
CLKGEN_FIELD(0x310, 0xf, 20) },
.lockstatus_present = true,
- .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
.powerup_polarity = 1,
.standby_polarity = 1,
.pll_ops= &st_quadfs_pll_c32_ops,
--
1.9.1
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Re: [PATCH 1/9] drivers: clk: st: Incorrect clocks status
Hi Stephen,
Can you drop also this patch because it's concerns an old platform and
there no values to make more changes.
BR
Gabriel.
On 25 June 2015 at 10:41, Gabriel Fernandez
wrote:
> Hi Stephen,
>
> Thanks for reviewing
>
>
> On 24 June 2015 at 22:02, Stephen Boyd wrote:
>> On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
>>> In the clk_summary output, the h/w status of DivMux is incorrect
>>> (Parent and Enable status), since the clk_mux_ops.get_parent()
>>> returns -ERRCODE when clock is OFF.
>>>
>>> Signed-off-by: Pankaj Dev
>>> Signed-off-by: Gabriel Fernandez
>>> ---
>>> drivers/clk/st/clkgen-mux.c | 15 +--
>>> 1 file changed, 9 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
>>> index 4fbe6e0..c94b56b 100644
>>> --- a/drivers/clk/st/clkgen-mux.c
>>> +++ b/drivers/clk/st/clkgen-mux.c
>>> @@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
>>>
>>> __clk_hw_set_clk(mux_hw, hw);
>>>
>>> - return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
>>> + return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
>>
>> Useless parentheses around it all, please drop.
>>
> Ok
>
>>> }
>>>
>>> static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>> @@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>>
>>> __clk_hw_set_clk(mux_hw, hw);
>>>
>>> - genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>>> - if ((s8)genamux->muxsel < 0) {
>>> - pr_debug("%s: %s: Invalid parent, setting to default.\n",
>>> - __func__, __clk_get_name(hw->clk));
>>> - genamux->muxsel = 0;
>>> + if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
>>> + genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>>
>> Hm.. maybe we should fix clk_mux_ops to return 0 if it can't find the
>> parent? Or when this clock is registered we should read the hardware and
>> set a default parent so that we can't get an error code here.
>>
> I 'll try the second solution.
>
> Best regards
>
> Gabriel
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
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Re: [PATCH 8/9] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Hi Stephen, Sorry for the delay i was in day off. Yes it's just a cleanup but it's to prepare introduction of new platform which use this PLL. If you want apply only fixes we can drop these last two patches. And in a second phase, deals with Maxime to avoid break compatibility. BR Gabriel. On 2 July 2015 at 18:59, Stephen Boyd wrote: > On 06/23, Gabriel Fernandez wrote: >> Use a generic name for this kind of PLL >> >> Signed-off-by: Gabriel Fernandez > > Is this just a cleanup/nicety? I could take this patch but patch > 9 needs to go through arm-soc and then we have to deal with DT > incompatibility. How about we drop these last two patches? > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/9] drivers: clk: st: Incorrect clocks status
Hi Stephen,
Thanks for reviewing
On 24 June 2015 at 22:02, Stephen Boyd wrote:
> On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
>> In the clk_summary output, the h/w status of DivMux is incorrect
>> (Parent and Enable status), since the clk_mux_ops.get_parent()
>> returns -ERRCODE when clock is OFF.
>>
>> Signed-off-by: Pankaj Dev
>> Signed-off-by: Gabriel Fernandez
>> ---
>> drivers/clk/st/clkgen-mux.c | 15 +--
>> 1 file changed, 9 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
>> index 4fbe6e0..c94b56b 100644
>> --- a/drivers/clk/st/clkgen-mux.c
>> +++ b/drivers/clk/st/clkgen-mux.c
>> @@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
>>
>> __clk_hw_set_clk(mux_hw, hw);
>>
>> - return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
>> + return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
>
> Useless parentheses around it all, please drop.
>
Ok
>> }
>>
>> static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>> @@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>
>> __clk_hw_set_clk(mux_hw, hw);
>>
>> - genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>> - if ((s8)genamux->muxsel < 0) {
>> - pr_debug("%s: %s: Invalid parent, setting to default.\n",
>> - __func__, __clk_get_name(hw->clk));
>> - genamux->muxsel = 0;
>> + if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
>> + genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>
> Hm.. maybe we should fix clk_mux_ops to return 0 if it can't find the
> parent? Or when this clock is registered we should read the hardware and
> set a default parent so that we can't get an error code here.
>
I 'll try the second solution.
Best regards
Gabriel
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
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[PATCH 2/9] drivers: clk: st: Incorrect register offset used for lock_status
Incorrect register offset used for sthi407 clockgenC
Signed-off-by: Pankaj Dev
---
drivers/clk/st/clkgen-fsyn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e94197f..e6d7073 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -340,7 +340,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
CLKGEN_FIELD(0x30c, 0xf, 20),
CLKGEN_FIELD(0x310, 0xf, 20) },
.lockstatus_present = true,
- .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
.powerup_polarity = 1,
.standby_polarity = 1,
.pll_ops= &st_quadfs_pll_c32_ops,
--
1.9.1
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[PATCH 5/9] drivers: clk: st: Fix flexgen lock init
From: Giuseppe Cavallaro
While proving lock, the following warning happens
and it is fixed after initializing lock in the setup
function
INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33
[] (unwind_backtrace+0x0/0xf4) from []
(show_stack+0x10/0x14)
[] (show_stack+0x10/0x14) from []
(__lock_acquire+0x900/0xb14)
[] (__lock_acquire+0x900/0xb14) from []
(lock_acquire+0x68/0x7c)
[] (lock_acquire+0x68/0x7c) from []
(_raw_spin_lock_irqsave+0x48/0x5c)
[] (_raw_spin_lock_irqsave+0x48/0x5c) from []
(clk_gate_endisable+0x28/0x88)
[] (clk_gate_endisable+0x28/0x88) from []
(clk_gate_enable+0xc/0x14)
[] (clk_gate_enable+0xc/0x14) from []
(flexgen_enable+0x28/0x40)
[] (flexgen_enable+0x28/0x40) from []
(__clk_enable+0x5c/0x9c)
[] (__clk_enable+0x5c/0x9c) from [] (clk_enable+0x18/0x2c)
[] (clk_enable+0x18/0x2c) from []
(st_lpc_of_register+0xc0/0x248)
[] (st_lpc_of_register+0xc0/0x248) from []
(clocksource_of_init+0x34/0x58)
[] (clocksource_of_init+0x34/0x58) from []
(sti_timer_init+0x10/0x18)
[] (sti_timer_init+0x10/0x18) from [] (time_init+0x20/0x30)
[] (time_init+0x20/0x30) from [] (start_kernel+0x20c/0x2e8)
[] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074)
Signed-off-by: Giuseppe Cavallaro
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clk-flexgen.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 657ca14..be06d2a 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -303,6 +303,8 @@ static void __init st_of_flexgen_setup(struct device_node
*np)
if (!rlock)
goto err;
+ spin_lock_init(rlock);
+
for (i = 0; i < clk_data->clk_num; i++) {
struct clk *clk;
const char *clk_name;
--
1.9.1
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[PATCH 4/9] drivers: clk: st: Fix FSYN channel values
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez --- drivers/clk/st/clkgen-fsyn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index e7e6782..9e26099 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -489,7 +489,7 @@ static int quadfs_pll_is_enabled(struct clk_hw *hw) struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); u32 npda = CLKGEN_READ(pll, npda); - return !!npda; + return pll->data->powerup_polarity ? !npda : !!npda; } static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs, @@ -774,7 +774,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw) if (fs->lock) spin_lock_irqsave(fs->lock, flags); - CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity); + CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity); if (fs->lock) spin_unlock_irqrestore(fs->lock, flags); -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/9] drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
This patch fixes the mux bit-setting for ClockgenA9.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 3919a67..ecb492e 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -586,7 +586,7 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
};
static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
- .shift = 1,
+ .shift = 0,
.width = 2,
};
--
1.9.1
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[PATCH 8/9] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index d9eb2e1..a2239cf 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -306,7 +306,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -349,7 +349,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1076,11 +1076,11 @@ static const struct of_device_id quadfs_of_match[] = {
},
{
.compatible = "st,stih407-quadfs660-C",
- .data = &st_fs660c32_C_407
+ .data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
- .data = &st_fs660c32_D_407
+ .data = &st_fs660c32_D
},
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 72d1c27..6742b3d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,7 +192,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1,24),
@@ -204,7 +204,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0
= {
.ops= &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1,24),
@@ -623,12 +623,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0,
},
{
- .compatible = "st,stih407-plls-c32-c0_0",
- .data = &st_pll3200c32_407_c0_0,
+ .compatible = "st,plls-c32-cx_0",
+ .data = &st_pll3200c32_cx_0,
},
{
- .compatible = "st,stih407-plls-c32-c0_1",
- .data = &st_pll3200c32_407_c0_1,
+ .compatible = "st,plls-c32-cx_1",
+ .data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
--
1.9.1
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[PATCH 6/9] drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
From: Pankaj Dev
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
is called
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clk-flexgen.c | 2 +-
drivers/clk/st/clkgen-fsyn.c | 2 +-
drivers/clk/st/clkgen-mux.c | 8 +---
drivers/clk/st/clkgen-pll.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index be06d2a..8dd8cce 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -190,7 +190,7 @@ static struct clk *clk_register_flexgen(const char *name,
init.name = name;
init.ops = &flexgen_ops;
- init.flags = CLK_IS_BASIC | flexgen_flags;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 9e26099..d9eb2e1 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -635,7 +635,7 @@ static struct clk * __init st_clk_register_quadfs_pll(
init.name = name;
init.ops = quadfs->pll_ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name;
init.num_parents = 1;
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index c94b56b..3919a67 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -239,7 +239,7 @@ static struct clk *clk_register_genamux(const char *name,
init.name = name;
init.ops = &clkgena_divmux_ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = parent_names;
init.num_parents = num_parents;
@@ -516,7 +516,8 @@ static void __init st_of_clkgena_prediv_setup(struct
device_node *np)
0, &clk_name))
return;
- clk = clk_register_divider_table(NULL, clk_name, parent_name, 0,
+ clk = clk_register_divider_table(NULL, clk_name, parent_name,
+CLK_GET_RATE_NOCACHE,
reg + data->offset, data->shift, 1,
0, data->table, NULL);
if (IS_ERR(clk))
@@ -789,7 +790,8 @@ static void __init st_of_clkgen_vcc_setup(struct
device_node *np)
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
-data->clk_flags);
+data->clk_flags |
+CLK_GET_RATE_NOCACHE);
if (IS_ERR(clk)) {
kfree(gate);
kfree(div);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 1065322..72d1c27 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -406,7 +406,7 @@ static struct clk * __init clkgen_pll_register(const char
*parent_name,
init.name = clk_name;
init.ops = pll_data->ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name;
init.num_parents = 1;
--
1.9.1
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[PATCH 9/9] ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf..d8b168e 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_0","st,clkgen-plls-c32"
+ "sst,plls-c32-cx_1","st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index e65744f..ad45f5e 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -134,7 +134,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -143,7 +143,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 6b5803a..d1f2aca 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 0ab23da..148e177 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1",
"st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1",
"st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
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[PATCH 1/9] drivers: clk: st: Incorrect clocks status
In the clk_summary output, the h/w status of DivMux is incorrect
(Parent and Enable status), since the clk_mux_ops.get_parent()
returns -ERRCODE when clock is OFF.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4fbe6e0..c94b56b 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
__clk_hw_set_clk(mux_hw, hw);
- return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
+ return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
}
static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
@@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
__clk_hw_set_clk(mux_hw, hw);
- genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
- if ((s8)genamux->muxsel < 0) {
- pr_debug("%s: %s: Invalid parent, setting to default.\n",
- __func__, __clk_get_name(hw->clk));
- genamux->muxsel = 0;
+ if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
+ genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
+ if ((s8)genamux->muxsel < 0) {
+ pr_debug("%s: %s: Invalid parent, setting to
default.\n",
+ __func__, __clk_get_name(hw->clk));
+ genamux->muxsel = 0;
+ }
}
return genamux->muxsel;
@@ -254,6 +256,7 @@ static struct clk *clk_register_genamux(const char *name,
} else {
genamux->mux.reg = reg + muxdata->mux_offset;
}
+ genamux->muxsel = CKGAX_CLKOPSRC_SWITCH_OFF;
for (i = 0; i < NUM_INPUTS; i++) {
/*
--
1.9.1
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[PATCH 0/9] clk: ST clock fixes
This first patch-set contains various clock fixes for ST SoC. Gabriel Fernandez (7): drivers: clk: st: Incorrect clocks status drivers: clk: st: Incorrect register offset used for lock_status drivers: clk: st: Remove unused code drivers: clk: st: Fix FSYN channel values drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Giuseppe Cavallaro (1): drivers: clk: st: Fix flexgen lock init Pankaj Dev (1): drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- arch/arm/boot/dts/stih407-clock.dtsi | 4 ++-- arch/arm/boot/dts/stih410-clock.dtsi | 4 ++-- arch/arm/boot/dts/stih418-clock.dtsi | 4 ++-- drivers/clk/st/clk-flexgen.c | 4 +++- drivers/clk/st/clkgen-fsyn.c | 20 +++-- drivers/clk/st/clkgen-mux.c| 25 +- drivers/clk/st/clkgen-pll.c| 14 ++-- 8 files changed, 41 insertions(+), 38 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/9] drivers: clk: st: Remove unused code
Remove this duplicated code due to a bad copy / paste.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e6d7073..e7e6782 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -1082,10 +1082,6 @@ static const struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih407-quadfs660-D",
.data = &st_fs660c32_D_407
},
- {
- .compatible = "st,stih407-quadfs660-D",
- .data = (void *)&st_fs660c32_D_407
- },
{}
};
--
1.9.1
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Re: [PATCH v3 3/5] PCI: st: Provide support for the sti PCIe controller
Hi
Thanks for reviewing.
On 11 April 2015 at 16:55, Arnd Bergmann wrote:
> On Saturday 11 April 2015 12:17:57 Paul Bolle wrote:
>> Something I didn't spot in my first look at this patch.
>>
>> On Fri, 2015-04-10 at 11:12 +0200, Gabriel FERNANDEZ wrote:
>> > --- a/drivers/pci/host/Kconfig
>> > +++ b/drivers/pci/host/Kconfig
>> >
>> > +config PCI_ST
>> > + bool "ST PCIe controller"
>> > + depends on ARCH_STI || (ARM && COMPILE_TEST)
>> > + select PCIE_DW
>> > + help
>> > + Enable PCIe controller support on ST Socs. This controller is based
>> > + on Designware hardware and therefore the driver re-uses the
>> > + Designware core functions to implement the driver.
>>
>> You can't have ARCH_STI without ARM, so ARM will always be set if this
>> driver is enabled. Correct?
>
> Right, though the ARM dependency could soon be dropped, once the PCIE_DW
> driver can use generic infrastructure in the few places it relies on
> ARM specific code today.
>
>> > --- /dev/null
>> > +++ b/drivers/pci/host/pci-st.c
>>
>> > + if (IS_ENABLED(CONFIG_ARM)) {
>> > + /*
>> > + * We have to hook the abort handler so that we can intercept
>> > + * bus errors when doing config read/write that return UR,
>> > + * which is flagged up as a bus error
>> > + */
>> > + hook_fault_code(16+6, st_pcie_abort_handler, SIGBUS, 0,
>> > + "imprecise external abort");
>> > + }
>>
>> So, unless I'm missing something obvious here, IS_ENABLED(CONFIG_ARM)
>> will always evaluate to 1. Can't that test be dropped?
>
> I would leave it in, as it's quite likely to get reused with ARM64 at some
> point in the future (no, I don't know anything about ST's product plans,
> but everybody seems to be doing this).
>
> Arnd
Yes i agree with that.
Gabriel
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Re: [STLinux Kernel] [PATCH 0/4] clk: Provide support for always-on clocks
Hi Peter, Lee, With these series as they are, we need 'clk_ignore_unused' on sthi407-b2120.dts and stih418-b2199.dts. We have to modificate stih407-clock.dtsi and stih418-clock.dtsi in same way. BR Gabriel On 2 April 2015 at 10:12, Peter Griffin wrote: > Hi Lee, > > On Fri, 27 Feb 2015, Lee Jones wrote: > >> Some hardware contains bunches of clocks which must never be >> turned off. If drivers a) fail to obtain a reference to any >> of these or b) give up a previously obtained reference >> during suspend, the common clk framework will attempt to >> disable them and a platform can fail irrecoverably as a >> result. Usually the only way to recover from these failures >> is to reboot. >> >> To avoid either of these two scenarios from catastrophically >> disabling an otherwise perfectly healthy running system, >> clocks can be identified as always-on using this property >> from inside a clocksource's node. The CLK_IGNORE_UNUSED >> flag will be applied to each clock instance named in this >> property, thus preventing them from being shut down by the >> framework. > > Great stuff. > > One minor comment is that assuming this works on stih407 and stih410 > to the extent that the platform can now boot without clk_ignore_unused > kenel parameter then you should have an additional patch to remove > clk_ignore_unused from the default bootargs in stih407-b2120.dts and > stih410-b2120.dts files. > > Maxime - Is it possible for you to test this series on stih418-b2199 as > a well? As it could most likely also be removed from stih418-b2199.dts file > to, but neither Lee or myself have the hardware to test. > > Apart from that, for the series: - > Acked-by: Peter Griffin > > regards, > > Peter. > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller
Hi Bjorn, pci-st.c driver could be modular with modification of pcie-designware core driver. But as Fabrice said it should be another patchset. What do you prefer ? drop all the module related macros as mentioned by Paul ? or keep macros like other vendors do ? Thanks Gabriel On 18 March 2015 at 11:35, Paul Bolle wrote: > Hi Fabrice, > > Fabrice Gasnier schreef op wo 18-03-2015 om 09:49 [+0100]: >> On 03/16/2015 04:11 PM, Paul Bolle wrote: >> >> +config PCI_ST >> >> + bool "ST PCIe controller" >> > You add a bool Kconfig symbol. A week or two ago I saw some patches fly >> > by that - I think - allowed PCIe controllers to be built modular. >> >> Thanks for your review. >> >> Are you talking about "PCI: Export symbols of PCI functions" patch, that >> is part of a series >> named "pci: iproc: Add Broadcom iProc PCIe support" ? > > Yes, that is the series I was thinking about. (I made you search lkml, > and that was a bit rude. But you found the patch anyhow.) > >> This controller doesn't look like to be based on pcie-designware core >> driver. >> Other vendors that are using "pcie-designware" core driver are also make >> it bool. >> The current core driver doesn't support module loading/unloading as I >> see it. >> If this is required, I also think this should be part of another patchset. >> >> What do you think ? > > I wouldn't know whether your driver might work as a loadable module, but > other people reading this surely will. But if it can't work as a module > you should drop all the module related macros etc. I spotted. Because > then they serve no purpose. > > > Paul Bolle > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller
Hi Kishon, I tested with my internal 3.10 ST Kernel but not on the 4.0. I think i'll implement it when i'm able to test it fully. Thanks On 17 March 2015 at 11:35, Kishon Vijay Abraham I wrote: > Hi, > > > On Monday 16 March 2015 07:50 PM, Gabriel FERNANDEZ wrote: >> >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> drivers/pci/host/Kconfig | 9 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pci-st.c | 617 >> ++ >> 3 files changed, 627 insertions(+) >> create mode 100644 drivers/pci/host/pci-st.c >> >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig >> index 7b892a9..af9f9212 100644 >> --- a/drivers/pci/host/Kconfig >> +++ b/drivers/pci/host/Kconfig >> @@ -106,4 +106,13 @@ config PCI_VERSATILE >> bool "ARM Versatile PB PCI controller" >> depends on ARCH_VERSATILE >> >> +config PCI_ST >> + bool "ST PCIe controller" >> + depends on ARCH_STI || (ARM && COMPILE_TEST) >> + select PCIE_DW >> + help >> + Enable PCIe controller support on ST Socs. This controller is >> based >> + on Designware hardware and therefore the driver re-uses the >> + Designware core functions to implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile >> index e61d91c..97c6622 100644 >> --- a/drivers/pci/host/Makefile >> +++ b/drivers/pci/host/Makefile >> @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o >> obj-$(CONFIG_PCI_XGENE) += pci-xgene.o >> obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >> obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o >> +obj-$(CONFIG_PCI_ST) += pci-st.o >> diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c >> new file mode 100644 >> index 000..47d >> --- /dev/null >> +++ b/drivers/pci/host/pci-st.c >> @@ -0,0 +1,617 @@ >> +/* >> + * Copyright (C) 2014 STMicroelectronics >> + * >> + * STMicroelectronics PCI express Driver for sti SoCs. >> + * ST PCIe IPs are built around a Synopsys IP Core. >> + * >> + * Author: Fabrice Gasnier >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2, as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define TRANSLATION_CONTROL0x900 >> +/* Controls if area is inclusive or exclusive */ >> +#define RC_PASS_ADDR_RANGE BIT(1) >> + >> +/* Base of area reserved for config accesses. Fixed size of 64K. */ >> +#define CFG_BASE_ADDRESS 0x92c >> +#define CFG_REGION_SIZE65536 >> +#define CFG_SPACE1_OFFSET 0x1000 >> + >> +/* First 4K of config space has this BDF (bus,device,function) */ >> +#define FUNC0_BDF_NUM 0x930 >> + >> +/* Mem regions */ >> +#define IN0_MEM_ADDR_START 0x964 >> +#define IN0_MEM_ADDR_LIMIT 0x968 >> +#define IN1_MEM_ADDR_START 0x974 >> +#define IN1_MEM_ADDR_LIMIT 0x978 >> + >> +/* This actually contains the LTSSM state machine state */ >> +#define PORT_LOGIC_DEBUG_REG_0 0x728 >> + >> +/* LTSSM state machine values */ >> +#define DEBUG_REG_0_LTSSM_MASK 0x1f >> +#define S_DETECT_QUIET 0x00 >> +#define S_DETECT_ACT 0x01 >> +#define S_POLL_ACTIVE 0x02 >> +#define S_POLL_COMPLIANCE 0x03 >> +#define S_POLL_CONFIG 0x04 >> +#define S_PRE_DETECT_QUIET 0x05 >> +#define S_DETECT_WAIT 0x06 >> +#define S_CFG_LINKWD_START 0x07 >> +#define S_CFG_LINKWD_ACEPT 0x08 >> +#define S_CFG_LANENUM_WAIT 0x09 >> +#define S_CFG_LANENUM_ACEPT0x0A >> +#define S_CFG_COMPLETE 0x0B >> +#define S_CFG_IDLE 0x0C >> +#define S_RCVRY_LOCK 0x0D >> +#defi
Re: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie
Hi Liviu,
You're right, i removed configuration space from the ranges.
Thanks for reviewing.
Gabriel
On 17 March 2015 at 12:42, Liviu Dudau wrote:
> Hi Gabriel,
>
> On Mon, Mar 16, 2015 at 02:20:32PM +, Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>> ---
>> Documentation/devicetree/bindings/pci/st-pcie.txt | 54
>> +++
>> 1 file changed, 54 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
>> b/Documentation/devicetree/bindings/pci/st-pcie.txt
>> new file mode 100644
>> index 000..94aae2d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
>> @@ -0,0 +1,54 @@
>> +STMicroelectronics STi PCIe controller
>> +
>> +This PCIe host controller is based on the Synopsis Designware PCIe IP
>> +and thus inherits all the common properties defined in designware-pcie.txt.
>> +
>> +Required properties:
>> + - compatible: "st,stih407-pcie"
>> + - reg: base address and length of the pcie controller, mem-window address
>> + and length available to the controller.
>> + - interrupts: A list of interrupt outputs of the controller. Must contain
>> an
>> + entry for each entry in the interrupt-names property.
>> + - interrupt-names: Should be "msi". STi interrupt that is asserted when an
>> + MSI is received.
>> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
>> + offset for IP configuration.
>> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP.
>> + Associated names must be "powerdown" and "softreset".
>> + - phys, phy-names: the phandle for the PHY device.
>> + Associated name must be "pcie"
>> +
>> +Optional properties:
>> + - reset-gpio: a GPIO spec to define which pin is connected to the bus
>> reset.
>> +
>> +Example:
>> +
>> +pcie0: pcie@9b0 {
>> + compatible = "st,stih407-pcie", "snps,dw-pcie";
>> + device_type = "pci";
>> + reg = <0x09b0 0x4000>, /* dbi cntrl registers */
>> + <0x2fff 0x0001>, /* configuration space */
>> + <0x4000 0x8000>; /* lmi mem window */
>> + reg-names = "dbi", "config", "mem-window";
>> + st,syscfg = <&syscfg_core 0xd8 0xe0>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x0800 0 0x2fff 0x2fff 0 0x0001 /*
>> configuration space */
>
> Unless you are trying to support some legacy code please remove the
> configuration space from the ranges.
> There is no resource type associated with config space and the generic parser
> will give you back an
> invalid resource type. The other reason for that is that if you really claim
> to be ECAM compliant by
> adding the config space here you need way more than 64K of space.
>
> Best regards,
> Liviu
>
>> + 0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
>> non-prefetchable memory */
>> + num-lanes = <1>;
>> + interrupts = ;
>> + interrupt-names = "msi";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT A */
>> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT B */
>> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /*
>> INT C */
>> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /*
>> INT D */
>> +
>> + resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
>> + <&softreset STIH407_PCIE0_SOFTRESET>;
>> + reset-names = "powerdown",
>> + "softreset";
>> + phys = <&phy_port0 PHY_TYPE_PCIE>;
>> + phy-names = "pcie";
>> +};
>> --
>> 1.9.1
>>
>>
>> ___
>> linux-arm-kernel mailing list
>> linux-arm-ker...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
> --
>
> | I would like to |
> | fix the world, |
> | but they're not |
> | giving me the |
> \ source code! /
> ---
> ¯\_(ツ)_/¯
>
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Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller
Thanks Paul for reviewing.
I'll check to be modular.
BR
Gabriel
On 16 March 2015 at 16:11, Paul Bolle wrote:
> On Mon, 2015-03-16 at 15:20 +0100, Gabriel FERNANDEZ wrote:
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>
>> +config PCI_ST
>> + bool "ST PCIe controller"
>
> You add a bool Kconfig symbol. A week or two ago I saw some patches fly
> by that - I think - allowed PCIe controllers to be built modular.
>
>> + depends on ARCH_STI || (ARM && COMPILE_TEST)
>> + select PCIE_DW
>> + help
>> + Enable PCIe controller support on ST Socs. This controller is based
>> + on Designware hardware and therefore the driver re-uses the
>> + Designware core functions to implement the driver.
>
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>
>> +obj-$(CONFIG_PCI_ST) += pci-st.o
>
> If you keep that symbol bool this objectfile will never be part of a
> module.
>
>> diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c
>> new file mode 100644
>> index 000..47d
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-st.c
>
>> +#include
>
> For built-in code this include is, probably, not needed.
>
>> +MODULE_DEVICE_TABLE(of, st_pcie_of_match);
>
> For built-in code that macro will always be preprocessed away.
>
>> +/* ST PCIe driver does not allow module unload */
>> +static int __init pcie_init(void)
>> +{
>> + return platform_driver_probe(&st_pcie_driver, st_pcie_probe);
>> +}
>> +device_initcall(pcie_init);
>
> I think the module unload comment is a bit odd for built-in only code.
>
>> +MODULE_AUTHOR("Fabrice Gasnier ");
>> +MODULE_DESCRIPTION("PCI express Driver for ST SoCs");
>> +MODULE_LICENSE("GPL v2");
>
> These three macros will be, basically, always preprocessed away as long
> as this code can't be built to be modular.
>
>
> Paul Bolle
>
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Re: [PATCH v2 4/5] PCI: designware: Add disable IO support
Hi Srinivas, Yes, you are right. Nevertheless i'll try the Kumar and Arnd 's request to not use DT to do that. BR Gabriel On 16 March 2015 at 18:53, Srinivas Kandagatla wrote: > > > On 16/03/15 14:20, Gabriel FERNANDEZ wrote: >> >> - bus-range: PCI bus numbers covered (it is recommended for new >> devicetrees to >> specify this property, to keep backwards compatibility a range of >> 0x00-0xff >> is assumed if not present) >> +- disable_io_support: set this property for PCIe host controller without >> IO >> + port access > > Shouldn't dt properties use hyphens rather than under scores ? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/5] PCI: designware: Add disable IO support
Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann wrote: > On Monday 16 March 2015 13:00:51 Kumar Gala wrote: >> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ >> wrote: >> >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. >> > >> > This patch adds the possibility to disable it through >> > a DT property, by creating an empty IO window and by >> > removing PCI_COMMAND_IO from the setup register. >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> > --- >> > .../devicetree/bindings/pci/designware-pcie.txt| 2 ++ >> > drivers/pci/host/pcie-designware.c | 24 >> > -- >> > drivers/pci/host/pcie-designware.h | 1 + >> > 3 files changed, 25 insertions(+), 2 deletions(-) >> >> Why not just update the code such that if the ranges doesn’t have an IO >> space rather than introducing a new DT property? > > I suspect we can simplify this now by changing over the designware PCI > code from pci_common_init_dev to calling pci_scan_root_bus() in the > same way that pci-versatile.c does. This would also clean up some > other areas of the driver and let you do proper error handling > in the probe. > > Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/5] MAINTAINERS: Add pci-st.c to ARCH/STI architecture
This patch adds the pci-st.c pci driver found on STMicroelectronics SoC's into the STI arch section of the maintainers file. Signed-off-by: Gabriel Fernandez --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a0dadde..83ed2c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1455,6 +1455,7 @@ F:drivers/clocksource/arm_global_timer.c F: drivers/i2c/busses/i2c-st.c F: drivers/media/rc/st_rc.c F: drivers/mmc/host/sdhci-st.c +F: drivers/pci/host/pci-st.c F: drivers/phy/phy-stih407-usb.c F: drivers/phy/phy-stih41x-usb.c F: drivers/pinctrl/pinctrl-st.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
b/Documentation/devicetree/bindings/pci/st-pcie.txt
new file mode 100644
index 000..94aae2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
@@ -0,0 +1,54 @@
+STMicroelectronics STi PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+ - compatible: "st,stih407-pcie"
+ - reg: base address and length of the pcie controller, mem-window address
+ and length available to the controller.
+ - interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+ - interrupt-names: Should be "msi". STi interrupt that is asserted when an
+ MSI is received.
+ - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
+ offset for IP configuration.
+ - resets, reset-names: the power-down and soft-reset lines of PCIe IP.
+ Associated names must be "powerdown" and "softreset".
+ - phys, phy-names: the phandle for the PHY device.
+ Associated name must be "pcie"
+
+Optional properties:
+ - reset-gpio: a GPIO spec to define which pin is connected to the bus reset.
+
+Example:
+
+pcie0: pcie@9b0 {
+ compatible = "st,stih407-pcie", "snps,dw-pcie";
+ device_type = "pci";
+ reg = <0x09b0 0x4000>, /* dbi cntrl registers */
+ <0x2fff 0x0001>, /* configuration space */
+ <0x4000 0x8000>; /* lmi mem window */
+ reg-names = "dbi", "config", "mem-window";
+ st,syscfg = <&syscfg_core 0xd8 0xe0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x0800 0 0x2fff 0x2fff 0 0x0001 /*
configuration space */
+ 0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = ;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT
A */
+ <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT
B */
+ <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT
C */
+ <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT
D */
+
+ resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
+<&softreset STIH407_PCIE0_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ phys = <&phy_port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie";
+};
--
1.9.1
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[PATCH v2 4/5] PCI: designware: Add disable IO support
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
This patch adds the possibility to disable it through
a DT property, by creating an empty IO window and by
removing PCI_COMMAND_IO from the setup register.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/pci/designware-pcie.txt| 2 ++
drivers/pci/host/pcie-designware.c | 24 --
drivers/pci/host/pcie-designware.h | 1 +
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 9f4faa8..40544d4 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -26,3 +26,5 @@ Optional properties:
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
specify this property, to keep backwards compatibility a range of 0x00-0xff
is assumed if not present)
+- disable_io_support: set this property for PCIe host controller without IO
+ port access
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 1f4ea6f..f9d70f5 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -471,6 +471,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
return -EINVAL;
}
+ pp->disable_io_support = of_property_read_bool(np,
+ "disable_io_support");
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
if (!pp->ops->msi_host_init) {
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
@@ -704,6 +707,7 @@ static struct pci_ops dw_pcie_ops = {
static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct pcie_port *pp;
+ struct resource *res;
pp = sys_to_pcie(sys);
@@ -719,6 +723,18 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
pci_add_resource(&sys->resources, &pp->busn);
+ if (pp->disable_io_support) {
+ /* This PCIe controller does not support IO, set an empty one */
+ res = devm_kzalloc(pp->dev, sizeof(*res), GFP_KERNEL);
+ if (res) {
+ res->start = 0;
+ res->end = 0;
+ res->name = "PCIe empty IO space";
+ res->flags = IORESOURCE_IO;
+ pci_add_resource(&sys->resources, res);
+ }
+ }
+
return 1;
}
@@ -822,8 +838,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* setup command register */
dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
val &= 0x;
- val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
+
+ if (!pp->disable_io_support)
+ val |= PCI_COMMAND_IO;
+
+ val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
+
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
}
diff --git a/drivers/pci/host/pcie-designware.h
b/drivers/pci/host/pcie-designware.h
index d0bbd27..027045d 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -52,6 +52,7 @@ struct pcie_port {
int msi_irq;
struct irq_domain *irq_domain;
unsigned long msi_data;
+ booldisable_io_support;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
--
1.9.1
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[PATCH v2 0/5] PCI: st: provide support for dw pcie
Changes in v2: - comestic corrections in device tree binding - add pci-st.c into MAINTAINERS - remove st_pcie_ops structure to avoid another level of indirection - remove nasty busy-loop - remove useless test using virt_to_phys() - move disable io support into dw-pcie driver I don't change the st_pcie_abort_handler() function because abort handling is masked during boot. This patch-set introduces a STMicroelectronics PCIe controller. It's based on designware PCIe driver. Gabriel Fernandez (5): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller PCI: designware: Add disable IO support MAINTAINERS: Add pci-st.c to ARCH/STI architecture .../devicetree/bindings/pci/designware-pcie.txt| 2 + Documentation/devicetree/bindings/pci/st-pcie.txt | 54 ++ MAINTAINERS| 1 + arch/arm/mach-sti/Kconfig | 2 + drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 617 + drivers/pci/host/pcie-designware.c | 24 +- drivers/pci/host/pcie-designware.h | 1 + 9 files changed, 709 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt create mode 100644 drivers/pci/host/pci-st.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] ARM: STi: Kconfig update for PCIe support
Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 3b1ac46..7f9b432 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -8,6 +8,8 @@ menuconfig ARCH_STI select ARCH_HAS_RESET_CONTROLLER select HAVE_ARM_SCU if SMP select ARCH_REQUIRE_GPIOLIB + select PCI_DOMAINS if PCI + select MIGHT_HAVE_PCI select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller
sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 617 ++ 3 files changed, 627 insertions(+) create mode 100644 drivers/pci/host/pci-st.c diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 7b892a9..af9f9212 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -106,4 +106,13 @@ config PCI_VERSATILE bool "ARM Versatile PB PCI controller" depends on ARCH_VERSATILE +config PCI_ST + bool "ST PCIe controller" + depends on ARCH_STI || (ARM && COMPILE_TEST) + select PCIE_DW + help + Enable PCIe controller support on ST Socs. This controller is based + on Designware hardware and therefore the driver re-uses the + Designware core functions to implement the driver. + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index e61d91c..97c6622 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o obj-$(CONFIG_PCI_XGENE) += pci-xgene.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o +obj-$(CONFIG_PCI_ST) += pci-st.o diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c new file mode 100644 index 000..47d --- /dev/null +++ b/drivers/pci/host/pci-st.c @@ -0,0 +1,617 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PCI express Driver for sti SoCs. + * ST PCIe IPs are built around a Synopsys IP Core. + * + * Author: Fabrice Gasnier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define TRANSLATION_CONTROL0x900 +/* Controls if area is inclusive or exclusive */ +#define RC_PASS_ADDR_RANGE BIT(1) + +/* Base of area reserved for config accesses. Fixed size of 64K. */ +#define CFG_BASE_ADDRESS 0x92c +#define CFG_REGION_SIZE65536 +#define CFG_SPACE1_OFFSET 0x1000 + +/* First 4K of config space has this BDF (bus,device,function) */ +#define FUNC0_BDF_NUM 0x930 + +/* Mem regions */ +#define IN0_MEM_ADDR_START 0x964 +#define IN0_MEM_ADDR_LIMIT 0x968 +#define IN1_MEM_ADDR_START 0x974 +#define IN1_MEM_ADDR_LIMIT 0x978 + +/* This actually contains the LTSSM state machine state */ +#define PORT_LOGIC_DEBUG_REG_0 0x728 + +/* LTSSM state machine values */ +#define DEBUG_REG_0_LTSSM_MASK 0x1f +#define S_DETECT_QUIET 0x00 +#define S_DETECT_ACT 0x01 +#define S_POLL_ACTIVE 0x02 +#define S_POLL_COMPLIANCE 0x03 +#define S_POLL_CONFIG 0x04 +#define S_PRE_DETECT_QUIET 0x05 +#define S_DETECT_WAIT 0x06 +#define S_CFG_LINKWD_START 0x07 +#define S_CFG_LINKWD_ACEPT 0x08 +#define S_CFG_LANENUM_WAIT 0x09 +#define S_CFG_LANENUM_ACEPT0x0A +#define S_CFG_COMPLETE 0x0B +#define S_CFG_IDLE 0x0C +#define S_RCVRY_LOCK 0x0D +#define S_RCVRY_SPEED 0x0E +#define S_RCVRY_RCVRCFG0x0F +#define S_RCVRY_IDLE 0x10 +#define S_L0 0x11 +#define S_L0S 0x12 +#define S_L123_SEND_EIDLE 0x13 +#define S_L1_IDLE 0x14 +#define S_L2_IDLE 0x15 +#define S_L2_WAKE 0x16 +#define S_DISABLED_ENTRY 0x17 +#define S_DISABLED_IDLE0x18 +#define S_DISABLED 0x19 +#define S_LPBK_ENTRY 0x1A +#define S_LPBK_ACTIVE 0x1B +#define S_LPBK_EXIT0x1C +#define S_LPBK_EXIT_TIMEOUT0x1D +#define S_HOT_RESET_ENTRY 0x1E +#define S_HOT_RESET0x1F + +/* syscfg bits */ +#define PCIE_SYS_INT BIT(5) +#define PCIE_APP_REQ_RETRY_EN BIT(3) +#define PCIE_APP_LTSSM_ENABLE BIT(2) +#define PCIE_APP_INIT_RST BIT(1) +#define PCIE_DEVICE_TYPE BIT(0) +#define PCIE_DEFAULT_VAL PCIE_DEVICE_TYPE + +/* Time to wait between testing the link in msecs (hardware poll interval) */ +#define LINK_LOOP_DELAY_MS 1 +/* Total amount of time to wait for the link to come up in msecs */ +#define LIN
Re: [PATCH 5/5] PCI: st: disable IO support
Hi,
Yes, we don't really care about this corner case.
Thanks for your reviewing.
BR
Gabriel
On 17 December 2014 at 15:01, One Thousand Gnomes
wrote:
> On Wed, 17 Dec 2014 11:34:46 +0100
> Gabriel FERNANDEZ wrote:
>
>> sti SoCs PCIe IPs are built around DesignWare IP Core.
>> But in these SoCs, PCIe IP doesn't support IO.
>> By default, when no IO space is provided, a default one is assigned.
>>
>> Add an empty IO resource to the bus, and disable IO by default.
>
> As a point of PCI pedantry I don't think this is quite sufficient. PCI
> has a weird corner case where I/O resources are implied rather than
> allocated.
>
> For IDE/SATA you may need to something like
>
> if (class == PCI_CLASS_STORAGE_IDE) {
> u8 progif;
> pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
> progif |= 5;
> pci_write_config_byte(dev, PCI_CLASS_PROG, &progif);
> }
>
> so that any adapter is kicked out of legacy mode and doesn't get implied
> I/O resources and interrupts. I don't know if that case matters for your
> usage.
>
>
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Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
On 19 January 2015 at 14:49, Arnd Bergmann wrote:
> On Monday 19 January 2015 13:37:33 Gabriel Fernandez wrote:
>> On 17 December 2014 at 23:14, Arnd Bergmann wrote:
>> > On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote:
>> > > +/*
>> > > + * On ARM platforms, we actually get a bus error returned when the PCIe
>> > IP
>> > > + * returns a UR or CRS instead of an OK.
>> > > + */
>> > > +static int st_pcie_abort_
>> >
>> > handler(unsigned long addr, unsigned int fsr,
>> > > + struct pt_regs *regs)
>> > > +{
>> > > + return 0;
>> > > +}
>> >
>> > You should check that it's actually PCI that caused the abort. Don't
>> > just ignore a hard error condition.
>> >
>> > Usually there are registers in the PCI core that let you identify what
>> > happened.
>> >
>>
>>
>> We return 0 because abort handler is not activated during boot.
>>
>
> Can you just remove the handler then? We should never have exception
> handlers that unconditionally return 0.
>
Ah sorry, we need the handler because we can received aborts from
user-land after the boot.
I have 2 solutions, the first to simplify we can only return 0.
The second is to manage handler during boot. Then i need for that a
new patch from Fabrice
https://lkml.org/lkml/2014/2/7/631
>> > > + * we must retry for up to a second before we decide the device is
>> > > + * dead. If we are still dead then we assume there is nothing
>> > there and
>> > > + * return ~0
>> > > + *
>> > > + * The downside of this is that we incur a delay of 1s for every
>> > pci
>> > > + * express link that doesn't have a device connected.
>> > > + */
>> > > + if (((where & ~3) == 0) && devfn == 0 && (data == 0 || data ==
>> > ~0)) {
>> > > + if (retry_count++ < 1000) {
>> > > + mdelay(1);
>> > > + goto retry;
>> > > + } else {
>> > > + *val = ~0;
>> > > + return PCIBIOS_DEVICE_NOT_FOUND;
>> > > + }
>> > > + }
>> > > +
>> > > + *val = data;
>> > > + return ret;
>> > > +}
>> >
>> > A busy-loop is extremely nasty. If this is only during the initial bus
>> > scan, could you use an msleep instead?
>> >
>> > yes it's during the initial bus scan.
>> But we can't use msleep because we are under raw_spin_lock_irqsave()
>> see PCI_OP_READ() macro in drivers/pci/access.c
>
> Ah, I see. Better use a loop with 'time_before()' and a much shorter
> delay then. Even a single mdelay(1) with irqs disabled can be annoying,
> so try to make the time as short as possible.
>
>> > Also, it sounds like the error you get is actually the fault that you
>> > are catching above. If this is correct, then use the fault handler to
>> > communicate this to the probe function.
>> >
>>
>> Same as above the handler is not activated during the boot and initial bus
>> scan.
>
> Maybe you could enable the handler during boot to catch this case, and
> then disable it later?
>
>> >
>> > > +static void st_msi_init_one(struct pcie_port *pp)
>> > > +{
>> > > + struct st_pcie *pcie = to_st_pcie(pp);
>> > > +
>> > > + /*
>> > > + * Set the magic address the hardware responds to. This has to be
>> > in
>> > > + * the range the PCI controller can write to.
>> > > + */
>> > > + dw_pcie_msi_init(pp);
>> > > +
>> > > + if ((virt_to_phys((void *)pp->msi_data) < pcie->lmi->start) ||
>> > > + (virt_to_phys((void *)pp->msi_data) > pcie->lmi->end))
>> > > + dev_err(pp->dev, "MSI addr miss-configured\n");
>> > > +}
>> >
>> > Why do you call virt_to_phys() here? Isn't
>> >
>> > msi_data a physical address?
>> >
>> ?
>>
>>
>> msi_data is a virtual address, it's obtained through a __get_free_pages()
>> function in dw_pcie_msi_init() procedure.
>
> I guess you need dma_map_single() then, or use dma_alloc_coherent instead
> of __get_free_pages(). There is no guarantee that the page you allocate
> there is actually visible to the PCI host at the same address that the CPU
> uses, so you need to map from a CPU address to a DMA address that the PCI
> host bridge uses.
>
> Arnd
This is only to check the msi magic address given to ip, we never read
or write in this area.
this code is only a check
BR
Gabriel
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Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
Hi Bjorn Helgaas,
On 12 January 2015 at 19:43, Bjorn Helgaas wrote:
> On Wed, Dec 17, 2014 at 11:34:44AM +0100, Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>> ---
>> drivers/pci/host/Kconfig | 5 +
>> drivers/pci/host/Makefile | 1 +
>> drivers/pci/host/pci-st.c | 713
>> ++
>
> Hi Gabriel,
>
> Can you add a MAINTAINERS update so I know who should ack changes to this
> driver?
yes no problem
>
>> 3 files changed, 719 insertions(+)
>> create mode 100644 drivers/pci/host/pci-st.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index c4b6568..999d2b9 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -102,4 +102,9 @@ config PCI_LAYERSCAPE
>> help
>> Say Y here if you want PCIe controller support on Layerscape SoCs.
>>
>> +config PCI_ST
>> + bool "ST STiH41x PCIe controller"
>> + depends on ARCH_STI
>> + select PCIE_DW
>
> Please add help text here.
>
okay
>> +static int st_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> + unsigned int devfn, int where, int size,
>> + u32 *val)
>> +{
>> + u32 data;
>> + u32 bdf;
>> + struct st_pcie *pcie = to_st_pcie(pp);
>> + int is_root_bus = pci_is_root_bus(bus);
>> + int retry_count = 0;
>> + int ret;
>> + void __iomem *addr;
>> +
>> + /*
>> + * Prerequisite
>> + * PCI express devices will respond to all config type 0 cycles, since
>> + * they are point to point links. Thus to avoid probing for multiple
>> + * devices on the root, dw-pcie already check for us if it is on the
>> + * root bus / other slots. Also, dw-pcie checks for the link being up
>> + * as we will hang if we issue a config request and the link is down.
>> + * A switch will reject requests for slots it knows do not exist.
>> + */
>> + bdf = bdf_num(bus->number, devfn, is_root_bus);
>> + addr = pcie->config_area + config_addr(where,
>> + bus->parent->number == pp->root_bus_nr);
>> +retry:
>> + /* Set the config packet devfn */
>> + writel_relaxed(bdf, pp->dbi_base + FUNC0_BDF_NUM);
>> + readl_relaxed(pp->dbi_base + FUNC0_BDF_NUM);
>> +
>> + ret = dw_pcie_cfg_read(addr, where, size, &data);
>> +
>> + /*
>> + * This is intended to help with when we are probing the bus. The
>> + * problem is that the wrapper logic doesn't have any way to
>> + * interrogate if the configuration request failed or not.
>> + * On the ARM we actually get a real bus error.
>> + *
>> + * Unfortunately this means it is impossible to tell the difference
>> + * between when a device doesn't exist (the switch will return a UR
>> + * completion) or the device does exist but isn't yet ready to accept
>> + * configuration requests (the device will return a CRS completion)
>
> We do have CRS support in the Linux PCI core, so I guess this comment means
> that the ST host bridge doesn't handle CRS correctly?
>
yes, it is.
>> + *
>> + * The result of this is that we will miss devices when probing.
>> + *
>> + * So if we are trying to read the dev/vendor id on devfn 0 and we
>> + * appear to get zero back, then we retry the request. We know that
>> + * zero can never be a valid device/vendor id. The specification says
>> + * we must retry for up to a second before we decide the device is
>> + * dead. If we are still dead then we assume there is nothing there and
>> + * return ~0
>> + *
>> + * The downside of this is that we incur a delay of 1s for every pci
>> + * express link that doesn't have a device connected.
>
> That sounds pretty bad and I assume is a consequence of CRS handling being
> broken in hardware.
>
>> + */
>> + if (((where & ~3) == 0) && devfn == 0 && (data == 0 || data == ~0)) {
>> + if (retry_count++ < 1000) {
>> + mdelay(1);
>> + goto retry;
>> + } else {
>> + *val = ~0;
>> + return PCIBIOS_DEVICE_NOT_FOUND;
>> + }
>> + }
>> +
>> + *val = data;
>> + return ret;
>> +}
>
>> +MODULE_LICENSE("GPLv2");
>
> See license_is_gpl_compatible(). This string needs to be "GPL v2", not
> "GPLv2" to avoid tainting the kernel.
>
okay
> Bjorn
Thanks for reviewing
BR
Gabriel
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Re: [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops
Hi Arnd, Jingoo, On 18 December 2014 at 05:58, Jingoo Han wrote: > On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote: >> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote: >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. > > Hi Gabriel, > > I cannot understand how ST sti SoCs PCIe IP does not support I/O. > As far as I know, it cannot be selected by the 'parameter'. > Then, H/W engineers dropped out the I/O control logic? > >> > >> > To support this, add setup_bus() to pcie_host_ops. > > >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> >> The dw-pcie driver should be able to tell whether the device has >> an I/O space or not, and do the right thing based on that. Don't >> add an implementation specific callback for that. > > I agree with Arnd's opinion. > > In addition, I have one more question. > Then, if a device that requires I/O region is connected to > PCIe slot of ST sti SoCs PCIe, what will happen? > It just prints error messages? > > Best regards, > Jingoo Han > >> >> Arnd > Arnd in other post mention to add an empty I/O space to workaround lack of I/O port access. Is it the right thing to do ? http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/299623.html Best regards -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
Hi Arnd,
On 17 December 2014 at 23:14, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>> ---
>> drivers/pci/host/Kconfig | 5 +
>> drivers/pci/host/Makefile | 1 +
>> drivers/pci/host/pci-st.c | 713
>> ++
>> 3 files changed, 719 insertions(+)
>> create mode 100644 drivers/pci/host/pci-st.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index c4b6568..999d2b9 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -102,4 +102,9 @@ config PCI_LAYERSCAPE
>> help
>> Say Y here if you want PCIe controller support on Layerscape SoCs.
>>
>> +config PCI_ST
>> + bool "ST STiH41x PCIe controller"
>> + depends on ARCH_STI
>> + select PCIE_DW
>
> I'd use 'depends on ARCH_STI || (ARM && COMPILE_TEST)' to enable
> building this on other platforms for test purposes.
>
ok
>> +
>> +#define to_st_pcie(x)container_of(x, struct st_pcie, pp)
>> +
>> +/**
>> + * struct st_pcie_ops - SOC dependent data
>> + * @init: reference to controller power & reset init routine
>> + * @enable_ltssm: reference to controller link enable routine
>> + * @disable_ltssm: reference to controller link disable routine
>> + * @phy_auto: flag when phy automatically configured
>> + */
>> +struct st_pcie_ops {
>> + int (*init)(struct pcie_port *pp);
>> + int (*enable_ltssm)(struct pcie_port *pp);
>> + int (*disable_ltssm)(struct pcie_port *pp);
>> + bool phy_auto;
>> +};
>
ok, i will fix it.
> It would be better not to invent another level of indirection. Try
> turning this around so you have a driver that binds to the specific
> SoC compatible string for the PCIe port while calling into a common
> library module for things that are shared.
>
>> +/*
>> + * On ARM platforms, we actually get a bus error returned when the PCIe IP
>> + * returns a UR or CRS instead of an OK.
>> + */
>> +static int st_pcie_abort_handler(unsigned long addr, unsigned int fsr,
>> + struct pt_regs *regs)
>> +{
>> + return 0;
>> +}
>
> You should check that it's actually PCI that caused the abort. Don't
> just ignore a hard error condition.
>
> Usually there are registers in the PCI core that let you identify what
> happened.
>
We return 0 because abort handler is not activated during boot.
>> +static int st_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> + unsigned int devfn, int where, int size,
>> + u32 *val)
>> +{
>> + u32 data;
>> + u32 bdf;
>> + struct st_pcie *pcie = to_st_pcie(pp);
>> + int is_root_bus = pci_is_root_bus(bus);
>> + int retry_count = 0;
>> + int ret;
>> + void __iomem *addr;
>> +
>> + /*
>> + * Prerequisite
>> + * PCI express devices will respond to all config type 0 cycles, since
>> + * they are point to point links. Thus to avoid probing for multiple
>> + * devices on the root, dw-pcie already check for us if it is on the
>> + * root bus / other slots. Also, dw-pcie checks for the link being up
>> + * as we will hang if we issue a config request and the link is down.
>> + * A switch will reject requests for slots it knows do not exist.
>> + */
>> + bdf = bdf_num(bus->number, devfn, is_root_bus);
>> + addr = pcie->config_area + config_addr(where,
>> + bus->parent->number == pp->root_bus_nr);
>> +retry:
>> + /* Set the config packet devfn */
>> + writel_relaxed(bdf, pp->dbi_base + FUNC0_BDF_NUM);
>> + readl_relaxed(pp->dbi_base + FUNC0_BDF_NUM);
>> +
>> + ret = dw_pcie_cfg_read(addr, where, size, &data);
>> +
>> + /*
>> + * This is intended to help with when we are probing the bus. The
>> + * problem is that the wrapper logic doesn't have any way to
>> + * interrogate if the configuration request failed or not.
>> + * On the ARM we actually get a real bus error.
>> + *
>> + * Unfortunately this means it is impossible to tell the difference
>> + * between when a device doesn't exist (the switch will return a UR
&
Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
Hi Jingoo, Thanks for reviewing On 18 December 2014 at 07:03, Jingoo Han wrote: > On Wednesday, December 17, 2014 7:35 PM, Gabriel FERNANDEZ wrote: >> >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> drivers/pci/host/Kconfig | 5 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pci-st.c | 713 >> ++ >> 3 files changed, 719 insertions(+) >> create mode 100644 drivers/pci/host/pci-st.c >> >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig >> index c4b6568..999d2b9 100644 >> --- a/drivers/pci/host/Kconfig >> +++ b/drivers/pci/host/Kconfig >> @@ -102,4 +102,9 @@ config PCI_LAYERSCAPE >> help >> Say Y here if you want PCIe controller support on Layerscape SoCs. >> >> +config PCI_ST >> + bool "ST STiH41x PCIe controller" >> + depends on ARCH_STI >> + select PCIE_DW >> + >> endmenu >> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile >> index 44c2699..ca14829 100644 >> --- a/drivers/pci/host/Makefile >> +++ b/drivers/pci/host/Makefile >> @@ -12,3 +12,4 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o >> pci-keystone.o >> obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o >> obj-$(CONFIG_PCI_XGENE) += pci-xgene.o >> obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o >> +obj-$(CONFIG_PCI_ST) += pci-st.o >> diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c >> new file mode 100644 >> index 000..bd3d32d >> --- /dev/null >> +++ b/drivers/pci/host/pci-st.c >> @@ -0,0 +1,713 @@ >> +/* >> + * Copyright (C) 2014 STMicroelectronics >> + * >> + * STMicroelectronics PCI express Driver for sti SoCs. >> + * ST PCIe IPs are built around a Synopsys IP Core. >> + * >> + * Author: Fabrice Gasnier >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2, as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > Please, re-order these headers alphabetically. > It enhances the readability. > sure >> + >> +#include "pcie-designware.h" >> + >> +#define TRANSLATION_CONTROL 0x900 >> +/* Controls if area is inclusive or exclusive */ >> +#define RC_PASS_ADDR_RANGE BIT(1) >> + >> +/* Base of area reserved for config accesses. Fixed size of 64K. */ >> +#define CFG_BASE_ADDRESS 0x92c >> +#define CFG_REGION_SIZE 65536 >> + >> +/* First 4K of config space has this BDF (bus,device,function) */ >> +#define FUNC0_BDF_NUM0x930 >> + >> +/* Mem regions */ >> +#define IN0_MEM_ADDR_START 0x964 >> +#define IN0_MEM_ADDR_LIMIT 0x968 >> +#define IN1_MEM_ADDR_START 0x974 >> +#define IN1_MEM_ADDR_LIMIT 0x978 >> + >> +/* This actually contains the LTSSM state machine state */ >> +#define PORT_LOGIC_DEBUG_REG_0 0x728 >> + >> +/* LTSSM state machine values*/ >> +#define DEBUG_REG_0_LTSSM_MASK 0x1f >> +#define S_DETECT_QUIET 0x00 >> +#define S_DETECT_ACT 0x01 >> +#define S_POLL_ACTIVE0x02 >> +#define S_POLL_COMPLIANCE0x03 >> +#define S_POLL_CONFIG0x04 >> +#define S_PRE_DETECT_QUIET 0x05 >> +#define S_DETECT_WAIT0x06 >> +#define S_CFG_LINKWD_START 0x07 >> +#define S_CFG_LINKWD_ACEPT 0x08 >> +#define S_CFG_LANENUM_WAIT 0x09 >> +#define S_CFG_LANENUM_ACEPT 0x0A >> +#define S_CFG_COMPLETE 0x0B >> +#define S_CFG_IDLE 0x0C >> +#define S_RCVRY_LOCK 0x0D >> +#define S_RCVRY_SPEED0x0E >> +#define S_RCVRY_RCVRCFG 0x0F >> +#define S_RCVRY_IDLE 0x10 >> +#define S_L0 0x11 >> +#define S_L0S0x12 >> +#define S_L123_SEND_EIDLE0x13 >> +#define S_L1_IDLE
Re: [PATCH 2/5] PCI: st: Add Device Tree bindings for sti pcie
Hi Arnd, Thanks for reviewing On 17 December 2014 at 23:01, Arnd Bergmann wrote: > On Wednesday 17 December 2014 11:34:43 Gabriel FERNANDEZ wrote: >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> Documentation/devicetree/bindings/pci/st-pcie.txt | 53 >> +++ >> 1 file changed, 53 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt >> >> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt >> b/Documentation/devicetree/bindings/pci/st-pcie.txt >> new file mode 100644 >> index 000..bd3488f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt >> @@ -0,0 +1,53 @@ >> +STMicroelectronics STi PCIe controller >> + >> +This PCIe host controller is based on the Synopsis Designware PCIe IP >> +and thus inherits all the common properties defined in designware-pcie.txt. >> + >> +Required properties: >> + - compatible: "st,stih407-pcie" >> + - reg: base address and length of the pcie controller, mem-window address >> + and length available to the controller. >> + - interrupts: A list of interrupt outputs of the controller. >> + - interrupt-names: Must include the following entries: >> + "msi": STi interrupt that is asserted when an MSI is received > > You should specify that only one interrupt may be present. > If you extend the binding, you will need to describe what the > second one is as well. > ok, i will change into: " - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. >> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg >> + offset for IP configuration. >> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. >> + Associated names must be "powerdown" and "softreset". >> + - phys, phy-names: the phandle for the PHY device. >> + Associated name must be "pcie_phy" > > Names should not have underscores in them in general. "pcie-phy" would > be fine, but just "pcie" seems good enough, unless there are existing > drivers that have established a specific naming. > just "pcie" is fine for me BR Gabriel > > Arnd > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] Enable DRM/KMS support for STiH407 and STiH410 boards
This patch-set Enable DRM/KMS support for STiH407-b2120 and STiH410-b2120 boards. This patch-set replace the previous one (PATCH 0/2] Enable DRM/KMS support for STiH407 Family boards) Gabriel Fernandez (2): ARM: DT: STiH407: Add DRM dt nodes ARM: DT: STiH410: Add DRM dt nodes arch/arm/boot/dts/stih407-b2120.dts | 3 +- arch/arm/boot/dts/stih407.dtsi | 151 +++ arch/arm/boot/dts/stih410.dtsi | 138 arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +- 4 files changed, 291 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/stih407.dtsi -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: DT: STiH407: Add DRM dt nodes
This patch adds the DRM/KMS dt nodes.
This node can't be in stih407-family.dtsi file because in the future we
will integrate a new stih418-b2199 board. It's a stih407 family board
with different drm/kms dt nodes.
That is why i created the stih407.dtsi file.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-b2120.dts | 3 +-
arch/arm/boot/dts/stih407.dtsi | 151 +++
arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
3 files changed, 153 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/stih407.dtsi
diff --git a/arch/arm/boot/dts/stih407-b2120.dts
b/arch/arm/boot/dts/stih407-b2120.dts
index 261d5e2..af48714 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,9 +7,8 @@
* published by the Free Software Foundation.
*/
/dts-v1/;
-#include "stih407-clock.dtsi"
-#include "stih407-family.dtsi"
#include "stihxxx-b2120.dtsi"
+#include "stih407.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
new file mode 100644
index 000..3efa3b2
--- /dev/null
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2015 STMicroelectronics Limited.
+ * Author: Gabriel Fernandez
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+/ {
+ soc {
+ /* Display */
+ vtg_main: sti-vtg-main@8d02800 {
+ compatible = "st,vtg";
+ reg = <0x8d02800 0x200>;
+ interrupts = ;
+ };
+
+ vtg_aux: sti-vtg-aux@8d00200 {
+ compatible = "st,vtg";
+ reg = <0x8d00200 0x100>;
+ interrupts = ;
+ };
+
+ sti-display-subsystem {
+ compatible = "st,sti-display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>;
+
+ assigned-clock-parents = <0>,
+<0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>;
+
+ assigned-clock-rates = <29700>, <29700>;
+
+ ranges;
+
+ sti-compositor@9d11000 {
+ compatible = "st,stih407-compositor";
+ reg = <0x9d11000 0x1000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "pix_gdp1",
+ "pix_gdp2",
+ "pix_gdp3",
+ "pix_gdp4",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_d2_flexge
[PATCH 2/2] ARM: DT: STiH410: Add DRM dt nodes
This patch adds the DRM/KMS dt nodes.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih410.dtsi | 138 +
1 file changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 37995f4..208b5e8 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -80,5 +80,143 @@
phys = <&usb2_picophy2>;
phy-names = "usb";
};
+
+ /* Display */
+ vtg_main: sti-vtg-main@8d02800 {
+ compatible = "st,vtg";
+ reg = <0x8d02800 0x200>;
+ interrupts = ;
+ };
+
+ vtg_aux: sti-vtg-aux@8d00200 {
+ compatible = "st,vtg";
+ reg = <0x8d00200 0x100>;
+ interrupts = ;
+ };
+
+ sti-display-subsystem {
+ compatible = "st,sti-display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>;
+
+ assigned-clock-parents = <0>,
+<0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>;
+
+ assigned-clock-rates = <29700>, <29700>;
+
+ ranges;
+
+ sti-compositor@9d11000 {
+ compatible = "st,stih407-compositor";
+ reg = <0x9d11000 0x1000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "pix_gdp1",
+ "pix_gdp2",
+ "pix_gdp3",
+ "pix_gdp4",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+<&clk_s_d2_flexgen CLK_PIX_GDP1>,
+<&clk_s_d2_flexgen CLK_PIX_GDP2>,
+<&clk_s_d2_flexgen CLK_PIX_GDP3>,
+<&clk_s_d2_flexgen CLK_PIX_GDP4>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 1>;
+
+ reset-names = "compo-main", "compo-aux";
+ resets = <&softreset STIH407_COMPO_SOFTRESET>,
+<&softreset STIH407_COMPO_SOFTRESET>;
+ st,vtg = <&vtg_main>, <&vtg_aux>;
+ };
+
+ sti-tvout@8d08000 {
+ compatible = "st,stih407-tvout";
+ reg = <0x8d08000 0x1000>;
+
[PATCH 1/3] phy: miphy28lp: Pass sysconfig register offsets via syscfg dt property.
Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy28lp phy driver to access sysconfig register offsets via
syscfg dt property.
This is because the reg property should not be mixing address spaces like
it does currently for miphy28lp. This change then also aligns us to how other
platforms such as keystone and bcm7445 pass there syscon offsets via DT.
I have updated the miphy28lp phy driver same way as Peter's implementation.
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 43 ++-
drivers/phy/phy-miphy28lp.c| 61 --
2 files changed, 48 insertions(+), 56 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index 46a135d..89caa88 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -26,6 +26,7 @@ Required properties (port (child) node):
filled in "reg". It can also contain the offset of the system
configuration
registers used as glue-logic to setup the device for
SATA/PCIe or USB3
devices.
+- st,syscfg: Offset of the parent configuration register.
- resets : phandle to the parent reset controller.
- reset-names : Associated name must be "miphy-sw-rst".
@@ -54,18 +55,12 @@ example:
phy_port0: port@9b22000 {
reg = <0x9b22000 0xff>,
<0x9b09000 0xff>,
- <0x9b04000 0xff>,
- <0x114 0x4>, /* sysctrl MiPHY cntrl */
- <0x818 0x4>, /* sysctrl MiPHY status*/
- <0xe0 0x4>, /* sysctrl PCIe */
- <0xec 0x4>; /* sysctrl SATA */
+ <0x9b04000 0xff>;
reg-names = "sata-up",
"pcie-up",
- "pipew",
- "miphy-ctrl-glue",
- "miphy-status-glue",
- "pcie-glue",
- "sata-glue";
+ "pipew";
+
+ st,syscfg = <0x114 0x818 0xe0 0xec>;
#phy-cells = <1>;
st,osc-rdy;
reset-names = "miphy-sw-rst";
@@ -75,18 +70,13 @@ example:
phy_port1: port@9b2a000 {
reg = <0x9b2a000 0xff>,
<0x9b19000 0xff>,
- <0x9b14000 0xff>,
- <0x118 0x4>,
- <0x81c 0x4>,
- <0xe4 0x4>,
- <0xf0 0x4>;
+ <0x9b14000 0xff>;
reg-names = "sata-up",
"pcie-up",
- "pipew",
- "miphy-ctrl-glue",
- "miphy-status-glue",
- "pcie-glue",
- "sata-glue";
+ "pipew";
+
+ st,syscfg = <0x118 0x81c 0xe4 0xf0>;
+
#phy-cells = <1>;
st,osc-force-ext;
reset-names = "miphy-sw-rst";
@@ -95,13 +85,12 @@ example:
phy_port2: port@8f95000 {
reg = <0x8f95000 0xff>,
- <0x8f9 0xff>,
- <0x11c 0x4>,
- <0x820 0x4>;
+ <0x8f9 0xff>;
reg-names = "pipew",
- "usb3-up",
- "miphy-ctrl-glue",
- "miphy-status-glue";
+ "usb3-up";
+
+ st,sysc
[PATCH 3/3] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY
Signed-off-by: Gabriel Fernandez --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 4b87fd1..88dfa7e 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -459,6 +459,7 @@ CONFIG_PWM_VT8500=y CONFIG_PHY_HIX5HD2_SATA=y CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_STIH41X_USB=y CONFIG_PHY_STIH407_USB=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-family.dtsi | 53 +++
arch/arm/boot/dts/stihxxx-b2120.dtsi | 11
2 files changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi
b/arch/arm/boot/dts/stih407-family.dtsi
index d4a8f84..c06a546 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -283,5 +283,58 @@
<&picophyreset STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x114 0x818 0xe0 0xec>;
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x118 0x81c 0xe4 0xf0>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f9 0xff>;
+ reg-names = "pipew",
+ "usb3-up";
+
+ st,syscfg = <0x11c 0x820>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi
b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 0074bd4..8af5282 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -55,5 +55,16 @@
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+
+ phy_port0: port@9b22000 {
+ st,osc-rdy;
+ };
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
};
};
--
1.9.1
--
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[PATCH 0/3] Enable myphy28lp support
The goal of this series is to enable the support of MiPHY28lp Generic PHY. The first patch is to update miphy28lp phy driver to access sysconfig register offsets via syscfg dt property. It's based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161 I have updated the miphy28lp phy driver same way as Peter's implementation. Gabriel Fernandez (3): phy: miphy28lp: Pass sysconfig register offsets via syscfg dt property. ARM: DT: STi: STiH407: Add DT node for MiPHY28lp ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY .../devicetree/bindings/phy/phy-miphy28lp.txt | 43 ++- arch/arm/boot/dts/stih407-family.dtsi | 53 +++ arch/arm/boot/dts/stihxxx-b2120.dtsi | 11 arch/arm/configs/multi_v7_defconfig| 1 + drivers/phy/phy-miphy28lp.c| 61 -- 5 files changed, 113 insertions(+), 56 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] PCI: st: Add Device Tree bindings for sti pcie
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt
b/Documentation/devicetree/bindings/pci/st-pcie.txt
new file mode 100644
index 000..bd3488f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/st-pcie.txt
@@ -0,0 +1,53 @@
+STMicroelectronics STi PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+ - compatible: "st,stih407-pcie"
+ - reg: base address and length of the pcie controller, mem-window address
+ and length available to the controller.
+ - interrupts: A list of interrupt outputs of the controller.
+ - interrupt-names: Must include the following entries:
+ "msi": STi interrupt that is asserted when an MSI is received
+ - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg
+ offset for IP configuration.
+ - resets, reset-names: the power-down and soft-reset lines of PCIe IP.
+ Associated names must be "powerdown" and "softreset".
+ - phys, phy-names: the phandle for the PHY device.
+ Associated name must be "pcie_phy"
+
+Optional properties:
+ - reset-gpio: a GPIO spec to define which pin is connected to the bus reset.
+
+Example:
+
+pcie0: pcie@9b0 {
+ compatible = "st,stih407-pcie", "snps,dw-pcie";
+ device_type = "pci";
+ reg = <0x09b0 0x4000>, /* dbi cntrl registers */
+ <0x2fff 0x0001>, /* configuration space */
+ <0x4000 0x8000>; /* lmi mem window */
+ reg-names = "dbi", "config", "mem-window";
+ st,syscfg = <&syscfg_core 0xd8 0xe0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x0800 0 0x2fff 0x2fff 0 0x0001 /*
configuration space */
+ 0x8200 0 0x2000 0x2000 0 0x0FFF>; /*
non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = ;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT
A */
+ <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT
B */
+ <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT
C */
+ <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT
D */
+
+ resets = <&powerdown STIH407_PCIE0_POWERDOWN>,
+<&softreset STIH407_PCIE0_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ phys = <&phy_port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie_phy";
+};
--
1.9.1
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[PATCH 1/5] ARM: STi: Kconfig update for PCIe support
Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 8825bc9..d1e563c 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -8,6 +8,8 @@ menuconfig ARCH_STI select ARCH_HAS_RESET_CONTROLLER select HAVE_ARM_SCU if SMP select ARCH_REQUIRE_GPIOLIB + select PCI_DOMAINS if PCI + select MIGHT_HAVE_PCI select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] PCI: st: disable IO support
sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs, PCIe IP doesn't support IO.
By default, when no IO space is provided, a default one is assigned.
Add an empty IO resource to the bus, and disable IO by default.
Signed-off-by: Fabrice Gasnier
---
drivers/pci/host/pci-st.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c
index bd3d32d..c0d3895 100644
--- a/drivers/pci/host/pci-st.c
+++ b/drivers/pci/host/pci-st.c
@@ -357,9 +357,15 @@ static void st_pcie_board_reset(struct pcie_port *pp)
static void st_pcie_hw_setup(struct pcie_port *pp)
{
struct st_pcie *pcie = to_st_pcie(pp);
+ u32 val;
dw_pcie_setup_rc(pp);
+ /* Disable IO support */
+ val = readl_relaxed(pp->dbi_base + PCI_COMMAND);
+ val &= ~PCI_COMMAND_IO;
+ writel_relaxed(val, pp->dbi_base + PCI_COMMAND);
+
/* Set up the config window to the top of the PCI address space */
writel_relaxed(pcie->config_window_start,
pp->dbi_base + CFG_BASE_ADDRESS);
@@ -445,11 +451,28 @@ static void st_pcie_host_init(struct pcie_port *pp)
st_msi_init_one(pp);
}
+static void st_pcie_setup_bus(struct pcie_port *pp, struct pci_sys_data *sys)
+{
+ struct resource *res;
+
+ /* This PCIe controller does not support IO, set an empty one. */
+ res = devm_kzalloc(pp->dev, sizeof(*res), GFP_KERNEL);
+ if (!res)
+ return;
+
+ res->start = 0;
+ res->end = 0;
+ res->name = "PCIe empty IO space";
+ res->flags = IORESOURCE_IO;
+ pci_add_resource(&sys->resources, res);
+}
+
static struct pcie_host_ops st_pcie_host_ops = {
.rd_other_conf = st_pcie_rd_other_conf,
.wr_other_conf = st_pcie_wr_other_conf,
.link_up = st_pcie_link_up,
.host_init = st_pcie_host_init,
+ .setup_bus = st_pcie_setup_bus,
};
static int st_pcie_init(struct pcie_port *pp)
--
1.9.1
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[PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 713 ++ 3 files changed, 719 insertions(+) create mode 100644 drivers/pci/host/pci-st.c diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index c4b6568..999d2b9 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -102,4 +102,9 @@ config PCI_LAYERSCAPE help Say Y here if you want PCIe controller support on Layerscape SoCs. +config PCI_ST + bool "ST STiH41x PCIe controller" + depends on ARCH_STI + select PCIE_DW + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 44c2699..ca14829 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o obj-$(CONFIG_PCI_XGENE) += pci-xgene.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o +obj-$(CONFIG_PCI_ST) += pci-st.o diff --git a/drivers/pci/host/pci-st.c b/drivers/pci/host/pci-st.c new file mode 100644 index 000..bd3d32d --- /dev/null +++ b/drivers/pci/host/pci-st.c @@ -0,0 +1,713 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PCI express Driver for sti SoCs. + * ST PCIe IPs are built around a Synopsys IP Core. + * + * Author: Fabrice Gasnier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define TRANSLATION_CONTROL0x900 +/* Controls if area is inclusive or exclusive */ +#define RC_PASS_ADDR_RANGE BIT(1) + +/* Base of area reserved for config accesses. Fixed size of 64K. */ +#define CFG_BASE_ADDRESS 0x92c +#define CFG_REGION_SIZE65536 + +/* First 4K of config space has this BDF (bus,device,function) */ +#define FUNC0_BDF_NUM 0x930 + +/* Mem regions */ +#define IN0_MEM_ADDR_START 0x964 +#define IN0_MEM_ADDR_LIMIT 0x968 +#define IN1_MEM_ADDR_START 0x974 +#define IN1_MEM_ADDR_LIMIT 0x978 + +/* This actually contains the LTSSM state machine state */ +#define PORT_LOGIC_DEBUG_REG_0 0x728 + +/* LTSSM state machine values */ +#define DEBUG_REG_0_LTSSM_MASK 0x1f +#define S_DETECT_QUIET 0x00 +#define S_DETECT_ACT 0x01 +#define S_POLL_ACTIVE 0x02 +#define S_POLL_COMPLIANCE 0x03 +#define S_POLL_CONFIG 0x04 +#define S_PRE_DETECT_QUIET 0x05 +#define S_DETECT_WAIT 0x06 +#define S_CFG_LINKWD_START 0x07 +#define S_CFG_LINKWD_ACEPT 0x08 +#define S_CFG_LANENUM_WAIT 0x09 +#define S_CFG_LANENUM_ACEPT0x0A +#define S_CFG_COMPLETE 0x0B +#define S_CFG_IDLE 0x0C +#define S_RCVRY_LOCK 0x0D +#define S_RCVRY_SPEED 0x0E +#define S_RCVRY_RCVRCFG0x0F +#define S_RCVRY_IDLE 0x10 +#define S_L0 0x11 +#define S_L0S 0x12 +#define S_L123_SEND_EIDLE 0x13 +#define S_L1_IDLE 0x14 +#define S_L2_IDLE 0x15 +#define S_L2_WAKE 0x16 +#define S_DISABLED_ENTRY 0x17 +#define S_DISABLED_IDLE0x18 +#define S_DISABLED 0x19 +#define S_LPBK_ENTRY 0x1A +#define S_LPBK_ACTIVE 0x1B +#define S_LPBK_EXIT0x1C +#define S_LPBK_EXIT_TIMEOUT0x1D +#define S_HOT_RESET_ENTRY 0x1E +#define S_HOT_RESET0x1F + +/* syscfg bits */ +#define PCIE_SYS_INT BIT(5) +#define PCIE_APP_REQ_RETRY_EN BIT(3) +#define PCIE_APP_LTSSM_ENABLE BIT(2) +#define PCIE_APP_INIT_RST BIT(1) +#define PCIE_DEVICE_TYPE BIT(0) +#define PCIE_DEFAULT_VAL PCIE_DEVICE_TYPE + +/* Time to wait between testing the link in msecs (hardware poll interval) */ +#define LINK_LOOP_DELAY_MS 1 +/* Total amount of time to wait for the link to come up in msecs */ +#define LINK_WAIT_MS 120 +#define LINK_LOOP_COUNT (LINK_WAIT_MS / LINK_LOOP_DELAY_MS) + +/* st,syscfg offsets */ +#define SYSCFG0_REG1 +#define SYSCFG1_REG2 + +#define to_st_pcie(x) container_of(x, struct st_pcie, pp) + +/** + * struct st_pcie_ops - SOC dependent data + * @init: ref
[PATCH 0/5] PCI: st: provide support for dw pcie
This patch-set introduces a STMicroelectronics PCIe controler. It's based on designware PCIe driver. Gabriel Fernandez (5): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller PCI: designware: Add setup bus-related to pcie_host_ops PCI: st: disable IO support Documentation/devicetree/bindings/pci/st-pcie.txt | 53 ++ arch/arm/mach-sti/Kconfig | 2 + drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 736 ++ drivers/pci/host/pcie-designware.c| 3 + drivers/pci/host/pcie-designware.h| 1 + 7 files changed, 801 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt create mode 100644 drivers/pci/host/pci-st.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
To support this, add setup_bus() to pcie_host_ops.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
drivers/pci/host/pcie-designware.c | 3 +++
drivers/pci/host/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index df781cd..98e19bc 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -719,6 +719,9 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
pci_add_resource(&sys->resources, &pp->busn);
+ if (pp->ops->setup_bus)
+ pp->ops->setup_bus(pp, sys);
+
return 1;
}
diff --git a/drivers/pci/host/pcie-designware.h
b/drivers/pci/host/pcie-designware.h
index d0bbd27..5c13de7 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -73,6 +73,7 @@ struct pcie_host_ops {
u32 (*get_msi_addr)(struct pcie_port *pp);
u32 (*get_msi_data)(struct pcie_port *pp, int pos);
void (*scan_bus)(struct pcie_port *pp);
+ void (*setup_bus)(struct pcie_port *pp, struct pci_sys_data *sys);
int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
};
--
1.9.1
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[PATCH 2/2] ARM: DT: STiH407: Specify default clocks for HDMI devices
Specify default clocks for HDMI devices to ensure a maximum of
compatible frequencies.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-family.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi
b/arch/arm/boot/dts/stih407-family.dtsi
index 5fd3c96..a7eb76c 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -292,6 +292,27 @@
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
+
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>;
+
+ assigned-clock-parents = <0>,
+<0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>;
+
+ assigned-clock-rates = <29700>, <29700>;
+
ranges;
sti-compositor@9d11000 {
@@ -334,6 +355,20 @@
resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
#address-cells = <1>;
#size-cells = <1>;
+
+ assigned-clocks = <&clk_s_d2_flexgen
CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen
CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen
CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_flexgen
CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>;
+
+ assigned-clock-parents = <&clk_s_d2_quadfs 0>,
+<&clk_tmdsout_hdmi>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d0_quadfs 0>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 0>;
ranges;
sti-hdmi@8d04000 {
--
1.9.1
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[PATCH 1/2] ARM: DT: STiH407: Add DRM dt nodes
This patch adds the DRM/KMS dt notes.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-family.dtsi | 104 ++
arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
2 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi
b/arch/arm/boot/dts/stih407-family.dtsi
index 3e31d32..5fd3c96 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -274,5 +274,109 @@
status = "disabled";
};
+
+ /* Display */
+ vtg_main: sti-vtg-main@8d02800 {
+ compatible = "st,vtg";
+ reg = <0x8d02800 0x200>;
+ interrupts = ;
+ };
+
+ vtg_aux: sti-vtg-aux@8d00200 {
+ compatible = "st,vtg";
+ reg = <0x8d00200 0x100>;
+ interrupts = ;
+ };
+
+ sti-display-subsystem {
+ compatible = "st,sti-display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sti-compositor@9d11000 {
+ compatible = "st,stih407-compositor";
+ reg = <0x9d11000 0x1000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "pix_gdp1",
+ "pix_gdp2",
+ "pix_gdp3",
+ "pix_gdp4",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_c0_flexgen CLK_COMPO_DVP>,
+<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+<&clk_s_d2_flexgen CLK_PIX_GDP1>,
+<&clk_s_d2_flexgen CLK_PIX_GDP2>,
+<&clk_s_d2_flexgen CLK_PIX_GDP3>,
+<&clk_s_d2_flexgen CLK_PIX_GDP4>,
+<&clk_s_d2_quadfs 0>,
+<&clk_s_d2_quadfs 1>;
+
+ reset-names = "compo-main", "compo-aux";
+ resets = <&softreset STIH407_COMPO_SOFTRESET>,
+<&softreset STIH407_COMPO_SOFTRESET>;
+ st,vtg = <&vtg_main>, <&vtg_aux>;
+ };
+
+ sti-tvout@8d08000 {
+ compatible = "st,stih407-tvout";
+ reg = <0x8d08000 0x1000>;
+ reg-names = "tvout-reg";
+ reset-names = "tvout";
+ resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sti-hdmi@8d04000 {
+ compatible = "st,stih407-hdmi";
+ reg = <0x8d04000 0x1000>;
+ reg-names = "hdmi-reg";
+ interrupts = ;
+ interrupt-names = "irq";
+ clock-names = "pix",
+ "tmds",
+ "phy",
+ "audio",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_d2_flexgen
CLK_PIX_HDMI>,
+
[PATCH 0/2] Enable DRM/KMS support for STiH407 Family boards
This patch-set Enable DRM/KMS support for STiH407 Family boards. Gabriel Fernandez (2): ARM: DT: STiH407: Add DRM dt nodes ARM: DT: STiH407: Specify default clocks for HDMI devices arch/arm/boot/dts/stih407-family.dtsi | 139 ++ arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +- 2 files changed, 140 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 8/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY
Signed-off-by: Gabriel Fernandez --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f1dc7fc..d5c2ff1 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -425,6 +425,7 @@ CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_SUN4I_USB=y CONFIG_EXT4_FS=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 7/8] phy: miphy28lp: Tune tx impedance across Soc cuts
This patch to compensate tx impedance (Sata, PCIe)
depending on Soc cuts the kernel is built for.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/phy/phy-miphy28lp.txt | 1 +
drivers/phy/phy-miphy28lp.c | 16
2 files changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index 4a3b4af..46a135d 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -40,6 +40,7 @@ Optional properties (port (child) node):
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative
line and positive
line).
- st,scc-on: enable ssc to reduce effects of EMI (only for sata or
PCIe).
+- st,tx-impedance-comp : to compensate tx impedance avoiding out of range
values.
example:
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index d8ff895..87dcc9a 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -204,6 +204,7 @@ struct miphy28lp_phy {
bool osc_rdy;
bool px_rx_pol_inv;
bool ssc;
+ bool tx_impedance;
struct reset_control *miphy_rst;
@@ -632,6 +633,12 @@ static void miphy_pcie_tune_ssc(struct miphy28lp_phy
*miphy_phy)
}
}
+static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
+{
+ /* Compensate Tx impedance to avoid out of range values */
+ writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
+}
+
static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
{
void __iomem *base = miphy_phy->base;
@@ -670,6 +677,9 @@ static inline int miphy28lp_configure_sata(struct
miphy28lp_phy *miphy_phy)
if (miphy_phy->ssc)
miphy_sata_tune_ssc(miphy_phy);
+ if (miphy_phy->tx_impedance)
+ miphy_tune_tx_impedance(miphy_phy);
+
return 0;
}
@@ -703,6 +713,9 @@ static inline int miphy28lp_configure_pcie(struct
miphy28lp_phy *miphy_phy)
if (miphy_phy->ssc)
miphy_pcie_tune_ssc(miphy_phy);
+ if (miphy_phy->tx_impedance)
+ miphy_tune_tx_impedance(miphy_phy);
+
return 0;
}
@@ -1154,6 +1167,9 @@ static int miphy28lp_of_probe(struct device_node *np,
miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
+ miphy_phy->tx_impedance =
+ of_property_read_bool(np, "st,tx-impedance-comp");
+
of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
if (!miphy_phy->sata_gen)
miphy_phy->sata_gen = SATA_GEN1;
--
1.9.1
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[PATCH v5 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-b2120.dts | 11 +++
arch/arm/boot/dts/stih407.dtsi | 65 +
2 files changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-b2120.dts
b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92..d0837fb 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -74,5 +74,16 @@
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+
+ phy_port0: port@9b22000 {
+ st,osc-rdy;
+ };
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 4f9024f..b8cc9a3 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -259,5 +259,70 @@
status = "disabled";
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>,
+ <0x114 0x4>, /* sysctrl MiPHY cntrl */
+ <0x818 0x4>, /* sysctrl MiPHY status*/
+ <0xe0 0x4>, /* sysctrl PCIe */
+ <0xec 0x4>; /* sysctrl SATA */
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>,
+ <0x118 0x4>,
+ <0x81c 0x4>,
+ <0xe4 0x4>,
+ <0xf0 0x4>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f9 0xff>,
+ <0x11c 0x4>,
+ <0x820 0x4>;
+ reg-names = "pipew",
+ "usb3-up",
+ "miphy-ctrl-glue",
+ "miphy-status-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
};
};
--
1.9.1
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[PATCH v5 6/8] phy: miphy28lp: Add SSC support for PCIE
SSC is the technique of modulating the operating frequency of a signal
slightly to spread its radiated emissions over a range of frequencies.
This reduction in the maximum emission for a given frequency helps meet
radiated emission requirements.
These settings are applicable for PCIE with Internal clock.
Signed-off-by: Harsh Gupta
Signed-off-by: Gabriel Fernandez
---
drivers/phy/phy-miphy28lp.c | 44
1 file changed, 44 insertions(+)
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index d2f797c..d8ff895 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -192,6 +192,7 @@
#define SATA_SPDMODE 1
#define MIPHY_SATA_BANK_NB 3
+#define MIPHY_PCIE_BANK_NB 2
struct miphy28lp_phy {
struct phy *phy;
@@ -591,6 +592,46 @@ static void miphy_sata_tune_ssc(struct miphy28lp_phy
*miphy_phy)
}
}
+static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+ u8 val;
+
+ /* Compensate Tx impedance to avoid out of range values */
+ /*
+* Enable the SSC on PLL for all banks
+* SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+*/
+ val = readb_relaxed(base + MIPHY_BOUNDARY_2);
+ val |= SSC_EN_SW;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
+
+ val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
+ val |= SSC_SEL;
+ writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
+
+ for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
+ writeb_relaxed(val, base + MIPHY_CONF);
+
+ /* Validate Step component */
+ writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
+ writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
+
+ /* Validate Period component */
+ writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
+ writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
+
+ /* Clear any previous request */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+
+ /* requests the PLL to take in account new parameters */
+ writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
+
+ /* To be sure there is no other pending requests */
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+ }
+}
+
static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
{
void __iomem *base = miphy_phy->base;
@@ -659,6 +700,9 @@ static inline int miphy28lp_configure_pcie(struct
miphy28lp_phy *miphy_phy)
if (err)
return err;
+ if (miphy_phy->ssc)
+ miphy_pcie_tune_ssc(miphy_phy);
+
return 0;
}
--
1.9.1
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[PATCH v5 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: alexandre torgue
Signed-off-by: Giuseppe Cavallaro
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +
1 file changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 000..b7c13ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,126 @@
+STMicroelectronics STi MIPHY28LP PHY binding
+
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA, PCIe or USB3.
+
+Required properties (controller (parent) node):
+- compatible : Should be "st,miphy28lp-phy".
+- st,syscfg: Should be a phandle of the system configuration register group
+ which contain the SATA, PCIe or USB3 mode setting bits.
+
+Required nodes : A sub-node is required for each channel the controller
+ provides. Address range information including the usual
+ 'reg' and 'reg-names' properties are used inside these
+ nodes to describe the controller's topology. These nodes
+ are translated by the driver's .xlate() function.
+
+Required properties (port (child) node):
+- #phy-cells : Should be 1 (See second example)
+ Cell after port phandle is device type from:
+ - PHY_TYPE_SATA
+ - PHY_TYPE_PCI
+ - PHY_TYPE_USB3
+- reg : Address and length of the register set for the device.
+- reg-names: The names of the register addresses corresponding to the
registers
+ filled in "reg". It can also contain the offset of the system
configuration
+ registers used as glue-logic to setup the device for
SATA/PCIe or USB3
+ devices.
+- resets : phandle to the parent reset controller.
+- reset-names : Associated name must be "miphy-sw-rst".
+
+Optional properties (port (child) node):
+- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic.
This
+ is not available in all the MiPHY. For example, for
STiH407, only the
+ MiPHY0 has this bit.
+- st,osc-force-ext : to select the external oscillator. This can change
from
+ different MiPHY inside the same SoC.
+- st,sata_gen : to select which SATA_SPDMODE has to be set in the
SATA system config
+ register.
+- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative
line and positive
+ line).
+
+example:
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>,
+ <0x114 0x4>, /* sysctrl MiPHY cntrl */
+ <0x818 0x4>, /* sysctrl MiPHY status*/
+ <0xe0 0x4>, /* sysctrl PCIe */
+ <0xec 0x4>; /* sysctrl SATA */
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+ st,osc-rdy;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>,
+ <0x118 0x4>,
+ <0x81c 0x4>,
+
