Re: [PATCH] arm64: dts: add all hi6220 uart nodes

[Haojian Zhuang]

On Thu, Oct 1, 2015 at 3:03 AM, Rob Herring  wrote:
> On Wed, Sep 30, 2015 at 1:12 PM, Tyler Baker  wrote:
>> On 30 September 2015 at 10:31, Mark Brown  wrote:
>>> On Wed, Sep 30, 2015 at 10:24:56AM +0200, Arnd Bergmann wrote:
 On Tuesday 29 September 2015 13:29:12 Tyler Baker wrote:
>>>
 > aliases {
 > serial0 = 
 > +   serial1 = 
 > +   serial2 = 
 > +   serial3 = 
 > +   serial4 = 
 > };
>>>
 In the changelog you mention "both uarts", but here you have five of them.
 Are they all accessible on the connector? If not, only provide aliases
 for the ones that are, using numbering that makes most sense for given
 how one would use the board.
>>
>> Thanks for the comment Arnd. Mark's comment below is correct, there
>> are only two UARTs accessible on the LS connection in addition to the
>> one on the board (solder pad).
>>
>> Is the following definition any clearer?
>>
>> serial0 =  // Onboard UART0
>> serial1 =  // LS expansion UART0
>> serial2 =  // LS expansion UART1
>
> Yes, but use C style comments.
>
> What about the BT UART?
>

Yes, all four uarts are used in hikey board. uar0 is onboard serial
uart. uart1 is
BT uart. uart2 & uart3 are connected to low speed expansion board. So Tyler
shouldn't decrease any uart from his current patch.
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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Tue, 2015-08-25 at 16:37 +0100, Leif Lindholm wrote:
 On Tue, Aug 25, 2015 at 04:51:22PM +0200, Ard Biesheuvel wrote:
  Arm kernel should either fetch memory information from
  efi or DT.
  
   Absolutely.
  
  Currently arm kernel fetch both efi memory information and
  reserved buffer from DTB at the same time.
  
   No, it does not.
  
  It should not, but it does. Due to an oversight, the stub removes
  /memreserve/ entries but ignores the reserved-memory node completely.
 
 Urgh.
 
  This was reported here in fact
  
  http://thread.gmane.org/gmane.linux.kernel.efi/5736/focus=5742
  
  but there has not been a followup to this series.
 
 Are all of those patches still relevant, or did some of them go in
 already?
 
 Haojian: can you give that patch a spin and see if it does what you
 need, combined with adding the reserved areas to the UEFI memory map?
 
 /
 Leif

It's so nice. This patch is what I need.

Thanks
Haojian

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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
 On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
   If your EFI memory map describes the memory as mappable, it is wrong.
  
  When kernel is working, kernel will create its own page table based on
  UEFI memory map. Since it's reserved in DTS file as Leo's patch, it'll
  be moved to reserved memblock. Why is it wrong?
  
  In the second, UEFI is firmware. When it's stable, nobody should change
  it without any reason.
 
 Much like the memory map.
 
  These reserved memory are used in mailbox driver.
  Look. It's driver, so it could be changed at any time.
 
 No, it is a set of regions of memory set aside for use by a different
 master in the system as well as communications with that master.
 
 The fact that there is a driver somewhere that is aware of this is
 entirely beside the point. All agents in the system must adher to this
 protocol.
 
  Why do you want
  to UEFI knowing this memory range? Do you hope UEFI to change when
  mailbox driver is changed?
 
 Yes.
 
 UEFI is a runtime environment. Having random magic areas not to be
 touched will cause random pieces of software running under it to break
 horribly or break other things horribly.
 Unless you mark them as reserved in the UEFI memory map.
 At which point the Linux kernel will automatically ignore them, and
 the proposed patch is redundant.
 
 So, yes, if you want a system that can boot reliably, run testsuites
 (like SCT or FWTS), run applications (like fastboot ... or the EFI
 stub kernel itself), then any memory regions that is reserved for
 mailbox communication (or other masters in the system) _must_ be
 marked in the EFI memory map.

1. We need support both UEFI and uboot. So the reserved buffer have to
be declared in DTB since they are used by kernel driver, not UEFI.

2. UEFI just loads grub. It's no time to run any other custom EFI
application.

Regards
Haojian

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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Mon, 2015-08-24 at 13:48 +0100, Mark Rutland wrote:
 I don't see why you need reserved-memory here, given you're not 
 referring to
 these regions by phandle anyway.

- Now we have enabled EFI_STUB, so the memory node will be removed in
  kernel:
efi_entry()
  \- allocate_new_fdt_and_exit_boot()
\- update_fdt();

  Finally in kernel it cannot use memory node to carve out reseved
  memory regions.

- On the other hand, DTS's the memory node is to describes the
  physical memory layout for the system; so it's better to use it only
  to describe the hardware info for memory. We can use reserved-memory
  to help manage the memory regions which are reserved from software
  perspective.
   
   The fact that you have no-map means that the memory should not be
   described to the kernel as mappable in the first place. It's wrong to
   place such memory in the memory node, even if listed in reserved-memory.
   
   If your EFI memory map describes the memory as mappable, it is wrong.
  
  When kernel is working, kernel will create its own page table based on
  UEFI memory map. Since it's reserved in DTS file as Leo's patch, it'll
  be moved to reserved memblock. Why is it wrong?
 
 That is a _Linux_ detail, not a _UEFI_ detail.
 
 Anything which only handles UEFI and knows nothing of reserved-memory
 (e.g. GRUB) will be broken and/or break the Linux use of the region, as
 it will happily try to allocate memory in the region (and could even
 decide to reserve it permanently for its own usage).
 
 If the memory is truly specific to the mailbox, then UEFI needs to know
 that it is reserved as such. If it is not, then it need not be described
 in the DT and can be allocated dynamically by the kernel.

No. We support both UEFI and uboot on hikey. We must reserve these
mailbox buffer in DT. Otherwise, it's a problem to support uboot.
We should only deliver one kernel and one DTB to support both UEFI and
uboot.

And mailbox driver is already upgraded from beginning. Nobody can say
that it won't be upgraded again in the future.

By the way, UEFI is loaded in the upper memory region of hikey. It won't
break anything in linux kernel.
 
  In the second, UEFI is firmware. When it's stable, nobody should change
  it without any reason. These reserved memory are used in mailbox driver.
  Look. It's driver, so it could be changed at any time. Why do you want
  to UEFI knowing this memory range? Do you hope UEFI to change when
  mailbox driver is changed?
 
 It shouldn't need to change if that memory is truly reserved for the
 sole use of the mailbox. If that's not the case then we have a different
 issue.
 
 If the memory range to use can be allocated by the driver, then I don't
 see why it should be described in reserved-memory. It certainly should
 not require a no-map attribute.
 
 Additionally, the driver needs to ensure that the requisite cache
 maintenance takes place prior to the use of the memory region given
 prior agents may have ampped it as cacheable, leaving stale (perhaps
 dirty) lines in the caches.
 

Since those mailbox buffer is declared as reserved with no-map
property, it means that linux kernel won't create the page table of
them.

The meaning of no-map is removing it from memory memblock.
setup_arch()
  |
  --- efi_init() -- Get memory map information from UEFI
  |
  --- arm64_memblock_init()
  |  |
  |  --- early_init_fdt_scan_reserved_mem()
  |   Get reserved memory buffer from DT. Split memory
  |   memblock according to reserved buffer.
  --- paging_init()
 |-- map_mem()
  _Only_ map the discrete memory memblock into kernel
  page table.

From this working flow, we could know that those mailbox buffers
won't be mapped into kernel page table. So there's no concern on
cache maintenance.
  
According to upper info, we still need to use reserved-memory node to
depict the reserved memory regions. i have no knowledge about EFI_STUB,
so please confirm or correct as needed.
   
   If the memory shouldn't be mapped, it should neither be in the memory
   node nor EFI memory map (with attributes allowing it to be mapped) to
   begin with.
  
  As I said above, kernel will create its own page table. When kernel's
  page table is working, UEFI's page table is destroying. So the memory
  won't be mapped twice at the same time. What's wrong?
   
   As far as I can see you do not need to use reserved-memory.
  
  1. Are we talking on the same thing? Leo already mentioned that all
  memory node in DTB will be destroyed by kernel when EFI_STUB is enabled
  on arm. Did you read the source code after his reply?
  And you suggested that Leo to use discrete memory region in DTB. It is
  really wrong. Kernel only gets memory map information from UEFI, not
  DTB.
 
 I did _not_ suggest that Leo use discrete memory. I suggested that
 reserved regions should 

Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Tue, 2015-08-25 at 10:46 +0100, Leif Lindholm wrote:
 On Tue, Aug 25, 2015 at 04:13:47PM +0800, Haojian Zhuang wrote:
  On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
   On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
 If your EFI memory map describes the memory as mappable, it is wrong.

When kernel is working, kernel will create its own page table based on
UEFI memory map. Since it's reserved in DTS file as Leo's patch, it'll
be moved to reserved memblock. Why is it wrong?

In the second, UEFI is firmware. When it's stable, nobody should change
it without any reason.
   
   Much like the memory map.
   
These reserved memory are used in mailbox driver.
Look. It's driver, so it could be changed at any time.
   
   No, it is a set of regions of memory set aside for use by a different
   master in the system as well as communications with that master.
   
   The fact that there is a driver somewhere that is aware of this is
   entirely beside the point. All agents in the system must adher to this
   protocol.
   
Why do you want
to UEFI knowing this memory range? Do you hope UEFI to change when
mailbox driver is changed?
   
   Yes.
   
   UEFI is a runtime environment. Having random magic areas not to be
   touched will cause random pieces of software running under it to break
   horribly or break other things horribly.
   Unless you mark them as reserved in the UEFI memory map.
   At which point the Linux kernel will automatically ignore them, and
   the proposed patch is redundant.
   
   So, yes, if you want a system that can boot reliably, run testsuites
   (like SCT or FWTS), run applications (like fastboot ... or the EFI
   stub kernel itself), then any memory regions that is reserved for
   mailbox communication (or other masters in the system) _must_ be
   marked in the EFI memory map.
  
  1. We need support both UEFI and uboot. So the reserved buffer have to
  be declared in DTB since they are used by kernel driver, not UEFI.
 
 The buffer may need to be declared in DTB also, but it most certanily
 needs to be declared in UEFI.
 
 And for the U-Boot case, since it is not memory available to Linux, it
 should not be declared as memory.

Something are messed at here. We have these buffer are used in mailbox.
They should be allocated as non-cacheable.

If these buffers are contained in memory memblock in kernel, it means
that they exist in kernel page table with cachable property. When it's
used in mailbox driver with non-cachable property, it'll only cause
cache maintenance issue. So Leo declared these buffers as reserved
in DT with no-map property. It's the key. It could avoid the cache
maintenance issue.

 
  2. UEFI just loads grub. It's no time to run any other custom EFI
  application.
 
 Apart from being completely irrelevant, how are you intending to
 validate that GRUB never touches these memory regions?
 

GRUB is just a part of bootloader. When linux kernel is running,
who cares GRUB? GRUB's lifetime is already finished.

By the way, UEFI code region is at [0x3Dxx_, 0x3DFF_]. Those
mailbox buffer is in [0x05e0_, 0x06f0_]. Then I can make sure
UEFI won't touch the reserved buffer. Even if UEFI touched the reserved
buffer, is it an issue? Definitely it's not. UEFI's lifetime is end
when linux kernel is running at hikey. Even if UEFI runtime service
is enabled, the runtime data area is at [0x38xx_, 0x38xx_].

 Build a version once, test it, and hope the results remain valid
 forever? And then when you move the regions and the previously working
 GRUB now tramples all over them? Or when something changes in upstream
 GRUB and its memory allocations drifts into the secretly untouchable
 regions?

As I said above, UEFI won't touch it. And even UEFI touch it, kernel
doesn't care since UEFI's lifetime is end.

 
 Are you then going to hack GRUB, release a special HiKey version of
 GRUB, not support any other versions, and still can your firmware
 UEFI?

I don't need to hack GRUB at all.

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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
   Are you then going to hack GRUB, release a special HiKey version of
   GRUB, not support any other versions, and still can your firmware
   UEFI?
  
  I don't need to hack GRUB at all.
 
 Then it is working for you by pure chance alone.
 
 Please listen to the advice you are being given here; we're trying to
 ensure that your platform functions (and continues to function) as best
 it can.

Since we discussed a lot on this, let's make a conclusion on it.

1. UEFI could append the reserved buffer in it's memory mapping.
2. These reserved buffer must be declared in DT, since we also need to
   support non-UEFI (uboot) at the same time.
3. Mailbox node should reference reserved buffer by phandle in DT. Then
   map the buffer as non-cacheable in driver.
4. These reserved buffer must use no-map property since it should be
   non-cacheable in driver.
5. A patch is necessary in kernel. If efi stub feature is enabled,
   arm kernel should not parse memory node or reserved memory buffer in
   DT any more. Arm kernel should either fetch memory information from 
   efi or DT. Currently arm kernel fetch both efi memory information and
   reserved buffer from DTB at the same time.

Do you agree on these points?

Regards
Haojian

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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Wed, 2015-08-26 at 00:00 +0800, Leo Yan wrote:
 On Tue, Aug 25, 2015 at 09:43:14PM +0800, Haojian Zhuang wrote:
  On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
 Are you then going to hack GRUB, release a special HiKey version of
 GRUB, not support any other versions, and still can your firmware
 UEFI?

I don't need to hack GRUB at all.
   
   Then it is working for you by pure chance alone.
   
   Please listen to the advice you are being given here; we're trying to
   ensure that your platform functions (and continues to function) as best
   it can.
  
  Since we discussed a lot on this, let's make a conclusion on it.
  
  1. UEFI could append the reserved buffer in it's memory mapping.
  2. These reserved buffer must be declared in DT, since we also need to
 support non-UEFI (uboot) at the same time.
  3. Mailbox node should reference reserved buffer by phandle in DT. Then
 map the buffer as non-cacheable in driver.
  4. These reserved buffer must use no-map property since it should be
 non-cacheable in driver.
 
 For more specific discussion for DTS, i list two options at here;
 
 - Option 1: just simply reserve memory regions through memory node,
   and mailbox node will directly use the buffer through reg ranges;
 
 - Option 2: use reserved-memory and mailbox node will refer phandle
   of reserved-memory;
 
 These two options both can work well with UEFI and Uboot, but option 1
 is more simple and straightforward; so i personally prefer it. But
 look forwarding your guys' suggestion.
 
 Option 1:
 
   memory@0 {
   device_type = memory;
   reg = 0x 0x 0x 0x05e0,
 0x 0x05f0 0x 0x00eff000,
 0x 0x06e0 0x 0x0060f000,
 0x 0x0741 0x 0x38bf;
   };
 
 [...]
 
   mailbox: mailbox@f751 {
   #mbox-cells = 1;
   compatible = hisilicon,hi6220-mbox;
   reg = 0x0 0xf751 0x0 0x1000, /* IPC_S */
 0x0 0x06dff800 0x0 0x0800; /* Mailbox buffer */
   interrupts = GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH;
   };
 
 Option 2:
 
   memory@0 {
   device_type = memory;
   reg = 0x0 0x0 0x0 0x4000;
   };
 
   reserved-memory {
   #address-cells = 2;
   #size-cells = 2;
   ranges;
 
   mcu_reserved: mcu_reserved@06dff000 {
   no-map;
   reg = 0x0 0x06dff000 0x0 0x1000,  /* MCU mailbox 
 buffer */
 0x0 0x05e0 0x0 0x0010,  /* MCU firmware 
 buffer */
 0x0 0x0740f000 0x0 0x1000;  /* MCU firmware 
 section */
   };
   };
 
 [...]
 
   mailbox: mailbox@f751 {
   #mbox-cells = 1;
   compatible = hisilicon,hi6220-mbox;
   reg = 0x0 0xf751 0x0 0x1000; /* IPC_S */
   memory-region = mcu_reserved;   /* Mailbox buffer */
   interrupts = GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH;
   };

I prefer the second one. From my view, memory node should only describe
the hardware information of memory.

Regards
Haojian

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Re: [PATCH v1 3/3] arm64: dts: add Hi6220 mailbox node

[Haojian Zhuang]

On Mon, 2015-08-24 at 10:51 +0100, Mark Rutland wrote:
 On Mon, Aug 24, 2015 at 10:18:45AM +0100, Leo Yan wrote:
  Hi Mark,
  
  On Fri, Aug 21, 2015 at 07:40:59PM +0100, Mark Rutland wrote:
   On Wed, Aug 19, 2015 at 10:37:35AM +0100, Leo Yan wrote:
On Hi6220, below memory regions in DDR have specific purpose:

  0x05e0, - 0x05ef,: For MCU firmware using at runtime;
  0x0740,f000 - 0x0740,: For MCU firmware's section;
  0x06df,f000 - 0x06df,: For mailbox message data.

This patch reserves these memory regions and add device node for
mailbox in dts.

Signed-off-by: Leo Yan leo@linaro.org
---
 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 20 
+---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi  |  8 
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts 
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539..d5470d3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -7,9 +7,6 @@
 
 /dts-v1/;
 
-/*Reserved 1MB memory for MCU*/
-/memreserve/ 0x05e0 0x0010;
-
 #include hi6220.dtsi
 
 / {
@@ -28,4 +25,21 @@
device_type = memory;
reg = 0x0 0x0 0x0 0x4000;
};
+
+   reserved-memory {
+   #address-cells = 2;
+   #size-cells = 2;
+   ranges;
+
+   mcu-buf@05e0 {
+   no-map;
+   reg = 0x0 0x05e0 0x0 0x0010,  /* MCU 
firmware buffer */
+ 0x0 0x0740f000 0x0 0x1000;  /* MCU 
firmware section */
+   };
+
+   mbox-buf@06dff000 {
+   no-map;
+   reg = 0x0 0x06dff000 0x0 0x1000;  /* 
Mailbox message buf */
+   };
+   };
   
   As far as I can see, it would be simpler to simply carve these out of the
   memory node.
   
   I don't see why you need reserved-memory here, given you're not referring 
   to
   these regions by phandle anyway.
  
  - Now we have enabled EFI_STUB, so the memory node will be removed in
kernel:
  efi_entry()
\- allocate_new_fdt_and_exit_boot()
  \- update_fdt();
  
Finally in kernel it cannot use memory node to carve out reseved
memory regions.
  
  - On the other hand, DTS's the memory node is to describes the
physical memory layout for the system; so it's better to use it only
to describe the hardware info for memory. We can use reserved-memory
to help manage the memory regions which are reserved from software
perspective.
 
 The fact that you have no-map means that the memory should not be
 described to the kernel as mappable in the first place. It's wrong to
 place such memory in the memory node, even if listed in reserved-memory.
 
 If your EFI memory map describes the memory as mappable, it is wrong.

When kernel is working, kernel will create its own page table based on
UEFI memory map. Since it's reserved in DTS file as Leo's patch, it'll
be moved to reserved memblock. Why is it wrong?

In the second, UEFI is firmware. When it's stable, nobody should change
it without any reason. These reserved memory are used in mailbox driver.
Look. It's driver, so it could be changed at any time. Why do you want
to UEFI knowing this memory range? Do you hope UEFI to change when
mailbox driver is changed?

 
  According to upper info, we still need to use reserved-memory node to
  depict the reserved memory regions. i have no knowledge about EFI_STUB,
  so please confirm or correct as needed.
 
 If the memory shouldn't be mapped, it should neither be in the memory
 node nor EFI memory map (with attributes allowing it to be mapped) to
 begin with.

As I said above, kernel will create its own page table. When kernel's
page table is working, UEFI's page table is destroying. So the memory
won't be mapped twice at the same time. What's wrong?
 
 As far as I can see you do not need to use reserved-memory.

1. Are we talking on the same thing? Leo already mentioned that all
memory node in DTB will be destroyed by kernel when EFI_STUB is enabled
on arm. Did you read the source code after his reply?
And you suggested that Leo to use discrete memory region in DTB. It is
really wrong. Kernel only gets memory map information from UEFI, not
DTB.

2. The working flow is in below.
   a. Kernel gets memory map information from UEFI.
   b. Kernel loads the memory reserved information from DTB.

3. Do you mean the reserved-memory is totally wrong? If it's wrong,
please submit patches to remove all reserved-memory in linux kernel
first.

4. Again and again. Memory node should be only used to describe the
RAM 

Re: [RESEND PATCH v6 0/2] ARM: hip04: add GPIO support

[Haojian Zhuang]

On 25 March 2015 at 14:57, Zhou Wang wangzh...@hisilicon.com wrote:
 This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
 synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
 corresponding dts. The default value of ARCH_NR_GPIOS is used to find gpio
 base here.

 Now this patchset is based on v4.0-rc5

 Change in v6:
 - Change E-mail address in signed-off-by to wangzh...@hisilicon.com
 Change in v5:
 - Base on v3.19-rc1
 - Just use default value of ARCH_NR_GPIOS to find gpio base. Remove the new
   added patch(3/4) in v4.
 Change in v4:
 - Delete default 128 if ARCH_HIP04 in arch/arm/Kconfig
 - add a new patch to support find GPIO base number in increasing order
 - add gpio-number-forward property in snps gpio binding doc
 Change in v3:
 - Move CONFIG_GPIO_DWAPB to hisi_defconfig
 - Add CONFIG_GPIOLIB, CONFIG_GPIO_SYSFS in hisi_defconfig
 Change in v2:
 - Add select GPIO_DWAPB in arch/arm/mach-hisi/Kconfig

 Link for v4:
 - http://www.spinics.net/lists/arm-kernel/msg383883.html
 Link for v3:
 - http://www.spinics.net/lists/devicetree/msg60324.html


 Zhou Wang (2):
   ARM: hip04: add GPIO configure in hisi_defconfig
   ARM: dts: hip04: add GPIO pieces

  arch/arm/boot/dts/hip04.dtsi| 75 
 +
  arch/arm/configs/hisi_defconfig |  1 +
  2 files changed, 76 insertions(+)

 --
 1.9.1

Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
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Re: [RESEND PATCH v3] mtd: hisilicon: add device tree node for NAND controller

[Haojian Zhuang]

On 25 March 2015 at 15:04, Zhou Wang wangzh...@hisilicon.com wrote:
 This patch adds dts support for NAND flash controller of Hisilicon Soc Hip04.
 Now it is based on v4.0-rc5

 Changes in v3:
 - Change E-mail address in signed-off-by to wangzh...@hisilicon.com
 Changes in v2:
 - Base on v3.19-rc1
 - Use nand-ecc-strength, nand-ecc-step-size to replace hisi,nand-ecc-bits
 Changes in v1:
 - Move partition and other board related information into board dts file:
   hip04-d01.dts

 Signed-off-by: Zhou Wang wangzh...@hisilicon.com
 ---
  arch/arm/boot/dts/hip04-d01.dts | 27 +++
  arch/arm/boot/dts/hip04.dtsi|  7 +++
  2 files changed, 34 insertions(+)

 diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
 index 40a9e33..ba04dd5 100644
 --- a/arch/arm/boot/dts/hip04-d01.dts
 +++ b/arch/arm/boot/dts/hip04-d01.dts
 @@ -28,5 +28,32 @@
 uart0: uart@4007000 {
 status = ok;
 };
 +
 +   nand: nand@402 {
 +   nand-bus-width = 8;
 +   nand-ecc-mode = hw;
 +   nand-ecc-strength = 16;
 +   nand-ecc-step-size = 1024;
 +
 +   partition@0 {
 +   label = nand_text;
 +   reg = 0x 0x0040;
 +   };
 +
 +   partition@0040 {
 +   label = nand_monitor;
 +   reg = 0x0040 0x0040;
 +   };
 +
 +   partition@0080 {
 +   label = nand_kernel;
 +   reg = 0x0080 0x0080;
 +   };
 +
 +   partition@0100 {
 +   label = nand_fs;
 +   reg = 0x0100 0x1f00;
 +   };
 +   };
 };
  };
 diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
 index 2388145..ac32fce 100644
 --- a/arch/arm/boot/dts/hip04.dtsi
 +++ b/arch/arm/boot/dts/hip04.dtsi
 @@ -269,6 +269,13 @@
 interrupts = 0 372 4;
 };

 +   nand: nand@402 {
 +   compatible = hisilicon,504-nfc;
 +   reg = 0x402 0x1, 0x500 0x1000;
 +   interrupts = 0 379 4;
 +   #address-cells = 1;
 +   #size-cells = 1;
 +   };
 };

 etb@0,e3c42000 {
 --
 1.9.1


Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
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Re: [PATCH v2 0/2] ARM: hip04: add GPIO support

[Haojian Zhuang]

On Wed, Nov 26, 2014 at 2:43 PM, Zhou Wang wangzhou@gmail.com wrote:
 This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
 synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
 corresponding dts.

 Change in v2:
 - Add select GPIO_DWAPB in arch/arm/mach-hisi/Kconfig

 Zhou Wang (2):
   ARM: hip04: set ARCH_NR_GPIO to 128
   ARM: dts: hip04: add GPIO pieces

  arch/arm/Kconfig |1 +
  arch/arm/boot/dts/hip04.dtsi |   75 
 ++
  arch/arm/mach-hisi/Kconfig   |1 +
  3 files changed, 77 insertions(+)

 --
 1.7.9.5


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Re: [PATCH v4 0/2] mtd: hisilicon: add a new driver for NAND controller of hisilicon hip04 Soc

[Haojian Zhuang]

On Tue, Nov 4, 2014 at 8:46 PM, Zhou Wang wangzhou@gmail.com wrote:
 This patchset adds the support for NAND controller of hisilicon hip04 Soc.
 The NAND controller IP was developed by hisilicon and needs a new driver to
 support it. This patchset is based on v3.18-rc1. I have tested that NAND flash
 controller works fine in Hip04 D01 board.

 Changes in v4:
 - add mtd-dev.parent = pdev-dev, thanks Frans Klaver.
 Changes in v3:
 - Modify code to eliminate some code style warnings.
 - add ecc-bits input check.
 - avoid using waterfall style in hisi_nfc_cmdfunc().
 Changes in v2:
 - Remove the patch for device tree, now patchset only has the driver and its
   device tree binding documentation.
 - Change the file name: hisi_nand.c to hisi504_nand.c.
 Changes in v1:
 - Remove callback functions out of struct hinfc_host, and call them directly
   in relative functions.
 - Change hinfc_read and hinfc_write from macros to inline functions.
 - Instead of putting pointers, embed struct nand_chip and struct mtd_info in
   struct hinfc_host directly.
 - rewrite some unclear lines in device tree binding document, correct some
   code style error.

 Link on v3:
 - https://lkml.org/lkml/2014/10/28/386
 Link on v2:
 - https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg750071.html
 Link on v1:
 - https://lkml.org/lkml/2014/7/15/198

 Zhou Wang (2):
   mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc
   mtd: hisilicon: add device tree binding documentation

  .../devicetree/bindings/mtd/hisi504-nand.txt   |   40 +
  drivers/mtd/nand/Kconfig   |5 +
  drivers/mtd/nand/Makefile  |1 +
  drivers/mtd/nand/hisi504_nand.c|  846 
 
  4 files changed, 892 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
  create mode 100644 drivers/mtd/nand/hisi504_nand.c

 --
 1.7.9.5


Hi David  Brian,

How do you think about this nand patch set? Could it be merged into v3.19?

Best Regards
Haojian
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Re: [PATCH V2 00/13] clk: mmp: clock device tree support

[Haojian Zhuang]

On 13 November 2014 08:35, Mike Turquette mturque...@linaro.org wrote:
 Quoting Haojian Zhuang (2014-11-04 00:15:55)
 On Fri, Oct 31, 2014 at 10:13 AM, Chao Xie chao@marvell.com wrote:
  From: Chao Xie chao@marvell.com
 
  The patch set focuses at support device tree for clock.
 
  The first part of the patches
clk: mmp: add prefix mmp for structures defined for clk-frac
clk: mmp: add spin lock for clk-frac
clk: mmp: add init callback for clk-frac
clk: mmp: move definiton of mmp_clk_frac to clk.h It enhances the 
  clk-frac.
 
  The second part of the patches
clk: mmp: add clock type mix
clk: mmp: add mmp private gate clock
 
  The third part of the patches
clk: mmp: add basic support functions for DT support
clk: mmp: add reset support
clk: mmp: add pxa168 DT support for clock driver
clk: mmp: add pxa910 DT support for clock driver
clk: mmp: add mmp2 DT support for clock driver
  It add the device tree support for pxa168, pxa910 and mmp2.
 
  V1 - V2:
Add reset support for the clocks that have reset bit.
 
  Chao Xie (13):
clk: mmp: add prefix mmp for structures defined for clk-frac
clk: mmp: add spin lock for clk-frac
clk: mmp: add init callback for clk-frac
clk: mmp: move definiton of mmp_clk_frac to clk.h
clk: mmp: add clock type mix
clk: mmp: add mmp private gate clock
clk: mmp: add basic support functions for DT support
clk: mmp: add reset support
clk: mmp: add pxa168 DT support for clock driver
clk: mmp: add pxa910 DT support for clock driver
clk: mmp: add mmp2 DT support for clock driver
arm: mmp: Make all the dts file to be compiled by Makefile
arm: mmp: Make use of the DT supported clock
 
   .../devicetree/bindings/clock/marvell,mmp2.txt |  21 +
   .../devicetree/bindings/clock/marvell,pxa168.txt   |  21 +
   .../devicetree/bindings/clock/marvell,pxa910.txt   |  21 +
   arch/arm/boot/dts/Makefile |   3 +
   arch/arm/boot/dts/mmp2-brownstone.dts  |   2 +-
   arch/arm/boot/dts/mmp2.dtsi|  29 +-
   arch/arm/boot/dts/pxa168-aspenite.dts  |   2 +-
   arch/arm/boot/dts/pxa168.dtsi  |  27 +-
   arch/arm/boot/dts/pxa910-dkb.dts   |   2 +-
   arch/arm/boot/dts/pxa910.dtsi  |  28 +-
   arch/arm/mach-mmp/Kconfig  |  12 +-
   arch/arm/mach-mmp/mmp-dt.c |  57 +--
   arch/arm/mach-mmp/mmp2-dt.c|  26 +-
   drivers/clk/mmp/Makefile   |   7 +-
   drivers/clk/mmp/clk-frac.c |  74 ++-
   drivers/clk/mmp/clk-gate.c | 133 ++
   drivers/clk/mmp/clk-mix.c  | 513 
  +
   drivers/clk/mmp/clk-mmp2.c |   6 +-
   drivers/clk/mmp/clk-of-mmp2.c  | 334 ++
   drivers/clk/mmp/clk-of-pxa168.c| 279 +++
   drivers/clk/mmp/clk-of-pxa910.c| 301 
   drivers/clk/mmp/clk-pxa168.c   |   6 +-
   drivers/clk/mmp/clk-pxa910.c   |   6 +-
   drivers/clk/mmp/clk.c  | 192 
   drivers/clk/mmp/clk.h  | 226 -
   drivers/clk/mmp/reset.c|  99 
   drivers/clk/mmp/reset.h|  31 ++
   include/dt-bindings/clock/marvell,mmp2.h   |  74 +++
   include/dt-bindings/clock/marvell,pxa168.h |  57 +++
   include/dt-bindings/clock/marvell,pxa910.h |  54 +++
   30 files changed, 2538 insertions(+), 105 deletions(-)
   create mode 100644 
  Documentation/devicetree/bindings/clock/marvell,mmp2.txt
   create mode 100644 
  Documentation/devicetree/bindings/clock/marvell,pxa168.txt
   create mode 100644 
  Documentation/devicetree/bindings/clock/marvell,pxa910.txt
   create mode 100644 drivers/clk/mmp/clk-gate.c
   create mode 100644 drivers/clk/mmp/clk-mix.c
   create mode 100644 drivers/clk/mmp/clk-of-mmp2.c
   create mode 100644 drivers/clk/mmp/clk-of-pxa168.c
   create mode 100644 drivers/clk/mmp/clk-of-pxa910.c
   create mode 100644 drivers/clk/mmp/clk.c
   create mode 100644 drivers/clk/mmp/reset.c
   create mode 100644 drivers/clk/mmp/reset.h
   create mode 100644 include/dt-bindings/clock/marvell,mmp2.h
   create mode 100644 include/dt-bindings/clock/marvell,pxa168.h
   create mode 100644 include/dt-bindings/clock/marvell,pxa910.h
 
  --
  1.8.3.2
 

 Acked-by: Haojian Zhuang haojian.zhu...@gmail.com

 Mike,
 Please merge all mach-mmp patches with clock together. Otherwise, it
 may result in build issue.

 Can patches #12  #13 go through arm-soc?


Hi Mike,

I also hope so. But patch #12 makes those dtb files built
automatically. And patch #13
references clocks that are defined in dt-binding files. If I merge
patch #12  #13, I'll

Re: [PATCH v4 0/2] mtd: hisilicon: add a new driver for NAND controller of hisilicon hip04 Soc

[Haojian Zhuang]

On Tue, Nov 4, 2014 at 8:46 PM, Zhou Wang wangzhou@gmail.com wrote:
 This patchset adds the support for NAND controller of hisilicon hip04 Soc.
 The NAND controller IP was developed by hisilicon and needs a new driver to
 support it. This patchset is based on v3.18-rc1. I have tested that NAND flash
 controller works fine in Hip04 D01 board.

 Changes in v4:
 - add mtd-dev.parent = pdev-dev, thanks Frans Klaver.
 Changes in v3:
 - Modify code to eliminate some code style warnings.
 - add ecc-bits input check.
 - avoid using waterfall style in hisi_nfc_cmdfunc().
 Changes in v2:
 - Remove the patch for device tree, now patchset only has the driver and its
   device tree binding documentation.
 - Change the file name: hisi_nand.c to hisi504_nand.c.
 Changes in v1:
 - Remove callback functions out of struct hinfc_host, and call them directly
   in relative functions.
 - Change hinfc_read and hinfc_write from macros to inline functions.
 - Instead of putting pointers, embed struct nand_chip and struct mtd_info in
   struct hinfc_host directly.
 - rewrite some unclear lines in device tree binding document, correct some
   code style error.

 Link on v3:
 - https://lkml.org/lkml/2014/10/28/386
 Link on v2:
 - https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg750071.html
 Link on v1:
 - https://lkml.org/lkml/2014/7/15/198

 Zhou Wang (2):
   mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc
   mtd: hisilicon: add device tree binding documentation

  .../devicetree/bindings/mtd/hisi504-nand.txt   |   40 +
  drivers/mtd/nand/Kconfig   |5 +
  drivers/mtd/nand/Makefile  |1 +
  drivers/mtd/nand/hisi504_nand.c|  846 
 
  4 files changed, 892 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
  create mode 100644 drivers/mtd/nand/hisi504_nand.c

 --
 1.7.9.5


Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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Re: [PATCH V2 00/13] clk: mmp: clock device tree support

[Haojian Zhuang]

On Fri, Oct 31, 2014 at 10:13 AM, Chao Xie chao@marvell.com wrote:
 From: Chao Xie chao@marvell.com

 The patch set focuses at support device tree for clock.

 The first part of the patches
   clk: mmp: add prefix mmp for structures defined for clk-frac
   clk: mmp: add spin lock for clk-frac
   clk: mmp: add init callback for clk-frac
   clk: mmp: move definiton of mmp_clk_frac to clk.h It enhances the clk-frac.

 The second part of the patches
   clk: mmp: add clock type mix
   clk: mmp: add mmp private gate clock

 The third part of the patches
   clk: mmp: add basic support functions for DT support
   clk: mmp: add reset support
   clk: mmp: add pxa168 DT support for clock driver
   clk: mmp: add pxa910 DT support for clock driver
   clk: mmp: add mmp2 DT support for clock driver
 It add the device tree support for pxa168, pxa910 and mmp2.

 V1 - V2:
   Add reset support for the clocks that have reset bit.

 Chao Xie (13):
   clk: mmp: add prefix mmp for structures defined for clk-frac
   clk: mmp: add spin lock for clk-frac
   clk: mmp: add init callback for clk-frac
   clk: mmp: move definiton of mmp_clk_frac to clk.h
   clk: mmp: add clock type mix
   clk: mmp: add mmp private gate clock
   clk: mmp: add basic support functions for DT support
   clk: mmp: add reset support
   clk: mmp: add pxa168 DT support for clock driver
   clk: mmp: add pxa910 DT support for clock driver
   clk: mmp: add mmp2 DT support for clock driver
   arm: mmp: Make all the dts file to be compiled by Makefile
   arm: mmp: Make use of the DT supported clock

  .../devicetree/bindings/clock/marvell,mmp2.txt |  21 +
  .../devicetree/bindings/clock/marvell,pxa168.txt   |  21 +
  .../devicetree/bindings/clock/marvell,pxa910.txt   |  21 +
  arch/arm/boot/dts/Makefile |   3 +
  arch/arm/boot/dts/mmp2-brownstone.dts  |   2 +-
  arch/arm/boot/dts/mmp2.dtsi|  29 +-
  arch/arm/boot/dts/pxa168-aspenite.dts  |   2 +-
  arch/arm/boot/dts/pxa168.dtsi  |  27 +-
  arch/arm/boot/dts/pxa910-dkb.dts   |   2 +-
  arch/arm/boot/dts/pxa910.dtsi  |  28 +-
  arch/arm/mach-mmp/Kconfig  |  12 +-
  arch/arm/mach-mmp/mmp-dt.c |  57 +--
  arch/arm/mach-mmp/mmp2-dt.c|  26 +-
  drivers/clk/mmp/Makefile   |   7 +-
  drivers/clk/mmp/clk-frac.c |  74 ++-
  drivers/clk/mmp/clk-gate.c | 133 ++
  drivers/clk/mmp/clk-mix.c  | 513 
 +
  drivers/clk/mmp/clk-mmp2.c |   6 +-
  drivers/clk/mmp/clk-of-mmp2.c  | 334 ++
  drivers/clk/mmp/clk-of-pxa168.c| 279 +++
  drivers/clk/mmp/clk-of-pxa910.c| 301 
  drivers/clk/mmp/clk-pxa168.c   |   6 +-
  drivers/clk/mmp/clk-pxa910.c   |   6 +-
  drivers/clk/mmp/clk.c  | 192 
  drivers/clk/mmp/clk.h  | 226 -
  drivers/clk/mmp/reset.c|  99 
  drivers/clk/mmp/reset.h|  31 ++
  include/dt-bindings/clock/marvell,mmp2.h   |  74 +++
  include/dt-bindings/clock/marvell,pxa168.h |  57 +++
  include/dt-bindings/clock/marvell,pxa910.h |  54 +++
  30 files changed, 2538 insertions(+), 105 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/clock/marvell,mmp2.txt
  create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa168.txt
  create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa910.txt
  create mode 100644 drivers/clk/mmp/clk-gate.c
  create mode 100644 drivers/clk/mmp/clk-mix.c
  create mode 100644 drivers/clk/mmp/clk-of-mmp2.c
  create mode 100644 drivers/clk/mmp/clk-of-pxa168.c
  create mode 100644 drivers/clk/mmp/clk-of-pxa910.c
  create mode 100644 drivers/clk/mmp/clk.c
  create mode 100644 drivers/clk/mmp/reset.c
  create mode 100644 drivers/clk/mmp/reset.h
  create mode 100644 include/dt-bindings/clock/marvell,mmp2.h
  create mode 100644 include/dt-bindings/clock/marvell,pxa168.h
  create mode 100644 include/dt-bindings/clock/marvell,pxa910.h

 --
 1.8.3.2


Acked-by: Haojian Zhuang haojian.zhu...@gmail.com

Mike,
Please merge all mach-mmp patches with clock together. Otherwise, it
may result in build issue.

Best Regards
Haojian
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Re: [PATCH v1 0/2] ARM: hip04: add GPIO support

[Haojian Zhuang]

On Wed, Oct 22, 2014 at 7:55 PM, Zhou Wang wangzhou@gmail.com wrote:
 This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
 synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
 corresponding dts.

 As the hip04 basic dts has been merged in 3.18 mainline kernel, I just resend
 this patchset for review.

 Zhou Wang (2):
   ARM: hip04: set ARCH_NR_GPIO to 128
   ARM: dts: hip04: add GPIO pieces

  arch/arm/Kconfig |1 +
  arch/arm/boot/dts/hip04.dtsi |   75 
 ++
  2 files changed, 76 insertions(+)


Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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Re: [PATCH v2 1/2] mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc

[Haojian Zhuang]

On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang wangzhou@gmail.com wrote:
 Signed-off-by: Zhou Wang wangzhou@gmail.com
 ---
  drivers/mtd/nand/Kconfig|5 +
  drivers/mtd/nand/Makefile   |1 +
  drivers/mtd/nand/hisi504_nand.c |  836 
 +++
  3 files changed, 842 insertions(+)
  create mode 100644 drivers/mtd/nand/hisi504_nand.c


I think that you need to run scripts/checkpatch.pl. There're some
warnings reported on this patch.

 +
 +   case NAND_CMD_SEQIN:
 +   host-offset = column;
 +

It's better not using waterfall style. Maybe you can write it clearly.
case NAND_CMD_SEQIN:
host-offset = column;
set_addr(mtd, column, page_addr);
break;

 +   chip-ecc.mode = of_get_nand_ecc_mode(np);
 +   /* read ecc-bits from dts */
 +   of_property_read_u32(np, hisi,nand-ecc-bits, host-ecc_bits);

Do you need to check the ecc_bits at here? Maybe user inputed the
wrong ecc_bits in DTS.

Best Regards
Haojian
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Re: [PATCH] ARM: dts: hip04: NAND controller support

[Haojian Zhuang]

On Thu, Oct 23, 2014 at 4:24 PM, Zhou Wang wangzhou@gmail.com wrote:
 This patch adds dts support of NAND flash controller for Hisilicon Soc Hip04.
 The patch is based on v3.18-rc1. I have tested that NAND flash controller
 works fine in Hip04 D01 board.

 Signed-off-by: Zhou Wang wangzhou@gmail.com
 ---
  arch/arm/boot/dts/hip04.dtsi |   30 ++
  1 file changed, 30 insertions(+)

 diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
 index 93b6c90..642a160 100644
 --- a/arch/arm/boot/dts/hip04.dtsi
 +++ b/arch/arm/boot/dts/hip04.dtsi
 @@ -263,5 +263,35 @@
 interrupts = 0 372 4;
 };

 +   nand: nand@402 {
 +   compatible = hisilicon,504-nfc;
 +   reg = 0x402 0x1, 0x500 0x1000;
 +   interrupts = 0 379 4;
 +   nand-bus-width = 8;
 +   nand-ecc-mode = none;
 +   hisi,nand-ecc-bits = 0;
 +   #address-cells = 1;
 +   #size-cells = 1;
 +
 +   partition@0 {
 +   label = nand_text;
 +   reg = 0x 0x0040;
 +   };
 +
 +   partition@0040 {
 +   label = nand_monitor;
 +   reg = 0x0040 0x0040;
 +   };
 +
 +   partition@0080 {
 +   label = nand_kernel;
 +   reg = 0x0080 0x0080;
 +   };
 +
 +   partition@0100 {
 +   label = nand_fs;
 +   reg = 0x0100 0x1f00;
 +   };

Partitions are different on different boards. But nand controller is
same on each chip. You
should define nand controller in soc dtsi file, and define partition
in board dts file.

Regards
Haojian
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Re: [PATCH] gpio: pl061 : fix gpio pl061 request bug

[Haojian Zhuang]

On 9 October 2014 20:03, Xinwei Kong kong.kongxin...@hisilicon.com wrote:
 From: k00278426 kong.kongxin...@hisilicon.com

 Some gpio controller dts nodes has no gpio-range property will cause gpio
 request fail(return -517).
 Maybe in this case gpio request shouldn't go into pinctrl subsystem.

 This patch try to resolve this gpio request issue.

 Signed-off-by: k00278426 kong.kongxin...@hisilicon.com
 Signed-off-by: Yunlei He heyun...@huawei.com
 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
 ---
  drivers/gpio/gpio-pl061.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
 index 84b49cf..37ffe38 100644
 --- a/drivers/gpio/gpio-pl061.c
 +++ b/drivers/gpio/gpio-pl061.c
 @@ -24,6 +24,7 @@
  #include linux/slab.h
  #include linux/pinctrl/consumer.h
  #include linux/pm.h
 +#include linux/of_address.h

  #define GPIODIR 0x400
  #define GPIOIS  0x404
 @@ -264,8 +265,10 @@ static int pl061_probe(struct amba_device *adev, const 
 struct amba_id *id)

 spin_lock_init(chip-lock);

 -   chip-gc.request = pl061_gpio_request;
 -   chip-gc.free = pl061_gpio_free;
 +   if (of_get_property(dev-of_node, gpio-ranges, NULL)) {
 +   chip-gc.request = pl061_gpio_request;
 +   chip-gc.free = pl061_gpio_free;
 +   }

Hi Xinwei,

Please follow the comments from Linus in the previous mail thread.

Regards
Haojian
 chip-gc.direction_input = pl061_direction_input;
 chip-gc.direction_output = pl061_direction_output;
 chip-gc.get = pl061_get_value;
 --
 1.9.1


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Re: [PATCH 1/2] ARM: pxa: dts: fix mmc controller compatible string

[Haojian Zhuang]

On Thu, Aug 14, 2014 at 5:46 PM, Daniel Mack zon...@gmail.com wrote:
 The vendor prefix was renamed from mrvl to marvell. Follow this
 change in the dts file.

 Signed-off-by: Daniel Mack zon...@gmail.com
 ---
  arch/arm/boot/dts/pxa2xx.dtsi | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
 index febd391..f188f8c 100644
 --- a/arch/arm/boot/dts/pxa2xx.dtsi
 +++ b/arch/arm/boot/dts/pxa2xx.dtsi
 @@ -128,7 +128,7 @@
 };

 mmc0: mmc@4110 {
 -   compatible = mrvl,pxa-mmc;
 +   compatible = marvell,pxa-mmc;
 reg = 0x4110 0x1000;
 interrupts = 23;
 dmas = dma 21
 --
 2.0.4


Applied these 2 patches.

Regards
Haojian
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Re: [PATCH 00/12] clk: mmp: clock device tree support

[Haojian Zhuang]

On 26 August 2014 12:38, Chao Xie chao@marvell.com wrote:
 From: Chao Xie chao@marvell.com

 The patch set focuses at support device tree for clock.

 The first part of the patches
   clk: mmp: add prefix mmp for structures defined for clk-frac
   clk: mmp: add spin lock for clk-frac
   clk: mmp: add init callback for clk-frac
   clk: mmp: move definiton of mmp_clk_frac to clk.h It enhances the clk-frac.

 The second part of the patches
   clk: mmp: add clock type mix
   clk: mmp: add mmp private gate clock

 The third part of the patches
   clk: mmp: add basic support functions for DT support
   clk: mmp: add pxa168 DT support for clock driver
   clk: mmp: add pxa910 DT support for clock driver
   clk: mmp: add mmp2 DT support for clock driver
 It add the device tree support for pxa168, pxa910 and mmp2.

 The final part of the patches
   arm: mmp: Make all the dts file to be compiled by Makefile
   arm: mmp: Make use of the DT supported clock
 It changes the mmp platform to use device tree to parse the clocks.

 Chao Xie (12):
   clk: mmp: add prefix mmp for structures defined for clk-frac
   clk: mmp: add spin lock for clk-frac
   clk: mmp: add init callback for clk-frac
   clk: mmp: move definiton of mmp_clk_frac to clk.h
   clk: mmp: add clock type mix
   clk: mmp: add mmp private gate clock
   clk: mmp: add basic support functions for DT support
   clk: mmp: add pxa168 DT support for clock driver
   clk: mmp: add pxa910 DT support for clock driver
   clk: mmp: add mmp2 DT support for clock driver
   arm: mmp: Make all the dts file to be compiled by Makefile
   arm: mmp: Make use of the DT supported clock

  .../bindings/clock/marvell-mmp2-clock.txt  |  20 +
  .../bindings/clock/marvell-pxa168-clock.txt|  20 +
  .../bindings/clock/marvell-pxa910-clock.txt|  20 +
  arch/arm/boot/dts/Makefile |   3 +
  arch/arm/boot/dts/mmp2-brownstone.dts  |   2 +-
  arch/arm/boot/dts/mmp2.dtsi|  20 +-
  arch/arm/boot/dts/pxa168-aspenite.dts  |   2 +-
  arch/arm/boot/dts/pxa168.dtsi  |  19 +-
  arch/arm/boot/dts/pxa910-dkb.dts   |   2 +-
  arch/arm/boot/dts/pxa910.dtsi  |  20 +-
  arch/arm/mach-mmp/Kconfig  |  10 +-
  arch/arm/mach-mmp/mmp-dt.c |  57 +--
  arch/arm/mach-mmp/mmp2-dt.c|  26 +-
  drivers/clk/mmp/Makefile   |   5 +-
  drivers/clk/mmp/clk-frac.c |  74 ++-
  drivers/clk/mmp/clk-gate.c | 133 ++
  drivers/clk/mmp/clk-mix.c  | 513 
 +
  drivers/clk/mmp/clk-mmp2.c |   6 +-
  drivers/clk/mmp/clk-of-mmp2.c  | 307 
  drivers/clk/mmp/clk-of-pxa168.c| 251 ++
  drivers/clk/mmp/clk-of-pxa910.c| 260 +++
  drivers/clk/mmp/clk-pxa168.c   |   6 +-
  drivers/clk/mmp/clk-pxa910.c   |   6 +-
  drivers/clk/mmp/clk.c  | 192 
  drivers/clk/mmp/clk.h  | 226 -
  include/dt-bindings/clock/marvell-mmp2.h   |  74 +++
  include/dt-bindings/clock/marvell-pxa168.h |  57 +++
  include/dt-bindings/clock/marvell-pxa910.h |  54 +++
  28 files changed, 2280 insertions(+), 105 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/clock/marvell-mmp2-clock.txt
  create mode 100644 
 Documentation/devicetree/bindings/clock/marvell-pxa168-clock.txt
  create mode 100644 
 Documentation/devicetree/bindings/clock/marvell-pxa910-clock.txt
  create mode 100644 drivers/clk/mmp/clk-gate.c
  create mode 100644 drivers/clk/mmp/clk-mix.c
  create mode 100644 drivers/clk/mmp/clk-of-mmp2.c
  create mode 100644 drivers/clk/mmp/clk-of-pxa168.c
  create mode 100644 drivers/clk/mmp/clk-of-pxa910.c
  create mode 100644 drivers/clk/mmp/clk.c
  create mode 100644 include/dt-bindings/clock/marvell-mmp2.h
  create mode 100644 include/dt-bindings/clock/marvell-pxa168.h
  create mode 100644 include/dt-bindings/clock/marvell-pxa910.h

 --
 1.8.3.2


Hi Mike,

I think that these clock patches are ready to merge. I want to go
through arm-soc tree since chao will also move timer into clock source
directory. Those patches will be depend on these clock patches.

Could you help to give your Ack on these patches?

Best Regards
Haojian
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Re: [PATCH v3 1/6] clk: add pxa clocks infrastructure

[Haojian Zhuang]

On Thu, Jul 31, 2014 at 4:50 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Add a the common code used by all PXA variants.

 This is the first step in the transition from architecture defined
 clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to
 have the same features (and not all the features) of the existing
 clocks, and enable the transition of PXA to device-tree.

 All PXA rely on a CKEN type clock, which :
  - has a gate (bit in CKEN register)
  - is generated from a PLL, generally divided
  - has an alternate low power clock

 Each variant will specialize the CKEN clock :
  - pxa25x have no low power clock
  - pxa27x in low power use always the 13 MHz ring oscillator
  - pxa3xx in low power have specific dividers for each clock

 The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get
 a handle on the clock. While pxa-clock.h will describe all the clocks of
 all the variants, each variant will only use a subset of it.

 Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
 ---
  drivers/clk/Makefile  |   1 +
  drivers/clk/pxa/Makefile  |   1 +
  drivers/clk/pxa/clk-pxa.c |  97 ++
  drivers/clk/pxa/clk-pxa.h | 107 
 ++
  include/dt-bindings/clock/pxa-clock.h |  77 
  5 files changed, 283 insertions(+)
  create mode 100644 drivers/clk/pxa/Makefile
  create mode 100644 drivers/clk/pxa/clk-pxa.c
  create mode 100644 drivers/clk/pxa/clk-pxa.h
  create mode 100644 include/dt-bindings/clock/pxa-clock.h

 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
 index 567f102..40390ea 100644
 --- a/drivers/clk/Makefile
 +++ b/drivers/clk/Makefile
 @@ -43,6 +43,7 @@ obj-$(CONFIG_ARCH_MMP)+= mmp/
  endif
  obj-$(CONFIG_PLAT_ORION)   += mvebu/
  obj-$(CONFIG_ARCH_MXS) += mxs/
 +obj-$(CONFIG_ARCH_PXA) += pxa/
  obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
  obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
 diff --git a/drivers/clk/pxa/Makefile b/drivers/clk/pxa/Makefile
 new file mode 100644
 index 000..cb2bd8f
 --- /dev/null
 +++ b/drivers/clk/pxa/Makefile
 @@ -0,0 +1 @@
 +obj-y  += clk-pxa.o
 diff --git a/drivers/clk/pxa/clk-pxa.c b/drivers/clk/pxa/clk-pxa.c
 new file mode 100644
 index 000..ef3c053
 --- /dev/null
 +++ b/drivers/clk/pxa/clk-pxa.c
 @@ -0,0 +1,97 @@
 +/*
 + * Marvell PXA family clocks
 + *
 + * Copyright (C) 2014 Robert Jarzmik
 + *
 + * Common clock code for PXA clocks (CKEN type clocks + DT)
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; version 2 of the License.
 + *
 + */
 +#include linux/clk.h
 +#include linux/clk-provider.h
 +#include linux/clkdev.h
 +#include linux/of.h
 +
 +#include dt-bindings/clock/pxa-clock.h
 +#include clk-pxa.h
 +
 +DEFINE_SPINLOCK(lock);
 +
 +static struct clk *pxa_clocks[CLK_MAX];
 +static struct clk_onecell_data onecell_data = {
 +   .clks = pxa_clocks,
 +   .clk_num = CLK_MAX,
 +};
 +
 +#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
 +
 +static unsigned long cken_recalc_rate(struct clk_hw *hw,
 + unsigned long parent_rate)
 +{
 +   struct pxa_clk_cken *pclk = to_pxa_clk(hw);
 +   struct clk_fixed_factor *fix;
 +
 +   if (!pclk-is_in_low_power || pclk-is_in_low_power())
 +   fix = pclk-lp;
 +   else
 +   fix = pclk-hp;
 +   fix-hw.clk = hw-clk;
 +   return clk_fixed_factor_ops.recalc_rate(fix-hw, parent_rate);
 +}
 +
 +static struct clk_ops cken_rate_ops = {
 +   .recalc_rate = cken_recalc_rate,
 +};
 +
 +static u8 cken_get_parent(struct clk_hw *hw)
 +{
 +   struct pxa_clk_cken *pclk = to_pxa_clk(hw);
 +
 +   if (!pclk-is_in_low_power)
 +   return 0;
 +   return pclk-is_in_low_power() ? 0 : 1;
 +}
 +
 +static struct clk_ops cken_mux_ops = {
 +   .get_parent = cken_get_parent,
 +   .set_parent = dummy_clk_set_parent,
 +};
 +
 +void __init clkdev_pxa_register(int ckid, const char *con_id,
 +   const char *dev_id, struct clk *clk)
 +{
 +   if (!IS_ERR(clk)  (ckid != CLK_NONE))

Will you specify CLK_NONE in clock driver? It seems that CLK_NONE
isn't used in pxa27x clock driver. And pxa_clocks[0] is not used. Is
it redundant?

 +   pxa_clocks[ckid] = clk;
 +   if (!IS_ERR(clk))
 +   clk_register_clkdev(clk, con_id, dev_id);
 +}
 +
 +int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
 +{
 +   int i;
 +   struct pxa_clk_cken *pclk;
 +   struct clk *clk;
 +
 +   for (i = 0; i  nb_clks; i++) {
 +   pclk = clks + i;
 +   pclk-gate.lock = lock;
 

Re: [PATCH v3 0/6] Migrate PXA27x platforms to clock framework

[Haojian Zhuang]

On Thu, Jul 31, 2014 at 4:50 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 This is the third opus of this serie.
 From the previous one :
  - the boot ordering was fixed
For DT, we rely on time_init() in arch/arm
For non-DT, we keep the postcore_init() until all 3 PXA variants are
converted, and meanwhile I'll discuss with Haojian where to call directly 
 the
clocks init function.
  - the section mismatches were fixed
A split is done between CKEN clock descriptor and CKEN clock structure

 The result was tested with a Mitac MIO A701 :
  - with the upstream platform-data based machine code
  - with the device-tree version

 As for the patches, if they are carried fully by Mike, I think there will be a
 minor conflict in arch/arm/mach-pxa/Makefile with the clocksource patches I
 submitted earlier.

 As before, the goal remains the same :
  - keeping legacy platforms working (ie. without device-tree)
  - enable PXA27x to work with a device-tree kernel, and hence
open the way to drivers conversion
  - be robust enough to support pxa25x and pxa3xx later inclusion
with almost no change to clk-pxa-dt.c.

 Robert Jarzmik (6):
   clk: add pxa clocks infrastructure
   clk: dts: document pxa clock binding
   arm: pxa: add clock pll selection bits
   clk: add pxa27x clock drivers
   dts: add devicetree bindings for pxa27x clocks
   arm: pxa: Transition pxa27x to clk framework

  .../devicetree/bindings/clock/pxa-clock.txt|  16 +
  arch/arm/Kconfig   |   1 +
  arch/arm/boot/dts/pxa27x.dtsi  |  20 +-
  arch/arm/mach-pxa/Makefile |   8 +-
  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h   |  10 +
  arch/arm/mach-pxa/pxa27x.c | 186 +--
  drivers/clk/Makefile   |   1 +
  drivers/clk/pxa/Makefile   |   2 +
  drivers/clk/pxa/clk-pxa.c  |  97 ++
  drivers/clk/pxa/clk-pxa.h  | 107 ++
  drivers/clk/pxa/clk-pxa27x.c   | 370 
 +
  include/dt-bindings/clock/pxa-clock.h  |  77 +
  12 files changed, 716 insertions(+), 179 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/clock/pxa-clock.txt
  create mode 100644 drivers/clk/pxa/Makefile
  create mode 100644 drivers/clk/pxa/clk-pxa.c
  create mode 100644 drivers/clk/pxa/clk-pxa.h
  create mode 100644 drivers/clk/pxa/clk-pxa27x.c
  create mode 100644 include/dt-bindings/clock/pxa-clock.h

 --
 2.0.0.rc2


Acked-by: Haojian Zhuang haojian.zhu...@gmail.com

Only with a small comment.

Regards
Haojian
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Re: [PATCH v2 0/6] Migrate PXA27x platforms to clock framework

[Haojian Zhuang]

On Sat, Jul 26, 2014 at 4:52 PM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Mike Turquette mturque...@linaro.org writes:

 Quoting Robert Jarzmik (2014-07-21 11:23:51)
 Robert Jarzmik robert.jarz...@free.fr writes:

  This is the second opus of this serie.

 Ping ?

 Hi Robert,

 Overall the series looks good to me. The only problem I see is that
 somewhere in the use of the PARENTS() macro there is a section mismatch
 introduced. I spent about 5 minutes looking at it and gave up. This
 problem introduces 26 section mismatch warnings building
 colibri_pxa270_defconfig.
 OK Mike, I'll fix this. This is probably because pxa27x_clocks array is not
 __init, and it references parents which are __init. I was lazy letting
 pxa27x_clocks not __init because I reuse the internal fields hw and 
 gate-hw
 later (hence I didn't leave the __init).
 This is a bit dirty and I'll launder it.

 Moreover, I have one fix which I had fixed wrt boot ordering : the
 postcore_init() must die. The reason behind is that I have no guarantee of
 ordering between clocks init and clocksource init, and clocksource relies on
 clocks.

 The right way will be AFAIK to call the core clocks init :
  - within the device-tree initialization function : pxa27x_dt_clocks_init()
  calls pxa27x_clocks_init9)
  - directly from pxa27x_init() or pxa_timer_init() in non-device tree setup

 Once those are fixed up then I will be happy to take this series. Do you
 want me to take all six patches through the clk tree, including the
 arm/arm stuff?
 I would feel more comfortable if :
  - you take the 4 first ones (3 clock ones + 1 arm pxa header bit definitions)
  - Haojian takes the last 2 ones (pxa ones)

I prefer that all these patches could go through clock tree. I just
want to avoid
build issue.

Acked-by: Haojian Zhuang haojian.zhu...@gmail.com

Regards
Haojian
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Re: [PATCH 1/4] clk: add pxa27x clock drivers

[Haojian Zhuang]

On Mon, Jun 30, 2014 at 2:32 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk.
 In the move :
  - convert to new clock framework legacy clocks
  - provide clocks as before for platform data based boards
  - provide clocks through devicetree with clk-pxa-dt

 This is the preliminary step in the conversion. The remaining steps are
 :
  - migrate pxa25x and pxa3xx
  - once PXA is fully converted to device tree, if that happens,
clk-pxa2* and clk-pxa3* should only hold the core clocks which cannot
be described in devicetree.

 Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
 ---
  drivers/clk/Makefile |   1 +
  drivers/clk/pxa/Makefile |   4 +
  drivers/clk/pxa/clk-pxa-dt.c |  76 ++
  drivers/clk/pxa/clk-pxa27x.c | 324 
 +++
  drivers/clk/pxa/clk-pxa2xx.c |  74 ++
  drivers/clk/pxa/clk-pxa2xx.h |  47 +++
  6 files changed, 526 insertions(+)
  create mode 100644 drivers/clk/pxa/Makefile
  create mode 100644 drivers/clk/pxa/clk-pxa-dt.c
  create mode 100644 drivers/clk/pxa/clk-pxa27x.c
  create mode 100644 drivers/clk/pxa/clk-pxa2xx.c
  create mode 100644 drivers/clk/pxa/clk-pxa2xx.h

 +
 +static struct pxa27x_clocks_fixed_cken pxa27x_without_dt_clocks[] __initdata 
 = {
 +   PXA2_FIXED_RATE(pxa2xx-uart.0, NULL, FFUART, 14857000, 1),
 +   PXA2_FIXED_RATE(pxa2xx-uart.1, NULL, BTUART, 14857000, 1),
 +   PXA2_FIXED_RATE(pxa2xx-uart.2, NULL, STUART, 14857000, 1),
 +   PXA2_FIXED_RATE(NULL, UARTCLK, STUART, 14857000, 1),
 +   PXA2_FIXED_RATE(pxa2xx-i2s, NULL, I2S, 14682000, 0),
 +   PXA2_FIXED_RATE(pxa2xx-i2c.0, NULL, I2C, 32842000, 0),
 +   PXA2_FIXED_RATE(pxa27x-udc, NULL, USB, 4800, 5),
 +   PXA2_FIXED_RATE(pxa2xx-mci.0, NULL, MMC, 1950, 0),
 +   PXA2_FIXED_RATE(pxa2xx-ir, FICPCLK, FICP, 4800, 0),
 +   PXA2_FIXED_RATE(pxa27x-ohci, NULL, USBHOST, 4800, 0),
 +   PXA2_FIXED_RATE(pxa2xx-i2c.1, NULL, PWRI2C, 1300, 0),
 +   PXA2_FIXED_RATE(pxa27x-keypad, NULL, KEYPAD, 32768, 0),
 +   PXA2_FIXED_RATE(pxa27x-ssp.0, NULL, SSP1, 1300, 0),
 +   PXA2_FIXED_RATE(pxa27x-ssp.1, NULL, SSP2, 1300, 0),
 +   PXA2_FIXED_RATE(pxa27x-ssp.2, NULL, SSP3, 1300, 0),
 +   PXA2_FIXED_RATE(pxa27x-pwm.0, NULL, PWM0, 1300, 0),
 +   PXA2_FIXED_RATE(pxa27x-pwm.1, NULL, PWM1, 1300, 0),
 +   PXA2_FIXED_RATE(NULL, AC97CLK, AC97, 24576000, 0),
 +   PXA2_FIXED_RATE(NULL, AC97CONFCLK, AC97CONF, 24576000, 0),
 +   PXA2_FIXED_RATE(NULL, MSLCLK, MSL, 4800, 0),
 +   PXA2_FIXED_RATE(NULL, USIMCLK, USIM, 4800, 0),
 +   PXA2_FIXED_RATE(NULL, MSTKCLK, MEMSTK, 1950, 0),
 +   PXA2_FIXED_RATE(NULL, IMCLK, IM, 0, 0),
 +   PXA2_FIXED_RATE_AO(pxa27x-memc, MEMCLK, MEMC, 0, 0),
 +};
 +
 +static struct pxa27x_clocks_var_rate pxa27x_var_rate_clocks[] __initdata = {
 +   PXA2_VAR_RATE(pxa2xx-fb, true, LCD, clk_pxa27x_lcd_ops),
 +   PXA2_VAR_RATE(pxa27x-camera.0, true, CAMERA, clk_pxa27x_lcd_ops),
 +   PXA2_VAR_RATE(pxa2xx-pcmcia, false, MEMC, clk_pxa27x_mem_ops),
 +};
 +

It's not good to define a VAR table any more.

Now we have the common clock framework. Since these three clocks are
used as clock
gate. And their clock frequency is controlled by other bits in
peripheral controller registers.
We can define parent  child clocks in clock tables. I think that you
can get a lot of
reference in clock drivers, such as exynos, hisilicon, ...

Same comment on PXA_FIXED_RATE table.

Regards
Haojian
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Re: [PATCH 2/4] dts: add devicetree bindings for pxa27x clocks

[Haojian Zhuang]

On Mon, Jun 30, 2014 at 2:32 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Add the clock tree description for the PXA27x based boards.

 Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
 ---
  arch/arm/boot/dts/pxa27x.dtsi| 134 
 ++-
  include/dt-bindings/clock/pxa2xx-clock.h |  45 +++
  2 files changed, 178 insertions(+), 1 deletion(-)
  create mode 100644 include/dt-bindings/clock/pxa2xx-clock.h

 diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
 index a705469..badaa71 100644
 --- a/arch/arm/boot/dts/pxa27x.dtsi
 +++ b/arch/arm/boot/dts/pxa27x.dtsi
 @@ -1,5 +1,6 @@
  /* The pxa3xx skeleton simply augments the 2xx version */
 -/include/ pxa2xx.dtsi
 +#include pxa2xx.dtsi
 +#include dt-bindings/clock/pxa2xx-clock.h

  / {
 model = Marvell PXA27x familiy SoC;
 @@ -35,4 +36,135 @@
 #pwm-cells = 1;
 };
 };
 +
 +   clocks {
 +  /*
 +   * The muxing of external clocks/internal dividers for osc* 
 clock
 +   * sources has been hidden under the carpet by now.
 +   */
 +   #address-cells = 1;
 +   #size-cells = 1;
 +   ranges;
 +
 +   osc13mhz:osc13mhz {
 +   compatible = fixed-clock;
 +#clock-cells = 0;
 +   clock-frequency = 1300;
 +   };
 +
 +   osc32_768khz:osc32_768khz {
 +   compatible = fixed-clock;
 +#clock-cells = 0;
 +   clock-frequency = 32768;
 +   };
 +
 +   pll_312mhz:pll_312mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = osc13mhz;
 +   clock-div = 1;
 +   clock-mult = 24;
 +   };
 +
 +   clk_48mhz:clk_48mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = pll_312mhz;
 +   clock-div = 13;
 +   clock-mult = 2;
 +   };
 +
 +   clk_32_842mhz:clk_32_842mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = pll_312mhz;
 +   clock-div = 19;
 +   clock-mult = 2;
 +   };
 +
 +   clk_19_5mhz:clk_19_5mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = pll_312mhz;
 +   clock-div = 32;
 +   clock-mult = 2;
 +   };
 +
 +   clk_14_857mhz:clk_14_857mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = pll_312mhz;
 +   clock-div = 42;
 +   clock-mult = 2;
 +   };
 +
 +   clk_14_682mhz:clk_14_682mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = pll_312mhz;
 +   clock-div = 51;
 +   clock-mult = 2;
 +   };
 +
 +   clk_13mhz:clk_13mhz {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = osc13mhz;
 +   clock-div = 1;
 +   clock-mult = 1;
 +   };
 +
 +   clk_dummy:clk_dummy {
 +   compatible = fixed-clock;
 +#clock-cells = 0;
 +   clock-frequency = 0;
 +   };
 +
 +   clk_ostimer:clk_ostimer {
 +   compatible = fixed-factor-clock;
 +#clock-cells = 0;
 +   clocks = osc13mhz;
 +   clock-div = 4;
 +   clock-mult = 1;
 +   };
 +
 +   pxa27x_sysclks:pxa27x_sysclks {
 +   compatible = marvell,pxa270-core-clocks;
 +   #clock-cells = 1;
 +   clocks = osc13mhz;
 +   clock-output-names = run mode, half-turbo mode,
 +   turbo mode, cpu core, system bus, 
 memory, lcd;
 +   };
 +
 +   pxa2xx_clks: pxa2xx_clks@4134 {
 +   compatible = marvell,pxa-clocks;
 +   reg = 0x4134 0x4;
 +   clocks =
 +   clk_13mhz, clk_13mhz, clk_dummy, 
 clk_13mhz,
 +   clk_13mhz, clk_14_857mhz, 
 clk_14_857mhz, clk_14_857mhz,
 + 

Re: [PATCH 0/4] Migrate PXA27x platforms to clock framework

[Haojian Zhuang]

On Tue, Jul 1, 2014 at 2:38 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Arnd Bergmann a...@arndb.de writes:

 On Sunday 29 June 2014 20:32:20 Robert Jarzmik wrote:
 As the RFC posted in [1] didn't meet an unrivaled success for
 review, I'm posting this serie for PXA27x transition to clock
 framework.

 This transition is needed :
  - to enable device-tree drivers port, as clocks are needed almost
everywhere
  - to enable the long term multi-platform kernel to support PXA

 As I had said before, this serie aims at :
  - keeping legacy platforms working (ie. without device-tree)
  - enable PXA27x to work with a device-tree kernel, and hence
open the way to drivers conversion
  - be robust enough to support pxa25x and pxa3xx later inclusion
with almost no change to clk-pxa-dt.c.

 As this serie is holding the rest of the device-tree drivers
 port, I'd like it to be reviewed, even it's an old unsexy
 platform.

 I have one basic question about this series: if pxa27x gets moved
 to used the common-clk framework but the others (pxa25x, pxa26x,
 pxa3xx, pxa93x) don't, does that imply that they become mutually
 exclusiv at compile-time?

 Unfortunately yes, they become exclusive.
 The reason being that arch/arm/mach-pxa/clock.c defines the function
 clk_enable(), which of course is also defined by the clock framework.

 If so, do you plan to first complete all of them before merging
 upstream, or do you intend to have one or more kernel releases
 that don't allow building a combined kernel for all pxa platforms?
 I intend to have first only pxa27x.
 Then in a second stage pxa27x + pxa25x + pxa3xx.

 I don't object to doing the latter, but if that is the plan, you
 need to make that very clear in the changelog and have all the
 relevant maintainers agree to that.
 OK, that would be Haojian then, I think he maintains all PXA platforms.

 Haojian, are you ok with that ? And BTW, does a combined kernel for PXA
 platforms even exists (mixing pxa3xx and pxa2xx for example) ?


It's acceptable to me that different silicons are queued in different stages.
I only request that it won't break the compiler building  bootup.

But I think that the pxa clock driver may be shared among all PXA silicons
except for the clock table. What's your opinion?

 Also (for my understanding) when you say that you plan to do
 pxa25x and pxa3xx next, does that include pxa26x and pxa93x?
 I don't have the Technical Reference Manuals for these ones so the answer is
 no. And Google wasn't a great friend at providing them.


Converting them into new clock driver may not rely on the reference manual.

 I assume it does as they are apparently minor revisions of the
 former, but it's not completely clear from your description.
 My description doesn't mention them, as I have no information about them, nor
 any hardware to test on.


We can request others to help testing in the mailing list.

Regards
Haojian
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Re: [PATCH 0/4] Migrate PXA27x platforms to clock framework

[Haojian Zhuang]

On Fri, Jul 4, 2014 at 6:14 AM, Robert Jarzmik robert.jarz...@free.fr wrote:
 Haojian Zhuang haojian.zhu...@gmail.com writes:

 Haojian, are you ok with that ? And BTW, does a combined kernel for PXA
 platforms even exists (mixing pxa3xx and pxa2xx for example) ?


 It's acceptable to me that different silicons are queued in different stages.
 I only request that it won't break the compiler building  bootup.
 OK.


 But I think that the pxa clock driver may be shared among all PXA silicons
 except for the clock table. What's your opinion?
 I don't think so because of the core clocks.
 These ones are specific to each pxa, and so their computation is :
  - pxa25x plays with CCCR and specific L, M and N2 multiplication tables
  - pxa27x plays with CCCR and specific L, M and N2 multiplication tables
  - pxa3xx plays with ASCR, MEMCLKCFG, and AC97 div

 I don't see very well how a clock table could describe that. Do you have
 something specific in mind ?


As I remember, those registers bits are encoded. So we can define a clock mux
that connected to those fixed clock dividers. Then the clock gate is
the child of
the clock mux.

In DTS file, peripheral device node could specify a clock rate. In
peripheral device
driver, it could also change the clock rate by clk_set_rate().

 Also (for my understanding) when you say that you plan to do
 pxa25x and pxa3xx next, does that include pxa26x and pxa93x?
 I don't have the Technical Reference Manuals for these ones so the answer is
 no. And Google wasn't a great friend at providing them.


 Converting them into new clock driver may not rely on the reference manual.
 Actually I went through the code and :
  - pxa26x is only a superset of pxa25x with one more clock : pxa26x-gpio
  - pxa93x is the same clock set as pxa3xx, right ?
 So if I convert pxa25x, pxa27x and pxa3xx I'll cover everything, right ?

 I assume it does as they are apparently minor revisions of the
 former, but it's not completely clear from your description.
 My description doesn't mention them, as I have no information about them, 
 nor
 any hardware to test on.


 We can request others to help testing in the mailing list.
 That's exactly what will enable pxa25x and pxa3xx. I have them converted in my
 tree, but I don't want to mix these patches in as I can't test them, and 
 testing
 brings in bigger delays.

Delay shouldn't be the block issue.

Regards
Haojian
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Re: Device-tree and Marvell vendor prefix

[Haojian Zhuang]

On Fri, Jun 20, 2014 at 3:22 AM, Robert Jarzmik robert.jarz...@free.fr wrote:

 Hi Haojian, Grant and Rob,

 I'm submitting various patches for Marvell PXA27x architecture to support
 device-tree.

 In a review from Guennadi, he made me a comment that the official prefix for
 Marvell is marvell (according to
 Documentation/devicetree/bindings/vendor-prefixes.txt).

 As a matter of fact, there are 2 prefixes used :
  - marvell : 264 uses in *.c files
  - mrvl : 64 uses in *.c files

 So which one should I use ?

 Cheers.

 --
 Robert

Please use marvell instead since it's preferred. We can't replace
mrvl by marvell roughly.
It may cause incompatible in other's tree. We can add marvell for
all mrvl entries.

Regards
Haojian
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Re: [PATCH 1/2] gpio: pl061: get gpio base from alias id

[Haojian Zhuang]

On 23 April 2014 21:21, Linus Walleij linus.wall...@linaro.org wrote:
 On Tue, Apr 22, 2014 at 3:35 AM, Haojian Zhuang
 haojian.zhu...@linaro.org wrote:

 If gpio base number isn't specified, the gpio base will be find from
 the end of gpio number. In order to keep with schematics, use alias
 to get the ID of gpio chip.

 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org

 The idea with GPIO numbers is not that these shall correspond
 to schematics or data sheets or anything like that. It's a completely
 Linux-internal number and has nothing to do with anything else.

 The same is true for IRQ numbers.

 The long term goal is to get rid of both GPIO and IRQ numbers
 and deal only with descriptors in the kernel.

Go it. But the gpio sysfs interface is using the gpio name with an
internal number. It'll make developer confusion since it's different
from datasheet
or schematics. Is there any plan to remove the confusion?

Regards
Haojian
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Re: [PATCH 1/2] gpio: pl061: get gpio base from alias id

[Haojian Zhuang]

On 24 April 2014 02:52, Rob Herring robherri...@gmail.com wrote:
 On Mon, Apr 21, 2014 at 8:35 PM, Haojian Zhuang
 haojian.zhu...@linaro.org wrote:
 If gpio base number isn't specified, the gpio base will be find from
 the end of gpio number. In order to keep with schematics, use alias
 to get the ID of gpio chip.

 NAK. This is an abuse aliases.

 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
 ---
  .../devicetree/bindings/gpio/gpio-pl061.txt| 31 
 ++

 Is something wrong with the binding doc already in pl061-gpio.txt?

Oh. I just copy my old patch to here. I didn't notice there's a new
pl061-gpio.txt. Thanks for reminder.

Regards
Haojian
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[PATCH 1/2] gpio: pl061: get gpio base from alias id

[Haojian Zhuang]

If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
to get the ID of gpio chip.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 .../devicetree/bindings/gpio/gpio-pl061.txt| 31 ++
 drivers/gpio/gpio-pl061.c  | 14 +-
 2 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-pl061.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-pl061.txt 
b/Documentation/devicetree/bindings/gpio/gpio-pl061.txt
new file mode 100644
index 000..164b5ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-pl061.txt
@@ -0,0 +1,31 @@
+PL061 GPIO controller bindings
+
+Required properties:
+- compatible:
+  - arm,pl061, arm,primecell.
+- #gpio-cells : Should be two.
+  - first cell is the gpio pin number
+  - second cell is used to specify the gpio polarity:
+  0 = active high
+  1 = active low
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupt-controller : Marks the device node as an interrupt controller.
+- #interrupt-cells : Should be two.
+  - first cell is the hw irq number
+  - second cell is used to specify the interrupt type:
+  0 = default, unspecified type
+  1 = rising edge triggered
+  2 = falling edge triggered
+  4 = high level triggered
+  8 = low level triggered
+
+Example:
+   gpio0: gpio@fc806000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xfc806000 0x1000;
+   interrupts = 0 64 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b0f4752..14f3ab5 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -236,6 +236,18 @@ static struct irq_chip pl061_irqchip = {
.irq_set_type   = pl061_irq_type,
 };
 
+/* Parse gpio base from DT */
+static int pl061_parse_gpio_base(struct device *dev)
+{
+   struct device_node *np = dev-of_node;
+   int ret, id;
+
+   id = of_alias_get_id(np, gpio);
+   if (id  0)
+   return id;
+   return (id * PL061_GPIO_NR);
+}
+
 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 {
struct device *dev = adev-dev;
@@ -255,7 +267,7 @@ static int pl061_probe(struct amba_device *adev, const 
struct amba_id *id)
return -ENODEV;
}
} else {
-   chip-gc.base = -1;
+   chip-gc.base = pl061_parse_gpio_base(dev);
irq_base = 0;
}
 
-- 
1.9.1

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[PATCH 2/2] ARM: dts: add gpio alias in hi3620 dts file

[Haojian Zhuang]

Use gpio alias to identify the index of gpio chip. Then we can keep the
same gpio number as schematics. Otherwise, gpio number is countered from
bottom to top.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/boot/dts/hi3620.dtsi | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 6836795..2aaae09 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -21,6 +21,28 @@
serial2 = uart2;
serial3 = uart3;
serial4 = uart4;
+   gpio0 = gpio0;
+   gpio1 = gpio1;
+   gpio2 = gpio2;
+   gpio3 = gpio3;
+   gpio4 = gpio4;
+   gpio5 = gpio5;
+   gpio6 = gpio6;
+   gpio7 = gpio7;
+   gpio8 = gpio8;
+   gpio9 = gpio9;
+   gpio10 = gpio10;
+   gpio11 = gpio11;
+   gpio12 = gpio12;
+   gpio13 = gpio13;
+   gpio14 = gpio14;
+   gpio15 = gpio15;
+   gpio16 = gpio16;
+   gpio17 = gpio17;
+   gpio18 = gpio18;
+   gpio19 = gpio19;
+   gpio20 = gpio20;
+   gpio21 = gpio21;
};
 
pclk: clk {
-- 
1.9.1

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Re: [PATCH 1/2] clk: hisilicon: add hi3620_mmc_clks

[Haojian Zhuang]

On 01/15/2014 04:29 PM, Mike Turquette wrote:

Quoting Haojian Zhuang (2014-01-14 21:59:40)

On 01/15/2014 11:53 AM, Mike Turquette wrote:

Quoting zhangfei (2014-01-14 17:40:25)

Dear Mike

On 01/15/2014 04:17 AM, Mike Turquette wrote:

Quoting Zhangfei Gao (2014-01-13 01:14:28)

Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Patch looks good to me with one exception. I do not have
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt in the
clk-next branch. Is there a stable branch I can pull in as a dependency?

Mach-hisi just have been uploaeded.
Have tried next-20140114, the patch can be applied successfully.
While v3.13-rc8 still can not.

Is this fine?

Can you give me a link to the branch that introduces
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt?

I guess the patch introducing it is going through arm-soc. Is this going
in for 3.14? If so then perhaps the clk tree and the arm-soc tree can
share a stable branch that introduces it.

Regards,
Mike


Some patches are merged into arm-soc, and others are in clk tree.
If sharing a stable branch between arm-soc and clk tree, it only means
that we need to revert all commits that are in arm-soc and clk tree.
I think it's too complex.

I'm suggesting reverting any patches that are applied to arm-soc. I'm
only suggesting that there might be a common branch that both the clk
and arm-soc trees can depend on to fix this problem.


How about split the patch? The patch on document should enter in arm-soc.

That is one approach. You might want to run it past the arm-soc folks
first to see if they will take in the binding definition for 3.14.

Regards,
Mike


Yes, so I already made Kevin in this loop. Let's see whether he has
any comments on it.

Regards
Haojian
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Re: [PATCH 1/2] clk: hisilicon: add hi3620_mmc_clks

[Haojian Zhuang]

On 01/15/2014 11:53 AM, Mike Turquette wrote:

Quoting zhangfei (2014-01-14 17:40:25)

Dear Mike

On 01/15/2014 04:17 AM, Mike Turquette wrote:

Quoting Zhangfei Gao (2014-01-13 01:14:28)

Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Jaehoon Chung jh80.ch...@samsung.com

Patch looks good to me with one exception. I do not have
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt in the
clk-next branch. Is there a stable branch I can pull in as a dependency?

Mach-hisi just have been uploaeded.
Have tried next-20140114, the patch can be applied successfully.
While v3.13-rc8 still can not.

Is this fine?

Can you give me a link to the branch that introduces
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt?

I guess the patch introducing it is going through arm-soc. Is this going
in for 3.14? If so then perhaps the clk tree and the arm-soc tree can
share a stable branch that introduces it.

Regards,
Mike


Some patches are merged into arm-soc, and others are in clk tree.
If sharing a stable branch between arm-soc and clk tree, it only means
that we need to revert all commits that are in arm-soc and clk tree.
I think it's too complex.

How about split the patch? The patch on document should enter in arm-soc.

Regards
Haojian
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[PATCH v12 03/08] ARM: config: enable hi3xxx in multi_v7_defconfig

[Haojian Zhuang]

From: Haojian Zhuang haojian.zhu...@linaro.org

Enable ARCH_HI3xxx in multi_v7_defconfig.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 4a5903e..7910d22 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -9,6 +9,7 @@ CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX51_DT=y
-- 
1.8.3.2

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[PATCH v12 02/08] ARM: dts: enable hi4511 with device tree

[Haojian Zhuang]

From: Haojian Zhuang haojian.zhu...@linaro.org

Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/hi3620.dtsi | 518 +
 arch/arm/boot/dts/hi4511.dts  | 648 ++
 3 files changed, 1167 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3620.dtsi
 create mode 100644 arch/arm/boot/dts/hi4511.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..a4c771f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
+dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
new file mode 100644
index 000..b9d8679
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -0,0 +1,518 @@
+/*
+ * Hisilicon Ltd. Hi3620 SoC
+ *
+ * Copyright (C) 2012-2013 Hisilicon Ltd.
+ * Copyright (C) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang haojian.zhu...@linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+   aliases {
+   serial0 = uart0;
+   serial1 = uart1;
+   serial2 = uart2;
+   serial3 = uart3;
+   serial4 = uart4;
+   };
+
+   pclk: clk {
+   compatible = fixed-clock;
+   #clock-cells = 0;
+   clock-frequency = 2600;
+   clock-output-names = apb_pclk;
+   };
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;
+
+   cpu@0 {
+   device_type = cpu;
+   compatible = arm,cortex-a9;
+   reg = 0x0;
+   next-level-cache = L2;
+   };
+   };
+
+   amba {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = arm,amba-bus;
+   interrupt-parent = gic;
+   ranges = 0 0xfc00 0x200;
+
+   L2: l2-cache {
+   compatible = arm,pl310-cache;
+   reg = 0xfc1 0x10;
+   interrupts = 0 15 4;
+   cache-unified;
+   cache-level = 2;
+   };
+
+   gic: interrupt-controller@1000 {
+   compatible = arm,cortex-a9-gic;
+   #interrupt-cells = 3;
+   #address-cells = 0;
+   interrupt-controller;
+   /* gic dist base, gic cpu base */
+   reg = 0x1000 0x1000, 0x100 0x100;
+   };
+
+   dual_timer0: dual_timer@80 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0x80 0x1000;
+   /* timer00  timer01 */
+   interrupts = 0 0 4, 0 1 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer1: dual_timer@801000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0x801000 0x1000;
+   /* timer10  timer11 */
+   interrupts = 0 2 4, 0 3 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer2: dual_timer@a01000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa01000 0x1000;
+   /* timer20  timer21 */
+   interrupts = 0 4 4, 0 5 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer3: dual_timer@a02000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa02000 0x1000;
+   /* timer30  timer31 */
+   interrupts = 0 6 4, 0 7 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer4: dual_timer@a03000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa03000 0x1000

[PATCH v12 00/08] enable hisilicon hi3xxx SoC

[Haojian Zhuang]

v12:
 1. Add CONFIG_SMP as default selection. Add GPIOLIB as default selection.
 2. Use macro definition to replace constant number in IO mapping of hi3620.c.
 3. Add more comments in platsmp.c.

v11:
 1. Add comments on iotable.
 2. Use dummy clock in DTS. Remove common clock binding in DTS file. Clock 
driver will be in another patchset.

v10:
 1. Use static IO mapping in Hi3xxx.
 2. Totally drop to support of Hi3716.
 3. Rename smp-off property to smp-offset.
 4. Remove hardcoding in hotplug driver.

v9:
 1. Clean code in DTS file according to Olof's comments.
 2. Since debug ll patch is going through Russell's tree, remove it
 from this patch set.

 v8:
 1. Drop to support CLK_GATE_SEPERATED_REG in common clock gate driver.
 Support this feature in hi3xxx clock driver.
 2. Clean unnecessary device node in DTS.
 3. Define all clocks in hi3620-clk.dtsi. And all clock nodes are defined
 in the clocks node.
 4. Fix the clock gate  clock mux for timer.
 5. Rename timer0~4 to dual_timer0~4 in DTS file. It's used to make
 name clearer.

 v7:
 1. Add hi3xxx_defconfig.
 2. Use reg property in clock node.
 3. Drop origin clock divider table.
 4. Reuse clock divider register helper.
 5. Reuse clock gate register helper.
 6. Append CLK_GATE_SEPERATED_REG flag in order to support Hisilicon
Hi3620 SoC.
 7. Rebase DEBUG_LL for Hi3xxx.
 8. Add more clock node in DTS file.

 v6:
 1. Remove hisilicon string from properties in clock driver.
 2. Replace array by pointer in clock driver. Since only sctrl parent
node exists at this time.

 v5:
 1. Remove HIWORD clk patches since they're merged into clk git tree.
 2. Set hisilicon,clk-reset property of clkgate node is optional.
 3. Update on commandline args in DTS file. Remove earlyprintk, mem, nfs.
 4. Move gpio-keys out of amba node in DTS file.

 v4:
 1. Add clk gate with HIWORD mask for Rockchip.
 2. Update comments and code of HIWORD flags for mux/divider.
 3. Append a mux without HIWORD mask in Hisilicon 3620.
 4. Fix the pinmux setting in Hi4511.

 v3:
 1. Use clk_register_mux_table().

 v2:
 1. Reuse mux  divider driver. So append CLK_MUX_HIWORD_MASK 
 CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
 2. Fix system timer running too fast because wrong divider is choosen.
 3. Remove .init_irq in DT machine descriptor.


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[PATCH v12 08/08] ARM: hi3xxx: select GPIO in Kconfig

[Haojian Zhuang]

Select GPIO in hi3xxx Kconfig.

Signed-off-by: Haojian Zhuang haojian.zhu...@gmail.com
---
 arch/arm/mach-hi3xxx/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
index 4007ecf..018ad67 100644
--- a/arch/arm/mach-hi3xxx/Kconfig
+++ b/arch/arm/mach-hi3xxx/Kconfig
@@ -3,6 +3,7 @@ config ARCH_HI3xxx
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
+   select ARCH_WANT_OPTIONAL_GPIOLIB
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
-- 
1.8.3.2

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[PATCH v12 06/08] ARM: hi3xxx: add hotplug support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable hotplug support on hi3xxx platform

How to test:
cat proc/interrupts
echo 0  /sys/devices/system/cpu/cpuX/online
cat proc/interrupts
echo 1  /sys/devices/system/cpu/cpuX/online

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/mach-hi3xxx/Makefile  |   1 +
 arch/arm/mach-hi3xxx/core.h|   4 +
 arch/arm/mach-hi3xxx/hotplug.c | 200 +
 arch/arm/mach-hi3xxx/platsmp.c |   5 ++
 4 files changed, 210 insertions(+)
 create mode 100644 arch/arm/mach-hi3xxx/hotplug.c

diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index 7a869a7..c9919e8 100644
--- a/arch/arm/mach-hi3xxx/Makefile
+++ b/arch/arm/mach-hi3xxx/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  += hi3xxx.o
 obj-$(CONFIG_SMP)  += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
diff --git a/arch/arm/mach-hi3xxx/core.h b/arch/arm/mach-hi3xxx/core.h
index 226f020..af23ec2 100644
--- a/arch/arm/mach-hi3xxx/core.h
+++ b/arch/arm/mach-hi3xxx/core.h
@@ -8,4 +8,8 @@ extern int hi3xxx_get_cpu_jump(int cpu);
 extern void secondary_startup(void);
 extern struct smp_operations hi3xxx_smp_ops;
 
+extern void hi3xxx_cpu_die(unsigned int cpu);
+extern int hi3xxx_cpu_kill(unsigned int cpu);
+extern void hi3xxx_set_cpu(int cpu, bool enable);
+
 #endif
diff --git a/arch/arm/mach-hi3xxx/hotplug.c b/arch/arm/mach-hi3xxx/hotplug.c
new file mode 100644
index 000..5dc949e
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/hotplug.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2013 Linaro Ltd.
+ * Copyright (c) 2013 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include linux/cpu.h
+#include linux/delay.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include asm/cacheflush.h
+#include asm/smp_plat.h
+#include core.h
+
+/* Sysctrl registers in Hi3620 SoC */
+#define SCISOEN0xc0
+#define SCISODIS   0xc4
+#define SCPERPWREN 0xd0
+#define SCPERPWRDIS0xd4
+#define SCCPUCOREEN0xf4
+#define SCCPUCOREDIS   0xf8
+#define SCPERCTRL0 0x200
+#define SCCPURSTEN 0x410
+#define SCCPURSTDIS0x414
+
+/*
+ * bit definition in SCISOEN/SCPERPWREN/...
+ *
+ * CPU2_ISO_CTRL   (1  5)
+ * CPU3_ISO_CTRL   (1  6)
+ * ...
+ */
+#define CPU2_ISO_CTRL  (1  5)
+
+/*
+ * bit definition in SCPERCTRL0
+ *
+ * CPU0_WFI_MASK_CFG   (1  28)
+ * CPU1_WFI_MASK_CFG   (1  29)
+ * ...
+ */
+#define CPU0_WFI_MASK_CFG  (1  28)
+
+/*
+ * bit definition in SCCPURSTEN/...
+ *
+ * CPU0_SRST_REQ_EN(1  0)
+ * CPU1_SRST_REQ_EN(1  1)
+ * ...
+ */
+#define CPU0_HPM_SRST_REQ_EN   (1  22)
+#define CPU0_DBG_SRST_REQ_EN   (1  12)
+#define CPU0_NEON_SRST_REQ_EN  (1  4)
+#define CPU0_SRST_REQ_EN   (1  0)
+
+enum {
+   HI3620_CTRL,
+   ERROR_CTRL,
+};
+
+static void __iomem *ctrl_base = NULL;
+static int id;
+
+static void set_cpu_hi3620(int cpu, bool enable)
+{
+   u32 val = 0;
+
+   if (enable) {
+   /* MTCMOS set */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCPERPWREN);
+   udelay(100);
+
+   /* Enable core */
+   writel_relaxed(0x01  cpu, ctrl_base + SCCPUCOREEN);
+
+   /* unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   /* reset */
+   val |= CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTEN);
+
+   /* ISO disable */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCISODIS);
+   udelay(1);
+
+   /* WFI Mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val = ~(CPU0_WFI_MASK_CFG  cpu);
+   writel_relaxed(val, ctrl_base + SCPERCTRL0);
+
+   /* Unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   } else {
+   /* wfi mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val |= (CPU0_WFI_MASK_CFG  cpu

[PATCH v12 07/08] ARM: dts: enable clock binding on Hi3620

[Haojian Zhuang]

Enable clock binding for Hi3620 common clock driver.

Signed-off-by: Haojian Zhuang haojian.zhu...@gmail.com
---
 arch/arm/boot/dts/hi3620.dtsi | 79 ---
 arch/arm/boot/dts/hi4511.dts  |  3 +-
 2 files changed, 46 insertions(+), 36 deletions(-)

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index e311937..ab1116d 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -11,7 +11,8 @@
  * publishhed by the Free Software Foundation.
  */
 
-/include/ skeleton.dtsi
+#include skeleton.dtsi
+#include dt-bindings/clock/hi3620-clock.h
 
 / {
aliases {
@@ -63,6 +64,7 @@
};
 
amba {
+
#address-cells = 1;
#size-cells = 1;
compatible = arm,amba-bus;
@@ -88,13 +90,20 @@
 
sysctrl: system-controller@802000 {
compatible = hisilicon,sysctrl;
-   reg = 0x802000 0x1000;
#address-cells = 1;
-   #size-cells = 0;
+   #size-cells = 1;
+   ranges = 0 0x802000 0x1000;
+   reg = 0x802000 0x1000;
 
smp-offset = 0x31c;
resume-offset = 0x308;
reboot-offset = 0x4;
+
+   clock: clock@0 {
+   compatible = hisilicon,hi3620-clock;
+   reg = 0 0x1;
+   #clock-cells = 1;
+   };
};
 
dual_timer0: dual_timer@80 {
@@ -102,7 +111,7 @@
reg = 0x80 0x1000;
/* timer00  timer01 */
interrupts = 0 0 4, 0 1 4;
-   clocks = pclk;
+   clocks = clock HI3620_TIMER0_MUX, clock 
HI3620_TIMER1_MUX;
clock-names = apb_pclk;
status = disabled;
};
@@ -112,7 +121,7 @@
reg = 0x801000 0x1000;
/* timer10  timer11 */
interrupts = 0 2 4, 0 3 4;
-   clocks = pclk;
+   clocks = clock HI3620_TIMER2_MUX, clock 
HI3620_TIMER3_MUX;
clock-names = apb_pclk;
status = disabled;
};
@@ -122,7 +131,7 @@
reg = 0xa01000 0x1000;
/* timer20  timer21 */
interrupts = 0 4 4, 0 5 4;
-   clocks = pclk;
+   clocks = clock HI3620_TIMER4_MUX, clock 
HI3620_TIMER5_MUX;
clock-names = apb_pclk;
status = disabled;
};
@@ -132,7 +141,7 @@
reg = 0xa02000 0x1000;
/* timer30  timer31 */
interrupts = 0 6 4, 0 7 4;
-   clocks = pclk;
+   clocks = clock HI3620_TIMER6_MUX, clock 
HI3620_TIMER7_MUX;
clock-names = apb_pclk;
status = disabled;
};
@@ -142,7 +151,7 @@
reg = 0xa03000 0x1000;
/* timer40  timer41 */
interrupts = 0 96 4, 0 97 4;
-   clocks = pclk;
+   clocks = clock HI3620_TIMER8_MUX, clock 
HI3620_TIMER9_MUX;
clock-names = apb_pclk;
status = disabled;
};
@@ -157,7 +166,7 @@
compatible = arm,pl011, arm,primecell;
reg = 0xb0 0x1000;
interrupts = 0 20 4;
-   clocks = pclk;
+   clocks = clock HI3620_UARTCLK0;
clock-names = apb_pclk;
status = disabled;
};
@@ -166,7 +175,7 @@
compatible = arm,pl011, arm,primecell;
reg = 0xb01000 0x1000;
interrupts = 0 21 4;
-   clocks = pclk;
+   clocks = clock HI3620_UARTCLK1;
clock-names = apb_pclk;
status = disabled;
};
@@ -175,7 +184,7 @@
compatible = arm,pl011, arm,primecell;
reg = 0xb02000 0x1000;
interrupts = 0 22 4;
-   clocks = pclk;
+   clocks = clock HI3620_UARTCLK2;
clock-names = apb_pclk;
status = disabled;
};
@@ -184,7 +193,7 @@
compatible = arm,pl011, arm,primecell;
reg = 0xb03000 0x1000;
interrupts = 0 23 4;
-   clocks

[PATCH v12 05/08] ARM: hi3xxx: add smp support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable SMP support on hi3xxx platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Tested-by: Li Xin li@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 .../bindings/arm/hisilicon/hisilicon.txt   | 26 +++
 arch/arm/boot/dts/hi3620.dtsi  | 38 ++
 arch/arm/mach-hi3xxx/Kconfig   |  4 ++
 arch/arm/mach-hi3xxx/Makefile  |  1 +
 arch/arm/mach-hi3xxx/core.h| 11 +++
 arch/arm/mach-hi3xxx/hi3xxx.c  | 41 ++-
 arch/arm/mach-hi3xxx/platsmp.c | 84 ++
 7 files changed, 203 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-hi3xxx/core.h
 create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 21a7336..8c7a465 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -4,3 +4,29 @@ Hisilicon Platforms Device Tree Bindings
 Hi4511 Board
 Required root node properties:
- compatible = hisilicon,hi3620-hi4511;
+
+Hisilicon system controller
+
+Required properties:
+- compatible : hisilicon,sysctrl
+- reg : Register address and size
+
+Optional properties:
+- smp-offset : offset in sysctrl for notifying slave cpu booting
+   cpu 1, reg;
+   cpu 2, reg + 0x4;
+   cpu 3, reg + 0x8;
+   If reg value is not zero, cpun exit wfi and go
+- resume-offset : offset in sysctrl for notifying cpu0 when resume
+- reboot-offset : offset in sysctrl for system reboot
+
+Example:
+
+   /* for Hi3620 */
+   sysctrl: system-controller@fc802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0xfc802000 0x1000;
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index b9d8679..e311937 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -39,6 +39,27 @@
reg = 0x0;
next-level-cache = L2;
};
+
+   cpu@1 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 1;
+   next-level-cache = L2;
+   };
+
+   cpu@2 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 2;
+   next-level-cache = L2;
+   };
+
+   cpu@3 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 3;
+   next-level-cache = L2;
+   };
};
 
amba {
@@ -65,6 +86,17 @@
reg = 0x1000 0x1000, 0x100 0x100;
};
 
+   sysctrl: system-controller@802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0x802000 0x1000;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
+
dual_timer0: dual_timer@80 {
compatible = arm,sp804, arm,primecell;
reg = 0x80 0x1000;
@@ -115,6 +147,12 @@
status = disabled;
};
 
+   timer5: timer@600 {
+   compatible = arm,cortex-a9-twd-timer;
+   reg = 0x600 0x20;
+   interrupts = 1 13 0xf01;
+   };
+
uart0: uart@b0 {
compatible = arm,pl011, arm,primecell;
reg = 0xb0 0x1000;
diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
index 68bd26c..4007ecf 100644
--- a/arch/arm/mach-hi3xxx/Kconfig
+++ b/arch/arm/mach-hi3xxx/Kconfig
@@ -6,7 +6,11 @@ config ARCH_HI3xxx
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
+   select HAVE_ARM_SCU
+   select HAVE_ARM_TWD
+   select HAVE_SMP
select PINCTRL
select PINCTRL_SINGLE
+   select SMP
help
  Support for Hisilicon Hi36xx/Hi37xx processor family
diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index d68ebb3..7a869a7 100644
--- a/arch/arm/mach-hi3xxx/Makefile
+++ b/arch/arm/mach-hi3xxx/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-y  += hi3xxx.o
+obj-$(CONFIG_SMP

Re: [PATCH RESEND v5 1/2] PWM: PXA: add device tree support to PWM driver

[Haojian Zhuang]

On 12/04/2013 05:03 PM, Thierry Reding wrote:

On Wed, Dec 04, 2013 at 09:12:51AM +0800, Haojian Zhuang wrote:

On 12/04/2013 02:45 AM, Mike Dunn wrote:

On 12/03/2013 02:17 AM, Thierry Reding wrote:

On Sat, Sep 21, 2013 at 12:19:33PM -0700, Mike Dunn wrote:

This patch adds device tree support to the PXA's PWM driver.  Nothing
needs to be extracted from the device tree node by the PWM device.
Client devices need only specify the period; the per-chip index is
implicitly zero because one device node must be present for each PWM
output in use.  This approach is more convenient due to the wide
variability in the number of PWM channels present across the various PXA
variants, and is made possible by the fact that the register sets for
each PWM channel are segregated from each other.  An of_xlate() method
is added to parse this single-cell node.  The existing ID table is
reused for the match table data.

Tested on a Palm Treo 680 (both platform data and DT cases).

Signed-off-by: Mike Dunn miked...@newsguy.com
---
  Documentation/devicetree/bindings/pwm/pxa-pwm.txt | 30 +
  drivers/pwm/pwm-pxa.c | 52 ++-
  2 files changed, 81 insertions(+), 1 deletion(-)
  create mode 100644 Documentation/devicetree/bindings/pwm/pxa-pwm.txt

Hi Mike,

It looks like this fell through the cracks. Is this patch still the
latest one you have? Should it still be applied?

Thierry


Hi Thierry,

Funny I should hear from you about this today I just turned my attention
back to this today and noticed that it never made it into your for-next branch.
  Yes, it is the latest.  If the patch still applies cleanly, please feel free.
Otherwise, I'd be glad to rework it against something more recent.

Also, we never got any ACKs for patch 2/2, which just adds the nodes to
arch/arm/boot/dts/pxa27x.dtsi
Any advice on whom to nudge?

Thanks much!
Mike


It's fine to me.

Acked-by: Haojian Zhuang haojian.zhu...@linaro.org

I think it's customary to take DTS file updates through the architecture
trees, so I think it'd be better if you took patch 2/2. There aren't any
dependencies between both patches either.

Thierry

OK. Let me handle this.

Regards
Haojian
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Re: [PATCH RESEND v5 1/2] PWM: PXA: add device tree support to PWM driver

[Haojian Zhuang]

On 12/04/2013 02:45 AM, Mike Dunn wrote:

On 12/03/2013 02:17 AM, Thierry Reding wrote:

On Sat, Sep 21, 2013 at 12:19:33PM -0700, Mike Dunn wrote:

This patch adds device tree support to the PXA's PWM driver.  Nothing
needs to be extracted from the device tree node by the PWM device.
Client devices need only specify the period; the per-chip index is
implicitly zero because one device node must be present for each PWM
output in use.  This approach is more convenient due to the wide
variability in the number of PWM channels present across the various PXA
variants, and is made possible by the fact that the register sets for
each PWM channel are segregated from each other.  An of_xlate() method
is added to parse this single-cell node.  The existing ID table is
reused for the match table data.

Tested on a Palm Treo 680 (both platform data and DT cases).

Signed-off-by: Mike Dunn miked...@newsguy.com
---
  Documentation/devicetree/bindings/pwm/pxa-pwm.txt | 30 +
  drivers/pwm/pwm-pxa.c | 52 ++-
  2 files changed, 81 insertions(+), 1 deletion(-)
  create mode 100644 Documentation/devicetree/bindings/pwm/pxa-pwm.txt

Hi Mike,

It looks like this fell through the cracks. Is this patch still the
latest one you have? Should it still be applied?

Thierry


Hi Thierry,

Funny I should hear from you about this today I just turned my attention
back to this today and noticed that it never made it into your for-next branch.
  Yes, it is the latest.  If the patch still applies cleanly, please feel free.
Otherwise, I'd be glad to rework it against something more recent.

Also, we never got any ACKs for patch 2/2, which just adds the nodes to
arch/arm/boot/dts/pxa27x.dtsi
Any advice on whom to nudge?

Thanks much!
Mike



It's fine to me.

Acked-by: Haojian Zhuang haojian.zhu...@linaro.org

Regards
Haojian
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Re: [PATCH v11 5/6] ARM: hi3xxx: add smp support

[Haojian Zhuang]

On 25 November 2013 12:00, Olof Johansson o...@lixom.net wrote:
 On Tue, Nov 12, 2013 at 12:49 AM, Haojian Zhuang
 haojian.zhu...@linaro.org wrote:
 On 7 November 2013 18:30, Dinh Nguyen dinh.li...@gmail.com wrote:

 On 11/7/13 2:41 AM, Haojian Zhuang wrote:
 From: Zhangfei Gao zhangfei@linaro.org

 Enable SMP support on hi3xxx platform

 Signed-off-by: Zhangfei Gao zhangfei@linaro.org
 Tested-by: Zhang Mingjun zhang.ming...@linaro.org
 Tested-by: Li Xin li@linaro.org
 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
 ---
  .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
  arch/arm/boot/dts/hi3620.dtsi  | 38 ++
  arch/arm/mach-hi3xxx/Kconfig   |  3 +
  arch/arm/mach-hi3xxx/Makefile  |  1 +
  arch/arm/mach-hi3xxx/core.h| 11 +++
  arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
  arch/arm/mach-hi3xxx/platsmp.c | 84 
 ++
  7 files changed, 197 insertions(+), 4 deletions(-)
  create mode 100644 arch/arm/mach-hi3xxx/core.h
  create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
 b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 index 3be60c8..8c7a465 100644
 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 @@ -1,10 +1,32 @@
  Hisilicon Platforms Device Tree Bindings
  

 -Hi3716 Development Board
 -Required root node properties:
 - - compatible = hisilicon,hi3716-dkb;
 -
  Hi4511 Board
  Required root node properties:
   - compatible = hisilicon,hi3620-hi4511;
 +
 +Hisilicon system controller
 +
 +Required properties:
 +- compatible : hisilicon,sysctrl
 +- reg : Register address and size
 +
 +Optional properties:
 +- smp-offset : offset in sysctrl for notifying slave cpu booting
 + cpu 1, reg;
 + cpu 2, reg + 0x4;
 + cpu 3, reg + 0x8;
 + If reg value is not zero, cpun exit wfi and go
 +- resume-offset : offset in sysctrl for notifying cpu0 when resume
 +- reboot-offset : offset in sysctrl for system reboot
 +
 +Example:
 +
 + /* for Hi3620 */
 + sysctrl: system-controller@fc802000 {
 + compatible = hisilicon,sysctrl;
 + reg = 0xfc802000 0x1000;
 + smp-offset = 0x31c;
 + resume-offset = 0x308;
 + reboot-offset = 0x4;
 + };
 diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
 index b9d8679..e311937 100644
 --- a/arch/arm/boot/dts/hi3620.dtsi
 +++ b/arch/arm/boot/dts/hi3620.dtsi
 @@ -39,6 +39,27 @@
   reg = 0x0;
   next-level-cache = L2;
   };
 +
 + cpu@1 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 1;
 + next-level-cache = L2;
 + };
 +
 + cpu@2 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 2;
 + next-level-cache = L2;
 + };
 +
 + cpu@3 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 3;
 + next-level-cache = L2;
 + };
   };

   amba {
 @@ -65,6 +86,17 @@
   reg = 0x1000 0x1000, 0x100 0x100;
   };

 + sysctrl: system-controller@802000 {
 + compatible = hisilicon,sysctrl;
 + reg = 0x802000 0x1000;
 + #address-cells = 1;
 + #size-cells = 0;
 +
 + smp-offset = 0x31c;
 + resume-offset = 0x308;
 + reboot-offset = 0x4;
 + };
 +
   dual_timer0: dual_timer@80 {
   compatible = arm,sp804, arm,primecell;
   reg = 0x80 0x1000;
 @@ -115,6 +147,12 @@
   status = disabled;
   };

 + timer5: timer@600 {
 + compatible = arm,cortex-a9-twd-timer;
 + reg = 0x600 0x20;
 + interrupts = 1 13 0xf01;
 + };
 Do you have a clocks node for this timer?

 As I mentioned in the 0th patch, clock binding are totally removed
 in this patch. And clock driver will be append in another patch set.

 +
   uart0: uart@b0 {
   compatible = arm,pl011, arm,primecell;
   reg = 0xb0 0x1000;
 diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
 index 68bd26c..d0f298a 100644
 --- a/arch/arm/mach-hi3xxx/Kconfig
 +++ b/arch/arm/mach-hi3xxx

Re: [PATCH v11 1/6] ARM: hi3xxx: add board support with device tree

[Haojian Zhuang]

On 7 November 2013 17:50, Dinh Nguyen dinh.li...@gmail.com wrote:

 On 11/7/13 2:41 AM, Haojian Zhuang wrote:
 Add board support with device tree for Hisilicon Hi3620 SoC platform.

 Changelog:
 v11:
 1. Add comments for iotable.

 v10:
 1. Add .map_io()  debug_ll_io_init() back. Since debug_ll_io_init() is
 only called if .map_io() isn't assigned. Use .map_io() to setup static
 IO mapping that is used in clock driver.

 v3:
 1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init()
 is called by default.
 2. Remove .init_machine() in DT machine descriptor. Since
 of_platform_populate() is called by default in DT mode.

 v2:
 1. Remove .init_irq() in DT machine descriptor. Since irqchip_init()
 is called by default in DT mode.

 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
 ---
  .../bindings/arm/hisilicon/hisilicon.txt   | 10 
  arch/arm/Kconfig   |  2 +
  arch/arm/Makefile  |  1 +
  arch/arm/mach-hi3xxx/Kconfig   | 12 +
  arch/arm/mach-hi3xxx/Makefile  |  5 ++
  arch/arm/mach-hi3xxx/hi3xxx.c  | 60 
 ++
  6 files changed, 90 insertions(+)
  create mode 100644 
 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
  create mode 100644 arch/arm/mach-hi3xxx/Kconfig
  create mode 100644 arch/arm/mach-hi3xxx/Makefile
  create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c

 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
 b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 new file mode 100644
 index 000..3be60c8
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 @@ -0,0 +1,10 @@
 +Hisilicon Platforms Device Tree Bindings
 +
 +
 +Hi3716 Development Board
 +Required root node properties:
 + - compatible = hisilicon,hi3716-dkb;
 +
 +Hi4511 Board
 +Required root node properties:
 + - compatible = hisilicon,hi3620-hi4511;
 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
 index 3f7714d..0118443 100644
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
 @@ -946,6 +946,8 @@ source arch/arm/mach-footbridge/Kconfig

  source arch/arm/mach-gemini/Kconfig

 +source arch/arm/mach-hi3xxx/Kconfig
 +
  source arch/arm/mach-highbank/Kconfig

  source arch/arm/mach-integrator/Kconfig
 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
 index a37a50f..23fb0b0 100644
 --- a/arch/arm/Makefile
 +++ b/arch/arm/Makefile
 @@ -155,6 +155,7 @@ machine-$(CONFIG_ARCH_EBSA110)+= ebsa110
  machine-$(CONFIG_ARCH_EP93XX)+= ep93xx
  machine-$(CONFIG_ARCH_EXYNOS)+= exynos
  machine-$(CONFIG_ARCH_GEMINI)+= gemini
 +machine-$(CONFIG_ARCH_HI3xxx)+= hi3xxx
  machine-$(CONFIG_ARCH_HIGHBANK)  += highbank
  machine-$(CONFIG_ARCH_INTEGRATOR)+= integrator
  machine-$(CONFIG_ARCH_IOP13XX)   += iop13xx
 diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
 new file mode 100644
 index 000..68bd26c
 --- /dev/null
 +++ b/arch/arm/mach-hi3xxx/Kconfig
 @@ -0,0 +1,12 @@
 +config ARCH_HI3xxx
 + bool Hisilicon Hi36xx/Hi37xx family if ARCH_MULTI_V7
 + select ARM_AMBA
 + select ARM_GIC
 + select ARM_TIMER_SP804
 + select CACHE_L2X0
 + select CLKSRC_OF
 I think you need COMMON_CLK here.

Why? COMMON_CLK will be selected if ARCH_MULTIPLATFORM is enabled. Why
do I need to choose it again?

 + select GENERIC_CLOCKEVENTS
 + select PINCTRL
 + select PINCTRL_SINGLE
 + help
 +   Support for Hisilicon Hi36xx/Hi37xx processor family
 diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
 new file mode 100644
 index 000..d68ebb3
 --- /dev/null
 +++ b/arch/arm/mach-hi3xxx/Makefile
 @@ -0,0 +1,5 @@
 +#
 +# Makefile for Hisilicon Hi36xx/Hi37xx processors line
 +#
 +
 +obj-y+= hi3xxx.o
 diff --git a/arch/arm/mach-hi3xxx/hi3xxx.c b/arch/arm/mach-hi3xxx/hi3xxx.c
 new file mode 100644
 index 000..925af13
 --- /dev/null
 +++ b/arch/arm/mach-hi3xxx/hi3xxx.c
 @@ -0,0 +1,60 @@
 +/*
 + * (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled 
 machine
 + *
 + * Copyright (c) 2012-2013 Hisilicon Ltd.
 + * Copyright (c) 2012-2013 Linaro Ltd.
 + *
 + * Author: Haojian Zhuang haojian.zhu...@linaro.org
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 +*/
 +
 +#include linux/clk-provider.h
 +#include linux/clocksource.h
 +#include linux/irqchip.h
 +#include linux/of_platform.h
 +
 +#include asm/mach/arch.h
 +#include asm/mach/map.h
 +
 +/*
 + * This table is only for optimization. Since ioremap() could always share
 + * the same mapping if it's defined as static IO mapping.
 + *
 + * Without this table

Re: [PATCH v11 5/6] ARM: hi3xxx: add smp support

[Haojian Zhuang]

On 7 November 2013 18:30, Dinh Nguyen dinh.li...@gmail.com wrote:

 On 11/7/13 2:41 AM, Haojian Zhuang wrote:
 From: Zhangfei Gao zhangfei@linaro.org

 Enable SMP support on hi3xxx platform

 Signed-off-by: Zhangfei Gao zhangfei@linaro.org
 Tested-by: Zhang Mingjun zhang.ming...@linaro.org
 Tested-by: Li Xin li@linaro.org
 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
 ---
  .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
  arch/arm/boot/dts/hi3620.dtsi  | 38 ++
  arch/arm/mach-hi3xxx/Kconfig   |  3 +
  arch/arm/mach-hi3xxx/Makefile  |  1 +
  arch/arm/mach-hi3xxx/core.h| 11 +++
  arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
  arch/arm/mach-hi3xxx/platsmp.c | 84 
 ++
  7 files changed, 197 insertions(+), 4 deletions(-)
  create mode 100644 arch/arm/mach-hi3xxx/core.h
  create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
 b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 index 3be60c8..8c7a465 100644
 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 @@ -1,10 +1,32 @@
  Hisilicon Platforms Device Tree Bindings
  

 -Hi3716 Development Board
 -Required root node properties:
 - - compatible = hisilicon,hi3716-dkb;
 -
  Hi4511 Board
  Required root node properties:
   - compatible = hisilicon,hi3620-hi4511;
 +
 +Hisilicon system controller
 +
 +Required properties:
 +- compatible : hisilicon,sysctrl
 +- reg : Register address and size
 +
 +Optional properties:
 +- smp-offset : offset in sysctrl for notifying slave cpu booting
 + cpu 1, reg;
 + cpu 2, reg + 0x4;
 + cpu 3, reg + 0x8;
 + If reg value is not zero, cpun exit wfi and go
 +- resume-offset : offset in sysctrl for notifying cpu0 when resume
 +- reboot-offset : offset in sysctrl for system reboot
 +
 +Example:
 +
 + /* for Hi3620 */
 + sysctrl: system-controller@fc802000 {
 + compatible = hisilicon,sysctrl;
 + reg = 0xfc802000 0x1000;
 + smp-offset = 0x31c;
 + resume-offset = 0x308;
 + reboot-offset = 0x4;
 + };
 diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
 index b9d8679..e311937 100644
 --- a/arch/arm/boot/dts/hi3620.dtsi
 +++ b/arch/arm/boot/dts/hi3620.dtsi
 @@ -39,6 +39,27 @@
   reg = 0x0;
   next-level-cache = L2;
   };
 +
 + cpu@1 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 1;
 + next-level-cache = L2;
 + };
 +
 + cpu@2 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 2;
 + next-level-cache = L2;
 + };
 +
 + cpu@3 {
 + compatible = arm,cortex-a9;
 + device_type = cpu;
 + reg = 3;
 + next-level-cache = L2;
 + };
   };

   amba {
 @@ -65,6 +86,17 @@
   reg = 0x1000 0x1000, 0x100 0x100;
   };

 + sysctrl: system-controller@802000 {
 + compatible = hisilicon,sysctrl;
 + reg = 0x802000 0x1000;
 + #address-cells = 1;
 + #size-cells = 0;
 +
 + smp-offset = 0x31c;
 + resume-offset = 0x308;
 + reboot-offset = 0x4;
 + };
 +
   dual_timer0: dual_timer@80 {
   compatible = arm,sp804, arm,primecell;
   reg = 0x80 0x1000;
 @@ -115,6 +147,12 @@
   status = disabled;
   };

 + timer5: timer@600 {
 + compatible = arm,cortex-a9-twd-timer;
 + reg = 0x600 0x20;
 + interrupts = 1 13 0xf01;
 + };
 Do you have a clocks node for this timer?

As I mentioned in the 0th patch, clock binding are totally removed
in this patch. And clock driver will be append in another patch set.

 +
   uart0: uart@b0 {
   compatible = arm,pl011, arm,primecell;
   reg = 0xb0 0x1000;
 diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
 index 68bd26c..d0f298a 100644
 --- a/arch/arm/mach-hi3xxx/Kconfig
 +++ b/arch/arm/mach-hi3xxx/Kconfig
 @@ -6,6 +6,9 @@ config ARCH_HI3xxx
   select CACHE_L2X0
   select CLKSRC_OF
   select GENERIC_CLOCKEVENTS
 + select HAVE_ARM_SCU

Re: [PATCH v11 5/6] ARM: hi3xxx: add smp support

[Haojian Zhuang]

On 11/13/2013 07:00 AM, Kevin Hilman wrote:

Haojian Zhuang haojian.zhu...@linaro.org writes:


On 7 November 2013 18:30, Dinh Nguyen dinh.li...@gmail.com wrote:

On 11/7/13 2:41 AM, Haojian Zhuang wrote:

From: Zhangfei Gao zhangfei@linaro.org

Enable SMP support on hi3xxx platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Tested-by: Li Xin li@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
  .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
  arch/arm/boot/dts/hi3620.dtsi  | 38 ++
  arch/arm/mach-hi3xxx/Kconfig   |  3 +
  arch/arm/mach-hi3xxx/Makefile  |  1 +
  arch/arm/mach-hi3xxx/core.h| 11 +++
  arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
  arch/arm/mach-hi3xxx/platsmp.c | 84 ++
  7 files changed, 197 insertions(+), 4 deletions(-)
  create mode 100644 arch/arm/mach-hi3xxx/core.h
  create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3be60c8..8c7a465 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,10 +1,32 @@
  Hisilicon Platforms Device Tree Bindings
  

-Hi3716 Development Board
-Required root node properties:
- - compatible = hisilicon,hi3716-dkb;
-
  Hi4511 Board
  Required root node properties:
   - compatible = hisilicon,hi3620-hi4511;
+
+Hisilicon system controller
+
+Required properties:
+- compatible : hisilicon,sysctrl
+- reg : Register address and size
+
+Optional properties:
+- smp-offset : offset in sysctrl for notifying slave cpu booting
+ cpu 1, reg;
+ cpu 2, reg + 0x4;
+ cpu 3, reg + 0x8;
+ If reg value is not zero, cpun exit wfi and go
+- resume-offset : offset in sysctrl for notifying cpu0 when resume
+- reboot-offset : offset in sysctrl for system reboot
+
+Example:
+
+ /* for Hi3620 */
+ sysctrl: system-controller@fc802000 {
+ compatible = hisilicon,sysctrl;
+ reg = 0xfc802000 0x1000;
+ smp-offset = 0x31c;
+ resume-offset = 0x308;
+ reboot-offset = 0x4;
+ };
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index b9d8679..e311937 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -39,6 +39,27 @@
   reg = 0x0;
   next-level-cache = L2;
   };
+
+ cpu@1 {
+ compatible = arm,cortex-a9;
+ device_type = cpu;
+ reg = 1;
+ next-level-cache = L2;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a9;
+ device_type = cpu;
+ reg = 2;
+ next-level-cache = L2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a9;
+ device_type = cpu;
+ reg = 3;
+ next-level-cache = L2;
+ };
   };

   amba {
@@ -65,6 +86,17 @@
   reg = 0x1000 0x1000, 0x100 0x100;
   };

+ sysctrl: system-controller@802000 {
+ compatible = hisilicon,sysctrl;
+ reg = 0x802000 0x1000;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ smp-offset = 0x31c;
+ resume-offset = 0x308;
+ reboot-offset = 0x4;
+ };
+
   dual_timer0: dual_timer@80 {
   compatible = arm,sp804, arm,primecell;
   reg = 0x80 0x1000;
@@ -115,6 +147,12 @@
   status = disabled;
   };

+ timer5: timer@600 {
+ compatible = arm,cortex-a9-twd-timer;
+ reg = 0x600 0x20;
+ interrupts = 1 13 0xf01;
+ };

Do you have a clocks node for this timer?

As I mentioned in the 0th patch, clock binding are totally removed
in this patch. And clock driver will be append in another patch set.

Still, won't this timer still need a dummy fixed-rate clock until the
real clocks are in place?  Otherwise it seems twd_get_clock() is going
to fail.

Kevin

sp804 is working. twd_get_clock() fails but it could calculate rate.
I tested on my platform. With this dummy fixed-rate clock, it could
work.

Regards
Haojian
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Re: [PATCH v11 5/6] ARM: hi3xxx: add smp support

[Haojian Zhuang]

On 11/13/2013 06:53 AM, Kevin Hilman wrote:

Haojian Zhuang haojian.zhu...@linaro.org writes:


From: Zhangfei Gao zhangfei@linaro.org

Enable SMP support on hi3xxx platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Tested-by: Li Xin li@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
  .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
  arch/arm/boot/dts/hi3620.dtsi  | 38 ++
  arch/arm/mach-hi3xxx/Kconfig   |  3 +
  arch/arm/mach-hi3xxx/Makefile  |  1 +
  arch/arm/mach-hi3xxx/core.h| 11 +++
  arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
  arch/arm/mach-hi3xxx/platsmp.c | 84 ++
  7 files changed, 197 insertions(+), 4 deletions(-)
  create mode 100644 arch/arm/mach-hi3xxx/core.h
  create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3be60c8..8c7a465 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,10 +1,32 @@
  Hisilicon Platforms Device Tree Bindings
  
  
-Hi3716 Development Board

-Required root node properties:
-   - compatible = hisilicon,hi3716-dkb;
-

This was added in patch 1/6, then removed here.  If it's not
needed/used, just drop it from patch 1 please.

Kevin

OK
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[PATCH v11 0/6] enable hi3xxx SoC

[Haojian Zhuang]

v11:
 1. Add comments on iotable.
 2. Use dummy clock in DTS. Remove common clock binding in DTS file. Clock 
driver will be in another patchset.

v10:
 1. Use static IO mapping in Hi3xxx.
 2. Totally drop to support of Hi3716.
 3. Rename smp-off property to smp-offset.
 4. Remove hardcoding in hotplug driver.

v9:
 1. Clean code in DTS file according to Olof's comments.
 2. Since debug ll patch is going through Russell's tree, remove it
 from this patch set.

 v8:
 1. Drop to support CLK_GATE_SEPERATED_REG in common clock gate driver.
 Support this feature in hi3xxx clock driver.
 2. Clean unnecessary device node in DTS.
 3. Define all clocks in hi3620-clk.dtsi. And all clock nodes are defined
 in the clocks node.
 4. Fix the clock gate  clock mux for timer.
 5. Rename timer0~4 to dual_timer0~4 in DTS file. It's used to make
 name clearer.

 v7:
 1. Add hi3xxx_defconfig.
 2. Use reg property in clock node.
 3. Drop origin clock divider table.
 4. Reuse clock divider register helper.
 5. Reuse clock gate register helper.
 6. Append CLK_GATE_SEPERATED_REG flag in order to support Hisilicon
Hi3620 SoC.
 7. Rebase DEBUG_LL for Hi3xxx.
 8. Add more clock node in DTS file.

 v6:
 1. Remove hisilicon string from properties in clock driver.
 2. Replace array by pointer in clock driver. Since only sctrl parent
node exists at this time.

 v5:
 1. Remove HIWORD clk patches since they're merged into clk git tree.
 2. Set hisilicon,clk-reset property of clkgate node is optional.
 3. Update on commandline args in DTS file. Remove earlyprintk, mem, nfs.
 4. Move gpio-keys out of amba node in DTS file.

 v4:
 1. Add clk gate with HIWORD mask for Rockchip.
 2. Update comments and code of HIWORD flags for mux/divider.
 3. Append a mux without HIWORD mask in Hisilicon 3620.
 4. Fix the pinmux setting in Hi4511.

 v3:
 1. Use clk_register_mux_table().

 v2:
 1. Reuse mux  divider driver. So append CLK_MUX_HIWORD_MASK 
 CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
 2. Fix system timer running too fast because wrong divider is choosen.
 3. Remove .init_irq in DT machine descriptor.


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[PATCH v11 4/6] ARM: config: add defconfig for Hi3xxx

[Haojian Zhuang]

Add default config for arch-hi3xxx. It's used for Hisilicon Hi3xxx SoC.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/configs/hi3xxx_defconfig | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/configs/hi3xxx_defconfig

diff --git a/arch/arm/configs/hi3xxx_defconfig 
b/arch/arm/configs/hi3xxx_defconfig
new file mode 100644
index 000..f186bdf
--- /dev/null
+++ b/arch/arm/configs/hi3xxx_defconfig
@@ -0,0 +1,56 @@
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_LZMA=y
+CONFIG_ARCH_HI3xxx=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_DRM=y
+CONFIG_FB_SIMPLE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_PL330_DMA=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOCKUP_DETECTOR=y
-- 
1.8.3.2

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[PATCH v11 5/6] ARM: hi3xxx: add smp support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable SMP support on hi3xxx platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Tested-by: Li Xin li@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
 arch/arm/boot/dts/hi3620.dtsi  | 38 ++
 arch/arm/mach-hi3xxx/Kconfig   |  3 +
 arch/arm/mach-hi3xxx/Makefile  |  1 +
 arch/arm/mach-hi3xxx/core.h| 11 +++
 arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
 arch/arm/mach-hi3xxx/platsmp.c | 84 ++
 7 files changed, 197 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-hi3xxx/core.h
 create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3be60c8..8c7a465 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,10 +1,32 @@
 Hisilicon Platforms Device Tree Bindings
 
 
-Hi3716 Development Board
-Required root node properties:
-   - compatible = hisilicon,hi3716-dkb;
-
 Hi4511 Board
 Required root node properties:
- compatible = hisilicon,hi3620-hi4511;
+
+Hisilicon system controller
+
+Required properties:
+- compatible : hisilicon,sysctrl
+- reg : Register address and size
+
+Optional properties:
+- smp-offset : offset in sysctrl for notifying slave cpu booting
+   cpu 1, reg;
+   cpu 2, reg + 0x4;
+   cpu 3, reg + 0x8;
+   If reg value is not zero, cpun exit wfi and go
+- resume-offset : offset in sysctrl for notifying cpu0 when resume
+- reboot-offset : offset in sysctrl for system reboot
+
+Example:
+
+   /* for Hi3620 */
+   sysctrl: system-controller@fc802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0xfc802000 0x1000;
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index b9d8679..e311937 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -39,6 +39,27 @@
reg = 0x0;
next-level-cache = L2;
};
+
+   cpu@1 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 1;
+   next-level-cache = L2;
+   };
+
+   cpu@2 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 2;
+   next-level-cache = L2;
+   };
+
+   cpu@3 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 3;
+   next-level-cache = L2;
+   };
};
 
amba {
@@ -65,6 +86,17 @@
reg = 0x1000 0x1000, 0x100 0x100;
};
 
+   sysctrl: system-controller@802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0x802000 0x1000;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
+
dual_timer0: dual_timer@80 {
compatible = arm,sp804, arm,primecell;
reg = 0x80 0x1000;
@@ -115,6 +147,12 @@
status = disabled;
};
 
+   timer5: timer@600 {
+   compatible = arm,cortex-a9-twd-timer;
+   reg = 0x600 0x20;
+   interrupts = 1 13 0xf01;
+   };
+
uart0: uart@b0 {
compatible = arm,pl011, arm,primecell;
reg = 0xb0 0x1000;
diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
index 68bd26c..d0f298a 100644
--- a/arch/arm/mach-hi3xxx/Kconfig
+++ b/arch/arm/mach-hi3xxx/Kconfig
@@ -6,6 +6,9 @@ config ARCH_HI3xxx
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
+   select HAVE_ARM_SCU
+   select HAVE_ARM_TWD
+   select HAVE_SMP
select PINCTRL
select PINCTRL_SINGLE
help
diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index d68ebb3..7a869a7 100644
--- a/arch/arm/mach-hi3xxx/Makefile
+++ b/arch/arm/mach-hi3xxx

[PATCH v11 3/6] ARM: config: enable hi3xxx in multi_v7_defconfig

[Haojian Zhuang]

Enable ARCH_HI3xxx in multi_v7_defconfig.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 6e572c6..6855397 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX51_DT=y
-- 
1.8.3.2

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[PATCH v11 1/6] ARM: hi3xxx: add board support with device tree

[Haojian Zhuang]

Add board support with device tree for Hisilicon Hi3620 SoC platform.

Changelog:
v11:
1. Add comments for iotable.

v10:
1. Add .map_io()  debug_ll_io_init() back. Since debug_ll_io_init() is
only called if .map_io() isn't assigned. Use .map_io() to setup static
IO mapping that is used in clock driver.

v3:
1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init()
is called by default.
2. Remove .init_machine() in DT machine descriptor. Since
of_platform_populate() is called by default in DT mode.

v2:
1. Remove .init_irq() in DT machine descriptor. Since irqchip_init()
is called by default in DT mode.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 .../bindings/arm/hisilicon/hisilicon.txt   | 10 
 arch/arm/Kconfig   |  2 +
 arch/arm/Makefile  |  1 +
 arch/arm/mach-hi3xxx/Kconfig   | 12 +
 arch/arm/mach-hi3xxx/Makefile  |  5 ++
 arch/arm/mach-hi3xxx/hi3xxx.c  | 60 ++
 6 files changed, 90 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 create mode 100644 arch/arm/mach-hi3xxx/Kconfig
 create mode 100644 arch/arm/mach-hi3xxx/Makefile
 create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
new file mode 100644
index 000..3be60c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -0,0 +1,10 @@
+Hisilicon Platforms Device Tree Bindings
+
+
+Hi3716 Development Board
+Required root node properties:
+   - compatible = hisilicon,hi3716-dkb;
+
+Hi4511 Board
+Required root node properties:
+   - compatible = hisilicon,hi3620-hi4511;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f7714d..0118443 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -946,6 +946,8 @@ source arch/arm/mach-footbridge/Kconfig
 
 source arch/arm/mach-gemini/Kconfig
 
+source arch/arm/mach-hi3xxx/Kconfig
+
 source arch/arm/mach-highbank/Kconfig
 
 source arch/arm/mach-integrator/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a37a50f..23fb0b0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -155,6 +155,7 @@ machine-$(CONFIG_ARCH_EBSA110)  += ebsa110
 machine-$(CONFIG_ARCH_EP93XX)  += ep93xx
 machine-$(CONFIG_ARCH_EXYNOS)  += exynos
 machine-$(CONFIG_ARCH_GEMINI)  += gemini
+machine-$(CONFIG_ARCH_HI3xxx)  += hi3xxx
 machine-$(CONFIG_ARCH_HIGHBANK)+= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)  += integrator
 machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
new file mode 100644
index 000..68bd26c
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/Kconfig
@@ -0,0 +1,12 @@
+config ARCH_HI3xxx
+   bool Hisilicon Hi36xx/Hi37xx family if ARCH_MULTI_V7
+   select ARM_AMBA
+   select ARM_GIC
+   select ARM_TIMER_SP804
+   select CACHE_L2X0
+   select CLKSRC_OF
+   select GENERIC_CLOCKEVENTS
+   select PINCTRL
+   select PINCTRL_SINGLE
+   help
+ Support for Hisilicon Hi36xx/Hi37xx processor family
diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
new file mode 100644
index 000..d68ebb3
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Hisilicon Hi36xx/Hi37xx processors line
+#
+
+obj-y  += hi3xxx.o
diff --git a/arch/arm/mach-hi3xxx/hi3xxx.c b/arch/arm/mach-hi3xxx/hi3xxx.c
new file mode 100644
index 000..925af13
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/hi3xxx.c
@@ -0,0 +1,60 @@
+/*
+ * (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled machine
+ *
+ * Copyright (c) 2012-2013 Hisilicon Ltd.
+ * Copyright (c) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang haojian.zhu...@linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/clk-provider.h
+#include linux/clocksource.h
+#include linux/irqchip.h
+#include linux/of_platform.h
+
+#include asm/mach/arch.h
+#include asm/mach/map.h
+
+/*
+ * This table is only for optimization. Since ioremap() could always share
+ * the same mapping if it's defined as static IO mapping.
+ *
+ * Without this table, system could also work. The cost is some virtual address
+ * spaces wasted since ioremap() may be called multi times for the same
+ * IO space.
+ */
+static struct map_desc hi3620_io_desc[] __initdata = {
+   {
+   .pfn= __phys_to_pfn(0xfc802000),
+   .virtual= 0xfe802000,
+   .length = 0x1000,
+   .type

[PATCH v11 6/6] ARM: hi3xxx: add hotplug support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable hotplug support on hi3xxx platform

How to test:
cat proc/interrupts
echo 0  /sys/devices/system/cpu/cpuX/online
cat proc/interrupts
echo 1  /sys/devices/system/cpu/cpuX/online

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/mach-hi3xxx/Makefile  |   1 +
 arch/arm/mach-hi3xxx/core.h|   4 +
 arch/arm/mach-hi3xxx/hotplug.c | 200 +
 arch/arm/mach-hi3xxx/platsmp.c |   5 ++
 4 files changed, 210 insertions(+)
 create mode 100644 arch/arm/mach-hi3xxx/hotplug.c

diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index 7a869a7..c9919e8 100644
--- a/arch/arm/mach-hi3xxx/Makefile
+++ b/arch/arm/mach-hi3xxx/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  += hi3xxx.o
 obj-$(CONFIG_SMP)  += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
diff --git a/arch/arm/mach-hi3xxx/core.h b/arch/arm/mach-hi3xxx/core.h
index 226f020..af23ec2 100644
--- a/arch/arm/mach-hi3xxx/core.h
+++ b/arch/arm/mach-hi3xxx/core.h
@@ -8,4 +8,8 @@ extern int hi3xxx_get_cpu_jump(int cpu);
 extern void secondary_startup(void);
 extern struct smp_operations hi3xxx_smp_ops;
 
+extern void hi3xxx_cpu_die(unsigned int cpu);
+extern int hi3xxx_cpu_kill(unsigned int cpu);
+extern void hi3xxx_set_cpu(int cpu, bool enable);
+
 #endif
diff --git a/arch/arm/mach-hi3xxx/hotplug.c b/arch/arm/mach-hi3xxx/hotplug.c
new file mode 100644
index 000..5dc949e
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/hotplug.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2013 Linaro Ltd.
+ * Copyright (c) 2013 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include linux/cpu.h
+#include linux/delay.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include asm/cacheflush.h
+#include asm/smp_plat.h
+#include core.h
+
+/* Sysctrl registers in Hi3620 SoC */
+#define SCISOEN0xc0
+#define SCISODIS   0xc4
+#define SCPERPWREN 0xd0
+#define SCPERPWRDIS0xd4
+#define SCCPUCOREEN0xf4
+#define SCCPUCOREDIS   0xf8
+#define SCPERCTRL0 0x200
+#define SCCPURSTEN 0x410
+#define SCCPURSTDIS0x414
+
+/*
+ * bit definition in SCISOEN/SCPERPWREN/...
+ *
+ * CPU2_ISO_CTRL   (1  5)
+ * CPU3_ISO_CTRL   (1  6)
+ * ...
+ */
+#define CPU2_ISO_CTRL  (1  5)
+
+/*
+ * bit definition in SCPERCTRL0
+ *
+ * CPU0_WFI_MASK_CFG   (1  28)
+ * CPU1_WFI_MASK_CFG   (1  29)
+ * ...
+ */
+#define CPU0_WFI_MASK_CFG  (1  28)
+
+/*
+ * bit definition in SCCPURSTEN/...
+ *
+ * CPU0_SRST_REQ_EN(1  0)
+ * CPU1_SRST_REQ_EN(1  1)
+ * ...
+ */
+#define CPU0_HPM_SRST_REQ_EN   (1  22)
+#define CPU0_DBG_SRST_REQ_EN   (1  12)
+#define CPU0_NEON_SRST_REQ_EN  (1  4)
+#define CPU0_SRST_REQ_EN   (1  0)
+
+enum {
+   HI3620_CTRL,
+   ERROR_CTRL,
+};
+
+static void __iomem *ctrl_base = NULL;
+static int id;
+
+static void set_cpu_hi3620(int cpu, bool enable)
+{
+   u32 val = 0;
+
+   if (enable) {
+   /* MTCMOS set */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCPERPWREN);
+   udelay(100);
+
+   /* Enable core */
+   writel_relaxed(0x01  cpu, ctrl_base + SCCPUCOREEN);
+
+   /* unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   /* reset */
+   val |= CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTEN);
+
+   /* ISO disable */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCISODIS);
+   udelay(1);
+
+   /* WFI Mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val = ~(CPU0_WFI_MASK_CFG  cpu);
+   writel_relaxed(val, ctrl_base + SCPERCTRL0);
+
+   /* Unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   } else {
+   /* wfi mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val |= (CPU0_WFI_MASK_CFG  cpu

[PATCH v11 2/6] ARM: dts: enable hi4511 with device tree

[Haojian Zhuang]

Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/hi3620.dtsi | 518 +
 arch/arm/boot/dts/hi4511.dts  | 648 ++
 3 files changed, 1167 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3620.dtsi
 create mode 100644 arch/arm/boot/dts/hi4511.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cc0f1fb..b4ec185 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
+dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
new file mode 100644
index 000..b9d8679
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -0,0 +1,518 @@
+/*
+ * Hisilicon Ltd. Hi3620 SoC
+ *
+ * Copyright (C) 2012-2013 Hisilicon Ltd.
+ * Copyright (C) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang haojian.zhu...@linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+   aliases {
+   serial0 = uart0;
+   serial1 = uart1;
+   serial2 = uart2;
+   serial3 = uart3;
+   serial4 = uart4;
+   };
+
+   pclk: clk {
+   compatible = fixed-clock;
+   #clock-cells = 0;
+   clock-frequency = 2600;
+   clock-output-names = apb_pclk;
+   };
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;
+
+   cpu@0 {
+   device_type = cpu;
+   compatible = arm,cortex-a9;
+   reg = 0x0;
+   next-level-cache = L2;
+   };
+   };
+
+   amba {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = arm,amba-bus;
+   interrupt-parent = gic;
+   ranges = 0 0xfc00 0x200;
+
+   L2: l2-cache {
+   compatible = arm,pl310-cache;
+   reg = 0xfc1 0x10;
+   interrupts = 0 15 4;
+   cache-unified;
+   cache-level = 2;
+   };
+
+   gic: interrupt-controller@1000 {
+   compatible = arm,cortex-a9-gic;
+   #interrupt-cells = 3;
+   #address-cells = 0;
+   interrupt-controller;
+   /* gic dist base, gic cpu base */
+   reg = 0x1000 0x1000, 0x100 0x100;
+   };
+
+   dual_timer0: dual_timer@80 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0x80 0x1000;
+   /* timer00  timer01 */
+   interrupts = 0 0 4, 0 1 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer1: dual_timer@801000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0x801000 0x1000;
+   /* timer10  timer11 */
+   interrupts = 0 2 4, 0 3 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer2: dual_timer@a01000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa01000 0x1000;
+   /* timer20  timer21 */
+   interrupts = 0 4 4, 0 5 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer3: dual_timer@a02000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa02000 0x1000;
+   /* timer30  timer31 */
+   interrupts = 0 6 4, 0 7 4;
+   clocks = pclk;
+   clock-names = apb_pclk;
+   status = disabled;
+   };
+
+   dual_timer4: dual_timer@a03000 {
+   compatible = arm,sp804, arm,primecell;
+   reg = 0xa03000 0x1000;
+   /* timer40  timer41

[PATCH v10 0/7] enable hi3xxx SoC

[Haojian Zhuang]

v10:
 1. Use static IO mapping in Hi3xxx.
 2. Totally drop to support of Hi3716.
 3. Rename smp-off property to smp-offset.
 4. Remove hardcoding in hotplug driver.

v9:
 1. Clean code in DTS file according to Olof's comments.
 2. Since debug ll patch is going through Russell's tree, remove it
 from this patch set.

 v8:
 1. Drop to support CLK_GATE_SEPERATED_REG in common clock gate driver.
 Support this feature in hi3xxx clock driver.
 2. Clean unnecessary device node in DTS.
 3. Define all clocks in hi3620-clk.dtsi. And all clock nodes are defined
 in the clocks node.
 4. Fix the clock gate  clock mux for timer.
 5. Rename timer0~4 to dual_timer0~4 in DTS file. It's used to make
 name clearer.

 v7:
 1. Add hi3xxx_defconfig.
 2. Use reg property in clock node.
 3. Drop origin clock divider table.
 4. Reuse clock divider register helper.
 5. Reuse clock gate register helper.
 6. Append CLK_GATE_SEPERATED_REG flag in order to support Hisilicon
Hi3620 SoC.
 7. Rebase DEBUG_LL for Hi3xxx.
 8. Add more clock node in DTS file.

 v6:
 1. Remove hisilicon string from properties in clock driver.
 2. Replace array by pointer in clock driver. Since only sctrl parent
node exists at this time.

 v5:
 1. Remove HIWORD clk patches since they're merged into clk git tree.
 2. Set hisilicon,clk-reset property of clkgate node is optional.
 3. Update on commandline args in DTS file. Remove earlyprintk, mem, nfs.
 4. Move gpio-keys out of amba node in DTS file.

 v4:
 1. Add clk gate with HIWORD mask for Rockchip.
 2. Update comments and code of HIWORD flags for mux/divider.
 3. Append a mux without HIWORD mask in Hisilicon 3620.
 4. Fix the pinmux setting in Hi4511.

 v3:
 1. Use clk_register_mux_table().

 v2:
 1. Reuse mux  divider driver. So append CLK_MUX_HIWORD_MASK 
 CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
 2. Fix system timer running too fast because wrong divider is choosen.
 3. Remove .init_irq in DT machine descriptor.

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[PATCH v10 6/7] ARM: hi3xxx: add smp support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable SMP support on hi3xxx platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Tested-by: Li Xin li@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 .../bindings/arm/hisilicon/hisilicon.txt   | 30 ++--
 arch/arm/boot/dts/hi3620.dtsi  | 38 ++
 arch/arm/mach-hi3xxx/Kconfig   |  3 +
 arch/arm/mach-hi3xxx/Makefile  |  1 +
 arch/arm/mach-hi3xxx/core.h| 11 +++
 arch/arm/mach-hi3xxx/hi3xxx.c  | 34 +
 arch/arm/mach-hi3xxx/platsmp.c | 84 ++
 7 files changed, 197 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-hi3xxx/core.h
 create mode 100644 arch/arm/mach-hi3xxx/platsmp.c

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3be60c8..8c7a465 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,10 +1,32 @@
 Hisilicon Platforms Device Tree Bindings
 
 
-Hi3716 Development Board
-Required root node properties:
-   - compatible = hisilicon,hi3716-dkb;
-
 Hi4511 Board
 Required root node properties:
- compatible = hisilicon,hi3620-hi4511;
+
+Hisilicon system controller
+
+Required properties:
+- compatible : hisilicon,sysctrl
+- reg : Register address and size
+
+Optional properties:
+- smp-offset : offset in sysctrl for notifying slave cpu booting
+   cpu 1, reg;
+   cpu 2, reg + 0x4;
+   cpu 3, reg + 0x8;
+   If reg value is not zero, cpun exit wfi and go
+- resume-offset : offset in sysctrl for notifying cpu0 when resume
+- reboot-offset : offset in sysctrl for system reboot
+
+Example:
+
+   /* for Hi3620 */
+   sysctrl: system-controller@fc802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0xfc802000 0x1000;
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index e05c65c..69640ea 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -34,6 +34,27 @@
reg = 0x0;
next-level-cache = L2;
};
+
+   cpu@1 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 1;
+   next-level-cache = L2;
+   };
+
+   cpu@2 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 2;
+   next-level-cache = L2;
+   };
+
+   cpu@3 {
+   compatible = arm,cortex-a9;
+   device_type = cpu;
+   reg = 3;
+   next-level-cache = L2;
+   };
};
 
amba {
@@ -60,6 +81,17 @@
reg = 0xfc001000 0x1000, 0xfc000100 0x100;
};
 
+   sysctrl: system-controller@fc802000 {
+   compatible = hisilicon,sysctrl;
+   reg = 0xfc802000 0x1000;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   smp-offset = 0x31c;
+   resume-offset = 0x308;
+   reboot-offset = 0x4;
+   };
+
dual_timer0: dual_timer@fc80 {
compatible = arm,sp804, arm,primecell;
reg = 0xfc80 0x1000;
@@ -110,6 +142,12 @@
status = disabled;
};
 
+   timer5: timer@fc000600 {
+   compatible = arm,cortex-a9-twd-timer;
+   reg = 0xfc000600 0x20;
+   interrupts = 1 13 0xf01;
+   };
+
uart0: uart@fcb0 {
compatible = arm,pl011, arm,primecell;
reg = 0xfcb0 0x1000;
diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig
index 68bd26c..d0f298a 100644
--- a/arch/arm/mach-hi3xxx/Kconfig
+++ b/arch/arm/mach-hi3xxx/Kconfig
@@ -6,6 +6,9 @@ config ARCH_HI3xxx
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
+   select HAVE_ARM_SCU
+   select HAVE_ARM_TWD
+   select HAVE_SMP
select PINCTRL
select PINCTRL_SINGLE
help
diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index d68ebb3..7a869a7 100644
--- a/arch/arm/mach-hi3xxx

[PATCH v10 7/7] ARM: hi3xxx: add hotplug support

[Haojian Zhuang]

From: Zhangfei Gao zhangfei@linaro.org

Enable hotplug support on hi3xxx platform

How to test:
cat proc/interrupts
echo 0  /sys/devices/system/cpu/cpuX/online
cat proc/interrupts
echo 1  /sys/devices/system/cpu/cpuX/online

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Zhang Mingjun zhang.ming...@linaro.org
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/mach-hi3xxx/Makefile  |   1 +
 arch/arm/mach-hi3xxx/core.h|   4 +
 arch/arm/mach-hi3xxx/hotplug.c | 200 +
 arch/arm/mach-hi3xxx/platsmp.c |   5 ++
 4 files changed, 210 insertions(+)
 create mode 100644 arch/arm/mach-hi3xxx/hotplug.c

diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile
index 7a869a7..c9919e8 100644
--- a/arch/arm/mach-hi3xxx/Makefile
+++ b/arch/arm/mach-hi3xxx/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  += hi3xxx.o
 obj-$(CONFIG_SMP)  += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
diff --git a/arch/arm/mach-hi3xxx/core.h b/arch/arm/mach-hi3xxx/core.h
index 226f020..af23ec2 100644
--- a/arch/arm/mach-hi3xxx/core.h
+++ b/arch/arm/mach-hi3xxx/core.h
@@ -8,4 +8,8 @@ extern int hi3xxx_get_cpu_jump(int cpu);
 extern void secondary_startup(void);
 extern struct smp_operations hi3xxx_smp_ops;
 
+extern void hi3xxx_cpu_die(unsigned int cpu);
+extern int hi3xxx_cpu_kill(unsigned int cpu);
+extern void hi3xxx_set_cpu(int cpu, bool enable);
+
 #endif
diff --git a/arch/arm/mach-hi3xxx/hotplug.c b/arch/arm/mach-hi3xxx/hotplug.c
new file mode 100644
index 000..5dc949e
--- /dev/null
+++ b/arch/arm/mach-hi3xxx/hotplug.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2013 Linaro Ltd.
+ * Copyright (c) 2013 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include linux/cpu.h
+#include linux/delay.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include asm/cacheflush.h
+#include asm/smp_plat.h
+#include core.h
+
+/* Sysctrl registers in Hi3620 SoC */
+#define SCISOEN0xc0
+#define SCISODIS   0xc4
+#define SCPERPWREN 0xd0
+#define SCPERPWRDIS0xd4
+#define SCCPUCOREEN0xf4
+#define SCCPUCOREDIS   0xf8
+#define SCPERCTRL0 0x200
+#define SCCPURSTEN 0x410
+#define SCCPURSTDIS0x414
+
+/*
+ * bit definition in SCISOEN/SCPERPWREN/...
+ *
+ * CPU2_ISO_CTRL   (1  5)
+ * CPU3_ISO_CTRL   (1  6)
+ * ...
+ */
+#define CPU2_ISO_CTRL  (1  5)
+
+/*
+ * bit definition in SCPERCTRL0
+ *
+ * CPU0_WFI_MASK_CFG   (1  28)
+ * CPU1_WFI_MASK_CFG   (1  29)
+ * ...
+ */
+#define CPU0_WFI_MASK_CFG  (1  28)
+
+/*
+ * bit definition in SCCPURSTEN/...
+ *
+ * CPU0_SRST_REQ_EN(1  0)
+ * CPU1_SRST_REQ_EN(1  1)
+ * ...
+ */
+#define CPU0_HPM_SRST_REQ_EN   (1  22)
+#define CPU0_DBG_SRST_REQ_EN   (1  12)
+#define CPU0_NEON_SRST_REQ_EN  (1  4)
+#define CPU0_SRST_REQ_EN   (1  0)
+
+enum {
+   HI3620_CTRL,
+   ERROR_CTRL,
+};
+
+static void __iomem *ctrl_base = NULL;
+static int id;
+
+static void set_cpu_hi3620(int cpu, bool enable)
+{
+   u32 val = 0;
+
+   if (enable) {
+   /* MTCMOS set */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCPERPWREN);
+   udelay(100);
+
+   /* Enable core */
+   writel_relaxed(0x01  cpu, ctrl_base + SCCPUCOREEN);
+
+   /* unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   /* reset */
+   val |= CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTEN);
+
+   /* ISO disable */
+   if ((cpu == 2) || (cpu == 3))
+   writel_relaxed(CPU2_ISO_CTRL  (cpu - 2),
+  ctrl_base + SCISODIS);
+   udelay(1);
+
+   /* WFI Mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val = ~(CPU0_WFI_MASK_CFG  cpu);
+   writel_relaxed(val, ctrl_base + SCPERCTRL0);
+
+   /* Unreset */
+   val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+   | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
+   writel_relaxed(val  cpu, ctrl_base + SCCPURSTDIS);
+   } else {
+   /* wfi mask */
+   val = readl_relaxed(ctrl_base + SCPERCTRL0);
+   val |= (CPU0_WFI_MASK_CFG  cpu

[PATCH v10 4/7] ARM: config: enable hi3xxx in multi_v7_defconfig

[Haojian Zhuang]

Enable ARCH_HI3xxx in multi_v7_defconfig.

Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 6e572c6..6855397 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX51_DT=y
-- 
1.8.1.2

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Re: [PATCH v10 2/7] ARM: hi3xxx: add board support with device tree

[Haojian Zhuang]

On 15 October 2013 21:00, Arnd Bergmann a...@arndb.de wrote:
 On Tuesday 15 October 2013, Haojian Zhuang wrote:

 Add board support with device tree for Hisilicon Hi3620 SoC platform.

 Changelog:
 v10:
 1. Add .map_io()  debug_ll_io_init() back. Since debug_ll_io_init() is
 only called if .map_io() isn't assigned. Use .map_io() to setup static
 IO mapping that is used in clock driver.


 This seems like a step in the wrong direction. Why would you want to use
 a static I/O mapping in the clock driver?

 Arnd

Because Stephen  Kevin asked me to use unit address in DTS file. They
also require me to use reg property to present real hardware address
in DTS file.

Regards
Haojian
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Re: [PATCH v10 2/7] ARM: hi3xxx: add board support with device tree

[Haojian Zhuang]

On 16 October 2013 09:08, Haojian Zhuang haojian.zhu...@linaro.org wrote:
 On 16 October 2013 02:06, Arnd Bergmann a...@arndb.de wrote:
 On Tuesday 15 October 2013, Haojian Zhuang wrote:
 On 15 October 2013 21:00, Arnd Bergmann a...@arndb.de wrote:
  On Tuesday 15 October 2013, Haojian Zhuang wrote:
 
  Add board support with device tree for Hisilicon Hi3620 SoC platform.
 
  Changelog:
  v10:
  1. Add .map_io()  debug_ll_io_init() back. Since debug_ll_io_init() is
  only called if .map_io() isn't assigned. Use .map_io() to setup static
  IO mapping that is used in clock driver.
 
 
  This seems like a step in the wrong direction. Why would you want to use
  a static I/O mapping in the clock driver?
 

 Because Stephen  Kevin asked me to use unit address in DTS file. They
 also require me to use reg property to present real hardware address
 in DTS file.

 Ah, so it's just an optimization, not required to make the clock driver
 work, I misread that. Can you add a comment near the hi3620_io_desc
 definition and verify that it still works without it?

 Yes, it can work without the IO table. The IO table could save a lot
 of virtual address space for IO mapping.

 I would also recommend to extend that static mapping to the entire
 0xfc80-0xfcbf range, or whatever you can use to get the most
 I/O devices with a small number of TLB entries.

 Arnd

 OK. I'll extend the static mapping to the entire range.

 Regards
 Haojian

Oh, no. I shouldn't extend the static mapping table to the entire range.

Most of the registers only need to map once in the probe() function
of the driver. Whether it's using static mapping or dynamic mapping,
there's no difference.

 The sysctrl register bank is used in both clock  platform
driver. Each clock node contains reg property, it needs to be parsed
by of_iomap(). Hotplug  SMP platform driver needs to parse sysctrl
register bank also. If I don't choose the static IO mapping for sysctrl
register bank, I have to define some global variable to store the
virtual address mapping. Or I have to cost lots of redundant virtual
address space for the same IO mapping.

So I'll only keep the static IO mapping for sysctrl.

Regards
Haojian
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Re: [PATCH v10 3/7] ARM: dts: enable hi4511 with device tree

[Haojian Zhuang]

On 16 October 2013 02:18, Arnd Bergmann a...@arndb.de wrote:
 On Tuesday 15 October 2013, Haojian Zhuang wrote:
 Enable Hisilicon Hi4511 development platform with device tree support.

 Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org

 Based on my other mail, some more comments here:

 +/ {
 + clocks {
 + #address-cells = 1;
 + #size-cells = 1;
 + ranges;

 Since all clocks are in the fc802000 page, I would prefer using a non-empty
 ranges to map the clocks into their own address space, like

 ranges = 0 0xfc802000 0x1000;


OK.

 + timer4_mux: timer4_mux@fc802018 {
 + compatible = hisilicon,clk-mux;
 + #clock-cells = 0;
 + clocks = osc32k timerclk45;
 + clock-output-names = timer4_mux;
 + reg = 0xfc802018 0x4;
 + clkmux-mask = 0x3;
 + clkmux-table = 0 0x1;
 + };

 which would turn this into

 timer4_mux: timer4_mux@18 {
 ...
 reg = 0x18 0x4;
 ...
 };

 The code would not be impacted by this.

 On a related note, I find it strange that you have multiple devices with the
 same register. Normally, we try to have device node names be generic,
 e.g. 'clock@18' rather than 'timer4_mux@18', but that won't work if the
 register is the same for all of them. Maybe some DT expert can comment
 on this.

Because multiple clock nodes (clock mux/clock gate/clock divider) are
sharing the same register. I think that it's common on ARM SoC. At
least, I can find this in both Hisilicon  Marvell PXA/MMP SoC.

If I force to merge multiple clock nodes into the same device node,
it'll become mess. Different clock nodes have different properties.
The property won't work any more if they are merged into the same
device node.

 +
 + amba {
 + #address-cells = 1;
 + #size-cells = 1;
 + compatible = arm,amba-bus;
 + interrupt-parent = gic;
 + ranges;
 +
 + L2: l2-cache {
 + compatible = arm,pl310-cache;
 + reg = 0xfc1 0x10;
 + interrupts = 0 15 4;
 + cache-unified;
 + cache-level = 2;
 + };

 For this node, we could use the same trick with the non-empty ranges, since
 all amba devices seem to be in the 0xfc00 range.

OK.

 If you do that, it probably makes sense to move the clock controller under 
 here
 as well.
Could I keep them into hi3620-clk.dtsi? Since both hi3620.dtsi 
hi3620-clk.dtsi are not small, merge them together only make people
reading hard.


 Arnd

Best Regards
Haojian
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