Re: [RFC/PATCH] pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindings

[Ivan T. Ivanov]

> On Nov 18, 2015, at 3:00 AM, Stephen Boyd <sb...@codeaurora.org> wrote:
> 
> The drivers don't really need to know which PMIC they're for, so
> make a generic binding for them. This alleviates us from updating
> the drivers every time a new PMIC comes out. It's still
> recommended that we update the binding with new PMIC models and
> always specify the specific model for the MPPs and gpios before
> the generic compatible string in devicetree, but this at least
> cuts down on adding more and more compatible strings to the
> drivers until we actually need them.
> 
> Cc: <devicetree@vger.kernel.org>
> Cc: "Ivan T. Ivanov" <iiva...@mm-sol.com>
> Cc: Bjorn Andersson <bjorn.anders...@sonymobile.com>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>

Thanks.

Acked-by: Ivan T. Ivanov <iivanov...@gmail.com>
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[PATCH v2 4/6] tty: serial: msm: Add TX DMA support

[Ivan T. Ivanov]

Add transmit DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 312 +++--
 drivers/tty/serial/msm_serial.h|   3 +
 3 files changed, 294 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a2114c217376..a600023d9ec1 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,9 @@ Required properties:
 Optional properties:
 - dmas: Should contain dma specifiers for transmit and receive channels
 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator  for Client Rate Control Interface to be
+   used with TX DMA channel. Required when using DMA for transmission
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index e33966280606..2f395f5d78d0 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -20,6 +20,8 @@
 #endif

 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -39,6 +41,10 @@

 #include "msm_serial.h"

+#define UARTDM_BURST_SIZE  16   /* in bytes */
+#define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
+#define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+
 enum {
UARTDM_1P1 = 1,
UARTDM_1P2,
@@ -46,6 +52,17 @@ enum {
UARTDM_1P4,
 };

+struct msm_dma {
+   struct dma_chan *chan;
+   enum dma_data_direction dir;
+   dma_addr_t  phys;
+   unsigned char   *virt;
+   dma_cookie_tcookie;
+   u32 enable_bit;
+   unsigned intcount;
+   struct dma_async_tx_descriptor  *desc;
+};
+
 struct msm_port {
struct uart_portuart;
charname[16];
@@ -55,8 +72,93 @@ struct msm_port {
int is_uartdm;
unsigned intold_snap_state;
boolbreak_detected;
+   struct msm_dma  tx_dma;
 };

+static void msm_handle_tx(struct uart_port *port);
+
+void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
+{
+   struct device *dev = port->dev;
+   unsigned int mapped;
+   u32 val;
+
+   mapped = dma->count;
+   dma->count = 0;
+
+   dmaengine_terminate_all(dma->chan);
+
+   /*
+* DMA Stall happens if enqueue and flush command happens concurrently.
+* For example before changing the baud rate/protocol configuration and
+* sending flush command to ADM, disable the channel of UARTDM.
+* Note: should not reset the receiver here immediately as it is not
+* suggested to do disable/reset or reset/disable at the same time.
+*/
+   val = msm_read(port, UARTDM_DMEN);
+   val &= ~dma->enable_bit;
+   msm_write(port, val, UARTDM_DMEN);
+
+   if (mapped)
+   dma_unmap_single(dev, dma->phys, mapped, dma->dir);
+}
+
+static void msm_release_dma(struct msm_port *msm_port)
+{
+   struct msm_dma *dma;
+
+   dma = _port->tx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   }
+
+   memset(dma, 0, sizeof(*dma));
+}
+
+static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->tx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "tx");
+   if (IS_ERR(dma->chan))
+   goto no_tx;
+
+   of_property_read_u32(dev->of_node, "qcom,tx-crci", );
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_MEM_TO_DEV;
+   conf.device_fc = true;
+   conf.dst_addr = base + UARTDM_TF;
+   conf.dst_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto rel_tx;
+
+   dma->dir = DMA_TO_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
+

[PATCH v2 2/6] tty: serial: msm: replaces (1 << x) with BIT(x) macro

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

Replaces (1 << x) with BIT(x) macro

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.h | 44 -
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 5b7722c3938b..60917d30c6b5 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -21,11 +21,11 @@
 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
 #define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
-#define UART_MR1_RX_RDY_CTL(1 << 7)
-#define UART_MR1_CTS_CTL   (1 << 6)
+#define UART_MR1_RX_RDY_CTLBIT(7)
+#define UART_MR1_CTS_CTL   BIT(6)

 #define UART_MR2   0x0004
-#define UART_MR2_ERROR_MODE(1 << 6)
+#define UART_MR2_ERROR_MODEBIT(6)
 #define UART_MR2_BITS_PER_CHAR 0x30
 #define UART_MR2_BITS_PER_CHAR_5   (0x0 << 4)
 #define UART_MR2_BITS_PER_CHAR_6   (0x1 << 4)
@@ -62,19 +62,19 @@
 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
 #define UART_CR_CMD_FORCE_STALE(4 << 8)
 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
-#define UART_CR_TX_DISABLE (1 << 3)
-#define UART_CR_TX_ENABLE  (1 << 2)
-#define UART_CR_RX_DISABLE (1 << 1)
-#define UART_CR_RX_ENABLE  (1 << 0)
+#define UART_CR_TX_DISABLE BIT(3)
+#define UART_CR_TX_ENABLE  BIT(2)
+#define UART_CR_RX_DISABLE BIT(1)
+#define UART_CR_RX_ENABLE  BIT(0)
 #define UART_CR_CMD_RESET_RXBREAK_START((1 << 11) | (2 << 4))

 #define UART_IMR   0x0014
-#define UART_IMR_TXLEV (1 << 0)
-#define UART_IMR_RXSTALE   (1 << 3)
-#define UART_IMR_RXLEV (1 << 4)
-#define UART_IMR_DELTA_CTS (1 << 5)
-#define UART_IMR_CURRENT_CTS   (1 << 6)
-#define UART_IMR_RXBREAK_START (1 << 10)
+#define UART_IMR_TXLEV BIT(0)
+#define UART_IMR_RXSTALE   BIT(3)
+#define UART_IMR_RXLEV BIT(4)
+#define UART_IMR_DELTA_CTS BIT(5)
+#define UART_IMR_CURRENT_CTS   BIT(6)
+#define UART_IMR_RXBREAK_START BIT(10)

 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
@@ -98,20 +98,20 @@
 #define UART_TEST_CTRL 0x0050

 #define UART_SR0x0008
-#define UART_SR_HUNT_CHAR  (1 << 7)
-#define UART_SR_RX_BREAK   (1 << 6)
-#define UART_SR_PAR_FRAME_ERR  (1 << 5)
-#define UART_SR_OVERRUN(1 << 4)
-#define UART_SR_TX_EMPTY   (1 << 3)
-#define UART_SR_TX_READY   (1 << 2)
-#define UART_SR_RX_FULL(1 << 1)
-#define UART_SR_RX_READY   (1 << 0)
+#define UART_SR_HUNT_CHAR  BIT(7)
+#define UART_SR_RX_BREAK   BIT(6)
+#define UART_SR_PAR_FRAME_ERR  BIT(5)
+#define UART_SR_OVERRUNBIT(4)
+#define UART_SR_TX_EMPTY   BIT(3)
+#define UART_SR_TX_READY   BIT(2)
+#define UART_SR_RX_FULLBIT(1)
+#define UART_SR_RX_READY   BIT(0)

 #define UART_RF0x000C
 #define UARTDM_RF  0x0070
 #define UART_MISR  0x0010
 #define UART_ISR   0x0014
-#define UART_ISR_TX_READY  (1 << 7)
+#define UART_ISR_TX_READY  BIT(7)

 #define UARTDM_RXFS0x50
 #define UARTDM_RXFS_BUF_SHIFT  0x7
--
1.9.1

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[PATCH v2 5/6] tty: serial: msm: Add RX DMA support

[Ivan T. Ivanov]

Add receive DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 232 -
 drivers/tty/serial/msm_serial.h|   4 +
 3 files changed, 236 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a600023d9ec1..182777fac9a2 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -29,6 +29,9 @@ Optional properties:
 - qcom,tx-crci: Identificator  for Client Rate Control Interface to be
used with TX DMA channel. Required when using DMA for transmission
with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator  for Client Rate Control Interface to be
+   used with RX DMA channel. Required when using DMA for reception
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 2f395f5d78d0..fc5f6b3b4bbb 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,7 @@
 #define UARTDM_BURST_SIZE  16   /* in bytes */
 #define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
 #define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)

 enum {
UARTDM_1P1 = 1,
@@ -73,9 +75,11 @@ struct msm_port {
unsigned intold_snap_state;
boolbreak_detected;
struct msm_dma  tx_dma;
+   struct msm_dma  rx_dma;
 };

 static void msm_handle_tx(struct uart_port *port);
+static void msm_start_rx_dma(struct msm_port *msm_port);

 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 {
@@ -114,6 +118,15 @@ static void msm_release_dma(struct msm_port *msm_port)
}

memset(dma, 0, sizeof(*dma));
+
+   dma = _port->rx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   kfree(dma->virt);
+   }
+
+   memset(dma, 0, sizeof(*dma));
 }

 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
@@ -159,6 +172,54 @@ no_tx:
memset(dma, 0, sizeof(*dma));
 }

+static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->rx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "rx");
+   if (IS_ERR(dma->chan))
+   goto no_rx;
+
+   of_property_read_u32(dev->of_node, "qcom,rx-crci", );
+
+   dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
+   if (!dma->virt)
+   goto rel_rx;
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_DEV_TO_MEM;
+   conf.device_fc = true;
+   conf.src_addr = base + UARTDM_RF;
+   conf.src_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto err;
+
+   dma->dir = DMA_FROM_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
+   else
+   dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
+
+   return;
+err:
+   kfree(dma->virt);
+rel_rx:
+   dma_release_channel(dma->chan);
+no_rx:
+   memset(dma, 0, sizeof(*dma));
+}
+
 static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
@@ -306,12 +367,151 @@ unmap:
dma_unmap_single(port->dev, dma->phys, count, dma->dir);
return ret;
 }
+
+static void msm_complete_rx_dma(void *args)
+{
+   struct msm_port *msm_port = args;
+   struct uart_port *port = _port->uart;
+   struct tty_port *tport = >state->port;
+   struct msm_dma *dma = _port->rx_dma;
+   int count = 0, i, sysrq;
+   unsigned long flags;
+   u32 val;
+
+   spin_lock_irqsave(>lock, flags);
+
+   /* Already stopped */
+   if (!dma->count)
+   go

[PATCH v2 6/6] tty: serial: msm: Remove 115.2 Kbps maximum baud rate limitation

[Ivan T. Ivanov]

UART controller is capable to perform transfers up to 4 Mbps.
Remove artificial 115.2 Kbps limitation.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index fc5f6b3b4bbb..abeb3d93 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -882,6 +882,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
{3, 0xdd,  8 },
{2, 0xee, 16 },
{1, 0xff, 31 },
+   {0, 0xff, 31 },
};

divisor = uart_get_divisor(port, baud);
@@ -893,16 +894,29 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
return entry; /* Default to smallest divider */
 }

-static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
+static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
+unsigned long *saved_flags)
 {
unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;
+   unsigned long flags;

entry = msm_find_best_baud(port, baud);

msm_write(port, entry->code, UART_CSR);

+   if (baud > 460800)
+   port->uartclk = baud * 16;
+
+   flags = *saved_flags;
+   spin_unlock_irqrestore(>lock, flags);
+
+   clk_set_rate(msm_port->clk, port->uartclk);
+
+   spin_lock_irqsave(>lock, flags);
+   *saved_flags = flags;
+
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
@@ -1026,8 +1040,8 @@ static void msm_set_termios(struct uart_port *port, 
struct ktermios *termios,
msm_stop_dma(port, dma);

/* calculate and set baud rate */
-   baud = uart_get_baud_rate(port, termios, old, 300, 115200);
-   baud = msm_set_baud_rate(port, baud);
+   baud = uart_get_baud_rate(port, termios, old, 300, 400);
+   baud = msm_set_baud_rate(port, baud, );
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);

--
1.9.1

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[PATCH v2 0/6] tty: serial: msm: Add DMA support and fix bit definitions

[Ivan T. Ivanov]

Hi,

This is second version of patches which DMA support for UARTDM type
of hardware found in Qualcomm chip sets.

Changes since v0 (https://lkml.org/lkml/2015/9/12/108):

* Fixed SysRq issue reported by Srini.
* Dropped [PATCH 3/7], which did not make any functional change.

Ivan T. Ivanov (4):
  tty: serial: msm: Add msm prefix to all driver functions
  tty: serial: msm: Add TX DMA support
  tty: serial: msm: Add RX DMA support
  tty: serial: msm: Remove 115.2 Kbps maximum baud rate limitation

Pramod Gurav (2):
  tty: serial: msm: Add mask value for UART_DM registers
  tty: serial: msm: replaces (1 << x) with BIT(x) macro

 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   6 +
 drivers/tty/serial/msm_serial.c| 620 +++--
 drivers/tty/serial/msm_serial.h|  53 +-
 3 files changed, 606 insertions(+), 73 deletions(-)

--
1.9.1

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[PATCH v2 3/6] tty: serial: msm: Add msm prefix to all driver functions

[Ivan T. Ivanov]

Make function naming consistent across this driver.
Also rename msm_irq to msm_uart_irq. No functional changes.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
---
 drivers/tty/serial/msm_serial.c | 40 
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index d08cfd3e1c3a..e33966280606 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -57,7 +57,7 @@ struct msm_port {
boolbreak_detected;
 };

-static inline void wait_for_xmitr(struct uart_port *port)
+static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
@@ -99,7 +99,7 @@ static void msm_enable_ms(struct uart_port *port)
msm_write(port, msm_port->imr, UART_IMR);
 }

-static void handle_rx_dm(struct uart_port *port, unsigned int misr)
+static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -171,7 +171,7 @@ static void handle_rx_dm(struct uart_port *port, unsigned 
int misr)
msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 }

-static void handle_rx(struct uart_port *port)
+static void msm_handle_rx(struct uart_port *port)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -224,14 +224,14 @@ static void handle_rx(struct uart_port *port)
spin_lock(>lock);
 }

-static void reset_dm_count(struct uart_port *port, int count)
+static void msm_reset_dm_count(struct uart_port *port, int count)
 {
-   wait_for_xmitr(port);
+   msm_wait_for_xmitr(port);
msm_write(port, count, UARTDM_NCF_TX);
msm_read(port, UARTDM_NCF_TX);
 }

-static void handle_tx(struct uart_port *port)
+static void msm_handle_tx(struct uart_port *port)
 {
struct circ_buf *xmit = >state->xmit;
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -250,13 +250,13 @@ static void handle_tx(struct uart_port *port)

if (port->x_char) {
if (msm_port->is_uartdm)
-   reset_dm_count(port, tx_count + 1);
+   msm_reset_dm_count(port, tx_count + 1);

iowrite8_rep(tf, >x_char, 1);
port->icount.tx++;
port->x_char = 0;
} else if (tx_count && msm_port->is_uartdm) {
-   reset_dm_count(port, tx_count);
+   msm_reset_dm_count(port, tx_count);
}

while (tf_pointer < tx_count) {
@@ -290,14 +290,14 @@ static void handle_tx(struct uart_port *port)
uart_write_wakeup(port);
 }

-static void handle_delta_cts(struct uart_port *port)
+static void msm_handle_delta_cts(struct uart_port *port)
 {
msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
port->icount.cts++;
wake_up_interruptible(>state->port.delta_msr_wait);
 }

-static irqreturn_t msm_irq(int irq, void *dev_id)
+static irqreturn_t msm_uart_irq(int irq, void *dev_id)
 {
struct uart_port *port = dev_id;
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -314,14 +314,14 @@ static irqreturn_t msm_irq(int irq, void *dev_id)

if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
if (msm_port->is_uartdm)
-   handle_rx_dm(port, misr);
+   msm_handle_rx_dm(port, misr);
else
-   handle_rx(port);
+   msm_handle_rx(port);
}
if (misr & UART_IMR_TXLEV)
-   handle_tx(port);
+   msm_handle_tx(port);
if (misr & UART_IMR_DELTA_CTS)
-   handle_delta_cts(port);
+   msm_handle_delta_cts(port);

msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
spin_unlock(>lock);
@@ -779,7 +779,7 @@ static void msm_poll_put_char(struct uart_port *port, 
unsigned char c)
msm_write(port, 0, UART_IMR);

if (msm_port->is_uartdm)
-   reset_dm_count(port, 1);
+   msm_reset_dm_count(port, 1);

/* Wait until FIFO is empty */
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
@@ -853,7 +853,7 @@ static struct msm_port msm_uart_ports[] = {

 #define UART_NRARRAY_SIZE(msm_uart_ports)

-static inline struct uart_port *get_port_from_line(unsigned int line)
+static inline struct uart_port *msm_get_port_from_line(unsigned int line)
 {
return _uart_ports[line].uart;
 }
@@ -880,7 +880,7 @@ static void __msm_console_write(struct uart_port *port, 
const char *s,

spin_lock(>lock);
if (is_uartdm)
-   reset_dm_count(port, coun

[PATCH v2 1/6] tty: serial: msm: Add mask value for UART_DM registers

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and
IPR registers respectively are different for UART and UART_DM hardware
cores. We have been using UART core mask values for these. Add the same
for UART_DM core.

There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do
it only for UART core.

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 26 --
 drivers/tty/serial/msm_serial.h |  2 ++
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b73889c8ed4b..d08cfd3e1c3a 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -421,7 +421,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)

 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
 {
-   unsigned int rxstale, watermark;
+   unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;

@@ -432,8 +432,15 @@ static int msm_set_baud_rate(struct uart_port *port, 
unsigned int baud)
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
-   watermark |= UART_IPR_RXSTALE_LAST;
-   watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
+   if (msm_port->is_uartdm) {
+   mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
+   } else {
+   watermark |= UART_IPR_RXSTALE_LAST;
+   mask = UART_IPR_STALE_TIMEOUT_MSB;
+   }
+
+   watermark |= mask & (rxstale << 2);
+
msm_write(port, watermark, UART_IPR);

/* set RX watermark */
@@ -476,7 +483,7 @@ static void msm_init_clock(struct uart_port *port)
 static int msm_startup(struct uart_port *port)
 {
struct msm_port *msm_port = UART_TO_MSM(port);
-   unsigned int data, rfr_level;
+   unsigned int data, rfr_level, mask;
int ret;

snprintf(msm_port->name, sizeof(msm_port->name),
@@ -496,11 +503,18 @@ static int msm_startup(struct uart_port *port)

/* set automatic RFR level */
data = msm_read(port, UART_MR1);
-   data &= ~UART_MR1_AUTO_RFR_LEVEL1;
+
+   if (msm_port->is_uartdm)
+   mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
+   else
+   mask = UART_MR1_AUTO_RFR_LEVEL1;
+
+   data &= ~mask;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
-   data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
+   data |= mask & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
+
return 0;
 }

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 737f69fe7113..5b7722c3938b 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -20,6 +20,7 @@

 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
+#define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
 #define UART_MR1_RX_RDY_CTL(1 << 7)
 #define UART_MR1_CTS_CTL   (1 << 6)

@@ -78,6 +79,7 @@
 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
+#define UART_DM_IPR_STALE_TIMEOUT_MSB  0xFF80

 #define UART_IPR   0x0018
 #define UART_TFWR  0x001C
--
1.9.1

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[PATCH v3 4/6] tty: serial: msm: Add TX DMA support

[Ivan T. Ivanov]

Add transmit DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 312 +++--
 drivers/tty/serial/msm_serial.h|   3 +
 3 files changed, 294 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a2114c217376..a600023d9ec1 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,9 @@ Required properties:
 Optional properties:
 - dmas: Should contain dma specifiers for transmit and receive channels
 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator  for Client Rate Control Interface to be
+   used with TX DMA channel. Required when using DMA for transmission
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 2315a614ff45..7006d979d9d2 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -20,6 +20,8 @@
 #endif

 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -39,6 +41,10 @@

 #include "msm_serial.h"

+#define UARTDM_BURST_SIZE  16   /* in bytes */
+#define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
+#define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+
 enum {
UARTDM_1P1 = 1,
UARTDM_1P2,
@@ -46,6 +52,17 @@ enum {
UARTDM_1P4,
 };

+struct msm_dma {
+   struct dma_chan *chan;
+   enum dma_data_direction dir;
+   dma_addr_t  phys;
+   unsigned char   *virt;
+   dma_cookie_tcookie;
+   u32 enable_bit;
+   unsigned intcount;
+   struct dma_async_tx_descriptor  *desc;
+};
+
 struct msm_port {
struct uart_portuart;
charname[16];
@@ -55,8 +72,93 @@ struct msm_port {
int is_uartdm;
unsigned intold_snap_state;
boolbreak_detected;
+   struct msm_dma  tx_dma;
 };

+static void msm_handle_tx(struct uart_port *port);
+
+void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
+{
+   struct device *dev = port->dev;
+   unsigned int mapped;
+   u32 val;
+
+   mapped = dma->count;
+   dma->count = 0;
+
+   dmaengine_terminate_all(dma->chan);
+
+   /*
+* DMA Stall happens if enqueue and flush command happens concurrently.
+* For example before changing the baud rate/protocol configuration and
+* sending flush command to ADM, disable the channel of UARTDM.
+* Note: should not reset the receiver here immediately as it is not
+* suggested to do disable/reset or reset/disable at the same time.
+*/
+   val = msm_read(port, UARTDM_DMEN);
+   val &= ~dma->enable_bit;
+   msm_write(port, val, UARTDM_DMEN);
+
+   if (mapped)
+   dma_unmap_single(dev, dma->phys, mapped, dma->dir);
+}
+
+static void msm_release_dma(struct msm_port *msm_port)
+{
+   struct msm_dma *dma;
+
+   dma = _port->tx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   }
+
+   memset(dma, 0, sizeof(*dma));
+}
+
+static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->tx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "tx");
+   if (IS_ERR(dma->chan))
+   goto no_tx;
+
+   of_property_read_u32(dev->of_node, "qcom,tx-crci", );
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_MEM_TO_DEV;
+   conf.device_fc = true;
+   conf.dst_addr = base + UARTDM_TF;
+   conf.dst_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto rel_tx;
+
+   dma->dir = DMA_TO_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
+

[PATCH v3 6/6] tty: serial: msm: Remove 115.2 Kbps maximum baud rate limitation

[Ivan T. Ivanov]

UART controller is capable to perform transfers up to 4 Mbps.
Remove artificial 115.2 Kbps limitation.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 3efb80f511db..dcde955475dc 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -882,6 +882,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
{3, 0xdd,  8 },
{2, 0xee, 16 },
{1, 0xff, 31 },
+   {0, 0xff, 31 },
};

divisor = uart_get_divisor(port, baud);
@@ -893,16 +894,29 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
return entry; /* Default to smallest divider */
 }

-static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
+static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
+unsigned long *saved_flags)
 {
unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;
+   unsigned long flags;

entry = msm_find_best_baud(port, baud);

msm_write(port, entry->code, UART_CSR);

+   if (baud > 460800)
+   port->uartclk = baud * 16;
+
+   flags = *saved_flags;
+   spin_unlock_irqrestore(>lock, flags);
+
+   clk_set_rate(msm_port->clk, port->uartclk);
+
+   spin_lock_irqsave(>lock, flags);
+   *saved_flags = flags;
+
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
@@ -1026,8 +1040,8 @@ static void msm_set_termios(struct uart_port *port, 
struct ktermios *termios,
msm_stop_dma(port, dma);

/* calculate and set baud rate */
-   baud = uart_get_baud_rate(port, termios, old, 300, 115200);
-   baud = msm_set_baud_rate(port, baud);
+   baud = uart_get_baud_rate(port, termios, old, 300, 400);
+   baud = msm_set_baud_rate(port, baud, );
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);

--
1.9.1

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Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support

[Ivan T. Ivanov]

On Wed, 2015-09-30 at 14:29 +0100, Mark Rutland wrote:
> On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote:
> > Add transmit DMA support for UARTDM type of controllers.
> > 
> > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
> > and APQ8016, which have UARTDM v1.4 and BAM DMA engine.
> > 
> > Signed-off-by: Ivan T. Ivanov iva...@linaro.org>
> > ---
> >  .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
> >  drivers/tty/serial/msm_serial.c| 312 
> > +++--
> >  drivers/tty/serial/msm_serial.h|   3 +
> >  3 files changed, 294 insertions(+), 24 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
> > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > index a2114c217376..a600023d9ec1 100644
> > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > @@ -26,6 +26,9 @@ Required properties:
> >  Optional properties:
> >  - dmas: Should contain dma specifiers for transmit and receive channels
> >  - dma-names: Should contain "tx" for transmit and "rx" for receive channels
> > +- qcom,tx-crci: Identificator  for Client Rate Control Interface to be
> > +   used with TX DMA channel. Required when using DMA for 
> > transmission
> > +   with UARTDM v1.3 and bellow.
> 
> This sounds like it belongs in the dma-specifier, and dealt with by the
> DMA controller driver.
> 
> Why does the UART driver need to know about this?

CRCI information was part of the first version of ADM DMA engine driver
bindings, but Andy remove it because some client devices are requiring
more that one CRCI number. See here[1] and here [2].

Regards,
Ivan

[1] 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314190.html
[2] https://lkml.org/lkml/2015/8/19/19


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Re: [PATCH v2 0/6] tty: serial: msm: Add DMA support and fix bit definitions

[Ivan T. Ivanov]

On Wed, 2015-09-30 at 15:08 +0300, Ivan T. Ivanov wrote:
> Hi,
> 
> This is second version of patches which DMA support for UARTDM type
> of hardware found in Qualcomm chip sets.
> 

Please ignore this patch set. Wrong set of changes.

Sorry,
Ivan
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[PATCH v3 3/6] tty: serial: msm: Add msm prefix to all driver functions

[Ivan T. Ivanov]

Make function naming consistent across this driver.
Also rename msm_irq to msm_uart_irq. No functional changes.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
---
 drivers/tty/serial/msm_serial.c | 42 -
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index d08cfd3e1c3a..2315a614ff45 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -57,7 +57,7 @@ struct msm_port {
boolbreak_detected;
 };

-static inline void wait_for_xmitr(struct uart_port *port)
+static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
@@ -99,7 +99,7 @@ static void msm_enable_ms(struct uart_port *port)
msm_write(port, msm_port->imr, UART_IMR);
 }

-static void handle_rx_dm(struct uart_port *port, unsigned int misr)
+static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -171,7 +171,7 @@ static void handle_rx_dm(struct uart_port *port, unsigned 
int misr)
msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 }

-static void handle_rx(struct uart_port *port)
+static void msm_handle_rx(struct uart_port *port)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -224,14 +224,14 @@ static void handle_rx(struct uart_port *port)
spin_lock(>lock);
 }

-static void reset_dm_count(struct uart_port *port, int count)
+static void msm_reset_dm_count(struct uart_port *port, int count)
 {
-   wait_for_xmitr(port);
+   msm_wait_for_xmitr(port);
msm_write(port, count, UARTDM_NCF_TX);
msm_read(port, UARTDM_NCF_TX);
 }

-static void handle_tx(struct uart_port *port)
+static void msm_handle_tx(struct uart_port *port)
 {
struct circ_buf *xmit = >state->xmit;
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -250,13 +250,13 @@ static void handle_tx(struct uart_port *port)

if (port->x_char) {
if (msm_port->is_uartdm)
-   reset_dm_count(port, tx_count + 1);
+   msm_reset_dm_count(port, tx_count + 1);

iowrite8_rep(tf, >x_char, 1);
port->icount.tx++;
port->x_char = 0;
} else if (tx_count && msm_port->is_uartdm) {
-   reset_dm_count(port, tx_count);
+   msm_reset_dm_count(port, tx_count);
}

while (tf_pointer < tx_count) {
@@ -290,14 +290,14 @@ static void handle_tx(struct uart_port *port)
uart_write_wakeup(port);
 }

-static void handle_delta_cts(struct uart_port *port)
+static void msm_handle_delta_cts(struct uart_port *port)
 {
msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
port->icount.cts++;
wake_up_interruptible(>state->port.delta_msr_wait);
 }

-static irqreturn_t msm_irq(int irq, void *dev_id)
+static irqreturn_t msm_uart_irq(int irq, void *dev_id)
 {
struct uart_port *port = dev_id;
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -314,14 +314,14 @@ static irqreturn_t msm_irq(int irq, void *dev_id)

if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
if (msm_port->is_uartdm)
-   handle_rx_dm(port, misr);
+   msm_handle_rx_dm(port, misr);
else
-   handle_rx(port);
+   msm_handle_rx(port);
}
if (misr & UART_IMR_TXLEV)
-   handle_tx(port);
+   msm_handle_tx(port);
if (misr & UART_IMR_DELTA_CTS)
-   handle_delta_cts(port);
+   msm_handle_delta_cts(port);

msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
spin_unlock(>lock);
@@ -489,7 +489,7 @@ static int msm_startup(struct uart_port *port)
snprintf(msm_port->name, sizeof(msm_port->name),
 "msm_serial%d", port->line);

-   ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
+   ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
  msm_port->name, port);
if (unlikely(ret))
return ret;
@@ -779,7 +779,7 @@ static void msm_poll_put_char(struct uart_port *port, 
unsigned char c)
msm_write(port, 0, UART_IMR);

if (msm_port->is_uartdm)
-   reset_dm_count(port, 1);
+   msm_reset_dm_count(port, 1);

/* Wait until FIFO is empty */
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
@@ -853,7 +853,7 @@ static struct msm_port msm_uart_ports

[PATCH v3 5/6] tty: serial: msm: Add RX DMA support

[Ivan T. Ivanov]

Add receive DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 232 -
 drivers/tty/serial/msm_serial.h|   4 +
 3 files changed, 236 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a600023d9ec1..182777fac9a2 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -29,6 +29,9 @@ Optional properties:
 - qcom,tx-crci: Identificator  for Client Rate Control Interface to be
used with TX DMA channel. Required when using DMA for transmission
with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator  for Client Rate Control Interface to be
+   used with RX DMA channel. Required when using DMA for reception
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 7006d979d9d2..3efb80f511db 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,7 @@
 #define UARTDM_BURST_SIZE  16   /* in bytes */
 #define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
 #define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)

 enum {
UARTDM_1P1 = 1,
@@ -73,9 +75,11 @@ struct msm_port {
unsigned intold_snap_state;
boolbreak_detected;
struct msm_dma  tx_dma;
+   struct msm_dma  rx_dma;
 };

 static void msm_handle_tx(struct uart_port *port);
+static void msm_start_rx_dma(struct msm_port *msm_port);

 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 {
@@ -114,6 +118,15 @@ static void msm_release_dma(struct msm_port *msm_port)
}

memset(dma, 0, sizeof(*dma));
+
+   dma = _port->rx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   kfree(dma->virt);
+   }
+
+   memset(dma, 0, sizeof(*dma));
 }

 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
@@ -159,6 +172,54 @@ no_tx:
memset(dma, 0, sizeof(*dma));
 }

+static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->rx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "rx");
+   if (IS_ERR(dma->chan))
+   goto no_rx;
+
+   of_property_read_u32(dev->of_node, "qcom,rx-crci", );
+
+   dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
+   if (!dma->virt)
+   goto rel_rx;
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_DEV_TO_MEM;
+   conf.device_fc = true;
+   conf.src_addr = base + UARTDM_RF;
+   conf.src_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto err;
+
+   dma->dir = DMA_FROM_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
+   else
+   dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
+
+   return;
+err:
+   kfree(dma->virt);
+rel_rx:
+   dma_release_channel(dma->chan);
+no_rx:
+   memset(dma, 0, sizeof(*dma));
+}
+
 static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
@@ -306,12 +367,151 @@ unmap:
dma_unmap_single(port->dev, dma->phys, count, dma->dir);
return ret;
 }
+
+static void msm_complete_rx_dma(void *args)
+{
+   struct msm_port *msm_port = args;
+   struct uart_port *port = _port->uart;
+   struct tty_port *tport = >state->port;
+   struct msm_dma *dma = _port->rx_dma;
+   int count = 0, i, sysrq;
+   unsigned long flags;
+   u32 val;
+
+   spin_lock_irqsave(>lock, flags);
+
+   /* Already stopped */
+   if (!dma->count)
+   go

[PATCH v3 2/6] tty: serial: msm: replaces (1 << x) with BIT(x) macro

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

Replaces (1 << x) with BIT(x) macro

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.h | 44 -
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 5b7722c3938b..60917d30c6b5 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -21,11 +21,11 @@
 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
 #define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
-#define UART_MR1_RX_RDY_CTL(1 << 7)
-#define UART_MR1_CTS_CTL   (1 << 6)
+#define UART_MR1_RX_RDY_CTLBIT(7)
+#define UART_MR1_CTS_CTL   BIT(6)

 #define UART_MR2   0x0004
-#define UART_MR2_ERROR_MODE(1 << 6)
+#define UART_MR2_ERROR_MODEBIT(6)
 #define UART_MR2_BITS_PER_CHAR 0x30
 #define UART_MR2_BITS_PER_CHAR_5   (0x0 << 4)
 #define UART_MR2_BITS_PER_CHAR_6   (0x1 << 4)
@@ -62,19 +62,19 @@
 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
 #define UART_CR_CMD_FORCE_STALE(4 << 8)
 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
-#define UART_CR_TX_DISABLE (1 << 3)
-#define UART_CR_TX_ENABLE  (1 << 2)
-#define UART_CR_RX_DISABLE (1 << 1)
-#define UART_CR_RX_ENABLE  (1 << 0)
+#define UART_CR_TX_DISABLE BIT(3)
+#define UART_CR_TX_ENABLE  BIT(2)
+#define UART_CR_RX_DISABLE BIT(1)
+#define UART_CR_RX_ENABLE  BIT(0)
 #define UART_CR_CMD_RESET_RXBREAK_START((1 << 11) | (2 << 4))

 #define UART_IMR   0x0014
-#define UART_IMR_TXLEV (1 << 0)
-#define UART_IMR_RXSTALE   (1 << 3)
-#define UART_IMR_RXLEV (1 << 4)
-#define UART_IMR_DELTA_CTS (1 << 5)
-#define UART_IMR_CURRENT_CTS   (1 << 6)
-#define UART_IMR_RXBREAK_START (1 << 10)
+#define UART_IMR_TXLEV BIT(0)
+#define UART_IMR_RXSTALE   BIT(3)
+#define UART_IMR_RXLEV BIT(4)
+#define UART_IMR_DELTA_CTS BIT(5)
+#define UART_IMR_CURRENT_CTS   BIT(6)
+#define UART_IMR_RXBREAK_START BIT(10)

 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
@@ -98,20 +98,20 @@
 #define UART_TEST_CTRL 0x0050

 #define UART_SR0x0008
-#define UART_SR_HUNT_CHAR  (1 << 7)
-#define UART_SR_RX_BREAK   (1 << 6)
-#define UART_SR_PAR_FRAME_ERR  (1 << 5)
-#define UART_SR_OVERRUN(1 << 4)
-#define UART_SR_TX_EMPTY   (1 << 3)
-#define UART_SR_TX_READY   (1 << 2)
-#define UART_SR_RX_FULL(1 << 1)
-#define UART_SR_RX_READY   (1 << 0)
+#define UART_SR_HUNT_CHAR  BIT(7)
+#define UART_SR_RX_BREAK   BIT(6)
+#define UART_SR_PAR_FRAME_ERR  BIT(5)
+#define UART_SR_OVERRUNBIT(4)
+#define UART_SR_TX_EMPTY   BIT(3)
+#define UART_SR_TX_READY   BIT(2)
+#define UART_SR_RX_FULLBIT(1)
+#define UART_SR_RX_READY   BIT(0)

 #define UART_RF0x000C
 #define UARTDM_RF  0x0070
 #define UART_MISR  0x0010
 #define UART_ISR   0x0014
-#define UART_ISR_TX_READY  (1 << 7)
+#define UART_ISR_TX_READY  BIT(7)

 #define UARTDM_RXFS0x50
 #define UARTDM_RXFS_BUF_SHIFT  0x7
--
1.9.1

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[PATCH v3 0/6] tty: serial: msm: Add DMA support and fix bit definitions

[Ivan T. Ivanov]

Hi,

This is the third version of patches which add DMA support for UARTDM type
of hardware found in Qualcomm chip sets.

Changes since v0 (https://lkml.org/lkml/2015/9/12/108):

* Fixed SysRq issue reported by Srini.
* Dropped [PATCH 3/7], because it did not make functional change.

Ivan T. Ivanov (4):
  tty: serial: msm: Add msm prefix to all driver functions
  tty: serial: msm: Add TX DMA support
  tty: serial: msm: Add RX DMA support
  tty: serial: msm: Remove 115.2 Kbps maximum baud rate limitation

Pramod Gurav (2):
  tty: serial: msm: Add mask value for UART_DM registers
  tty: serial: msm: replaces (1 << x) with BIT(x) macro

 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   6 +
 drivers/tty/serial/msm_serial.c| 622 +++--
 drivers/tty/serial/msm_serial.h|  53 +-
 3 files changed, 607 insertions(+), 74 deletions(-)

--
1.9.1

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[PATCH v3 1/6] tty: serial: msm: Add mask value for UART_DM registers

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and
IPR registers respectively are different for UART and UART_DM hardware
cores. We have been using UART core mask values for these. Add the same
for UART_DM core.

There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do
it only for UART core.

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 26 --
 drivers/tty/serial/msm_serial.h |  2 ++
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b73889c8ed4b..d08cfd3e1c3a 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -421,7 +421,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)

 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
 {
-   unsigned int rxstale, watermark;
+   unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;

@@ -432,8 +432,15 @@ static int msm_set_baud_rate(struct uart_port *port, 
unsigned int baud)
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
-   watermark |= UART_IPR_RXSTALE_LAST;
-   watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
+   if (msm_port->is_uartdm) {
+   mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
+   } else {
+   watermark |= UART_IPR_RXSTALE_LAST;
+   mask = UART_IPR_STALE_TIMEOUT_MSB;
+   }
+
+   watermark |= mask & (rxstale << 2);
+
msm_write(port, watermark, UART_IPR);

/* set RX watermark */
@@ -476,7 +483,7 @@ static void msm_init_clock(struct uart_port *port)
 static int msm_startup(struct uart_port *port)
 {
struct msm_port *msm_port = UART_TO_MSM(port);
-   unsigned int data, rfr_level;
+   unsigned int data, rfr_level, mask;
int ret;

snprintf(msm_port->name, sizeof(msm_port->name),
@@ -496,11 +503,18 @@ static int msm_startup(struct uart_port *port)

/* set automatic RFR level */
data = msm_read(port, UART_MR1);
-   data &= ~UART_MR1_AUTO_RFR_LEVEL1;
+
+   if (msm_port->is_uartdm)
+   mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
+   else
+   mask = UART_MR1_AUTO_RFR_LEVEL1;
+
+   data &= ~mask;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
-   data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
+   data |= mask & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
+
return 0;
 }

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 737f69fe7113..5b7722c3938b 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -20,6 +20,7 @@

 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
+#define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
 #define UART_MR1_RX_RDY_CTL(1 << 7)
 #define UART_MR1_CTS_CTL   (1 << 6)

@@ -78,6 +79,7 @@
 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
+#define UART_DM_IPR_STALE_TIMEOUT_MSB  0xFF80

 #define UART_IPR   0x0018
 #define UART_TFWR  0x001C
--
1.9.1

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Re: [PATCH 0/7] tty: serial: msm: Add DMA support and fix bit definitions

[Ivan T. Ivanov]

On Fri, 2015-09-25 at 00:27 +0100, Srinivas Kandagatla wrote:
> Hi Ivan,
> On 12/09/15 14:02, Ivan T. Ivanov wrote:
> > Hi,
> > 
> > Following patches add DMA support for UARTDM type of hardware.
> > 
> > Changes have been tested on UARTDM v1.3(APQ8064) and v1.4(APQ8016).
> > 
> > Patches from Gurav were published long ago here[1], I just addressed
> > remaining comments and coding style issues.
> > 
> > Any comments are welcome.
> Looks like Magic Sysrq is broken with this patches.

Oh, sorry. Interrupts have to be enabled during 
SysRq processing. I will send updated patch-set.

Regards,
Ivan
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Re: [PATCH 0/7] tty: serial: msm: Add DMA support and fix bit definitions

[Ivan T. Ivanov]

On Fri, 2015-09-25 at 00:27 +0100, Srinivas Kandagatla wrote:
> Hi Ivan,
> On 12/09/15 14:02, Ivan T. Ivanov wrote:
> > Hi,
> > 
> > Following patches add DMA support for UARTDM type of hardware.
> > 
> > Changes have been tested on UARTDM v1.3(APQ8064) and v1.4(APQ8016).
> > 
> > Patches from Gurav were published long ago here[1], I just addressed
> > remaining comments and coding style issues.
> > 
> > Any comments are welcome.
> Looks like Magic Sysrq is broken with this patches.


Will check it shortly.

Thanks,
Ivan
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Re: [PATCH 3/7] tty: serial: msm: Fix command Stale Event Enable definition

[Ivan T. Ivanov]

> On Sep 19, 2015, at 2:33 AM, Stephen Boyd <sb...@codeaurora.org> wrote:
> 
> On 09/12, Ivan T. Ivanov wrote:
>> Stale Event Enable command should be 5 not 8, fix this.
>> 
>> Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
>> ---
>> drivers/tty/serial/msm_serial.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/tty/serial/msm_serial.h 
>> b/drivers/tty/serial/msm_serial.h
>> index 60917d30c6b5..223f961f992a 100644
>> --- a/drivers/tty/serial/msm_serial.h
>> +++ b/drivers/tty/serial/msm_serial.h
>> @@ -59,7 +59,7 @@
>> #define UART_CR_CMD_SET_RFR  (13 << 4)
>> #define UART_CR_CMD_RESET_RFR(14 << 4)
>> #define UART_CR_CMD_PROTECTION_EN(16 << 4)
>> -#define UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
>> +#define UART_CR_CMD_STALE_EVENT_ENABLE  (5 << 8)
> 
> I don't get this one
> 
> 5 << 8 == 80 << 4
> 
> so this makes no difference.


Uh, of course. It is not 0x80. 

Regards,
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[PATCH v2 2/2] arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX

[Ivan T. Ivanov]

Add DMA channels definitions for UART1 and UART2 controllers.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 85f7bee33c18..4d313a9eba7b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -108,6 +108,8 @@
interrupts = ;
clocks = < GCC_BLSP1_UART1_APPS_CLK>, < 
GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 1>, <_dma 0>;
+   dma-names = "rx", "tx";
status = "disabled";
};

@@ -117,6 +119,8 @@
interrupts = ;
clocks = < GCC_BLSP1_UART2_APPS_CLK>, < 
GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 3>, <_dma 2>;
+   dma-names = "rx", "tx";
status = "disabled";
};

--
1.9.1

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[PATCH v2 0/2] arm64: dts: qcom: 8x16: UARTDM additions

[Ivan T. Ivanov]

Hi,

This is second version of the changes previously posted [1].
I have to rebase them on top of Andy's for-next[2] branch and rework them
a little bit, because some of the definitions have been already merged.

Regards,
Ivan

[1] https://lkml.org/lkml/2015/9/12/114
[2] https://www.codeaurora.org/cgit/quic/kernel/agross-msm/

Ivan T. Ivanov (2):
  arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations
  arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX

 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 13 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  4 
 2 files changed, 13 insertions(+), 4 deletions(-)

--
1.9.1

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[PATCH v2 1/2] arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations

[Ivan T. Ivanov]

Add devicetree bindings for UART1 CTS_N and RTS_N pins.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 42941b977c48..f9b74bb14d31 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -16,10 +16,13 @@
blsp1_uart1_default: blsp1_uart1_default {
pinmux {
function = "blsp_uart1";
-   pins = "gpio0", "gpio1";
+   //  TX, RX, CTS_N, RTS_N
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
};
pinconf {
-   pins = "gpio0", "gpio1";
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
drive-strength = <16>;
bias-disable;
};
@@ -28,10 +31,12 @@
blsp1_uart1_sleep: blsp1_uart1_sleep {
pinmux {
function = "gpio";
-   pins = "gpio0", "gpio1";
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
};
pinconf {
-   pins = "gpio0", "gpio1";
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
drive-strength = <2>;
bias-pull-down;
};
--
1.9.1

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Re: [PATCH v2 1/2] input: Add Qualcomm PM8941 power key driver

[Ivan T. Ivanov]

On Fri, 2015-01-23 at 16:19 -0800, Bjorn Andersson wrote:
> From: Courtney Cavin ca...@sonymobile.com>
> 
> Signed-off-by: Courtney Cavin ca...@sonymobile.com>
> Signed-off-by: Bjorn Andersson anders...@sonymobile.com>
> 



> 
> +config INPUT_PM8941_PWRKEY
> +   tristate "Qualcomm PM8941 power key support"
> +   depends on MFD_SPMI_PMIC
> +   help
> +   Say Y here if you want support for the power key 
> usually found
> +   on boards using a Qualcomm PM8941 compatible PMIC.
> +

Hi Bjorn, Courtney, 

Do you plan to extend this driver to support RESIN_N PMIC input?
 
It looks like the same downstream "qcom,qpnp-power-on" handle
this functionality for recent PMIC versions.

What will be the best way to add this new functionality, extend
this driver, write new one...?

Regards,
Ivan


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[PATCH 3/7] tty: serial: msm: Fix command Stale Event Enable definition

[Ivan T. Ivanov]

Stale Event Enable command should be 5 not 8, fix this.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 60917d30c6b5..223f961f992a 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -59,7 +59,7 @@
 #define UART_CR_CMD_SET_RFR(13 << 4)
 #define UART_CR_CMD_RESET_RFR  (14 << 4)
 #define UART_CR_CMD_PROTECTION_EN  (16 << 4)
-#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
+#define UART_CR_CMD_STALE_EVENT_ENABLE (5 << 8)
 #define UART_CR_CMD_FORCE_STALE(4 << 8)
 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
 #define UART_CR_TX_DISABLE BIT(3)
--
1.9.1

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[PATCH 7/7] tty: serial: msm: Remove 115.2 Kbps maximum baud rate limitation

[Ivan T. Ivanov]

UART controller is capable to perform transfers up to 4 Mbps.
Remove artificial 115.2 Kbps limitation.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 3f975392ebc0..223514979685 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -880,6 +880,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
{3, 0xdd,  8 },
{2, 0xee, 16 },
{1, 0xff, 31 },
+   {0, 0xff, 31 },
};

divisor = uart_get_divisor(port, baud);
@@ -891,16 +892,29 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)
return entry; /* Default to smallest divider */
 }

-static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
+static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
+unsigned long *saved_flags)
 {
unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;
+   unsigned long flags;

entry = msm_find_best_baud(port, baud);

msm_write(port, entry->code, UART_CSR);

+   if (baud > 460800)
+   port->uartclk = baud * 16;
+
+   flags = *saved_flags;
+   spin_unlock_irqrestore(>lock, flags);
+
+   clk_set_rate(msm_port->clk, port->uartclk);
+
+   spin_lock_irqsave(>lock, flags);
+   *saved_flags = flags;
+
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
@@ -1024,8 +1038,8 @@ static void msm_set_termios(struct uart_port *port, 
struct ktermios *termios,
msm_stop_dma(port, dma);

/* calculate and set baud rate */
-   baud = uart_get_baud_rate(port, termios, old, 300, 115200);
-   baud = msm_set_baud_rate(port, baud);
+   baud = uart_get_baud_rate(port, termios, old, 300, 400);
+   baud = msm_set_baud_rate(port, baud, );
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);

--
1.9.1

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[PATCH 4/7] tty: serial: msm: Add msm prefix to all driver functions

[Ivan T. Ivanov]

Make function naming consistent across this driver.
No functional changes.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 38 +++---
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index d08cfd3e1c3a..1c2a02634853 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -57,7 +57,7 @@ struct msm_port {
boolbreak_detected;
 };

-static inline void wait_for_xmitr(struct uart_port *port)
+static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
@@ -99,7 +99,7 @@ static void msm_enable_ms(struct uart_port *port)
msm_write(port, msm_port->imr, UART_IMR);
 }

-static void handle_rx_dm(struct uart_port *port, unsigned int misr)
+static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -171,7 +171,7 @@ static void handle_rx_dm(struct uart_port *port, unsigned 
int misr)
msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 }

-static void handle_rx(struct uart_port *port)
+static void msm_handle_rx(struct uart_port *port)
 {
struct tty_port *tport = >state->port;
unsigned int sr;
@@ -224,14 +224,14 @@ static void handle_rx(struct uart_port *port)
spin_lock(>lock);
 }

-static void reset_dm_count(struct uart_port *port, int count)
+static void msm_reset_dm_count(struct uart_port *port, int count)
 {
-   wait_for_xmitr(port);
+   msm_wait_for_xmitr(port);
msm_write(port, count, UARTDM_NCF_TX);
msm_read(port, UARTDM_NCF_TX);
 }

-static void handle_tx(struct uart_port *port)
+static void msm_handle_tx(struct uart_port *port)
 {
struct circ_buf *xmit = >state->xmit;
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -250,13 +250,13 @@ static void handle_tx(struct uart_port *port)

if (port->x_char) {
if (msm_port->is_uartdm)
-   reset_dm_count(port, tx_count + 1);
+   msm_reset_dm_count(port, tx_count + 1);

iowrite8_rep(tf, >x_char, 1);
port->icount.tx++;
port->x_char = 0;
} else if (tx_count && msm_port->is_uartdm) {
-   reset_dm_count(port, tx_count);
+   msm_reset_dm_count(port, tx_count);
}

while (tf_pointer < tx_count) {
@@ -290,7 +290,7 @@ static void handle_tx(struct uart_port *port)
uart_write_wakeup(port);
 }

-static void handle_delta_cts(struct uart_port *port)
+static void msm_handle_delta_cts(struct uart_port *port)
 {
msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
port->icount.cts++;
@@ -314,14 +314,14 @@ static irqreturn_t msm_irq(int irq, void *dev_id)

if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
if (msm_port->is_uartdm)
-   handle_rx_dm(port, misr);
+   msm_handle_rx_dm(port, misr);
else
-   handle_rx(port);
+   msm_handle_rx(port);
}
if (misr & UART_IMR_TXLEV)
-   handle_tx(port);
+   msm_handle_tx(port);
if (misr & UART_IMR_DELTA_CTS)
-   handle_delta_cts(port);
+   msm_handle_delta_cts(port);

msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
spin_unlock(>lock);
@@ -779,7 +779,7 @@ static void msm_poll_put_char(struct uart_port *port, 
unsigned char c)
msm_write(port, 0, UART_IMR);

if (msm_port->is_uartdm)
-   reset_dm_count(port, 1);
+   msm_reset_dm_count(port, 1);

/* Wait until FIFO is empty */
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
@@ -853,7 +853,7 @@ static struct msm_port msm_uart_ports[] = {

 #define UART_NRARRAY_SIZE(msm_uart_ports)

-static inline struct uart_port *get_port_from_line(unsigned int line)
+static inline struct uart_port *msm_get_port_from_line(unsigned int line)
 {
return _uart_ports[line].uart;
 }
@@ -880,7 +880,7 @@ static void __msm_console_write(struct uart_port *port, 
const char *s,

spin_lock(>lock);
if (is_uartdm)
-   reset_dm_count(port, count);
+   msm_reset_dm_count(port, count);

i = 0;
while (i < count) {
@@ -925,7 +925,7 @@ static void msm_console_write(struct console *co, const 
char *s,

BUG_ON(co->index < 0 || co->index >= UART_NR);

-   port = get_port_from_line(co->index);
+   port = msm_get_port_from_line(co->index);
msm_p

[PATCH 5/7] tty: serial: msm: Add TX DMA support

[Ivan T. Ivanov]

Add transmit DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 312 +++--
 drivers/tty/serial/msm_serial.h|   3 +
 3 files changed, 294 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a2114c217376..a600023d9ec1 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,9 @@ Required properties:
 Optional properties:
 - dmas: Should contain dma specifiers for transmit and receive channels
 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator  for Client Rate Control Interface to be
+   used with TX DMA channel. Required when using DMA for transmission
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 1c2a02634853..e40611afad09 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -20,6 +20,8 @@
 #endif

 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -39,6 +41,10 @@

 #include "msm_serial.h"

+#define UARTDM_BURST_SIZE  16   /* in bytes */
+#define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
+#define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+
 enum {
UARTDM_1P1 = 1,
UARTDM_1P2,
@@ -46,6 +52,17 @@ enum {
UARTDM_1P4,
 };

+struct msm_dma {
+   struct dma_chan *chan;
+   enum dma_data_direction dir;
+   dma_addr_t  phys;
+   unsigned char   *virt;
+   dma_cookie_tcookie;
+   u32 enable_bit;
+   unsigned intcount;
+   struct dma_async_tx_descriptor  *desc;
+};
+
 struct msm_port {
struct uart_portuart;
charname[16];
@@ -55,8 +72,93 @@ struct msm_port {
int is_uartdm;
unsigned intold_snap_state;
boolbreak_detected;
+   struct msm_dma  tx_dma;
 };

+static void msm_handle_tx(struct uart_port *port);
+
+void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
+{
+   struct device *dev = port->dev;
+   unsigned int mapped;
+   u32 val;
+
+   mapped = dma->count;
+   dma->count = 0;
+
+   dmaengine_terminate_all(dma->chan);
+
+   /*
+* DMA Stall happens if enqueue and flush command happens concurrently.
+* For example before changing the baud rate/protocol configuration and
+* sending flush command to ADM, disable the channel of UARTDM.
+* Note: should not reset the receiver here immediately as it is not
+* suggested to do disable/reset or reset/disable at the same time.
+*/
+   val = msm_read(port, UARTDM_DMEN);
+   val &= ~dma->enable_bit;
+   msm_write(port, val, UARTDM_DMEN);
+
+   if (mapped)
+   dma_unmap_single(dev, dma->phys, mapped, dma->dir);
+}
+
+static void msm_release_dma(struct msm_port *msm_port)
+{
+   struct msm_dma *dma;
+
+   dma = _port->tx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   }
+
+   memset(dma, 0, sizeof(*dma));
+}
+
+static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->tx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "tx");
+   if (IS_ERR(dma->chan))
+   goto no_tx;
+
+   of_property_read_u32(dev->of_node, "qcom,tx-crci", );
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_MEM_TO_DEV;
+   conf.device_fc = true;
+   conf.dst_addr = base + UARTDM_TF;
+   conf.dst_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto rel_tx;
+
+   dma->dir = DMA_TO_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
+

[PATCH 2/2] arm64: dts: qcom: 8x16: UART2 use DMA for RX and TX

[Ivan T. Ivanov]

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index f10ff7a2d0e3..6874221ec355 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -120,6 +120,8 @@
interrupts = ;
clocks = < GCC_BLSP1_UART2_APPS_CLK>, < 
GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 3>, <_dma 2>;
+   dma-names = "rx", "tx";
status = "disabled";
};

--
1.9.1

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[PATCH 6/7] tty: serial: msm: Add RX DMA support

[Ivan T. Ivanov]

Add receive DMA support for UARTDM type of controllers.

Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
 drivers/tty/serial/msm_serial.c| 230 -
 drivers/tty/serial/msm_serial.h|   4 +
 3 files changed, 234 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a600023d9ec1..182777fac9a2 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -29,6 +29,9 @@ Optional properties:
 - qcom,tx-crci: Identificator  for Client Rate Control Interface to be
used with TX DMA channel. Required when using DMA for transmission
with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator  for Client Rate Control Interface to be
+   used with RX DMA channel. Required when using DMA for reception
+   with UARTDM v1.3 and bellow.

 Note: Aliases may be defined to ensure the correct ordering of the UARTs.
 The alias serialN will result in the UART being assigned port N.  If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index e40611afad09..3f975392ebc0 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,7 @@
 #define UARTDM_BURST_SIZE  16   /* in bytes */
 #define UARTDM_TX_AIGN(x)  ((x) & ~0x3) /* valid for > 1p3 */
 #define UARTDM_TX_MAX  256   /* in bytes, valid for <= 1p3 */
+#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)

 enum {
UARTDM_1P1 = 1,
@@ -73,9 +75,11 @@ struct msm_port {
unsigned intold_snap_state;
boolbreak_detected;
struct msm_dma  tx_dma;
+   struct msm_dma  rx_dma;
 };

 static void msm_handle_tx(struct uart_port *port);
+static void msm_start_rx_dma(struct msm_port *msm_port);

 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 {
@@ -114,6 +118,15 @@ static void msm_release_dma(struct msm_port *msm_port)
}

memset(dma, 0, sizeof(*dma));
+
+   dma = _port->rx_dma;
+   if (dma->chan) {
+   msm_stop_dma(_port->uart, dma);
+   dma_release_channel(dma->chan);
+   kfree(dma->virt);
+   }
+
+   memset(dma, 0, sizeof(*dma));
 }

 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
@@ -159,6 +172,54 @@ no_tx:
memset(dma, 0, sizeof(*dma));
 }

+static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+   struct device *dev = msm_port->uart.dev;
+   struct dma_slave_config conf;
+   struct msm_dma *dma;
+   u32 crci = 0;
+   int ret;
+
+   dma = _port->rx_dma;
+
+   /* allocate DMA resources, if available */
+   dma->chan = dma_request_slave_channel_reason(dev, "rx");
+   if (IS_ERR(dma->chan))
+   goto no_rx;
+
+   of_property_read_u32(dev->of_node, "qcom,rx-crci", );
+
+   dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
+   if (!dma->virt)
+   goto rel_rx;
+
+   memset(, 0, sizeof(conf));
+   conf.direction = DMA_DEV_TO_MEM;
+   conf.device_fc = true;
+   conf.src_addr = base + UARTDM_RF;
+   conf.src_maxburst = UARTDM_BURST_SIZE;
+   conf.slave_id = crci;
+
+   ret = dmaengine_slave_config(dma->chan, );
+   if (ret)
+   goto err;
+
+   dma->dir = DMA_FROM_DEVICE;
+
+   if (msm_port->is_uartdm < UARTDM_1P4)
+   dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
+   else
+   dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
+
+   return;
+err:
+   kfree(dma->virt);
+rel_rx:
+   dma_release_channel(dma->chan);
+no_rx:
+   memset(dma, 0, sizeof(*dma));
+}
+
 static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
@@ -306,12 +367,149 @@ unmap:
dma_unmap_single(port->dev, dma->phys, count, dma->dir);
return ret;
 }
+
+static void msm_complete_rx_dma(void *args)
+{
+   struct msm_port *msm_port = args;
+   struct uart_port *port = _port->uart;
+   struct tty_port *tport = >state->port;
+   struct msm_dma *dma = _port->rx_dma;
+   int count = 0, i, sysrq;
+   unsigned long flags;
+   u32 val;
+
+   spin_lock_irqsave(>lock, flags);
+
+   /* Already stopped */
+   if (!dma->count)
+   go

[PATCH 2/7] tty: serial: msm: replaces (1 << x) with BIT(x) macro

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

Replaces (1 << x) with BIT(x) macro

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.h | 44 -
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 5b7722c3938b..60917d30c6b5 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -21,11 +21,11 @@
 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
 #define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
-#define UART_MR1_RX_RDY_CTL(1 << 7)
-#define UART_MR1_CTS_CTL   (1 << 6)
+#define UART_MR1_RX_RDY_CTLBIT(7)
+#define UART_MR1_CTS_CTL   BIT(6)

 #define UART_MR2   0x0004
-#define UART_MR2_ERROR_MODE(1 << 6)
+#define UART_MR2_ERROR_MODEBIT(6)
 #define UART_MR2_BITS_PER_CHAR 0x30
 #define UART_MR2_BITS_PER_CHAR_5   (0x0 << 4)
 #define UART_MR2_BITS_PER_CHAR_6   (0x1 << 4)
@@ -62,19 +62,19 @@
 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
 #define UART_CR_CMD_FORCE_STALE(4 << 8)
 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
-#define UART_CR_TX_DISABLE (1 << 3)
-#define UART_CR_TX_ENABLE  (1 << 2)
-#define UART_CR_RX_DISABLE (1 << 1)
-#define UART_CR_RX_ENABLE  (1 << 0)
+#define UART_CR_TX_DISABLE BIT(3)
+#define UART_CR_TX_ENABLE  BIT(2)
+#define UART_CR_RX_DISABLE BIT(1)
+#define UART_CR_RX_ENABLE  BIT(0)
 #define UART_CR_CMD_RESET_RXBREAK_START((1 << 11) | (2 << 4))

 #define UART_IMR   0x0014
-#define UART_IMR_TXLEV (1 << 0)
-#define UART_IMR_RXSTALE   (1 << 3)
-#define UART_IMR_RXLEV (1 << 4)
-#define UART_IMR_DELTA_CTS (1 << 5)
-#define UART_IMR_CURRENT_CTS   (1 << 6)
-#define UART_IMR_RXBREAK_START (1 << 10)
+#define UART_IMR_TXLEV BIT(0)
+#define UART_IMR_RXSTALE   BIT(3)
+#define UART_IMR_RXLEV BIT(4)
+#define UART_IMR_DELTA_CTS BIT(5)
+#define UART_IMR_CURRENT_CTS   BIT(6)
+#define UART_IMR_RXBREAK_START BIT(10)

 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
@@ -98,20 +98,20 @@
 #define UART_TEST_CTRL 0x0050

 #define UART_SR0x0008
-#define UART_SR_HUNT_CHAR  (1 << 7)
-#define UART_SR_RX_BREAK   (1 << 6)
-#define UART_SR_PAR_FRAME_ERR  (1 << 5)
-#define UART_SR_OVERRUN(1 << 4)
-#define UART_SR_TX_EMPTY   (1 << 3)
-#define UART_SR_TX_READY   (1 << 2)
-#define UART_SR_RX_FULL(1 << 1)
-#define UART_SR_RX_READY   (1 << 0)
+#define UART_SR_HUNT_CHAR  BIT(7)
+#define UART_SR_RX_BREAK   BIT(6)
+#define UART_SR_PAR_FRAME_ERR  BIT(5)
+#define UART_SR_OVERRUNBIT(4)
+#define UART_SR_TX_EMPTY   BIT(3)
+#define UART_SR_TX_READY   BIT(2)
+#define UART_SR_RX_FULLBIT(1)
+#define UART_SR_RX_READY   BIT(0)

 #define UART_RF0x000C
 #define UARTDM_RF  0x0070
 #define UART_MISR  0x0010
 #define UART_ISR   0x0014
-#define UART_ISR_TX_READY  (1 << 7)
+#define UART_ISR_TX_READY  BIT(7)

 #define UARTDM_RXFS0x50
 #define UARTDM_RXFS_BUF_SHIFT  0x7
--
1.9.1

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[PATCH 1/7] tty: serial: msm: Add mask value for UART_DM registers

[Ivan T. Ivanov]

From: Pramod Gurav <gpra...@codeaurora.org>

The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and
IPR registers respectively are different for UART and UART_DM hardware
cores. We have been using UART core mask values for these. Add the same
for UART_DM core.

There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do
it only for UART core.

Signed-off-by: Pramod Gurav <gpra...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 drivers/tty/serial/msm_serial.c | 26 --
 drivers/tty/serial/msm_serial.h |  2 ++
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b73889c8ed4b..d08cfd3e1c3a 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -421,7 +421,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int 
baud)

 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
 {
-   unsigned int rxstale, watermark;
+   unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = UART_TO_MSM(port);
const struct msm_baud_map *entry;

@@ -432,8 +432,15 @@ static int msm_set_baud_rate(struct uart_port *port, 
unsigned int baud)
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = UART_IPR_STALE_LSB & rxstale;
-   watermark |= UART_IPR_RXSTALE_LAST;
-   watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
+   if (msm_port->is_uartdm) {
+   mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
+   } else {
+   watermark |= UART_IPR_RXSTALE_LAST;
+   mask = UART_IPR_STALE_TIMEOUT_MSB;
+   }
+
+   watermark |= mask & (rxstale << 2);
+
msm_write(port, watermark, UART_IPR);

/* set RX watermark */
@@ -476,7 +483,7 @@ static void msm_init_clock(struct uart_port *port)
 static int msm_startup(struct uart_port *port)
 {
struct msm_port *msm_port = UART_TO_MSM(port);
-   unsigned int data, rfr_level;
+   unsigned int data, rfr_level, mask;
int ret;

snprintf(msm_port->name, sizeof(msm_port->name),
@@ -496,11 +503,18 @@ static int msm_startup(struct uart_port *port)

/* set automatic RFR level */
data = msm_read(port, UART_MR1);
-   data &= ~UART_MR1_AUTO_RFR_LEVEL1;
+
+   if (msm_port->is_uartdm)
+   mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
+   else
+   mask = UART_MR1_AUTO_RFR_LEVEL1;
+
+   data &= ~mask;
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
-   data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
+   data |= mask & (rfr_level << 2);
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, UART_MR1);
+
return 0;
 }

diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 737f69fe7113..5b7722c3938b 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -20,6 +20,7 @@

 #define UART_MR1_AUTO_RFR_LEVEL0   0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1   0x3FF00
+#define UART_DM_MR1_AUTO_RFR_LEVEL10xFF00
 #define UART_MR1_RX_RDY_CTL(1 << 7)
 #define UART_MR1_CTS_CTL   (1 << 6)

@@ -78,6 +79,7 @@
 #define UART_IPR_RXSTALE_LAST  0x20
 #define UART_IPR_STALE_LSB 0x1F
 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
+#define UART_DM_IPR_STALE_TIMEOUT_MSB  0xFF80

 #define UART_IPR   0x0018
 #define UART_TFWR  0x001C
--
1.9.1

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[PATCH 1/2] arm64: dts: qcom: 8x16: Add UART1 configuration nodes

[Ivan T. Ivanov]

Add devicetree bindings for UART1 pins and device
controller with DMA channel specifiers.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 29 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  | 12 
 2 files changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 568956859088..1330a7a6bcf1 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -13,6 +13,35 @@

  {

+   blsp1_uart1_default: blsp1_uart1_default {
+   pinmux {
+   function = "blsp_uart1";
+   //  TX, RX, CTS_N, RTS_N
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
+   };
+   pinconf {
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
+   drive-strength = <16>;
+   bias-disable;
+   };
+   };
+
+   blsp1_uart1_sleep: blsp1_uart1_sleep {
+   pinmux {
+   function = "blsp_uart1";
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
+   };
+   pinconf {
+   pins = "gpio0", "gpio1",
+  "gpio2", "gpio3";
+   drive-strength = <2>;
+   bias-pull-down;
+   };
+   };
+
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5911de008dd5..f10ff7a2d0e3 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -102,6 +102,18 @@
reg = <0x180 0x8>;
};

+   blsp1_uart1: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 1>, <_dma 0>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
blsp1_uart2: serial@78b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b 0x200>;
--
1.9.1

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Re: [PATCH v3] usb: chipidea: Use extcon framework for VBUS and ID detect

[Ivan T. Ivanov]

On Fri, 2015-06-05 at 17:26 +0800, Peter Chen wrote:
> On Fri, Jun 05, 2015 at 10:37:07AM +0300, Ivan T. Ivanov wrote:



> 
> > > > +
> > > > +static int ci_id_notifier(struct notifier_block *nb, unsigned long 
> > > > event,
> > > > +   void *ptr)
> > > > +{
> > > > +   struct ci_hdrc_cable *id = container_of(nb, struct 
> > > > ci_hdrc_cable, nb);
> > > > +   struct ci_hdrc *ci = id->ci;
> > > > +
> > > > +   if (event)
> > > > +   id->state = false;
> > > > +   else
> > > > +   id->state = true;
> > > > +
> > > > +   id->changed = true;
> > > > +
> 
> How to know the id value must be changed?
> How about using id->changed = (event != id->state) ? true : false?
> of cos, it needs to move before if {}.

This is handled already by extcon framework.

> 
> The same change may need to add to vbus notifier.
> 
> > > > +   ci_irq(ci->irq, ci);
> > > > +   return NOTIFY_DONE;
> > > > +}
> > > > +
> > > >  static int ci_get_platdata(struct device *dev,
> > > > struct ci_hdrc_platform_data *platdata)
> > > >  {
> > > > +   struct extcon_dev *ext_vbus, *ext_id;
> > > > +   struct ci_hdrc_cable *cable;
> > > > +   int ret;
> > > > +
> > > > if (!platdata->phy_mode)
> > > > platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
> > > > 
> > > > @@ -591,9 +630,89 @@ static int ci_get_platdata(struct device *dev,
> > > > if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
> > > > platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
> > > > 
> > > > +   ext_id = ERR_PTR(-ENODEV);
> > > > +   ext_vbus = ERR_PTR(-ENODEV);
> > > > +   if (of_property_read_bool(dev->of_node, "extcon")) {
> > > > +   /* Each one of them is not mandatory */
> > > > +   ext_vbus = extcon_get_edev_by_phandle(dev, 0);
> > > > +   if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
> > > > +   return PTR_ERR(ext_vbus);
> > > > +
> > > > +   ext_id = extcon_get_edev_by_phandle(dev, 1);
> > > > +   if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
> > > > +   return PTR_ERR(ext_id);
> > > > +   }
> > > > +
> > > > +   cable = >vbus_extcon;
> > > > +   cable->nb.notifier_call = ci_vbus_notifier;
> > > > +   cable->edev = ext_vbus;
> > > > +
> > > > +   if (!IS_ERR(ext_vbus)) {
> > > > +   ret = extcon_get_cable_state(cable->edev, "USB");
> 
> I have not read extcon framework too much, but seems you should only
> can get cable state after register it (through ci_extcon_register)?
> ci_get_platdata is called before ci core probe.

No that is not a problem, you can always read cable state if you have
reference to extcon device.

Will fix remaining comments in next version.

Regards,
Ivan
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[PATCH v4] usb: chipidea: Use extcon framework for VBUS and ID detect

[Ivan T. Ivanov]

On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.

Signed-off-by: Ivan T. Ivanov <ivan.iva...@linaro.org>
---

Changes sice v3 [1]:

* Migrate to new extcon framework API
* Address comments from Peter Chen.

Tested DRD role with "qcom,ci-hdrc" and "qcom,usb-8x16-phy" on DB410c

[1] https://lkml.org/lkml/2015/6/2/333

 .../devicetree/bindings/usb/ci-hdrc-usb2.txt   |   6 +
 drivers/usb/chipidea/Kconfig   |   1 +
 drivers/usb/chipidea/core.c| 125 +
 drivers/usb/chipidea/otg.c |  39 ++-
 include/linux/usb/chipidea.h   |  23 
 5 files changed, 193 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt 
b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
index d71ef07bca5d..aea7d0af5fd6 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
@@ -45,6 +45,11 @@ Optional properties:
   (4 bytes), This register represents the maximum length of a the burst
   in 32-bit words while moving data from the USB bus to system memory,
   changing this value takes effect only the SBUSCFG.AHBBRST is 0.
+- extcon: phandles to external connector devices. First phandle should point to
+  external connector, which provide "USB" cable events, the second should point
+  to external connector device, which provide "USB-HOST" cable events. If one
+  of the external connector devices is not required, empty <0> phandle should
+  be specified.

 Example:

@@ -61,4 +66,5 @@ Example:
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>; /* 64 bytes */
rx-burst-size-dword = <0x10>;
+   extcon = <0>, <_id>;
};
diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
index 5ce3f1d6a6ed..5619b8ca3bf3 100644
--- a/drivers/usb/chipidea/Kconfig
+++ b/drivers/usb/chipidea/Kconfig
@@ -1,6 +1,7 @@
 config USB_CHIPIDEA
tristate "ChipIdea Highspeed Dual Role Controller"
depends on ((USB_EHCI_HCD && USB_GADGET) || (USB_EHCI_HCD && 
!USB_GADGET) || (!USB_EHCI_HCD && USB_GADGET)) && HAS_DMA
+   select EXTCON
help
  Say Y here if your system has a dual role high speed USB
  controller based on ChipIdea silicon IP. Currently, only the
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 3feebf7f31f0..573c2876b263 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -47,6 +47,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -602,9 +603,45 @@ static irqreturn_t ci_irq(int irq, void *data)
return ret;
 }

+static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
+   void *ptr)
+{
+   struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
+   struct ci_hdrc *ci = vbus->ci;
+
+   if (event)
+   vbus->state = true;
+   else
+   vbus->state = false;
+
+   vbus->changed = true;
+
+   ci_irq(ci->irq, ci);
+   return NOTIFY_DONE;
+}
+
+static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
+ void *ptr)
+{
+   struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
+   struct ci_hdrc *ci = id->ci;
+
+   if (event)
+   id->state = false;
+   else
+   id->state = true;
+
+   id->changed = true;
+
+   ci_irq(ci->irq, ci);
+   return NOTIFY_DONE;
+}
+
 static int ci_get_platdata(struct device *dev,
struct ci_hdrc_platform_data *platdata)
 {
+   struct extcon_dev *ext_vbus, *ext_id;
+   struct ci_hdrc_cable *cable;
int ret;

if (!platdata->phy_mode)
@@ -695,9 +732,91 @@ static int ci_get_platdata(struct device *dev,
platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
}

+   ext_id = ERR_PTR(-ENODEV);
+   ext_vbus = ERR_PTR(-ENODEV);
+   if (of_property_read_bool(dev->of_node, "extcon")) {
+   /* Each one of them is not mandatory */
+   ext_vbus = extcon_get_edev_by_phandle(dev, 0);
+   if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
+   return PTR_ERR(ext_vbus);
+
+   ext_id = extcon_get_edev_by_phandle(dev, 1);
+   if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
+   return PTR_ERR(ext_id);
+   }
+
+   cable = >vbus_extcon;
+   cable->nb.notifier_call = ci_vbus_notifier;
+   cabl

[PATCH v2] usb: phy: msm: Add D+/D- lines route control

[Ivan T. Ivanov]

apq8016-sbc board is using Dual SPDT USB Switch (TC7USB40MU),
witch is controlled by GPIO to de/multiplex D+/D- USB lines to
USB2513B Hub and uB connector. Add support for this.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---

* Rebased on current testing/next.

 .../devicetree/bindings/usb/msm-hsusb.txt  |  4 ++
 drivers/usb/phy/phy-msm-usb.c  | 47 ++
 include/linux/usb/msm_hsusb.h  |  7 
 3 files changed, 58 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index bd8d9e7..8654a3e 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -52,6 +52,10 @@ Required properties:
 Optional properties:
 - dr_mode:  One of host, peripheral or otg. Defaults to otg

+- switch-gpio:  A phandle + gpio-specifier pair. Some boards are using Dual
+SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
+D+/D- USB lines between connectors.
+
 - qcom,phy-init-sequence: PHY configuration sequence values. This is related 
to Device
 Mode Eye Diagram test. Start address at which these values 
will be
 written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 61d86d8..c58c3c0 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -18,6 +18,7 @@

 #include linux/module.h
 #include linux/device.h
+#include linux/gpio/consumer.h
 #include linux/platform_device.h
 #include linux/clk.h
 #include linux/slab.h
@@ -32,6 +33,7 @@
 #include linux/pm_runtime.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/reboot.h
 #include linux/reset.h

 #include linux/usb.h
@@ -1471,6 +1473,14 @@ static int msm_otg_vbus_notifier(struct notifier_block 
*nb, unsigned long event,
else
clear_bit(B_SESS_VLD, motg-inputs);

+   if (test_bit(B_SESS_VLD, motg-inputs)) {
+   /* Switch D+/D- lines to Device connector */
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   } else {
+   /* Switch D+/D- lines to Hub */
+   gpiod_set_value_cansleep(motg-switch_gpio, 1);
+   }
+
schedule_work(motg-sm_work);

return NOTIFY_DONE;
@@ -1546,6 +1556,11 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)

motg-manual_pullup = of_property_read_bool(node, qcom,manual-pullup);

+   motg-switch_gpio = devm_gpiod_get_optional(pdev-dev, switch,
+   GPIOD_OUT_LOW);
+   if (IS_ERR(motg-switch_gpio))
+   return PTR_ERR(motg-switch_gpio);
+
ext_id = ERR_PTR(-ENODEV);
ext_vbus = ERR_PTR(-ENODEV);
if (of_property_read_bool(node, extcon)) {
@@ -1617,6 +1632,19 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)
return 0;
 }

+static int msm_otg_reboot_notify(struct notifier_block *this,
+unsigned long code, void *unused)
+{
+   struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
+
+   /*
+* Ensure that D+/D- lines are routed to uB connector, so
+* we could load bootloader/kernel at next reboot
+*/
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   return NOTIFY_DONE;
+}
+
 static int msm_otg_probe(struct platform_device *pdev)
 {
struct regulator_bulk_data regs[3];
@@ -1781,6 +1809,17 @@ static int msm_otg_probe(struct platform_device *pdev)
dev_dbg(pdev-dev, Can not create mode change 
file\n);
}

+   if (test_bit(B_SESS_VLD, motg-inputs)) {
+   /* Switch D+/D- lines to Device connector */
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   } else {
+   /* Switch D+/D- lines to Hub */
+   gpiod_set_value_cansleep(motg-switch_gpio, 1);
+   }
+
+   motg-reboot.notifier_call = msm_otg_reboot_notify;
+   register_reboot_notifier(motg-reboot);
+
pm_runtime_set_active(pdev-dev);
pm_runtime_enable(pdev-dev);

@@ -1807,6 +1846,14 @@ static int msm_otg_remove(struct platform_device *pdev)
if (phy-otg-host || phy-otg-gadget)
return -EBUSY;

+   unregister_reboot_notifier(motg-reboot);
+
+   /*
+* Ensure that D+/D- lines are routed to uB connector, so
+* we could load bootloader/kernel at next reboot
+*/
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+
extcon_unregister_notifier(motg-id.extcon, EXTCON_USB_HOST, 
motg-id.nb);
extcon_unregister_notifier(motg-vbus.extcon, EXTCON_USB, 
motg-vbus.nb);

diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 5df2c8f..8c8f685 100644

Re: [PATCH V4 2/7] qup: i2c: factor out common code for reuse

[Ivan T. Ivanov]

Hi Sricharan, 

On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
 

  static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
  {
 -   unsigned long left;
 -   int ret;
 +   int ret = 0;
 
 -   qup-msg = msg;
 -   qup-pos  = 0;
 +   /*
 +   * The QUP block will issue a NACK and STOP on the bus when 
 reaching
 +   * the end of the read, the length of the read is specified as 
 one byte
 +   * which limits the possible read to 256 (QUP_READ_LIMIT) 
 bytes.
 +   */
 +   if (msg-len  QUP_READ_LIMIT) {
 +   dev_err(qup-dev, HW not capable of reads over %d bytes\n,
 +   QUP_READ_LIMIT);
 +   return -EINVAL;
 +   }
 

This should be removed. Please see qup_i2c_quirks.

Regards,
Ivan
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Re: [PATCH V4 3/7] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
 QUP from version 2.1.1 onwards, supports a new format of
 i2c command tags. Tag codes instructs the controller to
 perform a operation like read/write. This new tagging version
 supports bam dma and transfers of more than 256 bytes without 'stop'
 in between. Adding the support for the same.

IIRC, more than 256 bytes in message is supported only in BAM(DMA)
mode, if this is true, please be more explicit in commit message.

You haven't tried to read more than 256 bytes with this
patch, right? See qup_i2c_quirks ;-) 

 
 
  struct qup_i2c_dev {
 struct device*dev;
 void __iomem*base;
 @@ -117,6 +138,7 @@ struct qup_i2c_dev {
 int in_blk_sz;
 
 unsigned longone_byte_t;
 +   struct qup_i2c_blockblk;
 
 struct i2c_msg*msg;
 /* Current posion in user message buffer */
 @@ -126,6 +148,14 @@ struct qup_i2c_dev {
 /* QUP core errors */
 u32 qup_err;
 
 +   int use_v2_tags;
 +
 +   int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg);
 +
 +   int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg);
 +

Do we really need additional level of indirection?

We have separate struct i2c_algorithm, then we have common 
qup_i2c_read/write methods and then we have different 
read/write sub functions. I don't think 3-4 lines code reuse
deserve increased complexity.

snip

 +static void qup_i2c_get_blk_data(struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg)
 +{

This is more like set_blk_metadata. Second argument could fit line above.

 +   memset(qup-blk, 0, sizeof(qup-blk));
 +
 +   if (!qup-use_v2_tags) {
 +   if (!(msg-flags  I2C_M_RD))
 +   qup-blk.tx_tag_len = 1;
 +   return;
 +   }
 +
 +   qup-blk.data_len = msg-len;
 +   qup-blk.count = (msg-len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
 +
 +   /* 4 bytes for first block and 2 writes for rest */
 +   qup-blk.tx_tag_len = 4 + (qup-blk.count - 1) * 2;
 +
 +   /* There are 2 tag bytes that are read in to fifo for every block */
 +   if (msg-flags  I2C_M_RD)
 +   qup-blk.rx_tag_len = qup-blk.count * 2;
 +}
 +

snip

 +static int qup_i2c_get_tags(u8 *tags, struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg)
 +{

This is more like set_tags.

 +   u16 addr = (msg-addr  1) | ((msg-flags  I2C_M_RD) == I2C_M_RD);
 +   int len = 0;
 +   int data_len;
 +
 +   if (qup-blk.pos == 0) {
 +   tags[len++] = QUP_TAG_V2_START;
 +   tags[len++] = addr  0xff;
 +
 +   if (msg-flags  I2C_M_TEN)
 +   tags[len++] = addr  8;
 +   }
 +
 +   /* Send _STOP commands for the last block */
 +   if (qup-blk.pos == (qup-blk.count - 1)) {
 +   if (msg-flags  I2C_M_RD)
 +   tags[len++] = QUP_TAG_V2_DATARD_STOP;
 +   else
 +   tags[len++] = QUP_TAG_V2_DATAWR_STOP;
 +   } else {
 +   if (msg-flags  I2C_M_RD)
 +   tags[len++] = QUP_TAG_V2_DATARD;
 +   else
 +   tags[len++] = QUP_TAG_V2_DATAWR;
 +   }
 +
 +   data_len = qup_i2c_get_data_len(qup);
 +
 +   /* 0 implies 256 bytes */
 +   if (data_len == QUP_READ_LIMIT)
 +   tags[len++] = 0;
 +   else
 +   tags[len++] = data_len;
 +
 +   return len;
 +}
 +

Regards,
Ivan

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Re: [PATCH V4 4/7] i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bit

[Ivan T. Ivanov]

Hi, 

On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:

snip

  #define ONE_BYTE   0x1
 +#define QUP_I2C_MX_CONFIG_DURING_RUN   BIT(31)
 
  struct qup_i2c_block {
 int count;
 @@ -121,6 +122,7 @@ struct qup_i2c_block {
 int rx_tag_len;
 int data_len;
 u8  tags[6];
 +   int config_run;

This is not directly related to block control logic, right?
Could it made part of qup_i2c_dev structure?

  };
 
  struct qup_i2c_dev {
 @@ -152,6 +154,10 @@ struct qup_i2c_dev {
 
 int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
 struct i2c_msg *msg);
 +   /* Current i2c_msg in i2c_msgs */
 +   int cmsg;
 +   /* total num of i2c_msgs */
 +   int num;

I think it will be simpler with just bool is_last evaluated in main xfer loop.

snip

 
 @@ -374,6 +383,9 @@ static void qup_i2c_get_blk_data(struct qup_i2c_dev *qup,
 /* There are 2 tag bytes that are read in to fifo for every block */
 if (msg-flags  I2C_M_RD)
 qup-blk.rx_tag_len = qup-blk.count * 2;
 +
 +   if (qup-cmsg)
 +   qup-blk.config_run = QUP_I2C_MX_CONFIG_DURING_RUN;

This could be moved to qup_i2c_xfer_v2() to avoid repeatedly setting it. 

  }

Regards,
Ivan
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Re: [PATCH V4 5/7] i2c: qup: Add bam dma capabilities

[Ivan T. Ivanov]

Hi Sricharan,

On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
 QUP cores can be attached to a BAM module, which acts as a dma engine for the
 QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data
 is written to the output FIFO and the BAM producer pipe received data is read
 from the input FIFO.
 
 With BAM capabilities, qup-i2c core can transfer more than 256 bytes, without 
 a
 'stop' which is not possible otherwise.
 
 Signed-off-by: Sricharan R sricha...@codeaurora.org
 ---
  drivers/i2c/busses/i2c-qup.c | 431 
 +--
  1 file changed, 415 insertions(+), 16 deletions(-)
 
 diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
 index c0757d9..810b021 100644
 --- a/drivers/i2c/busses/i2c-qup.c
 +++ b/drivers/i2c/busses/i2c-qup.c
 @@ -24,6 +24,11 @@
  #include linux/of.h
  #include linux/platform_device.h
  #include linux/pm_runtime.h
 +#include linux/dma-mapping.h
 +#include linux/scatterlist.h
 +#include linux/atomic.h
 +#include linux/dmaengine.h
 +#include linux/dmapool.h

Keep includes sorted alphabetically.

snip

 +#define MX_TX_RX_LEN   SZ_64K
 +#define MX_BLOCKS  (MX_TX_RX_LEN / QUP_READ_LIMIT)
 +
 +/* Max timeout in ms for 32k bytes */
 +#define TOUT_MAX   300
 +
  struct qup_i2c_block {
 int count;
 int pos;
 @@ -125,6 +143,23 @@ struct qup_i2c_block {
 int config_run;
  };
 
 +struct qup_i2c_tag {
 +   u8 *start;
 +   dma_addr_t addr;
 +};
 +
 +struct qup_i2c_bam_rx {
 +   struct  qup_i2c_tag scratch_tag;
 +   struct  dma_chan *dma_rx;
 +   struct  scatterlist *sg_rx;
 +};
 +
 +struct qup_i2c_bam_tx {
 +   struct  qup_i2c_tag footer_tag;
 +   struct  dma_chan *dma_tx;
 +   struct  scatterlist *sg_tx;
 +};
 +

The only difference between above 2 structures is name of the fields.
Please, just define one struct qup_i2c_bam and instantiate it twice.

  struct qup_i2c_dev {
 struct device*dev;
 void __iomem*base;
 @@ -154,14 +189,20 @@ struct qup_i2c_dev {
 
 int (*qup_i2c_write_one)(struct qup_i2c_dev *qup,
 struct i2c_msg *msg);
 +   int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg);
 +
 /* Current i2c_msg in i2c_msgs */
 int cmsg;
 /* total num of i2c_msgs */
 int num;
 
 -   int (*qup_i2c_read_one)(struct qup_i2c_dev *qup,
 -   struct i2c_msg *msg);
 -
 +   /* dma parameters */
 +   boolis_dma;
 +   struct  dma_pool *dpool;
 +   struct  qup_i2c_tag start_tag;
 +   struct  qup_i2c_bam_rx brx;
 +   struct  qup_i2c_bam_tx btx;
 struct completionxfer;
  };
 
 @@ -238,6 +279,14 @@ static int qup_i2c_poll_state(struct qup_i2c_dev *qup, 
 u32 req_state)
 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
  }
 
 +static void qup_i2c_flush(struct qup_i2c_dev *qup)
 +{
 +   u32 val = readl(qup-base + QUP_STATE);
 +
 +   val |= QUP_I2C_FLUSH;
 +   writel(val, qup-base + QUP_STATE);
 +}
 +

Used in only one place.

snip

 
 +static void qup_i2c_bam_cb(void *data)
 +{
 +   struct qup_i2c_dev *qup = data;
 +
 +   complete(qup-xfer);
 +}
 +
 +void qup_sg_set_buf(struct scatterlist *sg, void *buf, struct qup_i2c_tag 
 *tg,
 +   unsigned int buflen, struct 
 qup_i2c_dev *qup,
 +   int map, int dir)
 +{
 +   sg_set_buf(sg, buf, buflen);
 +   dma_map_sg(qup-dev, sg, 1, dir);
 +
 +   if (!map)
 +   sg_dma_address(sg) = tg-addr + ((u8 *)buf - tg-start);

Changing DMA address that we just mapped?

 +}
 +
 +static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
 +{
 +   if (qup-btx.dma_tx)
 +   dma_release_channel(qup-btx.dma_tx);
 +   if (qup-brx.dma_rx)
 +   dma_release_channel(qup-brx.dma_rx);
 +   qup-btx.dma_tx = NULL;
 +   qup-brx.dma_rx = NULL;
 +}
 +
 +static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
 +{
 +   if (!qup-btx.dma_tx) {
 +   qup-btx.dma_tx = dma_request_slave_channel(qup-dev, tx);

Please use dma_request_slave_channel_reason() and let deferred probe work.

 +   if (!qup-btx.dma_tx) {
 +   dev_err(qup-dev, \n tx channel not available);
 +   return -ENODEV;
 +   }
 +   }
 +
 +   if (!qup-brx.dma_rx) {
 +   qup-brx.dma_rx = dma_request_slave_channel(qup-dev, rx);
 +   if (!qup-brx.dma_rx) {
 +   dev_err(qup-dev, \n rx channel not available);
 +   qup_i2c_rel_dma(qup);
 +   return -ENODEV;
 +   }
 +   }
 +   return 0;
 +}
 +
 +static int bam_do_xfer(struct qup_i2c_dev *qup, struct 

[PATCH] usb: phy: msm: Add D+/D- lines route control

[Ivan T. Ivanov]

apq8016-sbc board is using Dual SPDT USB Switch (TC7USB40MU),
witch is controlled by GPIO to de/multiplex D+/D- USB lines to
USB2513B Hub and uB connector. Add support for this.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt  |  4 ++
 drivers/usb/phy/phy-msm-usb.c  | 47 ++
 include/linux/usb/msm_hsusb.h  |  7 
 3 files changed, 58 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index bd8d9e7..8654a3e 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -52,6 +52,10 @@ Required properties:
 Optional properties:
 - dr_mode:  One of host, peripheral or otg. Defaults to otg

+- switch-gpio:  A phandle + gpio-specifier pair. Some boards are using Dual
+SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
+D+/D- USB lines between connectors.
+
 - qcom,phy-init-sequence: PHY configuration sequence values. This is related 
to Device
 Mode Eye Diagram test. Start address at which these values 
will be
 written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 00c49bb..57c75fb 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -18,6 +18,7 @@

 #include linux/module.h
 #include linux/device.h
+#include linux/gpio/consumer.h
 #include linux/platform_device.h
 #include linux/clk.h
 #include linux/slab.h
@@ -32,6 +33,7 @@
 #include linux/pm_runtime.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/reboot.h
 #include linux/reset.h

 #include linux/usb.h
@@ -1471,6 +1473,14 @@ static int msm_otg_vbus_notifier(struct notifier_block 
*nb, unsigned long event,
else
clear_bit(B_SESS_VLD, motg-inputs);

+   if (test_bit(B_SESS_VLD, motg-inputs)) {
+   /* Switch D+/D- lines to Device connector */
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   } else {
+   /* Switch D+/D- lines to Hub */
+   gpiod_set_value_cansleep(motg-switch_gpio, 1);
+   }
+
schedule_work(motg-sm_work);

return NOTIFY_DONE;
@@ -1546,6 +1556,11 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)

motg-manual_pullup = of_property_read_bool(node, qcom,manual-pullup);

+   motg-switch_gpio = devm_gpiod_get_optional(pdev-dev, switch,
+   GPIOD_OUT_LOW);
+   if (IS_ERR(motg-switch_gpio))
+   return PTR_ERR(motg-switch_gpio);
+
ext_id = ERR_PTR(-ENODEV);
ext_vbus = ERR_PTR(-ENODEV);
if (of_property_read_bool(node, extcon)) {
@@ -1615,6 +1630,19 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)
return 0;
 }

+static int msm_otg_reboot_notify(struct notifier_block *this,
+unsigned long code, void *unused)
+{
+   struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
+
+   /*
+* Ensure that D+/D- lines are routed to uB connector, so
+* we could load bootloader/kernel at next reboot
+*/
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   return NOTIFY_DONE;
+}
+
 static int msm_otg_probe(struct platform_device *pdev)
 {
struct regulator_bulk_data regs[3];
@@ -1779,6 +1807,17 @@ static int msm_otg_probe(struct platform_device *pdev)
dev_dbg(pdev-dev, Can not create mode change 
file\n);
}

+   if (test_bit(B_SESS_VLD, motg-inputs)) {
+   /* Switch D+/D- lines to Device connector */
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+   } else {
+   /* Switch D+/D- lines to Hub */
+   gpiod_set_value_cansleep(motg-switch_gpio, 1);
+   }
+
+   motg-reboot.notifier_call = msm_otg_reboot_notify;
+   register_reboot_notifier(motg-reboot);
+
pm_runtime_set_active(pdev-dev);
pm_runtime_enable(pdev-dev);

@@ -1805,11 +1844,19 @@ static int msm_otg_remove(struct platform_device *pdev)
if (phy-otg-host || phy-otg-gadget)
return -EBUSY;

+   unregister_reboot_notifier(motg-reboot);
+
if (motg-id.conn.edev)
extcon_unregister_interest(motg-id.conn);
if (motg-vbus.conn.edev)
extcon_unregister_interest(motg-vbus.conn);

+   /*
+* Ensure that D+/D- lines are routed to uB connector, so
+* we could load bootloader/kernel at next reboot
+*/
+   gpiod_set_value_cansleep(motg-switch_gpio, 0);
+
msm_otg_debugfs_cleanup();
cancel_delayed_work_sync(motg-chg_work);
cancel_work_sync(motg-sm_work

[PATCH] usb: phy: qcom: New APQ8016/MSM8916 USB transceiver driver

[Ivan T. Ivanov]

Driver handles PHY initialization, clock management, power
management and workarounds required after resetting the hardware.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../devicetree/bindings/usb/qcom,usb-8x16-phy.txt  |  76 
 drivers/usb/phy/Kconfig|  14 +
 drivers/usb/phy/Makefile   |   1 +
 drivers/usb/phy/phy-qcom-8x16-usb.c| 436 +
 4 files changed, 527 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-8x16-phy.txt
 create mode 100644 drivers/usb/phy/phy-qcom-8x16-usb.c

diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-8x16-phy.txt 
b/Documentation/devicetree/bindings/usb/qcom,usb-8x16-phy.txt
new file mode 100644
index 000..2cb2168
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,usb-8x16-phy.txt
@@ -0,0 +1,76 @@
+Qualcomm's APQ8016/MSM8916 USB transceiver controller
+
+- compatible:
+Usage: required
+Value type: string
+Definition: Should contain qcom,usb-8x16-phy.
+
+- reg:
+Usage: required
+Value type: prop-encoded-array
+Definition: USB PHY base address and length of the register map
+
+- clocks:
+Usage: required
+Value type: prop-encoded-array
+Definition: See clock-bindings.txt section consumers. List of
+two clock specifiers for interface and core controller
+clocks.
+
+- clock-names:
+Usage: required
+Value type: string
+Definition: Must contain iface and core strings.
+
+- vddcx-supply:
+Usage: required
+Value type: phandle
+Definition: phandle to the regulator VDCCX supply node.
+
+- v1p8-supply:
+Usage: required
+Value type: phandle
+Definition: phandle to the regulator 1.8V supply node.
+
+- v3p3-supply:
+Usage: required
+Value type: phandle
+Definition: phandle to the regulator 3.3V supply node.
+
+- resets:
+Usage: required
+Value type: prop-encoded-array
+Definition: See reset.txt section consumers. PHY reset specifier.
+
+- reset-names:
+Usage: required
+Value type: string
+Definition: Must contain phy string.
+
+- switch-gpio:
+Usage: optional
+Value type: prop-encoded-array
+Definition: Some boards are using Dual SPDT USB Switch, witch is
+controlled by GPIO to de/multiplex D+/D- USB lines
+between connectors.
+
+Example:
+   usb_phy: phy@78d9000 {
+   compatible = qcom,usb-8x16-phy;
+   reg = 0x78d9000 0x400;
+
+   vddcx-supply = pm8916_s1_corner;
+   v1p8-supply = pm8916_l7;
+   v3p3-supply = pm8916_l13;
+
+   clocks = gcc GCC_USB_HS_AHB_CLK,
+gcc GCC_USB_HS_SYSTEM_CLK;
+   clock-names = iface, core;
+
+   resets = gcc GCC_USB2A_PHY_BCR;
+   reset-names = phy;
+
+   // D+/D- lines: 1 - Routed to HUB, 0 - Device connector
+   switch-gpio = pm8916_gpios 4 GPIO_ACTIVE_HIGH;
+   };
+
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 869c0cfcad..7d3beee 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -152,6 +152,20 @@ config USB_MSM_OTG
  This driver is not supported on boards like trout which
  has an external PHY.

+config USB_QCOM_8X16_PHY
+   tristate Qualcomm APQ8016/MSM8916 on-chip USB PHY controller support
+   depends on ARCH_QCOM || COMPILE_TEST
+   depends on RESET_CONTROLLER
+   select USB_PHY
+   select USB_ULPI_VIEWPORT
+   help
+ Enable this to support the USB transceiver on Qualcomm 8x16 chipsets.
+ It handles PHY initialization, clock management, power management,
+ and workarounds required after resetting the hardware.
+
+ To compile this driver as a module, choose M here: the
+ module will be called phy-qcom-8x16-usb.
+
 config USB_MV_OTG
tristate Marvell USB OTG support
depends on USB_EHCI_MV  USB_MV_UDC  PM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index e36ab1d..19c0dcc 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA)  += phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
 obj-$(CONFIG_USB_ISP1301)  += phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)  += phy-msm-usb.o
+obj-$(CONFIG_USB_QCOM_8X16_PHY)+= phy-qcom-8x16-usb.o
 obj-$(CONFIG_USB_MV_OTG)   += phy-mv-usb.o
 obj-$(CONFIG_USB_MXS_PHY)  += phy-mxs-usb.o
 obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-qcom-8x16-usb.c 
b/drivers/usb/phy/phy-qcom-8x16-usb.c
new file mode 100644
index 000..5d357a9
--- /dev/null
+++ b/drivers/usb/phy/phy-qcom-8x16-usb.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ *
+ * This program is free software

Re: [PATCH 5/8] pinctrl: qcom: spmi-mpp: Add support for setting analog output level

[Ivan T. Ivanov]

Hi Bjorn, 

On Wed, 2015-06-17 at 23:47 -0700, Bjorn Andersson wrote:
 When the MPP is configured for analog output the output level is selected by
 the AOUT_CTL register, this patch makes it possible to control this.
 
snip

 }
 @@ -748,6 +765,10 @@ static int pmic_mpp_populate(struct pmic_mpp_state 
 *state,
 
 pad-drive_strength = val;
 
 +   val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
 +   if (val  0)
 +   return val;
 +

Missing 

pad-aout_level = val;

 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
 if (val  0)
 return val;
 

Regards,
Ivan
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Re: [PATCH 0/8] Qualcomm PMIC pinctrl additions

[Ivan T. Ivanov]

On Wed, 2015-06-17 at 23:47 -0700, Bjorn Andersson wrote:
 This series starts out by fixing various issues found in the pm8941 mpp 
 driver.
 While doing this work, and trying to use the mpp driver from device tree it, 
 it
 became obvious that the current binding is not fit for neither the driver
 implementation nor the dts implementation.
 
 The main reason for this is that we inherited the functions from the gpio
 driver, where there is a notion of functions. But in the MPP the logical
 mapping of digital, analog and current sink makes much more sense to map as
 functions. The features previously exposed as functions are replaced by two
 properties (qcom,paired and qcom,dtest).
 
 The end result is a more natural device tree definition.
 
 With this in place the series introduces the gpio and mpp drivers for the ssbi
 based pmics; found in 8660, 8960 and 8064.
 
 Bjorn Andersson (8):
   pinctrl: qcom: spmi-mpp: Transition to generic dt binding parser
   pinctrl: qcom: spmi-mpp: Fixes related to enable handling
   pinctrl: qcom: spmi-mpp: Introduce defines for MODE_CTL
   pinctrl: qcom: spmi-mpp: Implement support for sink mode
   pinctrl: qcom: spmi-mpp: Add support for setting analog output level
   pinctrl: qcom: spmi-mpp: Transpose pinmux function
   mfd: pm8921: Implement irq_get_irqchip_state
   pinctrl: qcom: ssbi: Family A gpio  mpp drivers

Thank you Bjorn.

Now MPP drivers have its full functionality.

With two small comments on patch 5 and 8,

Reviewed-by: Ivan T. Ivanov iiva...@mm-sol.com
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[PATCH 0/7] arm64: dts: qcom: msm8916 fixes and updates

[Ivan T. Ivanov]

Following patches add configuration nodes for SPI, I2C, USB and SDHC devices
found in msm8916 and related pinctrl definitions. Also several GPIO have been
incorrectly assigned and are fixed now. LED control devices for apq 8016-sbc
board are added.

Regards,
Ivan

Ivan T. Ivanov (6):
  arm64: dts: qcom: Extend msm8916 pinctrl device coverage
  arm64: dts: qcom: Add msm8916 BLSP device nodes
  arm64: dts: qcom: Add msm8916 USB configuration nodes
  arm64: dts: qcom: apq8016-sbc: Don't hog client driver pins
  arm64: dts: qcom: Fix apq8016-sbc board USB related pin definitions
  arm64: dts: qcom: Add apq8016-sbc board LED's related device nodes

Srinivas Kandagatla (1):
  arm64: dts: qcom: Add msm8916 sdhci configuration nodes

 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi |  34 +-
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi |  14 +-
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |  51 +++
 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 430 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  | 227 +--
 5 files changed, 708 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi

--
1.9.1

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[PATCH 1/7] arm64: dts: qcom: Extend msm8916 pinctrl device coverage

[Ivan T. Ivanov]

Create separate file for MSM8916 pinctrl default/sleep pins state
definitions. Move in UART2 states and add SPI, I2C and SDC configurations.

Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 430 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  26 +-
 2 files changed, 432 insertions(+), 24 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi

diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
new file mode 100644
index 000..5689568
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -0,0 +1,430 @@
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+msmgpio {
+
+   blsp1_uart2_default: blsp1_uart2_default {
+   pinmux {
+   function = blsp_uart2;
+   pins = gpio4, gpio5;
+   };
+   pinconf {
+   pins = gpio4, gpio5;
+   drive-strength = 16;
+   bias-disable;
+   };
+   };
+
+   blsp1_uart2_sleep: blsp1_uart2_sleep {
+   pinmux {
+   function = blsp_uart2;
+   pins = gpio4, gpio5;
+   };
+   pinconf {
+   pins = gpio4, gpio5;
+   drive-strength = 2;
+   bias-pull-down;
+   };
+   };
+
+   spi1_default: spi1_default {
+   pinmux {
+   function = blsp_spi1;
+   pins = gpio0, gpio1, gpio3;
+   };
+   pinmux_cs {
+   function = gpio;
+   pins = gpio2;
+   };
+   pinconf {
+   pins = gpio0, gpio1, gpio3;
+   drive-strength = 12;
+   bias-disable;
+   };
+   pinconf_cs {
+   pins = gpio2;
+   drive-strength = 2;
+   bias-disable;
+   output-high;
+   };
+   };
+
+   spi1_sleep: spi1_sleep {
+   pinmux {
+   function = gpio;
+   pins = gpio0, gpio1, gpio2, gpio3;
+   };
+   pinconf {
+   pins = gpio0, gpio1, gpio2, gpio3;
+   drive-strength = 2;
+   bias-pull-down;
+   };
+   };
+
+   spi2_default: spi2_default {
+   pinmux {
+   function = blsp_spi2;
+   pins = gpio4, gpio5, gpio7;
+   };
+   pinmux_cs {
+   function = gpio;
+   pins = gpio6;
+   };
+   pinconf {
+   pins = gpio4, gpio5, gpio6, gpio7;
+   drive-strength = 12;
+   bias-disable;
+   };
+   pinconf_cs {
+   pins = gpio6;
+   drive-strength = 2;
+   bias-disable;
+   output-high;
+   };
+   };
+
+   spi2_sleep: spi2_sleep {
+   pinmux {
+   function = gpio;
+   pins = gpio4, gpio5, gpio6, gpio7;
+   };
+   pinconf {
+   pins = gpio4, gpio5, gpio6, gpio7;
+   drive-strength = 2;
+   bias-pull-down;
+   };
+   };
+
+   spi3_default: spi3_default {
+   pinmux {
+   function = blsp_spi3;
+   pins = gpio8, gpio9, gpio11;
+   };
+   pinmux_cs {
+   function = gpio;
+   pins = gpio10;
+   };
+   pinconf {
+   pins = gpio8, gpio9, gpio10, gpio11;
+   drive-strength = 12;
+   bias-disable;
+   };
+   pinconf_cs {
+   pins = gpio10;
+   drive-strength = 2;
+   bias-disable;
+   output-high

[PATCH 5/7] arm64: dts: qcom: apq8016-sbc: Don't hog client driver pins

[Ivan T. Ivanov]

Hogging pins from pinctrl driver prevents client drivers
to probe.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 3 ---
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi  | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index 535532b..37ca2ed 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -2,9 +2,6 @@

 pm8916_gpios {

-   pinctrl-names = default;
-   pinctrl-0 = pm8916_gpios_default;
-
pm8916_gpios_default: default {
usb_hub_reset_pm {
pins = gpio1;
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index 5f7023f..27087cf 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -3,9 +3,6 @@

 msmgpio {

-   pinctrl-names = default;
-   pinctrl-0 = soc_gpios_default;
-
soc_gpios_default: default {
usr_led_1_ctrl_default: usr_led_1_ctrl_default {
pins = gpio21;
--
1.9.1

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[PATCH 6/7] arm64: dts: qcom: Fix apq8016-sbc board USB related pin definitions

[Ivan T. Ivanov]

USB2513B HUB reset line is connected to PMIC GPIO3 not GPIO1.

Fix TC7USB40MU Dual SPDT Switch select input line control, which is
connected to PMIC GPIO4 not GPIO2 and disable the pin. It is not used
for now.

Remove user LEDs definitions, because they clash with above numbers.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 22 --
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index 37ca2ed..b568c49 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -2,26 +2,20 @@

 pm8916_gpios {

-   pm8916_gpios_default: default {
-   usb_hub_reset_pm {
-   pins = gpio1;
-   function = PMIC_GPIO_FUNC_NORMAL;
-   output-low;
-   };
-   usb_sw_sel_pm {
-   pins = gpio2;
-   function = PMIC_GPIO_FUNC_NORMAL;
-   input-disable;
-   };
-   usr_led_3_ctrl {
+   usb_hub_reset_pm: usb_hub_reset_pm {
+   pinconf {
pins = gpio3;
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
-   usr_led_4_ctrl {
+   };
+
+   usb_sw_sel_pm: usb_sw_sel_pm {
+   pinconf {
pins = gpio4;
function = PMIC_GPIO_FUNC_NORMAL;
-   output-low;
+   power-source = PM8916_GPIO_VPH;
+   input-disable;
};
};
 };
--
1.9.1

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[PATCH 3/7] arm64: dts: qcom: Add msm8916 sdhci configuration nodes

[Ivan T. Ivanov]

From: Srinivas Kandagatla srinivas.kandaga...@linaro.org

Add sdhci1 and sdhci2 device configuration nodes.

Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 6681c65..9ff0eb4 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -24,7 +24,10 @@
#address-cells = 2;
#size-cells = 2;

-   aliases { };
+   aliases {
+   sdhc1 = sdhc_1; /* SDC1 eMMC slot */
+   sdhc2 = sdhc_2; /* SDC2 SD card slot */
+   };

chosen { };

@@ -236,6 +239,35 @@
status = disabled;
};

+   sdhc_1: sdhci@07824000 {
+   compatible = qcom,sdhci-msm-v4;
+   reg = 0x07824900 0x11c, 0x07824000 0x800;
+   reg-names = hc_mem, core_mem;
+
+   interrupts = 0 123 0, 0 138 0;
+   interrupt-names = hc_irq, pwr_irq;
+   clocks = gcc GCC_SDCC1_APPS_CLK,
+gcc GCC_SDCC1_AHB_CLK;
+   clock-names = core, iface;
+   bus-width = 8;
+   non-removable;
+   status = disabled;
+   };
+
+   sdhc_2: sdhci@07864000 {
+   compatible = qcom,sdhci-msm-v4;
+   reg = 0x07864900 0x11c, 0x07864000 0x800;
+   reg-names = hc_mem, core_mem;
+
+   interrupts = 0 125 0, 0 221 0;
+   interrupt-names = hc_irq, pwr_irq;
+   clocks = gcc GCC_SDCC2_APPS_CLK,
+gcc GCC_SDCC2_AHB_CLK;
+   clock-names = core, iface;
+   bus-width = 4;
+   status = disabled;
+   };
+
intc: interrupt-controller@b00 {
compatible = qcom,msm-qgic2;
interrupt-controller;
--
1.9.1

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[PATCH 2/7] arm64: dts: qcom: Add msm8916 BLSP device nodes

[Ivan T. Ivanov]

Add device nodes for SPI1, SPI2, SPI3, I2C4, SPI5, SPI6 and
BAM(DMA) engine connected to them.

Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 128 ++
 1 file changed, 128 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9ab9a92..6681c65 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -108,6 +108,134 @@
status = disabled;
};

+   blsp_dma: dma@7884000 {
+   compatible = qcom,bam-v1.7.0;
+   reg = 0x07884000 0x23000;
+   interrupts = GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_AHB_CLK;
+   clock-names = bam_clk;
+   #dma-cells = 1;
+   qcom,ee = 0;
+   status = disabled;
+   };
+
+   blsp_spi1: spi@78b5000 {
+   compatible = qcom,spi-qup-v2.2.1;
+   reg = 0x078b5000 0x600;
+   interrupts = GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_QUP1_SPI_APPS_CLK,
+gcc GCC_BLSP1_AHB_CLK;
+   clock-names = core, iface;
+   dmas = blsp_dma 5, blsp_dma 4;
+   dma-names = rx, tx;
+   pinctrl-names = default, sleep;
+   pinctrl-0 = spi1_default;
+   pinctrl-1 = spi1_sleep;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   blsp_spi2: spi@78b6000 {
+   compatible = qcom,spi-qup-v2.2.1;
+   reg = 0x078b6000 0x600;
+   interrupts = GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_QUP2_SPI_APPS_CLK,
+gcc GCC_BLSP1_AHB_CLK;
+   clock-names = core, iface;
+   dmas = blsp_dma 7, blsp_dma 6;
+   dma-names = rx, tx;
+   pinctrl-names = default, sleep;
+   pinctrl-0 = spi2_default;
+   pinctrl-1 = spi2_sleep;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   blsp_spi3: spi@78b7000 {
+   compatible = qcom,spi-qup-v2.2.1;
+   reg = 0x078b7000 0x600;
+   interrupts = GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_QUP3_SPI_APPS_CLK,
+gcc GCC_BLSP1_AHB_CLK;
+   clock-names = core, iface;
+   dmas = blsp_dma 9, blsp_dma 8;
+   dma-names = rx, tx;
+   pinctrl-names = default, sleep;
+   pinctrl-0 = spi3_default;
+   pinctrl-1 = spi3_sleep;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   blsp_spi4: spi@78b8000 {
+   compatible = qcom,spi-qup-v2.2.1;
+   reg = 0x078b8000 0x600;
+   interrupts = GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_QUP4_SPI_APPS_CLK,
+gcc GCC_BLSP1_AHB_CLK;
+   clock-names = core, iface;
+   dmas = blsp_dma 11, blsp_dma 10;
+   dma-names = rx, tx;
+   pinctrl-names = default, sleep;
+   pinctrl-0 = spi4_default;
+   pinctrl-1 = spi4_sleep;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   blsp_spi5: spi@78b9000 {
+   compatible = qcom,spi-qup-v2.2.1;
+   reg = 0x078b9000 0x600;
+   interrupts = GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH;
+   clocks = gcc GCC_BLSP1_QUP5_SPI_APPS_CLK,
+gcc GCC_BLSP1_AHB_CLK;
+   clock-names = core, iface;
+   dmas = blsp_dma 13, blsp_dma 12;
+   dma-names = rx, tx;
+   pinctrl-names = default, sleep;
+   pinctrl-0 = spi5_default;
+   pinctrl-1 = spi5_sleep;
+   #address-cells = 1;
+   #size-cells = 0

[PATCH 7/7] arm64: dts: qcom: Add apq8016-sbc board LED's related device nodes

[Ivan T. Ivanov]

APQ8016 SBC board have 6 user controllable LED's.

Add following devices:

LED1 green LED triggered by system heartbeat.
LED2 green LED triggered by access to eMMC device.
LED3 green LED triggered by access to SD card.
LED4 green LED no trigger assigned.
LED5 yellow LED triggered by access to WLAN.
LED6 blue LED triggered by access to Bluetooth.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 19 
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 11 ++---
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  | 51 ++
 3 files changed, 73 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index b568c49..e03c11d 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -18,4 +18,23 @@
input-disable;
};
};
+
+   pm8916_gpios_leds: pm8916_gpios_leds {
+   pinconf {
+   pins = gpio1, gpio2;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   };
+};
+
+pm8916_mpps {
+
+   pm8916_mpps_leds: pm8916_mpps_leds {
+   pinconf {
+   pins = mpp2, mpp3;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   };
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index 27087cf..cbeee0b 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -3,14 +3,9 @@

 msmgpio {

-   soc_gpios_default: default {
-   usr_led_1_ctrl_default: usr_led_1_ctrl_default {
-   pins = gpio21;
-   function = gpio;
-   output-low;
-   };
-   usr_led_2_ctrl_default: usr_led_2_ctrl_default {
-   pins = gpio120;
+   msmgpio_leds: msmgpio_leds {
+   pinconf {
+   pins = gpio21, gpio120;
function = gpio;
output-low;
};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 98abece..66804ff 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -32,5 +32,56 @@
pinctrl-0 = blsp1_uart2_default;
pinctrl-1 = blsp1_uart2_sleep;
};
+
+   leds {
+   pinctrl-names = default;
+   pinctrl-0 = msmgpio_leds,
+   pm8916_gpios_leds,
+   pm8916_mpps_leds;
+
+   compatible = gpio-leds;
+
+   led@1 {
+   label = apq8016-sbc:green:user1;
+   gpios = msmgpio 21 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = heartbeat;
+   default-state = off;
+   };
+
+   led@2 {
+   label = apq8016-sbc:green:user2;
+   gpios = msmgpio 120 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = mmc0;
+   default-state = off;
+   };
+
+   led@3 {
+   label = apq8016-sbc:green:user3;
+   gpios = pm8916_gpios 1 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = mmc1;
+   default-state = off;
+   };
+
+   led@4 {
+   label = apq8016-sbc:green:user4;
+   gpios = pm8916_gpios 2 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = none;
+   default-state = off;
+   };
+
+   led@5 {
+   label = apq8016-sbc:yellow:wlan;
+   gpios = pm8916_mpps 2 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = wlan;
+   default-state = off;
+   };
+
+   led@6 {
+   label = apq8016-sbc:blue:bt;
+   gpios = pm8916_mpps 3 GPIO_ACTIVE_HIGH;
+   linux,default-trigger = bt;
+   default-state = off;
+   };
+   };
};
 };
--
1.9.1

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[PATCH 4/7] arm64: dts: qcom: Add msm8916 USB configuration nodes

[Ivan T. Ivanov]

Add Host, Device and OTG configuration nodes.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9ff0eb4..5911de0 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -268,6 +268,45 @@
status = disabled;
};

+   usb_dev: usb@78d9000 {
+   compatible = qcom,ci-hdrc;
+   reg = 0x78d9000 0x400;
+   dr_mode = peripheral;
+   interrupts = GIC_SPI 134 IRQ_TYPE_NONE;
+   usb-phy = usb_otg;
+   status = disabled;
+   };
+
+   usb_host: ehci@78d9000 {
+   compatible = qcom,ehci-host;
+   reg = 0x78d9000 0x400;
+   interrupts = GIC_SPI 134 IRQ_TYPE_NONE;
+   usb-phy = usb_otg;
+   status = disabled;
+   };
+
+   usb_otg: phy@78d9000 {
+   compatible = qcom,usb-otg-snps;
+   reg = 0x78d9000 0x400;
+   interrupts = GIC_SPI 134 IRQ_TYPE_EDGE_BOTH,
+GIC_SPI 140 IRQ_TYPE_EDGE_RISING;
+
+   qcom,vdd-levels = 1 5 7;
+   qcom,phy-init-sequence = 0x44 0x6B 0x24 0x13;
+   dr_mode = peripheral;
+   qcom,otg-control = 2; // PMIC
+
+   clocks = gcc GCC_USB_HS_AHB_CLK,
+gcc GCC_USB_HS_SYSTEM_CLK,
+gcc GCC_USB2A_PHY_SLEEP_CLK;
+   clock-names = iface, core, sleep;
+
+   resets = gcc GCC_USB2A_PHY_BCR,
+gcc GCC_USB_HS_BCR;
+   reset-names = phy, link;
+   status = disabled;
+   };
+
intc: interrupt-controller@b00 {
compatible = qcom,msm-qgic2;
interrupt-controller;
--
1.9.1

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Re: [PATCH v3 4/6] dt-bindings: Consolidate ChipIdea USB ci13xxx bindings

[Ivan T. Ivanov]

On Fri, 2015-05-29 at 11:38 -0500, Rob Herring wrote:
 Combine the ChipIdea USB binding into a single document to reduce
 duplication and fragmentation. This marks use of the old PHY bindings as
 deprecated. Future compatible bindings should use generic PHY binding.
 
 Signed-off-by: Rob Herring r...@kernel.org
 Cc: Ivan T. Ivanov iiva...@mm-sol.com
 Cc: Peter Chen c...@freescale.com
 Cc: Daniel Tang ta...@gmail.com
 Cc: Pawel Moll m...@arm.com
 Cc: Mark Rutland rutl...@arm.com
 Cc: Ian Campbell ijc+devicet...@hellion.org.uk
 Cc: Kumar Gala ga...@codeaurora.org
 Cc: devicetree@vger.kernel.org
 ---
  .../devicetree/bindings/usb/ci-hdrc-imx.txt| 35 
 --
  .../devicetree/bindings/usb/ci-hdrc-qcom.txt   | 17 ---
  .../devicetree/bindings/usb/ci-hdrc-usb2.txt   | 22 +-
  .../devicetree/bindings/usb/ci-hdrc-zevio.txt  | 17 ---
  4 files changed, 21 insertions(+), 70 deletions(-)
  delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
  delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
  delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt

Thanks. For Qualcomm part:

Acked-by: Ivan T. Ivanov iiva...@mm-sol.com
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Re: [PATCH v2] usb: chipidea: Use extcon framework for VBUS and ID detect

[Ivan T. Ivanov]

On Wed, 2015-04-15 at 16:35 +0300, Ivan T. Ivanov wrote:
 On recent Qualcomm platforms VBUS and ID lines are not routed to
 USB PHY LINK controller. Use extcon framework to receive connect
 and disconnect ID and VBUS notification.
 
 Signed-off-by: Ivan T. Ivanov iva...@linaro.org
 ---
 
 Changes since v0 [1], as per Peter Chen suggestions:
 
 * Moved external connector parsing code to ci_get_platdata()
 * Moved external connector related variables to struct ci_hdrc_platform_data
 * Rename ci_host_notifier() to ci_id_notifier()
 * Fixed device bindings description
 * Use select EXTCON framework, instead of depends on.
 
 [1] https://lkml.org/lkml/2015/4/9/116

Hi Peter, 

Did you have any further comments on this patch
or what is your plan about it.

Regards,
Ivan
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[PATCH v2 0/2] Add initial CoreSight support for the Qualcomm 8x16 chipsets

[Ivan T. Ivanov]

Add initial CoreSight support for the Qualcomm 8x16 chipsets

This patch series add initial set of CoreSight components for the
8x16 chipsets.

Components will not be functional, because of missing clock controller
driver, which is under internal testing.

Patches are based on Enable CoreSight for the Ux500 [1] and
Support for coresight ETMv4 tracer [2]

Changes since first version [3]:

* Added comments about not described funnels ports in DT files.
* Removed MODULE_ macros.
* Print replicator version at probe time.
* Fixed Kconfig driver description.
* Added 1x suffix to compatible string, to reflect supported replicator 
version
* Add comment how replicator output port is disabled.

[1] http://www.spinics.net/lists/arm-kernel/msg412873.html
[2] https://lwn.net/Articles/641585/
[3] https://lkml.org/lkml/2015/4/29/241

Ivan T. Ivanov (1):
  arm64: dts: qcom: Add msm8916 CoreSight components

Pratik Patel (1):
  coresight: replicator: Add Qualcomm CoreSight Replicator driver

 .../devicetree/bindings/arm/coresight.txt  |   1 +
 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi| 254 +
 drivers/hwtracing/coresight/Kconfig|   8 +
 drivers/hwtracing/coresight/Makefile   |   1 +
 .../coresight/coresight-replicator-qcom.c  | 214 +
 5 files changed, 478 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
 create mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c

--
1.9.1

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Re: [PATCH 1/2] usb: phy: msm: Use extcon framework for VBUS and ID detection

[Ivan T. Ivanov]

On Thu, 2015-04-09 at 11:34 +0300, Ivan T. Ivanov wrote:
 On recent Qualcomm platforms VBUS and ID lines are not routed to
 USB PHY LINK controller. Use extcon framework to receive connect
 and disconnect ID and VBUS notification.
 
 Signed-off-by: Ivan T. Ivanov iva...@linaro.org

Hi Felipe,

Did you have any comments on this and/or following patches?

Regards,
Ivan
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[PATCH v2 4/7] arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916

[Ivan T. Ivanov]

Add SPMI PMIC Arbiter configuration nodes for MSM8916.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index f212b83..92c96eb 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -192,5 +192,23 @@
status = disabled;
};
};
+
+   spmi_bus: spmi@200f000 {
+   compatible = qcom,spmi-pmic-arb;
+   reg = 0x200f000 0x001000,
+ 0x240 0x40,
+ 0x2c0 0x40,
+ 0x380 0x20,
+ 0x200a000 0x002100;
+   reg-names = core, chnls, obsrvr, intr, cnfg;
+   interrupt-names = periph_irq;
+   interrupts = GIC_SPI 190 IRQ_TYPE_NONE;
+   qcom,ee = 0;
+   qcom,channel = 0;
+   #address-cells = 2;
+   #size-cells = 0;
+   interrupt-controller;
+   #interrupt-cells = 4;
+   };
};
 };
--
1.9.1

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[PATCH v2 5/7] arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PM9816 has 2 SPMI devices per physical package. Add PMIC configuration
nodes including sub-function device nodes and include them in boards,
which are using 8x16 based chipset.

PM9816 sub-function devices include:

* GPIO block, with 4 pins
* MPP block, with 4 pins
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature.
* Power key device, which is responsible for clean system
  reboot or shutdown
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi |  1 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi |  1 +
 arch/arm64/boot/dts/qcom/pm8916.dtsi  | 99 +++
 3 files changed, 101 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 703a4f1..58f0055f 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -12,6 +12,7 @@
  */

 #include msm8916.dtsi
+#include pm8916.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index bea871b..a1aa0b2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -12,6 +12,7 @@
  */

 #include msm8916.dtsi
+#include pm8916.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi 
b/arch/arm64/boot/dts/qcom/pm8916.dtsi
new file mode 100644
index 000..b222ece
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -0,0 +1,99 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+   usid0: pm8916@0 {
+   compatible = qcom,spmi-pmic;
+   reg = 0x0 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x6100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pwrkey@800 {
+   compatible = qcom,pm8941-pwrkey;
+   reg = 0x800;
+   interrupts = 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH;
+   debounce = 15625;
+   bias-pull-up;
+   };
+
+   pm8916_gpios: gpios@c000 {
+   compatible = qcom,pm8916-gpio;
+   reg = 0xc000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 IRQ_TYPE_NONE,
+0 0xc1 0 IRQ_TYPE_NONE,
+0 0xc2 0 IRQ_TYPE_NONE,
+0 0xc3 0 IRQ_TYPE_NONE;
+   };
+
+   pm8916_mpps: mpps@a000 {
+   compatible = qcom,pm8916-mpp;
+   reg = 0xa000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 IRQ_TYPE_NONE,
+0 0xa1 0 IRQ_TYPE_NONE,
+0 0xa2 0 IRQ_TYPE_NONE,
+0 0xa3 0 IRQ_TYPE_NONE;
+   };
+
+   pm8916_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+   io-channels = pm8916_vadc VADC_DIE_TEMP;
+   io-channel-names = thermal;
+   #thermal-sensor-cells = 0;
+   };
+
+   pm8916_vadc: vadc@3100 {
+   compatible = qcom,spmi-vadc;
+   reg = 0x3100 0x100;
+   interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+   #address-cells = 1;
+   #size-cells = 0;
+   #io-channel-cells = 1;
+
+   usb_in {
+   reg = VADC_USBIN;
+   qcom,pre-scaling = 1 10;
+   };
+   vph_pwr {
+   reg = VADC_VSYS;
+   qcom,pre-scaling = 1 3;
+   };
+   die_temp {
+   reg = VADC_DIE_TEMP;
+   };
+   ref_625mv {
+   reg = VADC_REF_625MV;
+   };
+   ref_1250v {
+   reg = VADC_REF_1250MV;
+   };
+   ref_gnd

[PATCH v2 3/7] ARM: dts: qcom: Add PMA8084 functions device nodes

[Ivan T. Ivanov]

Add configuration nodes for following devices:

* GPIO block, with 22 pins
* MPP block, with 8 pins
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature.
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pma8084.dtsi | 92 +
 1 file changed, 92 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi 
b/arch/arm/boot/dts/qcom-pma8084.dtsi
index a5a4fe6..5e240cc 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -1,3 +1,5 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
 #include dt-bindings/spmi/spmi.h

 spmi_bus {
@@ -7,6 +9,96 @@
reg = 0x0 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x100,
+ 0x6100 0x100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pma8084_gpios: gpios@c000 {
+   compatible = qcom,pma8084-gpio;
+   reg = 0xc000 0x1600;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 IRQ_TYPE_NONE,
+0 0xc1 0 IRQ_TYPE_NONE,
+0 0xc2 0 IRQ_TYPE_NONE,
+0 0xc3 0 IRQ_TYPE_NONE,
+0 0xc4 0 IRQ_TYPE_NONE,
+0 0xc5 0 IRQ_TYPE_NONE,
+0 0xc6 0 IRQ_TYPE_NONE,
+0 0xc7 0 IRQ_TYPE_NONE,
+0 0xc8 0 IRQ_TYPE_NONE,
+0 0xc9 0 IRQ_TYPE_NONE,
+0 0xca 0 IRQ_TYPE_NONE,
+0 0xcb 0 IRQ_TYPE_NONE,
+0 0xcc 0 IRQ_TYPE_NONE,
+0 0xcd 0 IRQ_TYPE_NONE,
+0 0xce 0 IRQ_TYPE_NONE,
+0 0xcf 0 IRQ_TYPE_NONE,
+0 0xd0 0 IRQ_TYPE_NONE,
+0 0xd1 0 IRQ_TYPE_NONE,
+0 0xd2 0 IRQ_TYPE_NONE,
+0 0xd3 0 IRQ_TYPE_NONE,
+0 0xd4 0 IRQ_TYPE_NONE,
+0 0xd5 0 IRQ_TYPE_NONE;
+   };
+
+   pma8084_mpps: mpps@a000 {
+   compatible = qcom,pma8084-mpp;
+   reg = 0xa000 0x800;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 IRQ_TYPE_NONE,
+0 0xa1 0 IRQ_TYPE_NONE,
+0 0xa2 0 IRQ_TYPE_NONE,
+0 0xa3 0 IRQ_TYPE_NONE,
+0 0xa4 0 IRQ_TYPE_NONE,
+0 0xa5 0 IRQ_TYPE_NONE,
+0 0xa6 0 IRQ_TYPE_NONE,
+0 0xa7 0 IRQ_TYPE_NONE;
+   };
+
+   pma8084_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+   #thermal-sensor-cells = 0;
+   io-channels = pma8084_vadc VADC_DIE_TEMP;
+   io-channel-names = thermal;
+   };
+
+   pma8084_vadc: vadc@3100 {
+   compatible = qcom,spmi-vadc;
+   reg = 0x3100 0x100;
+   interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+   #address-cells = 1;
+   #size-cells = 0;
+   #io-channel-cells = 1;
+   io-channel-ranges;
+
+   die_temp {
+   reg = VADC_DIE_TEMP;
+   };
+   ref_625mv {
+   reg = VADC_REF_625MV;
+   };
+   ref_1250v {
+   reg = VADC_REF_1250MV;
+   };
+   ref_buf_625mv {
+   reg = VADC_SPARE1;
+   };
+   ref_gnd {
+   reg = VADC_GND_REF;
+   };
+   ref_vdd {
+   reg

[PATCH v2 6/7] arm64: dts: qcom: Add MSM8916 restart device node

[Ivan T. Ivanov]

Add the restart node so we can reboot the device.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 92c96eb..7887588 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -77,6 +77,11 @@
ranges = 0 0 0 0x;
compatible = simple-bus;

+   restart@4ab000 {
+   compatible = qcom,pshold;
+   reg = 0x4ab000 0x4;
+   };
+
pinctrl@100 {
compatible = qcom,msm8916-pinctrl;
reg = 0x100 0x30;
--
1.9.1

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[PATCH v2 7/7] arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board

[Ivan T. Ivanov]

Add initial device configuration nodes for APQ8016 and PM8916 GPIO's.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 ++
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 +++
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |  2 ++
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  2 +-
 4 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
new file mode 100644
index 000..535532b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -0,0 +1,30 @@
+#include dt-bindings/pinctrl/qcom,pmic-gpio.h
+
+pm8916_gpios {
+
+   pinctrl-names = default;
+   pinctrl-0 = pm8916_gpios_default;
+
+   pm8916_gpios_default: default {
+   usb_hub_reset_pm {
+   pins = gpio1;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   usb_sw_sel_pm {
+   pins = gpio2;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   input-disable;
+   };
+   usr_led_3_ctrl {
+   pins = gpio3;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   usr_led_4_ctrl {
+   pins = gpio4;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
new file mode 100644
index 000..5f7023f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -0,0 +1,21 @@
+
+#include dt-bindings/gpio/gpio.h
+
+msmgpio {
+
+   pinctrl-names = default;
+   pinctrl-0 = soc_gpios_default;
+
+   soc_gpios_default: default {
+   usr_led_1_ctrl_default: usr_led_1_ctrl_default {
+   pins = gpio21;
+   function = gpio;
+   output-low;
+   };
+   usr_led_2_ctrl_default: usr_led_2_ctrl_default {
+   pins = gpio120;
+   function = gpio;
+   output-low;
+   };
+   };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 58f0055f..98abece 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -13,6 +13,8 @@

 #include msm8916.dtsi
 #include pm8916.dtsi
+#include apq8016-sbc-soc-pins.dtsi
+#include apq8016-sbc-pmic-pins.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 7887588..0f49ebd 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -82,7 +82,7 @@
reg = 0x4ab000 0x4;
};

-   pinctrl@100 {
+   msmgpio: pinctrl@100 {
compatible = qcom,msm8916-pinctrl;
reg = 0x100 0x30;
interrupts = GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH;
--
1.9.1

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[PATCH v2 1/7] ARM: dts: qcom: Add PM8841 functions device nodes

[Ivan T. Ivanov]

Add configuration nodes for multi purpose pins and
thermal sensor devices. Thermal sensor will report
PMIC die temperature.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pm8841.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 73813cc..8f1a0b1 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -1,3 +1,4 @@
+#include dt-bindings/interrupt-controller/irq.h
 #include dt-bindings/spmi/spmi.h

 spmi_bus {
@@ -7,6 +8,23 @@
reg = 0x4 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   pm8841_mpps: mpps@a000 {
+   compatible = qcom,pm8841-mpp;
+   reg = 0xa000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 4 0xa0 0 IRQ_TYPE_NONE,
+4 0xa1 0 IRQ_TYPE_NONE,
+4 0xa2 0 IRQ_TYPE_NONE,
+4 0xa3 0 IRQ_TYPE_NONE;
+   };
+
+   temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 4 0x24 0 IRQ_TYPE_EDGE_RISING;
+   };
};

usid5: pm8841@5 {
--
1.9.1

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[PATCH v2 0/7] ARM: dts: qcom: Add more device coniguration nodes

[Ivan T. Ivanov]

Recent Qualcomm PMIC's devices are accessed over SPMI bus.
Every PMIC has several sub-function devices inside.

First three patches are adding device nodes to PM8841, PM8941 and PMA8084 
PMIC's.
Next two are introducing PM8916 PMIC chip with its device nodes. The sixth one
add restart device node for MSM8916 chip. And the last one add initial GPIO
definitions for APQ8016 SBC board.

checkpatch will complain about appears un-documented for several drivers,
but I am expecting they to mergeed soon, hopefully during this merge window.

Changes since v0 [2]:

* Add proper IRQ_TYPE_* specifiers in the interrupt bidings.

Patches are created top of Kumar's kernel tree and tags/qcom-dt-for-4.1 [1].

[1] https://lkml.org/lkml/2015/3/27/599
[2] http://comments.gmane.org/gmane.linux.ports.arm.msm/12610

Ivan T. Ivanov (7):
  ARM: dts: qcom: Add PM8841 functions device nodes
  ARM: dts: qcom: Add PM8941 functions device nodes
  ARM: dts: qcom: Add PMA8084 functions device nodes
  arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916
  arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes
  arm64: dts: qcom: Add MSM8916 restart device node
  arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC
board

 arch/arm/boot/dts/qcom-pm8841.dtsi |  18 +++
 arch/arm/boot/dts/qcom-pm8941.dtsi | 133 -
 arch/arm/boot/dts/qcom-pma8084.dtsi|  92 ++
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi |  30 +
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi |  21 
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |   3 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi  |   1 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  25 +++-
 arch/arm64/boot/dts/qcom/pm8916.dtsi   |  99 +++
 9 files changed, 420 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi

--
1.9.1

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[PATCH v2 2/7] ARM: dts: qcom: Add PM8941 functions device nodes

[Ivan T. Ivanov]

Add configuration nodes for following devices:

* GPIO block, with 36 pins
* MPP block, with 8 pins
* Current ADC (IADC)
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature
* Power key device, which is responsible for clean system
  reboot or shutdown
* White LED device
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pm8941.dtsi | 133 -
 1 file changed, 132 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi 
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 24c5088..aa774e6 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -1,3 +1,5 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
 #include dt-bindings/spmi/spmi.h

 spmi_bus {
@@ -7,12 +9,141 @@
reg = 0x0 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x100,
+ 0x6100 0x100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pwrkey@800 {
+   compatible = qcom,pm8941-pwrkey;
+   reg = 0x800 0x100;
+   interrupts = 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH;
+   debounce = 15625;
+   bias-pull-up;
+   };
+
+   pm8941_gpios: gpios@c000 {
+   compatible = qcom,pm8941-gpio;
+   reg = 0xc000 0x2400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 IRQ_TYPE_NONE,
+0 0xc1 0 IRQ_TYPE_NONE,
+0 0xc2 0 IRQ_TYPE_NONE,
+0 0xc3 0 IRQ_TYPE_NONE,
+0 0xc4 0 IRQ_TYPE_NONE,
+0 0xc5 0 IRQ_TYPE_NONE,
+0 0xc6 0 IRQ_TYPE_NONE,
+0 0xc7 0 IRQ_TYPE_NONE,
+0 0xc8 0 IRQ_TYPE_NONE,
+0 0xc9 0 IRQ_TYPE_NONE,
+0 0xca 0 IRQ_TYPE_NONE,
+0 0xcb 0 IRQ_TYPE_NONE,
+0 0xcc 0 IRQ_TYPE_NONE,
+0 0xcd 0 IRQ_TYPE_NONE,
+0 0xce 0 IRQ_TYPE_NONE,
+0 0xcf 0 IRQ_TYPE_NONE,
+0 0xd0 0 IRQ_TYPE_NONE,
+0 0xd1 0 IRQ_TYPE_NONE,
+0 0xd2 0 IRQ_TYPE_NONE,
+0 0xd3 0 IRQ_TYPE_NONE,
+0 0xd4 0 IRQ_TYPE_NONE,
+0 0xd5 0 IRQ_TYPE_NONE,
+0 0xd6 0 IRQ_TYPE_NONE,
+0 0xd7 0 IRQ_TYPE_NONE,
+0 0xd8 0 IRQ_TYPE_NONE,
+0 0xd9 0 IRQ_TYPE_NONE,
+0 0xda 0 IRQ_TYPE_NONE,
+0 0xdb 0 IRQ_TYPE_NONE,
+0 0xdc 0 IRQ_TYPE_NONE,
+0 0xdd 0 IRQ_TYPE_NONE,
+0 0xde 0 IRQ_TYPE_NONE,
+0 0xdf 0 IRQ_TYPE_NONE,
+0 0xe0 0 IRQ_TYPE_NONE,
+0 0xe1 0 IRQ_TYPE_NONE,
+0 0xe2 0 IRQ_TYPE_NONE,
+0 0xe3 0 IRQ_TYPE_NONE;
+   };
+
+   pm8941_mpps: mpps@a000 {
+   compatible = qcom,pm8941-mpp;
+   reg = 0xa000 0x800;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 IRQ_TYPE_NONE,
+0 0xa1 0 IRQ_TYPE_NONE,
+0 0xa2 0 IRQ_TYPE_NONE,
+0 0xa3 0 IRQ_TYPE_NONE,
+0 0xa4 0 IRQ_TYPE_NONE,
+0 0xa5 0 IRQ_TYPE_NONE,
+0 0xa6 0 IRQ_TYPE_NONE,
+0 0xa7 0 IRQ_TYPE_NONE;
+   };
+
+   pm8941_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100

Re: [PATCH v3 2/4] extcon: usb-gpio: add support for VBUS detection

[Ivan T. Ivanov]

Hi,

On Thu, 2015-04-16 at 16:00 +0900, Chanwoo Choi wrote:
 Hi Peter,
 
 On 04/16/2015 10:59 AM, Peter Chen wrote:
  

  Ok, from USB point, external id/vbus value can't decide
  which role the controller will be, the controller driver
  will decide role according to many things, eg, user configurations,
  id/vbus value, OTG HNP, etc.
  
  So, from USB controller/phy driver, it doesn't care which cable is
  inserted, it cares about id/vbus value. Eg, it can get id/vbus value
  and it will be notified when the id/vbus value has changed.
 
 OK, I change the notifier name and add notifier events as following:
 
 - extcon_{register|unregister}_usb_notifier(struct extcon_dev *edev, struct 
 notifier_block *nb);
 - list of notifier events
 #define EXTCON_USB_ID_L_VBUS_L0   /* ID low  and VBUS low */
 #define EXTCON_USB_ID_L_VBUS_H1   /* ID low  and VBUS high */
 #define EXTCON_USB_ID_H_VBUS_L2   /* ID high and VBUS low */
 #define EXTCON_USB_ID_H_VBUS_H3   /* ID high and VBUS high */

I am still confused, why we mix ID and VBUS events into one? 
Those are two lines and they are not necessarily handled by
the same extcon_dev.

Ivan
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Re: [PATCH V3 2/6] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Wed, 2015-04-15 at 20:14 +0530, Sricharan R wrote:
 
 
 +#define QUP_I2C_MX_CONFIG_DURING_RUN   BIT(31)

Could you explain what is this for?

   This is a new feature in the V2 version of the controller,
   to support multiple i2c sub transfers without having
   a 'stop' bit in-between. Without this the i2c controller
   inserts a 'stop' on the bus when the WR/RD count registers
   reaches zero and are configured for the next transfer. So setting
   this bit when the controller is in 'RUN' state, avoids sending the
   'stop' during RUN state.
   I can add this comment in the patch.
  
  And how v2 of this patch was worked if you introduce this bit now?
  Bit is also not used by downstream driver, AFICS?
  
 The one of the reason for this and the bam support patches in
 this series was to support multiple transfers of i2c_msgs without
   a 'stop' inbetween them. So without that the driver sends a 'stop'
 between each sub-transfer. 

Are you saying that there is bug in the hardware? Please, could you
point me to codeaurora driver, which is using this bit? 



-static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg 
*msg)
 +static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct 
 i2c_msg *msg,
 +   int run)

And 'run' stands for?
  'run' just says whether the controller is in 'RUN' or 'RESET' state.
   I can change it to is_run_st to make it clear.
{
 -   /* Number of entries to shift out, including the start */
 -   int total = msg-len + 1;
 +   /* Total Number of entries to shift out, including the tags */
 +   int total;
 +
 +   if (qup-use_v2_tags) {
 +   total = msg-len + qup-tx_tag_len;
 +   if (run)
 +   total |= QUP_I2C_MX_CONFIG_DURING_RUN;

What?

  This means, if the controller is in 'RUN' state, for
  reconfiguring the RD/WR counts this bit has to be set to avoid
  'stop' bits.
  
  I don't buy it, sorry. Problem with v1 of the tags is that controller
  can not read more than 256 bytes without automatically generate STOP
  at the end, because transfer length specified with QUP_TAG_REC tag
  is 8 bits wide. There is no limitation for writes with v1 tags,
  because controller is explicitly instructed when to send out STOP.
  
 correct till this.
 
  For v2 of the tags, writes behaves more or less the same, and the
  good news are that there is new read tag QUP_TAG_V2_DATARD, which
  did't generate STOP when specified amount of data is read, still
  up to 256 bytes in chunk. Read transfers with size more than 256
  could be formed in following way:
  
  V2_START | Slave Address | V2_DATARD | countx | ... | V2_DATARD_STOP | 
  county.
  
   The above is true for a single subtransfer for reading/writing
 more than  256 bytes. But for doing WRITE, READ kind of sub
   transfers once the first sub transfer (write) is over, and
   while re-configuring the _COUNT registers for the next transfers,
 'a stop' between is inserted.

From controller itself or driver?

 +static void qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct 
 i2c_msg *msg)
 +{
 +   u32 data_len = 0, tag_len;
 +
 +   tag_len = qup-blk.block_tag_len[qup-blk.block_pos];
 +
 +   if (!(msg-flags  I2C_M_RD))
 +   data_len = 
 qup-blk.block_data_len[qup-blk.block_pos];
 +
 +   qup_i2c_send_data(qup, tag_len, qup-tags, data_len, 
 msg-buf);

This assumes that writes are up to 256 bytes, and tags and data blocks
are completely written to FIFO buffer, right?

  Yes, since we send/read data in blocks (256 bytes).
  
  How deep is the FIFO? Is it guaranteed that the whole write
  or read data, including tags will fit in.
  
   Write/read fifo functions (also for V1) currently wait for the
fifo full and empty flags conditions.

I will say that this is true for v1, but not for v2, 
because the way of how FIFO is filled in v2.

 +static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg 
 *msg,
 +   int 
 run, int last)
{
   unsigned long left;
   int ret;
 @@ -329,13 +501,20 @@ static int qup_i2c_write_one(struct qup_i2c_dev 
 *qup, struct 
 i2c_msg *msg)
   qup-msg = msg;
   qup-pos = 0;
 
 +   if (qup-use_v2_tags)
 +   qup_i2c_create_tag_v2(qup, msg, last);
 +   else
 +   qup-blk.blocks = 0;
 +
   enable_irq(qup-irq);
 
 -   qup_i2c_set_write_mode(qup, msg);
 +   qup_i2c_set_write_mode(qup, msg, run);
 
 -   ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 -   if 

[PATCH v2] usb: chipidea: Use extcon framework for VBUS and ID detect

[Ivan T. Ivanov]

On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---

Changes since v0 [1], as per Peter Chen suggestions:

* Moved external connector parsing code to ci_get_platdata()
* Moved external connector related variables to struct ci_hdrc_platform_data
* Rename ci_host_notifier() to ci_id_notifier()
* Fixed device bindings description
* Use select EXTCON framework, instead of depends on.

[1] https://lkml.org/lkml/2015/4/9/116

 .../devicetree/bindings/usb/ci-hdrc-qcom.txt   |  9 +++
 drivers/usb/chipidea/Kconfig   |  1 +
 drivers/usb/chipidea/core.c| 87 ++
 drivers/usb/chipidea/otg.c | 26 ++-
 include/linux/usb/chipidea.h   | 17 +
 5 files changed, 139 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt 
b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
index f2899b5..c635aca 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
@@ -7,6 +7,14 @@ Required properties:
 - usb-phy:  phandle for the PHY device
 - dr_mode:  Should be peripheral

+Optional properties:
+- extcon:   phandles to external connector devices. First phandle
+should point to external connector, which provide USB
+cable events, the second should point to external connector
+device, which provide USB-HOST cable events. If one of
+the external connector devices is not required, empty 0
+phandle should be specified.
+
 Examples:
gadget@f9a55000 {
compatible = qcom,ci-hdrc;
@@ -14,4 +22,5 @@ Examples:
dr_mode = peripheral;
interrupts = 0 134 0;
usb-phy = usbphy0;
+   extcon = 0, usb_id;
};
diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
index 5ce3f1d..5619b8c 100644
--- a/drivers/usb/chipidea/Kconfig
+++ b/drivers/usb/chipidea/Kconfig
@@ -1,6 +1,7 @@
 config USB_CHIPIDEA
tristate ChipIdea Highspeed Dual Role Controller
depends on ((USB_EHCI_HCD  USB_GADGET) || (USB_EHCI_HCD  
!USB_GADGET) || (!USB_EHCI_HCD  USB_GADGET))  HAS_DMA
+   select EXTCON
help
  Say Y here if your system has a dual role high speed USB
  controller based on ChipIdea silicon IP. Currently, only the
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 74fea4f..e1d495d 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -47,6 +47,7 @@
 #include linux/delay.h
 #include linux/device.h
 #include linux/dma-mapping.h
+#include linux/extcon.h
 #include linux/phy/phy.h
 #include linux/platform_device.h
 #include linux/module.h
@@ -557,9 +558,39 @@ static irqreturn_t ci_irq(int irq, void *data)
return ret;
 }

+static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
+void *ptr)
+{
+   struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
+
+   if (event)
+   vbus-state = true;
+   else
+   vbus-state = false;
+
+   return NOTIFY_DONE;
+}
+
+static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
+  void *ptr)
+{
+   struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
+
+   if (event)
+   id-state = false;
+   else
+   id-state = true;
+
+   return NOTIFY_DONE;
+}
+
 static int ci_get_platdata(struct device *dev,
struct ci_hdrc_platform_data *platdata)
 {
+   struct extcon_dev *ext_vbus, *ext_id;
+   struct ci_hdrc_cable *cable;
+   int ret;
+
if (!platdata-phy_mode)
platdata-phy_mode = of_usb_get_phy_mode(dev-of_node);

@@ -591,6 +622,53 @@ static int ci_get_platdata(struct device *dev,
if (of_usb_get_maximum_speed(dev-of_node) == USB_SPEED_FULL)
platdata-flags |= CI_HDRC_FORCE_FULLSPEED;

+   ext_id = ERR_PTR(-ENODEV);
+   ext_vbus = ERR_PTR(-ENODEV);
+   if (of_property_read_bool(dev-of_node, extcon)) {
+   /* Each one of them is not mandatory */
+   ext_vbus = extcon_get_edev_by_phandle(dev, 0);
+   if (IS_ERR(ext_vbus)  PTR_ERR(ext_vbus) != -ENODEV)
+   return PTR_ERR(ext_vbus);
+
+   ext_id = extcon_get_edev_by_phandle(dev, 1);
+   if (IS_ERR(ext_id)  PTR_ERR(ext_id) != -ENODEV)
+   return PTR_ERR(ext_id);
+   }
+
+   if (!IS_ERR(ext_vbus)) {
+   cable = platdata-vbus_extcon;
+   cable-nb.notifier_call = ci_vbus_notifier;
+   ret

Re: [PATCH v2] usb: chipidea: Use extcon framework for VBUS and ID detect

[Ivan T. Ivanov]

Hi Robert,

On Wed, 2015-04-15 at 16:11 +0200, Robert Baldyga wrote:
 Hi Ivan,
 
 On 04/15/2015 03:35 PM, Ivan T. Ivanov wrote:
  On recent Qualcomm platforms VBUS and ID lines are not routed to
  USB PHY LINK controller. Use extcon framework to receive connect
  and disconnect ID and VBUS notification.
  
  Signed-off-by: Ivan T. Ivanov iva...@linaro.org
  ---
  
  Changes since v0 [1], as per Peter Chen suggestions:
  
  * Moved external connector parsing code to ci_get_platdata()
  * Moved external connector related variables to struct ci_hdrc_platform_data
  * Rename ci_host_notifier() to ci_id_notifier()
  * Fixed device bindings description
  * Use select EXTCON framework, instead of depends on.
  
  [1] https://lkml.org/lkml/2015/4/9/116
  
   .../devicetree/bindings/usb/ci-hdrc-qcom.txt   |  9 +++
   drivers/usb/chipidea/Kconfig   |  1 +
   drivers/usb/chipidea/core.c| 87 
  ++
   drivers/usb/chipidea/otg.c | 26 ++-
   include/linux/usb/chipidea.h   | 17 +
   5 files changed, 139 insertions(+), 1 deletion(-)
  
  diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt 
  b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
  index f2899b5..c635aca 100644
  --- a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
  +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
  @@ -7,6 +7,14 @@ Required properties:
   - usb-phy:  phandle for the PHY device
   - dr_mode:  Should be peripheral
  
  +Optional properties:
  +- extcon:   phandles to external connector devices. First phandle
  +should point to external connector, which provide USB
  +cable events, the second should point to external connector
  +device, which provide USB-HOST cable events. If one of
  +the external connector devices is not required, empty 0
  +phandle should be specified.
 
 Do you expect to have USB and USB-HOST notifiers supplied by two
 different extcon drivers? It looks strange. I don't think so that we
 ever will need to deal with such weird configuration.

Yes. That is what I have today on my desk.

 
  +
   Examples:
     gadget@f9a55000 {
  compatible = qcom,ci-hdrc;
  @@ -14,4 +22,5 @@ Examples:
  dr_mode = peripheral;
  interrupts = 0 134 0;
  usb-phy = usbphy0;
  +   extcon = 0, usb_id;
  };
  diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
  index 5ce3f1d..5619b8c 100644
  --- a/drivers/usb/chipidea/Kconfig
  +++ b/drivers/usb/chipidea/Kconfig
  @@ -1,6 +1,7 @@
   config USB_CHIPIDEA
  tristate ChipIdea Highspeed Dual Role Controller
  depends on ((USB_EHCI_HCD  USB_GADGET) || (USB_EHCI_HCD  
  !USB_GADGET) || 
  (!USB_EHCI_HCD  USB_GADGET))  HAS_DMA
  +   select EXTCON
  help
  Say Y here if your system has a dual role high 
  speed USB
  controller based on ChipIdea silicon IP. Currently, 
  only the
  diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
  index 74fea4f..e1d495d 100644
  --- a/drivers/usb/chipidea/core.c
  +++ b/drivers/usb/chipidea/core.c
  @@ -47,6 +47,7 @@
   #include linux/delay.h
   #include linux/device.h
   #include linux/dma-mapping.h
  +#include linux/extcon.h
   #include linux/phy/phy.h
   #include linux/platform_device.h
   #include linux/module.h
  @@ -557,9 +558,39 @@ static irqreturn_t ci_irq(int irq, void *data)
  return ret;
   }
  
  +static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
  +   void *ptr)
  +{
  +   struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, 
  nb);
  +
  +   if (event)
  +   vbus-state = true;
  +   else
  +   vbus-state = false;
  +
  +   return NOTIFY_DONE;
  +}
 
 Actually it's not true that USB cable state is equal to VBUS state.

But this is how it supposed to work right now, no?

I have to admit that the naming is really confusing.

 USB and USB-HOST are mutually exclusive, and when you have ID=0,
 which means USB-HOST is connected, USB cable will be seen as
 disconnected even when VBUS=1.
 
 We are currently discussing how to pass VBUS state to USB OTG drivers.
 You can find discussion here:
 http://www.spinics.net/lists/linux-usb/msg123895.html

Sure, I am following this discussion. When it settles down, I can change
this as appropriate, until then this is what we will have in 4.1.

It will be messy refactoring, I think. All extcon providers and consumers
are using strings to denote cable names. Not to mention that extcon-class
is using USB-Host, while all others are using USB-HOST.

Regards,
Ivan

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Re: [PATCH V3 2/6] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Wed, 2015-04-15 at 12:09 +0530, Sricharan R wrote:

   +/* frequency definitions for high speed and max speed */
   +#define I2C_QUP_CLK_FAST_FREQ  100
  
  This is fast mode, if I am not mistaken.
  
   ya, up to 1MHZ is fast and up to 3.4MHZ is HS.
   We use this macro to check if the desired freq is in HS range.
   The above comment can be changed though to make it clear.

My point was that this is neither high nor max speed.

   +
 /* Status, Error flags */
 #define I2C_STATUS_WR_BUFFER_FULL  BIT(0)
 #define I2C_STATUS_BUS_ACTIVE  BIT(8)
   @@ -102,6 +119,15 @@
 #define RESET_BIT  0x0
 #define ONE_BYTE   0x1
   
   +#define QUP_I2C_MX_CONFIG_DURING_RUN   BIT(31)
  
  Could you explain what is this for?
  
This is a new feature in the V2 version of the controller,
to support multiple i2c sub transfers without having
a 'stop' bit in-between. Without this the i2c controller
inserts a 'stop' on the bus when the WR/RD count registers
reaches zero and are configured for the next transfer. So setting
this bit when the controller is in 'RUN' state, avoids sending the
'stop' during RUN state.
I can add this comment in the patch.

And how v2 of this patch was worked if you introduce this bit now?
Bit is also not used by downstream driver, AFICS?

 
   +
   +struct qup_i2c_block {
   +   int blocks;

count

   +   u8  *block_tag_len;

just tag_len, 

   +   int *block_data_len;

just data_len,

   +   int block_pos;

just pos?

   +};
   +
 struct qup_i2c_dev {
struct device*dev;
void __iomem*base;
   @@ -115,9 +141,17 @@ struct qup_i2c_dev {
int in_fifo_sz;
int out_blk_sz;
int in_blk_sz;
   -
   +   struct  qup_i2c_blockblk;
unsigned longone_byte_t;
   
   +   int is_hs;
   +   booluse_v2_tags;
   +
   +   int tx_tag_len;
   +   int rx_tag_len;
   +   u8  *tags;
   +   int tags_pos;
   +
struct i2c_msg*msg;
/* Current posion in user message buffer */
int pos;
   @@ -263,10 +297,19 @@ static int qup_i2c_wait_ready(struct qup_i2c_dev 
   *qup, int op, bool val,
}
 }
  
  Is this better tag related fields grouping?
  
 
  struct qup_i2c_tag_block {
  
   u8  tag[2];
   // int  tag_len; this is alway 2, or?
   int data_len; // this could be zero, right?
  };
  
 There is a struct for qup_i2c_block which has tag and data len. Not sure
 what change you suggest above ? Also with V2 transfers tag len need
   not be 2. It can be more than that based on the data len.

The point is that: I will like to see better grouping of
related variables. Now they are spread all over. Would it
be possible to also take care for tx_tag_len, rx_tag_len, 
tags, tags_pos.

 
   -static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct 
   i2c_msg *msg)
   +static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct 
   i2c_msg *msg,
   +   int run)
  
  And 'run' stands for?
   'run' just says whether the controller is in 'RUN' or 'RESET' state.
I can change it to is_run_st to make it clear.
 {
   -   /* Number of entries to shift out, including the start */
   -   int total = msg-len + 1;
   +   /* Total Number of entries to shift out, including the tags */
   +   int total;
   +
   +   if (qup-use_v2_tags) {
   +   total = msg-len + qup-tx_tag_len;
   +   if (run)
   +   total |= QUP_I2C_MX_CONFIG_DURING_RUN;
  
  What?
  
   This means, if the controller is in 'RUN' state, for
   reconfiguring the RD/WR counts this bit has to be set to avoid
   'stop' bits.

I don't buy it, sorry. Problem with v1 of the tags is that controller
can not read more than 256 bytes without automatically generate STOP
at the end, because transfer length specified with QUP_TAG_REC tag
is 8 bits wide. There is no limitation for writes with v1 tags,
because controller is explicitly instructed when to send out STOP.

For v2 of the tags, writes behaves more or less the same, and the
good news are that there is new read tag QUP_TAG_V2_DATARD, which 
did't generate STOP when specified amount of data is read, still
up to 256 bytes in chunk. Read transfers with size more than 256
could be formed in following way:

V2_START | Slave Address | V2_DATARD | countx | ... | V2_DATARD_STOP | county.

 
   
   -static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg 
   *msg)
   +static void qup_i2c_create_tag_v2(struct qup_i2c_dev *qup,
   +   struct i2c_msg *msg, int 
   last)
   +{
   +   u16 addr = (msg-addr  1) | ((msg-flags  I2C_M_RD) == 
   I2C_M_RD);
   +   int len = 

Re: [PATCH V3 2/6] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Sat, 2015-04-11 at 12:39 +0530, Sricharan R wrote:
 From: Andy Gross agr...@codeaurora.org
 
 QUP from version 2.1.1 onwards, supports a new format of
 i2c command tags. Tag codes instructs the controller to
 perform a operation like read/write. This new tagging version
 supports bam dma and transfers of more than 256 bytes without 'stop'
 in between. Adding the support for the same.
 

But the read and write messages size QUP_READ_LIMIT?

 For each block a data_write/read tag and data_len tag is added to
 the output fifo. For the final block of data write_stop/read_stop
 tag is used.
 
 Signed-off-by: Andy Gross agr...@codeaurora.org
 Signed-off-by: Sricharan R sricha...@codeaurora.org
 ---
 [V3] Addressed comments from Andy Gross agr...@codeaurora.org
  to coalesce each i2c_msg in i2c_msgs as a single transfer.
  Added macros to i2c_wait_ready function.
 
  drivers/i2c/busses/i2c-qup.c | 393 
 +--
  1 file changed, 337 insertions(+), 56 deletions(-)
 
 diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
 index 9ccf3e8..16a8f69 100644
 --- a/drivers/i2c/busses/i2c-qup.c
 +++ b/drivers/i2c/busses/i2c-qup.c
 @@ -24,6 +24,7 @@
  #include linux/of.h
  #include linux/platform_device.h
  #include linux/pm_runtime.h
 +#include linux/slab.h
 
  /* QUP Registers */
  #define QUP_CONFIG 0x000
 @@ -42,6 +43,7 @@
  #define QUP_IN_FIFO_BASE   0x218
  #define QUP_I2C_CLK_CTL0x400
  #define QUP_I2C_STATUS 0x404
 +#define QUP_I2C_MASTER_GEN 0x408
 
  /* QUP States and reset values */
  #define QUP_RESET_STATE0
 @@ -69,6 +71,8 @@
  #define QUP_CLOCK_AUTO_GATEBIT(13)
  #define I2C_MINI_CORE  (2  8)
  #define I2C_N_VAL  15
 +#define I2C_N_VAL_V2   7
 +
  /* Most significant word offset in FIFO port */
  #define QUP_MSW_SHIFT  (I2C_N_VAL + 1)
 
 @@ -80,17 +84,30 @@
 
  #define QUP_REPACK_EN  (QUP_UNPACK_EN | QUP_PACK_EN)
 
 +#define QUP_V2_TAGS_EN 1
 +
  #define QUP_OUTPUT_BLOCK_SIZE(x)(((x)  0)  0x03)
  #define QUP_OUTPUT_FIFO_SIZE(x)(((x)  2)  0x07)
  #define QUP_INPUT_BLOCK_SIZE(x)(((x)  5)  0x03)
  #define QUP_INPUT_FIFO_SIZE(x) (((x)  7)  0x07)
 
 -/* QUP tags */
 +/* QUP V1 tags */
  #define QUP_TAG_START  (1  8)
  #define QUP_TAG_DATA   (2  8)
  #define QUP_TAG_STOP   (3  8)
  #define QUP_TAG_REC(4  8)
 
 +/* QUP v2 tags */
 +#define QUP_TAG_V2_HS  0xff
 +#define QUP_TAG_V2_START   0x81
 +#define QUP_TAG_V2_DATAWR  0x82
 +#define QUP_TAG_V2_DATAWR_STOP 0x83
 +#define QUP_TAG_V2_DATARD  0x85
 +#define QUP_TAG_V2_DATARD_STOP 0x87
 +
 +/* frequency definitions for high speed and max speed */
 +#define I2C_QUP_CLK_FAST_FREQ  100

This is fast mode, if I am not mistaken.

 +
  /* Status, Error flags */
  #define I2C_STATUS_WR_BUFFER_FULL  BIT(0)
  #define I2C_STATUS_BUS_ACTIVE  BIT(8)
 @@ -102,6 +119,15 @@
  #define RESET_BIT  0x0
  #define ONE_BYTE   0x1
 
 +#define QUP_I2C_MX_CONFIG_DURING_RUN   BIT(31)

Could you explain what is this for?

 +
 +struct qup_i2c_block {
 +   int blocks;
 +   u8  *block_tag_len;
 +   int *block_data_len;
 +   int block_pos;
 +};
 +
  struct qup_i2c_dev {
 struct device*dev;
 void __iomem*base;
 @@ -115,9 +141,17 @@ struct qup_i2c_dev {
 int in_fifo_sz;
 int out_blk_sz;
 int in_blk_sz;
 -
 +   struct  qup_i2c_blockblk;
 unsigned longone_byte_t;
 
 +   int is_hs;
 +   booluse_v2_tags;
 +
 +   int tx_tag_len;
 +   int rx_tag_len;
 +   u8  *tags;
 +   int tags_pos;
 +
 struct i2c_msg*msg;
 /* Current posion in user message buffer */
 int pos;
 @@ -263,10 +297,19 @@ static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, 
 int op, bool val,
 }
  }

Is this better tag related fields grouping?

struct qup_i2c_tag_block {

u8  tag[2];
// int  tag_len; this is alway 2, or?
int data_len; // this could be zero, right?
};

 
 -static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg 
 *msg)
 +static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg 
 *msg,
 +   int run)

And 'run' stands for?

  {
 -   /* Number of entries to shift out, including the start */
 -   int total = msg-len + 1;
 +   /* Total Number of entries to shift out, including the tags */
 +   int total;
 +
 +   if (qup-use_v2_tags) {
 +   total = msg-len + qup-tx_tag_len;
 +   if (run)
 +   total |= QUP_I2C_MX_CONFIG_DURING_RUN;

What?

 +   } else {
 +   total = msg-len + 1; /* 

Re: [PATCH] usb: chipidea: Use extcon framework for VBUS and ID detection

[Ivan T. Ivanov]

 On Apr 13, 2015, at 6:53 AM, Peter Chen peter.c...@freescale.com wrote:
 
 On Thu, Apr 09, 2015 at 11:33:38AM +0300, Ivan T. Ivanov wrote:
 On recent Qualcomm platforms VBUS and ID lines are not routed to
 USB PHY LINK controller. Use extcon framework to receive connect
 and disconnect ID and VBUS notification.
 
 

snip

 
 +Optional properties:
 +- extcon:   phandles to external connector devices. First phandle
 +should point to external connector, which provide USB
 +cable events, the second should point to external connector
 +device, which provide USB-HOST cable events. If one of
 +the external connector devices is not required empty 0
 +phandle should be specified.
 
 You mean if id connector is not needed, we write dts like below:
 extcon = usb_vbus, 0;
 
 If it is, you may miss ',' between required and empty 0”.

Yes. Will fix it.

 u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
 {
 -return hw_read(ci, OP_OTGSC, mask);
 +u32 val = hw_read(ci, OP_OTGSC, mask);
 +
 +if ((mask  OTGSC_BSV)  ci-vbus.conn.edev) {
 
 You may use || since you can't get vbus and id value from
 cpu register (otgsc).

The idea is to not rely on the register content for these
bits if user have defined these DT bindings.

Will fix rest of the comments and resend.

Thank you,
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[PATCH 2/2] usb: phy: msm: Manual PHY and LINK controller VBUS change notification

[Ivan T. Ivanov]

VBUS is not routed to USB PHY on recent Qualcomm platforms. USB controller
must see VBUS in order to pull-up DP when setting RS bit. Henc configure
USB PHY and LINK registers sense VBUS and enable manual pullup on D+ line.

Cc: Vamsi Krishna vskri...@codeaurora.org
Cc: Mayank Rana mr...@codeaurora.org
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt  |  4 
 drivers/usb/phy/phy-msm-usb.c  | 26 ++
 include/linux/usb/msm_hsusb.h  |  5 +
 include/linux/usb/msm_hsusb_hw.h   |  9 
 4 files changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index f26bcfa..bd8d9e7 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -69,6 +69,10 @@ Optional properties:
 (no, min, max) where each value represents either a voltage
 in microvolts or a value corresponding to voltage corner.

+- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
+and controller driver therefore enables pull-up explicitly
+before starting controller using usbcmd run/stop bit.
+
 - extcon:   phandles to external connector devices. First phandle
 should point to external connector, which provide USB
 cable events, the second should point to external connector
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index d47c3eb..4a928f7 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -245,8 +245,14 @@ static void ulpi_init(struct msm_otg *motg)
 static int msm_phy_notify_disconnect(struct usb_phy *phy,
   enum usb_device_speed speed)
 {
+   struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
int val;

+   if (motg-manual_pullup) {
+   val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
+   usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
+   }
+
/*
 * Put the transceiver in non-driving mode. Otherwise host
 * may not detect soft-disconnection.
@@ -431,6 +437,24 @@ static int msm_phy_init(struct usb_phy *phy)
ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
}

+   if (motg-manual_pullup) {
+   val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
+   ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
+
+   val = readl(USB_GENCONFIG_2);
+   val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
+   writel(val, USB_GENCONFIG_2);
+
+   val = readl(USB_USBCMD);
+   val |= USBCMD_SESS_VLD_CTRL;
+   writel(val, USB_USBCMD);
+
+   val = ulpi_read(phy, ULPI_FUNC_CTRL);
+   val = ~ULPI_FUNC_CTRL_OPMODE_MASK;
+   val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
+   ulpi_write(phy, val, ULPI_FUNC_CTRL);
+   }
+
if (motg-phy_number)
writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);

@@ -1529,6 +1553,8 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)
motg-vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
}

+   motg-manual_pullup = of_property_read_bool(node, qcom,manual-pullup);
+
ext_id = ERR_PTR(-ENODEV);
ext_vbus = ERR_PTR(-ENODEV);
if (of_property_read_bool(node, extcon)) {
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 9a38e77..a5edc8d 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -153,6 +153,9 @@ struct msm_usb_cable {
  * @chg_type: The type of charger attached.
  * @dcd_retires: The retry count used to track Data contact
  *   detection process.
+ * @manual_pullup: true if VBUS is not routed to USB controller/phy
+ * and controller driver therefore enables pull-up explicitly before
+ * starting controller using usbcmd run/stop bit.
  * @vbus: VBUS signal state trakining, using extcon framework
  * @id: ID signal state trakining, using extcon framework
  */
@@ -185,6 +188,8 @@ struct msm_otg {
struct reset_control *link_rst;
int vdd_levels[3];

+   bool manual_pullup;
+
struct msm_usb_cable vbus;
struct msm_usb_cable id;
 };
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index a29f603..e159b39 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -21,6 +21,8 @@

 #define USB_AHBBURST (MSM_USB_BASE + 0x0090)
 #define USB_AHBMODE  (MSM_USB_BASE + 0x0098)
+#define USB_GENCONFIG_2  (MSM_USB_BASE + 0x00a0)
+
 #define USB_CAPLENGTH(MSM_USB_BASE + 0x0100) /* 8 bit */

 #define USB_USBCMD

[PATCH] usb: chipidea: Use extcon framework for VBUS and ID detection

[Ivan T. Ivanov]

On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---

Suggestions for better solution are welcome!

 .../devicetree/bindings/usb/ci-hdrc-qcom.txt   |  9 +++
 drivers/usb/chipidea/Kconfig   |  1 +
 drivers/usb/chipidea/ci.h  | 18 +
 drivers/usb/chipidea/core.c| 77 ++
 drivers/usb/chipidea/otg.c | 19 +-
 5 files changed, 123 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt 
b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
index f2899b5..788da49 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
@@ -7,6 +7,14 @@ Required properties:
 - usb-phy:  phandle for the PHY device
 - dr_mode:  Should be peripheral

+Optional properties:
+- extcon:   phandles to external connector devices. First phandle
+should point to external connector, which provide USB
+cable events, the second should point to external connector
+device, which provide USB-HOST cable events. If one of
+the external connector devices is not required empty 0
+phandle should be specified.
+
 Examples:
gadget@f9a55000 {
compatible = qcom,ci-hdrc;
@@ -14,4 +22,5 @@ Examples:
dr_mode = peripheral;
interrupts = 0 134 0;
usb-phy = usbphy0;
+   extcon = usb_vbus, usb_id;
};
diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig
index 77b47d8..a67b67f 100644
--- a/drivers/usb/chipidea/Kconfig
+++ b/drivers/usb/chipidea/Kconfig
@@ -1,6 +1,7 @@
 config USB_CHIPIDEA
tristate ChipIdea Highspeed Dual Role Controller
depends on ((USB_EHCI_HCD  USB_GADGET) || (USB_EHCI_HCD  
!USB_GADGET) || (!USB_EHCI_HCD  USB_GADGET))  HAS_DMA
+   depends on EXTCON
help
  Say Y here if your system has a dual role high speed USB
  controller based on ChipIdea silicon IP. Currently, only the
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index 65913d4..04e7aee 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -13,6 +13,7 @@
 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
 #define __DRIVERS_USB_CHIPIDEA_CI_H

+#include linux/extcon.h
 #include linux/list.h
 #include linux/irqreturn.h
 #include linux/usb.h
@@ -132,6 +133,18 @@ struct hw_bank {
 };

 /**
+ * struct ci_hdrc - structure for exteternal connector cable state tracking
+ * @state: current state of the line
+ * @nb: hold event notification callback
+ * @conn: used for notification registration
+ */
+struct ci_cable {
+   boolstate;
+   struct notifier_block   nb;
+   struct extcon_specific_cable_nb conn;
+};
+
+/**
  * struct ci_hdrc - chipidea device representation
  * @dev: pointer to parent device
  * @lock: access synchronization
@@ -169,6 +182,8 @@ struct hw_bank {
  * @b_sess_valid_event: indicates there is a vbus event, and handled
  * at ci_otg_work
  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
+ * @vbus: VBUS signal state trakining, using extcon framework
+ * @id: ID signal state trakining, using extcon framework
  */
 struct ci_hdrc {
struct device   *dev;
@@ -211,6 +226,9 @@ struct ci_hdrc {
boolid_event;
boolb_sess_valid_event;
boolimx28_write_fix;
+
+   struct ci_cable vbus;
+   struct ci_cable id;
 };

 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index a57dc88..0f805bd 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -47,6 +47,7 @@
 #include linux/delay.h
 #include linux/device.h
 #include linux/dma-mapping.h
+#include linux/extcon.h
 #include linux/phy/phy.h
 #include linux/platform_device.h
 #include linux/module.h
@@ -646,9 +647,36 @@ static void ci_get_otg_capable(struct ci_hdrc *ci)
dev_dbg(ci-dev, It is OTG capable controller\n);
 }

+static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
+void *ptr)
+{
+   struct ci_cable *vbus = container_of(nb, struct ci_cable, nb);
+
+   if (event)
+   vbus-state = true;
+   else
+   vbus-state = false;
+
+   return NOTIFY_DONE;
+}
+
+static int ci_host_notifier(struct notifier_block *nb, unsigned long event,
+  void *ptr)
+{
+   struct ci_cable *id = container_of(nb, struct ci_cable

[PATCH 1/2] usb: phy: msm: Use extcon framework for VBUS and ID detection

[Ivan T. Ivanov]

On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt  |  7 ++
 drivers/usb/phy/Kconfig|  1 +
 drivers/usb/phy/phy-msm-usb.c  | 84 ++
 include/linux/usb/msm_hsusb.h  | 17 +
 4 files changed, 109 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt 
b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 2826f2a..f26bcfa 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -69,6 +69,13 @@ Optional properties:
 (no, min, max) where each value represents either a voltage
 in microvolts or a value corresponding to voltage corner.

+- extcon:   phandles to external connector devices. First phandle
+should point to external connector, which provide USB
+cable events, the second should point to external connector
+device, which provide USB-HOST cable events. If one of
+the external connector devices is not required empty 0
+phandle should be specified.
+
 Example HSUSB OTG controller device node:

 usb@f9a55000 {
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 52d3d58..ca584ef 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -141,6 +141,7 @@ config USB_MSM_OTG
tristate Qualcomm on-chip USB OTG controller support
depends on (USB || USB_GADGET)  (ARCH_MSM || ARCH_QCOM || 
COMPILE_TEST)
depends on RESET_CONTROLLER
+   depends on EXTCON
select USB_PHY
help
  Enable this to support the USB OTG transceiver on Qualcomm chips. It
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 000fd89..d47c3eb 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -1445,9 +1445,42 @@ static const struct of_device_id msm_otg_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);

+static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long 
event,
+   void *ptr)
+{
+   struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
+   struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
+
+   if (event)
+   set_bit(B_SESS_VLD, motg-inputs);
+   else
+   clear_bit(B_SESS_VLD, motg-inputs);
+
+   schedule_work(motg-sm_work);
+
+   return NOTIFY_DONE;
+}
+
+static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
+   void *ptr)
+{
+   struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
+   struct msm_otg *motg = container_of(id, struct msm_otg, id);
+
+   if (event)
+   clear_bit(ID, motg-inputs);
+   else
+   set_bit(ID, motg-inputs);
+
+   schedule_work(motg-sm_work);
+
+   return NOTIFY_DONE;
+}
+
 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
 {
struct msm_otg_platform_data *pdata;
+   struct extcon_dev *ext_id, *ext_vbus;
const struct of_device_id *id;
struct device_node *node = pdev-dev.of_node;
struct property *prop;
@@ -1496,6 +1529,52 @@ static int msm_otg_read_dt(struct platform_device *pdev, 
struct msm_otg *motg)
motg-vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
}

+   ext_id = ERR_PTR(-ENODEV);
+   ext_vbus = ERR_PTR(-ENODEV);
+   if (of_property_read_bool(node, extcon)) {
+
+   /* Each one of them is not mandatory */
+   ext_vbus = extcon_get_edev_by_phandle(pdev-dev, 0);
+   if (IS_ERR(ext_vbus)  PTR_ERR(ext_vbus) != -ENODEV)
+   return PTR_ERR(ext_vbus);
+
+   ext_id = extcon_get_edev_by_phandle(pdev-dev, 1);
+   if (IS_ERR(ext_id)  PTR_ERR(ext_id) != -ENODEV)
+   return PTR_ERR(ext_id);
+   }
+
+   if (!IS_ERR(ext_vbus)) {
+   motg-vbus.nb.notifier_call = msm_otg_vbus_notifier;
+   ret = extcon_register_interest(motg-vbus.conn, ext_vbus-name,
+  USB, motg-vbus.nb);
+   if (ret  0) {
+   dev_err(pdev-dev, register VBUS notifier failed\n);
+   return ret;
+   }
+
+   ret = extcon_get_cable_state(ext_vbus, USB);
+   if (ret)
+   set_bit(B_SESS_VLD, motg-inputs);
+   else
+   clear_bit(B_SESS_VLD, motg-inputs);
+   }
+
+   if (!IS_ERR(ext_id)) {
+   motg-id.nb.notifier_call

Re: [PATCH 1/7] ARM: dts: qcom: Add PM8841 functions device nodes

[Ivan T. Ivanov]

On Wed, 2015-04-01 at 14:54 -0500, Kumar Gala wrote:
 On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov iva...@linaro.org wrote:
 
  Add configuration nodes for multi purpose pins and
  thermal sensor devices. Thermal sensor will report
  PMIC die temperature.
  
  Signed-off-by: Ivan T. Ivanov iva...@linaro.org
  ---
  arch/arm/boot/dts/qcom-pm8841.dtsi | 14 ++
  1 file changed, 14 insertions(+)
  
  diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
  b/arch/arm/boot/dts/qcom-pm8841.dtsi
  index 73813cc..5c109bd 100644
  --- a/arch/arm/boot/dts/qcom-pm8841.dtsi
  +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
  @@ -7,6 +7,20 @@
  reg = 0x4 SPMI_USID;
  #address-cells = 1;
  #size-cells = 0;
  +
  +   pm8841_mpps: mpps@a000 {
  +   compatible = qcom,pm8841-mpp;
  +   reg = 0xa000 0x400;
  +   gpio-controller;
  +   #gpio-cells = 2;
  +   interrupts = 4 0xa0 0 0, 4 0xa1 0 0, 4 0xa2 0 
  0, 4 0xa3 0 0;
 
 What’s the interrupt parent here with 4 cells? 

SPMI PMIC Arbiter controller.

Ivan
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[PATCH 3/7] ARM: dts: qcom: Add PMA8084 functions device nodes

[Ivan T. Ivanov]

* GPIO block, with 22 pins
* MPP block, with 8 pins
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature.
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pma8084.dtsi | 70 +
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi 
b/arch/arm/boot/dts/qcom-pma8084.dtsi
index a5a4fe6..9092c2e 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -1,3 +1,5 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
 #include dt-bindings/spmi/spmi.h

 spmi_bus {
@@ -7,6 +9,74 @@
reg = 0x0 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x100,
+ 0x6100 0x100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pma8084_gpios: gpios@c000 {
+   compatible = qcom,pma8084-gpio;
+   reg = 0xc000 0x1600;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 0, 0 0xc1 0 0, 0 0xc2 0 0, 
0 0xc3 0 0,
+0 0xc4 0 0, 0 0xc5 0 0, 0 0xc6 0 0, 
0 0xc7 0 0,
+0 0xc8 0 0, 0 0xc9 0 0, 0 0xca 0 0, 
0 0xcb 0 0,
+0 0xcc 0 0, 0 0xcd 0 0, 0 0xce 0 0, 
0 0xcf 0 0,
+0 0xd0 0 0, 0 0xd1 0 0, 0 0xd2 0 0, 
0 0xd3 0 0,
+0 0xd4 0 0, 0 0xd5 0 0;
+   };
+
+   pma8084_mpps: mpps@a000 {
+   compatible = qcom,pma8084-mpp;
+   reg = 0xa000 0x800;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 0, 0 0xa1 0 0, 0 0xa2 0 0, 
0 0xa3 0 0,
+0 0xa4 0 0, 0 0xa5 0 0, 0 0xa6 0 0, 
0 0xa7 0 0;
+   };
+
+   pma8084_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+   #thermal-sensor-cells = 0;
+   io-channels = pma8084_vadc VADC_DIE_TEMP;
+   io-channel-names = thermal;
+   };
+
+   pma8084_vadc: vadc@3100 {
+   compatible = qcom,spmi-vadc;
+   reg = 0x3100 0x100;
+   interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+   #address-cells = 1;
+   #size-cells = 0;
+   #io-channel-cells = 1;
+   io-channel-ranges;
+
+   die_temp {
+   reg = VADC_DIE_TEMP;
+   };
+   ref_625mv {
+   reg = VADC_REF_625MV;
+   };
+   ref_1250v {
+   reg = VADC_REF_1250MV;
+   };
+   ref_buf_625mv {
+   reg = VADC_SPARE1;
+   };
+   ref_gnd {
+   reg = VADC_GND_REF;
+   };
+   ref_vdd {
+   reg = VADC_VDD_VADC;
+   };
+   };
};

usid1: pma8084@1 {
--
1.9.1

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[PATCH 1/7] ARM: dts: qcom: Add PM8841 functions device nodes

[Ivan T. Ivanov]

Add configuration nodes for multi purpose pins and
thermal sensor devices. Thermal sensor will report
PMIC die temperature.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pm8841.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 73813cc..5c109bd 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -7,6 +7,20 @@
reg = 0x4 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   pm8841_mpps: mpps@a000 {
+   compatible = qcom,pm8841-mpp;
+   reg = 0xa000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 4 0xa0 0 0, 4 0xa1 0 0, 4 0xa2 0 0, 
4 0xa3 0 0;
+   };
+
+   temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 4 0x24 0 IRQ_TYPE_EDGE_RISING;
+   };
};

usid5: pm8841@5 {
--
1.9.1

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[PATCH 2/7] ARM: dts: qcom: Add PM8941 functions device nodes

[Ivan T. Ivanov]

Add configuration nodes for following devices:

* GPIO block, with 36 pins
* MPP block, with 8 pins
* Current ADC (IADC)
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature
* Power key device, which is responsible for clean system
  reboot or shutdown
* White LED device
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm/boot/dts/qcom-pm8941.dtsi | 98 ++
 1 file changed, 98 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi 
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 24c5088..23a9268 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -1,3 +1,5 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
 #include dt-bindings/spmi/spmi.h

 spmi_bus {
@@ -7,6 +9,89 @@
reg = 0x0 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x100,
+ 0x6100 0x100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pwrkey@800 {
+   compatible = qcom,pm8941-pwrkey;
+   reg = 0x800 0x100;
+   interrupts = 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH;
+   debounce = 15625;
+   bias-pull-up;
+   };
+
+   pm8941_gpios: gpios@c000 {
+   compatible = qcom,pm8941-gpio;
+   reg = 0xc000 0x2400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 0, 0 0xc1 0 0, 0 0xc2 0 0, 
0 0xc3 0 0,
+0 0xc4 0 0, 0 0xc5 0 0, 0 0xc6 0 0, 
0 0xc7 0 0,
+0 0xc8 0 0, 0 0xc9 0 0, 0 0xca 0 0, 
0 0xcb 0 0,
+0 0xcc 0 0, 0 0xcd 0 0, 0 0xce 0 0, 
0 0xcf 0 0,
+0 0xd0 0 0, 0 0xd1 0 0, 0 0xd2 0 0, 
0 0xd3 0 0,
+0 0xd4 0 0, 0 0xd5 0 0, 0 0xd6 0 0, 
0 0xd7 0 0,
+0 0xd8 0 0, 0 0xd9 0 0, 0 0xda 0 0, 
0 0xdb 0 0,
+0 0xdc 0 0, 0 0xdd 0 0, 0 0xde 0 0, 
0 0xdf 0 0,
+0 0xe0 0 0, 0 0xe1 0 0, 0 0xe2 0 0, 
0 0xe3 0 0;
+   };
+
+   pm8941_mpps: mpps@a000 {
+   compatible = qcom,pm8941-mpp;
+   reg = 0xa000 0x800;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 0, 0 0xa1 0 0, 0 0xa2 0 0, 
0 0xa3 0 0,
+0 0xa4 0 0, 0 0xa5 0 0, 0 0xa6 0 0, 
0 0xa7 0 0;
+   };
+
+   pm8941_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+   io-channels = pm8941_vadc VADC_DIE_TEMP;
+   io-channel-names = thermal;
+   #thermal-sensor-cells = 0;
+   };
+
+   pm8941_vadc: vadc@3100 {
+   compatible = qcom,spmi-vadc;
+   reg = 0x3100 0x100;
+   interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+   #address-cells = 1;
+   #size-cells = 0;
+   #io-channel-cells = 1;
+
+   die_temp {
+   reg = VADC_DIE_TEMP;
+   };
+   ref_625mv {
+   reg = VADC_REF_625MV;
+   };
+   ref_1250v {
+   reg = VADC_REF_1250MV;
+   };
+   ref_gnd {
+   reg = VADC_GND_REF;
+   };
+   ref_vdd {
+   reg = VADC_VDD_VADC;
+   };
+   };
+
+   pm8941_iadc: iadc@3600 {
+   compatible = qcom,pm8941-iadc, qcom,spmi-iadc;
+   reg = 0x3600 0x100,
+ 0x12f1 0x1;
+   interrupts = 0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING;
+   qcom,external-resistor-micro-ohms = 1;
+   };
};

usid1: pm8941@1 {
@@ -14,5 +99,18 @@
reg = 0x1 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+   wled@d800 {
+   compatible

[PATCH 0/7] ARM: dts: qcom: Add more device coniguration nodes

[Ivan T. Ivanov]

Recent Qualcomm PMIC's devices are accessed over SPMI bus.
Every PMIC has several sub-function devices inside.

First three patches are adding device nodes to PM8841, PM8941 and PMA8084 
PMIC's.
Next two are introducing PM8916 PMIC chip with its device nodes.
Sixth add restart device node for MSM8916 chip.
And the last one add initial GPIO definitions for APQ8016 SBC board.

All compatible drivers are already merged or will soon be merged,
hopefully in the 4.1 merge window. This is why checkpatch will complain about
appears un-documented. checkpatch will also complain about
line over 80 characters, but I hope that in this case this is in favor
in readability.

Patches are created top of Kumar's kernel tree and tags/qcom-dt-for-4.1 [1].

Any comments are welcome.

Regards,
Ivan

[1] https://lkml.org/lkml/2015/3/27/599

Ivan T. Ivanov (7):
  ARM: dts: qcom: Add PM8841 functions device nodes
  ARM: dts: qcom: Add PM8941 functions device nodes
  ARM: dts: qcom: Add PMA8084 functions device nodes
  arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916
  arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes
  arm64: dts: qcom: Add MSM8916 restart device node
  arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC
board

 arch/arm/boot/dts/qcom-pm8841.dtsi | 14 
 arch/arm/boot/dts/qcom-pm8941.dtsi | 98 ++
 arch/arm/boot/dts/qcom-pma8084.dtsi| 70 
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 +++
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 +
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |  3 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi  |  1 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi  | 25 +-
 arch/arm64/boot/dts/qcom/pm8916.dtsi   | 93 
 9 files changed, 354 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi

--
1.9.1

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[PATCH 6/7] arm64: dts: qcom: Add MSM8916 restart device node

[Ivan T. Ivanov]

Add the restart node so we can reboot the device.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 02a4916..c95592d 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -77,6 +77,11 @@
ranges = 0 0 0 0x;
compatible = simple-bus;

+   restart@4ab000 {
+   compatible = qcom,pshold;
+   reg = 0x4ab000 0x4;
+   };
+
pinctrl@100 {
compatible = qcom,msm8916-pinctrl;
reg = 0x100 0x30;
--
1.9.1

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[PATCH 7/7] arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board

[Ivan T. Ivanov]

Add initial device configuration nodes for APQ8016 and PM8916 GPIO's.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 ++
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 +++
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi  |  2 ++
 arch/arm64/boot/dts/qcom/msm8916.dtsi  |  2 +-
 4 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
new file mode 100644
index 000..535532b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -0,0 +1,30 @@
+#include dt-bindings/pinctrl/qcom,pmic-gpio.h
+
+pm8916_gpios {
+
+   pinctrl-names = default;
+   pinctrl-0 = pm8916_gpios_default;
+
+   pm8916_gpios_default: default {
+   usb_hub_reset_pm {
+   pins = gpio1;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   usb_sw_sel_pm {
+   pins = gpio2;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   input-disable;
+   };
+   usr_led_3_ctrl {
+   pins = gpio3;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   usr_led_4_ctrl {
+   pins = gpio4;
+   function = PMIC_GPIO_FUNC_NORMAL;
+   output-low;
+   };
+   };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
new file mode 100644
index 000..5f7023f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -0,0 +1,21 @@
+
+#include dt-bindings/gpio/gpio.h
+
+msmgpio {
+
+   pinctrl-names = default;
+   pinctrl-0 = soc_gpios_default;
+
+   soc_gpios_default: default {
+   usr_led_1_ctrl_default: usr_led_1_ctrl_default {
+   pins = gpio21;
+   function = gpio;
+   output-low;
+   };
+   usr_led_2_ctrl_default: usr_led_2_ctrl_default {
+   pins = gpio120;
+   function = gpio;
+   output-low;
+   };
+   };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 58f0055f..98abece 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -13,6 +13,8 @@

 #include msm8916.dtsi
 #include pm8916.dtsi
+#include apq8016-sbc-soc-pins.dtsi
+#include apq8016-sbc-pmic-pins.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index c95592d..4951fcc 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -82,7 +82,7 @@
reg = 0x4ab000 0x4;
};

-   pinctrl@100 {
+   msmgpio: pinctrl@100 {
compatible = qcom,msm8916-pinctrl;
reg = 0x100 0x30;
interrupts = GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH;
--
1.9.1

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[PATCH 5/7] arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PM9816 has 2 SPMI devices per physical package. Add PMIC configuration
nodes including sub-function device nodes and include them in boards,
which are using 8x16 based chipset.

PM9816 sub-function devices include:

* GPIO block, with 4 pins
* MPP block, with 4 pins
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
  channel report PMIC die temperature.
* Power key device, which is responsible for clean system
  reboot or shutdown
* RTC device

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi |  1 +
 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi |  1 +
 arch/arm64/boot/dts/qcom/pm8916.dtsi  | 93 +++
 3 files changed, 95 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi 
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 703a4f1..58f0055f 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -12,6 +12,7 @@
  */

 #include msm8916.dtsi
+#include pm8916.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index bea871b..a1aa0b2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -12,6 +12,7 @@
  */

 #include msm8916.dtsi
+#include pm8916.dtsi

 / {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi 
b/arch/arm64/boot/dts/qcom/pm8916.dtsi
new file mode 100644
index 000..2a5ad2c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -0,0 +1,93 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+   usid0: pm8916@0 {
+   compatible =qcom,spmi-pmic;
+   reg = 0x0 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   rtc@6000 {
+   compatible = qcom,pm8941-rtc;
+   reg = 0x6000 0x6100;
+   reg-names = rtc, alarm;
+   interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+   };
+
+   pwrkey@800 {
+   compatible = qcom,pm8941-pwrkey;
+   reg = 0x800;
+   interrupts = 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH;
+   debounce = 15625;
+   bias-pull-up;
+   };
+
+   pm8916_gpios: gpios@c000 {
+   compatible = qcom,pm8916-gpio;
+   reg = 0xc000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xc0 0 0, 0 0xc1 0 0, 0 0xc2 0 0, 
0 0xc3 0 0;
+   };
+
+   pm8916_mpps: mpps@a000 {
+   compatible = qcom,pm8916-mpp;
+   reg = 0xa000 0x400;
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupts = 0 0xa0 0 0, 0 0xa1 0 0, 0 0xa2 0 0, 
0 0xa3 0 0;
+   };
+
+   pm8916_temp: temp-alarm@2400 {
+   compatible = qcom,spmi-temp-alarm;
+   reg = 0x2400 0x100;
+   interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+   io-channels = pm8916_vadc VADC_DIE_TEMP;
+   io-channel-names = thermal;
+   #thermal-sensor-cells = 0;
+   };
+
+   pm8916_vadc: vadc@3100 {
+   compatible = qcom,spmi-vadc;
+   reg = 0x3100 0x100;
+   interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+   #address-cells = 1;
+   #size-cells = 0;
+   #io-channel-cells = 1;
+
+   usb_in {
+   reg = VADC_USBIN;
+   qcom,pre-scaling = 1 10;
+   };
+   vph_pwr {
+   reg = VADC_VSYS;
+   qcom,pre-scaling = 1 3;
+   };
+   die_temp {
+   reg = VADC_DIE_TEMP;
+   };
+   ref_625mv {
+   reg = VADC_REF_625MV;
+   };
+   ref_1250v {
+   reg = VADC_REF_1250MV;
+   };
+   ref_gnd {
+   reg = VADC_GND_REF;
+   };
+   ref_vdd {
+   reg = VADC_VDD_VADC;
+   };
+   };
+   };
+
+   usid1: pm8916@1 {
+   compatible =qcom,spmi-pmic;
+   reg = 0x1

[PATCH 4/7] arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916

[Ivan T. Ivanov]

Add SPMI PMIC Arbiter configuration nodes for MSM8916.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index f212b83..02a4916 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -192,5 +192,23 @@
status = disabled;
};
};
+
+   spmi_bus: spmi@200f000 {
+   compatible = qcom,spmi-pmic-arb;
+   reg = 0x200f000 0x1000,
+   0x240 0x40,
+   0x2c0 0x40,
+   0x380 0x20,
+   0x200a000 0x2100;
+   reg-names = core, chnls, obsrvr, intr, cnfg;
+   interrupt-names = periph_irq;
+   interrupts = 0 190 0;
+   qcom,ee = 0;
+   qcom,channel = 0;
+   #address-cells = 2;
+   #size-cells = 0;
+   interrupt-controller;
+   #interrupt-cells = 4;
+   };
};
 };
--
1.9.1

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[PATCH] pinctrl: Add support for PM8916 GPIO's and MPP's

[Ivan T. Ivanov]

Add compatible string definitions and supported pin functions.

Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
 .../devicetree/bindings/pinctrl/qcom,pmic-gpio.txt|  2 ++
 .../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt |  2 ++
 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c  |  1 +
 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c   |  1 +
 include/dt-bindings/pinctrl/qcom,pmic-gpio.h  | 15 +++
 include/dt-bindings/pinctrl/qcom,pmic-mpp.h   |  4 
 6 files changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
index 7ed0804..1ae63c0 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -10,6 +10,7 @@ PMIC's from Qualcomm.
qcom,pm8018-gpio
qcom,pm8038-gpio
qcom,pm8058-gpio
+   qcom,pm8916-gpio
qcom,pm8917-gpio
qcom,pm8921-gpio
qcom,pm8941-gpio
@@ -74,6 +75,7 @@ to specify in a pin configuration subnode:
gpio1-gpio6 for pm8018
gpio1-gpio12 for pm8038
gpio1-gpio40 for pm8058
+   gpio1-gpio4 for pm8916
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
index 854774b..ed19991 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
@@ -8,6 +8,7 @@ of PMIC's from Qualcomm.
Value type: string
Definition: Should contain one of:
qcom,pm8841-mpp,
+   qcom,pm8916-mpp,
qcom,pm8941-mpp,
qcom,pma8084-mpp,

@@ -67,6 +68,7 @@ to specify in a pin configuration subnode:
Definition: List of MPP pins affected by the properties specified in
this subnode.  Valid pins are:
mpp1-mpp4 for pm8841
+   mpp1-mpp4 for pm8916
mpp1-mpp8 for pm8941
mpp1-mpp4 for pma8084

diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c 
b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 0f11a26..b2d2221 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -810,6 +810,7 @@ static int pmic_gpio_remove(struct platform_device *pdev)
 }

 static const struct of_device_id pmic_gpio_of_match[] = {
+   { .compatible = qcom,pm8916-gpio },   /* 4 GPIO's */
{ .compatible = qcom,pm8941-gpio },   /* 36 GPIO's */
{ .compatible = qcom,pma8084-gpio },  /* 22 GPIO's */
{ },
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c 
b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index a8924db..8f36c5f 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -925,6 +925,7 @@ static int pmic_mpp_remove(struct platform_device *pdev)

 static const struct of_device_id pmic_mpp_of_match[] = {
{ .compatible = qcom,pm8841-mpp },/* 4 MPP's */
+   { .compatible = qcom,pm8916-mpp },/* 4 MPP's */
{ .compatible = qcom,pm8941-mpp },/* 8 MPP's */
{ .compatible = qcom,pma8084-mpp },   /* 8 MPP's */
{ },
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h 
b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
index fa74d7c..aafa76c 100644
--- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -48,6 +48,14 @@
 #define PM8058_GPIO_L5 6
 #define PM8058_GPIO_L2 7

+/*
+ * Note: PM8916 GPIO1 and GPIO2 are supporting
+ * only L2(1.15V) and L5(1.8V) options
+ */
+#define PM8916_GPIO_VPH0
+#define PM8916_GPIO_L2 2
+#define PM8916_GPIO_L5 3
+
 #define PM8917_GPIO_VPH0
 #define PM8917_GPIO_S4 2
 #define PM8917_GPIO_L153
@@ -115,6 +123,13 @@
 #define PM8058_GPIO39_MP3_CLK  PMIC_GPIO_FUNC_FUNC1
 #define PM8058_GPIO40_EXT_BB_ENPMIC_GPIO_FUNC_FUNC1

+#define PM8916_GPIO1_BAT_ALRM_OUT  PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO1_KEYP_DRV  PMIC_GPIO_FUNC_FUNC2
+#define PM8916_GPIO2_DIV_CLK   PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
+#define PM8916_GPIO3_KEYP_DRV  PMIC_GPIO_FUNC_FUNC1
+#define PM8916_GPIO4_KEYP_DRV  PMIC_GPIO_FUNC_FUNC2
+
 #define PM8917_GPIO9_18_KEYP_DRV   PMIC_GPIO_FUNC_FUNC1
 #define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
 #define

Re: [PATCH 2/6] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Thu, 2015-03-26 at 11:14 +0530, Sricharan R wrote:
 
   +   if (msg-flags  I2C_M_RD)
   +   qup-rx_tag_len = (qup-blocks  1);
  
  here again.
  
 hmm, why not shift ?

Because it makes reading code harder and because compiler
 is smart enough to choose appropriate instruction for
underling CPU architecture.

   +   else
   +   qup-rx_tag_len = 0;
   +}
   +
   +static u32 qup_i2c_xfer_data(struct qup_i2c_dev *qup, int len,
   +   u8 *buf, 
   int last)
   +{
  
  I think that xfer is too vague in this case, prefer write or send.
  
 ok. Will change it to send.
   +   static u32 val, idx;
  
  static? please fix.
   That was intentional. Using to pack tag and data in to one word across
   two calls. So preserving val, idx across calls.

Sorry this is no go! Reorganize the code, please.

Regards,
Ivan
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Re: [PATCH 3/6] i2c: qup: Add bam dma capabilities

[Ivan T. Ivanov]

Hi Sricharan,

On Fri, 2015-03-13 at 23:19 +0530, Sricharan R wrote:


  #define QUP_I2C_MASTER_GEN 0x408
 +#define QUP_I2C_MASTER_CONFIG  0x408
 

Unused.

  #define QUP_READ_LIMIT 256
 +#define MX_TX_RX_LEN   SZ_64K
 +#define MX_BLOCKS  (MX_TX_RX_LEN / QUP_READ_LIMIT)
 +
 +#define TOUT_MAX   300 /* Max timeout for 32k tx/tx */
 

seconds, muliseconds?

  struct qup_i2c_config {
 int tag_ver;
 int max_freq;
  };
 
 +struct tag {

Please use consistent naming convention.

 +   u8 *start;
 +   dma_addr_t addr;
 +};
 +
  struct qup_i2c_dev {
 struct device*dev;
 void __iomem*base;
 @@ -157,9 +181,35 @@ struct qup_i2c_dev {
 /* QUP core errors */
 u32 qup_err;
 
 +   /* dma parameters */
 +   boolis_dma;
 +   struct  dma_pool *dpool;
 +   struct  tag start_tag;
 +   struct  tag scratch_tag;
 +   struct  tag footer_tag;
 +   struct  dma_chan *dma_tx;
 +   struct  dma_chan *dma_rx;
 +   struct  scatterlist *sg_tx;
 +   struct  scatterlist *sg_rx;
 +   dma_addr_tsg_tx_phys;
 +   dma_addr_tsg_rx_phys;

Maybe these could be organized in structure per direction.

 +
 struct completionxfer;
  };
 
 +struct i2c_bam_xfer {

Unused.

 +   struct qup_i2c_dev *qup;
 +   u32 start_len;
 +
 +   u32 rx_nents;
 +   u32 tx_nents;
 +
 +   struct dma_async_tx_descriptor *tx_desc;
 +   dma_cookie_t tx_cookie;
 +   struct dma_async_tx_descriptor *rx_desc;
 +   dma_cookie_t rx_cookie;

structure per direction.

 +};
 +
 

 +static void bam_i2c_callback(void *data)
 +{

Please use consistent naming, here and bellow.

 +   struct qup_i2c_dev *qup = data;
 +
 +   complete(qup-xfer);
 +}
 +
 +static int get_start_tag(u8 *tag, struct i2c_msg *msg, int first, int last,
 +   int blen)
 +{
 +   u8 addr = (msg-addr  1) | ((msg-flags  I2C_M_RD) == I2C_M_RD);
 +   u8 op;
 +   int len = 0;
 +
 +   /* always issue stop for each read block */
 +   if (last) {
 +   if (msg-flags  I2C_M_RD)
 +   op = QUP_TAG_V2_DATARD_STOP;
 +   else
 +   op = QUP_TAG_V2_DATAWR_STOP;
 +   } else {
 +   if (msg-flags  I2C_M_RD)
 +   op = QUP_TAG_V2_DATARD;
 +   else
 +   op = QUP_TAG_V2_DATAWR;
 +   }
 +
 +   if (msg-flags  I2C_M_TEN) {
 +   len += 5;
 +   tag[0] = QUP_TAG_V2_START;
 +   tag[1] = addr;
 +   tag[2] = op;
 +   tag[3] = blen;
 +
 +   if (msg-flags  I2C_M_RD  last) {
 +   len += 2;
 +   tag[4] = QUP_BAM_INPUT_EOT;
 +   tag[5] = QUP_BAM_FLUSH_STOP;
 +   }
 +   } else {
 +   if (first) {
 +   tag[len++] = QUP_TAG_V2_START;
 +   tag[len++] = addr;
 +   }
 +
 +   tag[len++] = op;
 +   tag[len++] = blen;
 +
 +   if (msg-flags  I2C_M_RD  last) {
 +   tag[len++] = QUP_BAM_INPUT_EOT;
 +   tag[len++] = QUP_BAM_FLUSH_STOP;
 +   }
 +   }
 +
 +   return len;
 +}

Maybe could be split to 2 functions?

 -static const struct i2c_algorithm qup_i2c_algo = {
 +static struct i2c_algorithm qup_i2c_algo = {

Why?

 .master_xfer= qup_i2c_xfer,
 .functionality= qup_i2c_func,
  };
 @@ -839,6 +1136,7 @@ static int qup_i2c_probe(struct platform_device *pdev)
 u32 clk_freq = 10;
 const struct qup_i2c_config *config;
 const struct of_device_id *of_id;
 +   int blocks;
 
 qup = devm_kzalloc(pdev-dev, sizeof(*qup), GFP_KERNEL);
 if (!qup)
 @@ -875,6 +1173,53 @@ static int qup_i2c_probe(struct platform_device *pdev)
 return qup-irq;
 }
 
 +   if (of_device_is_compatible(pdev-dev.of_node, qcom,i2c-qup-v2.1.1) 
 ||
 +   of_device_is_compatible(pdev-dev.of_node,
 +   qcom,i2c-qup-v2.2.1)) {

Logic will be simpler if you check just for version 1 of the controller.

 +   qup-dma_rx = dma_request_slave_channel(pdev-dev, bam-rx);
 +

Please use dma_request_slave_channel_reason.

As Andy noted, please use just rx, tx

 +   if (!qup-dma_rx)
 +   return -EPROBE_DEFER;

Don't mask other errors, here and bellow. DMA support should be optional.

 dev_err(qup-dev, Could not get core clock\n);
 @@ -989,6 +1334,14 @@ static int qup_i2c_remove(struct platform_device *pdev)
  {
 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
 
 +   dma_pool_free(qup-dpool, qup-start_tag.start,
 +   
 qup-start_tag.addr);
 +   

Re: [PATCH 2/6] i2c: qup: Add V2 tags support

[Ivan T. Ivanov]

Hi Sricharan,

On Fri, 2015-03-13 at 23:19 +0530, Sricharan R wrote:
 From: Andy Gross agr...@codeaurora.org
 
 QUP from version 2.1.1 onwards, supports a new format of
 i2c command tags. Tag codes instructs the controller to
 perform a operation like read/write. This new tagging version
 supports bam dma and transfers of more than 256 bytes without 'stop'
 in between. Adding the support for the same.
 
 For each block a data_write/read tag and data_len tag is added to
 the output fifo. For the final block of data write_stop/read_stop
 tag is used.
 
 Signed-off-by: Andy Gross agr...@codeaurora.org
 Signed-off-by: Sricharan R sricha...@codeaurora.org
 ---
  drivers/i2c/busses/i2c-qup.c | 342 
 ++-
 

snip

 +#define I2C_QUP_CLK_MAX_FREQ   340

unused?

 +
  /* Status, Error flags */
  #define I2C_STATUS_WR_BUFFER_FULL  BIT(0)
  #define I2C_STATUS_BUS_ACTIVE  BIT(8)
 @@ -99,6 +117,11 @@
 
  #define QUP_READ_LIMIT 256
 
 +struct qup_i2c_config {
 +   int tag_ver;
 +   int max_freq;
 +};
 +

Do you really need this one. It is referenced only during probe, 
but information contained in is already available by other means.


  struct qup_i2c_dev {
 struct device*dev;
 void __iomem*base;
 @@ -112,9 +135,20 @@ struct qup_i2c_dev {
 int in_fifo_sz;
 int out_blk_sz;
 int in_blk_sz;
 -
 +   int blocks;
 +   u8  *block_tag_len;
 +   int *block_data_len;

Maybe these could be organized in struct?

snip

 
 +static void qup_i2c_create_tag_v2(struct qup_i2c_dev *qup,
 +   struct i2c_msg *msg)
 +{
 +   u16 addr = (msg-addr  1) | ((msg-flags  I2C_M_RD) == I2C_M_RD);
 +   int len = 0, prev_len = 0;
 +   int blocks = 0;
 +   int rem;
 +   int block_len = 0;
 +   int data_len;
 +
 +   qup-block_pos = 0;
 +   qup-pos = 0;
 +   qup-blocks = (msg-len + QUP_READ_LIMIT - 1) / (QUP_READ_LIMIT);

Braces around QUP_READ_LIMIT are not needed.

 +   rem = msg-len % QUP_READ_LIMIT;
 +
 +   /* 2 tag bytes for each block + 2 extra bytes for first block */
 +   qup-tags = kzalloc((qup-blocks  1) + 2, GFP_KERNEL);

Don't play tricks with shifts, just use multiplication.

 +   qup-block_tag_len = kzalloc(qup-blocks, GFP_KERNEL);
 +   qup-block_data_len = kzalloc(sizeof(int) * qup-blocks, GFP_KERNEL);

Better use sizeof(*qup-block_data_len).

 +
 +   while (blocks  qup-blocks) {
 +   /* 0 is used to specify a READ_LIMIT of 256 bytes */
 +   data_len = (blocks  (qup-blocks - 1)) ? 0 : rem;
 +
 +   /* Send START and ADDR bytes only for the first block */
 +   if (!blocks) {
 +   qup-tags[len++] = QUP_TAG_V2_START;
 +
 +   if (qup-is_hs) {
 +   qup-tags[len++] = QUP_TAG_V2_HS;
 +   qup-tags[len++] = QUP_TAG_V2_START;

Is this second QUP_TAG_V2_START intentional?

 +   }
 +
 +   qup-tags[len++] = addr  0xff;
 +   if (msg-flags  I2C_M_TEN)
 +   qup-tags[len++] = addr  8;
 +   }
 +
 +   /* Send _STOP commands for the last block */
 +   if (blocks == (qup-blocks - 1)) {
 +   if (msg-flags  I2C_M_RD)
 +   qup-tags[len++] = QUP_TAG_V2_DATARD_STOP;
 +   else
 +   qup-tags[len++] = QUP_TAG_V2_DATAWR_STOP;
 +   } else {
 +   if (msg-flags  I2C_M_RD)
 +   qup-tags[len++] = QUP_TAG_V2_DATARD;
 +   else
 +   qup-tags[len++] = QUP_TAG_V2_DATAWR;
 +   }
 +
 +   qup-tags[len++] = data_len;
 +   block_len = len - prev_len;
 +   prev_len = len;
 +   qup-block_tag_len[blocks] = block_len;
 +
 +   if (!data_len)
 +   qup-block_data_len[blocks] = QUP_READ_LIMIT;
 +   else
 +   qup-block_data_len[blocks] = data_len;
 +
 +   qup-tags_pos = 0;
 +   blocks++;
 +   }
 +
 +   qup-tx_tag_len = len;
 +
 +   if (msg-flags  I2C_M_RD)
 +   qup-rx_tag_len = (qup-blocks  1);

here again.

 +   else
 +   qup-rx_tag_len = 0;
 +}
 +
 +static u32 qup_i2c_xfer_data(struct qup_i2c_dev *qup, int len,
 +   u8 *buf, int 
 last)
 +{

I think that xfer is too vague in this case, prefer write or send.

 +   static u32 val, idx;

static? please fix.

 +   u32  t, rem, pos = 0;
 +
 +   rem = len - pos + idx;
 +
 +   while (rem) {
 +   if (qup_i2c_wait_ready(qup, QUP_OUT_FULL, 0, 4)) {
 +  

Re: [PATCH v4 1/1] extcon: usb-gpio: Introduce gpio usb extcon driver

[Ivan T. Ivanov]

Hi,

On Tue, 2015-03-17 at 11:01 +0900, Chanwoo Choi wrote:
 Hi Ivan,
 
 On 03/16/2015 11:23 PM, Ivan T. Ivanov wrote:
  Hi Roger,
  
  On Mon, 2015-03-16 at 15:11 +0200, Roger Quadros wrote:
   Hi Ivan,
   
   On 16/03/15 14:32, Ivan T. Ivanov wrote:
Hi,

On Mon, 2015-02-02 at 12:21 +0200, Roger Quadros wrote:
 This driver observes the USB ID pin connected over a GPIO and
 updates the USB cable extcon states accordingly.
 
 The existing GPIO extcon driver is not suitable for this purpose
 as it needs to be taught to understand USB cable states and it
 can't handle more than one cable per instance.
 
 For the USB case we need to handle 2 cable states.
 1) USB (attach/detach)
 2) USB-HOST (attach/detach)
 
 This driver can be easily updated in the future to handle VBUS
 events in case it happens to be available on GPIO for any platform.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 ---
 v4:
 - got rid of id_irqwake flag. Fail if enable/disable_irq_wake() fails
 - changed host cable name to USB-HOST

I am sorry that I am getting a bit little late into this.

Isn't supposed that we have to use strings defined in
const char extcon_cable_name[][]?


 +
 +/* List of detectable cables */
 +enum {
 +   EXTCON_CABLE_USB = 0,
 +   EXTCON_CABLE_USB_HOST,
 +

Same here: duplicated with enum extcon_cable_name

 +   EXTCON_CABLE_END,
 +};
 +
 +static const char *usb_extcon_cable[] = {
 +   [EXTCON_CABLE_USB] = USB,
 +   [EXTCON_CABLE_USB_HOST] = USB-HOST,
 +   NULL,
 +};
   
   I'm not exactly sure how else it is supposed to work if we
   support only a subset of cables from the global extcon_cable_name[][].
  
  I don't see issue that we use just 2 events. I think that we can
  reuse  enum extcon_cable_name

Now I see that extcon_dev_register() expect NULL terminated array of 
pointers, so it will not be possible to use enum extcon_cable_name
as index in the above array, sorry.

   and strings already defined in
  extcon_cable_name[][] global variable. It is defined extern in
  extcon.h file exactly for this purpose, no?
 
 'extcon_cable_name' global variable is not used on extcon driver directly.
 It is just recommended cable name.

Hm, this is what bothers me. How client drivers will know cable name if 
every provider start using its own naming scheme? 

If I write client driver I will use:

extcon_register_interest(obj, name, extcon_cable_name[EXTCON_USB_HOST], nb);

and this will now work with this driver because it define string differently.

... Well, I see that string is changed because your recommendation :-), 
then lets fix extcon_cable_name strings and not let drivers define its own
names.


 I have plan to use standard cable name for extcon driver instead of that
 each extcon driver define the cable name.
 

Sound like a good plan :-)

Regards,
Ivan



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Re: [PATCH v4 1/1] extcon: usb-gpio: Introduce gpio usb extcon driver

[Ivan T. Ivanov]

Fixed spelling error.

On Tue, 2015-03-17 at 09:52 +0200, Ivan T. Ivanov wrote:
 Hi,
 
 On Tue, 2015-03-17 at 11:01 +0900, Chanwoo Choi wrote:
  Hi Ivan,
  
  On 03/16/2015 11:23 PM, Ivan T. Ivanov wrote:
   Hi Roger,
   
   On Mon, 2015-03-16 at 15:11 +0200, Roger Quadros wrote:
Hi Ivan,

On 16/03/15 14:32, Ivan T. Ivanov wrote:
 Hi,
 
 On Mon, 2015-02-02 at 12:21 +0200, Roger Quadros wrote:
  This driver observes the USB ID pin connected over a GPIO and
  updates the USB cable extcon states accordingly.
  
  The existing GPIO extcon driver is not suitable for this purpose
  as it needs to be taught to understand USB cable states and it
  can't handle more than one cable per instance.
  
  For the USB case we need to handle 2 cable states.
  1) USB (attach/detach)
  2) USB-HOST (attach/detach)
  
  This driver can be easily updated in the future to handle VBUS
  events in case it happens to be available on GPIO for any platform.
  
  Signed-off-by: Roger Quadros rog...@ti.com
  ---
  v4:
  - got rid of id_irqwake flag. Fail if enable/disable_irq_wake() 
  fails
  - changed host cable name to USB-HOST
 
 I am sorry that I am getting a bit little late into this.
 
 Isn't supposed that we have to use strings defined in
 const char extcon_cable_name[][]?
 
 
  +
  +/* List of detectable cables */
  +enum {
  +   EXTCON_CABLE_USB = 0,
  +   EXTCON_CABLE_USB_HOST,
  +
 
 Same here: duplicated with enum extcon_cable_name
 
  +   EXTCON_CABLE_END,
  +};
  +
  +static const char *usb_extcon_cable[] = {
  +   [EXTCON_CABLE_USB] = USB,
  +   [EXTCON_CABLE_USB_HOST] = USB-HOST,
  +   NULL,
  +};

I'm not exactly sure how else it is supposed to work if we
support only a subset of cables from the global extcon_cable_name[][].
   
   I don't see issue that we use just 2 events. I think that we can
   reuse  enum extcon_cable_name
 
 Now I see that extcon_dev_register() expect NULL terminated array of
 pointers, so it will not be possible to use enum extcon_cable_name
 as index in the above array, sorry.
 
and strings already defined in
   extcon_cable_name[][] global variable. It is defined extern in
   extcon.h file exactly for this purpose, no?
  
  'extcon_cable_name' global variable is not used on extcon driver directly.
  It is just recommended cable name.
 
 Hm, this is what bothers me. How client drivers will know cable name if
 every provider start using its own naming scheme?
 
 If I write client driver I will use:
 
 extcon_register_interest(obj, name, extcon_cable_name[EXTCON_USB_HOST], nb);
 
 and this will now work with this driver because it define string differently.
^^^
s/now/not/

 
 ... Well, I see that string is changed because your recommendation :-),
 then lets fix extcon_cable_name strings and not let drivers define its own
 names.
 
 
  I have plan to use standard cable name for extcon driver instead of that
  each extcon driver define the cable name.
  
 
 Sound like a good plan :-)
 
 Regards,
 Ivan
 
 
 
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[PATCH v2 0/3] Add initial DT support for Qualcomm SPMI PMIC devices

[Ivan T. Ivanov]

Following set of patches add initial DT support for PMIC devices
found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
could be found here [1]. First version of the patches could be found here [2].

Changes since first version.

* Added more specific compatible strings to PMIC's DT configuration nodes.
* Changed #size-cells of the PMIC's DT configuration nodes from 0 to 1.
  #size-cells property is used by drivers to obtain size of the resource 
regions.
* Added Reviewed-by from Bjorn and Andy. Hopefully it still stands after these
  changes.

Regards,
Ivan

[1] http://lwn.net/Articles/564637/
[2] https://lkml.org/lkml/2015/2/3/228

Ivan T. Ivanov (3):
  ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
  ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
  ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes

 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts|  2 ++
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts|  1 +
 arch/arm/boot/dts/qcom-apq8084-mtp.dts|  1 +
 arch/arm/boot/dts/qcom-apq8084.dtsi   | 16 
 arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts |  2 ++
 arch/arm/boot/dts/qcom-msm8974.dtsi   | 16 
 arch/arm/boot/dts/qcom-pm8841.dtsi| 18 ++
 arch/arm/boot/dts/qcom-pm8941.dtsi| 18 ++
 arch/arm/boot/dts/qcom-pma8084.dtsi   | 18 ++
 9 files changed, 92 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi

--
1.9.1

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[PATCH v2 1/3] ARM: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974

[Ivan T. Ivanov]

Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.

Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 16 
 arch/arm/boot/dts/qcom-msm8974.dtsi | 16 
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi 
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc..dbedf64 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -226,5 +226,21 @@
clock-names = core, iface;
status = disabled;
};
+
+   spmi_bus: spmi@fc4cf000 {
+   compatible = qcom,spmi-pmic-arb;
+   reg-names = core, intr, cnfg;
+   reg = 0xfc4cf000 0x1000,
+ 0xfc4cb000 0x1000,
+ 0xfc4ca000 0x1000;
+   interrupt-names = periph_irq;
+   interrupts = 0 190 0;
+   qcom,ee = 0;
+   qcom,channel = 0;
+   #address-cells = 2;
+   #size-cells = 0;
+   interrupt-controller;
+   #interrupt-cells = 4;
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi 
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec1..2d11641 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -247,5 +247,21 @@
#address-cells = 1;
#size-cells = 0;
};
+
+   spmi_bus: spmi@fc4cf000 {
+   compatible = qcom,spmi-pmic-arb;
+   reg-names = core, intr, cnfg;
+   reg = 0xfc4cf000 0x1000,
+ 0xfc4cb000 0x1000,
+ 0xfc4ca000 0x1000;
+   interrupt-names = periph_irq;
+   interrupts = 0 190 0;
+   qcom,ee = 0;
+   qcom,channel = 0;
+   #address-cells = 2;
+   #size-cells = 0;
+   interrupt-controller;
+   #interrupt-cells = 4;
+   };
};
 };
--
1.9.1

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[PATCH v3] mfd: Add specific compatible strings for Qualcomm's SPMI PMIC's

[Ivan T. Ivanov]

Some of the PMIC's could have specific regmap configuration
tables in future, so add specific compatible strings for known
PMIC's. Also print runtime detected chip revision information.

Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---

Changes since v2

* Fixed error checks from regmap_reads's.
* Reorganized pmic_spmi_id_table.
* Lower device info print level.

 .../devicetree/bindings/mfd/qcom,spmi-pmic.txt |  19 +++-
 drivers/mfd/qcom-spmi-pmic.c   | 103 +++--
 2 files changed, 111 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt 
b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
index 7182b88..6ac06c1 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
@@ -15,10 +15,21 @@ each. A function can consume one or more of these 
fixed-size register regions.

 Required properties:
 - compatible:  Should contain one of:
- qcom,pm8941
- qcom,pm8841
- qcom,pma8084
- or generalized qcom,spmi-pmic.
+   qcom,pm8941,
+   qcom,pm8841,
+   qcom,pma8084,
+   qcom,pm8019,
+   qcom,pm8226,
+   qcom,pm8110,
+   qcom,pma8084,
+   qcom,pmi8962,
+   qcom,pmd9635,
+   qcom,pm8994,
+   qcom,pmi8994,
+   qcom,pm8916,
+   qcom,pm8004,
+   qcom,pm8909,
+   or generalized qcom,spmi-pmic.
 - reg: Specifies the SPMI USID slave address for this device.
For more information see:
Documentation/devicetree/bindings/spmi/spmi.txt
diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c
index 4b8beb2..af6ac1c 100644
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -17,6 +17,100 @@
 #include linux/regmap.h
 #include linux/of_platform.h

+#define PMIC_REV2  0x101
+#define PMIC_REV3  0x102
+#define PMIC_REV4  0x103
+#define PMIC_TYPE  0x104
+#define PMIC_SUBTYPE   0x105
+
+#define PMIC_TYPE_VALUE0x51
+
+#define COMMON_SUBTYPE 0x00
+#define PM8941_SUBTYPE 0x01
+#define PM8841_SUBTYPE 0x02
+#define PM8019_SUBTYPE 0x03
+#define PM8226_SUBTYPE 0x04
+#define PM8110_SUBTYPE 0x05
+#define PMA8084_SUBTYPE0x06
+#define PMI8962_SUBTYPE0x07
+#define PMD9635_SUBTYPE0x08
+#define PM8994_SUBTYPE 0x09
+#define PMI8994_SUBTYPE0x0a
+#define PM8916_SUBTYPE 0x0b
+#define PM8004_SUBTYPE 0x0c
+#define PM8909_SUBTYPE 0x0d
+
+static const struct of_device_id pmic_spmi_id_table[] = {
+   { .compatible = qcom,spmi-pmic, .data = (void *)COMMON_SUBTYPE },
+   { .compatible = qcom,pm8941,.data = (void *)PM8941_SUBTYPE },
+   { .compatible = qcom,pm8841,.data = (void *)PM8841_SUBTYPE },
+   { .compatible = qcom,pm8019,.data = (void *)PM8019_SUBTYPE },
+   { .compatible = qcom,pm8226,.data = (void *)PM8226_SUBTYPE },
+   { .compatible = qcom,pm8110,.data = (void *)PM8110_SUBTYPE },
+   { .compatible = qcom,pma8084,   .data = (void *)PMA8084_SUBTYPE },
+   { .compatible = qcom,pmi8962,   .data = (void *)PMI8962_SUBTYPE },
+   { .compatible = qcom,pmd9635,   .data = (void *)PMD9635_SUBTYPE },
+   { .compatible = qcom,pm8994,.data = (void *)PM8994_SUBTYPE },
+   { .compatible = qcom,pmi8994,   .data = (void *)PMI8994_SUBTYPE },
+   { .compatible = qcom,pm8916,.data = (void *)PM8916_SUBTYPE },
+   { .compatible = qcom,pm8004,.data = (void *)PM8004_SUBTYPE },
+   { .compatible = qcom,pm8909,.data = (void *)PM8909_SUBTYPE },
+   { }
+};
+
+static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
+{
+   unsigned int rev2, minor, major, type, subtype;
+   const char *name = unknown;
+   int ret, i;
+
+   ret = regmap_read(map, PMIC_TYPE, type);
+   if (ret  0)
+   return;
+
+   if (type != PMIC_TYPE_VALUE)
+   return;
+
+   ret = regmap_read(map, PMIC_SUBTYPE, subtype);
+   if (ret  0)
+   return;
+
+   for (i = 0; i  ARRAY_SIZE(pmic_spmi_id_table); i++) {
+   if (subtype == (unsigned long)pmic_spmi_id_table[i].data)
+   break;
+   }
+
+   if (i != ARRAY_SIZE(pmic_spmi_id_table))
+   name = pmic_spmi_id_table[i].compatible;
+
+   ret = regmap_read(map, PMIC_REV2, rev2);
+   if (ret  0)
+   return;
+
+   ret = regmap_read(map, PMIC_REV3, minor);
+   if (ret  0)
+   return;
+
+   ret = regmap_read(map

[PATCH v2 3/3] ARM: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PMA8084 have 2 SPMI devices per physical package. Add their
configuration nodes and include them in boards which are using
AQP8084 based chipset.

Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |  1 +
 arch/arm/boot/dts/qcom-apq8084-mtp.dts |  1 +
 arch/arm/boot/dts/qcom-pma8084.dtsi| 18 ++
 3 files changed, 20 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi

diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts 
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index c9ff108..f7725b9 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -1,4 +1,5 @@
 #include qcom-apq8084.dtsi
+#include qcom-pma8084.dtsi

 / {
model = Qualcomm APQ8084/IFC6540;
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts 
b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 8ecec58..cb43acf 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -1,4 +1,5 @@
 #include qcom-apq8084.dtsi
+#include qcom-pma8084.dtsi

 / {
model = Qualcomm APQ 8084-MTP;
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi 
b/arch/arm/boot/dts/qcom-pma8084.dtsi
new file mode 100644
index 000..b1116a1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -0,0 +1,18 @@
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+   usid0: pma8084@0 {
+   compatible = qcom,pma8084, qcom,spmi-pmic;
+   reg = 0x0 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+
+   usid1: pma8084@1 {
+   compatible = qcom,pma8084, qcom,spmi-pmic;
+   reg = 0x1 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+};
--
1.9.1

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[PATCH v2 2/3] ARM: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes

[Ivan T. Ivanov]

PM8841 and PM8941 have 2 SPMI devices per physical package.
Add their configuration nodes and include them in boards
which are using 8x74 based chipset.

Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts|  2 ++
 arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts |  2 ++
 arch/arm/boot/dts/qcom-pm8841.dtsi| 18 ++
 arch/arm/boot/dts/qcom-pm8941.dtsi| 18 ++
 4 files changed, 40 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi

diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts 
b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 4737049..d484d08 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -1,4 +1,6 @@
 #include qcom-msm8974.dtsi
+#include qcom-pm8841.dtsi
+#include qcom-pm8941.dtsi

 / {
model = Qualcomm APQ8074 Dragonboard;
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts 
b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index 21b..bd35b06 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -1,4 +1,6 @@
 #include qcom-msm8974.dtsi
+#include qcom-pm8841.dtsi
+#include qcom-pm8941.dtsi

 / {
model = Sony Xperia Z1;
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi 
b/arch/arm/boot/dts/qcom-pm8841.dtsi
new file mode 100644
index 000..45b5eaf
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -0,0 +1,18 @@
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+   usid4: pm8841@4 {
+   compatible = qcom,pm8841, qcom,spmi-pmic;
+   reg = 0x4 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+
+   usid5: pm8841@5 {
+   compatible = qcom,pm8841, qcom,spmi-pmic;
+   reg = 0x5 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi 
b/arch/arm/boot/dts/qcom-pm8941.dtsi
new file mode 100644
index 000..78069f5
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -0,0 +1,18 @@
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+   usid0: pm8941@0 {
+   compatible = qcom,pm8941, qcom,spmi-pmic;
+   reg = 0x0 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+
+   usid1: pm8941@1 {
+   compatible = qcom,pm8941, qcom,spmi-pmic;
+   reg = 0x1 SPMI_USID;
+   #address-cells = 1;
+   #size-cells = 1;
+   };
+};
--
1.9.1

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Re: [PATCH v4 1/1] extcon: usb-gpio: Introduce gpio usb extcon driver

[Ivan T. Ivanov]

Hi, 

On Mon, 2015-02-02 at 12:21 +0200, Roger Quadros wrote:
 This driver observes the USB ID pin connected over a GPIO and
 updates the USB cable extcon states accordingly.
 
 The existing GPIO extcon driver is not suitable for this purpose
 as it needs to be taught to understand USB cable states and it
 can't handle more than one cable per instance.
 
 For the USB case we need to handle 2 cable states.
 1) USB (attach/detach)
 2) USB-HOST (attach/detach)
 
 This driver can be easily updated in the future to handle VBUS
 events in case it happens to be available on GPIO for any platform.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 ---
 v4:
 - got rid of id_irqwake flag. Fail if enable/disable_irq_wake() fails
 - changed host cable name to USB-HOST

I am sorry that I am getting a bit little late into this.

Isn't supposed that we have to use strings defined in 
const char extcon_cable_name[][]?


 +
 +/* List of detectable cables */
 +enum {
 +   EXTCON_CABLE_USB = 0,
 +   EXTCON_CABLE_USB_HOST,
 +

Same here: duplicated with enum extcon_cable_name

 +   EXTCON_CABLE_END,
 +};
 +
 +static const char *usb_extcon_cable[] = {
 +   [EXTCON_CABLE_USB] = USB,
 +   [EXTCON_CABLE_USB_HOST] = USB-HOST,
 +   NULL,
 +};
 

snip

 +
 +static int usb_extcon_probe(struct platform_device *pdev)
 +{
 

snip

 +
 +   ret = devm_request_threaded_irq(dev, info-id_irq, NULL,
 +   usb_irq_handler,
 +   IRQF_TRIGGER_RISING |
 +   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,

Shouldn't triggers be defined in DTS files?


Regards,
Ivan

 
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Re: [PATCH v4 1/1] extcon: usb-gpio: Introduce gpio usb extcon driver

[Ivan T. Ivanov]

Hi Roger, 

On Mon, 2015-03-16 at 15:11 +0200, Roger Quadros wrote:
 Hi Ivan,
 
 On 16/03/15 14:32, Ivan T. Ivanov wrote:
  Hi,
  
  On Mon, 2015-02-02 at 12:21 +0200, Roger Quadros wrote:
   This driver observes the USB ID pin connected over a GPIO and
   updates the USB cable extcon states accordingly.
   
   The existing GPIO extcon driver is not suitable for this purpose
   as it needs to be taught to understand USB cable states and it
   can't handle more than one cable per instance.
   
   For the USB case we need to handle 2 cable states.
   1) USB (attach/detach)
   2) USB-HOST (attach/detach)
   
   This driver can be easily updated in the future to handle VBUS
   events in case it happens to be available on GPIO for any platform.
   
   Signed-off-by: Roger Quadros rog...@ti.com
   ---
   v4:
   - got rid of id_irqwake flag. Fail if enable/disable_irq_wake() fails
   - changed host cable name to USB-HOST
  
  I am sorry that I am getting a bit little late into this.
  
  Isn't supposed that we have to use strings defined in
  const char extcon_cable_name[][]?
  
  
   +
   +/* List of detectable cables */
   +enum {
   +   EXTCON_CABLE_USB = 0,
   +   EXTCON_CABLE_USB_HOST,
   +
  
  Same here: duplicated with enum extcon_cable_name
  
   +   EXTCON_CABLE_END,
   +};
   +
   +static const char *usb_extcon_cable[] = {
   +   [EXTCON_CABLE_USB] = USB,
   +   [EXTCON_CABLE_USB_HOST] = USB-HOST,
   +   NULL,
   +};
 
 I'm not exactly sure how else it is supposed to work if we
 support only a subset of cables from the global extcon_cable_name[][].

I don't see issue that we use just 2 events. I think that we can
reuse  enum extcon_cable_name and strings already defined in 
extcon_cable_name[][] global variable. It is defined extern in
extcon.h file exactly for this purpose, no?

 
  
  snip
  
   +
   +static int usb_extcon_probe(struct platform_device *pdev)
   +{
   
  
  snip
  
   +
   +   ret = devm_request_threaded_irq(dev, info-id_irq, NULL,
   +   usb_irq_handler,
   +   IRQF_TRIGGER_RISING |
   +   IRQF_TRIGGER_FALLING | 
   IRQF_ONESHOT,
  
  Shouldn't triggers be defined in DTS files?
 
 Could be but we're sure that we always need the trigger for both 
 rising/falling edges
 in this case. So the usage is more appropriately decided from application 
 point of view
 rather than h/w point of view. h/w is generic GPIO.

No strong opinion on this. Could it be that GPIO did't support edge
triggered interrupt, but just level triggered?

Regards,
Ivan

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Re: [PATCH v4] spi: qup: Add DMA capabilities

[Ivan T. Ivanov]

On Wed, 2015-03-04 at 12:02 +0200, Stanimir Varbanov wrote:
 From: Andy Gross agr...@codeaurora.org
 
 This patch adds DMA capabilities to the spi-qup driver.  If DMA channels are
 present, the QUP will use DMA instead of block mode for transfers to/from SPI
 peripherals for transactions larger than the length of a block.
 
 Signed-off-by: Andy Gross agr...@codeaurora.org
 Signed-off-by: Stanimir Varbanov varba...@linaro.org

Reviewed-by: Ivan T. Ivanov iiva...@mm-sol.com

Tested on top of Archit's DMA patch[1].

Thanks,
Ivan

[1] https://lkml.org/lkml/2015/1/22/52

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Re: [PATCH v2] mfd: Add specific compatible strings for Qualcomm's SPMI PMIC's

[Ivan T. Ivanov]

On Wed, 2015-03-04 at 11:05 -0800, Stephen Boyd wrote:
 On 03/04/15 02:19, Ivan T. Ivanov wrote:
  +
  +static const struct of_device_id pmic_spmi_id_table[] = {
  +   [COMMON_SUBTYPE]  = { .compatible = qcom,spmi-pmic },
  +   [PM8941_SUBTYPE]  = { .compatible = qcom,pm8941 },
  +   [PM8841_SUBTYPE]  = { .compatible = qcom,pm8841 },
  +   [PM8019_SUBTYPE]  = { .compatible = qcom,pm8019 },
  +   [PM8226_SUBTYPE]  = { .compatible = qcom,pm8226 },
  +   [PM8110_SUBTYPE]  = { .compatible = qcom,pm8110 },
  +   [PMA8084_SUBTYPE] = { .compatible = qcom,pma8084 },
  +   [PMI8962_SUBTYPE] = { .compatible = qcom,pmi8962 },
  +   [PMD9635_SUBTYPE] = { .compatible = qcom,pmd9635 },
  +   [PM8994_SUBTYPE]  = { .compatible = qcom,pm8994 },
  +   [PMI8994_SUBTYPE] = { .compatible = qcom,pmi8994 },
  +   [PM8916_SUBTYPE]  = { .compatible = qcom,pm8916 },
  +   [PM8004_SUBTYPE]  = { .compatible = qcom,pm8004 },
  +   [PM8909_SUBTYPE]  = { .compatible = qcom,pm8909 },
  +   { }
  +};
 
 Also this seems error prone in the case where we may have skips between
 pmic model numbers and then the of_device_id table is going to have a
 sentinel in the middle of the table. It's probably better to store the
 subtype number in the data field and iterate over the array.

True. Will reorganize.

Thanks,
Ivan
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Re: [PATCH v2] mfd: Add specific compatible strings for Qualcomm's SPMI PMIC's

[Ivan T. Ivanov]

On Wed, 2015-03-04 at 11:01 -0800, Stephen Boyd wrote:
 On 03/04/15 02:19, Ivan T. Ivanov wrote:
  diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c
  index 4b8beb2..a1af4e5 100644
  --- a/drivers/mfd/qcom-spmi-pmic.c
  +++ b/drivers/mfd/qcom-spmi-pmic.c
  
  +
  +static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
  +{
  +   unsigned int rev2, minor, major, type, subtype;
  +   int ret;
  +
  +   ret = regmap_read(map, PMIC_TYPE, type);
  +   if (ret  0)
  +   return;
  +
  +   if (type != PMIC_TYPE_VALUE)
  +   return;
  +
  +   ret = regmap_read(map, PMIC_SUBTYPE, subtype);
  +   if (ret  0)
  +   return;
  +
  +   if (subtype  ARRAY_SIZE(pmic_spmi_id_table))
  +   return;
  +
  +   rev2 = regmap_read(map, PMIC_REV2, rev2);
 
 ret = ?

Ouch. will fix.

 
  
  +
  +   dev_info(dev, %s-v%d.%d detected\n,
  +   pmic_spmi_id_table[subtype].compatible, major, 
  minor);
  +}
  
 
 I wonder if this should be dev_dbg.

It is not so much verbose, right? I could cut detected. I will like to keep 
it.

Thanks, 
Ivan
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Re: [PATCH v3] spi: qup: Add DMA capabilities

[Ivan T. Ivanov]

Hi Stan,

It looks good now, except it doesn't apply and two small issues below:

On Fri, 2015-02-27 at 18:58 +0200, Stanimir Varbanov wrote:
 From: Andy Gross agr...@codeaurora.org
 
 This patch adds DMA capabilities to the spi-qup driver.  If DMA channels are
 present, the QUP will use DMA instead of block mode for transfers to/from SPI
 peripherals for transactions larger than the length of a block.
 
 Signed-off-by: Andy Gross agr...@codeaurora.org
 Signed-off-by: Stanimir Varbanov varba...@linaro.org
 ---
 
 v2 - v3
  - now using one dma done callback on rx channel if bidirectional transfer
and on tx channel if only transmit transfer
  - rearranged the spi_qup_transfer_one() in order to reuse wait for
completion and completion init code
  - move dma init function early in .probe to avoid controller reset if
probe deffer
  - add function to get controller mode

snip

 
 +
 +static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
 +{
 

snip

 +
 +   /* set DMA parameters */
 +   rx_conf-direction = DMA_DEV_TO_MEM;
 +   rx_conf-device_fc = 1;

Strictly speeching this is a bool not int.

 +   rx_conf-src_addr = base + QUP_INPUT_FIFO;
 +   rx_conf-src_maxburst = spi-in_blk_sz;
 +
 +   tx_conf-direction = DMA_MEM_TO_DEV;
 +   tx_conf-device_fc = 1;

Same here.


 @@ -553,6 +813,8 @@ static int spi_qup_probe(struct platform_device *pdev)
 master-transfer_one = spi_qup_transfer_one;
 master-dev.of_node = pdev-dev.of_node;
 master-auto_runtime_pm = true;
 +   master-dma_alignment = dma_get_cache_alignment();
 +   master-max_dma_len = SPI_MAX_DMA_XFER;
 
 platform_set_drvdata(pdev, master);
 
 @@ -564,6 +826,12 @@ static int spi_qup_probe(struct platform_device *pdev)
 controller-cclk = cclk;
 controller-irq = irq;
 
 +   ret = spi_qup_init_dma(master, res-start);
 +   if (ret == -EPROBE_DEFER)
 +   goto error;
 +   else if (!ret)
 +   master-can_dma = spi_qup_can_dma;
 +
 /* set v1 flag if device is version 1 */
 if (of_device_is_compatible(dev-of_node, qcom,spi-qup-v1.1.1))
 controller-qup_v1 = 1;

It is not visible from this patch, but in case of error reseting
SPI controller (QUP_STATE_RESET), exit error path should be 
'error_dma' and not 'error' label.

 @@ -624,7 +892,7 @@ static int spi_qup_probe(struct platform_device *pdev)
 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
   
   
 IRQF_TRIGGER_HIGH, pdev-name, controller);
 if (ret)
 -   goto error;
 +   goto error_dma;
 
 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
 pm_runtime_use_autosuspend(dev);
 @@ -639,6 +907,8 @@ static int spi_qup_probe(struct platform_device *pdev)
 
  disable_pm:
 pm_runtime_disable(pdev-dev);
 +error_dma:
 +   spi_qup_release_dma(master);
  error:
 clk_disable_unprepare(cclk);
 clk_disable_unprepare(iclk);
 @@ -730,6 +1000,8 @@ static int spi_qup_remove(struct platform_device *pdev)
 if (ret)
 return ret;
 
 +   spi_qup_release_dma(master);
 +
 clk_disable_unprepare(controller-cclk);
 clk_disable_unprepare(controller-iclk);
 

Regards,
Ivan



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