[PATCH 0/6] Add support for MAXIM MAX77620/MAX20024 PMIC
Add SW support for MAXIM Semiconductor's Power Management IC (PMIC) MAX77620/MAX20024. This PMIC supports DC-DC/LDOS, GPIOs, RTC, watchdog, clocks etc. This series add respective driver for each of sub-modules. Laxman Dewangan (6): DT: mfd: add device-tree binding doc fro PMIC max77620/max20024 mfd: max77620: add core driver for MAX77620/MAX20024 pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024 gpio: max77620: add gpio driver for MAX77620/MAX20024 rtc: max77620: add support for max77620/max20024 RTC driver regulator: max77620: add regulator driver for max77620/max20024 Documentation/devicetree/bindings/mfd/max77620.txt | 383 +++ drivers/gpio/Kconfig |9 + drivers/gpio/Makefile |1 + drivers/gpio/gpio-max77620.c | 330 ++ drivers/mfd/Kconfig| 15 + drivers/mfd/Makefile |1 + drivers/mfd/max77620.c | 926 + drivers/pinctrl/Kconfig| 10 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-max77620.c | 700 + drivers/regulator/Kconfig |9 + drivers/regulator/Makefile |1 + drivers/regulator/max77620-regulator.c | 1062 drivers/rtc/Kconfig|9 + drivers/rtc/Makefile |1 + drivers/rtc/rtc-max77620.c | 574 +++ include/dt-bindings/mfd/max77620.h | 38 + include/linux/mfd/max77620.h | 503 + 18 files changed, 4573 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt create mode 100644 drivers/gpio/gpio-max77620.c create mode 100644 drivers/mfd/max77620.c create mode 100644 drivers/pinctrl/pinctrl-max77620.c create mode 100644 drivers/regulator/max77620-regulator.c create mode 100644 drivers/rtc/rtc-max77620.c create mode 100644 include/dt-bindings/mfd/max77620.h create mode 100644 include/linux/mfd/max77620.h -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2] regulator: max8973: add support for junction thermal warning
The driver MAX8973 supports the driver for Maxim PMIC MAX77621.
MAX77621 supports the junction temp warning at 120 degC and
140 degC which is configurable. It generates alert signal when
junction temperature crosses these threshold.
MAX77621 does not support the continuous temp monitoring of
junction temperature. It just report whether junction temperature
crossed the threshold or not.
Add support to
- Configure junction temp warning threshold via DT property
to generate alert when it crosses the threshold.
- Add support to interrupt the host from this device when alert
occurred.
- read the junction temp via thermal framework.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Remove irq flags from DT
- More details about supported temp by MAX77621
.../bindings/regulator/max8973-regulator.txt | 5 +
drivers/regulator/max8973-regulator.c | 140 -
include/linux/regulator/max8973-regulator.h| 4 +
3 files changed, 147 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
index f80ea2f..93f9939 100644
--- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -31,6 +31,11 @@ Optional properties:
property is available then etr will be enable default.
Enhanced transient response (ETR) will affect the configuration of CKADV.
+-maxim,junction-temp-warning: Junction temp warning on which device generates
+ warning interrupts. This is in millicelcius.
+
+Please note that thermal functionality is only supported on MAX77621. The
+threshold warning supported by MAX77621 are 120 degC and 140 degC.
Example:
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 5b75b7c..4640d1b 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -38,6 +38,9 @@
#include
#include
#include
+#include
+#include
+#include
/* Register definitions */
#define MAX8973_VOUT 0x0
@@ -74,6 +77,7 @@
#define MAX8973_WDTMR_ENABLE BIT(6)
#define MAX8973_DISCH_ENBABLE BIT(5)
#define MAX8973_FT_ENABLE BIT(4)
+#define MAX77621_T_JUNCTION_120BIT(7)
#define MAX8973_CKKADV_TRIP_MASK 0xC
#define MAX8973_CKKADV_TRIP_DISABLE0xC
@@ -93,6 +97,13 @@
#define MAX8973_VOLATGE_STEP 6250
#define MAX8973_BUCK_N_VOLTAGE 0x80
+#define MAX77621_CHIPID_TJINT_SBIT(0)
+
+#define MAX77621_NORMAL_OPERATING_TEMP 10
+#define MAX77621_TJINT_WARNING_TEMP_12012
+#define MAX77621_TJINT_WARNING_TEMP_14014
+
+
enum device_id {
MAX8973,
MAX77621
@@ -112,6 +123,9 @@ struct max8973_chip {
int curr_gpio_val;
struct regulator_ops ops;
enum device_id id;
+ int junction_temp_warning;
+ int irq;
+ struct thermal_zone_device *tz_device;
};
/*
@@ -391,6 +405,10 @@ static int max8973_init_dcdc(struct max8973_chip *max,
if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
control1 |= MAX8973_FREQSHIFT_9PER;
+ if ((max->id == MAX77621) && (pdata->junction_temp_warning ==
+ MAX77621_TJINT_WARNING_TEMP_120))
+ control2 |= MAX77621_T_JUNCTION_120;
+
if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
control2 |= MAX8973_DISCH_ENBABLE;
@@ -457,6 +475,100 @@ static int max8973_init_dcdc(struct max8973_chip *max,
return ret;
}
+#ifdef CONFIG_THERMAL_OF
+static int max8973_thermal_read_temp(void *data, int *temp)
+{
+ struct max8973_chip *mchip = data;
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(mchip->regmap, MAX8973_CHIPID1, &val);
+ if (ret < 0) {
+ dev_err(mchip->dev, "register CHIPID1 read failed, %d", ret);
+ return ret;
+ }
+
+ /* +1 degC to trigger cool devive */
+ if (val & MAX77621_CHIPID_TJINT_S)
+ *temp = mchip->junction_temp_warning + 1000;
+ else
+ *temp = MAX77621_NORMAL_OPERATING_TEMP;
+
+ return 0;
+}
+
+static irqreturn_t max8973_thermal_irq(int irq, void *data)
+{
+ struct max8973_chip *mchip = data;
+
+ dev_info(mchip->dev, "Junction Temp warning occurred\n");
+ thermal_zone_device_update(mchip->tz_device,
+ THERMAL_DEVICE_EVENT_THRESHOLD);
+ return IRQ_HANDLED;
+}
+
+static con
Re: [PATCH 1/1] regulator: max8973: add support for junction thermal warning
On Wednesday 06 January 2016 07:55 PM, Rob Herring wrote: On Wed, Jan 06, 2016 at 12:37:35PM +, Mark Brown wrote: On Wed, Jan 06, 2016 at 05:49:22PM +0530, Laxman Dewangan wrote: On Wednesday 06 January 2016 05:48 PM, Mark Brown wrote: * PGP Signed by an unknown key On Wed, Jan 06, 2016 at 11:45:22AM +0530, Laxman Dewangan wrote: Enhanced transient response (ETR) will affect the configuration of CKADV. +-maxim,junction-temp-warning: Junction temp warning on which device generates + warning interrupts. This needs to specify what the values are - it looks like it's raw register values but I'd have expected from this that it'd be an actual temperature. I tried to roundoff to the next higher threshold when supported value (120 or 140 degC) is not provided in driver. But it is fine to me to specify the possible value setting here and DT binding doc. Will do on next patch. I don't really mind which you use so long as the documentation is clear. I prefer that degrees are used rather than register values. From DT/platform, any values can be passed. Driver will round off to next higher side. The document details will only provide what is supported by the PMIC device. E.g. It can pass to ,<=120C and driver will set nearest threshold which is 120C. If it is >120C then it will set to 140C. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] regulator: max8973: add support for junction thermal warning
On Wednesday 06 January 2016 06:07 PM, Mark Brown wrote: * PGP Signed by an unknown key In one of design, interrupt from MAX77620, and alert from both MAX77621 shorted and going to Arm GIC controller. On this case, I need to register the interrupt as SHARED interrupt. This property can not be passed via "interrupt" properties from DT. That's why this flag is added to support this. If the driver supports shared interrupts it should just register as a shared interrupt all the time, there is nothing about shared interrupts which requires that the pin actually be shared. Now, by default, if I register the interrupt as SHARED in driver then it failed on second design as GPIO does not offer to register as SHARED interrupt. What makes you say that this would fail? The failure was due to the mismatch flags when registering interrupts. I used flag as ONESHOT, TRIGGER Type and SHARED. I experimented as make the interrupt flag as SHARED all places (and ONESHOT always) so that all interrupt flag same for all registration on both design. This way it works fine. It success on GPIO based flag also. Now I am passing SHARED | ONESHOT on both driver interrupt registration. I will drop the interrupt flag option from DT on next patch. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] regulator: max8973: add support for junction thermal warning
On Wednesday 06 January 2016 05:48 PM, Mark Brown wrote: * PGP Signed by an unknown key On Wed, Jan 06, 2016 at 11:45:22AM +0530, Laxman Dewangan wrote: Enhanced transient response (ETR) will affect the configuration of CKADV. +-maxim,junction-temp-warning: Junction temp warning on which device generates + warning interrupts. This needs to specify what the values are - it looks like it's raw register values but I'd have expected from this that it'd be an actual temperature. I tried to roundoff to the next higher threshold when supported value (120 or 140 degC) is not provided in driver. But it is fine to me to specify the possible value setting here and DT binding doc. Will do on next patch. +-interrupt-flags: Interrupt flags for registering interrupt which can not be + passed via interrupt properties. Why is this being specified and what are the values? Most devices don't have this... I have two different design with this device: In both design, I have main PMIC like MAX77620 and two MAX77621. In one of design, interrupt from MAX77620, and alert from both MAX77621 shorted and going to Arm GIC controller. On this case, I need to register the interrupt as SHARED interrupt. This property can not be passed via "interrupt" properties from DT. That's why this flag is added to support this. On other design, interrupt from all devices are going to different pins, MAX77620 to ARM GIC and MAX77621 to different gpio pins. On this case, interrupt are not SHARED. Now, by default, if I register the interrupt as SHARED in driver then it failed on second design as GPIO does not offer to register as SHARED interrupt. To support both design, I have added flag properties and passed from DT. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] ARM: dts: omap5-board-common: enable rtc and charging of backup battery
On Wednesday 06 January 2016 01:12 PM, H. Nikolaus Schaller wrote:
Hi,
Am 06.01.2016 um 00:40 schrieb Nishanth Menon :
On 01/05/2016 06:01 AM, H. Nikolaus Schaller wrote:
+ rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 IRQ_TYPE_NONE>;
IRQ_TYPE_NONE is not correct here -> it should have some polarity - if
it had none, there'd be no interrupt, right?
Well, it just translates IRQ_TYPE_NONE through
Linux/include/dt-bindings/interrupt-controller/irq.h
to
interrupts = <8 0>;
which is given as an example in
Documentation//devicetree/bindings/rtc/rtc-palmas.txt
Since I don't know anything about the rtc driver beyond the bindings
documentation I assume it is correct...
I have added Laxman Dewangan because he introduced this interrupts = <8 0>;
As this is for palmas interrupt controller, it does not use the second
field for interrupt from RTC.
So there is no really any polarity. It can be set to 0.
The second argument will be used for GPIOs mainly. However, support need
to be added on GPIO driver for rising/falling configuration.
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[PATCH 1/1] regulator: max8973: add support for junction thermal warning
The driver MAX8973 supports the driver for Maxim PMIC MAX77621.
MAX77621 supports the junction temp warning at 120 degC and
140 degC which is configurable. It generates alert signal when
junction temperature crosses these threshold.
MAX77621 does not support the continuous temp monitoring of
junction temperature. It just report whether junction temperature
crossed the threshold or not.
Add support to
- Configure junction temp warning threshold via DT property
to generate alert when it crosses the threshold.
- Add support to interrupt the host from this device when alert
occurred.
- read the junction temp via thermal framework.
Signed-off-by: Laxman Dewangan
---
.../bindings/regulator/max8973-regulator.txt | 6 +
drivers/regulator/max8973-regulator.c | 144 -
include/linux/regulator/max8973-regulator.h| 6 +
3 files changed, 154 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
index f80ea2f..88bf9b1 100644
--- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -31,6 +31,12 @@ Optional properties:
property is available then etr will be enable default.
Enhanced transient response (ETR) will affect the configuration of CKADV.
+-maxim,junction-temp-warning: Junction temp warning on which device generates
+ warning interrupts.
+-interrupt-flags: Interrupt flags for registering interrupt which can not be
+ passed via interrupt properties.
+
+Please note that thermal functionality is only supported on MAX77621.
Example:
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 5b75b7c..6ffb3ac 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -38,6 +38,9 @@
#include
#include
#include
+#include
+#include
+#include
/* Register definitions */
#define MAX8973_VOUT 0x0
@@ -74,6 +77,7 @@
#define MAX8973_WDTMR_ENABLE BIT(6)
#define MAX8973_DISCH_ENBABLE BIT(5)
#define MAX8973_FT_ENABLE BIT(4)
+#define MAX77621_T_JUNCTION_120BIT(7)
#define MAX8973_CKKADV_TRIP_MASK 0xC
#define MAX8973_CKKADV_TRIP_DISABLE0xC
@@ -93,6 +97,13 @@
#define MAX8973_VOLATGE_STEP 6250
#define MAX8973_BUCK_N_VOLTAGE 0x80
+#define MAX77621_CHIPID_TJINT_SBIT(0)
+
+#define MAX77621_NORMAL_OPERATING_TEMP 10
+#define MAX77621_TJINT_WARNING_TEMP_12012
+#define MAX77621_TJINT_WARNING_TEMP_14014
+
+
enum device_id {
MAX8973,
MAX77621
@@ -112,6 +123,10 @@ struct max8973_chip {
int curr_gpio_val;
struct regulator_ops ops;
enum device_id id;
+ int junction_temp_warning;
+ int irq;
+ unsigned long irq_flags;
+ struct thermal_zone_device *tz_device;
};
/*
@@ -391,6 +406,10 @@ static int max8973_init_dcdc(struct max8973_chip *max,
if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
control1 |= MAX8973_FREQSHIFT_9PER;
+ if ((max->id == MAX77621) && (pdata->junction_temp_warning ==
+ MAX77621_TJINT_WARNING_TEMP_120))
+ control2 |= MAX77621_T_JUNCTION_120;
+
if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
control2 |= MAX8973_DISCH_ENBABLE;
@@ -457,6 +476,94 @@ static int max8973_init_dcdc(struct max8973_chip *max,
return ret;
}
+#ifdef CONFIG_THERMAL_OF
+static int max8973_thermal_read_temp(void *data, int *temp)
+{
+ struct max8973_chip *mchip = data;
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(mchip->regmap, MAX8973_CHIPID1, &val);
+ if (ret < 0) {
+ dev_err(mchip->dev, "register CHIPID1 read failed, %d", ret);
+ return ret;
+ }
+
+ /* +1 degC to trigger cool devive */
+ if (val & MAX77621_CHIPID_TJINT_S)
+ *temp = mchip->junction_temp_warning + 1000;
+ else
+ *temp = MAX77621_NORMAL_OPERATING_TEMP;
+
+ return 0;
+}
+
+static irqreturn_t max8973_thermal_irq(int irq, void *data)
+{
+ struct max8973_chip *mchip = data;
+
+ dev_info(mchip->dev, "Junction Temp warning occurred\n");
+ thermal_zone_device_update(mchip->tz_device);
+ return IRQ_HANDLED;
+}
+
+static const struct thermal_zone_of_device_ops max77621_tz_ops = {
+ .get_temp = max8973_the
Re: [PATCH v2 2/3] iio:adc:palmas: add DT support
On Monday 05 October 2015 11:44 AM, H. Nikolaus Schaller wrote: From: Marek Belisko Code was found at: https://android.googlesource.com/kernel/tegra/+/a90856a6626d502d42c6e7abccbdf9d730b36270%5E%21/#F1 Signed-off-by: Laxman Dewangan [Fixed minor typos + add channels list to documentation] Signed-off-by: Marek Belisko --- Acked-by: Laxman Dewangan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/3] iio:adc: add iio driver for Palmas (twl6035/7) gpadc
On Monday 05 October 2015 11:44 AM, H. Nikolaus Schaller wrote: This driver code was found as: https://android.googlesource.com/kernel/tegra/+/aaabb2e045f31e5a970109ffdaae900dd403d17e/drivers/staging/iio/adc Fixed various compilation issues and test this driver on omap5 evm. Signed-off-by: Pradeep Goudagunta Signed-off-by: H. Nikolaus Schaller Signed-off-by: Marek Belisko Acked-by: Laxman Dewangan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] regulator: max8973: add support to configure ETR from DT
The MAX8973/MAX77621 feature an Enhanced Transient Response(ETR)
circuit that is enabled through software. The enhanced transient
response reduces the voltage droop during large load steps by
temporarily allowing all three phases to fire in unison, slewing
total inductor current faster than would normally be possible if
all three phases continued to operate 120deg out of phase. The
enhanced transient response detector features two selectable
sensitivity settings, which select the output voltage slew rate
during load transients that triggers the ETR circuit. The sensitivity
of the ETR detector is set by the CKADV[1:0] bits in the CONTROL2
register.
Add support to configure the ETR through platform data from DT.
Update the DT binding document accordingly.
Signed-off-by: Laxman Dewangan
---
.../bindings/regulator/max8973-regulator.txt | 6 ++
drivers/regulator/max8973-regulator.c | 19 +++
2 files changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
index 55efb24..f80ea2f 100644
--- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -25,6 +25,12 @@ Optional properties:
-maxim,enable-frequency-shift: boolean, enable 9% frequency shift.
-maxim,enable-bias-control: boolean, enable bias control. By enabling this
startup delay can be reduce to 20us from 220us.
+-maxim,enable-etr: boolean, enable Enhanced Transient Response.
+-maxim,enable-high-etr-sensitivity: boolean, Enhanced transient response
+ circuit is enabled and set for high sensitivity. If this
+ property is available then etr will be enable default.
+
+Enhanced transient response (ETR) will affect the configuration of CKADV.
Example:
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index e94ddcf..a8fd7f4 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -421,6 +421,8 @@ static struct max8973_regulator_platform_data
*max8973_parse_dt(
struct device_node *np = dev->of_node;
int ret;
u32 pval;
+ bool etr_enable;
+ bool etr_sensitivity_high;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
@@ -452,6 +454,23 @@ static struct max8973_regulator_platform_data
*max8973_parse_dt(
if (of_property_read_bool(np, "maxim,enable-bias-control"))
pdata->control_flags |= MAX8973_CONTROL_BIAS_ENABLE;
+ etr_enable = of_property_read_bool(np, "maxim,enable-etr");
+ etr_sensitivity_high = of_property_read_bool(np,
+ "maxim,enable-high-etr-sensitivity");
+ if (etr_sensitivity_high)
+ etr_enable = true;
+
+ if (etr_enable) {
+ if (etr_sensitivity_high)
+ pdata->control_flags |=
+ MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US;
+ else
+ pdata->control_flags |=
+ MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US;
+ } else {
+ pdata->control_flags |= MAX8973_CONTROL_CLKADV_TRIP_DISABLED;
+ }
+
return pdata;
}
--
2.1.4
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[PATCH 3/3] regulator: max8973: add support to configure ETR based on rail load
Add support to configure Enhanced Transient Response Enable (ETR)
and Sensitivity Selection based on maximum current i.e. expected
load on that rail.
Maxim recommended as:
- Enable ETR with high sensitivity (75mV/us) for 0 to 9A expected loads,
- Enable ETR with low sensitivity (150mV/us) for 9A to 12A expected loads.
- Disable ETR for expected load > 12A.
These recommendation will be configured for MAX77621 when maximum load
is provided through regulator constraint for maximum current from platform.
Signed-off-by: Laxman Dewangan
---
drivers/regulator/max8973-regulator.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index a8fd7f4..f673659 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -75,6 +75,7 @@
#define MAX8973_DISCH_ENBABLE BIT(5)
#define MAX8973_FT_ENABLE BIT(4)
+#define MAX8973_CKKADV_TRIP_MASK 0xC
#define MAX8973_CKKADV_TRIP_DISABLE0xC
#define MAX8973_CKKADV_TRIP_75mV_PER_US0x0
#define MAX8973_CKKADV_TRIP_150mV_PER_US 0x4
@@ -282,6 +283,55 @@ static int max8973_set_ramp_delay(struct regulator_dev
*rdev,
return ret;
}
+static int max8973_set_current_limit(struct regulator_dev *rdev,
+ int min_ua, int max_ua)
+{
+ struct max8973_chip *max = rdev_get_drvdata(rdev);
+ unsigned int val;
+ int ret;
+
+ if (max_ua <= 900)
+ val = MAX8973_CKKADV_TRIP_75mV_PER_US;
+ else if (max_ua <= 1200)
+ val = MAX8973_CKKADV_TRIP_150mV_PER_US;
+ else
+ val = MAX8973_CKKADV_TRIP_DISABLE;
+
+ ret = regmap_update_bits(max->regmap, MAX8973_CONTROL2,
+ MAX8973_CKKADV_TRIP_MASK, val);
+ if (ret < 0) {
+ dev_err(max->dev, "register %d update failed: %d\n",
+ MAX8973_CONTROL2, ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int max8973_get_current_limit(struct regulator_dev *rdev)
+{
+ struct max8973_chip *max = rdev_get_drvdata(rdev);
+ unsigned int control2;
+ int ret;
+
+ ret = regmap_read(max->regmap, MAX8973_CONTROL2, &control2);
+ if (ret < 0) {
+ dev_err(max->dev, "register %d read failed: %d\n",
+ MAX8973_CONTROL2, ret);
+ return ret;
+ }
+ switch (control2 & MAX8973_CKKADV_TRIP_MASK) {
+ case MAX8973_CKKADV_TRIP_DISABLE:
+ return 1500;
+ case MAX8973_CKKADV_TRIP_150mV_PER_US:
+ return 1200;
+ case MAX8973_CKKADV_TRIP_75mV_PER_US:
+ return 900;
+ default:
+ break;
+ }
+ return 900;
+}
+
static const struct regulator_ops max8973_dcdc_ops = {
.get_voltage_sel= max8973_dcdc_get_voltage_sel,
.set_voltage_sel= max8973_dcdc_set_voltage_sel,
@@ -632,6 +682,8 @@ static int max8973_probe(struct i2c_client *client,
max->ops.enable = regulator_enable_regmap;
max->ops.disable = regulator_disable_regmap;
max->ops.is_enabled = regulator_is_enabled_regmap;
+ max->ops.set_current_limit = max8973_set_current_limit;
+ max->ops.get_current_limit = max8973_get_current_limit;
break;
default:
break;
--
2.1.4
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[PATCH 1/3] regulator: max8973: Fix up control flag option for bias control
The control flag for the bias control is MAX8973_CONTROL_BIAS_ENABLE rather than MAX8973_BIAS_ENABLE which is macro for the bits in register. Fix this typo. Signed-off-by: Laxman Dewangan --- drivers/regulator/max8973-regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973-regulator.c index 6f2bdad..e94ddcf 100644 --- a/drivers/regulator/max8973-regulator.c +++ b/drivers/regulator/max8973-regulator.c @@ -450,7 +450,7 @@ static struct max8973_regulator_platform_data *max8973_parse_dt( pdata->control_flags |= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE; if (of_property_read_bool(np, "maxim,enable-bias-control")) - pdata->control_flags |= MAX8973_BIAS_ENABLE; + pdata->control_flags |= MAX8973_CONTROL_BIAS_ENABLE; return pdata; } -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] regulator: max8973: add support for MAX77621
Maxim MAX77621 device is high-efficiency, three-phase,
DC-DC step-down switching regulator delivers peak
output currents up to 16A. This device is extension of
MAX8973 and compatible with the register definition.
The MAX77621 has the SHUTDOWN pin which is EN pin on the
MAX8973. On MAX77621, the SHUTDOWN pin (active low) reset
device register to its POR/OTP value. The voltage output
is enabled when SHUTDONW pin is HIGH and EN bit on VOUT
register is HIGH.
For MAX8973, VOUT is enabled when EN bit or EN pin is high.
Add support of the MAX77621 device on max8973 regulator driver
with following changes:
- Make sure SHUTDOWN pin is set HIGH through GPIO calls if
GPIO from AP connected to SHUTDOWN pin provided.
- Enable/disable the rail through register access only.
Signed-off-by: Laxman Dewangan
---
.../bindings/regulator/max8973-regulator.txt | 4 +-
drivers/regulator/max8973-regulator.c | 104 +
2 files changed, 87 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
index 201a263..55efb24 100644
--- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -2,7 +2,9 @@
Required properties:
-- compatible: must be "maxim,max8973"
+- compatible: must be one of following:
+ "maxim,max8973"
+ "maxim,max77621".
- reg: the i2c slave address of the regulator. It should be 0x1b.
Any standard regulator properties can be used to configure the single max8973
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 663e4df..89e53e0 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -91,6 +92,11 @@
#define MAX8973_VOLATGE_STEP 6250
#define MAX8973_BUCK_N_VOLTAGE 0x80
+enum device_id {
+ MAX8973,
+ MAX77621
+};
+
/* Maxim 8973 chip information */
struct max8973_chip {
struct device *dev;
@@ -104,6 +110,7 @@ struct max8973_chip {
int curr_vout_reg;
int curr_gpio_val;
struct regulator_ops ops;
+ enum device_id id;
};
/*
@@ -390,7 +397,7 @@ static int max8973_init_dcdc(struct max8973_chip *max,
}
/* If external control is enabled then disable EN bit */
- if (max->enable_external_control) {
+ if (max->enable_external_control && (max->id == MAX8973)) {
ret = regmap_update_bits(max->regmap, MAX8973_VOUT,
MAX8973_VOUT_ENABLE, 0);
if (ret < 0)
@@ -448,6 +455,13 @@ static struct max8973_regulator_platform_data
*max8973_parse_dt(
return pdata;
}
+static const struct of_device_id of_max8973_match_tbl[] = {
+ { .compatible = "maxim,max8973", .data = (void *)MAX8973, },
+ { .compatible = "maxim,max77621", .data = (void *)MAX77621, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, of_max8973_match_tbl);
+
static int max8973_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -457,6 +471,7 @@ static int max8973_probe(struct i2c_client *client,
struct regulator_dev *rdev;
struct max8973_chip *max;
bool pdata_from_dt = false;
+ unsigned int chip_id;
int ret;
pdata = dev_get_platdata(&client->dev);
@@ -486,6 +501,27 @@ static int max8973_probe(struct i2c_client *client,
return ret;
}
+ if (client->dev.of_node) {
+ const struct of_device_id *match;
+
+ match = of_match_device(of_match_ptr(of_max8973_match_tbl),
+ &client->dev);
+ if (!match)
+ return -ENODATA;
+ max->id = (u32)((uintptr_t)match->data);
+ } else {
+ max->id = id->driver_data;
+ }
+
+ ret = regmap_read(max->regmap, MAX8973_CHIPID1, &chip_id);
+ if (ret < 0) {
+ dev_err(&client->dev, "register CHIPID1 read failed, %d", ret);
+ return ret;
+ }
+
+ dev_info(&client->dev, "CHIP-ID OTP: 0x%02x ID_M: 0x%02x\n",
+ (chip_id >> 4) & 0xF, (chip_id >> 1) & 0x7);
+
i2c_set_clientdata(client, max);
max->ops = max8973_dcdc_ops;
max->dev = &client->dev;
@@ -507,14 +543,6 @@ static int max8973_probe(struct i2c_client *client,
if (gpio_is_valid(max->enable_gpio))
max->enable_external_control = true;
-
[PATCH 1/2] regulator: max8973: configure ramp delay through callback
Regulator core framework support the configuration of ramp
delay reading from platform specific regulator data via the
regulator callback ops.
Instead of reading regulator init data on driver and setting
ramp delay, use the callback to achieve this.
Signed-off-by: Laxman Dewangan
---
drivers/regulator/max8973-regulator.c | 73 +++
1 file changed, 57 insertions(+), 16 deletions(-)
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 00cf91c..663e4df 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -67,6 +67,7 @@
#define MAX8973_RAMP_25mV_PER_US 0x1
#define MAX8973_RAMP_50mV_PER_US 0x2
#define MAX8973_RAMP_200mV_PER_US 0x3
+#define MAX8973_RAMP_MASK 0x3
/* MAX8973_CONTROL2 */
#define MAX8973_WDTMR_ENABLE BIT(6)
@@ -243,12 +244,45 @@ static unsigned int max8973_dcdc_get_mode(struct
regulator_dev *rdev)
REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
}
+static int max8973_set_ramp_delay(struct regulator_dev *rdev,
+ int ramp_delay)
+{
+ struct max8973_chip *max = rdev_get_drvdata(rdev);
+ unsigned int control;
+ int ret;
+ int ret_val;
+
+ /* Set ramp delay */
+ if (ramp_delay < 25000) {
+ control = MAX8973_RAMP_12mV_PER_US;
+ ret_val = 12000;
+ } else if (ramp_delay < 5) {
+ control = MAX8973_RAMP_25mV_PER_US;
+ ret_val = 25000;
+ } else if (ramp_delay < 20) {
+ control = MAX8973_RAMP_50mV_PER_US;
+ ret_val = 5;
+ } else {
+ control = MAX8973_RAMP_200mV_PER_US;
+ ret_val = 20;
+ }
+
+ ret = regmap_update_bits(max->regmap, MAX8973_CONTROL1,
+ MAX8973_RAMP_MASK, control);
+ if (ret < 0)
+ dev_err(max->dev, "register %d update failed, %d",
+ MAX8973_CONTROL1, ret);
+ return ret;
+}
+
static const struct regulator_ops max8973_dcdc_ops = {
.get_voltage_sel= max8973_dcdc_get_voltage_sel,
.set_voltage_sel= max8973_dcdc_set_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.set_mode = max8973_dcdc_set_mode,
.get_mode = max8973_dcdc_get_mode,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .set_ramp_delay = max8973_set_ramp_delay,
};
static int max8973_init_dcdc(struct max8973_chip *max,
@@ -257,6 +291,29 @@ static int max8973_init_dcdc(struct max8973_chip *max,
int ret;
uint8_t control1 = 0;
uint8_t control2 = 0;
+ unsigned int data;
+
+ ret = regmap_read(max->regmap, MAX8973_CONTROL1, &data);
+ if (ret < 0) {
+ dev_err(max->dev, "register %d read failed, err = %d",
+ MAX8973_CONTROL1, ret);
+ return ret;
+ }
+ control1 = data & MAX8973_RAMP_MASK;
+ switch (control1) {
+ case MAX8973_RAMP_12mV_PER_US:
+ max->desc.ramp_delay = 12000;
+ break;
+ case MAX8973_RAMP_25mV_PER_US:
+ max->desc.ramp_delay = 252000;
+ break;
+ case MAX8973_RAMP_50mV_PER_US:
+ max->desc.ramp_delay = 5;
+ break;
+ case MAX8973_RAMP_200mV_PER_US:
+ max->desc.ramp_delay = 20;
+ break;
+ }
if (pdata->control_flags & MAX8973_CONTROL_REMOTE_SENSE_ENABLE)
control1 |= MAX8973_SNS_ENABLE;
@@ -277,22 +334,6 @@ static int max8973_init_dcdc(struct max8973_chip *max,
if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
control1 |= MAX8973_FREQSHIFT_9PER;
- /* Set ramp delay */
- if (pdata->reg_init_data &&
- pdata->reg_init_data->constraints.ramp_delay) {
- if (pdata->reg_init_data->constraints.ramp_delay < 25000)
- control1 |= MAX8973_RAMP_12mV_PER_US;
- else if (pdata->reg_init_data->constraints.ramp_delay < 5)
- control1 |= MAX8973_RAMP_25mV_PER_US;
- else if (pdata->reg_init_data->constraints.ramp_delay < 20)
- control1 |= MAX8973_RAMP_50mV_PER_US;
- else
- control1 |= MAX8973_RAMP_200mV_PER_US;
- } else {
- control1 |= MAX8973_RAMP_12mV_PER_US;
- max->desc.ramp_delay = 12500;
- }
-
if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
control2 |
Re: [PATCH 3/3] regulator: max8973: add DT parsing of platform specific parameter
On Tuesday 21 April 2015 02:49 AM, Mark Brown wrote: * PGP Signed by an unknown key On Mon, Apr 20, 2015 at 06:24:17PM +0530, Laxman Dewangan wrote: +Optional properties: + +-maxim,externally-enable: boolean, externally control the regulator output + enable/disable. I'd have expected this to be enabled if a GPIO is provided to do the control rather than having a specific property for it. Curently there is no support for providing a GPIO for external control pins. I have follow on patch to support this as my platform control the EN pin of the device through GPIO. There is also case that the EN pin is controlled by the control signal from host power management controller directly and this control signal is not exported as GPIO. So we need this option to support on both cases. There is another device from Maxim, MAX77621, which is compatible on register with this device but it has converted the EN pin as SHTDN pin. I have follow on patches to support this device through this driver instead of duplicating the driver. MAX8973: Vout is enabled when EN pin OR EN bit on register is 1. MAX77621: Vout is enabled when EN pin AND EN bit on register is 1. If EN pin (renamed as SHTDN pin) goes low, it reset the entire register configuration. In our platform, we are using MAX77621 and SHTDN pin of MAX77621 is controlled through GPIO. On this case, we will use the GPIO as always HIGH and control Vout enable/disable through the register EN bit write otherwise, we will need to restore all configuration on each regulator enable. So on MAX77621 use, we will provide the GPIO for SHTDN pin to make it enable always and it will not be controlled externally, it will be controlled through register access. +-maxim,enable-falling-slew-rate: boolean, enable falling slew rate. +-maxim,enable-active-discharge: boolean: enable active discharge. +-maxim,enable-frequency-shift: boolean, enable 9% frequency shift. +-maxim,enable-bias-control: boolean, enable bias control. By enabling this + startup delay can be reduce to 20us from 220us. It looks like we should be implementing the set_ramp_delay() operation here? It is actually enable_time which changes with this bias enable/disable. So we need to provide desc->enable_time based on this flag. Currently it is missing on driver. I have few more patches, not sent because did not want to bulk the review and started with small changes which can be discussed easily. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] regulator: max8973: make default/unset dvs gpio as invalid gpio
On Tuesday 21 April 2015 02:45 AM, Mark Brown wrote: * PGP Signed by an unknown key On Mon, Apr 20, 2015 at 06:24:16PM +0530, Laxman Dewangan wrote: If platform data has dvs-gpio value 0 as default/unset then make this as invalid gpio so that function gpio_is_valid() can return false on this case. OK, so this handles the problem with the first patch - it should have been the first patch to help with review. Yaah, I realized after reading your comment on patch 1 that I should have on different sequence. Thanks for accepting the patches. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] regulator: max8973: get rid of extra variable for gpio validity
To find that dvs-gpio is valid or not, gpio API gpio_is_valid()
can be directly used instead of intermediate variable.
Removing the extra variable and using the gpio_is_valid().
Signed-off-by: Laxman Dewangan
---
This is same as earlier patch. Making this as part of this series.
drivers/regulator/max8973-regulator.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index c3d55c2..1890808 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -100,7 +100,6 @@ struct max8973_chip {
int curr_vout_val[MAX8973_MAX_VOUT_REG];
int curr_vout_reg;
int curr_gpio_val;
- bool valid_dvs_gpio;
struct regulator_ops ops;
};
@@ -174,7 +173,7 @@ static int max8973_dcdc_set_voltage_sel(struct
regulator_dev *rdev,
* If gpios are available to select the VOUT register then least
* recently used register for new configuration.
*/
- if (max->valid_dvs_gpio)
+ if (gpio_is_valid(max->dvs_gpio))
found = find_voltage_set_register(max, vsel,
&vout_reg, &gpio_val);
@@ -191,7 +190,7 @@ static int max8973_dcdc_set_voltage_sel(struct
regulator_dev *rdev,
}
/* Select proper VOUT register vio gpios */
- if (max->valid_dvs_gpio) {
+ if (gpio_is_valid(max->dvs_gpio)) {
gpio_set_value_cansleep(max->dvs_gpio, gpio_val & 0x1);
max->curr_gpio_val = gpio_val;
}
@@ -434,7 +433,6 @@ static int max8973_probe(struct i2c_client *client,
max->dvs_gpio, ret);
return ret;
}
- max->valid_dvs_gpio = true;
/*
* Initialize the lru index with vout_reg id
@@ -444,8 +442,6 @@ static int max8973_probe(struct i2c_client *client,
max->lru_index[i] = i;
max->lru_index[0] = max->curr_vout_reg;
max->lru_index[max->curr_vout_reg] = 0;
- } else {
- max->valid_dvs_gpio = false;
}
if (pdata) {
--
1.8.1.5
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[PATCH 2/3] regulator: max8973: make default/unset dvs gpio as invalid gpio
If platform data has dvs-gpio value 0 as default/unset then
make this as invalid gpio so that function gpio_is_valid()
can return false on this case.
Signed-off-by: Laxman Dewangan
---
As discussed on the patch
[PATCH] regulator: max8973: get rid of extra variable for gpio validity
Adding handling of unset/default gpio on platform data which is set as
0.
drivers/regulator/max8973-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 1890808..85fa2de 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -408,7 +408,7 @@ static int max8973_probe(struct i2c_client *client,
}
if (pdata) {
- max->dvs_gpio = pdata->dvs_gpio;
+ max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL;
max->enable_external_control = pdata->enable_ext_control;
max->curr_gpio_val = pdata->dvs_def_state;
max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state;
--
1.8.1.5
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[PATCH 3/3] regulator: max8973: add DT parsing of platform specific parameter
There are some platform specific parameter required to configure
the device like enable external control, DVS gpio etc.
Add DT parsing of such properties to make platform specific data.
Update DT binding doc accordingly.
Signed-off-by: Laxman Dewangan
---
.../bindings/regulator/max8973-regulator.txt | 14
drivers/regulator/max8973-regulator.c | 85 +-
2 files changed, 79 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
index 4f15d8a..f63de7d 100644
--- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -8,6 +8,20 @@ Required properties:
Any standard regulator properties can be used to configure the single max8973
DCDC.
+Optional properties:
+
+-maxim,externally-enable: boolean, externally control the regulator output
+ enable/disable.
+-maxim,dvs-gpio: GPIO which is connected to DVS pin of device.
+-maxim,dvs-default-state: Default state of GPIO during initialisation.
+ 1 for HIGH and 0 for LOW.
+-maxim,enable-remote-sense: boolean, enable reote sense.
+-maxim,enable-falling-slew-rate: boolean, enable falling slew rate.
+-maxim,enable-active-discharge: boolean: enable active discharge.
+-maxim,enable-frequency-shift: boolean, enable 9% frequency shift.
+-maxim,enable-bias-control: boolean, enable bias control. By enabling this
+ startup delay can be reduce to 20us from 220us.
+
Example:
max8973@1b {
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973-regulator.c
index 85fa2de..da7059c 100644
--- a/drivers/regulator/max8973-regulator.c
+++ b/drivers/regulator/max8973-regulator.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -360,6 +361,46 @@ static const struct regmap_config max8973_regmap_config = {
.cache_type = REGCACHE_RBTREE,
};
+static struct max8973_regulator_platform_data *max8973_parse_dt(
+ struct device *dev)
+{
+ struct max8973_regulator_platform_data *pdata;
+ struct device_node *np = dev->of_node;
+ int ret;
+ u32 pval;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return NULL;
+
+ pdata->enable_ext_control = of_property_read_bool(np,
+ "maxim,externally-enable");
+ pdata->dvs_gpio = of_get_named_gpio(np, "maxim,dvs-gpio", 0);
+
+ ret = of_property_read_u32(np, "maxim,dvs-default-state", &pval);
+ if (!ret)
+ pdata->dvs_def_state = pval;
+
+ if (of_property_read_bool(np, "maxim,enable-remote-sense"))
+ pdata->control_flags |= MAX8973_CONTROL_REMOTE_SENSE_ENABLE;
+
+ if (of_property_read_bool(np, "maxim,enable-falling-slew-rate"))
+ pdata->control_flags |=
+ MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE;
+
+ if (of_property_read_bool(np, "maxim,enable-active-discharge"))
+ pdata->control_flags |=
+ MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE;
+
+ if (of_property_read_bool(np, "maxim,enable-frequency-shift"))
+ pdata->control_flags |= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE;
+
+ if (of_property_read_bool(np, "maxim,enable-bias-control"))
+ pdata->control_flags |= MAX8973_BIAS_ENABLE;
+
+ return pdata;
+}
+
static int max8973_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -367,15 +408,24 @@ static int max8973_probe(struct i2c_client *client,
struct regulator_config config = { };
struct regulator_dev *rdev;
struct max8973_chip *max;
+ bool pdata_from_dt = false;
int ret;
pdata = dev_get_platdata(&client->dev);
- if (!pdata && !client->dev.of_node) {
+ if (!pdata && client->dev.of_node) {
+ pdata = max8973_parse_dt(&client->dev);
+ pdata_from_dt = true;
+ }
+
+ if (!pdata) {
dev_err(&client->dev, "No Platform data");
return -EIO;
}
+ if (pdata->dvs_gpio == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL);
if (!max)
return -ENOMEM;
@@ -399,7 +449,7 @@ static int max8973_probe(struct i2c_client *client,
max->desc.uV_step = MAX8973_VOLATGE_STEP;
max->desc.n_voltages = MAX8973_BUCK_N_VOLTAGE;
- if (!pdata || !pdata->enable_ext_control) {
+
[PATCH 0/3] regulator: max8973: cleanups and add DT parsing for platform data
Remove redundant variables for dvs gpio validity, handle unset/default dvs gpio and add DT parsing for platform data. Laxman Dewangan (3): regulator: max8973: get rid of extra variable for gpio validity regulator: max8973: make default/unset dvs gpio as invalid gpio regulator: max8973: add DT parsing of platform specific parameter .../bindings/regulator/max8973-regulator.txt | 14 drivers/regulator/max8973-regulator.c | 93 -- 2 files changed, 81 insertions(+), 26 deletions(-) -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] Input: gpio_keys - add device tree support for interrupt only keys
On Thursday 13 November 2014 04:35 PM, Arnd Bergmann wrote: On Thursday 13 November 2014 16:29:02 Laxman Dewangan wrote: Yes, I posted patch for interrupt key on context on key connected to PMIC-Onkey. On PMIC, there is onkey pin input which generates interrupt only when it toggles. So if we have key (power key on our platforms) connected to this pin then we will only get interrupt from PMIC. Instead of implementing full interrupt key driver, I added this support on existing gpio keys. So is this code still in place, and do you think it's worthwhile to have a DT binding for it? Could the PMIC register a gpio controller instead? This pin is not supported as GPIO and so exporting the functionality through GPIO is not feasible until we treat the onkey as GPIO pin without actual gpio functionality i..e only interrupt functionality. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] Input: gpio_keys - add device tree support for interrupt only keys
On Thursday 13 November 2014 04:30 PM, Arnd Bergmann wrote: On Thursday 13 November 2014 11:52:48 Alexander Stein wrote: On Thursday 13 November 2014 11:47:13, Arnd Bergmann wrote: Regarding your initial use case of testing interrupt polarity, would you have been able to do the same thing by looking at the interrupt count in /proc/interrupts? This is only possible if some driver actually requests this interrupt, no? Yes, I think that is correct, at least with sparseirq, which is now the default. For interrupts that are mapped by the irqchip, you can look up the number of spurious interrupts in /proc/irq//spurious. yes, I came across multiple PMIC(TPS65910, MAXIM, Ricoh) module which generates interrupt when their On-key pin get toggle. Key is connected with this pin of PMIC and for on-key driver, we are using the gpio-keys driver by passing interrupt number instead of complete new driver. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] Input: gpio_keys - add device tree support for interrupt only keys
On Thursday 13 November 2014 04:17 PM, Arnd Bergmann wrote:
On Thursday 13 November 2014 11:35:42 Alexander Stein wrote:
On Wednesday 12 November 2014 20:16:06, Arnd Bergmann wrote:
On Wednesday 12 November 2014 17:38:31 Alexander Stein wrote:
On Wednesday 12 November 2014 17:04:57, Arnd Bergmann wrote:
On Wednesday 12 November 2014 17:02:56 Alexander Stein wrote:
This features already exists for board config setups. Add support for
device tree based systems.
Signed-off-by: Alexander Stein
---
Please note: Due to current lack of hardware I could not test it yet. V2
includes the changes proposed by Dmitry.
Changes in v2:
* Added device tree bindings
* IRQ is only parsed and mapped when there is no "gpios" property
Can you list one or more examples in the patch description?
Are these systems that don't expose the GPIO controller with a
standalone driver, or systems that really actually connect the
buttons to an interrupt pin?
You mean a use case? I came to this situation to test interrupt polarity on a
microcontroller, thus a simple /IRQ pin, no GPIO at all. So in the end I have
an input just connected to an interrupt line.
I noticed gpio_keys using platform data only can be used for this setup. So I
added this support for device tree.
I meant a specific board file that uses this, which can't be converted
to DT without your change.
I've searched (hopefully) the complete arch/ tree on v3.18-rc4 for
struct gpio_keys_button and checked each occurrence. I didn't found
any usage of IRQ based input keys.
Ok, I see.
I notice that Laxman Dewangan initially added the feature as part of
(I assume) work on Tegra, but these days Tegra is DT-only so it can't
actually get used for that any more.
If we have a real usecase, I think we can still take your patch, but
my impression at the moment is that it may be better to instead
remove the feature entirely by reverting d8ee4a1c9052 ("Input:
gpio_keys - add support for interrupt only keys").
Regarding your initial use case of testing interrupt polarity, would
you have been able to do the same thing by looking at the interrupt
count in /proc/interrupts?
Yes, I posted patch for interrupt key on context on key connected to
PMIC-Onkey.
On PMIC, there is onkey pin input which generates interrupt only when it
toggles. So if we have key (power key on our platforms) connected to
this pin then we will only get interrupt from PMIC.
Instead of implementing full interrupt key driver, I added this support
on existing gpio keys.
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Re: [PATCH 1/2] regulator: userspace-consumer: add DT binding details
On Wednesday 30 July 2014 10:10 PM, Mark Brown wrote: * PGP Signed by an unknown key On Wed, Jul 30, 2014 at 04:53:03PM +0100, Mark Rutland wrote: On Wed, Jul 30, 2014 at 02:54:00PM +0100, Laxman Dewangan wrote: +Required properties: +- compatible : Must be "reg-userspace-consumer". I would never expect to see "userspace" in a DT beinding string; this is entirely a software abstraction description and has nothing to do with the interaction of HW components. Why do you think we need this in the DT? Yes, this is test code - it is not intended to be used in production. Any binding should be for the consumer using this, not for this implementation detail. We have the GPS module and its driver in the user space. There is no code for GPS on kernel. Just power on and open port from user space, get the information. On this case, how do we power on GPS module if we don't expose it? It need two power source for digital section and analog section. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] regulator: userspace-consumer: add DT binding details
Add DT binding document and details DT binding for the driver
regulator/userspace-consumer.
Signed-off-by: Laxman Dewangan
---
.../bindings/regulator/userspace-consumer.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/userspace-consumer.txt
diff --git a/Documentation/devicetree/bindings/regulator/userspace-consumer.txt
b/Documentation/devicetree/bindings/regulator/userspace-consumer.txt
new file mode 100644
index 000..73c651c
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/userspace-consumer.txt
@@ -0,0 +1,26 @@
+Userspace consumer regulators
+
+Required properties:
+- compatible : Must be "reg-userspace-consumer".
+- regulator-supplies: Supply names for this regulator. This can be
+ multiple strings.
+
+Optional properties:
+- regulator-name: Name of the consumer line.
+- regulator-boot-on: Enable regulator on booting.
+
+With all supply names, there should be -supply to pass regulators
+handle as defined in regulator.txt.
+
+Example:
+
+ userspace-consumer {
+ compatible = "reg-userspace-consumer";
+
+ regulator-name = "gps-consumer";
+ regulator-boot-on;
+ regulator-supplies = "vdd", "vcc", "vdd-3v3";
+ vdd-supply = <®1>;
+ vcc-supply = <®2>;
+ vdd-3v3-supply = <®3>;
+ };
--
1.8.1.5
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[PATCH 2/2] regulator: userspace-consumer: add DT support
Add DT support of the regulator driver userspace-consumer.
The supply names for this driver is provided through DT properties
so that proper regulator handle can be acquired.
Signed-off-by: Laxman Dewangan
---
drivers/regulator/userspace-consumer.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/regulator/userspace-consumer.c
b/drivers/regulator/userspace-consumer.c
index 765acc1..91d50a2 100644
--- a/drivers/regulator/userspace-consumer.c
+++ b/drivers/regulator/userspace-consumer.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
struct userspace_consumer_data {
const char *name;
@@ -105,6 +106,41 @@ static const struct attribute_group attr_group = {
.attrs = attributes,
};
+static struct regulator_userspace_consumer_data *get_pdata_from_dt_node(
+ struct platform_device *pdev)
+{
+ struct regulator_userspace_consumer_data *pdata;
+ struct device_node *np = pdev->dev.of_node;
+ struct property *prop;
+ const char *supply;
+ int num_supplies;
+ int count = 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return ERR_PTR(-ENOMEM);
+
+ pdata->name = of_get_property(np, "regulator-name", NULL);
+ pdata->init_on = of_property_read_bool(np, "regulator-boot-on");
+
+ num_supplies = of_property_count_strings(np, "regulator-supplies");
+ if (num_supplies < 0) {
+ dev_err(&pdev->dev,
+ "could not parse property regulator-supplies\n");
+ return ERR_PTR(-EINVAL);
+ }
+ pdata->num_supplies = num_supplies;
+ pdata->supplies = devm_kzalloc(&pdev->dev, num_supplies *
+ sizeof(*pdata->supplies), GFP_KERNEL);
+ if (!pdata->supplies)
+ return ERR_PTR(-ENOMEM);
+
+ of_property_for_each_string(np, "regulator-supplies", prop, supply)
+ pdata->supplies[count++].supply = supply;
+
+ return pdata;
+}
+
static int regulator_userspace_consumer_probe(struct platform_device *pdev)
{
struct regulator_userspace_consumer_data *pdata;
@@ -112,6 +148,11 @@ static int regulator_userspace_consumer_probe(struct
platform_device *pdev)
int ret;
pdata = dev_get_platdata(&pdev->dev);
+ if (!pdata && pdev->dev.of_node) {
+ pdata = get_pdata_from_dt_node(pdev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ }
if (!pdata)
return -EINVAL;
@@ -171,11 +212,18 @@ static int regulator_userspace_consumer_remove(struct
platform_device *pdev)
return 0;
}
+static const struct of_device_id regulator_userspace_consumer_of_match[] = {
+ { .compatible = "reg-userspace-consumer", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, regulator_userspace_consumer_of_match);
+
static struct platform_driver regulator_userspace_consumer_driver = {
.probe = regulator_userspace_consumer_probe,
.remove = regulator_userspace_consumer_remove,
.driver = {
.name = "reg-userspace-consumer",
+ .of_match_table = regulator_userspace_consumer_of_match,
},
};
--
1.8.1.5
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[PATCH-REPOST] regulator: gpio: fix default of regulator-type property
As per driver, the absense of "regulator-type" default to voltage type. Correct the document to say default is voltage instead of current. Signed-off-by: Laxman Dewangan --- Seems somehow this is missed for review, reposting it. Documentation/devicetree/bindings/regulator/gpio-regulator.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt index e5cac1e..dd1ed78 100644 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt @@ -13,7 +13,7 @@ Optional properties: - startup-delay-us : Startup time in microseconds. - enable-active-high : Polarity of GPIO is active high (default is low). - regulator-type : Specifies what is being regulated, must be either - "voltage" or "current", defaults to current. + "voltage" or "current", defaults to voltage. Any property defined as part of the core regulator binding defined in regulator.txt can also be used. -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] dt-binding: mfd: as3722: correct macro name
The macro name for enable3 pin is named as AS3722_EXT_CONTROL_PIN_ENABLE2 which is conflict with the enable2 pin. Correct this macro name to correctly reflect the enable pin i.e. AS3722_EXT_CONTROL_PIN_ENABLE3. Signed-off-by: Laxman Dewangan Reported-by: Dan Willemsen --- include/dt-bindings/mfd/as3722.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/mfd/as3722.h b/include/dt-bindings/mfd/as3722.h index 0e69256..e66c089 100644 --- a/include/dt-bindings/mfd/as3722.h +++ b/include/dt-bindings/mfd/as3722.h @@ -13,7 +13,7 @@ /* External control pins */ #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 -#define AS3722_EXT_CONTROL_PIN_ENABLE2 3 +#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 /* Interrupt numbers for AS3722 */ #define AS3722_IRQ_LID 0 -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V5 REPOST] mfd: add support for ams AS3722 PMIC
On Friday 06 June 2014 08:58 PM, Lee Jones wrote: Laxman, This patch has already been applied, but ... + as3722->en_intern_int_pullup = of_property_read_bool(np, + "ams,enable-internal-int-pullup"); + as3722->en_intern_i2c_pullup = of_property_read_bool(np, + "ams,enable-internal-i2c-pullup"); These are still not documented. Can you please do so? Sure, Thanks for pointing this out. I sent the patch. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Doc: mfd: as3722: Add details of optional missing property
Add details of following properties which are used on driver but not documented on DT binding document. - ams,enable-internal-int-pullup - ams,enable-internal-i2c-pullup Signed-off-by: Laxman Dewangan Reported-by: Lee Jones --- Documentation/devicetree/bindings/mfd/as3722.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt index 8edcb9b..4f64b2a 100644 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -13,6 +13,14 @@ Required properties: The second cell is the flags, encoded as the trigger masks from binding document interrupts.txt, using dt-bindings/irq. +Optional properties: + +- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on + interrupt pin. Missing this will disable internal pullup on INT pin. +- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on + i2c scl/sda pins. Missing this will disable internal pullup on i2c + scl/sda lines. + Optional submodule and their properties: === -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] regulator: gpio: fix default of regulator-type property
As per driver, the absense of "regulator-type" default to voltage type. Correct the document to say default is voltage instead of current. Signed-off-by: Laxman Dewangan --- Documentation/devicetree/bindings/regulator/gpio-regulator.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt index e5cac1e..dd1ed78 100644 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt @@ -13,7 +13,7 @@ Optional properties: - startup-delay-us : Startup time in microseconds. - enable-active-high : Polarity of GPIO is active high (default is low). - regulator-type : Specifies what is being regulated, must be either - "voltage" or "current", defaults to current. + "voltage" or "current", defaults to voltage. Any property defined as part of the core regulator binding defined in regulator.txt can also be used. -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: tegra: fix Dalmore PMIC IRQ polarity
On Saturday 15 February 2014 03:28 AM, Stephen Warren wrote: From: Stephen Warren The Tegra PMC's resume-from-sleep logic wants an active-low IRQ input from the PMIC. However, the PMIC IRQ is also routed to the GIC, which only supports active high IRQs (or rising edge). Hence, the signal must be inverted in the PMC before being routed to the GIC. This implies that the PMC DT property nvidia,invert-interrupt must be set, and it is. The PMIC's DT interrupts property must represent the IRQ level at the GIC, since that is the PMIC's parent IRQ controller. Fix the PMIC's interrupts property to correctly describe the GIC input polarity. However, the PMIC IRQ output's polarity is programmable in HW, and by default follows the parent IRQ controller's input polarity. We need to have an active-low output due to the inversion inside the Tegra PMC. Hence, add the ti,irq-externally-inverted property to the PMIC. Looks good to me. Acked-by: Laxman Dewangan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] mfd: palmas: support IRQ inversion at the board level
On Saturday 15 February 2014 03:28 AM, Stephen Warren wrote: From: Stephen Warren Some boards or SoCs have an inverter between the PMIC IRQ output pin and the IRQ controller input signal. The IRQ specifier in DT is meant to represent the IRQ flags at the input to the IRQ controller. Looks good to me. Acked-by: Laxman Dewangan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/2] mfd: AS3722: add dt node properties for system power controller
ams AS3722 device supports the power off by turning off its all rails.
Add dt node properties to enable this functionality on this device.
Signed-off-by: Laxman Dewangan
Tested-by: Stephen Warren
---
Changes form V1:
- Rephrase sentence and mention that propery is boolean type.
- Added Tested by.
Documentation/devicetree/bindings/mfd/as3722.txt | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt
b/Documentation/devicetree/bindings/mfd/as3722.txt
index fc2191e..8edcb9b 100644
--- a/Documentation/devicetree/bindings/mfd/as3722.txt
+++ b/Documentation/devicetree/bindings/mfd/as3722.txt
@@ -112,6 +112,15 @@ Following are properties of regulator subnode.
ams,enable-tracking: Enable tracking with SD1, only supported
by LDO3.
+Power-off:
+=
+AS3722 supports the system power off by turning off all its rail. This
+is provided through pm_power_off.
+The device node should have the following properties to enable this
+functionality
+ams,system-power-controller: Boolean, to enable the power off functionality
+through this device.
+
Example:
#include
@@ -120,6 +129,8 @@ ams3722 {
compatible = "ams,as3722";
reg = <0x48>;
+ ams,system-power-controller;
+
interrupt-parent = <&intc>;
interrupt-controller;
#interrupt-cells = <2>;
--
1.7.9.5
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[PATCH V2 2/2] power: reset: as3722: add power-off driver
ams AS3722 supports the power off functionality to turn off
system.
Add power off driver for ams AS3722.
Signed-off-by: Laxman Dewangan
Tested-by: Stephen Warren
---
Changes from V1:
- Just added tested by.
drivers/power/reset/Kconfig |6 +++
drivers/power/reset/Makefile |1 +
drivers/power/reset/as3722-poweroff.c | 96 +
3 files changed, 103 insertions(+)
create mode 100644 drivers/power/reset/as3722-poweroff.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 9b3ea53..6d452a7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -6,6 +6,12 @@ menuconfig POWER_RESET
Say Y here to enable board reset and power off
+config POWER_RESET_AS3722
+ bool "ams AS3722 power-off driver"
+ depends on MFD_AS3722 && POWER_RESET
+ help
+ This driver supports turning off board via a ams AS3722 power-off.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 3e6ed88..a5b4a77 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/as3722-poweroff.c
b/drivers/power/reset/as3722-poweroff.c
new file mode 100644
index 000..6849711
--- /dev/null
+++ b/drivers/power/reset/as3722-poweroff.c
@@ -0,0 +1,96 @@
+/*
+ * Power off driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_poweroff {
+ struct device *dev;
+ struct as3722 *as3722;
+};
+
+static struct as3722_poweroff *as3722_pm_poweroff;
+
+static void as3722_pm_power_off(void)
+{
+ int ret;
+
+ if (!as3722_pm_poweroff) {
+ pr_err("AS3722 poweroff is not initialised\n");
+ return;
+ }
+
+ ret = as3722_update_bits(as3722_pm_poweroff->as3722,
+ AS3722_RESET_CONTROL_REG, AS3722_POWER_OFF, AS3722_POWER_OFF);
+ if (ret < 0)
+ dev_err(as3722_pm_poweroff->dev,
+ "RESET_CONTROL_REG update failed, %d\n", ret);
+}
+
+static int as3722_poweroff_probe(struct platform_device *pdev)
+{
+ struct as3722_poweroff *as3722_poweroff;
+ struct device_node *np = pdev->dev.parent->of_node;
+
+ if (!np)
+ return -EINVAL;
+
+ if (!of_property_read_bool(np, "ams,system-power-controller"))
+ return 0;
+
+ as3722_poweroff = devm_kzalloc(&pdev->dev, sizeof(*as3722_poweroff),
+ GFP_KERNEL);
+ if (!as3722_poweroff)
+ return -ENOMEM;
+
+ as3722_poweroff->as3722 = dev_get_drvdata(pdev->dev.parent);
+ as3722_poweroff->dev = &pdev->dev;
+ as3722_pm_poweroff = as3722_poweroff;
+ if (!pm_power_off)
+ pm_power_off = as3722_pm_power_off;
+
+ return 0;
+}
+
+static int as3722_poweroff_remove(struct platform_device *pdev)
+{
+ if (pm_power_off == as3722_pm_power_off)
+ pm_power_off = NULL;
+ as3722_pm_poweroff = NULL;
+
+ return 0;
+}
+
+static struct platform_driver as3722_poweroff_driver = {
+ .driver = {
+ .name = "as3722-power-off",
+ .owner = THIS_MODULE,
+ },
+ .probe = as3722_poweroff_probe,
+ .remove = as3722_poweroff_remove,
+};
+
+module_platform_driver(as3722_poweroff_driver);
+
+MODULE_DESCRIPTION("Power off driver for ams AS3722 PMIC Device");
+MODULE_ALIAS("platform:as3722-power-off");
+MODULE_AUTHOR("Laxman Dewangan ");
+MODULE_LICENSE("GPL v2");
--
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[PATCH 2/2] power: reset: as3722: add power-off driver
ams AS3722 supports the power off functionality to turn off
system.
Add power off driver for ams AS3722.
Signed-off-by: Laxman Dewangan
---
drivers/power/reset/Kconfig |6 +++
drivers/power/reset/Makefile |1 +
drivers/power/reset/as3722-poweroff.c | 96 +
3 files changed, 103 insertions(+)
create mode 100644 drivers/power/reset/as3722-poweroff.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 9b3ea53..6d452a7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -6,6 +6,12 @@ menuconfig POWER_RESET
Say Y here to enable board reset and power off
+config POWER_RESET_AS3722
+ bool "ams AS3722 power-off driver"
+ depends on MFD_AS3722 && POWER_RESET
+ help
+ This driver supports turning off board via a ams AS3722 power-off.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 3e6ed88..a5b4a77 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/as3722-poweroff.c
b/drivers/power/reset/as3722-poweroff.c
new file mode 100644
index 000..6849711
--- /dev/null
+++ b/drivers/power/reset/as3722-poweroff.c
@@ -0,0 +1,96 @@
+/*
+ * Power off driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_poweroff {
+ struct device *dev;
+ struct as3722 *as3722;
+};
+
+static struct as3722_poweroff *as3722_pm_poweroff;
+
+static void as3722_pm_power_off(void)
+{
+ int ret;
+
+ if (!as3722_pm_poweroff) {
+ pr_err("AS3722 poweroff is not initialised\n");
+ return;
+ }
+
+ ret = as3722_update_bits(as3722_pm_poweroff->as3722,
+ AS3722_RESET_CONTROL_REG, AS3722_POWER_OFF, AS3722_POWER_OFF);
+ if (ret < 0)
+ dev_err(as3722_pm_poweroff->dev,
+ "RESET_CONTROL_REG update failed, %d\n", ret);
+}
+
+static int as3722_poweroff_probe(struct platform_device *pdev)
+{
+ struct as3722_poweroff *as3722_poweroff;
+ struct device_node *np = pdev->dev.parent->of_node;
+
+ if (!np)
+ return -EINVAL;
+
+ if (!of_property_read_bool(np, "ams,system-power-controller"))
+ return 0;
+
+ as3722_poweroff = devm_kzalloc(&pdev->dev, sizeof(*as3722_poweroff),
+ GFP_KERNEL);
+ if (!as3722_poweroff)
+ return -ENOMEM;
+
+ as3722_poweroff->as3722 = dev_get_drvdata(pdev->dev.parent);
+ as3722_poweroff->dev = &pdev->dev;
+ as3722_pm_poweroff = as3722_poweroff;
+ if (!pm_power_off)
+ pm_power_off = as3722_pm_power_off;
+
+ return 0;
+}
+
+static int as3722_poweroff_remove(struct platform_device *pdev)
+{
+ if (pm_power_off == as3722_pm_power_off)
+ pm_power_off = NULL;
+ as3722_pm_poweroff = NULL;
+
+ return 0;
+}
+
+static struct platform_driver as3722_poweroff_driver = {
+ .driver = {
+ .name = "as3722-power-off",
+ .owner = THIS_MODULE,
+ },
+ .probe = as3722_poweroff_probe,
+ .remove = as3722_poweroff_remove,
+};
+
+module_platform_driver(as3722_poweroff_driver);
+
+MODULE_DESCRIPTION("Power off driver for ams AS3722 PMIC Device");
+MODULE_ALIAS("platform:as3722-power-off");
+MODULE_AUTHOR("Laxman Dewangan ");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
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[PATCH 1/2] mfd: AS3722: add dt node properties for system power controller
ams AS3722 device supports the power off by turning off its all rails. Add dt node properties to enable this functionality on this device. Signed-off-by: Laxman Dewangan --- Documentation/devicetree/bindings/mfd/as3722.txt |9 + 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt index fc2191e..1e54937 100644 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -112,6 +112,15 @@ Following are properties of regulator subnode. ams,enable-tracking: Enable tracking with SD1, only supported by LDO3. +Power-off: += +AS3722 supports the system power off by turning off all its rail. The power off +is provided through pm power off. +The device node should have the following properties to enable power-off +functionality from ams AS3722: +ams,system-power-controller: To enable the power off functionality through + device. + Example: #include -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] of: add support for reading s32 property value
On Thursday 12 December 2013 11:31 PM, Stephen Warren wrote:
On 12/12/2013 06:24 AM, Laxman Dewangan wrote:
Add of_property_read_s32() to read the signed 32bit number
from dt property value. This supports to pass the -ve numbers
from dt. Use 2's complement method for represnting negative number
and passed as u32 from dts. When reading back the value, again
converted to 2's complement if msb shows as 1.
diff --git a/include/linux/of.h b/include/linux/of.h
+static inline int of_property_read_s32(const struct device_node *np,
+ const char *propname,
+ s32 *out_value)
+{
+ u32 val;
+ int ret;
+
+ ret = of_property_read_u32(np, propname, &val);
+ if (ret < 0)
+ return ret;
+
+ /* 2's complement if MSB is 1 */
+ *out_value = (val & 0x8000U) ? -((val ^ 0xU) + 1) : val;
I may not be thinking straight today since I have a cold, but doesn't
patch 2/2 encode negative values as 2's complement, and an s32 variable
in the kernel is also encoded as 2's complement, so all you need here is
a cast:
*out_value = (s32)val;
... since the cast doesn't change the binary representation?
This is correct if all architecture follows the 2's complement for -Ve
number representation.
If this is true then the patch will become more easy.
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Re: [PATCH 1/2] ARM: tegra: enable ams AS3722 drivers
On Friday 13 December 2013 03:21 AM, Stephen Warren wrote: On 12/12/2013 02:20 PM, Stephen Warren wrote: On 12/12/2013 06:31 AM, Laxman Dewangan wrote: ams AS3722 is the system power manager module IC for the Tegra124 based Venice2 platform. Enable configs for gpio, pincontrol, rtc, regulator support from this device. I've squashed patch 1/2 into Tegra's for-3.14/defconfig branch. I've applied patch 2/2 to Tegra's for-3.14/dt branch. Actually, I'm dropping patch 2/2 since it causes a whole bunch of error spew during boot: [0.628315] tegra124-pinctrl 7868.pinmux: invalid group "dap2_dout_pp2" for function "rsvd4" [0.635309] tegra124-pinctrl 7868.pinmux: does not have pin group dap2_dout_pp2 [0.642999] tegra124-pinctrl 7868.pinmux: could not map group config for "dap2_dout_pp2" [0.731176] as3722-pinctrl as3722-pinctrl: pin gpio0 already requested by as3722-pinctrl; cannot claim for as3722-regulator [0.742312] as3722-pinctrl as3722-pinctrl: pin-0 (as3722-regulator) status -22 [0.749526] as3722-pinctrl as3722-pinctrl: could not request pin 0 (gpio0) from group gpio0 on device as3722-pinctrl [0.760133] as3722-regulator as3722-regulator: Error applying setting, reverse things back [0.835838] as3722-regulator as3722-regulator: Failed to find supply vin-ldo1-6 [0.843312] as3722-regulator as3722-regulator: regulator 8 register failed -517 [0.852263] platform as3722-regulator: Driver as3722-regulator requests probe deferral [0.984920] as3722-pinctrl as3722-pinctrl: pin gpio0 already requested by as3722-pinctrl; cannot claim for as3722-rtc [0.995537] as3722-pinctrl as3722-pinctrl: pin-0 (as3722-rtc) status -22 [1.002244] as3722-pinctrl as3722-pinctrl: could not request pin 0 (gpio0) from group gpio0 on device as3722-pinctrl [1.012848] as3722-rtc as3722-rtc: Error applying setting, reverse things back I did not observe this issue in my log, probably overlooked. I will repro this and fix/update the issue/patch. Thanks, laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: tegra: add ams AS3722 device to Venice2 DT
Add ams AS3722 entry for gpio/pincontrol and regulators
to venice2 DT.
Signed-off-by: Laxman Dewangan
---
This patch is on top of the patch for pincontrol for venice2.
Tested with all regulator and sub driver registartion on Venice2.
arch/arm/boot/dts/tegra124-venice2.dts | 285 +++-
1 files changed, 284 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
index 7a01171..423371f 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -350,6 +350,28 @@
nvidia,open-drain = ;
};
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "rsvd3";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ dap3_dout_pp2 {
+ nvidia,pins = "dap2_dout_pp2";
+ nvidia,function = "rsvd4";
+ nvidia,enable-input = ;
+ nvidia,tristate = ;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,enable-input = ;
+ nvidia,tristate = ;
+ };
+
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = ;
@@ -419,7 +441,190 @@
i2c@7000d000 {
status = "okay";
- clock-frequency = <10>;
+ clock-frequency = <40>;
+
+ as3722: as3722@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ gpio1_2_4_7 {
+ pins = "gpio1", "gpio2", "gpio4",
"gpio7";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio3_6 {
+ pins = "gpio3", "gpio6";
+ bias-high-impedance;
+ };
+
+ gpio5 {
+ pins = "gpio5";
+ function = "clk32k-out";
+ };
+ };
+
+ regulators {
+ vsup-sd2-supply = <&vdd_ac_bat_reg>;
+ vsup-sd3-supply = <&vdd_ac_bat_reg>;
+ vsup-sd4-supply = <&vdd_ac_bat_reg>;
+ vsup-sd5-supply = <&vdd_ac_bat_reg>;
+ vin-ldo0-supply = <&as3722_sd2>;
+ vin-ldo1-6-supply = <&vdd_3v3_reg>;
+ vin-ldo2-5-7-supply = <&as3722_sd5>;
+ vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
+ vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
+ vin-ldo11-supply = <&vdd_3v3_reg>;
+
+ sd0 {
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <140>;
+ regulator-min-microamp = <350>;
+ regulator-max-microamp = <350>;
+
[PATCH 1/2] ARM: tegra: enable ams AS3722 drivers
ams AS3722 is the system power manager module IC for the Tegra124 based Venice2 platform. Enable configs for gpio, pincontrol, rtc, regulator support from this device. Signed-off-by: Laxman Dewangan --- arch/arm/configs/tegra_defconfig |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 4461185..5cf4a48 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -137,6 +137,7 @@ CONFIG_SPI=y CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y +CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_PALMAS=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X_IRQ=y @@ -149,6 +150,7 @@ CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_SENSORS_LM90=y +CONFIG_MFD_AS3722=y CONFIG_MFD_MAX8907=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y @@ -157,6 +159,7 @@ CONFIG_MFD_TPS65910=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_PALMAS=y @@ -218,6 +221,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] of: add support for reading s32 property value
Add of_property_read_s32() to read the signed 32bit number
from dt property value. This supports to pass the -ve numbers
from dt. Use 2's complement method for represnting negative number
and passed as u32 from dts. When reading back the value, again
converted to 2's complement if msb shows as 1.
Signed-off-by: Laxman Dewangan
CC: da...@gibson.dropbear.id.au
CC: swar...@nvidia.com
---
We required to pass the -ve value from DT and after looking the discussion
http://www.mail-archive.com/linux-arm-msm@vger.kernel.org/msg05108.html
I created this patch.
I CCed to David and Stephen on this.
include/linux/of.h | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..17c0327 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -601,6 +601,22 @@ static inline int of_property_read_u32(const struct
device_node *np,
return of_property_read_u32_array(np, propname, out_value, 1);
}
+static inline int of_property_read_s32(const struct device_node *np,
+ const char *propname,
+ s32 *out_value)
+{
+ u32 val;
+ int ret;
+
+ ret = of_property_read_u32(np, propname, &val);
+ if (ret < 0)
+ return ret;
+
+ /* 2's complement if MSB is 1 */
+ *out_value = (val & 0x8000U) ? -((val ^ 0xU) + 1) : val;
+ return ret;
+}
+
#define of_property_for_each_u32(np, propname, prop, p, u) \
for (prop = of_find_property(np, propname, NULL), \
p = of_prop_next_u32(prop, NULL, &u); \
--
1.7.0.4
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[PATCH 2/2] dt-binding: add header to define types and conversion
Add a header file to define the macros for type conversion to be used by DTS file. Add macro for the S32 to U32 conversion by using 2's complement. Signed-off-by: Laxman Dewangan --- include/dt-bindings/types.h | 18 ++ 1 files changed, 18 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/types.h diff --git a/include/dt-bindings/types.h b/include/dt-bindings/types.h new file mode 100644 index 000..2b7ea75 --- /dev/null +++ b/include/dt-bindings/types.h @@ -0,0 +1,18 @@ +/* + * This header provides macros for different types and conversions + */ + +#ifndef _DT_BINDINGS_TYPES_H_ +#define _DT_BINDINGS_TYPES_H_ + +/* + * S32_TO_U32: This macro converts the signed number to 2's complement + * unisgned number. E.g. S32_TO_U32(-3) will be 0xfffd and + * S32_TO_U32(3) will be 0x3; + * Use of_property_read_s32() for getting back the correct signed value + * in driver. + */ +#define S32_TO_U32(x) (((x) < 0) ? (((-(x)) ^ 0xU) + 1) : (x)) + +#endif + -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/2] pinctrl: tegra: Add devicetree binding document for Tegra124
This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Signed-off-by: Laxman Dewangan Acked-by: Stephen Warren --- Changes from V1: - Referred the dt-binding header file on describing the nodes. Changes from V2: - Rewording reg properties. - drop drv_type as it is not applicable. .../bindings/pinctrl/nvidia,tegra124-pinmux.txt| 144 1 files changed, 144 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt new file mode 100644 index 000..6464bf7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt @@ -0,0 +1,144 @@ +NVIDIA Tegra124 pinmux controller + +The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30 +pinctrl binding, as described in nvidia,tegra20-pinmux.txt and +nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as +a baseline, and only documents the differences between the two bindings. + +Required properties: +- compatible: "nvidia,tegra124-pinmux" +- reg: Should contain a list of base address and size pairs for: +-- first entry - the drive strength and pad control registers. +-- second entry - the pinmux registers + +Tegra124 adds the following optional properties for pin configuration subnodes. +The macros for options are defined in the + include/dt-binding/pinctrl/pinctrl-tegra.h. +- nvidia,enable-input: Integer. Enable the pin's input path. + enable :TEGRA_PIN_ENABLE0 and + disable or output only: TEGRA_PIN_DISABLE. +- nvidia,open-drain: Integer. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,lock: Integer. Lock the pin configuration against further changes +until reset. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,io-reset: Integer. Reset the IO path. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE + +Please refer the Tegra TRM for complete details regarding which groups +support which functionality. + +Valid values for pin and group names are: + + per-pin mux groups: + +These all support nvidia,function, nvidia,tristate, nvidia,pull, +nvidia,enable-input. Some support nvidia,lock nvidia,open-drain, +nvidia,io-reset and nvidia,rcv-sel. + + ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4, + ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0, + ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, + dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, + sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, + ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1, + uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4, + gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, + dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, + pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, + pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, + pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, + sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, + sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1, + cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck, + pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, + kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, + kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, + kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1, + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, + kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, + clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, + dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6, + spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, + dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, + sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
[PATCH] ARM: tegra: add default pinctrl nodes for Venice2
Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: Laxman Dewangan
---
This change depends on the series of
- adding dt-binding header file for pincontrol.
The pinmux configuration is based on
http://p4viewer/get///syseng/WMP/Projects/T124/ChromeBook/PM371/Venice2_T124_customer_pinmux_based_on_P4_rev47_2013-07-12.xlsm
and downstream conifguration of pins for given SFIO.
This is based o
arch/arm/boot/dts/tegra124-venice2.dts | 376
arch/arm/boot/dts/tegra124.dtsi|1 +
2 files changed, 377 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
index 431d67a..3a93a02 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -10,6 +10,382 @@
reg = <0x8000 0x8000>;
};
+ pinmux: pinmux@7868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_default>;
+
+ pinmux_default: common {
+ dap_mclk1_pw4 {
+ nvidia,pins = "dap_mclk1_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_fs_pn0",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4",
+ "dap2_dout_pa5",
+ "dap2_fs_pa2",
+ "dap2_sclk_pa3";
+ nvidia,function = "i2s1";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ dvfs_pwm_px0 {
+ nvidia,pins = "dvfs_pwm_px0";
+ nvidia,function = "cldvfs";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ dvfs_clk_px2 {
+ nvidia,pins = "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ };
+
+
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,lock = ;
+ nvidia,open-drain = ;
+ };
+
+
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,enable-input = ;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+
[PATCH V2 1/2] pinctrl: tegra: Add devicetree binding document for Tegra124
This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Signed-off-by: Laxman Dewangan --- Changes from V1: - Referred the dt-binding header file on describing the nodes. .../bindings/pinctrl/nvidia,tegra124-pinmux.txt| 147 1 files changed, 147 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt new file mode 100644 index 000..12ef772 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt @@ -0,0 +1,147 @@ +NVIDIA Tegra124 pinmux controller + +The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30 +pinctrl binding, as described in nvidia,tegra20-pinmux.txt and +nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as +a baseline, and only documents the differences between the two bindings. + +Required properties: +- compatible: "nvidia,tegra124-pinmux" +- reg: Should contain the register physical address and length for each of + the pad control and mux registers. The first bank of address must be the + driver strength pad control register address and second bank address must + be pinmux register address. + +Tegra124 adds the following optional properties for pin configuration subnodes. +The macros for options are defined in the + include/dt-binding/pinctrl/pinctrl-tegra.h. +- nvidia,enable-input: Integer. Enable the pin's input path. + enable :TEGRA_PIN_ENABLE0 and + disable or output only: TEGRA_PIN_DISABLE. +- nvidia,open-drain: Integer. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,lock: Integer. Lock the pin configuration against further changes +until reset. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,io-reset: Integer. Reset the IO path. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,drive-type: Integer. Valid range 0...3. + + +Please refer the Tegra TRM for complete details regarding which groups +support which functionality. + +Valid values for pin and group names are: + + per-pin mux groups: + +These all support nvidia,function, nvidia,tristate, nvidia,pull, +nvidia,enable-input. Some support nvidia,lock nvidia,open-drain, +nvidia,io-reset and nvidia,rcv-sel. + + ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4, + ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0, + ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, + dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, + sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, + ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1, + uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4, + gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, + dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, + pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, + pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, + pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, + sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, + sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1, + cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck, + pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, + kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, + kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, + kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1, + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, + kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, + clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, + dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6, + spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, + dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, + sdmmc3_clk_pa6,
Re: [PATCH V3 0/4] ARM: tegra: convert dts files of all Tegra platforms to use pinctrl defines
On Friday 06 December 2013 05:03 AM, Stephen Warren wrote: On 12/05/2013 03:44 AM, Laxman Dewangan wrote: This patch series convert dts files of all Tegra's platforms to use the pinctron dt-binding macro for better readability. I think this series looks fine now; I'll apply soon pending what happens with the DMA/reset/ binding rework. There are quite a few typos/spelling/capitalization mistakes in the commit descriptions, but I'll fix them up when applying. Thanks for review. I like to also update the dt binding document to use thes macro. Will post the chnage for doc update also. And I want to refer this for t124 dt binding doc of pinctrl also. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/4] pinctrl: tegra: add pinmux controller driver for Tegra124
On Friday 06 December 2013 05:00 AM, Stephen Warren wrote:
On 12/05/2013 03:57 AM, Laxman Dewangan wrote:
From: Ashwini Ghuge
This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.
The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.
This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".
Originally written by Ashwini Gguhe.
ldewangan:
- cleanup the patches,
- Fix address issue.
IIRC, Thierry mentioned he had some fixes in his local branch for this
driver. Thierry, can you please confirm/deny this?
I made the following comment on the version Ashwini posted, which hasn't
been addressed yet:
A day or two ago during upstream review:
Yes, we have some missing entry and I responded into other mail thread.
I will post the diff here to complete.
+static const struct tegra_function tegra124_functions[] = {
...
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2cpwr),
Is that complete? Tegra124 apparently has 6 I2C controllers. Are the
pins for the new sixth controller (0x7000d100) not affected by the pinmux?
That said, if we find things are missing, I suppose we can add them
later without breaking existing ABI. Breakage would only happen if we
had to change/remove something.
During downstream review quite a while ago I also said:
I2C6 pinmux is not in this controller, it is dpaux controller and we
have not supported this. This require little bit different handling. I
have already downstream bug for support this. Will add you in loop so
that single fix can work for mainline and downstream.
Other than I2C6, some other mux are missing.
+static const struct pinctrl_pin_desc tegra124_pins[] = {
There are two spaces before "tegra124_pins[]".
+static const char * const gmi_groups[] = {
+ "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6",
+ "uart3_txd_pw6",
+ "uart3_rxd_pw7",
+ "uart3_cts_n_pa1",
+ "uart3_rts_n_pc0",
+
+ "pu0",
It'd be best not to have blank lines in the middle of arrays. The same comment
exists elsewhere in the
file, so make sure you search the whole file.
Nits:
- There are some cases of multiple blank lines back-to-back.
- There's a blank line at the end of the file.
Aside from those minor issues, patches 1/4 and 4/4,
Acked-by: Stephen Warren
(BTW, those 2 patches would go through the pinctrl tree, and patches 2/4
and 3/4 would go through the Tegra tree. You generally shouldn't posted
patches that will be applied to different trees in the same series,
since there aren't dependencies).
Fine.
Should I sent the diff or full change? I think full change as this need
to go on pincontrol subsystem, not in Tegra.
Thanks,
Laxman
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Re: [PATCH 1/4] pinctrl: tegra: Add devicetree binding document for Tegra124
On Friday 06 December 2013 04:47 AM, Stephen Warren wrote: On 12/05/2013 03:57 AM, Laxman Dewangan wrote: This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Is this a repost of what Ashwini sent a few weeks back, or V2? If V2, it'd be useful to know what changed... I am not aware that Ashwini already sent back. I did not get chance to talk to her on this. I was thinking that it is still in internal review. Anyhow, I compare the downstream to your linux-next-common and found some diff. Something fixed in your tree which need downstream and something fixed in downstream which need to upstream. :) One diff is Mux enums are: TEGRA_MUX_SATA, TEGRA_MUX_CCLA, TEGRA_MUX_PE0, TEGRA_MUX_PE, TEGRA_MUX_PE1, TEGRA_MUX_DP, TEGRA_MUX_RTCK, TEGRA_MUX_SYS, TEGRA_MUX_CLK, TEGRA_MUX_TMDS, }; Functions definitions are: FUNCTION(sata), FUNCTION(ccla), FUNCTION(rtck), FUNCTION(pe0), FUNCTION(pe), FUNCTION(pe1), FUNCTION(dp), I think I will post the patch to fix this issue. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] ARM: tegra: add pinmux controller to tegra124.dtsi
On Friday 06 December 2013 04:49 AM, Stephen Warren wrote: On 12/05/2013 04:16 PM, Stephen Warren wrote: On 12/05/2013 03:57 AM, Laxman Dewangan wrote: The tegra124 pinmux controller is identical to tegra114 with removing some of existing pins from T114 and adding new pins. I already sent this patch. Oh, I do notice one difference between the two patches: Mine: + reg = <0x7868 0x148>, /* Pad control registers */ + <0x70003000 0x40c>; /* Mux registers */ Yours: + reg = <0x7868 0x164 /* Pad control registers */ + 0x70003000 0x434>;/* PinMux registers */ Are the increase register lengths in your patch correct? If so, I guess I'll drop my patch and replace it with yours if you fix up the unit address. Yes, the last entry of the bank 0 and 1 are: DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), and PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, DP, 0x3430, N, N, N), -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] ARM: tegra: add pinmux controller to tegra124.dtsi
The tegra124 pinmux controller is identical to tegra114 with
removing some of existing pins from T114 and adding new pins.
Signed-off-by: Laxman Dewangan
---
arch/arm/boot/dts/tegra124.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b741300..39bfcce 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -47,6 +47,12 @@
interrupt-controller;
};
+ pinmux: pinmux {
+ compatible = "nvidia,tegra124-pinmux";
+ reg = <0x7868 0x164 /* Pad control registers */
+ 0x70003000 0x434>; /* PinMux registers */
+ };
+
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
--
1.7.1.1
--
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[PATCH 1/4] pinctrl: tegra: Add devicetree binding document for Tegra124
This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Signed-off-by: Laxman Dewangan --- .../bindings/pinctrl/nvidia,tegra124-pinmux.txt| 137 1 files changed, 137 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt new file mode 100644 index 000..016dad6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt @@ -0,0 +1,137 @@ +NVIDIA Tegra124 pinmux controller + +The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30 +pinctrl binding, as described in nvidia,tegra20-pinmux.txt and +nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as +a baseline, and only documents the differences between the two bindings. + +Required properties: +- compatible: "nvidia,tegra124-pinmux" +- reg: Should contain the register physical address and length for each of + the pad control and mux registers. The first bank of address must be the + driver strength pad control register address and second bank address must + be pinmux register address. + +Tegra124 adds the following optional properties for pin configuration subnodes: +- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. +- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. +- nvidia,lock: Integer. Lock the pin configuration against further changes +until reset. 0: no, 1: yes. +- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. +- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high. +- nvidia,drive-type: Integer. Valid range 0...3. + +The macros for options are defined in the +include/dt-binding/pinctrl/pinctrl-tegra.h. + +Please refer the Tegra TRM for complete details regarding which groups +support which functionality. + +Valid values for pin and group names are: + + per-pin mux groups: + +These all support nvidia,function, nvidia,tristate, nvidia,pull, +nvidia,enable-input. Some support nvidia,lock nvidia,open-drain, +nvidia,io-reset and nvidia,rcv-sel. + + ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4, + ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0, + ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, + dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, + sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, + ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1, + uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4, + gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, + dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, + pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, + pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, + pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, + sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, + sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1, + cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck, + pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, + kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, + kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, + kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1, + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, + kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, + clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, + dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6, + spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, + dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, + sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, + sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, + pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5, + pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3, + sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, + usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5, + gmi_clk_lb, reset_out_n, kb_row16_pt
[PATCH 3/4] ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
The pincontrol driver for Tegra124 is build through config PINCTRL_TEGRA124. Select this config option whenever Tegra124 SoC is enabled. Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f..807e7bc 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -63,6 +63,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA124 help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/4] pinctrl: tegra: Add pincontrol driver for Tegra124 SoC
Add pincontrol driver for NVIDIA's Tegra124 SoCs. This series add pincontrol driver which contains the pinmux tables for tegra124, pincontrol dt binding doc, dtsi file change for adding pinmux node, selecting pincontrol config for Tegra124. Ashwini Ghuge (1): pinctrl: tegra: add pinmux controller driver for Tegra124 Laxman Dewangan (3): pinctrl: tegra: Add devicetree binding document for Tegra124 ARM: tegra: add pinmux controller to tegra124.dtsi ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC .../bindings/pinctrl/nvidia,tegra124-pinmux.txt| 137 + arch/arm/boot/dts/tegra124.dtsi|6 + arch/arm/mach-tegra/Kconfig|1 + drivers/pinctrl/Kconfig|4 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-tegra124.c | 3147 6 files changed, 3296 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt create mode 100644 drivers/pinctrl/pinctrl-tegra124.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 2/4] ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Changes based on new macro name.
Changes from V2:
- Add description in commit message.
arch/arm/boot/dts/tegra114-dalmore.dts | 548
arch/arm/boot/dts/tegra114.dtsi|1 +
2 files changed, 275 insertions(+), 274 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23..1fe2656 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -19,41 +19,41 @@
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
@@ -61,17 +61,17 @@
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,e
[PATCH V3 0/4] ARM: tegra: convert dts files of all Tegra platforms to use pinctrl defines
This patch series convert dts files of all Tegra's platforms to use the pinctron dt-binding macro for better readability. Changes from V1: - Get rid of lots of macro and converge it to TEGRA_PIN_ENABLE/DISABLE. - Change macro name for PULL UP/DOWN/NONE. Changes from V2: - Add more comment on defines. - Add two more patches for having simialr change for Tegra20 and Tegra30 platforms. Laxman Dewangan (4): ARM: tegra: Add header file for pinctrl constants ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines arch/arm/boot/dts/tegra114-dalmore.dts | 548 +- arch/arm/boot/dts/tegra114.dtsi |1 + arch/arm/boot/dts/tegra20-colibri-512.dtsi | 104 +++--- arch/arm/boot/dts/tegra20-harmony.dts | 30 +- arch/arm/boot/dts/tegra20-iris-512.dts | 10 +- arch/arm/boot/dts/tegra20-paz00.dts | 30 +- arch/arm/boot/dts/tegra20-seaboard.dts | 44 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 30 +- arch/arm/boot/dts/tegra20-trimslice.dts | 34 +- arch/arm/boot/dts/tegra20-ventana.dts | 44 +- arch/arm/boot/dts/tegra20-whistler.dts | 40 +- arch/arm/boot/dts/tegra20.dtsi |1 + arch/arm/boot/dts/tegra30-beaver.dts| 34 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 +- arch/arm/boot/dts/tegra30.dtsi |1 + include/dt-bindings/pinctrl/pinctrl-tegra.h | 45 +++ 16 files changed, 542 insertions(+), 494 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 4/4] ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan
---
- New patch on this series.
arch/arm/boot/dts/tegra30-beaver.dts | 34 ++--
arch/arm/boot/dts/tegra30-cardhu.dtsi | 40
arch/arm/boot/dts/tegra30.dtsi|1 +
3 files changed, 38 insertions(+), 37 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts
b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad69..48b89a4 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -52,8 +52,8 @@
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
@@ -62,14 +62,14 @@
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
@@ -78,15 +78,15 @@
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4";
nvidia,function = "sdmmc3";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
@@ -98,8 +98,8 @@
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
dap2_fs_pa2 {
nvidia,pins = "dap2_fs_pa2",
@@ -107,18 +107,18 @@
"dap2_din_pa4",
"dap2_dout_pa5";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
pex_l1_prsnt_n_pdd4 {
nvidia,pins = "pex_l1_prsnt_n_pdd4",
"pex_l1_clkreq_n_pdd6";
- nvidia,pull = <2>;
+ nvidia,pull = ;
};
sdio3 {
nvidia,pins = "drive_sdio3";
- nvidia,high-speed-mode = <0>;
- nvidia,
[PATCH V3 3/4] ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan
---
- New patch on this series.
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 104 ++--
arch/arm/boot/dts/tegra20-harmony.dts | 30
arch/arm/boot/dts/tegra20-iris-512.dts | 10 ++--
arch/arm/boot/dts/tegra20-paz00.dts| 30
arch/arm/boot/dts/tegra20-seaboard.dts | 44 ++--
arch/arm/boot/dts/tegra20-tamonten.dtsi| 30
arch/arm/boot/dts/tegra20-trimslice.dts| 34 +-
arch/arm/boot/dts/tegra20-ventana.dts | 44 ++--
arch/arm/boot/dts/tegra20-whistler.dts | 40 +-
arch/arm/boot/dts/tegra20.dtsi |1 +
10 files changed, 184 insertions(+), 183 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index d5c9bca..6ae66ad 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -27,20 +27,20 @@
audio_refclk {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
crt {
nvidia,pins = "crtp";
nvidia,function = "crt";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
displaya {
nvidia,pins = "ld0", "ld1", "ld2", "ld3",
@@ -50,151 +50,151 @@
"lhs", "lpw0", "lpw2", "lsc0",
"lsc1", "lsck", "lsda", "lspi", "lvs";
nvidia,function = "displaya";
- nvidia,tristate = <1>;
+ nvidia,tristate = ;
};
gpio_dte {
nvidia,pins = "dte";
nvidia,function = "rsvd1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
gpio_gmi {
nvidia,pins = "ata", "atc", "atd", "ate",
"dap1", "dap2", "dap4", "gpu", "irrx",
"irtx", "spia", "spib", "spic";
nvidia,function = "gmi";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
gpio_pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
gpio_uac {
nvidia,pins = "uac";
nvidia,function = "rsvd2";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
};
hdint {
nvidia,pins = &
[PATCH V3 1/4] ARM: tegra: Add header file for pinctrl constants
This new header file defines pincontrol constants for Tegra to use from Tegra's DTS file for pincontrol properties option. Signed-off-by: Laxman Dewangan Reviewed-by: Thierry Reding --- Changes from V1: - Get rid of lots of macro and converge it to TEGRA_PIN_ENABLE/DISABLE. - Change macro name for PULL UP/DOWN/NONE. Changes from V2: - Convert TEGRA -> Tegra. - Add comment on ENABLE/DSIABLE and remove from pulls. include/dt-bindings/pinctrl/pinctrl-tegra.h | 45 +++ 1 files changed, 45 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 000..ebafa49 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,45 @@ +/* + * This header provides constants for Tegra pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* + * Enable/disable for diffeent dt properties. This is applicable for + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. + */ +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +#define TEGRA_PIN_PULL_NONE0 +#define TEGRA_PIN_PULL_DOWN1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode driver */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +/* Rising/Falling slew rate */ +#define TEGRA_PIN_SLEW_RATE_FASTEST0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST3 + +#endif -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
On Wednesday 04 December 2013 01:39 AM, Stephen Warren wrote: On 12/02/2013 06:55 AM, Laxman Dewangan wrote: Signed-off-by: Laxman Dewangan Patch description? BTW, did you compile all the Tegra DT files before and after this change, and make sure that there's zero difference between them (i.e. they're identical byte-for-byte when compiled)? I don't feel like manually double-checking this entire patch... I just made changes for the Dalmore only. Not touched Tegra30 and Tegra20_ platform dts. For Dalmore, I compare the binary before and after this change as well dts generated back from dtb using dtc. It is same. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
On Wednesday 04 December 2013 01:38 AM, Stephen Warren wrote: On 12/02/2013 11:04 PM, Laxman Dewangan wrote: On Monday 02 December 2013 07:55 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote: + +/* Schmitt enable/disable */ +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE0 +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE1 These are all boolean, so I wonder if perhaps we should be simply defining a single pair and reuse that in different contexts: #define TEGRA_PIN_DISABLE0 #define TEGRA_PIN_ENABLE1 The property names should provide enough context for them to be used unambiguously. I can make generic ENABLE/DISABLE macro as you suggested but datasheet says as 0=NORMAL, 1 = TRISTATE. and that's why I kept name very near to the datasheet. That documentation is relative to a specific field, whereas the namespace for #defines is global. Hence, we may have to name #defines using stricter rules than the TRM's field values, in order to make them unambiguous. I send the V2 patches on which I have taken care of this. Request you to please review. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: tegra: convert device tree files to use key defines
On Wednesday 04 December 2013 01:34 AM, Stephen Warren wrote: On 12/02/2013 06:09 AM, Laxman Dewangan wrote: Use key code macros for all key code refernced for keys. For tegra20-seaboard.dts and tegra20-harmony.dts: The key comment for key (16th row and 1st column) is KEY_KPSLASH but code is 0x004e which is the key code for KEY_KPPLUS. As there other key exist with KY_KPPLUS, I am assuming key code is wrong and comment is fine. With this assumption, I am keeping the key code as KEY_KPSLASH. This looks reasonable, and I'll apply it soon. What is the patch based on? Note that I recently sent a patch to fix the sort order of DT nodes in all Tegra DT files, which I'll apply early since it's a cleanup, and IIRC some of the KBC nodes may have been moved by that patch, so this may conflict. I'll see if I can rebase while applying it. I worked on linux-next of 20131202. If there is any issue, I can generate new patch based on the branch which you suggest. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Changes as per new macros.
arch/arm/boot/dts/tegra114-dalmore.dts | 549
1 files changed, 275 insertions(+), 274 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23..5930a2d 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include
+#include
#include "tegra114.dtsi"
/ {
@@ -19,41 +20,41 @@
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
@@ -61,17 +62,17 @@
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
ulpi_clk_py0 {
[PATCH V2 1/2] ARM: tegra: Add header file for pinctrl constants
This new header file defines pincontrol constants for Tegra to use from Tegra's DTS file for pincontrol properties option. Signed-off-by: Laxman Dewangan --- Changes from V1: - Get rid of lots of macro and converge it to TEGRA_PIN_ENABLE/DISABLE. - Change macro name for PULL UP/DOWN/NONE. include/dt-bindings/pinctrl/pinctrl-tegra.h | 40 +++ 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 000..e5f02f8 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,40 @@ +/* + * This header provides constants for TEGRA pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +/* Pull up/down/normal */ +#define TEGRA_PIN_PULL_NONE0 +#define TEGRA_PIN_PULL_DOWN1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +#define TEGRA_PIN_SLEW_RATE_FASTEST0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST3 + +#endif -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
On Monday 02 December 2013 07:55 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Mon, Dec 02, 2013 at 07:25:01PM +0530, Laxman Dewangan wrote: + +/* Schmitt enable/disable */ +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE0 +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1 These are all boolean, so I wonder if perhaps we should be simply defining a single pair and reuse that in different contexts: #define TEGRA_PIN_DISABLE 0 #define TEGRA_PIN_ENABLE1 The property names should provide enough context for them to be used unambiguously. I can make generic ENABLE/DISABLE macro as you suggested but datasheet says as 0=NORMAL, 1 = TRISTATE. and that's why I kept name very near to the datasheet. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: tegra: convert device tree file of Dalmore to use pinctrl defines
Signed-off-by: Laxman Dewangan
---
arch/arm/boot/dts/tegra114-dalmore.dts | 549
1 files changed, 275 insertions(+), 274 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23..ea0eb31 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include
+#include
#include "tegra114.dtsi"
/ {
@@ -19,41 +20,41 @@
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <1>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
@@ -61,17 +62,17 @@
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <1>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- nvidia,enable-input = <0>;
+ nvidia,pull = ;
+ nvidia,tristate = ;
+ nvidia,enable-input = ;
};
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +85,128
[PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants
Defines pincontrol constants to use from Tegra's DTS file for tegra pincontrol properties option. Signed-off-by: Laxman Dewangan --- include/dt-bindings/pinctrl/pinctrl-tegra.h | 65 +++ 1 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 000..c2bfa3f --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,65 @@ +/* + * This header provides constants for TEGRA pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* Input/output */ +#define TEGRA_PIN_OUTPUT 0 +#define TEGRA_PIN_INPUT1 + +/* Pull up/down/normal */ +#define TEGRA_PIN_PUPD_NORMAL 0 +#define TEGRA_PIN_PUPD_PULL_DOWN 1 +#define TEGRA_PIN_PUPD_PULL_UP 2 + +/* Tristate/normal */ +#define TEGRA_PIN_NORMAL 0 +#define TEGRA_PIN_TRISTATE 1 + +/* Rcv Sel enable/disable */ +#define TEGRA_PIN_RCV_SEL_DISABLE 0 +#define TEGRA_PIN_RCV_SEL_ENABLE 1 + +/* Lock enable/disable */ +#define TEGRA_PIN_LOCK_DISABLE 0 +#define TEGRA_PIN_LOCK_ENABLE 1 + +/* Open drain enable/disable */ +#define TEGRA_PIN_OPEN_DRAIN_DISABLE 0 +#define TEGRA_PIN_OPEN_DRAIN_ENABLE1 + +/* High speed mode */ +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_DISABLE0 +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE 1 + +/* Schmitt enable/disable */ +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE0 +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1 + +/* Low power mode */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +#define TEGRA_PIN_SLEW_RATE_FASTEST0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST3 + +#endif -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: tegra: convert device tree files to use key defines
Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan
---
arch/arm/boot/dts/tegra20-harmony.dts | 221 +-
arch/arm/boot/dts/tegra20-paz00.dts |3 +-
arch/arm/boot/dts/tegra20-seaboard.dts | 261 ---
arch/arm/boot/dts/tegra20-trimslice.dts |3 +-
arch/arm/boot/dts/tegra20-ventana.dts |3 +-
arch/arm/boot/dts/tegra20-whistler.dts |9 +-
6 files changed, 253 insertions(+), 247 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts
b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab3..8f79fc3 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,5 +1,6 @@
/dts-v1/;
+#include
#include "tegra20.dtsi"
/ {
@@ -502,7 +503,7 @@
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
- linux,code = <116>; /* KEY_POWER */
+ linux,code = ;
gpio-key,wakeup;
};
};
@@ -513,115 +514,115 @@
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
- linux,keymap = <0x00020011 /* KEY_W */
- 0x0003001F /* KEY_S */
- 0x0004001E /* KEY_A */
- 0x0005002C /* KEY_Z */
- 0x000701D0 /* KEY_FN */
- 0x0107008B /* KEY_MENU */
- 0x02060038 /* KEY_LEFTALT */
- 0x02070064 /* KEY_RIGHTALT */
- 0x0306 /* KEY_5 */
- 0x03010005 /* KEY_4 */
- 0x03020013 /* KEY_R */
- 0x03030012 /* KEY_E */
- 0x03040021 /* KEY_F */
- 0x03050020 /* KEY_D */
- 0x0306002D /* KEY_X */
- 0x0408 /* KEY_7 */
- 0x04010007 /* KEY_6 */
- 0x04020014 /* KEY_T */
- 0x04030023 /* KEY_H */
- 0x04040022 /* KEY_G */
- 0x0405002F /* KEY_V */
- 0x0406002E /* KEY_C */
- 0x04070039 /* KEY_SPACE */
- 0x050A /* KEY_9 */
- 0x05010009 /* KEY_8 */
- 0x05020016 /* KEY_U */
- 0x05030015 /* KEY_Y */
- 0x05040024 /* KEY_J */
- 0x05050031 /* KEY_N */
- 0x05060030 /* KEY_B */
- 0x0507002B /* KEY_BACKSLASH */
- 0x060C /* KEY_MINUS */
- 0x0601000B /* KEY_0 */
- 0x06020018 /* KEY_O */
- 0x06030017 /* KEY_I */
- 0x06040026 /* KEY_L */
- 0x06050025 /* KEY_K */
- 0x06060033 /* KEY_COMMA */
- 0x06070032 /* KEY_M */
- 0x0701000D /* KEY_EQUAL */
- 0x0702001B /* KEY_RIGHTBRACE */
- 0x0703001C /* KEY_ENTER */
- 0x0707008B /* KEY_MENU */
- 0x0804002A /* KEY_LEFTSHIFT */
- 0x08050036 /* KEY_RIGHTSHIFT */
- 0x0905001D /* KEY_LEFTCTRL */
- 0x09070061 /* KEY_RIGHTCTRL */
- 0x0B1A /* KEY_LEFTBRACE */
- 0x0B010019 /* KEY_P */
- 0x0B020028 /* KEY_APOSTROPHE */
- 0x0B030027 /* KEY_SEMICOLON */
- 0x0B040035 /* KEY_SLASH */
-
[PATCH] ARM: tegra: add port FF to GPIO ID's
From: Ashwini Ghuge NVIDIA Tegra124 supports has the new gpio port as GPIO_FF. Add the macro for this port name. Signed-off-by: Ashwini Ghuge Signed-off-by: Laxman Dewangan --- include/dt-bindings/gpio/tegra-gpio.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h index 4d179c0..197dc28 100644 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ b/include/dt-bindings/gpio/tegra-gpio.h @@ -43,6 +43,7 @@ #define TEGRA_GPIO_BANK_ID_CC 28 #define TEGRA_GPIO_BANK_ID_DD 29 #define TEGRA_GPIO_BANK_ID_EE 30 +#define TEGRA_GPIO_BANK_ID_FF 31 #define TEGRA_GPIO(bank, offset) \ ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/5] mfd: as3722: add DT details for clock support of ams AS3722
Add DT details for using the clocks from ams AS3722. Signed-off-by: Laxman Dewangan --- Changes from V1: - This is new patch of series which was part of code change, splitting it on different change. Documentation/devicetree/bindings/mfd/as3722.txt |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt index fc2191e..e782f39 100644 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -112,6 +112,15 @@ Following are properties of regulator subnode. ams,enable-tracking: Enable tracking with SD1, only supported by LDO3. +Clock: +== +AS3722 supports one 32KHz clock to output from device. The clock control is +provided through the clock driver. +This binding uses the common clock binding ./clock-bindings.txt. +The device node should have the optional properties to support the clock: +#clock-cells: from common clock binding; shall be set to 1. The clock id for + single clock output is 0. + Example: #include -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/5] mfd: as3722: add clock driver as mfd-sub device
Device ams AS3722 supports the one 32KHz clock output. The clock
control support is provided through clock driver.
Add clock driver as mfd sub device to probe the clock driver.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Move the DT doc change to separate change.
drivers/mfd/as3722.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/mfd/as3722.c b/drivers/mfd/as3722.c
index f161f2e..1d3415c 100644
--- a/drivers/mfd/as3722.c
+++ b/drivers/mfd/as3722.c
@@ -72,6 +72,9 @@ static struct mfd_cell as3722_devs[] = {
.resources = as3722_adc_resource,
},
{
+ .name = "as3722-clk",
+ },
+ {
.name = "as3722-power-off",
},
};
--
1.7.1.1
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[PATCH V2 3/5] clk: as3722: add clock driver for ams AS3722
Device ams AS3722 supports one clock 32KHz output. Add clock driver
to control the clock through clock framework.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- None.
drivers/clk/Kconfig |8 ++
drivers/clk/Makefile |1 +
drivers/clk/clk-as3722.c | 161 ++
3 files changed, 170 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/clk-as3722.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5c51115..03257bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -78,6 +78,14 @@ config CLK_TWL6040
McPDM. McPDM module is using the external bit clock on the McPDM bus
as functional clock.
+config COMMON_CLK_AS3722
+ tristate "ams AS3722 clock32K driver"
+ depends on MFD_AS3722
+ help
+ ---help---
+ Supports the clocking subsystem of the ams AS3722 PMIC from ams.
+ This device supports one 32KHz clock.
+
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
depends on ARCH_ZYNQ || MICROBLAZE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fe3121b..b94624d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_X86) += x86/
# Chip specific
+obj-$(CONFIG_COMMON_CLK_AS3722) += clk-as3722.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
diff --git a/drivers/clk/clk-as3722.c b/drivers/clk/clk-as3722.c
new file mode 100644
index 000..0f786c3
--- /dev/null
+++ b/drivers/clk/clk-as3722.c
@@ -0,0 +1,161 @@
+/*
+ * Clock driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_clks {
+ struct device *dev;
+ struct as3722 *as3722;
+ struct clk_hw hw;
+ struct clk *clk;
+ struct clk_onecell_data clk_data;
+};
+
+static inline struct as3722_clks *to_as3722_clks(struct clk_hw *hw)
+{
+ return container_of(hw, struct as3722_clks, hw);
+}
+
+static unsigned long as3722_clks_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return 32768;
+}
+
+static int as3722_clks_prepare(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+
+ ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG,
+ AS3722_RTC_CLK32K_OUT_EN, AS3722_RTC_CLK32K_OUT_EN);
+ if (ret < 0)
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n",
+ ret);
+
+ return ret;
+}
+
+static void as3722_clks_unprepare(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+
+ ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG,
+ AS3722_RTC_CLK32K_OUT_EN, 0);
+ if (ret < 0)
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n",
+ ret);
+}
+
+static int as3722_clks_is_prepared(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+ u32 val;
+
+ ret = as3722_read(as3722_clks->as3722, AS3722_RTC_CONTROL_REG, &val);
+ if (ret < 0) {
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG read failed, %d\n",
+ ret);
+ return ret;
+ }
+
+ return !!(val & AS3722_RTC_CLK32K_OUT_EN);
+}
+
+static struct clk_ops as3722_clks_ops = {
+ .prepare= as3722_clks_prepare,
+ .unprepare = as3722_clks_unprepare,
+ .is_prepared= as3722_clks_is_prepared,
+ .recalc_rate= as3722_clks_recalc_rate,
+};
+
+static struct clk_init_data as3722_clks_hw_init = {
+ .name = "clk32k",
+ .ops = &as3722_clks_ops,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+
+static int as3722_clks_probe(struct platform_device *pdev)
+{
+ struct as3722_clks *as3722_clks;
+ struct clk *clk;
+ int ret;
+
+ as3722_clks = devm_kzalloc(&pdev->dev, sizeof(*as3722_clks),
+ GFP_KERNEL);
+
[PATCH V2 4/5] mfd: AS3722: add dt node properties for system power controller
ams AS3722 device supports the power off by turning off its all rails. Add dt node properties to enable this functionality on this device. Signed-off-by: Laxman Dewangan --- Changes from V1: - None Documentation/devicetree/bindings/mfd/as3722.txt |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt index e782f39..1a2fa8a 100644 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -121,6 +121,15 @@ The device node should have the optional properties to support the clock: #clock-cells: from common clock binding; shall be set to 1. The clock id for single clock output is 0. +Power-off: += + +AS3722 supports the system power off by turning off all its rail. The power off +is provided through pm power off. +The device node should have the following properties to enable power-off +functionality from ams AS3722: +ams,system-power-controller: To enable the power off functionality through + device. Example: #include -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 5/5] power: reset: as3722: add power-off driver
ams AS3722 supports the power off functionality to turn off
system.
Add power off driver for ams AS3722.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- None
drivers/power/reset/Kconfig |6 ++
drivers/power/reset/Makefile |1 +
drivers/power/reset/as3722-poweroff.c | 96 +
3 files changed, 103 insertions(+), 0 deletions(-)
create mode 100644 drivers/power/reset/as3722-poweroff.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 9b3ea53..6d452a7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -6,6 +6,12 @@ menuconfig POWER_RESET
Say Y here to enable board reset and power off
+config POWER_RESET_AS3722
+ bool "ams AS3722 power-off driver"
+ depends on MFD_AS3722 && POWER_RESET
+ help
+ This driver supports turning off board via a ams AS3722 power-off.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 3e6ed88..a5b4a77 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/as3722-poweroff.c
b/drivers/power/reset/as3722-poweroff.c
new file mode 100644
index 000..0e489ff
--- /dev/null
+++ b/drivers/power/reset/as3722-poweroff.c
@@ -0,0 +1,96 @@
+/*
+ * Power off driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_poweroff {
+ struct device *dev;
+ struct as3722 *as3722;
+};
+
+static struct as3722_poweroff *as3722_pm_poweroff;
+
+static void as3722_pm_power_off(void)
+{
+ int ret;
+
+ if (!as3722_pm_poweroff) {
+ pr_err("AS3722 poweroff is not initialised\n");
+ return;
+ }
+
+ ret = as3722_update_bits(as3722_pm_poweroff->as3722,
+ AS3722_RESET_CONTROL_REG, AS3722_POWER_OFF, AS3722_POWER_OFF);
+ if (ret < 0)
+ dev_err(as3722_pm_poweroff->dev,
+ "RESET_CONTROL_REG update failed, %d\n", ret);
+}
+
+static int as3722_poweroff_probe(struct platform_device *pdev)
+{
+ struct as3722_poweroff *as3722_poweroff;
+ struct device_node *np = pdev->dev.parent->of_node;
+
+ if (!np)
+ return -EINVAL;
+
+ if (!of_property_read_bool(np, "ams,system-power-controller"))
+ return 0;
+
+ as3722_poweroff = devm_kzalloc(&pdev->dev, sizeof(*as3722_poweroff),
+ GFP_KERNEL);
+ if (!as3722_poweroff)
+ return -ENOMEM;
+
+ as3722_poweroff->as3722 = dev_get_drvdata(pdev->dev.parent);
+ as3722_poweroff->dev = &pdev->dev;
+ as3722_pm_poweroff = as3722_poweroff;
+ if (!pm_power_off)
+ pm_power_off = as3722_pm_power_off;
+
+ return 0;
+}
+
+static int as3722_poweroff_remove(struct platform_device *pdev)
+{
+ if (pm_power_off == as3722_pm_power_off)
+ pm_power_off = NULL;
+ as3722_pm_poweroff = NULL;
+
+ return 0;
+}
+
+static struct platform_driver as3722_poweroff_driver = {
+ .driver = {
+ .name = "as3722-power-off",
+ .owner = THIS_MODULE,
+ },
+ .probe = as3722_poweroff_probe,
+ .remove = as3722_poweroff_remove,
+};
+
+module_platform_driver(as3722_poweroff_driver);
+
+MODULE_DESCRIPTION("Power off driver for ams AS3722 PMIC Device");
+MODULE_ALIAS("platform:as3722-power-off");
+MODULE_AUTHOR("Laxman Dewangan ");
+MODULE_LICENSE("GPL v2");
--
1.7.1.1
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[PATCH V2 0/5] clk/power: add clock and power off driver for AS3722
Add power off and clock driver for the ams AS3722. The mfd patches are depends on mfd subtree which can be applied independtly. The pacthes are created such that clock driver can go in clock tree and power off driver in power sub tree. Changes from V1: - Split the DT doc and driver change in two changes. - Keeping all other code same as V1. Laxman Dewangan (5): mfd: as3722: add clock driver as mfd-sub device mfd: as3722: add DT details for clock support of ams AS3722 clk: as3722: add clock driver for ams AS3722 mfd: AS3722: add dt node properties for system power controller power: reset: as3722: add power-off driver Documentation/devicetree/bindings/mfd/as3722.txt | 18 +++ drivers/clk/Kconfig |8 + drivers/clk/Makefile |1 + drivers/clk/clk-as3722.c | 166 ++ drivers/mfd/as3722.c |3 + drivers/power/reset/Kconfig |6 + drivers/power/reset/Makefile |1 + drivers/power/reset/as3722-poweroff.c| 101 + 8 files changed, 304 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-as3722.c create mode 100644 drivers/power/reset/as3722-poweroff.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] power: reset: as3722: add power-off driver
ams AS3722 supports the power off functionality to turn off
system.
Add power off driver for ams AS3722.
Signed-off-by: Laxman Dewangan
---
drivers/power/reset/Kconfig |6 ++
drivers/power/reset/Makefile |1 +
drivers/power/reset/as3722-poweroff.c | 101 +
3 files changed, 108 insertions(+), 0 deletions(-)
create mode 100644 drivers/power/reset/as3722-poweroff.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 9b3ea53..6d452a7 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -6,6 +6,12 @@ menuconfig POWER_RESET
Say Y here to enable board reset and power off
+config POWER_RESET_AS3722
+ bool "ams AS3722 power-off driver"
+ depends on MFD_AS3722 && POWER_RESET
+ help
+ This driver supports turning off board via a ams AS3722 power-off.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 3e6ed88..a5b4a77 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/as3722-poweroff.c
b/drivers/power/reset/as3722-poweroff.c
new file mode 100644
index 000..64e7c7f
--- /dev/null
+++ b/drivers/power/reset/as3722-poweroff.c
@@ -0,0 +1,101 @@
+/*
+ * Power off driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_poweroff {
+ struct device *dev;
+ struct as3722 *as3722;
+};
+
+static struct as3722_poweroff *as3722_pm_poweroff;
+
+static void as3722_pm_power_off(void)
+{
+ int ret;
+
+ if (!as3722_pm_poweroff) {
+ pr_err("AS3722 poweroff is not initialised\n");
+ return;
+ }
+
+ ret = as3722_update_bits(as3722_pm_poweroff->as3722,
+ AS3722_RESET_CONTROL_REG, AS3722_POWER_OFF, AS3722_POWER_OFF);
+ if (ret < 0)
+ dev_err(as3722_pm_poweroff->dev,
+ "RESET_CONTROL_REG update failed, %d\n", ret);
+}
+
+static int as3722_poweroff_probe(struct platform_device *pdev)
+{
+ struct as3722_poweroff *as3722_poweroff;
+ struct device_node *np = pdev->dev.parent->of_node;
+
+ if (!np)
+ return -EINVAL;
+
+ if (!of_property_read_bool(np, "ams,system-power-controller"))
+ return 0;
+
+ as3722_poweroff = devm_kzalloc(&pdev->dev, sizeof(*as3722_poweroff),
+ GFP_KERNEL);
+ if (!as3722_poweroff)
+ return -ENOMEM;
+
+ as3722_poweroff->as3722 = dev_get_drvdata(pdev->dev.parent);
+ as3722_poweroff->dev = &pdev->dev;
+ as3722_pm_poweroff = as3722_poweroff;
+ if (!pm_power_off)
+ pm_power_off = as3722_pm_power_off;
+
+ return 0;
+}
+
+static int as3722_poweroff_remove(struct platform_device *pdev)
+{
+ if (pm_power_off == as3722_pm_power_off)
+ pm_power_off = NULL;
+ as3722_pm_poweroff = NULL;
+
+ return 0;
+}
+
+static struct platform_driver as3722_poweroff_driver = {
+ .driver = {
+ .name = "as3722-power-off",
+ .owner = THIS_MODULE,
+ },
+ .probe = as3722_poweroff_probe,
+ .remove = as3722_poweroff_remove,
+};
+
+module_platform_driver(as3722_poweroff_driver);
+
+MODULE_DESCRIPTION("Power off driver for ams AS3722 PMIC Device");
+MODULE_ALIAS("platform:as3722-power-off");
+MODULE_AUTHOR("Laxman Dewangan ");
+MODULE_LICENSE("GPL v2");
--
1.7.1.1
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[PATCH 3/4] mfd: AS3722: add dt node properties for system power controller
ams AS3722 device supports the power off by turning off its all rails. Add dt node properties to enable this functionality on this device. Signed-off-by: Laxman Dewangan --- Documentation/devicetree/bindings/mfd/as3722.txt |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt index e782f39..1a2fa8a 100644 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -121,6 +121,15 @@ The device node should have the optional properties to support the clock: #clock-cells: from common clock binding; shall be set to 1. The clock id for single clock output is 0. +Power-off: += + +AS3722 supports the system power off by turning off all its rail. The power off +is provided through pm power off. +The device node should have the following properties to enable power-off +functionality from ams AS3722: +ams,system-power-controller: To enable the power off functionality through + device. Example: #include -- 1.7.1.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] mfd: as3722: add clock driver as mfd-sub device for the ams AS3722
Device ams AS3722 supports the one 32KHz clock output. The clock control
support is provided through clock driver.
Add clock driver as mfd sub device to probe the clock driver.
Signed-off-by: Laxman Dewangan
---
Documentation/devicetree/bindings/mfd/as3722.txt |9 +
drivers/mfd/as3722.c |3 +++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt
b/Documentation/devicetree/bindings/mfd/as3722.txt
index fc2191e..e782f39 100644
--- a/Documentation/devicetree/bindings/mfd/as3722.txt
+++ b/Documentation/devicetree/bindings/mfd/as3722.txt
@@ -112,6 +112,15 @@ Following are properties of regulator subnode.
ams,enable-tracking: Enable tracking with SD1, only supported
by LDO3.
+Clock:
+==
+AS3722 supports one 32KHz clock to output from device. The clock control is
+provided through the clock driver.
+This binding uses the common clock binding ./clock-bindings.txt.
+The device node should have the optional properties to support the clock:
+#clock-cells: from common clock binding; shall be set to 1. The clock id for
+ single clock output is 0.
+
Example:
#include
diff --git a/drivers/mfd/as3722.c b/drivers/mfd/as3722.c
index f161f2e..1d3415c 100644
--- a/drivers/mfd/as3722.c
+++ b/drivers/mfd/as3722.c
@@ -72,6 +72,9 @@ static struct mfd_cell as3722_devs[] = {
.resources = as3722_adc_resource,
},
{
+ .name = "as3722-clk",
+ },
+ {
.name = "as3722-power-off",
},
};
--
1.7.1.1
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[PATCH 2/4] clk: as3722: add clock driver for ams AS3722
Device ams AS3722 supports one clock 32KHz output. Add clock driver
to control the clock through clock framework.
Signed-off-by: Laxman Dewangan
---
drivers/clk/Kconfig |8 ++
drivers/clk/Makefile |1 +
drivers/clk/clk-as3722.c | 166 ++
3 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/clk-as3722.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5c51115..03257bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -78,6 +78,14 @@ config CLK_TWL6040
McPDM. McPDM module is using the external bit clock on the McPDM bus
as functional clock.
+config COMMON_CLK_AS3722
+ tristate "ams AS3722 clock32K driver"
+ depends on MFD_AS3722
+ help
+ ---help---
+ Supports the clocking subsystem of the ams AS3722 PMIC from ams.
+ This device supports one 32KHz clock.
+
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
depends on ARCH_ZYNQ || MICROBLAZE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fe3121b..b94624d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_X86) += x86/
# Chip specific
+obj-$(CONFIG_COMMON_CLK_AS3722) += clk-as3722.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
diff --git a/drivers/clk/clk-as3722.c b/drivers/clk/clk-as3722.c
new file mode 100644
index 000..9358029
--- /dev/null
+++ b/drivers/clk/clk-as3722.c
@@ -0,0 +1,166 @@
+/*
+ * Clock driver for ams AS3722 device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct as3722_clks {
+ struct device *dev;
+ struct as3722 *as3722;
+ struct clk_hw hw;
+ struct clk *clk;
+ struct clk_onecell_data clk_data;
+};
+
+static inline struct as3722_clks *to_as3722_clks(struct clk_hw *hw)
+{
+ return container_of(hw, struct as3722_clks, hw);
+}
+
+static unsigned long as3722_clks_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return 32768;
+}
+
+static int as3722_clks_prepare(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+
+ ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG,
+ AS3722_RTC_CLK32K_OUT_EN, AS3722_RTC_CLK32K_OUT_EN);
+ if (ret < 0)
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n",
+ ret);
+
+ return ret;
+}
+
+static void as3722_clks_unprepare(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+
+ ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG,
+ AS3722_RTC_CLK32K_OUT_EN, 0);
+ if (ret < 0)
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n",
+ ret);
+}
+
+static int as3722_clks_is_prepared(struct clk_hw *hw)
+{
+ struct as3722_clks *as3722_clks = to_as3722_clks(hw);
+ int ret;
+ u32 val;
+
+ ret = as3722_read(as3722_clks->as3722, AS3722_RTC_CONTROL_REG, &val);
+ if (ret < 0) {
+ dev_err(as3722_clks->dev, "RTC_CONTROL_REG read failed, %d\n",
+ ret);
+ return ret;
+ }
+
+ return !!(val & AS3722_RTC_CLK32K_OUT_EN);
+}
+
+static struct clk_ops as3722_clks_ops = {
+ .prepare= as3722_clks_prepare,
+ .unprepare = as3722_clks_unprepare,
+ .is_prepared= as3722_clks_is_prepared,
+ .recalc_rate= as3722_clks_recalc_rate,
+};
+
+static struct clk_init_data as3722_clks_hw_init = {
+ .name = "clk32k",
+ .ops = &as3722_clks_ops,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+
+static int as3722_clks_probe(struct platform_device *pdev)
+{
+ struct as3722_clks *a
[PATCH 0/4] clk/power: add clock and power off driver for AS3722
Add power off and clock driver for the ams AS3722. The mfd patches are depends on mfd subtree which can be applied independtly. The pacthes are created such that clock driver can go in clock tree and power off driver in power sub tree. Laxman Dewangan (4): mfd: as3722: add clock driver as mfd-sub device for the ams AS3722 clk: as3722: add clock driver for ams AS3722 mfd: AS3722: add dt node properties for system power controller power: reset: as3722: add power-off driver Documentation/devicetree/bindings/mfd/as3722.txt | 18 +++ drivers/clk/Kconfig |8 + drivers/clk/Makefile |1 + drivers/clk/clk-as3722.c | 166 ++ drivers/mfd/as3722.c |3 + drivers/power/reset/Kconfig |6 + drivers/power/reset/Makefile |1 + drivers/power/reset/as3722-poweroff.c| 101 + 8 files changed, 304 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-as3722.c create mode 100644 drivers/power/reset/as3722-poweroff.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V6 3/3] drivers/rtc/rtc-as3722: add RTC driver
Hi Andrew, Can you please review this patch? If it is lost then I will be happy to repost it. Thanks, Laxman On Monday 21 October 2013 05:17 PM, Laxman Dewangan wrote: The ams AS3722 is a compact system PMU suitable for mobile phones, tablets etc. Add a driver to support accessing the RTC found on the ams AS3722 PMIC using RTC framework. Signed-off-by: Laxman Dewangan Signed-off-by: Florian Lobmaier -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 REPOST] mfd: add support for ams AS3722 PMIC
The ams AS3722 is a compact system PMU suitable for mobile phones, tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down controller, 11 LDOs, RTC, automatic battery, temperature and over-current monitoring, 8 GPIOs, ADC and a watchdog. Add MFD core driver for the AS3722 to support core functionality. Signed-off-by: Laxman Dewangan Signed-off-by: Florian Lobmaier Acked-by: Lee Jones Acked-by: Stephen Warren --- Changes from V1: - Remove compatible string from DT for subnode. - Nit cleanups in driver and use module_i2c_driver Changes from V2: - Change DT file to reflect the changes in gpio/pincntrl driver. Now there is no extra subnode. Changes from V3: - Combine DT of pincontrol and regulator to mfd. - Nits cleanups. - AMS to ams. Changes from V4: - Rephrased the dt binding documents. - Added dt-binding header for DTS file. - Fix some of indention issue in dt documents. Reposting V5 as per Lee's. Documentation/devicetree/bindings/mfd/as3722.txt | 194 ++ drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile |1 + drivers/mfd/as3722.c | 449 ++ include/dt-bindings/mfd/as3722.h | 52 +++ include/linux/mfd/as3722.h | 423 6 files changed, 1131 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/as3722.txt create mode 100644 drivers/mfd/as3722.c create mode 100644 include/dt-bindings/mfd/as3722.h create mode 100644 include/linux/mfd/as3722.h diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt new file mode 100644 index 000..fc2191e --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -0,0 +1,194 @@ +* ams AS3722 Power management IC. + +Required properties: +--- +- compatible: Must be "ams,as3722". +- reg: I2C device address. +- interrupt-controller: AS3722 has internal interrupt controller which takes the + interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well + as external input. +- #interrupt-cells: Should be set to 2 for IRQ number and flags. + The first cell is the IRQ number. IRQ numbers for different interrupt source + of AS3722 are defined at dt-bindings/mfd/as3722.h + The second cell is the flags, encoded as the trigger masks from binding document + interrupts.txt, using dt-bindings/irq. + +Optional submodule and their properties: +=== + +Pinmux and GPIO: +=== +Device has 8 GPIO pins which can be configured as GPIO as well as the special IO +functions. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Following are properties which is needed if GPIO and pinmux functionality +is required: +Required properties: +--- + - gpio-controller: Marks the device node as a GPIO controller. + - #gpio-cells: Number of GPIO cells. Refer to binding document + gpio/gpio.txt + +Optional properties: + + Following properties are require if pin control setting is required + at boot. + - pinctrl-names: A pinctrl state named "default" be defined, using the + bindings in pinctrl/pinctrl-binding.txt. + - pinctrl[0...n]: Properties to contain the phandle that refer to + different nodes of pin control settings. These nodes represents + the pin control setting of state 0 to state n. Each of these + nodes contains different subnodes to represents some desired + configuration for a list of pins. This configuration can + include the mux function to select on those pin(s), and + various pin configuration parameters, such as pull-up, + open drain. + + Each subnode have following properties: + Required properties: + - pins: List of pins. Valid values of pins properties are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, + gpio6, gpio7 + + Optional properties: + function, bias-disable, bias-pull-up, bias-pull-down, + bias-high-impedance, drive-open-drain. + + Valid values for function properties are: + gpio, interrupt-out, gpio-in-interrupt, + vsup-vbat-low-undebounce-out, + vsup-vbat-low-debounce-out, + voltage-in-standby, oc-pg-sd0, oc-pg-sd6, + powergo
Re: [PATCH V4] clk: palmas: add clock driver for palmas
Hi Mike, On Wednesday 09 October 2013 04:34 PM, Laxman Dewangan wrote: Palmas devices has two clock output CLK32K_KG and CLK32K_KG_AUDIO which can be enable/disable through software. Add clock driver support for the Palmas 32KHz clocks. Can you please review this version? I have taken care of all earlier feedbacks. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V6 3/3] drivers/rtc/rtc-as3722: add RTC driver
The ams AS3722 is a compact system PMU suitable for mobile phones,
tablets etc.
Add a driver to support accessing the RTC found on the ams AS3722
PMIC using RTC framework.
Signed-off-by: Laxman Dewangan
Signed-off-by: Florian Lobmaier
---
Changes from V1:
- Get rid of clk32k out configuration from RTC. Will add clock driver.
Changes from V2:
- None.
Changes form V3:
- Change AMS to ams.
Changes form V4:
- None
Changes from V5:
- Use CONFIG_PM_SLEEP instead of CONFIG_PM
- Remove compatiable as it is not used.
- use masked updates for bit enable in place of write to avoid unintentional
change.
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-as3722.c | 280 ++
3 files changed, 291 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-as3722.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 9654aa3..d8785d7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -153,6 +153,16 @@ config RTC_DRV_88PM80X
This driver can also be built as a module. If so, the module
will be called rtc-88pm80x.
+config RTC_DRV_AS3722
+ tristate "ams AS3722 RTC driver"
+ depends on MFD_AS3722
+ help
+ If you say yes here you get support for the RTC of ams AS3722 PMIC
+ chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-as3722.
+
config RTC_DRV_DS1307
tristate "Dallas/Maxim DS1307/37/38/39/40, ST M41T00, EPSON RX-8025"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2dff3d2..fdb5764 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
+obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
diff --git a/drivers/rtc/rtc-as3722.c b/drivers/rtc/rtc-as3722.c
new file mode 100644
index 000..a796e8f
--- /dev/null
+++ b/drivers/rtc/rtc-as3722.c
@@ -0,0 +1,280 @@
+/*
+ * rtc-as3722.c - Real Time Clock driver for ams AS3722 PMICs
+ *
+ * Copyright (C) 2013 ams AG
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * Author: Florian Lobmaier
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define AS3722_RTC_START_YEAR2000
+struct as3722_rtc {
+ struct rtc_device *rtc;
+ struct device *dev;
+ struct as3722 *as3722;
+ int alarm_irq;
+ boolirq_enable;
+};
+
+static void as3722_time_to_reg(u8 *rbuff, struct rtc_time *tm)
+{
+ rbuff[0] = bin2bcd(tm->tm_sec);
+ rbuff[1] = bin2bcd(tm->tm_min);
+ rbuff[2] = bin2bcd(tm->tm_hour);
+ rbuff[3] = bin2bcd(tm->tm_mday);
+ rbuff[4] = bin2bcd(tm->tm_mon);
+ rbuff[5] = bin2bcd(tm->tm_year - (AS3722_RTC_START_YEAR - 1900));
+}
+
+static void as3722_reg_to_time(u8 *rbuff, struct rtc_time *tm)
+{
+ tm->tm_sec = bcd2bin(rbuff[0] & 0x7F);
+ tm->tm_min = bcd2bin(rbuff[1] & 0x7F);
+ tm->tm_hour = bcd2bin(rbuff[2] & 0x3F);
+ tm->tm_mday = bcd2bin(rbuff[3] & 0x3F);
+ tm->tm_mon = bcd2bin(rbuff[4] & 0x1F);
+ tm->tm_year = (AS3722_RTC_START_YEAR - 1900) + bcd2bin(rbuff[5] & 0x7F);
+ return;
+}
+
+static int as3722_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct as3722_rtc *as3722_rtc = dev_get_drvdata(dev);
+ struct as3722 *as3722 = as3722_rtc->as3722;
+ u8 as_time_array[6];
+ int ret;
+
+ ret = as3722_block_read(as3722, AS3722_RTC_SECOND_REG,
+ 6, as_time_array);
+ if (ret < 0) {
+ dev_err(dev, "RTC_SECOND reg block read failed %d\n", ret);
+ return
Re: [PATCH V5 1/3] mfd: add support for ams AS3722 PMIC
Hi Lee/Samuel, On Wednesday 09 October 2013 09:43 PM, Stephen Warren wrote: On 10/09/2013 06:29 AM, Laxman Dewangan wrote: The ams AS3722 is a compact system PMU suitable for mobile phones, tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down controller, 11 LDOs, RTC, automatic battery, temperature and over-current monitoring, 8 GPIOs, ADC and a watchdog. Add MFD core driver for the AS3722 to support core functionality. OK, I think the binding here is about clear enough, so the binding, Acked-by: Stephen Warren I saw that Lee has already acked this (V4) for the nondt side. As there is no issue on dt side also, can it be apply please? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V5 3/3] drivers/rtc/rtc-as3722: add RTC driver
On Friday 11 October 2013 04:17 AM, Mark Brown wrote: * PGP Signed by an unknown key On Thu, Oct 10, 2013 at 03:24:46PM -0700, Andrew Morton wrote: +#ifdef CONFIG_PM Most (but not all!) rtc drivers use CONFIG_PM_SLEEP. People have madly mucked with CONFIG_PM* and I don't know the difference and I don't know what's going on and I don't know of a convenient place to go to find out. If you work it out, please be sure to tell me! But as soon as I figure it out I'm sure they'll go and madly muck with it again. The two effective options for this stuff are PM_SLEEP (for system suspend) and PM_RUNTIME (for runtime suspend which RTCs are unlikely to use I guess). PM mostly just enables selection of the other two. I think, correct defs is CONFIG_PM_SLEEP here. I will re-spin this patch. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6] extcon: palmas: Added a new compatible type *ti,palmas-usb-vid*
On Thursday 10 October 2013 06:07 PM, Kishon Vijay Abraham I wrote: The Palmas device contains only a USB VBUS-ID detector, so added a compatible type *ti,palmas-usb-vid*. Didn't remove the existing compatible types for backward compatibility. I dont have much issue on this nomenclature but just second thought: The Palmas USB module is capable of detection VBUS, ID-GND, ID-RA, ID-RB, ID-RC and ID-FLOAT as per BC1.2. This sub-module only detect the cable, does nothing more than this. In this case, should we say "ti,palmas-usb-extcon"? Again extcon is linux specific terminology and this can be defer. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [rtc-linux] [PATCH V5 2/3] pincntrl: add support for ams AS3722 pin control driver
On Tuesday 08 October 2013 05:46 PM, Linus Walleij wrote: On Wed, Oct 2, 2013 at 5:50 PM, Laxman Dewangan wrote: The AS3722 is a compact system PMU suitable for mobile phones, tablets etc. Add a driver to support accessing the GPIO, pinmux and pin configuration of 8 GPIO pins found on the ams AS3722 through pin control driver and gpiolib. The driver will register itself as the pincontrol driver and gpio driver. Signed-off-by: Laxman Dewangan --- Changes from V1: - Nit cleanups in driver and use module_platform_driver. Changes from V2: - Move the gpio driver from gpio folder to pinctnrl driver and register driver as pincontrol driver. - Provide pin configuration through pincntrl framework. Changes from V3: - Added gpio ranges and pinctrl_gpio calls. - Used pinctrl_gpio_* calls on gpio chips callback. - Remove dummy function which just return not supported. - Nit cleanups. Changes from V4: - Drop separate DT binding document as it is moved to mfd/as3722.txt. As mentioned I am happy with this driver, Acked-by: Linus Walleij When you agreed with the DT folks and want me to merge it, tell me. Stephen has given the ACK from DT side, so I think you can merge this patch. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 1/3] mfd: add support for ams AS3722 PMIC
The ams AS3722 is a compact system PMU suitable for mobile phones, tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down controller, 11 LDOs, RTC, automatic battery, temperature and over-current monitoring, 8 GPIOs, ADC and a watchdog. Add MFD core driver for the AS3722 to support core functionality. Signed-off-by: Laxman Dewangan Signed-off-by: Florian Lobmaier Acked-by: Lee Jones --- Changes from V1: - Remove compatible string from DT for subnode. - Nit cleanups in driver and use module_i2c_driver Changes from V2: - Change DT file to reflect the changes in gpio/pincntrl driver. Now there is no extra subnode. Changes from V3: - Combine DT of pincontrol and regulator to mfd. - Nits cleanups. - AMS to ams. Changes from V4: - Rephrased the dt binding documents. - Added dt-binding header for DTS file. - Fix some of indention issue in dt documents. Documentation/devicetree/bindings/mfd/as3722.txt | 194 ++ drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile |1 + drivers/mfd/as3722.c | 449 ++ include/dt-bindings/mfd/as3722.h | 52 +++ include/linux/mfd/as3722.h | 423 6 files changed, 1131 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/as3722.txt create mode 100644 drivers/mfd/as3722.c create mode 100644 include/dt-bindings/mfd/as3722.h create mode 100644 include/linux/mfd/as3722.h diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt new file mode 100644 index 000..fc2191e --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/as3722.txt @@ -0,0 +1,194 @@ +* ams AS3722 Power management IC. + +Required properties: +--- +- compatible: Must be "ams,as3722". +- reg: I2C device address. +- interrupt-controller: AS3722 has internal interrupt controller which takes the + interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well + as external input. +- #interrupt-cells: Should be set to 2 for IRQ number and flags. + The first cell is the IRQ number. IRQ numbers for different interrupt source + of AS3722 are defined at dt-bindings/mfd/as3722.h + The second cell is the flags, encoded as the trigger masks from binding document + interrupts.txt, using dt-bindings/irq. + +Optional submodule and their properties: +=== + +Pinmux and GPIO: +=== +Device has 8 GPIO pins which can be configured as GPIO as well as the special IO +functions. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Following are properties which is needed if GPIO and pinmux functionality +is required: +Required properties: +--- + - gpio-controller: Marks the device node as a GPIO controller. + - #gpio-cells: Number of GPIO cells. Refer to binding document + gpio/gpio.txt + +Optional properties: + + Following properties are require if pin control setting is required + at boot. + - pinctrl-names: A pinctrl state named "default" be defined, using the + bindings in pinctrl/pinctrl-binding.txt. + - pinctrl[0...n]: Properties to contain the phandle that refer to + different nodes of pin control settings. These nodes represents + the pin control setting of state 0 to state n. Each of these + nodes contains different subnodes to represents some desired + configuration for a list of pins. This configuration can + include the mux function to select on those pin(s), and + various pin configuration parameters, such as pull-up, + open drain. + + Each subnode have following properties: + Required properties: + - pins: List of pins. Valid values of pins properties are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, + gpio6, gpio7 + + Optional properties: + function, bias-disable, bias-pull-up, bias-pull-down, + bias-high-impedance, drive-open-drain. + + Valid values for function properties are: + gpio, interrupt-out, gpio-in-interrupt, + vsup-vbat-low-undebounce-out, + vsup-vbat-low-debounce-out, + voltage-in-standby, oc-pg-sd0, oc-pg-sd6, + powergood-out, pwm-in, pwm-out, clk32k-out, + watchdog-i
[PATCH V5 0/3] Add AMS AS3722 mfd, pincontrol and RTC driver.
This series add the driver support for AMS AS3722 PMIC. The driver includes MFD, pincontrol and GPIO, regulator and RTC. Changes from V1: - Remove compatible string from DT for subnode. - Add macro in regmap.h for definign range. - Nit cleanups in driver and use module_i2c_driver/module_platform_driver. - Use linear_range and added regulator_map_* on regulators. - Move OC configuration to regulator_current limit setting. - Get rid of clk32k out configuration from RTC. Will add clock driver. Changes from V2: - Drop the already applied patches on V2 series regmap: add helper macro to set min/max range of register regulator: as3722: add regulator driver for AMS AS3722 - Move the GPIo driver to pincontrol driver to expose the pin configuration through pincontrol. - rewrite the DT binding of the mfd. Changes from V3: - Change AMS to ams - combine DT of regulator, pincontrol to the mfd. - Taken care of Lee's nits feedback. Changes from V4: - Rephrased the DT binding document. - Add header for dt-binding macros. Laxman Dewangan (3): mfd: add support for ams AS3722 PMIC pincntrl: add support for ams AS3722 pin control driver drivers/rtc/rtc-as3722: add RTC driver Documentation/devicetree/bindings/mfd/as3722.txt | 194 +++ drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile |1 + drivers/mfd/as3722.c | 449 +++ drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-as3722.c | 630 ++ drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile |1 + drivers/rtc/rtc-as3722.c | 296 ++ include/dt-bindings/mfd/as3722.h | 52 ++ include/linux/mfd/as3722.h | 423 +++ 12 files changed, 2080 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/as3722.txt create mode 100644 drivers/mfd/as3722.c create mode 100644 drivers/pinctrl/pinctrl-as3722.c create mode 100644 drivers/rtc/rtc-as3722.c create mode 100644 include/dt-bindings/mfd/as3722.h create mode 100644 include/linux/mfd/as3722.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 3/3] drivers/rtc/rtc-as3722: add RTC driver
The ams AS3722 is a compact system PMU suitable for mobile phones,
tablets etc.
Add a driver to support accessing the RTC found on the ams AS3722
PMIC using RTC framework.
Signed-off-by: Laxman Dewangan
Signed-off-by: Florian Lobmaier
---
Changes from V1:
- Get rid of clk32k out configuration from RTC. Will add clock driver.
Changes from V2:
- None.
Changes form V3:
- Change AMS to ams.
Changes form V4:
- None
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-as3722.c | 296 ++
3 files changed, 307 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-as3722.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 9654aa3..d8785d7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -153,6 +153,16 @@ config RTC_DRV_88PM80X
This driver can also be built as a module. If so, the module
will be called rtc-88pm80x.
+config RTC_DRV_AS3722
+ tristate "ams AS3722 RTC driver"
+ depends on MFD_AS3722
+ help
+ If you say yes here you get support for the RTC of ams AS3722 PMIC
+ chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-as3722.
+
config RTC_DRV_DS1307
tristate "Dallas/Maxim DS1307/37/38/39/40, ST M41T00, EPSON RX-8025"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2dff3d2..fdb5764 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
+obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
diff --git a/drivers/rtc/rtc-as3722.c b/drivers/rtc/rtc-as3722.c
new file mode 100644
index 000..430a927
--- /dev/null
+++ b/drivers/rtc/rtc-as3722.c
@@ -0,0 +1,296 @@
+/*
+ * rtc-as3722.c - Real Time Clock driver for ams AS3722 PMICs
+ *
+ * Copyright (C) 2013 ams AG
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * Author: Florian Lobmaier
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define AS3722_RTC_START_YEAR2000
+struct as3722_rtc {
+ struct rtc_device *rtc;
+ struct device *dev;
+ struct as3722 *as3722;
+ int alarm_irq;
+ boolirq_enable;
+};
+
+static void as3722_time_to_reg(u8 *rbuff, struct rtc_time *tm)
+{
+ rbuff[0] = bin2bcd(tm->tm_sec);
+ rbuff[1] = bin2bcd(tm->tm_min);
+ rbuff[2] = bin2bcd(tm->tm_hour);
+ rbuff[3] = bin2bcd(tm->tm_mday);
+ rbuff[4] = bin2bcd(tm->tm_mon);
+ rbuff[5] = bin2bcd(tm->tm_year - (AS3722_RTC_START_YEAR - 1900));
+}
+
+static void as3722_reg_to_time(u8 *rbuff, struct rtc_time *tm)
+{
+ tm->tm_sec = bcd2bin(rbuff[0] & 0x7F);
+ tm->tm_min = bcd2bin(rbuff[1] & 0x7F);
+ tm->tm_hour = bcd2bin(rbuff[2] & 0x3F);
+ tm->tm_mday = bcd2bin(rbuff[3] & 0x3F);
+ tm->tm_mon = bcd2bin(rbuff[4] & 0x1F);
+ tm->tm_year = (AS3722_RTC_START_YEAR - 1900) + bcd2bin(rbuff[5] & 0x7F);
+ return;
+}
+
+static int as3722_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct as3722_rtc *as3722_rtc = dev_get_drvdata(dev);
+ struct as3722 *as3722 = as3722_rtc->as3722;
+ u8 as_time_array[6];
+ int ret;
+
+ ret = as3722_block_read(as3722, AS3722_RTC_SECOND_REG,
+ 6, as_time_array);
+ if (ret < 0) {
+ dev_err(dev, "RTC_SECOND reg block read failed %d\n", ret);
+ return ret;
+ }
+ as3722_reg_to_time(as_time_array, tm);
+ return 0;
+}
+
+static int as3722_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct a
[PATCH V5 2/3] pincntrl: add support for ams AS3722 pin control driver
The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.
Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.
The driver will register itself as the pincontrol driver and gpio driver.
Signed-off-by: Laxman Dewangan
Acked-by: Linus Walleij
---
Changes from V1:
- Nit cleanups in driver and use module_platform_driver.
Changes from V2:
- Move the gpio driver from gpio folder to pinctnrl driver and register
driver as pincontrol driver.
- Provide pin configuration through pincntrl framework.
Changes from V3:
- Added gpio ranges and pinctrl_gpio calls.
- Used pinctrl_gpio_* calls on gpio chips callback.
- Remove dummy function which just return not supported.
- Nit cleanups.
Changes from V4:
- Drop separate DT binding document as it is moved to mfd/as3722.txt.
- Added ack from Linus.
drivers/pinctrl/Kconfig | 11 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-as3722.c | 630 ++
3 files changed, 642 insertions(+), 0 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-as3722.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 21db201..85f5462 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -59,6 +59,17 @@ config PINCTRL_ADI2
future processors. This option is selected automatically when specific
machine and arch are selected to build.
+config PINCTRL_AS3722
+ bool "Pinctrl and GPIO driver for ams AS3722 PMIC"
+ depends on MFD_AS3722 && GPIOLIB
+ select PINMUX
+ select GENERIC_PINCONF
+ help
+ AS3722 device supports the configuration of GPIO pins for different
+ functionality. This driver supports the pinmux, push-pull and
+ open drain configuration for the GPIO pins of AS3722 devices. It also
+ supports the GPIO functionality through gpiolib.
+
config PINCTRL_BF54x
def_bool y if BF54x
select PINCTRL_ADI2
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index bbeb980..3d14cb8 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
+obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
obj-$(CONFIG_PINCTRL_BF54x)+= pinctrl-adi2-bf54x.o
obj-$(CONFIG_PINCTRL_BF60x)+= pinctrl-adi2-bf60x.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
new file mode 100644
index 000..01bffc1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -0,0 +1,630 @@
+/*
+ * ams AS3722 pin control and GPIO driver.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define AS3722_PIN_GPIO0 0
+#define AS3722_PIN_GPIO1 1
+#define AS3722_PIN_GPIO2 2
+#define AS3722_PIN_GPIO3 3
+#define AS3722_PIN_GPIO4 4
+#define AS3722_PIN_GPIO5 5
+#define AS3722_PIN_GPIO6 6
+#define AS3722_PIN_GPIO7 7
+#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
+
+#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
+#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
+#define AS3722_GPIO_MODE_HIGH_IMPEDBIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
+#define AS3722_GPIO_MODE_OPEN_DRAINBIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
+
+struct as3722_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned ngroups;
+ int mux_option;
+};
+
+struct as3722_gpio_pin_control {
+ bool enable_gpio_invert;
+ unsigned mode_prop;
+ int io_function;
+};
+
+struct as3722_pingroup
[PATCH V4] clk: palmas: add clock driver for palmas
Palmas devices has two clock output CLK32K_KG and CLK32K_KG_AUDIO
which can be enable/disable through software.
Add clock driver support for the Palmas 32KHz clocks.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Call prepare if the clk is needed for boot-enable or sleep control.
- change is_enabled to is_prepared.
- Added ops palmas_clks_recalc_rate.
- Added of_clk_add_provider().
Changes from V2:
- Convert magic number to defines.
Changes from V3:
- Drop the option of clock enable at boot.
- Add the dt-binding header for DTS file and added macros for ext pin and
clock id.
- Rephrase some of sentences.
- Error check on init conifgurations.
- Code cleanups for getting rid of some of enums.
.../devicetree/bindings/clock/clk-palmas.txt | 50 +++
drivers/clk/Kconfig|7 +
drivers/clk/Makefile |1 +
drivers/clk/clk-palmas.c | 333
include/dt-bindings/mfd/palmas.h | 22 ++
5 files changed, 413 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-palmas.txt
create mode 100644 drivers/clk/clk-palmas.c
create mode 100644 include/dt-bindings/mfd/palmas.h
diff --git a/Documentation/devicetree/bindings/clock/clk-palmas.txt
b/Documentation/devicetree/bindings/clock/clk-palmas.txt
new file mode 100644
index 000..907c454
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-palmas.txt
@@ -0,0 +1,50 @@
+* Palmas 32KHz clocks *
+
+Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
+
+This binding uses the common clock binding ./clock-bindings.txt.
+
+Required properties:
+- compatible : shall be "ti,palmas-clk".
+- #clock-cells : from common clock binding; shall be set to 1. The clock id for
+ different clocks are:
+ 0 for CLK32K_KG
+ 1 for CLK32K_KG_AUDIO.
+ The macros of clocks id for DTS is defined at
+ dt-bindings/mfd/palmas.h
+
+Optional subnode:
+ The clock node has optional subnode to provide the init configuration of
+ clocks like sleep control.
+
+ The subnode name is fixed and it should be
+ clk32k_kg for the 32KHz KG clock.
+ clk32k_kg_audio for the 32KHz KG_AUDIO clock.
+
+ Optional subnode properties:
+ ti,external-sleep-control: The external enable input pins controlled the
+ enable/disable of clocks. The external enable input pins
ENABLE1,
+ ENABLE2 and NSLEEP. The valid values for the external pins are:
+ 1 for ENABLE1
+ 2 for ENABLE2
+ 3 for NSLEEP.
+ Option 0 or missing this property means the clock is
+ enabled/disabled via register access and these pins do
+ not have any control.
+ The macros of external control pins for DTS is defined at
+ dt-bindings/mfd/palmas.h
+
+Example:
+ #include
+ ...
+ palmas: tps65913@58 {
+ ...
+ clock {
+ compatible = "ti,palmas-clk";
+ #clock-cells = <1>;
+ clk32k_kg {
+ ti,external-sleep-control =
;
+ };
+ };
+ ...
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 279407a..6b8c233 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -93,6 +93,13 @@ config CLK_PPC_CORENET
This adds the clock driver support for Freescale PowerPC corenet
platforms using common clock framework.
+config COMMON_CLK_PALMAS
+ tristate "Clock driver for TI Palmas devices"
+ depends on MFD_PALMAS
+ ---help---
+ This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
+ using common clock framework.
+
endmenu
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..32e04cf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
new file mode 100644
index 000..e6e56d1
--- /dev/null
+++ b/drivers/clk/clk-palmas.c
@@ -0,0 +1,333 @@
+/*
+ * Clock driver for Palmas device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software
Re: [PATCH V3] clk: palmas: add clock driver for palmas
On Tuesday 08 October 2013 08:58 PM, Mark Rutland wrote: On Tue, Oct 08, 2013 at 03:39:54PM +0100, Laxman Dewangan wrote: + + Optional subnode properties: + ti,clock-boot-enable: Enable clock at the time of booting. Dumb question: Why is this needed? should'nt relevant drivers do a clk_get to enable the relevant clocks? If some board needs this clock to be always available for rest of system to work without any specific driver then this flag is useful. Do we _actually_ need this right now, or is this hypothetical? If we don't need it now, remove it. If you think we need it know, please describe exactly why (i.e. what device needs the clock to work, why does this affect the rest of the board if we don't ahve a driver for that device, why don't we just write a driver for that device). Ok, I will remove it. Going with nothing free of cost for the driver/system and client need to call the proper APIs. + ti,external-sleep-control: The clock is enable/disabled by state + of external enable input pins ENABLE, ENABLE2 and NSLEEP. + The valid value for the external pins are: + 1 for ENABLE1 + 2 for ENABLE2 + 3 for NSLEEP. I asked this on the last version (before having noticed this one). What actually drives those pins to control the clock(s)? Is this for setting the clock to be controlled by the external pin, or is the clock hard-wired to a particular pin? This is for setting the clock to be controlled by the external pin. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3] clk: palmas: add clock driver for palmas
Thanks Nishanth for review.
On Tuesday 08 October 2013 06:59 PM, Nishanth Menon wrote:
On 10/08/2013 08:21 AM, Laxman Dewangan wrote:
Palmas devices has two clock output CLK32K_KG and CLK32K_KG_AUDIO
not all palmas devices have 2 clocks - example: tps659038
This is for generic palmas and I have seen it for TPS65913, TPS65914,
TPS80036. If the generic one is not compatible then it need to add
device specific and at that time, it is require to update the binding
document accordingly.
|7 +
drivers/clk/Makefile |1 +
drivers/clk/clk-palmas.c | 340
http://www.spinics.net/lists/devicetree/msg04855.html
Do we do 2 patches now? one seperate for binding and implementation?
What is our current preference now a days?
Currently it is implementation + binding doc in one patch.
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
+
+This binding uses the common clock binding ./clock-bindings.txt.
proper link would be to provide
Documentation/devicetree/bindings/clock/clock-bindings.txt ?
Hmm, other patch I got feedback from DT maintainers to do not use the
absolute path as document directory may change
+
+Clock 32KHz KG is output 0 of the driver and clock 32KHz is output 1.
+
+Required properties:
+- compatible : shall be "ti,palmas-clk".
To handle variants of Palmas chips in production, you'd want to be
specific here clk32k_kg and clk32k_kg_audio.
The compatible is the device sub module level, not the clock level. Same
thing we are following on regulators.
+
+ Optional subnode properties:
+ ti,clock-boot-enable: Enable clock at the time of booting.
Dumb question: Why is this needed? should'nt relevant drivers do a
clk_get to enable the relevant clocks?
If some board needs this clock to be always available for rest of system
to work without any specific driver then this flag is useful.
+ ti,external-sleep-control: The clock is enable/disabled by state
+ of external enable input pins ENABLE, ENABLE2 and NSLEEP.
+ The valid value for the external pins are:
+ 1 for ENABLE1
+ 2 for ENABLE2
+ 3 for NSLEEP.
could we not have macros for readability?
I am thinking of adding the palmas for dt-binding and then change on
multiple places. I will post patches for this.
the patch will go on dt tree as include/dt-bindings and then on
documents file and then on actually DTS. I will work towards this but
scoping out of this patch.
+
+
+enum PALMAS_CLOCK32K {
+ PALMAS_CLOCK32KG,
+ PALMAS_CLOCK32KG_AUDIO,
+
+ /* Last entry */
+ PALMAS_CLOCK32K_NR,
+};
you should be able to get rid of this entirely
Probably yes but it is easy to read (atleast for me).
+ cinfo->clk = clk;
+ palmas_clks->clk_data.clks[i] = clk;
+ palmas_clks->clk_data.clk_num++;
+ palmas_clks_init_configure(cinfo);
we dont handle error here?
Intentionally I ignore error, just print and continue the registration.
+
+MODULE_AUTHOR("Laxman Dewangan ");
+MODULE_LICENSE("GPL v2");
I wonder if we can simplify this with CLK_OF_DECLARE - I suppose it
wont work if of_clk_init(NULL); was invoked previously.
This driver has dependency over the mfd driver and hence until mfd
driver invoked and get registered, this driver should not be called. The
platform driver registration is done in mfd.
As per my understanding and referring the other code, CLK_OF_DECLARE is
useful if there is no such dependency. Please correct me if this is not
true.
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[PATCH V3] clk: palmas: add clock driver for palmas
Palmas devices has two clock output CLK32K_KG and CLK32K_KG_AUDIO
which can be enable/disable through software.
Add clock driver support for the Palmas 32KHz clocks.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Call prepare if the clk is needed for boot-enable or sleep control.
- change is_enabled to is_prepared.
- Added ops palmas_clks_recalc_rate.
- Added of_clk_add_provider().
Changes from V2:
- Convert magic number to defines.
.../devicetree/bindings/clock/clk-palmas.txt | 45 +++
drivers/clk/Kconfig|7 +
drivers/clk/Makefile |1 +
drivers/clk/clk-palmas.c | 340
4 files changed, 393 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-palmas.txt
create mode 100644 drivers/clk/clk-palmas.c
diff --git a/Documentation/devicetree/bindings/clock/clk-palmas.txt
b/Documentation/devicetree/bindings/clock/clk-palmas.txt
new file mode 100644
index 000..c247538
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-palmas.txt
@@ -0,0 +1,45 @@
+* Palmas 32KHz clocks *
+
+Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
+
+This binding uses the common clock binding ./clock-bindings.txt.
+
+Clock 32KHz KG is output 0 of the driver and clock 32KHz is output 1.
+
+Required properties:
+- compatible : shall be "ti,palmas-clk".
+- #clock-cells : from common clock binding; shall be set to 1.
+
+Optional subnode:
+ The clock node has optional subnode to provide the init configuration of
+ clocks like boot enable, sleep control.
+
+ The subnode name is fixed and it should be
+ clk32k_kg for the 32KHz KG clock.
+ clk32k_kg_audio for the 32KHz KG_AUDIO clock.
+
+ Optional subnode properties:
+ ti,clock-boot-enable: Enable clock at the time of booting.
+ ti,external-sleep-control: The clock is enable/disabled by state
+ of external enable input pins ENABLE, ENABLE2 and NSLEEP.
+ The valid value for the external pins are:
+ 1 for ENABLE1
+ 2 for ENABLE2
+ 3 for NSLEEP.
+ Option 0 or missing this property means the clock is
+ enabled/disabled via register access and these pins do
+ not have any control.
+
+Example:
+ clock {
+ compatible = "ti,palmas-clk";
+ #clock-cells = <1>;
+ clk32k_kg {
+ ti,clock-boot-enable;
+ ti,external-sleep-control = <3>;
+ };
+
+ clk32k_kg_audio {
+ ti,clock-boot-enable;
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 279407a..6b8c233 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -93,6 +93,13 @@ config CLK_PPC_CORENET
This adds the clock driver support for Freescale PowerPC corenet
platforms using common clock framework.
+config COMMON_CLK_PALMAS
+ tristate "Clock driver for TI Palmas devices"
+ depends on MFD_PALMAS
+ ---help---
+ This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
+ using common clock framework.
+
endmenu
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..32e04cf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
new file mode 100644
index 000..3e070b2
--- /dev/null
+++ b/drivers/clk/clk-palmas.c
@@ -0,0 +1,340 @@
+/*
+ * Clock driver for Palmas device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum PALMAS_CLOCK
Re: [PATCH V2] clk: palmas: add clock driver for palmas
On Tuesday 08 October 2013 06:32 AM, Mike Turquette wrote:
Quoting Laxman Dewangan (2013-10-07 07:05:51)
+ if (!ret) {
+ switch (prop) {
+ case 1:
+ prop = PALMAS_EXT_CONTROL_ENABLE1;
+ break;
+ case 2:
+ prop = PALMAS_EXT_CONTROL_ENABLE2;
+ break;
+ case 3:
+ prop = PALMAS_EXT_CONTROL_NSLEEP;
+ break;
Can magic numbers be replaced with defines?
Fine, will do in V3.
+
+ ret = palmas_update_bits(palmas_clks->palmas, PALMAS_RESOURCE_BASE,
+ cinfo->clk_desc->control_reg,
+ cinfo->clk_desc->sleep_mask, 0);
What does this call to palmas_update_bits do?
This APIs update the selected bits based on mask. This is wrapper over
the regmap_update_bits() to provide the interface at the Palmas register
access.
The palmas registers are paged on different i2c address and offset. The
i2c address and offset is decided based on base_address and offset.
This APIs does all calculation to get the correct i2c slave address and
offset address based on argument.
+static int palmas_clks_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
I'll be taking Sylwester's clock deregistration series after he
publishes the next version, so if you want to call clk_unregister here
(based on the new call) you could.
If you want to add that in a later patch it is OK.
Thanks for pointing me this changes. I like to add this on my follow on
(later) patch, not on this. -- 1.7.1.1
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Re: [PATCH V2] clk: palmas: add clock driver for palmas
On Monday 07 October 2013 07:35 PM, Laxman Dewangan wrote: --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,3 +43,5 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o +obj-y += clk-test.o Sorry, silly mistake, the line +obj-y += clk-test.o is not require. This was done for testing only. I will respin the patch but wait for some more feedback if any to add on next version. Thanks, Laxman -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2] clk: palmas: add clock driver for palmas
Palmas devices has two clock output CLK32K_KG and CLK32K_KG_AUDIO
which can be nebale/disable through software.
Add clock driver support for the Palmas 32k clocks.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Call prepare if the clk is needed for boot-enable or sleep control.
- change is_enabled to is_prepared.
- Added ops palmas_clks_recalc_rate.
- Added of_clk_add_provider().
.../devicetree/bindings/clock/clk-palmas.txt | 45 +++
drivers/clk/Kconfig|7 +
drivers/clk/Makefile |2 +
drivers/clk/clk-palmas.c | 336
4 files changed, 390 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-palmas.txt
create mode 100644 drivers/clk/clk-palmas.c
diff --git a/Documentation/devicetree/bindings/clock/clk-palmas.txt
b/Documentation/devicetree/bindings/clock/clk-palmas.txt
new file mode 100644
index 000..c247538
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-palmas.txt
@@ -0,0 +1,45 @@
+* Palmas 32KHz clocks *
+
+Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
+
+This binding uses the common clock binding ./clock-bindings.txt.
+
+Clock 32KHz KG is output 0 of the driver and clock 32KHz is output 1.
+
+Required properties:
+- compatible : shall be "ti,palmas-clk".
+- #clock-cells : from common clock binding; shall be set to 1.
+
+Optional subnode:
+ The clock node has optional subnode to provide the init configuration of
+ clocks like boot enable, sleep control.
+
+ The subnode name is fixed and it should be
+ clk32k_kg for the 32KHz KG clock.
+ clk32k_kg_audio for the 32KHz KG_AUDIO clock.
+
+ Optional subnode properties:
+ ti,clock-boot-enable: Enable clock at the time of booting.
+ ti,external-sleep-control: The clock is enable/disabled by state
+ of external enable input pins ENABLE, ENABLE2 and NSLEEP.
+ The valid value for the external pins are:
+ 1 for ENABLE1
+ 2 for ENABLE2
+ 3 for NSLEEP.
+ Option 0 or missing this property means the clock is
+ enabled/disabled via register access and these pins do
+ not have any control.
+
+Example:
+ clock {
+ compatible = "ti,palmas-clk";
+ #clock-cells = <1>;
+ clk32k_kg {
+ ti,clock-boot-enable;
+ ti,external-sleep-control = <3>;
+ };
+
+ clk32k_kg_audio {
+ ti,clock-boot-enable;
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 279407a..6b8c233 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -93,6 +93,13 @@ config CLK_PPC_CORENET
This adds the clock driver support for Freescale PowerPC corenet
platforms using common clock framework.
+config COMMON_CLK_PALMAS
+ tristate "Clock driver for TI Palmas devices"
+ depends on MFD_PALMAS
+ ---help---
+ This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
+ using common clock framework.
+
endmenu
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..f168ff7 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,3 +43,5 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
+obj-y += clk-test.o
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
new file mode 100644
index 000..804c76e
--- /dev/null
+++ b/drivers/clk/clk-palmas.c
@@ -0,0 +1,336 @@
+/*
+ * Clock driver for Palmas device.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum PALMAS_CLOCK32K {
+ PALMAS_CLOC
