[PATCH v5 net-next 3/3] dt-bindings: net: macb: Add NP4 macb variant
Add NP4 macb SoC variant.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/net/macb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index 38c8e84..5c397ca 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be "cdns,[-]{macb|gem}"
Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
available on sama5d3 SoCs.
+ Use "cdns,np4-macb" for NP4 SoC devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
"cdns,macb".
Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
the Cadence GEM, or the generic form: "cdns,gem".
--
1.9.1
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[PATCH v5 net-next 1/3] net: ethernet: cadence-macb: Add disabled usrio caps
On some platforms, the macb integration does not use the USRIO
register to configure the (R)MII port and clocks.
When the register is not implemented and the MACB error signal
is connected to the bus error, reading or writing to the USRIO
register can trigger some Imprecise External Aborts on ARM platforms.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index 8b45bc9..fa53bc3 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2124,7 +2124,8 @@ static void macb_get_regs(struct net_device *dev, struct
ethtool_regs *regs,
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
- regs_buff[12] = macb_or_gem_readl(bp, USRIO);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
+ regs_buff[12] = macb_or_gem_readl(bp, USRIO);
if (macb_is_gem(bp)) {
regs_buff[13] = gem_readl(bp, DMACFG);
}
@@ -2403,19 +2404,21 @@ static int macb_init(struct platform_device *pdev)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
- val = 0;
- if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
- val = GEM_BIT(RGMII);
- else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
-(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(RMII);
- else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(MII);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
+ val = 0;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ val = GEM_BIT(RGMII);
+ else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
+(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(RMII);
+ else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(MII);
- if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
- val |= MACB_BIT(CLKEN);
+ if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+ val |= MACB_BIT(CLKEN);
- macb_or_gem_writel(bp, USRIO, val);
+ macb_or_gem_writel(bp, USRIO, val);
+ }
/* Set MII management clock divider */
val = macb_mdc_clk_div(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h
b/drivers/net/ethernet/cadence/macb.h
index 5c03e81..0d4ecfc 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -400,6 +400,7 @@
#define MACB_CAPS_USRIO_HAS_CLKEN 0x0002
#define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x0004
#define MACB_CAPS_NO_GIGABIT_HALF 0x0008
+#define MACB_CAPS_USRIO_DISABLED 0x0010
#define MACB_CAPS_FIFO_MODE0x1000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000
#define MACB_CAPS_SG_DISABLED 0x4000
--
1.9.1
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[PATCH v5 net-next 2/3] net: macb: Add NP4 macb config using USRIO_DISABLED
Declare a new NP4 SoC variant having USRIO_DISABLED as capability bit.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index fa53bc3..d12ee07 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2781,6 +2781,11 @@ static const struct macb_config emac_config = {
.init = at91ether_init,
};
+static const struct macb_config np4_config = {
+ .caps = MACB_CAPS_USRIO_DISABLED,
+ .clk_init = macb_clk_init,
+ .init = macb_init,
+};
static const struct macb_config zynqmp_config = {
.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
@@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
{ .compatible = "cdns,macb" },
+ { .compatible = "cdns,np4-macb", .data = &np4_config },
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
{ .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
--
1.9.1
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[PATCH v5 net-next 0/3] Add new capability and macb DT variant
The first patch introduces a new capability bit to disable usage of the USRIO register on platform not implementing it thus avoiding some external imprecise aborts on ARM based platforms. The two last patchs adds a new macb variant compatible name using the capability, the NP4 SoC uses this particular hardware configuration. v1: http://lkml.kernel.org/r/1449485914-12883-1-git-send-email-narmstr...@baylibre.com v2: http://lkml.kernel.org/r/1449582726-6148-1-git-send-email-narmstr...@baylibre.com v3: http://lkml.kernel.org/r/1451898103-21868-1-git-send-email-narmstr...@baylibre.com v4: http://lkml.kernel.org/r/1451900573-22657-1-git-send-email-narmstr...@baylibre.com v5: switch SoC name to non-generic NP4 name Neil Armstrong (3): net: ethernet: cadence-macb: Add disabled usrio caps net: macb: Add NP4 macb config using USRIO_DISABLED dt-bindings: net: macb: Add NP4 macb variant Documentation/devicetree/bindings/net/macb.txt | 1 + drivers/net/ethernet/cadence/macb.c| 33 -- drivers/net/ethernet/cadence/macb.h| 1 + 3 files changed, 23 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 net-next 2/3] net: macb: Add NPx macb config using USRIO_DISABLED cap
On 01/04/2016 11:38 AM, Nicolas Ferre wrote:
> Le 04/01/2016 10:42, Neil Armstrong a écrit :
>> static const struct macb_config zynqmp_config = {
>> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
>> @@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
>> { .compatible = "cdns,at32ap7000-macb" },
>> { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
>> { .compatible = "cdns,macb" },
>> +{ .compatible = "cdns,npx-macb", .data = &npx_config },
>
> I can accept that, but I think that you'd better make your device tree
> compatibility string *not* generic. Name it by the first NPx SoC or
> perfectly compatible SoC family that has this configuration and you'll
> be able to make the NP(x+1) compatible with it.
Well, the first Soc having this configuration is Np4, would cdns,np4-macb be ok
?
>
> It has proven to be much more future proof and even if in the early days
> of DT on ARM we accepted some binding with generic strings like this one
> below, It has proven to be a mistake.
>
>> { .compatible = "cdns,gem", .data = &pc302gem_config },
>> { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
>>
>
>
Neil
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[PATCH v4 net-next 0/3] Add new capability and macb DT variant
The first patch introduces a new capability bit to disable usage of the USRIO register on platform not implementing it thus avoiding some external imprecise aborts on ARM based platforms. The two last patchs adds a new macb variant compatible name using the capability, the NPx name is temporary and must be fixed when the first patch hits mainline. Only the first patch should be merged right now until the compatible name is fixed. v1: http://lkml.kernel.org/r/1449485914-12883-1-git-send-email-narmstr...@baylibre.com v2: http://lkml.kernel.org/r/1449582726-6148-1-git-send-email-narmstr...@baylibre.com v3: http://lkml.kernel.org/r/1451898103-21868-1-git-send-email-narmstr...@baylibre.com v4: as nicolas suggested, use a new macb config and a new product/vendor prefix Neil Armstrong (3): net: ethernet: cadence-macb: Add disabled usrio caps net: macb: Add NPx macb config using USRIO_DISABLED cap dt-bindings: net: macb: Add NPx macb variant Documentation/devicetree/bindings/net/macb.txt | 1 + drivers/net/ethernet/cadence/macb.c| 33 -- drivers/net/ethernet/cadence/macb.h| 1 + 3 files changed, 23 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 net-next 1/3] net: ethernet: cadence-macb: Add disabled usrio caps
On some platforms, the macb integration does not use the USRIO
register to configure the (R)MII port and clocks.
When the register is not implemented and the MACB error signal
is connected to the bus error, reading or writing to the USRIO
register can trigger some Imprecise External Aborts on ARM platforms.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index 8b45bc9..fa53bc3 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2124,7 +2124,8 @@ static void macb_get_regs(struct net_device *dev, struct
ethtool_regs *regs,
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
- regs_buff[12] = macb_or_gem_readl(bp, USRIO);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
+ regs_buff[12] = macb_or_gem_readl(bp, USRIO);
if (macb_is_gem(bp)) {
regs_buff[13] = gem_readl(bp, DMACFG);
}
@@ -2403,19 +2404,21 @@ static int macb_init(struct platform_device *pdev)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
- val = 0;
- if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
- val = GEM_BIT(RGMII);
- else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
-(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(RMII);
- else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(MII);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
+ val = 0;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ val = GEM_BIT(RGMII);
+ else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
+(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(RMII);
+ else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(MII);
- if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
- val |= MACB_BIT(CLKEN);
+ if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+ val |= MACB_BIT(CLKEN);
- macb_or_gem_writel(bp, USRIO, val);
+ macb_or_gem_writel(bp, USRIO, val);
+ }
/* Set MII management clock divider */
val = macb_mdc_clk_div(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h
b/drivers/net/ethernet/cadence/macb.h
index 5c03e81..0d4ecfc 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -400,6 +400,7 @@
#define MACB_CAPS_USRIO_HAS_CLKEN 0x0002
#define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x0004
#define MACB_CAPS_NO_GIGABIT_HALF 0x0008
+#define MACB_CAPS_USRIO_DISABLED 0x0010
#define MACB_CAPS_FIFO_MODE0x1000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000
#define MACB_CAPS_SG_DISABLED 0x4000
--
1.9.1
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[PATCH v4 net-next 2/3] net: macb: Add NPx macb config using USRIO_DISABLED cap
Declare a new SoC variant for NPx SoCs having USRIO_DISABLED as
capability bit.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index fa53bc3..a9e27a7 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2781,6 +2781,11 @@ static const struct macb_config emac_config = {
.init = at91ether_init,
};
+static const struct macb_config npx_config = {
+ .caps = MACB_CAPS_USRIO_DISABLED,
+ .clk_init = macb_clk_init,
+ .init = macb_init,
+};
static const struct macb_config zynqmp_config = {
.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
@@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
{ .compatible = "cdns,macb" },
+ { .compatible = "cdns,npx-macb", .data = &npx_config },
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
{ .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
--
1.9.1
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[PATCH v4 net-next 3/3] dt-bindings: net: macb: Add NPx macb variant
Add NPx macb variant for NPx SoCs.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/net/macb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index 38c8e84..638cdde 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be "cdns,[-]{macb|gem}"
Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
available on sama5d3 SoCs.
+ Use "cdns,npx-macb" for NPX SoCs devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
"cdns,macb".
Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
the Cadence GEM, or the generic form: "cdns,gem".
--
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[PATCH 1/2] memory: omap-gpmc: Add support for AAD timings
In order to support extended timings parameters on hardware supporting the
"AAD" mode like the AM335x or DM816x, add these entries into the GPMC driver
if the hardware is capable.
Tested on DM816x and AM335x.
Signed-off-by: Neil Armstrong
---
drivers/memory/omap-gpmc.c | 30 ++
include/linux/omap-gpmc.h | 5 +
2 files changed, 35 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 6515dfc..21825dd 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -541,9 +541,20 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
+ if (gpmc_capability & GPMC_HAS_MUX_AAD) {
+ GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
+ GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
+ "adv-aad-mux-rd-off-ns");
+ GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
+ "adv-aad-mux-wr-off-ns");
+ }
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
+ if (gpmc_capability & GPMC_HAS_MUX_AAD) {
+ GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
+ GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
+ }
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
@@ -734,9 +745,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings
*t,
GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
+ if (gpmc_capability & GPMC_HAS_MUX_AAD) {
+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
+ }
GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
+ if (gpmc_capability & GPMC_HAS_MUX_AAD) {
+ GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
+ GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
+ }
GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
@@ -1722,6 +1742,12 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
+ of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
+&gpmc_t->adv_aad_mux_on);
+ of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
+&gpmc_t->adv_aad_mux_rd_off);
+ of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
+&gpmc_t->adv_aad_mux_wr_off);
/* WE signal timings */
of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
@@ -1730,6 +1756,10 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
/* OE signal timings */
of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
+ of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
+&gpmc_t->oe_aad_mux_on);
+ of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
+&gpmc_t->oe_aad_mux_off);
/* access and cycle timings */
of_property_read_u32(np, "gpmc,page-burst-access-ns",
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 7dee0014..d833eb4 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -51,6 +51,9 @@ struct gpmc_timings {
u32 adv_on; /* Assertion time */
u32 adv_rd_off; /* Read deassertion time */
u32 adv_wr_off; /* Write deassertion time */
+ u32 adv_aad_mux_on; /* ADV assertion time for AAD */
+ u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
+ u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
/* WE signals timings corresponding to GPMC_CONFIG4 */
[PATCH 2/2] dt-bindings: bus: ti-gpmc: Add AAD timings properties
In order to support advanced AAD timings, add these properties to the DT GPMC bindings. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/bus/ti-gpmc.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt index 704be93..0168370 100644 --- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt +++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -46,6 +46,9 @@ Timing properties for child nodes. All are optional and default to 0. - gpmc,adv-on-ns: Assertion time - gpmc,adv-rd-off-ns: Read deassertion time - gpmc,adv-wr-off-ns: Write deassertion time + - gpmc,adv-aad-mux-on-ns: Assertion time for AAD + - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD + - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - gpmc,we-on-ns Assertion time @@ -54,6 +57,8 @@ Timing properties for child nodes. All are optional and default to 0. OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - gpmc,oe-on-ns: Assertion time - gpmc,oe-off-ns: Deassertion time + - gpmc,oe-aad-mux-on-ns: Assertion time for AAD + - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] ti-gpmc: Add support for AAD timings
This serie add support for the GPMC Advanced AAD timings on hardware supporting the feature like the AM335x and DM816X. Neil Armstrong (2): memory: omap-gpmc: Add support for AAD timings dt-bindings: bus: ti-gpmc: Add AAD timings properties Documentation/devicetree/bindings/bus/ti-gpmc.txt | 5 drivers/memory/omap-gpmc.c| 30 +++ include/linux/omap-gpmc.h | 5 3 files changed, 40 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 net-next 0/3] Add new capability and parse from DT
The first patch introduces a new capability bit to disable usage of the USRIO register on platform not implementing it thus avoiding some external imprecise aborts on ARM based platforms. The two last patchs implements a DT fallback to get the software defined capabilities from DT in the case of the generic compatible form is used. These properties will permit support of future implementations of macb/gem without the need for adding new static structures in the code. v1: http://lkml.kernel.org/r/1449485914-12883-1-git-send-email-narmstr...@baylibre.com v2: switch to CAPS_* bit and add all software CAPS_* as DT properties Neil Armstrong (3): net: ethernet: cadence-macb: Add disabled usrio caps net: ethernet: cadence-macb: Add fallback to read DT provided caps bindings: ethernet: macb: Add optional caps properties Documentation/devicetree/bindings/net/macb.txt | 10 drivers/net/ethernet/cadence/macb.c| 72 +- drivers/net/ethernet/cadence/macb.h| 1 + 3 files changed, 71 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 net-next 1/3] net: ethernet: cadence-macb: Add disabled usrio caps
On some platforms, the macb integration does not use the USRIO
register to configure the (R)MII port and clocks.
When the register is not implemented and the MACB error signal
is connected to the bus error, reading or writing to the USRIO
register can trigger some Imprecise External Aborts on ARM platforms.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index 169059c..9325140 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2122,7 +2122,8 @@ static void macb_get_regs(struct net_device *dev, struct
ethtool_regs *regs,
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
- regs_buff[12] = macb_or_gem_readl(bp, USRIO);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
+ regs_buff[12] = macb_or_gem_readl(bp, USRIO);
if (macb_is_gem(bp)) {
regs_buff[13] = gem_readl(bp, DMACFG);
}
@@ -2401,19 +2402,21 @@ static int macb_init(struct platform_device *pdev)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
- val = 0;
- if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
- val = GEM_BIT(RGMII);
- else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
-(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(RMII);
- else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(MII);
+ if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
+ val = 0;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ val = GEM_BIT(RGMII);
+ else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
+(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(RMII);
+ else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(MII);
- if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
- val |= MACB_BIT(CLKEN);
+ if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+ val |= MACB_BIT(CLKEN);
- macb_or_gem_writel(bp, USRIO, val);
+ macb_or_gem_writel(bp, USRIO, val);
+ }
/* Set MII management clock divider */
val = macb_mdc_clk_div(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h
b/drivers/net/ethernet/cadence/macb.h
index d83b0db..65ea049 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -400,6 +400,7 @@
#define MACB_CAPS_USRIO_HAS_CLKEN 0x0002
#define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x0004
#define MACB_CAPS_NO_GIGABIT_HALF 0x0008
+#define MACB_CAPS_USRIO_DISABLED 0x0010
#define MACB_CAPS_FIFO_MODE0x1000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000
#define MACB_CAPS_SG_DISABLED 0x4000
--
1.9.1
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[PATCH v2 net-next 2/3] net: ethernet: cadence-macb: Add fallback to read DT provided caps
Add 1:1 mapping of software defines caps parsing from DT in case the
generic macb compatible form is used.
These properties will provide support for futures implementations
only defined from DT without need to update the driver code to support
new variants.
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/cadence/macb.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index 9325140..28a9a8b 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2795,6 +2795,48 @@ static const struct macb_config zynq_config = {
.init = macb_init,
};
+static const struct macb_config *macb_parse_dt_caps(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct macb_config *macb_config;
+ u32 val;
+
+ macb_config = devm_kzalloc(dev, sizeof(*macb_config), GFP_KERNEL);
+ if (!macb_config)
+ return NULL;
+
+ if (of_property_read_bool(np, "cdns,usrio-has-clken"))
+ macb_config->caps |= MACB_CAPS_USRIO_HAS_CLKEN;
+
+ if (of_property_read_bool(np, "cdns,usrio-default-mii"))
+ macb_config->caps |= MACB_CAPS_USRIO_DEFAULT_IS_MII;
+
+ if (of_property_read_bool(np, "cdns,no-gigabit-half"))
+ macb_config->caps |= MACB_CAPS_NO_GIGABIT_HALF;
+
+ if (of_property_read_bool(np, "cdns,usrio-disabled"))
+ macb_config->caps |= MACB_CAPS_USRIO_DISABLED;
+
+ if (of_property_read_bool(np, "cdns,gem-sg-disabled"))
+ macb_config->caps |= MACB_CAPS_SG_DISABLED;
+
+ if (of_property_read_bool(np, "cdns,gem-has-gigabit"))
+ macb_config->caps |= MACB_CAPS_GIGABIT_MODE_AVAILABLE;
+
+ if (of_property_read_bool(np, "cdns,usrio-disabled"))
+ macb_config->caps |= MACB_CAPS_USRIO_DISABLED;
+
+ if (!of_property_read_u32(np, "cdns,dma-burst-length", &val))
+ macb_config->dma_burst_length = val;
+
+ if (!of_property_read_u32(np, "cdns,jumbo-max-length", &val)) {
+ macb_config->jumbo_max_len = val;
+ macb_config->caps |= MACB_CAPS_JUMBO;
+ }
+
+ return macb_config;
+}
+
static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
@@ -2847,6 +2889,9 @@ static int macb_probe(struct platform_device *pdev)
clk_init = macb_config->clk_init;
init = macb_config->init;
}
+
+ if (!macb_config)
+ macb_config = macb_parse_dt_caps(&pdev->dev);
}
err = clk_init(pdev, &pclk, &hclk, &tx_clk);
--
1.9.1
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[PATCH v2 net-next 3/3] bindings: ethernet: macb: Add optional caps properties
Add generic caps properties to the binding in order to support
future macb/gem implementations with the generic macb compatible form.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/net/macb.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index b5d7976..891c72e 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -19,6 +19,16 @@ Required properties:
Optional elements: 'tx_clk'
- clocks: Phandles to input clocks.
+Optional properties:
+- cdns,usrio-has-clken: Boolean; The USRIO register has an clock-enable bit.
+- cdns,usrio-default-mii: Boolean; The USRIO register defaults to MII mode.
+- cdns,usrio-disabled: Boolean; The USRIO register is not implemented.
+- cdns,no-gigabit-half: Boolean; The MAC does not support 1000/Half link mode.
+- cdns,gem-sg-disabled: Boolean; The MAC does not support Scatter-Gather mode.
+- cdns,gem-has-gigabit: Boolean; The MAC supports Gigabit Ethernet.
+- cdns,dma-burst-length: Should countain the DMA burst length.
+- cdns,jumbo-max-length: Should countain the maximum Jumbo frame length.
+
Examples:
macb0: ethernet@fffc4000 {
--
1.9.1
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Re: [PATCH net 1/2] net: cadence: macb: Disable USRIO register on some platforms
Hi Josh, 2015-12-07 20:32 GMT+01:00 Josh Cartwright : > On Mon, Dec 07, 2015 at 11:58:33AM +0100, Neil Armstrong wrote: >> On some platforms, the macb integration does not use the USRIO >> register to configure the (R)MII port and clocks. >> When the register is not implemented and the MACB error signal >> is connected to the bus error, reading or writing to the USRIO >> register can trigger some Imprecise External Aborts on ARM platforms. >> --- > > Does this make sense to even be a separate bool device tree property? > > This sort of configuration is typically done by: >1. Creating a new 'caps' bit; relevant codepaths check that bit >2. Creating a new "compatible" string for your platform's macb > instance >3. Creating a new 'struct macb_config' instance for your platform, > setting any relevant caps bits when it is selected. > > Josh I see the point, but according to the User Guide : >User I/O Register > The MACB design provides up to 16 inputs and 16 outputs, > for which the state of the I/O may > be read or set under the control of the processor interface. > If the user I/O is disabled as a configuration option, this address space is > defined > as reserved, and hence will be a read-only register of value 0x0. On the design I worked on, the macb_user_* signals were commented, thus disabling this register. The implementation is not mandatory, and the "generic" macb compatible "cdns,macb" should disable usage of USRIO register by default and be only used for platform specific macb instances... Is it OK if I add a new 'caps' bit and use it for the "generic" macb instance ? For the device tree property, it should be safe to have the generic instances of macb and gem to rely on these properties instead of hardcoded instances. (it's the biggest aim of device tree, no ? no more hardcoded 'caps' bit ?) The "no-usrio" and other should eventually map 'caps' bits along the generic instances. Neil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH net 1/2] net: cadence: macb: Disable USRIO register on some platforms
On some platforms, the macb integration does not use the USRIO
register to configure the (R)MII port and clocks.
When the register is not implemented and the MACB error signal
is connected to the bus error, reading or writing to the USRIO
register can trigger some Imprecise External Aborts on ARM platforms.
---
drivers/net/ethernet/cadence/macb.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index 169059c..3897620 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2122,7 +2122,9 @@ static void macb_get_regs(struct net_device *dev, struct
ethtool_regs *regs,
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
- regs_buff[12] = macb_or_gem_readl(bp, USRIO);
+ if (!of_property_read_bool(bp->pdev->dev.of_node, "no-usrio")) {
+ regs_buff[12] = macb_or_gem_readl(bp, USRIO);
+ }
if (macb_is_gem(bp)) {
regs_buff[13] = gem_readl(bp, DMACFG);
}
@@ -2401,19 +2403,22 @@ static int macb_init(struct platform_device *pdev)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
- val = 0;
- if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
- val = GEM_BIT(RGMII);
- else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
-(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(RMII);
- else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
- val = MACB_BIT(MII);
+ /* Some platform do not implement the USRIO register */
+ if (!of_property_read_bool(pdev->dev.of_node, "no-usrio")) {
+ val = 0;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ val = GEM_BIT(RGMII);
+ else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
+(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(RMII);
+ else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
+ val = MACB_BIT(MII);
- if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
- val |= MACB_BIT(CLKEN);
+ if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+ val |= MACB_BIT(CLKEN);
- macb_or_gem_writel(bp, USRIO, val);
+ macb_or_gem_writel(bp, USRIO, val);
+ }
/* Set MII management clock divider */
val = macb_mdc_clk_div(bp);
--
1.9.1
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[PATCH net 2/2] bindings: net: macb: add no-usrio optional property
Add the no-usrio optional property to disable usage of the USRIO
register on platforms not implementing it.
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index b5d7976..a15ee54 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -19,6 +19,9 @@ Required properties:
Optional elements: 'tx_clk'
- clocks: Phandles to input clocks.
+Optional properties:
+- no-usrio: Indicates the platform integration does not implement the USRIO
register.
+
Examples:
macb0: ethernet@fffc4000 {
--
1.9.1
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[PATCH net 0/2] Add a property to disable MACB USRIO register
This patchet introduces an optional DT property to disable usage of the USRIO register on platform not implementing it thus avaiding some external impresise aborts of ARM based platforms. Neil Armstrong (2): net: cadence: macb: Disable USRIO register on some platforms bindings: net: macb: add no-usrio optional property Documentation/devicetree/bindings/net/macb.txt | 3 +++ drivers/net/ethernet/cadence/macb.c| 29 +++--- 2 files changed, 20 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/5] arm: dts: complete dm816x device tree
On 11/12/2015 06:47 PM, Tony Lindgren wrote: > * Neil Armstrong [151112 06:08]: >> In order to fix support for the dm816x platform, add missing bits in >> the dm816x dtsi and cleanup OCP. > > Which ones are needed as fixes for the v4.4-rc kernel? > > Regards, > > Tony > >> The last patch adds support for the omap4-hwspinlock. >> >> v2: add ocp hwmod cleanup >> >> Neil Armstrong (5): >> arm: dts: add dm816x missing #mbox-cells >> arm: dts: add dm816x missing spi DT dma handles Tony, The two first are fixes for v4.4-rc. >> arm: dts: add dm816x pwm property to timers >> arm: dts: remove dm816x invalid DT l3_main hwmod >> arm: dts: Add omap4-hwspinlock support in dm816x the 3 following can wait. >> >> arch/arm/boot/dts/dm816x.dtsi | 20 +--- >> 1 file changed, 17 insertions(+), 3 deletions(-) >> >> -- >> 1.9.1 Thanks, Neil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/5] arm: dts: add dm816x missing spi DT dma handles
Add the missing SPI controller DMA handler in the dm816x DT
node, only properties for the two channels on four were present.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index a7a34e4..eee636d 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -280,8 +280,11 @@
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17
- &edma 18 &edma 19>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
+ &edma 18 &edma 19
+ &edma 20 &edma 21
+ &edma 22 &edma 23>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
};
mmc1: mmc@4806 {
--
1.9.1
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[PATCH v2 1/5] arm: dts: add dm816x missing #mbox-cells
Add missing #mbox-cells for dm816x mbox DT node.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 3c99cfa..a7a34e4 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -218,6 +218,7 @@
reg = <0x480c8000 0x2000>;
interrupts = <77>;
ti,hwmods = "mailbox";
+ #mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
mbox_dsp: mbox_dsp {
--
1.9.1
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[PATCH v2 3/5] arm: dts: add dm816x pwm property to timers
Adds ti,timer-pwm property to timers 4 to 7 to permit usage of their
PWM output fonctionnality via the dmtimer driver.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index eee636d..51ad4a9 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -323,6 +323,7 @@
reg = <0x48044000 0x2000>;
interrupts = <92>;
ti,hwmods = "timer4";
+ ti,timer-pwm;
};
timer5: timer@48046000 {
@@ -330,6 +331,7 @@
reg = <0x48046000 0x2000>;
interrupts = <93>;
ti,hwmods = "timer5";
+ ti,timer-pwm;
};
timer6: timer@48048000 {
@@ -337,6 +339,7 @@
reg = <0x48048000 0x2000>;
interrupts = <94>;
ti,hwmods = "timer6";
+ ti,timer-pwm;
};
timer7: timer@4804a000 {
@@ -344,6 +347,7 @@
reg = <0x4804a000 0x2000>;
interrupts = <95>;
ti,hwmods = "timer7";
+ ti,timer-pwm;
};
uart1: uart@4802 {
--
1.9.1
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[PATCH v2 4/5] arm: dts: remove dm816x invalid DT l3_main hwmod
Remove invalid l3_main hwmod entry from dm816x DT ocp node.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 51ad4a9..b9feeea 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -64,7 +64,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- ti,hwmods = "l3_main";
prcm: prcm@4818 {
compatible = "ti,dm816-prcm";
--
1.9.1
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[PATCH v2 5/5] arm: dts: Add omap4-hwspinlock support in dm816x
Add dm816x DT entries for omap4-hwspinlock support as hwmod spinbox.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index b9feeea..eb9bea1 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -226,6 +226,13 @@
};
};
+ spinbox: spinbox@480ca000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x480ca000 0x2000>;
+ ti,hwmods = "spinbox";
+ #hwlock-cells = <1>;
+ };
+
mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
--
1.9.1
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[PATCH v2 0/5] arm: dts: complete dm816x device tree
In order to fix support for the dm816x platform, add missing bits in the dm816x dtsi and cleanup OCP. The last patch adds support for the omap4-hwspinlock. v2: add ocp hwmod cleanup Neil Armstrong (5): arm: dts: add dm816x missing #mbox-cells arm: dts: add dm816x missing spi DT dma handles arm: dts: add dm816x pwm property to timers arm: dts: remove dm816x invalid DT l3_main hwmod arm: dts: Add omap4-hwspinlock support in dm816x arch/arm/boot/dts/dm816x.dtsi | 20 +--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v3 1/2] base: dma-coherent: Add DT property for non exclusive shared-dma-pool
In order to have the ability to declare a non exclusive shared-dma-pool,
i.e. without the DMA_MEMORY_EXCLUSIVE flag, add the 'no-exclusive' DT
optional parameter to initialize the coherent memory without the flag.
Signed-off-by: Neil Armstrong
---
drivers/base/dma-coherent.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
index 55b8398..b57478f 100644
--- a/drivers/base/dma-coherent.c
+++ b/drivers/base/dma-coherent.c
@@ -279,10 +279,14 @@ EXPORT_SYMBOL(dma_mmap_from_coherent);
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
{
struct dma_coherent_mem *mem = rmem->priv;
+ unsigned flags = 0;
+
+ if (!of_get_flat_dt_prop(rmem->fdt_node, "no-exclusive", NULL))
+ flags |= DMA_MEMORY_EXCLUSIVE;
if (!mem &&
dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
-DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE,
+DMA_MEMORY_MAP | flags,
&mem) != DMA_MEMORY_MAP) {
pr_err("Reserved memory: failed to init DMA memory pool at %pa,
size %ld MiB\n",
&rmem->base, (unsigned long)rmem->size / SZ_1M);
--
1.9.1
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[RFC PATCH v3 0/2] Expose DMA_MEMORY_EXCLUSIVE through shared-dma-pool
The shared-dma-pool dt node only exposes exclusive memory, but in order to export non-exclusive coherent memory, add the no-exclusive property and document it. v3: use correct of_get_flat_dt_prop helper v2: simplify patch by looking for DT attribute in callback Neil Armstrong (2): base: dma-coherent: Add DT property for non exclusive shared-dma-pool devicetree: reserved-memory: document the optional no-exclusive parameter .../devicetree/bindings/reserved-memory/reserved-memory.txt | 3 +++ drivers/base/dma-coherent.c | 6 +- 2 files changed, 8 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v3 2/2] devicetree: reserved-memory: document the optional no-exclusive parameter
Document the 'no-exclusive' parameter used for the 'shared-dma-pool' compatible reserved-memory type. Acked-by: Rob Herring Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt index 3da0ebd..897aada 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt @@ -63,6 +63,9 @@ reusable (optional) - empty property able to reclaim it back. Typically that means that the operating system can use that region to store volatile or cached data that can be otherwise regenerated or migrated elsewhere. +no-exclusive (optional) - empty property +- Indicates the operating system can fall back to the default allocation + mechanism if no more enough memory is available from this pool. Linux implementation note: - If a "linux,cma-default" property is present, then Linux will use the -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v2 1/2] base: dma-coherent: Add DT property for non exclusive shared-dma-pool
In order to have the ability to declare a non exclusive shared-dma-pool,
i.e. without the DMA_MEMORY_EXCLUSIVE flag, add the 'no-exclusive' DT
optional parameter to initialize the coherent memory without the flag.
Signed-off-by: Neil Armstrong
---
drivers/base/dma-coherent.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
index 55b8398..cda6364 100644
--- a/drivers/base/dma-coherent.c
+++ b/drivers/base/dma-coherent.c
@@ -279,10 +279,14 @@ EXPORT_SYMBOL(dma_mmap_from_coherent);
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
{
struct dma_coherent_mem *mem = rmem->priv;
+ unsigned flags = 0;
+
+ if (!of_property_read_bool(rmem->fdt_node, "no-exclusive"))
+ flags |= DMA_MEMORY_EXCLUSIVE;
if (!mem &&
dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
-DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE,
+DMA_MEMORY_MAP | flags,
&mem) != DMA_MEMORY_MAP) {
pr_err("Reserved memory: failed to init DMA memory pool at %pa,
size %ld MiB\n",
&rmem->base, (unsigned long)rmem->size / SZ_1M);
--
1.9.1
--
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[RFC PATCH v2 2/2] devicetree: reserved-memory: document the optional no-exclusive parameter
Document the 'no-exclusive' parameter used for the 'shared-dma-pool' compatible reserved-memory type. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt index 3da0ebd..897aada 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt @@ -63,6 +63,9 @@ reusable (optional) - empty property able to reclaim it back. Typically that means that the operating system can use that region to store volatile or cached data that can be otherwise regenerated or migrated elsewhere. +no-exclusive (optional) - empty property +- Indicates the operating system can fall back to the default allocation + mechanism if no more enough memory is available from this pool. Linux implementation note: - If a "linux,cma-default" property is present, then Linux will use the -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v2 0/2] Expose DMA_MEMORY_EXCLUSIVE through shared-dma-pool
The shared-dma-pool dt node only exposes exclusive memory, but in order to export non-exclusive coherent memory, add the no-exclusive property and document it. v2: simplify patch by looking for DT attribute in callback Neil Armstrong (2): base: dma-coherent: Add DT property for non exclusive shared-dma-pool devicetree: reserved-memory: document the optional no-exclusive parameter .../devicetree/bindings/reserved-memory/reserved-memory.txt | 3 +++ drivers/base/dma-coherent.c | 6 +- 2 files changed, 8 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/4] arm: dts: complete dm816x device tree
In order to fix support for the dm816x platform, add missing bits in the dm816x dtsi. The last patch adds support for the omap4-hwspinlock. Neil Armstrong (4): arm: dts: add dm816x missing #mbox-cells arm: dts: add dm816x missing spi DT dma handles arm: dts: add dm816x pwm property to timers arm: dts: Add omap4-hwspinlock support in dm816x arch/arm/boot/dts/dm816x.dtsi | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] arm: dts: add dm816x missing spi DT dma handles
Add the missing SPI controller DMA handler in the dm816x DT
node, only properties for the two channels on four were present.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index a7a34e4..eee636d 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -280,8 +280,11 @@
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17
- &edma 18 &edma 19>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
+ &edma 18 &edma 19
+ &edma 20 &edma 21
+ &edma 22 &edma 23>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
};
mmc1: mmc@4806 {
--
1.9.1
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[PATCH 1/4] arm: dts: add dm816x missing #mbox-cells
Add missing #mbox-cells for dm816x mbox DT node.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 3c99cfa..a7a34e4 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -218,6 +218,7 @@
reg = <0x480c8000 0x2000>;
interrupts = <77>;
ti,hwmods = "mailbox";
+ #mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
mbox_dsp: mbox_dsp {
--
1.9.1
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[PATCH 4/4] arm: dts: Add omap4-hwspinlock support in dm816x
Add dm816x DT entries for omap4-hwspinlock support as hwmod spinbox.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 51ad4a9..f655ce1 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -227,6 +227,13 @@
};
};
+ spinbox: spinbox@480ca000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x480ca000 0x2000>;
+ ti,hwmods = "spinbox";
+ #hwlock-cells = <1>;
+ };
+
mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
--
1.9.1
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[PATCH 3/4] arm: dts: add dm816x pwm property to timers
Adds ti,timer-pwm property to timers 4 to 7 to permit usage of their
PWM output fonctionnality via the dmtimer driver.
Cc: Brian Hutchinson
Signed-off-by: Neil Armstrong
---
arch/arm/boot/dts/dm816x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index eee636d..51ad4a9 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -323,6 +323,7 @@
reg = <0x48044000 0x2000>;
interrupts = <92>;
ti,hwmods = "timer4";
+ ti,timer-pwm;
};
timer5: timer@48046000 {
@@ -330,6 +331,7 @@
reg = <0x48046000 0x2000>;
interrupts = <93>;
ti,hwmods = "timer5";
+ ti,timer-pwm;
};
timer6: timer@48048000 {
@@ -337,6 +339,7 @@
reg = <0x48048000 0x2000>;
interrupts = <94>;
ti,hwmods = "timer6";
+ ti,timer-pwm;
};
timer7: timer@4804a000 {
@@ -344,6 +347,7 @@
reg = <0x4804a000 0x2000>;
interrupts = <95>;
ti,hwmods = "timer7";
+ ti,timer-pwm;
};
uart1: uart@4802 {
--
1.9.1
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[PATCH 1/2] base: dma-coherent: Add DT property for non exclusive shared-dma-pool
In order to have the ability to declare a non exclusive shared-dma-pool,
i.e. without the DMA_MEMORY_EXCLUSIVE flag, add the 'no-exclusive' DT
optional parameter to initialize the coherent memory without the flag.
Leave exclusive memory as default.
Signed-off-by: Neil Armstrong
---
drivers/base/dma-coherent.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
index 55b8398..e32d3cc 100644
--- a/drivers/base/dma-coherent.c
+++ b/drivers/base/dma-coherent.c
@@ -276,13 +276,14 @@ EXPORT_SYMBOL(dma_mmap_from_coherent);
#include
#include
-static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
+static int rmem_dma_device_flags_init(struct reserved_mem *rmem,
+ struct device *dev, int flags)
{
struct dma_coherent_mem *mem = rmem->priv;
if (!mem &&
dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
-DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE,
+DMA_MEMORY_MAP | flags,
&mem) != DMA_MEMORY_MAP) {
pr_err("Reserved memory: failed to init DMA memory pool at %pa,
size %ld MiB\n",
&rmem->base, (unsigned long)rmem->size / SZ_1M);
@@ -293,6 +294,17 @@ static int rmem_dma_device_init(struct reserved_mem *rmem,
struct device *dev)
return 0;
}
+static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
+{
+ return rmem_dma_device_flags_init(rmem, dev, 0);
+}
+
+static int rmem_dma_device_exclusive_init(struct reserved_mem *rmem,
+ struct device *dev)
+{
+ return rmem_dma_device_flags_init(rmem, dev, DMA_MEMORY_EXCLUSIVE);
+}
+
static void rmem_dma_device_release(struct reserved_mem *rmem,
struct device *dev)
{
@@ -304,6 +316,11 @@ static const struct reserved_mem_ops rmem_dma_ops = {
.device_release = rmem_dma_device_release,
};
+static const struct reserved_mem_ops rmem_dma_exclusive_ops = {
+ .device_init= rmem_dma_device_exclusive_init,
+ .device_release = rmem_dma_device_release,
+};
+
static int __init rmem_dma_setup(struct reserved_mem *rmem)
{
unsigned long node = rmem->fdt_node;
@@ -318,7 +335,10 @@ static int __init rmem_dma_setup(struct reserved_mem *rmem)
}
#endif
- rmem->ops = &rmem_dma_ops;
+ if (of_get_flat_dt_prop(node, "no-exclusive", NULL))
+ rmem->ops = &rmem_dma_ops;
+ else
+ rmem->ops = &rmem_dma_exclusive_ops;
pr_info("Reserved memory: created DMA memory pool at %pa, size %ld
MiB\n",
&rmem->base, (unsigned long)rmem->size / SZ_1M);
return 0;
--
1.9.1
--
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[PATCH 0/2] Expose DMA_MEMORY_EXCLUSIVE through shared-dma-pool
The shared-dma-pool dt node only exposes exclusive memory, but in order to export non-exclusive coherent memory, add the no-exclusive property and document it. Neil Armstrong (2): base: dma-coherent: Add DT property for non exclusive shared-dma-pool devicetree: reserved-memory: document the optional no-exclusive parameter .../bindings/reserved-memory/reserved-memory.txt | 3 +++ drivers/base/dma-coherent.c| 26 +++--- 2 files changed, 26 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] devicetree: reserved-memory: document the optional no-exclusive parameter
Document the 'no-exclusive' parameter used for the 'shared-dma-pool' compatible reserved-memory type. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt index 3da0ebd..897aada 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt @@ -63,6 +63,9 @@ reusable (optional) - empty property able to reclaim it back. Typically that means that the operating system can use that region to store volatile or cached data that can be otherwise regenerated or migrated elsewhere. +no-exclusive (optional) - empty property +- Indicates the operating system can fall back to the default allocation + mechanism if no more enough memory is available from this pool. Linux implementation note: - If a "linux,cma-default" property is present, then Linux will use the -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
pyfdt : Python Flattened Device Tree Parser
Hi All, I wanted to notice you about a new project I started recently : pyftd You can find the Apache 2 licenced code at : https://github.com/superna/pyfdt I needed to parse Fdt blob from python and I created the corresponding library. The library is python 2.6 and 2.7 compatible and is tested against dtc tests blobs. It supports dtb loading into in-memory objects and DTS or DTB output. I plan to add "path" lookups and properties changing. I do not have any time to implement a 'compiler' but it would be possible. Regards, Neil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
