Re: [PATCH v5 net-next 3/3] dt-bindings: net: macb: Add NP4 macb variant
Le 05/01/2016 14:39, Neil Armstrong a écrit :
> Add NP4 macb SoC variant.
>
> Signed-off-by: Neil Armstrong
Acked-by: Nicolas Ferre
Neil, thanks for your understanding and reactivity concerning this patch
series.
Bye,
> ---
> Documentation/devicetree/bindings/net/macb.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/net/macb.txt
> b/Documentation/devicetree/bindings/net/macb.txt
> index 38c8e84..5c397ca 100644
> --- a/Documentation/devicetree/bindings/net/macb.txt
> +++ b/Documentation/devicetree/bindings/net/macb.txt
> @@ -4,6 +4,7 @@ Required properties:
> - compatible: Should be "cdns,[-]{macb|gem}"
>Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
>available on sama5d3 SoCs.
> + Use "cdns,np4-macb" for NP4 SoC devices.
>Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
> "cdns,macb".
>Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based
> on
>the Cadence GEM, or the generic form: "cdns,gem".
>
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Re: [PATCH v5 net-next 2/3] net: macb: Add NP4 macb config using USRIO_DISABLED
Le 05/01/2016 14:39, Neil Armstrong a écrit :
> Declare a new NP4 SoC variant having USRIO_DISABLED as capability bit.
>
> Signed-off-by: Neil Armstrong
Acked-by: Nicolas Ferre
> ---
> drivers/net/ethernet/cadence/macb.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> index fa53bc3..d12ee07 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -2781,6 +2781,11 @@ static const struct macb_config emac_config = {
> .init = at91ether_init,
> };
>
> +static const struct macb_config np4_config = {
> + .caps = MACB_CAPS_USRIO_DISABLED,
> + .clk_init = macb_clk_init,
> + .init = macb_init,
> +};
>
> static const struct macb_config zynqmp_config = {
> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
> @@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
> { .compatible = "cdns,at32ap7000-macb" },
> { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
> { .compatible = "cdns,macb" },
> + { .compatible = "cdns,np4-macb", .data = &np4_config },
> { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
> { .compatible = "cdns,gem", .data = &pc302gem_config },
> { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
>
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Re: [PATCH v5 net-next 1/3] net: ethernet: cadence-macb: Add disabled usrio caps
Le 05/01/2016 14:39, Neil Armstrong a écrit :
> On some platforms, the macb integration does not use the USRIO
> register to configure the (R)MII port and clocks.
> When the register is not implemented and the MACB error signal
> is connected to the bus error, reading or writing to the USRIO
> register can trigger some Imprecise External Aborts on ARM platforms.
>
> Signed-off-by: Neil Armstrong
Acked-by: Nicolas Ferre
Thanks!
> ---
> drivers/net/ethernet/cadence/macb.c | 27 +++
> drivers/net/ethernet/cadence/macb.h | 1 +
> 2 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> index 8b45bc9..fa53bc3 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -2124,7 +2124,8 @@ static void macb_get_regs(struct net_device *dev,
> struct ethtool_regs *regs,
> regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
> regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
>
> - regs_buff[12] = macb_or_gem_readl(bp, USRIO);
> + if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
> + regs_buff[12] = macb_or_gem_readl(bp, USRIO);
> if (macb_is_gem(bp)) {
> regs_buff[13] = gem_readl(bp, DMACFG);
> }
> @@ -2403,19 +2404,21 @@ static int macb_init(struct platform_device *pdev)
> dev->hw_features &= ~NETIF_F_SG;
> dev->features = dev->hw_features;
>
> - val = 0;
> - if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
> - val = GEM_BIT(RGMII);
> - else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
> - (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> - val = MACB_BIT(RMII);
> - else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> - val = MACB_BIT(MII);
> + if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
> + val = 0;
> + if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
> + val = GEM_BIT(RGMII);
> + else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
> + (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> + val = MACB_BIT(RMII);
> + else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> + val = MACB_BIT(MII);
>
> - if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
> - val |= MACB_BIT(CLKEN);
> + if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
> + val |= MACB_BIT(CLKEN);
>
> - macb_or_gem_writel(bp, USRIO, val);
> + macb_or_gem_writel(bp, USRIO, val);
> + }
>
> /* Set MII management clock divider */
> val = macb_mdc_clk_div(bp);
> diff --git a/drivers/net/ethernet/cadence/macb.h
> b/drivers/net/ethernet/cadence/macb.h
> index 5c03e81..0d4ecfc 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -400,6 +400,7 @@
> #define MACB_CAPS_USRIO_HAS_CLKEN0x0002
> #define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x0004
> #define MACB_CAPS_NO_GIGABIT_HALF0x0008
> +#define MACB_CAPS_USRIO_DISABLED 0x0010
> #define MACB_CAPS_FIFO_MODE 0x1000
> #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000
> #define MACB_CAPS_SG_DISABLED0x4000
>
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Re: [PATCH v4 net-next 2/3] net: macb: Add NPx macb config using USRIO_DISABLED cap
Le 05/01/2016 13:20, Neil Armstrong a écrit :
> On 01/04/2016 11:38 AM, Nicolas Ferre wrote:
>> Le 04/01/2016 10:42, Neil Armstrong a écrit :
>>> static const struct macb_config zynqmp_config = {
>>> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
>>> @@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
>>> { .compatible = "cdns,at32ap7000-macb" },
>>> { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
>>> { .compatible = "cdns,macb" },
>>> + { .compatible = "cdns,npx-macb", .data = &npx_config },
>>
>> I can accept that, but I think that you'd better make your device tree
>> compatibility string *not* generic. Name it by the first NPx SoC or
>> perfectly compatible SoC family that has this configuration and you'll
>> be able to make the NP(x+1) compatible with it.
> Well, the first Soc having this configuration is Np4, would cdns,np4-macb be
> ok ?
Yes, absolutely.
Thanks
>> It has proven to be much more future proof and even if in the early days
>> of DT on ARM we accepted some binding with generic strings like this one
>> below, It has proven to be a mistake.
>>
>>> { .compatible = "cdns,gem", .data = &pc302gem_config },
>>> { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
>>>
>>
>>
>
> Neil
>
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Re: [PATCH v4 net-next 2/3] net: macb: Add NPx macb config using USRIO_DISABLED cap
Le 04/01/2016 10:42, Neil Armstrong a écrit :
> Declare a new SoC variant for NPx SoCs having USRIO_DISABLED as
> capability bit.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/net/ethernet/cadence/macb.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> index fa53bc3..a9e27a7 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -2781,6 +2781,11 @@ static const struct macb_config emac_config = {
> .init = at91ether_init,
> };
>
> +static const struct macb_config npx_config = {
> + .caps = MACB_CAPS_USRIO_DISABLED,
> + .clk_init = macb_clk_init,
> + .init = macb_init,
> +};
>
> static const struct macb_config zynqmp_config = {
> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
> @@ -2801,6 +2806,7 @@ static const struct of_device_id macb_dt_ids[] = {
> { .compatible = "cdns,at32ap7000-macb" },
> { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
> { .compatible = "cdns,macb" },
> + { .compatible = "cdns,npx-macb", .data = &npx_config },
I can accept that, but I think that you'd better make your device tree
compatibility string *not* generic. Name it by the first NPx SoC or
perfectly compatible SoC family that has this configuration and you'll
be able to make the NP(x+1) compatible with it.
It has proven to be much more future proof and even if in the early days
of DT on ARM we accepted some binding with generic strings like this one
below, It has proven to be a mistake.
> { .compatible = "cdns,gem", .data = &pc302gem_config },
> { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
>
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Re: [PATCH v2 2/2] ASoC: atmel-classd: DT binding for PDMIC driver
It seems that the $subject is not correct.
Le 17/12/2015 10:44, Songjun Wu a écrit :
> DT binding documentation for this new ASoC driver.
>
> Signed-off-by: Songjun Wu
> ---
>
> Changes in v2: None
>
> .../devicetree/bindings/sound/atmel-pdmic.txt | 55
>
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/atmel-pdmic.txt
>
> diff --git a/Documentation/devicetree/bindings/sound/atmel-pdmic.txt
> b/Documentation/devicetree/bindings/sound/atmel-pdmic.txt
> new file mode 100644
> index 000..e0875f1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/atmel-pdmic.txt
> @@ -0,0 +1,55 @@
> +* Atmel PDMIC driver under ALSA SoC architecture
> +
> +Required properties:
> +- compatible
> + Should be "atmel,sama5d2-pdmic".
> +- reg
> + Should contain PDMIC registers location and length.
> +- interrupts
> + Should contain the IRQ line for the PDMIC.
> +- dmas
> + One DMA specifiers as described in atmel-dma.txt and dma.txt files.
> +- dma-names
> + Must be "rx".
> +- clock-names
> + Required elements:
> + - "pclk"peripheral clock
> + - "gclk"generated clock
> +- clocks
> + Must contain an entry for each required entry in clock-names.
> + Please refer to clock-bindings.txt.
> +- atmel,mic-min-freq
> + The minimal frequency that the micphone supports.
> +- atmel,mic-max-freq
> + The maximal frequency that the micphone supports.
> +
> +Optional properties:
> +- pinctrl-names, pinctrl-0
> + Please refer to pinctrl-bindings.txt.
> +- atmel,model
> + The user-visible name of this sound card.
> + The default value is "PDMIC".
> +- atmel,mic-offset
> + The offset that should be added.
> + The range is from -32768 to 32767.
> + The default value is 0.
> +
> +Example:
> + pdmic@f8018000 {
> + compatible = "atmel,sama5d2-pdmic";
> + reg = <0xf8018000 0x124>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(50))>;
> + dma-names = "rx";
> + clocks = <&pdmic_clk>, <&pdmic_gclk>;
> + clock-names = "pclk", "gclk";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pdmic_default>;
> + atmel,model = "PDMIC @ sama5d2_xplained";
> + atmel,mic-min-freq = <100>;
> + atmel,mic-max-freq = <3246000>;
> + atmel,mic-offset = <0x0>;
> + };
>
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Re: [PATCH] ARM: at91/dt: sama5d2: add watchdog node
Le 05/11/2015 08:39, Wenyou Yang a écrit :
> Add watchdog node to support SAMA5D4 watchdog.
>
> Signed-off-by: Wenyou Yang
Acked-by: Nicolas Ferre
And stacked on top of at91-4.5-dt.
Thanks!
> ---
>
> arch/arm/boot/dts/at91-sama5d2_xplained.dts |4
> arch/arm/boot/dts/sama5d2.dtsi |7 +++
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index e07c2b2..de3ef02 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -181,6 +181,10 @@
> };
> };
>
> + watchdog@f8048040 {
> + status = "okay";
> + };
> +
> uart3: serial@fc008000 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart3_default>;
> diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
> index c1f0cba..c29ff70 100644
> --- a/arch/arm/boot/dts/sama5d2.dtsi
> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> @@ -929,6 +929,13 @@
> clocks = <&h32ck>;
> };
>
> + watchdog@f8048040 {
> + compatible = "atmel,sama5d4-wdt";
> + reg = <0xf8048040 0x10>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
> + status = "disabled";
> + };
> +
> sckc@f8048050 {
> compatible = "atmel,at91sam9x5-sckc";
> reg = <0xf8048050 0x4>;
>
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Re: [PATCH linux-next 5/5] mtd: atmel-quadspi: add driver for Atmel QSPI controller
Le 07/12/2015 15:09, Cyrille Pitchen a écrit :
> This driver add support to the new Atmel QSPI controller embedded into
> sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
> controller.
>
> Signed-off-by: Cyrille Pitchen
Brian,
This driver has been maturing for months and my only goal is to keep on
supporting it.
As I already gave my Ack this summer, here is it now for sure:
Acked-by: Nicolas Ferre
I recall that Marek gave his as well and might also agree with the
changes and re-iterate his support.
Together with the current work of Cyrille on the spi-nor Quad SPI
support ("[PATCH linux-next 0/4] mtd: spi-nor: fix Quad SPI memory
support"), I have the feeling that this driver deserves an inclusion in
linux-next.
The infrastructure put in place and then used by this driver will
certainly help other developers to build their driver on top. I had the
impression that at least Marek was considering to use this for his
Cadence driver:
His quote from mid-September:
"
Are there any news on this patch series? I'd like to use that for my own
QSPI driver (the Cadence one), so I'd like to check on the status. Are you
still working on this please ?
"
Can we find a way to give this work even more exposure and consider at
least the spi-nor and m25p80 parts mentioned just above for mainline
inclusion?
Best regards,
> ---
> drivers/mtd/spi-nor/Kconfig | 8 +
> drivers/mtd/spi-nor/Makefile| 3 +-
> drivers/mtd/spi-nor/atmel-quadspi.c | 877
>
> 3 files changed, 887 insertions(+), 1 deletion(-)
> create mode 100644 drivers/mtd/spi-nor/atmel-quadspi.c
>
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 0dc927540b3d..15f45dbbfe0d 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -37,6 +37,14 @@ config SPI_FSL_QUADSPI
> This controller does not support generic SPI. It only supports
> SPI NOR.
>
> +config SPI_ATMEL_QUADSPI
> + tristate "Atmel Quad SPI Controller"
> + depends on OF && HAS_DMA && (ARCH_AT91 || COMPILE_TEST)
> + help
> + This enables support for the Quad SPI controller in master mode.
> + This driver does not support generic SPI. The implementation only
> + supports SPI NOR.
> +
> config SPI_NXP_SPIFI
> tristate "NXP SPI Flash Interface (SPIFI)"
> depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
> index 0bf3a7f81675..0cbed0e4ae8c 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -1,4 +1,5 @@
> obj-$(CONFIG_MTD_SPI_NOR)+= spi-nor.o
> obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o
> -obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o
> +obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
> +obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
> obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c
> b/drivers/mtd/spi-nor/atmel-quadspi.c
> new file mode 100644
> index ..bdebfdc92842
> --- /dev/null
> +++ b/drivers/mtd/spi-nor/atmel-quadspi.c
> @@ -0,0 +1,877 @@
> +/*
> + * Driver for Atmel QSPI Controller
> + *
> + * Copyright (C) 2015 Atmel Corporation
> + *
> + * Author: Cyrille Pitchen
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +/* QSPI register offsets */
> +#define QSPI_CR 0x /* Control Register */
> +#define QSPI_MR 0x0004 /* Mode Register */
> +#define QSPI_RD 0x0008 /* Receive Data Register */
> +#define QSPI_TD 0x000c /* Transmit Data Register */
> +#define QSPI_SR 0x0010 /* Status Register */
> +#define QS
Re: [PATCH linux-next 4/5] Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
Le 07/12/2015 15:09, Cyrille Pitchen a écrit :
> This patch documents the DT bindings for the driver of the Atmel QSPI
> controller embedded inside sama5d2x SoCs.
>
> Signed-off-by: Cyrille Pitchen
The change is very small from previous one and moreover accepted by Rob.
So, for sure:
Acked-by: Nicolas Ferre
> ---
> .../devicetree/bindings/mtd/atmel-quadspi.txt | 32
> ++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> new file mode 100644
> index ..e81f20f9faf1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> @@ -0,0 +1,32 @@
> +* Atmel Quad Serial Peripheral Interface (QSPI)
> +
> +Required properties:
> +- compatible: Should be "atmel,sama5d2-qspi".
> +- reg:Should contain the locations and lengths of the base
> registers
> + and the mapped memory.
> +- reg-names: Should contain the resource reg names:
> + - qspi_base: configuration register address space
> + - qspi_mmap: memory mapped address space
> +- interrupts: Should contain the interrupt for the device.
> +- clocks: The phandle of the clock needed by the QSPI controller.
> +- #address-cells: Should be <1>.
> +- #size-cells:Should be <0>.
> +
> +Example:
> +
> +spi@f002 {
> + compatible = "atmel,sama5d2-qspi";
> + reg = <0xf002 0x100>, <0xd000 0x800>;
> + reg-names = "qpsi_base", "qspi_mmap";
> + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&spi0_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi0_default>;
> + status = "okay";
> +
> + m25p80@0 {
> + ...
> + };
> +};
>
--
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Re: [PATCH v2 net-next 2/3] net: ethernet: cadence-macb: Add fallback to read DT provided caps
Le 08/12/2015 16:00, Arnd Bergmann a écrit : > On Tuesday 08 December 2015 14:52:05 Neil Armstrong wrote: >> Add 1:1 mapping of software defines caps parsing from DT in case the >> generic macb compatible form is used. >> These properties will provide support for futures implementations >> only defined from DT without need to update the driver code to support >> new variants. >> >> Signed-off-by: Neil Armstrong >> > > Translating the Linux implementation specific configuration into > DT properties directly is usually not the best way. > > Could we instead have a lookup table by compatible string to set the > flags? It seems that there are lots of different flags but only a > couple of different users of this IP block. Also, the fact that > you are now adding yet another quirk tells me that the set you > define today is unlikely to cover all the future requirements. This is basically what I told Neil in my previous email. I understand you point Neil, but I don't find it makes sense and Arnd described it better that I did. So please find a proper compatibility string and simply use it. What about: "cdns,the_name_of_the_product_that_first_implemented_this_no_usrio_special_case-gem"? Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH net 1/2] net: cadence: macb: Disable USRIO register on some platforms
Le 08/12/2015 10:21, Neil Armstrong a écrit : > Hi Josh, > > 2015-12-07 20:32 GMT+01:00 Josh Cartwright : >> On Mon, Dec 07, 2015 at 11:58:33AM +0100, Neil Armstrong wrote: >>> On some platforms, the macb integration does not use the USRIO >>> register to configure the (R)MII port and clocks. >>> When the register is not implemented and the MACB error signal >>> is connected to the bus error, reading or writing to the USRIO >>> register can trigger some Imprecise External Aborts on ARM platforms. >>> --- >> >> Does this make sense to even be a separate bool device tree property? >> >> This sort of configuration is typically done by: >>1. Creating a new 'caps' bit; relevant codepaths check that bit >>2. Creating a new "compatible" string for your platform's macb >> instance >>3. Creating a new 'struct macb_config' instance for your platform, >> setting any relevant caps bits when it is selected. >> >> Josh > > I see the point, but according to the User Guide : >> User I/O Register >> The MACB design provides up to 16 inputs and 16 outputs, >> for which the state of the I/O may >> be read or set under the control of the processor interface. >> If the user I/O is disabled as a configuration option, this address space is >> defined >> as reserved, and hence will be a read-only register of value 0x0. > > On the design I worked on, the macb_user_* signals were commented, > thus disabling this register. > > The implementation is not mandatory, and the "generic" macb compatible > "cdns,macb" should disable > usage of USRIO register by default and be only used for platform > specific macb instances... > > Is it OK if I add a new 'caps' bit and use it for the "generic" macb instance > ? I would say no as some platform may already use this compatibility string. So If you need a different capability set, please create a new compatible string and use this one. > For the device tree property, it should be safe to have the generic > instances of macb and gem to > rely on these properties instead of hardcoded instances. > (it's the biggest aim of device tree, no ? no more hardcoded 'caps' bit ?) > The "no-usrio" and other should eventually map 'caps' bits along the > generic instances. It has been decided a log time ago to use these capabilities and to have mixed approach to the actual configuration of the IP: - from the compatibility string - from the configuration registers. I may be sometimes challenging to figure out where the final property comes from but it has proven to be pretty well adapted to any kind of situation. So let's continue with this and not insert additional properties to this binding. Best regards, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/4] ARM: at91/dt: sama5d4: update i2c compatible string
Le 03/12/2015 10:53, Ludovic Desroches a écrit :
> A new compatible string has been introduced: atmel,sama5d4-i2c. It
> allows to use the i2c-sda-hold-time-ns property if needed.
>
> Signed-off-by: Ludovic Desroches
Wolfram, we'll take this one with us in the at91 branches that will go
into arm-soc. It'll be queued in at91-4.5-dt branch soon.
Acked-by: Nicolas Ferre
> ---
> arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 2193637..83d7e7c 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -916,7 +916,7 @@
> };
>
> i2c0: i2c@f8014000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8014000 0x4000>;
> interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
> @@ -935,7 +935,7 @@
> };
>
> i2c1: i2c@f8018000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8018000 0x4000>;
> interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
> @@ -975,7 +975,7 @@
> };
>
> i2c2: i2c@f8024000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8024000 0x4000>;
> interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
>
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Re: [PATCH v2 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time
Le 03/12/2015 10:53, Ludovic Desroches a écrit :
> Data have to be held longer for the PMIC device. The ACT8945A
> datasheet claims that minimum SDA data hold time is about 300 ns.
>
> Signed-off-by: Ludovic Desroches
Same here, we'll take this one with at91 material in at91-4.5-dt branch
soon.
Acked-by: Nicolas Ferre
Thanks, bye.
> ---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index ad6de73..9bced00 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -129,6 +129,7 @@
> dmas = <0>, <0>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_i2c0_default>;
> + i2c-sda-hold-time-ns = <350>;
> status = "okay";
>
> pmic: act8865@5b {
>
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Re: [PATCH v2 2/4] i2c: at91: update bindings documention
Le 03/12/2015 10:53, Ludovic Desroches a écrit :
> The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.
>
> Signed-off-by: Ludovic Desroches
> Acked-by: Rob Herring
Acked-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/i2c/i2c-at91.txt | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> index 6e81dc1..ef973a0 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> @@ -3,7 +3,7 @@ I2C for Atmel platforms
> Required properties :
> - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
> "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c",
> "atmel,at91sam9g10-i2c",
> - "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
> + "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
> - reg: physical base address of the controller and length of memory mapped
> region.
> - interrupts: interrupt number to the cpu.
> @@ -17,6 +17,8 @@ Optional properties:
> - dma-names: should contain "tx" and "rx".
> - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for
> FIFO
>capable I2C controllers.
> +- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
> + and "atmel,sama5d2-i2c".
> - Child nodes conforming to i2c bus binding
>
> Examples :
> @@ -52,6 +54,7 @@ i2c0: i2c@f8034600 {
> #size-cells = <0>;
> clocks = <&flx0>;
> atmel,fifo-size = <16>;
> + i2c-sda-hold-time-ns = <336>;
>
> wm8731: wm8731@1a {
> compatible = "wm8731";
>
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Re: [PATCH v2 1/4] i2c: at91: add support for the HOLD field
Le 03/12/2015 10:53, Ludovic Desroches a écrit :
> The hold field allows to configure the data hold time which can be set
> with the help of the generic binding 'i2c-sda-hold-time-ns'. This
> feature has been introduced with SAMA5D4 SoC family.
>
> Signed-off-by: Ludovic Desroches
Acked-by: Nicolas Ferre
> ---
> drivers/i2c/busses/i2c-at91.c | 53
> ---
> 1 file changed, 50 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index 10835d1..921d32b 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -64,6 +64,8 @@
> #define AT91_TWI_IADR 0x000c /* Internal Address Register */
>
> #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg
> */
> +#define AT91_TWI_CWGR_HOLD_MAX 0x1f
> +#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
>
> #define AT91_TWI_SR 0x0020 /* Status Register */
> #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
> @@ -110,6 +112,7 @@ struct at91_twi_pdata {
> unsigned clk_offset;
> bool has_unre_flag;
> bool has_alt_cmd;
> + bool has_hold_field;
> struct at_dma_slave dma_slave;
> };
>
> @@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
> */
> static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
> {
> - int ckdiv, cdiv, div;
> + int ckdiv, cdiv, div, hold = 0;
> struct at91_twi_pdata *pdata = dev->pdata;
> int offset = pdata->clk_offset;
> int max_ckdiv = pdata->clk_max_div;
> + u32 twd_hold_time_ns = 0;
>
> div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> 2 * twi_clk) - offset);
> @@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev
> *dev, int twi_clk)
> cdiv = 255;
> }
>
> - dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
> - dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
> + if (pdata->has_hold_field) {
> + of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
> + &twd_hold_time_ns);
> +
> + /*
> + * hold time = HOLD + 3 x T_peripheral_clock
> + * Use clk rate in kHz to prevent overflows when computing
> + * hold.
> + */
> + hold = DIV_ROUND_UP(twd_hold_time_ns
> + * (clk_get_rate(dev->clk) / 1000), 100);
> + hold -= 3;
> + if (hold < 0)
> + hold = 0;
> + if (hold > AT91_TWI_CWGR_HOLD_MAX) {
> + dev_warn(dev->dev,
> + "HOLD field set to its maximum value (%d
> instead of %d)\n",
> + AT91_TWI_CWGR_HOLD_MAX, hold);
> + hold = AT91_TWI_CWGR_HOLD_MAX;
> + }
> + }
> +
> + dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
> + | AT91_TWI_CWGR_HOLD(hold);
> +
> + dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
> + cdiv, ckdiv, hold, twd_hold_time_ns);
> }
>
> static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
> @@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
> .clk_offset = 3,
> .has_unre_flag = true,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> };
>
> static struct at91_twi_pdata at91sam9261_config = {
> @@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
> .clk_offset = 4,
> .has_unre_flag = false,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> };
>
> static struct at91_twi_pdata at91sam9260_config = {
> @@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
> .clk_offset = 4,
> .has_unre_flag = false,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> };
>
> static struct at91_twi_pdata at91sam9g20_config = {
> @@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
> .clk_offset = 4,
> .has_unre_flag = false,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> };
>
> static struct at91_twi_pdata at91sam9g10_config = {
> @@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
> .clk_off
Re: [PATCH 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time
Le 02/12/2015 11:39, Ludovic Desroches a écrit :
> Data have to been hold longer for the PMIC device.
s/been/be/
It can also be interesting to know where the value comes from...
> Signed-off-by: Ludovic Desroches
> ---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index ad6de73..9bced00 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -129,6 +129,7 @@
> dmas = <0>, <0>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_i2c0_default>;
> + i2c-sda-hold-time-ns = <350>;
> status = "okay";
>
> pmic: act8865@5b {
>
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Re: [PATCH 3/4] ARM: at91/dt: sama5d4: update i2c compatible string
Le 02/12/2015 11:39, Ludovic Desroches a écrit :
> A new compatible string has been introduced: atmel,sama5d4-i2c. It
> allows to use the i2c-sda-hold-time-ns property if needed.
>
> Signed-off-by: Ludovic Desroches
Acked-by: Nicolas Ferre
Ok, we'll need to synchronize with Wolfram for the 2 remaining ones of
this series.
> ---
> arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 2193637..83d7e7c 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -916,7 +916,7 @@
> };
>
> i2c0: i2c@f8014000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8014000 0x4000>;
> interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
> @@ -935,7 +935,7 @@
> };
>
> i2c1: i2c@f8018000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8018000 0x4000>;
> interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
> @@ -975,7 +975,7 @@
> };
>
> i2c2: i2c@f8024000 {
> - compatible = "atmel,at91sam9x5-i2c";
> + compatible = "atmel,sama5d4-i2c";
> reg = <0xf8024000 0x4000>;
> interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
> dmas = <&dma1
>
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Re: [PATCH 2/4] i2c: at91: update bindings documention
Le 02/12/2015 11:39, Ludovic Desroches a écrit :
> The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.
>
> Signed-off-by: Ludovic Desroches
> ---
> Documentation/devicetree/bindings/i2c/i2c-at91.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> index 6e81dc1..67c6f2e 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> @@ -3,7 +3,7 @@ I2C for Atmel platforms
> Required properties :
> - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
> "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c",
> "atmel,at91sam9g10-i2c",
> - "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
> + "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
> - reg: physical base address of the controller and length of memory mapped
> region.
> - interrupts: interrupt number to the cpu.
> @@ -17,6 +17,7 @@ Optional properties:
> - dma-names: should contain "tx" and "rx".
> - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for
> FIFO
>capable I2C controllers.
> +- i2c-sda-hold-time-ns: TWD hold time, only available from
> "atmel,sama5d4-i2c".
Yep, but you must make it clearer that sama5d2 also has this property
available: people usually don't know that sama5d2 comes after sama5d4
over time...
Bye,
> - Child nodes conforming to i2c bus binding
>
> Examples :
> @@ -52,6 +53,7 @@ i2c0: i2c@f8034600 {
> #size-cells = <0>;
> clocks = <&flx0>;
> atmel,fifo-size = <16>;
> + i2c-sda-hold-time-ns = <336>;
>
> wm8731: wm8731@1a {
> compatible = "wm8731";
>
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Re: [PATCH 1/4] i2c: at91: add upport for the HOLD field
_flag = false,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> };
>
> static const struct platform_device_id at91_twi_devtypes[] = {
> @@ -854,6 +889,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
> .clk_offset = 4,
> .has_unre_flag = false,
> .has_alt_cmd = false,
> + .has_hold_field = false,
> +};
> +
> +static struct at91_twi_pdata sama5d4_config = {
> + .clk_max_div = 7,
> + .clk_offset = 4,
> + .has_unre_flag = false,
> + .has_alt_cmd = false,
> + .has_hold_field = true,
> };
>
> static struct at91_twi_pdata sama5d2_config = {
> @@ -861,6 +905,7 @@ static struct at91_twi_pdata sama5d2_config = {
> .clk_offset = 4,
> .has_unre_flag = true,
> .has_alt_cmd = true,
> + .has_hold_field = true,
> };
>
> static const struct of_device_id atmel_twi_dt_ids[] = {
> @@ -883,6 +928,9 @@ static const struct of_device_id atmel_twi_dt_ids[] = {
> .compatible = "atmel,at91sam9x5-i2c",
> .data = &at91sam9x5_config,
> }, {
> + .compatible = "atmel,sama5d4-i2c",
> + .data = &sama5d4_config,
> + }, {
> .compatible = "atmel,sama5d2-i2c",
> .data = &sama5d2_config,
> }, {
Otherwise it's okay for me.
Bye,
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Re: [PATCH] net/macb: bindings doc: Merge cdns-emac to macb
Le 30/11/2015 14:51, Michal Simek a écrit :
> Merge two bindings for the same driver to together.
>
> Signed-off-by: Michal Simek
Acked-by: Nicolas Ferre
> ---
>
> Documentation/devicetree/bindings/net/cdns-emac.txt | 20
> Documentation/devicetree/bindings/net/macb.txt | 3 +++
> 2 files changed, 3 insertions(+), 20 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/net/cdns-emac.txt
>
> diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt
> b/Documentation/devicetree/bindings/net/cdns-emac.txt
> deleted file mode 100644
> index 4451ee973223..
> --- a/Documentation/devicetree/bindings/net/cdns-emac.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -* Cadence EMAC Ethernet controller
> -
> -Required properties:
> -- compatible: Should be "cdns,[-]{emac}"
> - Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
> - Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
> - Or the generic form: "cdns,emac".
> -- reg: Address and length of the register set for the device
> -- interrupts: Should contain macb interrupt
> -- phy-mode: see ethernet.txt file in the same directory.
> -
> -Examples:
> -
> - macb0: ethernet@fffc4000 {
> - compatible = "cdns,at91rm9200-emac";
> - reg = <0xfffc4000 0x4000>;
> - interrupts = <21>;
> - phy-mode = "rmii";
> - local-mac-address = [3a 0e 03 04 05 06];
> - };
> diff --git a/Documentation/devicetree/bindings/net/macb.txt
> b/Documentation/devicetree/bindings/net/macb.txt
> index b5d79761ac97..1361a6daf63f 100644
> --- a/Documentation/devicetree/bindings/net/macb.txt
> +++ b/Documentation/devicetree/bindings/net/macb.txt
> @@ -2,6 +2,7 @@
>
> Required properties:
> - compatible: Should be "cdns,[-]{macb|gem}"
> + Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
>Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
>available on sama5d3 SoCs.
>Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
> "cdns,macb".
> @@ -10,7 +11,9 @@ Required properties:
>Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2
> SoCs.
>Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
>Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4
> SoCs.
> + Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
>Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
> + Or the generic form: "cdns,emac".
> - reg: Address and length of the register set for the device
> - interrupts: Should contain macb interrupt
> - phy-mode: See ethernet.txt file in the same directory.
>
--
Nicolas Ferre
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Re: [PATCH 10/19] ARM: dts: at91: replace gpio-key,wakeup with wakeup-source property
Le 21/10/2015 14:41, Sudeep Holla a écrit : > > > On 21/10/15 12:13, Sudeep Holla wrote: >> On 21/10/15 12:01, Ulf Hansson wrote: >>> On 21 October 2015 at 12:25, Sudeep Holla wrote: > > [..] > >>>> >>>> Yes that was my intention for splitting the patches per SoC group. >>>> Many SoC maintainers prefer that. >>> >>> Hold on! All patches that changes the DT parsing to accept the >>> "standardized wakeup-source" binding, need to be merged upstream >>> before corresponding DTS changes. >>> >> >> Agreed. Sorry for that I forgot about it as there are only few >> subsystems that needed additions. Most of the input subsystem had >> already moved to new binding, just that binding documents were left >> unchanged. >> > > Having looked at it again, I think at-least this patch has no dependency > on those driver/sub-system changes. Only patch 11, 13 and 17 has > dependency. All the other DTS changes are related to input subsystem > where all the required changes are already there. Actually I checked before answering and all the drivers are already converted for the AT91 patch: so for this 10/19 patch I'm fine... Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 10/19] ARM: dts: at91: replace gpio-key,wakeup with wakeup-source property
Le 21/10/2015 12:10, Sudeep Holla a écrit :
> Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
> check for/support the legacy "gpio-key,wakeup" boolean property to
> enable gpio buttons as wakeup source, "wakeup-source" is the new
> standard binding.
>
> This patch replaces the legacy "gpio-key,wakeup" with the unified
> "wakeup-source" property in order to avoid any futher copy-paste
> duplication.
>
> Cc: Nicolas Ferre
I'm not against this if the whole series goes further.
Acked-by: Nicolas Ferre
I suspect that we would need to take this patch with us on the AT91
branches that would go to arm-soc. Is it the intentions?
Thanks, bye.
> Cc: Alexandre Belloni
> Cc: Jean-Christophe Plagniol-Villard
> Signed-off-by: Sudeep Holla
> ---
> arch/arm/boot/dts/animeo_ip.dts | 6 +++---
> arch/arm/boot/dts/at91-foxg20.dts | 2 +-
> arch/arm/boot/dts/at91-kizbox.dts | 4 ++--
> arch/arm/boot/dts/at91-kizbox2.dts | 6 +++---
> arch/arm/boot/dts/at91-kizboxmini.dts | 4 ++--
> arch/arm/boot/dts/at91-qil_a9260.dts| 2 +-
> arch/arm/boot/dts/at91-sama5d3_xplained.dts | 2 +-
> arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
> arch/arm/boot/dts/at91-sama5d4ek.dts| 2 +-
> arch/arm/boot/dts/at91sam9261ek.dts | 10 +-
> arch/arm/boot/dts/at91sam9263ek.dts | 4 ++--
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 4 ++--
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 4 ++--
> arch/arm/boot/dts/at91sam9n12ek.dts | 2 +-
> arch/arm/boot/dts/at91sam9rlek.dts | 4 ++--
> arch/arm/boot/dts/sama5d35ek.dts| 2 +-
> arch/arm/boot/dts/usb_a9260_common.dtsi | 2 +-
> arch/arm/boot/dts/usb_a9263.dts | 2 +-
> 18 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
> index 4e0ad3b82796..0962f2fa3f6e 100644
> --- a/arch/arm/boot/dts/animeo_ip.dts
> +++ b/arch/arm/boot/dts/animeo_ip.dts
> @@ -155,21 +155,21 @@
> label = "keyswitch_in";
> gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
> linux,code = <28>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
>
> error_in {
> label = "error_in";
> gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
> linux,code = <29>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
>
> btn {
> label = "btn";
> gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
> linux,code = <31>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/boot/dts/at91-foxg20.dts
> b/arch/arm/boot/dts/at91-foxg20.dts
> index f89598af4c2b..6bf873e7d96c 100644
> --- a/arch/arm/boot/dts/at91-foxg20.dts
> +++ b/arch/arm/boot/dts/at91-foxg20.dts
> @@ -159,7 +159,7 @@
> label = "Button";
> gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
> linux,code = <0x103>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/boot/dts/at91-kizbox.dts
> b/arch/arm/boot/dts/at91-kizbox.dts
> index bf18ece0c027..8afe35f64034 100644
> --- a/arch/arm/boot/dts/at91-kizbox.dts
> +++ b/arch/arm/boot/dts/at91-kizbox.dts
> @@ -94,14 +94,14 @@
> label = "PB_RST";
> gpios = <&pioB 30 GPIO_ACTIVE_HIGH>;
> linux,code = <0x100>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
>
> user {
> label = "PB_USER";
> gpios = <&pioB 31 GPIO_ACTIVE_HIGH>;
> linux,code = <0x101>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
> };
>
> diff --git a/arch/arm/boot/dts/at91-kizbox2.dts
> b/arch/arm/boot/dts/at91-kizbox2.dts
> index f0b1563cb3f1..50a14568f094 100644
> --- a/arch/arm/boot/dts/at91-kizbox2.dts
> +++ b/arch/arm/boot/dts/at91-kizbox2.dts
> @@ -171,21 +171,21 @@
> label = "PB_PROG";
>
Re: [PATCH 3/3] ARM: at91/defconfig: update sama5 defconfig
Le 15/10/2015 17:31, Ludovic Desroches a écrit : > On Thu, Oct 15, 2015 at 03:24:51PM +0200, Alexandre Belloni wrote: >> Hi, >> >> On 14/10/2015 at 14:11:24 +0200, Ludovic Desroches wrote : >>> Add SAMA5D2 SoC plus Atmel flexcom and Atmel sdhci devices. >>> >>> Signed-off-by: Ludovic Desroches >>> --- >>> arch/arm/configs/sama5_defconfig | 6 +- >>> 1 file changed, 5 insertions(+), 1 deletion(-) >>> >> It is probably worth updating the multi_v7_defconfig too (in a separate >> patch). >> > > Maybe I have to send a whole defconfig update . I mean when you do > savedefconfig, you have more changes. I won't send each one separately. I > have kept changes which were in relation with the stuff I had. > > Or I can send a defconfig update from the savedefconfig and then add > sama5d2, flexcom and sdhci. Actually you can do this for our own AT91 defconfigs. For the multi_v7_defconfig I would recommend to simply make a patch with our updates and let the arm-soc maintainer merge it with their current one: I mean, they will manage the conflicts on this file anyway and the changes to this file will not be part of one or our pull-requests but a patch that they will handle separately: so no need to add more update than the strictly needed ones on our end. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/7] ARM: at91/defconfig: sama5: add PIO4 controller support
Le 21/09/2015 20:25, Linus Walleij a écrit : > On Wed, Sep 16, 2015 at 8:37 AM, Ludovic Desroches > wrote: > >> SAMA5D2 chip family has a new PIO controller. >> >> Signed-off-by: Ludovic Desroches > > Acked-by: Linus Walleij > > Please merge this through Nicolas' AT91 tree. Added in the at91-4.4-defconfig branch. Thanks. Paul, This symbol will appear in Linus W.'s tree and is selected in mine. So you may find that the symbol appear unused before the two trees are merged in Linux-next or mainline. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/7] New Atmel PIO4 pinctrl/gpio driver
Le 21/09/2015 20:50, Linus Walleij a écrit : > On Wed, Sep 16, 2015 at 8:36 AM, Ludovic Desroches > wrote: > >> The Atmel PIO4 controller has been introduced with SAMA5D2 chip family. This >> drivers manages both pinmux/pinconf and gpio stuff. It is inspired by >> Mediatek >> pinctrl driver. >> >> Changes from v1: >> - remove some unneeded gpio specific ops (gpio_request, gpio_free, >> gpio_request_enable, gpio_disable_free and gpio_set_direction). >> - code styling fixes. >> - add sama5d2 pin description and device pin muxing. > > Looks Good To Me, and has Sascha's ACKs, so merged patches > 1, 2, 3, 4 to the pinctrl tree. Please merge the AT91 DT things into > the AT91 tree. Great! So patch 5 is included in at91-4.4-defconfig branch. patches 6 and 7 queued in at91-4.4-dt branch. They are included in at91-next that is merged in linux-next and will both take the arm-soc path later in the cycle. Thanks, bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH linux-next v9 0/3] mfd: flexcom: add a driver for Flexcom
Le 20/09/2015 06:19, Lee Jones a écrit : > Patch set description? Cyrille actually placed it as the v1 changelog below... > Once Rob is satisfied, please re-submit this set with Nicolas' Acks I think that Rob was okay with the DT binding: "A few comments, but in general looks fine." and it may not be important to tack Rob for addition of his formal tag... Or maybe this message can act as a "ping" for Rob... > and I will re-review. We wait one or two days before Cyrille re-send the series. We are looking forward to using this driver in Linux-next soon. Bye, >> ChangeLog >> >> v9: >> - go back to v5 (use the new "atmel,flexcom-mode" DT property). >> - fix the name of the spi node in the DT example: from spi@f8034400 to >> spi@400 >> - align the fields of the struct platform_driver atmel_flexcom_driver as >> suggested by Lee Jones. >> >> v8: >> - fix the name of the spi node in the DT example: from spi@f8034400 to >> spi@2,0 >> - use the return code of op_property_read_u32_index() instead of -EINVAL >> to report error. >> - add Acked-by from Nicolas Ferre >> >> v7: >> - read the operating mode from the very first u32 of the reg property from >> the first available child node (should be unique). >> - update the DT bindings documentation accordingly. >> >> v6: >> - select the operating mode according to the "compatible" DT property of >> the first available child node (should be unique). >> - remove the "atmel,flexcom-mode" DT property so the need of a header file >> defining macros for the possible values of this deprecated property. >> >> v5: >> - create a header file containing macros used by DT bindings >> - use numeric constants instead of strings to select the Flexcom mode >> - change the license to "GPL v2" >> - update the DT binding documentation to make it more readable and add >> references to USART, SPI and I2C DT binding documentations. remove the >> useless label in the Example section. >> - change the register prefix from FX_ to FLEX_ to match the Flexcom >> programmer datasheet. >> - rename some variables to make them more understandable. >> >> v4: >> - check clk_prepare_enable() return code in atmel_flexcom_probe() >> - add a commit message to the DT binding patch >> >> v3: >> - remove MODULE_ALIAS() >> - add Acked-by from Boris Brezillon and Alexandre Belloni >> >> v2: >> - enhance the documentation of DT bindings and change the way the "ranges" >> property is used. >> - replace __raw_readl() and __raw_writel() by readl() and writel(). >> - change the module license to "GPL" for v2 or later >> - print the selected flexcom mode after the hardware version >> >> v1: >> This series of patches a support to the Atmel Flexcom, a wrapper which >> integrates an USART, a SPI controller and a TWI controller. Only one >> peripheral can be used at a time. The active function is selected though >> the Flexcom Mode Register. >> >> Cyrille Pitchen (3): >> mfd: atmel-flexcom: create include file with macros used by DT >> bindings >> mfd: devicetree: add bindings for Atmel Flexcom >> mfd: atmel-flexcom: add a driver for Atmel Flexible Serial >> Communication Unit >> >> .../devicetree/bindings/mfd/atmel-flexcom.txt | 67 + >> drivers/mfd/Kconfig | 11 +++ >> drivers/mfd/Makefile | 1 + >> drivers/mfd/atmel-flexcom.c| 104 >> + >> include/dt-bindings/mfd/atmel-flexcom.h| 16 >> 5 files changed, 199 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt >> create mode 100644 drivers/mfd/atmel-flexcom.c >> create mode 100644 include/dt-bindings/mfd/atmel-flexcom.h >> > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: at91/dt: ov2640: add hsync/vsync-active property
Le 21/09/2015 03:19, Josh Wu a écrit :
> Hi, Nicolas
>
> On 9/18/2015 10:09 PM, Nicolas Ferre wrote:
>> Le 18/09/2015 13:28, Josh Wu a écrit :
>>> On at91sam9x5ek/at91sam9m10g45ek/sama5d3xek boards, we use the parallel
>>> connection for ov2640. So we must set the hsync/vsync property (1 means
>>> active high).
>>> Otherwise, the connection would be seen as BT.656 or BT.1120.
>>>
>>> Signed-off-by: Josh Wu
>> Hi Josh,
>>
>> Does this patch apply because of the new enhancement that you had
>> proposed in "media: atmel-isi: parse the DT parameters for
>> vsync/hsync/pixclock polarity" or does it apply even before?
>> Is it a fix that applies to older kernels?
> It's is a fix, according to the dt binding of video interface.
> So it should be applied before:
>
> "media: atmel-isi: parse the DT parameters for
> vsync/hsync/pixclock polarity".
>
>
> it has no impact in older kernel as the driver doesn't parse that
> property yet.
>
>>
>> So, should I wait for the enhancements to enter media git tree or can I
>> take them anyway?
>
> yes, you can take it without waiting for the media tree. Thanks.
Fair enough.
Acked-by: Nicolas Ferre
Thanks for the information. Bye,
> Best Regards,
> Josh Wu
>
>>
>> Bye,
>>
>>> ---
>>>
>>> arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 ++
>>> arch/arm/boot/dts/at91sam9x5ek.dtsi| 2 ++
>>> arch/arm/boot/dts/sama5d3xmb.dtsi | 2 ++
>>> 3 files changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts
>>> b/arch/arm/boot/dts/at91sam9m10g45ek.dts
>>> index d1ae60a..9d16ef8 100644
>>> --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
>>> +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
>>> @@ -198,6 +198,8 @@
>>> isi_0: endpoint {
>>> remote-endpoint = <&ov2640_0>;
>>> bus-width = <8>;
>>> + vsync-active = <1>;
>>> + hsync-active = <1>;
>>> };
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi
>>> b/arch/arm/boot/dts/at91sam9x5ek.dtsi
>>> index d237c46..479f200 100644
>>> --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
>>> @@ -66,6 +66,8 @@
>>> isi_0: endpoint@0 {
>>> remote-endpoint = <&ov2640_0>;
>>> bus-width = <8>;
>>> + vsync-active = <1>;
>>> + hsync-active = <1>;
>>> };
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
>>> b/arch/arm/boot/dts/sama5d3xmb.dtsi
>>> index 83bee7a..8901042 100644
>>> --- a/arch/arm/boot/dts/sama5d3xmb.dtsi
>>> +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
>>> @@ -87,6 +87,8 @@
>>> isi_0: endpoint {
>>> remote-endpoint = <&ov2640_0>;
>>> bus-width = <8>;
>>> + vsync-active = <1>;
>>> + hsync-active = <1>;
>>> };
>>> };
>>> };
>>>
>>
>
>
--
Nicolas Ferre
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Re: [PATCH] ARM: at91/dt: ov2640: add hsync/vsync-active property
Le 18/09/2015 13:28, Josh Wu a écrit :
> On at91sam9x5ek/at91sam9m10g45ek/sama5d3xek boards, we use the parallel
> connection for ov2640. So we must set the hsync/vsync property (1 means
> active high).
> Otherwise, the connection would be seen as BT.656 or BT.1120.
>
> Signed-off-by: Josh Wu
Hi Josh,
Does this patch apply because of the new enhancement that you had
proposed in "media: atmel-isi: parse the DT parameters for
vsync/hsync/pixclock polarity" or does it apply even before?
Is it a fix that applies to older kernels?
So, should I wait for the enhancements to enter media git tree or can I
take them anyway?
Bye,
> ---
>
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 ++
> arch/arm/boot/dts/at91sam9x5ek.dtsi| 2 ++
> arch/arm/boot/dts/sama5d3xmb.dtsi | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts
> b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> index d1ae60a..9d16ef8 100644
> --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
> +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> @@ -198,6 +198,8 @@
> isi_0: endpoint {
> remote-endpoint = <&ov2640_0>;
> bus-width = <8>;
> + vsync-active = <1>;
> + hsync-active = <1>;
> };
> };
> };
> diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi
> b/arch/arm/boot/dts/at91sam9x5ek.dtsi
> index d237c46..479f200 100644
> --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
> @@ -66,6 +66,8 @@
> isi_0: endpoint@0 {
> remote-endpoint = <&ov2640_0>;
> bus-width = <8>;
> + vsync-active = <1>;
> + hsync-active = <1>;
> };
> };
> };
> diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
> b/arch/arm/boot/dts/sama5d3xmb.dtsi
> index 83bee7a..8901042 100644
> --- a/arch/arm/boot/dts/sama5d3xmb.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
> @@ -87,6 +87,8 @@
> isi_0: endpoint {
> remote-endpoint = <&ov2640_0>;
> bus-width = <8>;
> + vsync-active = <1>;
> + hsync-active = <1>;
> };
> };
> };
>
--
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Re: [PATCH linux-next v9 2/3] mfd: devicetree: add bindings for Atmel Flexcom
Le 01/09/2015 16:46, Cyrille Pitchen a écrit :
> This patch documents the DT bindings for the Atmel Flexcom which will be
> introduced by sama5d2x SoCs. These bindings will be used by the actual
> Flexcom driver to be sent in another patch.
>
> Signed-off-by: Cyrille Pitchen
> Acked-by: Boris Brezillon
> Acked-by: Alexandre Belloni
After all, this approach is far more simple and obvious than the use of
the "reg" property, so coming back to this "atmel,flexcom-mode" option
make a lot of sense.
Acked-by: Nicolas Ferre
Bye,
> ---
> .../devicetree/bindings/mfd/atmel-flexcom.txt | 67
> ++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
> b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
> new file mode 100644
> index ..fc3511e41542
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
> @@ -0,0 +1,67 @@
> +* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit)
> +
> +The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
> +controller and an USART. Only one function can be used at a time and is
> chosen
> +at boot time according to the device tree.
> +
> +Required properties:
> +- compatible:Should be "atmel,sama5d2-flexcom"
> +- reg: Should be the offset/length value for Flexcom
> dedicated
> + I/O registers (without USART, TWI or SPI registers).
> +- clocks:Should be the Flexcom peripheral clock from PMC.
> +- #address-cells:Should be <1>
> +- #size-cells: Should be <1>
> +- ranges:Should be one range for the full I/O register region
> + (including USART, TWI and SPI registers).
> +- atmel,flexcom-mode:Should be one of the 3 following macros as
> defined in
> + include/dt-bindings/mfd/atmel-flexcom.h:
> + - ATMEL_FLEXCOM_MODE_USART for USART
> + - ATMEL_FLEXCOM_MODE_SPI for SPI
> + - ATMEL_FLEXCOM_MODE_TWI for I2C
> +
> +Required child:
> +a single child device of type matching the "atmel,flexcom-mode" property.
> +
> +The reg property of this child should be:
> +- <0x200 0x200> for USART
> +- <0x400 0x200> for SPI
> +- <0x600 0x200> for I2C
> +
> +The phandle provided by the clocks property of the child is the same as one
> for
> +the Flexcom parent.
> +
> +Other properties remain unchanged. See documentation of the respective
> device:
> +- ../serial/atmel-usart.txt
> +- ../spi/spi_atmel.txt
> +- ../i2c/i2c-at91.txt
> +
> +Example:
> +
> +flexcom@f8034000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf8034000 0x200>;
> + clocks = <&flx0_clk>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf8034000 0x800>;
> + atmel,flexcom-mode = ;
> +
> + spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flx0_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&flx0_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> +
> + mtd_dataflash@0 {
> + compatible = "atmel,at25f512b";
> + reg = <0>;
> + spi-max-frequency = <2000>;
> + };
> + };
> +};
>
--
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Re: [PATCH linux-next v9 1/3] mfd: atmel-flexcom: create include file with macros used by DT bindings
Le 01/09/2015 16:46, Cyrille Pitchen a écrit : > This patch defines some macros to be used as value for the > "atmel,flexcom-mode" DT property. This value is then written into > the Operating Mode (OPMODE) bit field of the Flexcom Mode Register. > > Signed-off-by: Cyrille Pitchen Acked-by: Nicolas Ferre > --- > include/dt-bindings/mfd/atmel-flexcom.h | 16 > 1 file changed, 16 insertions(+) > create mode 100644 include/dt-bindings/mfd/atmel-flexcom.h > > diff --git a/include/dt-bindings/mfd/atmel-flexcom.h > b/include/dt-bindings/mfd/atmel-flexcom.h > new file mode 100644 > index ..6728f2851b4d > --- /dev/null > +++ b/include/dt-bindings/mfd/atmel-flexcom.h > @@ -0,0 +1,16 @@ > +/* > + * This header provides macros for Atmel Flexcom DT bindings. > + * > + * Copyright (C) 2015 Cyrille Pitchen > + * > + * GPLv2 only > + */ > + > +#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ > +#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ > + > +#define ATMEL_FLEXCOM_MODE_USART 1 > +#define ATMEL_FLEXCOM_MODE_SPI 2 > +#define ATMEL_FLEXCOM_MODE_TWI 3 > + > +#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/5] Documentation: dt-bindings: add example DT binding document
Le 01/09/2015 19:35, Tim Bird a écrit :
> On Fri, Aug 28, 2015 at 7:53 AM, Rob Herring wrote:
>> On Fri, Aug 28, 2015 at 12:23 AM, Matt Porter wrote:
> ...
>>> +example:
>>> + - dts: |
>>> + sk11@0 {
>>> + compatible = "skel,sk11";
>>> + reg = <0>;
>>> + spi-max-frequency = <100>;
>>> + spi-cs-high;
>>> + };
>>
>> At least in this example, we could generate it. Examples are nice, but
>> we have dts files full of examples already. I get a fair number of
>> "fix the example" patches, so maybe we should eliminate the simple
>> ones.
>
> I would hesitate to eliminate examples. I've been saved by them on
> a few occasions, when the dts files only had one or two instances
> of a type of binding, somewhat different from each other, and the example
> helped
> break the tie. If there's something wrong with the example, it's a sign
> of an out-of-date binding doc, just as much as if the text were wrong.
> It ought to be possible to validate the example versus the binding doc
> (as Pantelis says), so ultimately we should be able to catch errors here
> as well.
I back Tim's advice.
Example are so important that I regularly find myself thinking "ah-ha,
okay that's supposed to work like that" after having read the binding
documentation.
Bye,
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Re: [PATCH v3 5/5] mtd: atmel-quadspi: add driver for Atmel QSPI controller
mtd;
> + char modalias[40];
> + int irq, err = 0;
> +
> + if (of_get_child_count(np) != 1)
> + return -ENODEV;
> + child = of_get_next_child(np, NULL);
> +
> + aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
> + if (!aq) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + platform_set_drvdata(pdev, aq);
> + aq->pdev = pdev;
> + /* Start in Extended SPI (1-1-1) */
> + aq->ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
> +
> + /* Map the registers */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + aq->regs = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(aq->regs)) {
> + dev_err(&pdev->dev, "missing registers\n");
> + err = PTR_ERR(aq->regs);
> + goto exit;
> + }
> +
> + /* Map the AHB memory */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + aq->mem = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(aq->mem)) {
> + dev_err(&pdev->dev, "missing AHB memory\n");
> + err = PTR_ERR(aq->regs);
> + goto exit;
> + }
> + aq->phys_addr = (dma_addr_t)res->start;
> +
> + /* Get the peripheral clock */
> + aq->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(aq->clk)) {
> + dev_err(&pdev->dev, "missing peripheral clock\n");
> + err = PTR_ERR(aq->clk);
> + goto exit;
> + }
> +
> + /* Enable the peripheral clock */
> + err = clk_prepare_enable(aq->clk);
> + if (err) {
> + dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
> + goto exit;
> + }
> +
> + /* Request the IRQ */
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "missing IRQ\n");
> + err = irq;
> + goto disable_clk;
> + }
> + err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
> +0, dev_name(&pdev->dev), aq);
> + if (err)
> + goto disable_clk;
> +
> + /* Try to get a DMA channel for memcpy() operation */
> + dma_cap_zero(mask);
> + dma_cap_set(DMA_MEMCPY, mask);
> + aq->chan = dma_request_channel(mask, NULL, NULL);
> + if (!aq->chan)
> + dev_warn(&pdev->dev, "no available DMA channel\n");
> +
> + /* Setup the spi-nor */
> + nor = &aq->nor;
> + mtd = &aq->mtd;
> +
> + nor->mtd = mtd;
> + nor->dev = &pdev->dev;
> + nor->priv = aq;
> + mtd->priv = nor;
> +
> + nor->read_reg = atmel_qspi_read_reg;
> + nor->write_reg = atmel_qspi_write_reg;
> + nor->read = atmel_qspi_read;
> + nor->write = atmel_qspi_write;
> + nor->erase = atmel_qspi_erase;
> + nor->set_protocol = atmel_qspi_set_protocol;
> +
> + if (of_modalias_node(child, modalias, sizeof(modalias)) < 0) {
> + err = -ENODEV;
> + goto release_channel;
> + }
> +
> + err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
> + if (err < 0)
> + goto release_channel;
> +
> + err = atmel_qspi_init(aq);
> + if (err)
> + goto release_channel;
> +
> + nor->dev->of_node = child;
> + err = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
> + nor->dev->of_node = np;
> + if (err)
> + goto release_channel;
> +
> + ppdata.of_node = child;
> + err = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> + if (err)
> + goto release_channel;
> +
> + of_node_put(child);
> +
> + return 0;
> +
> +release_channel:
> + if (aq->chan)
> + dma_release_channel(aq->chan);
> +disable_clk:
> + clk_disable_unprepare(aq->clk);
> +exit:
> + of_node_put(child);
> +
> + return err;
> +}
> +
> +static int atmel_qspi_remove(struct platform_device *pdev)
> +{
> + struct atmel_qspi *aq = platform_get_drvdata(pdev);
> +
> + mtd_device_unregister(&aq->mtd);
> + qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
> + if (aq->chan)
> + dma_release_channel(aq->chan);
> + clk_disable_unprepare(aq->clk);
> + return 0;
> +}
> +
> +
> +static const struct of_device_id atmel_qspi_dt_ids[] = {
> + { .compatible = "atmel,sama5d2-qspi" },
> + { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
> +
> +static struct platform_driver atmel_qspi_driver = {
> + .driver = {
> + .name = "atmel_qspi",
> + .of_match_table = atmel_qspi_dt_ids,
> + },
> + .probe = atmel_qspi_probe,
> + .remove = atmel_qspi_remove,
> +};
> +module_platform_driver(atmel_qspi_driver);
> +
> +MODULE_AUTHOR("Cyrille Pitchen ");
> +MODULE_DESCRIPTION("Atmel QSPI Controller driver");
> +MODULE_LICENSE("GPL v2");
Otherwise, once checked my comments above, you can add my:
Acked-by: Nicolas Ferre
Thanks, bye,
--
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Re: [PATCH v3 4/5] Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
Le 27/07/2015 10:59, Cyrille Pitchen a écrit :
> This patch documents the DT bindings for the driver of the Atmel QSPI
> controller embedded inside sama5d2x SoCs.
>
> Signed-off-by: Cyrille Pitchen
Yes, it seems good:
Acked-by: Nicolas Ferre
> ---
> .../devicetree/bindings/mtd/atmel-quadspi.txt | 29
> ++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> new file mode 100644
> index ..0b8d545bb198
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
> @@ -0,0 +1,29 @@
> +* Atmel Quad Serial Peripheral Interface (QSPI)
> +
> +Required properties:
> +- compatible: should be "atmel,sama5d2-qspi"
> +- reg:the first contains the register location and length,
> + the second contains the memory mapping address and length
> +- interrupts: should contain the interrupt for the device
> +- clocks: the phandle of the clock needed by the QSPI controller
> +- #address-cells: should be <1>
> +- #size-cells:should be <0>
> +
> +Example:
> +
> +spi@f002 {
> + compatible = "atmel,sama5d2-qspi";
> + reg = <0xf002 0x100>,
> + <0xd000 0x800>;
> + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&spi0_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi0_default>;
> + status = "okay";
> +
> + m25p80@0 {
> + ...
> + };
> +};
>
--
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Re: [PATCH v2 2/2] ARM: at91: sama5/dt: update rstc to correct compatible string
Le 20/07/2015 14:37, Nicolas Ferre a écrit :
> Le 20/07/2015 11:32, Josh Wu a écrit :
>> They'll use "atmel,sama5d3-rstc" for reset function.
>>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Josh Wu
>
> Acked-by: Nicolas Ferre
>
> And we'll have to synchronize with the other patches. The best way to
> deal with that can be to take both of them with us through arm-soc.
>
> Sebastian,
>
> 1/ as you weren't in the CC list of the original patch, do you want me
> to re-send the whole series?
>
> 2/ can we take these driver's changes with use through the arm-soc git
> tree so that we can manage the synchronization better?
Okay, so to ease synchronization, I take this one with me through
arm-soc and add the old compatibility string as a fallback => the newer
will be used when merged...
Thanks, bye.
> Thanks, bye,
>
>> ---
>>
>> Changes in v2: None
>>
>> arch/arm/boot/dts/sama5d3.dtsi | 2 +-
>> arch/arm/boot/dts/sama5d4.dtsi | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
>> index 9e2444b..280255b 100644
>> --- a/arch/arm/boot/dts/sama5d3.dtsi
>> +++ b/arch/arm/boot/dts/sama5d3.dtsi
>> @@ -1259,7 +1259,7 @@
>> };
>>
>> rstc@fe00 {
>> -compatible = "atmel,at91sam9g45-rstc";
>> +compatible = "atmel,sama5d3-rstc";
>> reg = <0xfe00 0x10>;
>> };
>>
>> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
>> index 3ee22ee..481196c 100644
>> --- a/arch/arm/boot/dts/sama5d4.dtsi
>> +++ b/arch/arm/boot/dts/sama5d4.dtsi
>> @@ -1277,7 +1277,7 @@
>> };
>>
>> rstc@fc068600 {
>> -compatible = "atmel,at91sam9g45-rstc";
>> +compatible = "atmel,sama5d3-rstc";
>> reg = <0xfc068600 0x10>;
>> };
>>
>>
>
>
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Re: [PATCH v1 1/2] dt: atmel-usart: document new I/O data register width property
Le 30/07/2015 15:06, Andy Shevchenko a écrit : > This change documents a new property for the Atmel serial device, allowing an > implementer to specify either four bytes or one byte access to the controller > data register. > > This supports a change that unbreaks this driver on ATNGW100 board. > > Signed-off-by: Andy Shevchenko > --- > Documentation/devicetree/bindings/serial/atmel-usart.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt > b/Documentation/devicetree/bindings/serial/atmel-usart.txt > index e6e6142..a8c290a7 100644 > --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt > +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt > @@ -6,6 +6,8 @@ Required properties: >additional mode or an USART new feature. >For the dbgu UART, use "atmel,-dbgu", "atmel,-usart" > - reg: Should contain registers location and length > +- reg-io-width: The I/O register width (in bytes) implemented by > + this device. Supported values are 1 or 4 (the default). Well, sorry but no. The proper way to implement this is to cling to certain compatible strings. But I'm pretty sure that this issue shall not be fixed like this. But I think that Cyrille is about to propose another version. Let's wait for his code... Bye, > - interrupts: Should contain interrupt > - clock-names: tuple listing input clock names. > Required elements: "usart" > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] ARM: at91: dts: add isi & ov2640 dt nodes for at91sam9m10g45ek board
Le 18/06/2015 17:45, Alexandre Belloni a écrit : > Hi, > > Seems good to me, a small comment below: > > On 16/06/2015 at 18:08:34 +0800, Josh Wu wrote : >> @@ -1068,8 +1076,12 @@ >> clocks = <&isi_clk>; >> clock-names = "isi_clk"; >> pinctrl-names = "default"; >> -pinctrl-0 = <&pinctrl_isi>; >> +pinctrl-0 = <&pinctrl_isi_data_0_7>; > > I would say that the pinctrl is board specific so both pinctrl-names and > pinctrl-0 should go to at91sam9m10g45ek.dts I move it in the board file. Otherwise: Acked-by: Nicolas Ferre and stacked on top of at91-4.3-dt. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] power: reset: at91: add sama5d3 reset function
Le 20/07/2015 18:42, Sebastian Reichel a écrit : > Hi, > > On Mon, Jul 20, 2015 at 05:32:05PM +0800, Josh Wu wrote: >> This patch introduces a new compatible string: "atmel,sama5d3-rstc" and >> new reset function for sama5d3 and later chips. >> >> As in sama5d3 or later chips, we don't have to shutdown the DDR >> controller before reset. Shutdown the DDR controller before reset is a >> workaround to avoid DDR signal driving the bus, but since sama5d3 and >> later chips there is no such a conflict. >> >> So in this patch: >>1. the sama5d3 reset function only need to write the rstc register >> and return. >>2. we can remove the code related with sama5d3 DDR controller as >> we don't use it at all. >> >> Signed-off-by: Josh Wu >> Acked-by: Nicolas Ferre > > queued. Sebastian, As my Device Tree changes depend on this modification, we can synchronize in tree ways: 1/ you provide me a stable branch so that I can pull it before applying my changes that can go through arm-soc. 2/ you let me take the driver's modifications with me and the two patches of the series would go through arm-soc. 3/ you take the second patch of my series with my Acked-by tag and carry both of them up to Linus' tree. Please tell me your preference. Thanks, bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFCv2 2/3] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
Le 28/07/2015 07:03, Moritz Fischer a écrit : > Hi Michal, > > I agree we need to be careful with changing the bindings. > > On Sun, Jul 26, 2015 at 11:56 PM, Michal Simek wrote: >> Hi Moritz, >> >> On 07/25/2015 02:21 AM, Moritz Fischer wrote: >>> Signed-off-by: Moritz Fischer >>> --- >>> arch/arm/boot/dts/zynq-7000.dtsi| 43 - >> >> This patch is nice in general but every change in binding should be >> discussed separately. There is also necessary to wire them up in the >> driver to do action. That's why I think that will be the best just to >> add the code to slcr and keep others untouched. > > Ok, just to clarify: You'd suggest to just add the rstc as child node > to the slcr, > and leave the other nodes untouched? > >> >> For example MACB/GEM is one example. Adding names to this node and >> extending driver to work properly with reset means that all others MACB >> users will be affected. Definitely this patch should be ACKed by Nicolas. Actually, I don't know why a reset property should be added to the macb driver... Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 2/2] mfd: atmel-flexcom: add a driver for Atmel Flexible Serial Communication Unit
*pdev)
>> +{
>> +struct device_node *child, *np = pdev->dev.of_node;
>> +struct clk *clk;
>> +struct resource *res;
>> +void __iomem *base;
>> +u32 opmode;
>> +int err;
>> +
>> +child = of_get_next_available_child(np, NULL);
>> +if (!child)
>> +return -ENODEV;
>> +
>> +/*
>> + * The Operating Mode is stored into the first u32 of the reg property
>> + * of the child.
>> + */
>> +err = of_property_read_u32_index(child, "reg", 0, &opmode);
>> +of_node_put(child);
>
> Don't think you need to of_node_put() after a u32 read.
Well, it's after an of_get_next_available_child() which is similar to
of_get_next_child(). It is said to release the node by calling
of_node_put()... So I suspect it's necessary.
Bye,
>
>> +if (err)
>> +return -EINVAL;
>
> Why are you making up your own return value.
>
> Just return err.
>
>> +if ((opmode == FLEX_MR_OPMODE_NO_COM) ||
>> +(opmode & ~FLEX_MR_OPMODE_MASK))
>> +return -EINVAL;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +base = devm_ioremap_resource(&pdev->dev, res);
>> +if (IS_ERR(base))
>> +return PTR_ERR(base);
>> +
>> +clk = devm_clk_get(&pdev->dev, NULL);
>> +if (IS_ERR(clk))
>> +return PTR_ERR(clk);
>> +
>> +err = clk_prepare_enable(clk);
>> +if (err)
>> +return err;
>> +
>> +/*
>> + * Set the Operating Mode in the Mode Register: only the selected device
>> + * is clocked. Hence, registers of the other serial devices remain
>> + * inaccessible and are read as zero. Also the external I/O lines of the
>> + * Flexcom are muxed to reach the selected device.
>> + */
>> +writel(opmode, base + FLEX_MR);
>> +
>> +clk_disable_unprepare(clk);
>> +
>> +return of_platform_populate(np, NULL, NULL, &pdev->dev);
>> +}
>> +
>> +static const struct of_device_id atmel_flexcom_of_match[] = {
>> +{ .compatible = "atmel,sama5d2-flexcom" },
>> +{ /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);
>> +
>> +static struct platform_driver atmel_flexcom_driver = {
>> +.probe = atmel_flexcom_probe,
>> +.driver = {
>> +.name = "atmel_flexcom",
>> +.of_match_table = atmel_flexcom_of_match,
>> +},
>> +};
>> +
>> +module_platform_driver(atmel_flexcom_driver);
>> +
>> +MODULE_AUTHOR("Cyrille Pitchen ");
>> +MODULE_DESCRIPTION("Atmel Flexcom MFD driver");
>> +MODULE_LICENSE("GPL v2");
>
--
Nicolas Ferre
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Re: [PATCH v7 2/2] mfd: atmel-flexcom: add a driver for Atmel Flexible Serial Communication Unit
Le 23/07/2015 18:42, Cyrille Pitchen a écrit :
> This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
> integrates one SPI controller, one I2C controller and one USART. Only one
> function can be enabled at a time. This driver selects the function once
> for all, when the Flexcom is probed, using the "reg" property of the first
> (should be unique) available DT child node.
>
> This driver has chosen to present the Flexcom to the system as a MFD so
> the implementation is seamless for the existing Atmel SPI, I2C and USART
> drivers.
>
> Also the Flexcom embeds FIFOs: the latest patches of the SPI, I2C and
> USART drivers take advantage of this new feature.
Acked-by: Nicolas Ferre
Thank you.
Bye,
> Signed-off-by: Cyrille Pitchen
> ---
> drivers/mfd/Kconfig | 11 +
> drivers/mfd/Makefile| 1 +
> drivers/mfd/atmel-flexcom.c | 113
>
> 3 files changed, 125 insertions(+)
> create mode 100644 drivers/mfd/atmel-flexcom.c
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 653815950aa2..2c75472c679c 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -60,6 +60,17 @@ config MFD_AAT2870_CORE
> additional drivers must be enabled in order to use the
> functionality of the device.
>
> +config MFD_ATMEL_FLEXCOM
> + tristate "Atmel Flexcom (Flexible Serial Communication Unit)"
> + select MFD_CORE
> + depends on OF
> + help
> + Select this to get support for Atmel Flexcom. This is a wrapper
> + which embeds a SPI controller, a I2C controller and a USART. Only
> + one function can be used at a time. The choice is done at boot time
> + by the probe function of this MFD driver according to a device tree
> + property.
> +
> config MFD_ATMEL_HLCDC
> tristate "Atmel HLCDC (High-end LCD Controller)"
> select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index ea40e076cb61..0705eb2d873d 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -160,6 +160,7 @@ obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o
> obj-$(CONFIG_TPS65911_COMPARATOR)+= tps65911-comparator.o
> obj-$(CONFIG_MFD_TPS65090) += tps65090.o
> obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
> +obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o
> obj-$(CONFIG_MFD_ATMEL_HLCDC)+= atmel-hlcdc.o
> obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
> obj-$(CONFIG_MFD_PALMAS) += palmas.o
> diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c
> new file mode 100644
> index ..0d06b70696b0
> --- /dev/null
> +++ b/drivers/mfd/atmel-flexcom.c
> @@ -0,0 +1,113 @@
> +/*
> + * Driver for Atmel Flexcom
> + *
> + * Copyright (C) 2015 Atmel Corporation
> + *
> + * Author: Cyrille Pitchen
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* I/O register offsets */
> +#define FLEX_MR 0x0 /* Mode Register */
> +#define FLEX_VERSION 0xfc/* Version Register */
> +
> +/* Mode Register bit fields */
> +#define FLEX_MR_OPMODE_MASK 0x3
> +#define FLEX_MR_OPMODE_NO_COM0x0
> +#define FLEX_MR_OPMODE_USART 0x1
> +#define FLEX_MR_OPMODE_SPI 0x2
> +#define FLEX_MR_OPMODE_TWI 0x3
> +
> +
> +static int atmel_flexcom_probe(struct platform_device *pdev)
> +{
> + struct device_node *child, *np = pdev->dev.of_node;
> + struct clk *clk;
> + struct resource *res;
> + void __iomem *base;
> + u32 opmode;
> + int err;
> +
> + child = of_get_next_available_child(np, NULL);
> + if (!child)
> + return -ENODEV;
> +
> + /*
> + * The Operating Mode is stored into the first u32 of the reg property
> + * of the child.
> + */
> + err = of_property_read_u32_index(child, "reg", 0, &opmode);
> +
Re: [PATCH v7 1/2] mfd: devicetree: add bindings for Atmel Flexcom
Le 23/07/2015 21:48, Boris Brezillon a écrit :
> On Thu, 23 Jul 2015 18:42:55 +0200
> Cyrille Pitchen wrote:
>
>> This patch documents the DT bindings for the Atmel Flexcom which will be
>> introduced by sama5d2x SoCs. These bindings will be used by the actual
>> Flexcom driver to be sent in another patch.
>>
>> Signed-off-by: Cyrille Pitchen
>> ---
>> .../devicetree/bindings/mfd/atmel-flexcom.txt | 68
>> ++
>> 1 file changed, 68 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
>> b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
>> new file mode 100644
>> index ..a63226b7a9cb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
>> @@ -0,0 +1,68 @@
>> +* Device tree bindings for Atmel Flexcom (Flexible Serial Communication
>> Unit)
>> +
>> +The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
>> +controller and an USART. Only one function can be used at a time and is
>> chosen
>> +at boot time according to the device tree.
>> +
>> +Required properties:
>> +- compatible: Should be "atmel,sama5d2-flexcom"
>> +- reg: Should be the pair (offset, size) for the
>> Flexcom
>> +dedicated I/O registers (without USART, TWI or SPI
>> +registers).
>> +- clocks: Should be the Flexcom peripheral clock from PMC.
>> +- #address-cells: Should be <2>
>> +- #size-cells: Should be <1>
>> +- ranges: Should be a list of ranges.
>> +One range per peripheral wrapped by the Flexcom. So each
>> +range is a triplet (child_addr, parent_addr, size). The
>> +first u32 of "child_addr" is the value to be set in the
>> +Operating Mode bitfield of the Flexcom Mode Register.
>> +Then "parent_addr" stores the base address of the
>> +corresponding peripheral in the system memory. Finally,
>> +"size" if the size of the memory region of this
>> +peripheral.
>> +
>> +Required child:
>> +A single available child for the serial controller to enable.
>> +
>> +Required properties of this child:
>> +- reg: Should be a pair (child_addr, size) with
>> child_addr
>> +matching one of the parent ranges.
>> +- clocks: Should be the very same phandle as for the parent's one.
>> +
>> +Other properties remain unchanged. See documentation of the respective
>> device:
>> +- ../serial/atmel-usart.txt
>> +- ../spi/spi_atmel.txt
>> +- ../i2c/i2c-at91.txt
>> +
>> +Example:
>> +
>> +flexcom@f8034000 {
>> +compatible = "atmel,sama5d2-flexcom";
>> +reg = <0xf8034000 0x200>;
>> +clocks = <&flx0_clk>;
>> +#address-cells = <2>;
>> +#size-cells = <1>;
>> +ranges = <1 0 0xf8034200 0x200 /* opmode 1: USART */
>> + 2 0 0xf8034400 0x200 /* opmode 2: SPI */
>> + 3 0 0xf8034600 0x200>;/* opmode 3: I2C */
Yes, the opmode(s) are exactly the values described in the product
datasheet.
>> +
>> +spi@f8034400 {
>
> Should be:
>
> spi@2,0 {
Yep!
I was silently following the discussion in the background and I admit
that this approach is pretty elegant.
So, if this approach is validated you can also add my:
Acked-by: Nicolas Ferre
>> +compatible = "atmel,at91rm9200-spi";
>> +reg = <2 0 0x200>;
>> +interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
>> +pinctrl-names = "default";
>> +pinctrl-0 = <&pinctrl_flx0_default>;
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +clocks = <&flx0_clk>;
>> +clock-names = "spi_clk";
>> +atmel,fifo-size = <32>;
>> +
>> +mtd_dataflash@0 {
>> +compatible = "atmel,at25f512b";
>> +reg = <0>;
>> +spi-max-frequency = <2000>;
>> +};
>> +};
>> +};
>
>
>
--
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Re: [NET-NEXT PATCH] net: macb: Change capability mask for jumbo support
Le 23/07/2015 12:14, Harini Katakam a écrit : > JUMBO and NO_GIGABIT_HALF have the same capability masks. > Change one of them. > > Signed-off-by: Harini Katakam Yes, indeed: Acked-by: Nicolas Ferre > --- > drivers/net/ethernet/cadence/macb.h |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/cadence/macb.h > b/drivers/net/ethernet/cadence/macb.h > index d746559..8fb80b2 100644 > --- a/drivers/net/ethernet/cadence/macb.h > +++ b/drivers/net/ethernet/cadence/macb.h > @@ -399,7 +399,7 @@ > #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000 > #define MACB_CAPS_SG_DISABLED0x4000 > #define MACB_CAPS_MACB_IS_GEM0x8000 > -#define MACB_CAPS_JUMBO 0x0008 > +#define MACB_CAPS_JUMBO 0x0010 > > /* Bit manipulation macros */ > #define MACB_BIT(name) \ > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] ARM: at91: sama5/dt: update rstc to correct compatible string
Le 20/07/2015 11:32, Josh Wu a écrit :
> They'll use "atmel,sama5d3-rstc" for reset function.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Josh Wu
Acked-by: Nicolas Ferre
And we'll have to synchronize with the other patches. The best way to
deal with that can be to take both of them with us through arm-soc.
Sebastian,
1/ as you weren't in the CC list of the original patch, do you want me
to re-send the whole series?
2/ can we take these driver's changes with use through the arm-soc git
tree so that we can manage the synchronization better?
Thanks, bye,
> ---
>
> Changes in v2: None
>
> arch/arm/boot/dts/sama5d3.dtsi | 2 +-
> arch/arm/boot/dts/sama5d4.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
> index 9e2444b..280255b 100644
> --- a/arch/arm/boot/dts/sama5d3.dtsi
> +++ b/arch/arm/boot/dts/sama5d3.dtsi
> @@ -1259,7 +1259,7 @@
> };
>
> rstc@fe00 {
> - compatible = "atmel,at91sam9g45-rstc";
> + compatible = "atmel,sama5d3-rstc";
> reg = <0xfe00 0x10>;
> };
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 3ee22ee..481196c 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -1277,7 +1277,7 @@
> };
>
> rstc@fc068600 {
> - compatible = "atmel,at91sam9g45-rstc";
> + compatible = "atmel,sama5d3-rstc";
> reg = <0xfc068600 0x10>;
> };
>
>
--
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Re: [PATCH v4 4/5] tty/serial: at91: add support to FIFOs
Le 02/07/2015 15:18, Cyrille Pitchen a écrit :
> Depending on the hardware, TX and RX FIFOs may be available. The RX
> FIFO can avoid receive overruns, especially when DMA transfers are
> not used to read data from the Receive Holding Register. For heavy
> system load, The CPU is likely not be able to fetch data fast enough
> from the RHR.
>
> In addition, the RX FIFO can supersede the DMA/PDC to control the RTS
> line when the Hardware Handshaking mode is enabled. Two thresholds
> are to be set for that purpose:
> - When the number of data in the RX FIFO crosses and becomes lower
> than or equal to the low threshold, the RTS line is set to low
> level: the remote peer is requested to send data.
> - When the number of data in the RX FIFO crosses and becomes greater
> than or equal to the high threshold, the RTS line is set to high
> level: the remote peer should stop sending new data.
> - low threshold <= high threshold
> Once these two thresholds are set properly, this new feature is
> enabled by setting the FIFO RTS Control bit of the FIFO Mode Register.
>
> FIFOs also introduce a new multiple data mode: the USART works either
> in multiple data mode or in single data (legacy) mode.
>
> If MODE9 bit is set into the Mode Register or if USMODE is set to
> either LIN_MASTER, LIN_SLAVE or LON_MODE, FIFOs operate in single
> data mode. Otherwise, they operate in multiple data mode.
>
> In this new multiple data mode, accesses to the Receive Holding
> Register or Transmit Holding Register slightly change.
>
> Since this driver implements neither the 9bit data feature (MODE9 bit
> set into the Mode Register) nor LIN modes, the USART works in
> multiple data mode whenever FIFOs are available and enabled. We also
> assume that data are 8bit wide.
>
> In single data mode, 32bit access CAN be used to read a single data
> from RHR or write a single data into THR.
> However in multiple data mode, a 32bit access to RHR now allows us to
> read four consecutive data from RX FIFO. Also a 32bit access to THR
> now allows to write four consecutive data into TX FIFO. So we MUST
> use 8bit access whenever only one data have to be read/written at a
> time.
>
> Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
Thanks!
> ---
> drivers/tty/serial/atmel_serial.c | 100
> +++---
> include/linux/atmel_serial.h | 36 ++
> 2 files changed, 130 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/tty/serial/atmel_serial.c
> b/drivers/tty/serial/atmel_serial.c
> index e7c337de31d1..87de21f0c7a3 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -56,6 +56,15 @@
> /* Revisit: We should calculate this based on the actual port settings */
> #define PDC_RX_TIMEOUT (3 * 10)/* 3 bytes */
>
> +/* The minium number of data FIFOs should be able to contain */
> +#define ATMEL_MIN_FIFO_SIZE 8
> +/*
> + * These two offsets are substracted from the RX FIFO size to define the RTS
> + * high and low thresholds
> + */
> +#define ATMEL_RTS_HIGH_OFFSET16
> +#define ATMEL_RTS_LOW_OFFSET 20
> +
> #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
> #define SUPPORT_SYSRQ
> #endif
> @@ -141,6 +150,9 @@ struct atmel_uart_port {
> struct mctrl_gpios *gpios;
> int gpio_irq[UART_GPIO_MAX];
> unsigned inttx_done_mask;
> + u32 fifo_size;
> + u32 rts_high;
> + u32 rts_low;
> boolms_irq_enabled;
> boolis_usart; /* usart or uart */
> struct timer_list uart_timer; /* uart timer */
> @@ -191,6 +203,16 @@ static inline void atmel_uart_writel(struct uart_port
> *port, u32 reg, u32 value)
> __raw_writel(value, port->membase + reg);
> }
>
> +static inline u8 atmel_uart_readb(struct uart_port *port, u32 reg)
> +{
> + return __raw_readb(port->membase + reg);
> +}
> +
> +static inline void atmel_uart_writeb(struct uart_port *port, u32 reg, u8
> value)
> +{
> + __raw_writeb(value, port->membase + reg);
> +}
> +
> #ifdef CONFIG_SERIAL_ATMEL_PDC
> static bool atmel_use_pdc_rx(struct uart_port *port)
> {
> @@ -635,7 +657,7 @@ static void atmel_rx_chars(struct uart_port *port)
>
> status = atmel_uart_readl(port, ATMEL_US_CSR);
> while (status & ATMEL_US_RXRDY) {
> - ch = atmel_uart_readl(port, ATMEL_US_RHR);
> + ch = atmel_uart_readb(port, ATMEL_US_RHR);
>
> /*
>
Re: [PATCH v4 3/5] tty/serial: at91: remove bunch of macros to access UART registers
Le 02/07/2015 15:18, Cyrille Pitchen a écrit :
> This patch replaces the UART_PUT_*, resp. UART_GET_*, macros by
> atmel_uart_writel(), resp. atmel_uart_readl(), inline function calls.
>
> Signed-off-by: Cyrille Pitchen
Ok with this move:
Acked-by: Nicolas Ferre
> ---
> drivers/tty/serial/atmel_serial.c | 313
> +++---
> 1 file changed, 159 insertions(+), 154 deletions(-)
>
> diff --git a/drivers/tty/serial/atmel_serial.c
> b/drivers/tty/serial/atmel_serial.c
> index 2a8f528153e7..e7c337de31d1 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -88,37 +88,6 @@ static void atmel_stop_rx(struct uart_port *port);
>
> #define ATMEL_ISR_PASS_LIMIT 256
>
> -/* UART registers. CR is write-only, hence no GET macro */
> -#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
> -#define UART_GET_MR(port)__raw_readl((port)->membase + ATMEL_US_MR)
> -#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
> -#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
> -#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
> -#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
> -#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
> -#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
> -#define UART_PUT_CHAR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_US_THR)
> -#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
> -#define UART_PUT_BRGR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_US_BRGR)
> -#define UART_PUT_RTOR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_US_RTOR)
> -#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase +
> ATMEL_US_TTGR)
> -#define UART_GET_IP_NAME(port) __raw_readl((port)->membase +
> ATMEL_US_NAME)
> -#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase +
> ATMEL_US_VERSION)
> -
> - /* PDC registers */
> -#define UART_PUT_PTCR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_PDC_PTCR)
> -#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
> -
> -#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
> -#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
> -#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
> -#define UART_PUT_RNPR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_PDC_RNPR)
> -#define UART_PUT_RNCR(port,v)__raw_writel(v, (port)->membase +
> ATMEL_PDC_RNCR)
> -
> -#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
> -#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
> -#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
> -
> struct atmel_dma_buffer {
> unsigned char *buf;
> dma_addr_t dma_addr;
> @@ -212,6 +181,16 @@ to_atmel_uart_port(struct uart_port *uart)
> return container_of(uart, struct atmel_uart_port, uart);
> }
>
> +static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
> +{
> + return __raw_readl(port->membase + reg);
> +}
> +
> +static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32
> value)
> +{
> + __raw_writel(value, port->membase + reg);
> +}
> +
> #ifdef CONFIG_SERIAL_ATMEL_PDC
> static bool atmel_use_pdc_rx(struct uart_port *port)
> {
> @@ -257,7 +236,7 @@ static unsigned int atmel_get_lines_status(struct
> uart_port *port)
> struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
> unsigned int status, ret = 0;
>
> - status = UART_GET_CSR(port);
> + status = atmel_uart_readl(port, ATMEL_US_CSR);
>
> mctrl_gpio_get(atmel_port->gpios, &ret);
>
> @@ -304,9 +283,9 @@ static int atmel_config_rs485(struct uart_port *port,
> unsigned int mode;
>
> /* Disable interrupts */
> - UART_PUT_IDR(port, atmel_port->tx_done_mask);
> + atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
>
> - mode = UART_GET_MR(port);
> + mode = atmel_uart_readl(port, ATMEL_US_MR);
>
> /* Resetting serial mode to RS232 (0x0) */
> mode &= ~ATMEL_US_USMODE;
> @@ -316,7 +295,8 @@ static int atmel_config_rs485(struct uart_port *port,
> if (rs485conf->flags & SER_RS485_ENABLED) {
> dev_dbg(port->dev, "Setting UART to RS485\n");
> atmel_po
Re: [RESEND PATCH 1/2] pinctrl: change function behavior for per pin muxing controllers
Le 17/06/2015 17:55, Stephen Warren a écrit : > On 06/17/2015 06:38 AM, Ludovic Desroches wrote: [..] >> I have sent patches months ago trying to improve things by having >> something more flexible. I don't think I introduce too big changes. >> The only answers I got were from people thinking that pinctrl framework >> conception is not good to fit all kind of controllers. I re-sent the >> patch series to gain more expose and have no answer... > > I don't see anything in your description which implies pinctrl isn't > perfectly suitable for your HW. We are not talking about suitability, we are talking about some little changes to the generic part, just to have more accurate information and a little bit more flexibility with our controller. We read the drivers that Stephen pointed out and it seems that it even doesn't use the whole generic part of the pinconf. Moreover, we do think that the statement "one pin" == "one group" leads to a loss of information and ease of use. We are not talking about the use of defines, tables, macros to reach an usable pinctrl: let's say that we have different views. > Note that I'm on vacation for a couple weeks soon, and I don't expect to > follow this conversation during that time. Ultimately, LinusW owns the > pinctrl subsystem, and you need to convince him of any changes. Okay, so we are back at the same situation we had ended up with several months ago: - no agreement on 3 points: 1/ ways to use groups in generic pinctrl 2/ ways to describe a comprehensive configuration in device tree 3/ readability of a sysfs information - no way out on the generic pinctrl little changes that Ludovic proposed as Linus W. never gave his point of view (RFC posts on April the 2nd). Ludovic explained at length our point of view and gave detailed technical arguments. We don't intend to convince you, we just would like the harmless modifications to be integrated. As we preferred to give a chance to the generic pinconf/pinctrl for our use by adding a little bit of flexibility, we are now in a situation where we are nearly obliged to give up this approach and write a new driver without the use of the generic facilities: what a pity! We lost several months of useless work to match what we thought the maintainer would prefer. So Linus, do you confirm that we won't go further with this approach? We are pretty disappointed by the way this interaction with the pinctrl sub-system went. Best regards, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH linux-next v2 4/4] tty/serial: at91: use 32bit writes into TX FIFO when DMA is enabled
sg_dma_address(sg) = phys_addr;
> + sg_dma_len(sg) = part1_len;
> +
> + phys_addr += part1_len;
> + }
> +
> + if (part2_len) {
> + sg = &sgl[sg_len++];
> + sg_dma_address(sg) = phys_addr;
> + sg_dma_len(sg) = part2_len;
> + }
> +
> + /*
> + * save tx_len so atmel_complete_tx_dma() will increase
> + * xmit->tail correctly
> + */
> + atmel_port->tx_len = tx_len;
>
> desc = dmaengine_prep_slave_sg(chan,
> -sg,
> -1,
> +sgl,
> +sg_len,
> DMA_MEM_TO_DEV,
> DMA_PREP_INTERRUPT |
> DMA_CTRL_ACK);
> @@ -830,7 +861,7 @@ static void atmel_tx_dma(struct uart_port *port)
> return;
> }
>
> - dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
> + dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
>
> atmel_port->desc_tx = desc;
> desc->callback = atmel_complete_tx_dma;
> @@ -890,7 +921,9 @@ static int atmel_prepare_tx_dma(struct uart_port *port)
> /* Configure the slave DMA */
> memset(&config, 0, sizeof(config));
> config.direction = DMA_MEM_TO_DEV;
> - config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> + config.dst_addr_width = (atmel_port->fifo_size) ?
> + DMA_SLAVE_BUSWIDTH_4_BYTES :
> + DMA_SLAVE_BUSWIDTH_1_BYTE;
> config.dst_addr = port->mapbase + ATMEL_US_THR;
> config.dst_maxburst = 1;
>
> @@ -1823,6 +1856,9 @@ static int atmel_startup(struct uart_port *port)
> ATMEL_US_RXFCLR |
> ATMEL_US_TXFLCLR);
>
> + if (atmel_use_dma_tx(port))
> + txrdym = ATMEL_US_FOUR_DATA;
> +
Ok, I see now why you used a variable for txrdym: no problem to keep it
like you did then.
> fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
> if (atmel_port->rts_high &&
> atmel_port->rts_low)
>
Acked-by: Nicolas Ferre
Thanks!
--
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Re: [PATCH linux-next v2 3/4] tty/serial: at91: add support to FIFOs
FCLR BIT(25) /* Receive FIFO Clear */ > +#define ATMEL_US_TXFLCLRBIT(26) /* Transmit FIFO Lock Clear */ > +#define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */ > +#define ATMEL_US_FIFODISBIT(31) /* FIFO disable */ > > #define ATMEL_US_MR 0x04/* Mode Register */ > #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */ > @@ -124,6 +129,37 @@ > #define ATMEL_US_NER 0x44/* Number of Errors Register */ > #define ATMEL_US_IF 0x4c/* IrDA Filter Register */ > > +#define ATMEL_US_CMPR0x90/* Comparaison Register */ > +#define ATMEL_US_FMR 0xa0/* FIFO Mode Register */ > +#define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready > Mode */ > +#define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready > Mode */ > +#define ATMEL_US_ONE_DATA 0x0 > +#define ATMEL_US_TWO_DATA 0x1 > +#define ATMEL_US_FOUR_DATA 0x2 > +#define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */ > +#define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO > Threshold */ > +#define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO > Threshold */ > +#define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO > Threshold2 */ > + > +#define ATMEL_US_FLR 0xa4/* FIFO Level Register */ > +#define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO > Level */ > +#define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO > Level */ > + > +#define ATMEL_US_FIER0xa8/* FIFO Interrupt Enable > Register */ > +#define ATMEL_US_FIDR0xac/* FIFO Interrupt Disable > Register */ > +#define ATMEL_US_FIMR0xb0/* FIFO Interrupt Mask Register > */ > +#define ATMEL_US_FESR 0xb4/* FIFO Event Status Register */ > +#define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */ > +#define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */ > +#define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag > */ > +#define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */ > +#define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */ > +#define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag > */ > +#define ATMEL_US_TXFPTEFBIT(6) /* Transmit FIFO Pointer Error > Flag */ > +#define ATMEL_US_RXFPTEFBIT(7) /* Receive FIFO Pointer Error > Flag */ > +#define ATMEL_US_TXFLOCKBIT(8) /* Transmit FIFO Lock (FESR > only) */ > +#define ATMEL_US_RXFTHF2BIT(9) /* Receive FIFO Threshold Flag > 2 */ > + > #define ATMEL_US_NAME0xf0/* Ip Name */ > #define ATMEL_US_VERSION 0xfc/* Ip Version */ Otherwise it look good. Thanks, bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH linux-next v2 2/4] tty/serial: at91: fix some macro definitions to fit coding style
Le 11/06/2015 18:20, Cyrille Pitchen a écrit : > This patch updates macro definitions in atmel_serial.h to fit the > 80 column rule. > > Please note that some deprecated comments such as "[AT91SAM9261 only]" > are removed as the corresponding bits also exist in some later chips. > > The patch also fix macro definitions in atmel_serial.c to replace > (port,v) by (port, v). > > Signed-off-by: Cyrille Pitchen Acked-by: Nicolas Ferre > --- > drivers/tty/serial/atmel_serial.c | 52 +- > include/linux/atmel_serial.h | 204 > +++--- > 2 files changed, 128 insertions(+), 128 deletions(-) > > diff --git a/drivers/tty/serial/atmel_serial.c > b/drivers/tty/serial/atmel_serial.c > index 2a8f528..112e74b 100644 > --- a/drivers/tty/serial/atmel_serial.c > +++ b/drivers/tty/serial/atmel_serial.c > @@ -89,35 +89,35 @@ static void atmel_stop_rx(struct uart_port *port); > #define ATMEL_ISR_PASS_LIMIT 256 > > /* UART registers. CR is write-only, hence no GET macro */ > -#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) > -#define UART_GET_MR(port)__raw_readl((port)->membase + ATMEL_US_MR) > -#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) > -#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) > -#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) > -#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) > -#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) > -#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) > -#define UART_PUT_CHAR(port,v)__raw_writel(v, (port)->membase + > ATMEL_US_THR) > -#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) > -#define UART_PUT_BRGR(port,v)__raw_writel(v, (port)->membase + > ATMEL_US_BRGR) > -#define UART_PUT_RTOR(port,v)__raw_writel(v, (port)->membase + > ATMEL_US_RTOR) > -#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_TTGR) > -#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + > ATMEL_US_NAME) > -#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + > ATMEL_US_VERSION) > +#define UART_PUT_CR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_CR) > +#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) > +#define UART_PUT_MR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_MR) > +#define UART_PUT_IER(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_IER) > +#define UART_PUT_IDR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_IDR) > +#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) > +#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) > +#define UART_GET_CHAR(port)__raw_readl((port)->membase + ATMEL_US_RHR) > +#define UART_PUT_CHAR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_THR) > +#define UART_GET_BRGR(port)__raw_readl((port)->membase + ATMEL_US_BRGR) > +#define UART_PUT_BRGR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_BRGR) > +#define UART_PUT_RTOR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_RTOR) > +#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + > ATMEL_US_TTGR) > +#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) > +#define UART_GET_IP_VERS(port) __raw_readl((port)->membase + > ATMEL_US_VERSION) > > /* PDC registers */ > -#define UART_PUT_PTCR(port,v)__raw_writel(v, (port)->membase + > ATMEL_PDC_PTCR) > -#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) > +#define UART_PUT_PTCR(port, v) __raw_writel(v, (port)->membase + > ATMEL_PDC_PTCR) > +#define UART_GET_PTSR(port)__raw_readl((port)->membase + ATMEL_PDC_PTSR) > > -#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) > -#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) > -#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) > -#define UART_PUT_RNPR(port,v)__raw_writel(v, (port)->membase + > ATMEL_PDC_RNPR) > -#define UART_PUT_RNCR(port,v)__raw_writel(v, (port)->membase + > ATMEL_PDC_RNCR) > +#define UART_PUT_RPR(port, v) __raw_writel(v, (port)->membase + > ATMEL_PDC_RPR) > +#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) > +#define UART_PUT_RCR(port, v) __raw_writel(v, (port)->membase + > ATMEL_PDC_RCR) > +#define UART_PUT_RNPR(port, v) __raw_wr
Re: [PATCH linux-next v2 1/4] ARM: at91/dt: add a new DT property to support FIFOs on Atmel USARTs
Le 11/06/2015 18:20, Cyrille Pitchen a écrit : > This patch adds a new DT property, "atmel,fifo-size", to enable and set > the maximum number of data the RX and TX FIFOs can store on FIFO capable > USARTs. > > Please be aware that the VERSION register can not be used to guess the > size of FIFOs. Indeed, for a given hardware version, the USARTs can be > integrated on Atmel SoCs with different FIFO sizes. Also the > "atmel,fifo-size" property is optional as older USARTs don't embed FIFO at > all. > > Besides, the FIFO size can not be read or guessed from other registers: > When designing the FIFO feature, no dedicated registers were added to > store this size. Unsed spaces in the I/O register range are limited and > better reserved for future usages. Instead, the FIFO size of each > peripheral is documented in the programmer datasheet. > > Finally, on a given SoC, there can be several instances of USART with > different FIFO sizes. This explain why we'd rather use a dedicated DT > property than use the "compatible" property. > > Signed-off-by: Cyrille Pitchen Acked-by: Nicolas Ferre > --- > Documentation/devicetree/bindings/serial/atmel-usart.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt > b/Documentation/devicetree/bindings/serial/atmel-usart.txt > index 90787aa..e6e6142 100644 > --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt > +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt > @@ -22,6 +22,8 @@ Optional properties: > memory peripheral interface and USART DMA channel ID, FIFO > configuration. > Refer to dma.txt and atmel-dma.txt for details. > - dma-names: "rx" for RX channel, "tx" for TX channel. > +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for > FIFO > + capable USARTs. > > compatible description: > - at91rm9200: legacy USART support > @@ -57,4 +59,5 @@ Example: > dmas = <&dma0 2 0x3>, > <&dma0 2 0x204>; > dma-names = "tx", "rx"; > + atmel,fifo-size = <32>; > }; > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 4/6] i2c: at91: add support for new alternative command mode
at91_twi_write(dev, AT91_TWI_IADR, internal_address);
> }
>
> - at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
> -| ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
> + is_read = (m_start->flags & I2C_M_RD);
> + if (dev->pdata->has_alt_cmd) {
> + if (m_start->len > 0) {
> + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
> + at91_twi_write(dev, AT91_TWI_ACR,
> +AT91_TWI_ACR_DATAL(m_start->len) |
> +((is_read) ? AT91_TWI_ACR_DIR : 0));
> + use_alt_cmd = true;
> + } else {
> + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
> + }
> + }
> +
> + at91_twi_write(dev, AT91_TWI_MMR,
> +(m_start->addr << 16) |
> +int_addr_flag |
> +((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
>
> dev->buf_len = m_start->len;
> dev->buf = m_start->buf;
> @@ -582,30 +647,35 @@ static struct at91_twi_pdata at91rm9200_config = {
> .clk_max_div = 5,
> .clk_offset = 3,
> .has_unre_flag = true,
> + .has_alt_cmd = false,
> };
>
> static struct at91_twi_pdata at91sam9261_config = {
> .clk_max_div = 5,
> .clk_offset = 4,
> .has_unre_flag = false,
> + .has_alt_cmd = false,
> };
>
> static struct at91_twi_pdata at91sam9260_config = {
> .clk_max_div = 7,
> .clk_offset = 4,
> .has_unre_flag = false,
> + .has_alt_cmd = false,
> };
>
> static struct at91_twi_pdata at91sam9g20_config = {
> .clk_max_div = 7,
> .clk_offset = 4,
> .has_unre_flag = false,
> + .has_alt_cmd = false,
> };
>
> static struct at91_twi_pdata at91sam9g10_config = {
> .clk_max_div = 7,
> .clk_offset = 4,
> .has_unre_flag = false,
> + .has_alt_cmd = false,
> };
>
> static const struct platform_device_id at91_twi_devtypes[] = {
> @@ -634,6 +704,14 @@ static struct at91_twi_pdata at91sam9x5_config = {
> .clk_max_div = 7,
> .clk_offset = 4,
> .has_unre_flag = false,
> + .has_alt_cmd = false,
> +};
> +
> +static struct at91_twi_pdata at91sama5d2_config = {
No, please name it:
"sama5d2_config"
> + .clk_max_div = 7,
> + .clk_offset = 4,
> + .has_unre_flag = true,
> + .has_alt_cmd = true,
> };
>
> static const struct of_device_id atmel_twi_dt_ids[] = {
> @@ -656,6 +734,9 @@ static const struct of_device_id atmel_twi_dt_ids[] = {
> .compatible = "atmel,at91sam9x5-i2c",
> .data = &at91sam9x5_config,
> }, {
> + .compatible = "atmel,at91sama5d2-i2c",
> + .data = &at91sama5d2_config,
Please remove the "at91" for these products and use "atmel,sama5d2-i2c"
Thanks.
> + }, {
> /* sentinel */
> }
> };
>
--
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Re: [PATCH v5 3/6] i2c: at91: update documentation for DT bindings
Le 03/06/2015 18:25, Cyrille Pitchen a écrit :
> add a new value "atmel,at91sama5d2-i2c" for the "compatible" property.
Well, here I would like "atmel,sama5d2-i2c" like any other "SAMA5"
product compatibility string out there...
Aka NAK for me ;-)
> add a new optional property "atmel,fifo-size" to enable FIFO support when
> available.
> add missing optional properties "dmas" and "dma-names".
>
> Signed-off-by: Cyrille Pitchen
> ---
> Documentation/devicetree/bindings/i2c/i2c-at91.txt | 29
> --
> 1 file changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> index 388f0a2..7c04fd9 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
> @@ -2,8 +2,8 @@ I2C for Atmel platforms
>
> Required properties :
> - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
> - "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c",
> "atmel,at91sam9g10-i2c"
> - or "atmel,at91sam9x5-i2c"
> + "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c",
> "atmel,at91sam9g10-i2c",
> + "atmel,at91sam9x5-i2c" or "atmel,at91sama5d2-i2c"
Ditto
> - reg: physical base address of the controller and length of memory mapped
> region.
> - interrupts: interrupt number to the cpu.
> @@ -13,6 +13,9 @@ Required properties :
>
> Optional properties:
> - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to
> 10
> +- dmas: A list of two dma specifiers, one for each entry in dma-names.
> +- dma-names: should contain "tx" and "rx".
> +- atmel,fifo-size: size of the RX and TX FIFOs, if available.
> - Child nodes conforming to i2c bus binding
>
> Examples :
> @@ -32,3 +35,25 @@ i2c0: i2c@fff84000 {
> pagesize = <128>;
> }
> }
> +
> +i2c0: i2c@f8034600 {
> + compatible = "atmel,at91sama5d2-i2c";
Ditto
> + reg = <0xf8034600 0x100>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
> + AT91_XDMAC_DT_PERID(11)>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
> + AT91_XDMAC_DT_PERID(12)>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&flx0>;
> + atmel,fifo-size = <32>;
> +
> + wm8731: wm8731@1a {
> + compatible = "wm8731";
> + reg = <0x1a>;
> + };
> +};
>
--
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Re: [PATCH v3 3/3] spi: atmel: add support to FIFOs
Le 09/06/2015 13:53, Cyrille Pitchen a écrit : > To enable the FIFO feature a "atmel,fifo-size" attribute with a strictly > positive value must be added into the node of the device-tree describing > the spi controller. > > When FIFOs are enabled, the RX one is forced to operate in SINGLE data > mode because this driver configures the spi controller as a master. In > master mode only, the Received Data Register has an additionnal Peripheral > Chip Select field, which prevents us from reading more than a single data > at each register access. > > Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a > 8bit data size is used, only two data by access could be written into the > Transmit Data Register. Indeed the first data has to be written into the > lowest 16 bits whereas the second data has to be written into the highest > 16 bits of the TDR. When DMA transfers are used to send data, we don't > rework the transmit buffer to cope with this hardware limitation: the > additional copies required to prepare a new input buffer suited to both > the DMA controller and the spi controller would waste all the benefit of > the DMA transfer. Instead, the DMA controller is configured to write only > one data at time into the TDR. > > In pio mode, two data are written in the TDR in a single access. > > Signed-off-by: Cyrille Pitchen It's neat: thanks Cyrille: Acked-by: Nicolas Ferre > --- > drivers/spi/spi-atmel.c | 255 > ++-- > 1 file changed, 245 insertions(+), 10 deletions(-) > > diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c > index aa7d202..c9eca34 100644 > --- a/drivers/spi/spi-atmel.c > +++ b/drivers/spi/spi-atmel.c > @@ -41,6 +41,8 @@ > #define SPI_CSR1 0x0034 > #define SPI_CSR2 0x0038 > #define SPI_CSR3 0x003c > +#define SPI_FMR 0x0040 > +#define SPI_FLR 0x0044 > #define SPI_VERSION 0x00fc > #define SPI_RPR 0x0100 > #define SPI_RCR 0x0104 > @@ -62,6 +64,14 @@ > #define SPI_SWRST_SIZE 1 > #define SPI_LASTXFER_OFFSET 24 > #define SPI_LASTXFER_SIZE1 > +#define SPI_TXFCLR_OFFSET16 > +#define SPI_TXFCLR_SIZE 1 > +#define SPI_RXFCLR_OFFSET17 > +#define SPI_RXFCLR_SIZE 1 > +#define SPI_FIFOEN_OFFSET30 > +#define SPI_FIFOEN_SIZE 1 > +#define SPI_FIFODIS_OFFSET 31 > +#define SPI_FIFODIS_SIZE 1 > > /* Bitfields in MR */ > #define SPI_MSTR_OFFSET 0 > @@ -114,6 +124,22 @@ > #define SPI_TXEMPTY_SIZE 1 > #define SPI_SPIENS_OFFSET16 > #define SPI_SPIENS_SIZE 1 > +#define SPI_TXFEF_OFFSET 24 > +#define SPI_TXFEF_SIZE 1 > +#define SPI_TXFFF_OFFSET 25 > +#define SPI_TXFFF_SIZE 1 > +#define SPI_TXFTHF_OFFSET26 > +#define SPI_TXFTHF_SIZE 1 > +#define SPI_RXFEF_OFFSET 27 > +#define SPI_RXFEF_SIZE 1 > +#define SPI_RXFFF_OFFSET 28 > +#define SPI_RXFFF_SIZE 1 > +#define SPI_RXFTHF_OFFSET29 > +#define SPI_RXFTHF_SIZE 1 > +#define SPI_TXFPTEF_OFFSET 30 > +#define SPI_TXFPTEF_SIZE 1 > +#define SPI_RXFPTEF_OFFSET 31 > +#define SPI_RXFPTEF_SIZE 1 > > /* Bitfields in CSR0 */ > #define SPI_CPOL_OFFSET 0 > @@ -157,6 +183,22 @@ > #define SPI_TXTDIS_OFFSET9 > #define SPI_TXTDIS_SIZE 1 > > +/* Bitfields in FMR */ > +#define SPI_TXRDYM_OFFSET0 > +#define SPI_TXRDYM_SIZE 2 > +#define SPI_RXRDYM_OFFSET4 > +#define SPI_RXRDYM_SIZE 2 > +#define SPI_TXFTHRES_OFFSET 16 > +#define SPI_TXFTHRES_SIZE6 > +#define SPI_RXFTHRES_OFFSET 24 > +#define SPI_RXFTHRES_SIZE6 > + > +/* Bitfields in FLR */ > +#define SPI_TXFL_OFFSET
Re: [PATCH v3 2/3] spi: atmel: update DT bindings documentation
Le 09/06/2015 13:53, Cyrille Pitchen a écrit :
> - add new property "atmel,fifo-size"
> - change "cs-gpios" to optional for SPI controller version >= 2.
>
> Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/spi/spi_atmel.txt | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt
> b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> index 4f8184d..fb588b3 100644
> --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
> +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> @@ -4,11 +4,16 @@ Required properties:
> - compatible : should be "atmel,at91rm9200-spi".
> - reg: Address and length of the register set for the device
> - interrupts: Should contain spi interrupt
> -- cs-gpios: chipselects
> +- cs-gpios: chipselects (optional for SPI controller version >= 2 with the
> + Chip Select Active After Transfer feature).
> - clock-names: tuple listing input clock names.
> Required elements: "spi_clk"
> - clocks: phandles to input clocks.
>
> +Optional properties:
> +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for
> FIFO
> + capable SPI controllers.
> +
> Example:
>
> spi1: spi@fffcc000 {
> @@ -20,6 +25,7 @@ spi1: spi@fffcc000 {
> clocks = <&spi1_clk>;
> clock-names = "spi_clk";
> cs-gpios = <&pioB 3 0>;
> + atmel,fifo-size = <32>;
> status = "okay";
>
> mmc-slot@0 {
>
--
Nicolas Ferre
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Re: [PATCH v3 1/3] spi: atmel: add support for the internal chip-select of the spi controller
Le 09/06/2015 13:53, Cyrille Pitchen a écrit :
> This patch relies on the CSAAT (Chip Select Active After Transfer) feature
> introduced by the version 2 of the spi controller. This new mode allows to
> use properly the internal chip-select output pin of the spi controller
> instead of using external gpios. Consequently, the "cs-gpios" device-tree
> property becomes optional.
>
> When the new CSAAT bit is set into the Chip Select Register, the internal
> chip-select output pin remains asserted till both the following conditions
> become true:
> - the LASTXFER bit is set into the Control Register (or the Transmit Data
> Register)
> - the Transmit Data Register and its shift register are empty.
>
> WARNING: if the LASTXFER bit is set into the Control Register then new
> data are written into the Transmit Data Register fast enough to keep its
> shifter not empty, the chip-select output pin remains asserted. Only when
> the shifter becomes empty, the chip-select output pin is unasserted.
>
> When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit
> is ignored in both the Control Register and the Transmit Data Register.
> The internal chip-select output pin remains active as long as the Transmit
> Data Register or its shift register are not empty.
>
> Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
> ---
> drivers/spi/spi-atmel.c | 37 -
> 1 file changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index a2f40b1..aa7d202 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -246,6 +246,7 @@ struct atmel_spi {
>
> booluse_dma;
> booluse_pdc;
> + booluse_cs_gpios;
> /* dmaengine data */
> struct atmel_spi_dmadma;
>
> @@ -321,7 +322,8 @@ static void cs_activate(struct atmel_spi *as, struct
> spi_device *spi)
> }
>
> mr = spi_readl(as, MR);
> - gpio_set_value(asd->npcs_pin, active);
> + if (as->use_cs_gpios)
> + gpio_set_value(asd->npcs_pin, active);
> } else {
> u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
> int i;
> @@ -337,7 +339,7 @@ static void cs_activate(struct atmel_spi *as, struct
> spi_device *spi)
>
> mr = spi_readl(as, MR);
> mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
> - if (spi->chip_select != 0)
> + if (as->use_cs_gpios && spi->chip_select != 0)
> gpio_set_value(asd->npcs_pin, active);
> spi_writel(as, MR, mr);
> }
> @@ -366,7 +368,9 @@ static void cs_deactivate(struct atmel_spi *as, struct
> spi_device *spi)
> asd->npcs_pin, active ? " (low)" : "",
> mr);
>
> - if (atmel_spi_is_v2(as) || spi->chip_select != 0)
> + if (!as->use_cs_gpios)
> + spi_writel(as, CR, SPI_BIT(LASTXFER));
> + else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
> gpio_set_value(asd->npcs_pin, !active);
> }
>
> @@ -996,6 +1000,8 @@ static int atmel_spi_setup(struct spi_device *spi)
> csr |= SPI_BIT(CPOL);
> if (!(spi->mode & SPI_CPHA))
> csr |= SPI_BIT(NCPHA);
> + if (!as->use_cs_gpios)
> + csr |= SPI_BIT(CSAAT);
>
> /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
>*
> @@ -1009,7 +1015,9 @@ static int atmel_spi_setup(struct spi_device *spi)
> /* chipselect must have been muxed as GPIO (e.g. in board setup) */
> npcs_pin = (unsigned long)spi->controller_data;
>
> - if (gpio_is_valid(spi->cs_gpio))
> + if (!as->use_cs_gpios)
> + npcs_pin = spi->chip_select;
> + else if (gpio_is_valid(spi->cs_gpio))
> npcs_pin = spi->cs_gpio;
>
> asd = spi->controller_state;
> @@ -1018,15 +1026,19 @@ static int atmel_spi_setup(struct spi_device *spi)
> if (!asd)
> return -ENOMEM;
>
> - ret = gpio_request(npcs_pin, dev_name(&spi->dev));
> - if (ret) {
> - kfree(asd);
> - return ret;
> + if (as->use_cs_gpios) {
> + ret = gpio_request(npcs_pin, dev_name(&spi->dev));
> + if (ret) {
> + kfree(asd);
> +
Re: [PATCH] ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes
Le 08/06/2015 15:55, Ludovic Desroches a écrit :
> The xdmac channel configuration is done in one cell not two. This error
> prevents from probing devices correctly.
>
> Signed-off-by: Ludovic Desroches
> Fixes: 83906783b766 ("ARM: at91/dt: sama5d4: add aes, sha and tdes nodes")
> Cc: sta...@vger.kernel.org # 4.1
Acked-by: Nicolas Ferre
Arnd, Olof, Kevin,
This patch is a fix concerning material that had been added to 4.1, so
it's not exactly a regression.
So, as we missed the last train to 4.1, I'd like to queue it for 4.2 but
it's the only patch I have on top of my previous DT pull-request
(at91-dt4, not taken by you, yet).
So, should I build another pull-request (at91-dt5) or can you take this
single patch when you pull the at91-dt4 material?
BTW, here is the link to patchwork if it's easier:
https://patchwork.kernel.org/patch/6565591/
Thanks, bye,
> ---
> arch/arm/boot/dts/sama5d4.dtsi | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 6b1bb58..51ddec4 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -1125,10 +1125,10 @@
> compatible = "atmel,at91sam9g46-aes";
> reg = <0xfc044000 0x100>;
> interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1))
> - AT91_XDMAC_DT_PERID(41)>,
> -<&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1))
> - AT91_XDMAC_DT_PERID(40)>;
> + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(41))>,
> +<&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(40))>;
> dma-names = "tx", "rx";
> clocks = <&aes_clk>;
> clock-names = "aes_clk";
> @@ -1139,10 +1139,10 @@
> compatible = "atmel,at91sam9g46-tdes";
> reg = <0xfc04c000 0x100>;
> interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
> - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1))
> - AT91_XDMAC_DT_PERID(42)>,
> -<&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1))
> - AT91_XDMAC_DT_PERID(43)>;
> + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(42))>,
> +<&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(43))>;
> dma-names = "tx", "rx";
> clocks = <&tdes_clk>;
> clock-names = "tdes_clk";
> @@ -1153,8 +1153,8 @@
> compatible = "atmel,at91sam9g46-sha";
> reg = <0xfc05 0x100>;
> interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
> - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1))
> - AT91_XDMAC_DT_PERID(44)>;
> + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1)
> + | AT91_XDMAC_DT_PERID(44))>;
> dma-names = "tx";
> clocks = <&sha_clk>;
> clock-names = "sha_clk";
>
--
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Re: [PATCH v2 3/3] spi: atmel: add support to FIFOs
)xfer->rx_buf + offset);
> + u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
> + u16 rd; /* RD field is the lowest 16 bits of RDR */
> +
> + if (xfer->bits_per_word > 8)
> + as->current_remaining_bytes -= 2 * size;
> + else
> + as->current_remaining_bytes -= size;
Yes, the operation is in data, not bytes => okay.
> +
> + while (size) {
> + rd = spi_readl(as, RDR);
> + if (xfer->rx_buf) {
> + if (xfer->bits_per_word > 8)
> + *words++ = rd;
> + else
> + *bytes++ = rd;
> + }
> + size--;
> + }
> +}
> +
> +/* Called from IRQ
> + *
> + * Must update "current_remaining_bytes" to keep track of data
> + * to transfer.
> + */
> +static void
> +atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
> +{
> + if (as->fifo_size)
> + atmel_spi_pump_fifo_data(as, xfer);
> + else
> + atmel_spi_pump_single_data(as, xfer);
> +}
> +
> /* Interrupt
> *
> * No need for locking in this Interrupt handler: done_status is the
> @@ -916,7 +1128,7 @@ atmel_spi_pio_interrupt(int irq, void *dev_id)
>
> complete(&as->xfer_completion);
>
> - } else if (pending & SPI_BIT(RDRF)) {
> + } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
> atmel_spi_lock(as);
>
> if (as->current_remaining_bytes) {
> @@ -1399,6 +1611,13 @@ static int atmel_spi_probe(struct platform_device
> *pdev)
> spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> spi_writel(as, CR, SPI_BIT(SPIEN));
>
> + as->fifo_size = 0;
> + if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
> + &as->fifo_size)) {
> + dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
> + spi_writel(as, CR, SPI_BIT(FIFOEN));
> + }
> +
> /* go! */
> dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
> (unsigned long)regs->start, irq);
>
Otherwise, it looks okay: thanks!
Bye,
--
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Re: [PATCH v2 2/3] spi: atmel: update DT bindings documentation
Le 08/06/2015 18:07, Cyrille Pitchen a écrit :
> - add new property "atmel,fifo-size"
> - change "cs-gpios" to optional for SPI controller version >= 2.
>
> Signed-off-by: Cyrille Pitchen
Acked-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/spi/spi_atmel.txt | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt
> b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> index 4f8184d..7ef7f6bc 100644
> --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
> +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> @@ -4,11 +4,16 @@ Required properties:
> - compatible : should be "atmel,at91rm9200-spi".
> - reg: Address and length of the register set for the device
> - interrupts: Should contain spi interrupt
> -- cs-gpios: chipselects
> +- cs-gpios: chipselects (optional for SPI controller version >= 2 with the
> + Alternative Command Mode).
> - clock-names: tuple listing input clock names.
> Required elements: "spi_clk"
> - clocks: phandles to input clocks.
>
> +Optional properties:
> +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for
> FIFO
> + capable SPI controllers.
> +
> Example:
>
> spi1: spi@fffcc000 {
> @@ -20,6 +25,7 @@ spi1: spi@fffcc000 {
> clocks = <&spi1_clk>;
> clock-names = "spi_clk";
> cs-gpios = <&pioB 3 0>;
> + atmel,fifo-size = <32>;
> status = "okay";
>
> mmc-slot@0 {
>
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Re: [PATCH v2 1/3] spi: atmel: add support for the internal chip-select of the spi controller
Le 08/06/2015 18:07, Cyrille Pitchen a écrit :
> This patch relies on the CSAAT (Chip Select Active After Transfer) feature
> introduced by the version 2 of the spi controller. This new mode allows to
> use properly the internal chip-select output pin of the spi controller
> instead of using external gpios. Consequently, the "cs-gpios" device-tree
> property becomes optional.
>
> When the new CSAAT bit is set into the Chip Select Register, the internal
> chip-select output pin remains asserted till both the following conditions
> become true:
> - the LASTXFER bit is set into the Control Register (or the Transmit Data
> Register)
> - the Transmit Data Register and its shift register are empty.
>
> WARNING: if the LASTXFER bit is set into the Control Register then new
> data are written into the Transmit Data Register fast enough to keep its
> shifter not empty, the chip-select output pin remains asserted. Only when
> the shifter becomes empty, the chip-select output pin is unasserted.
>
> When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit
> is ignored in both the Control Register and the Transmit Data Register.
> The internal chip-select output pin remains active as long as the Transmit
> Data Register or its shift register are not empty.
>
> Signed-off-by: Cyrille Pitchen
It seems okay:
Acked-by: Nicolas Ferre
Thanks.
Some additional changes might be needed: see below...
> ---
> drivers/spi/spi-atmel.c | 37 -
> 1 file changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index a2f40b1..aa7d202 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -246,6 +246,7 @@ struct atmel_spi {
>
> booluse_dma;
> booluse_pdc;
> + booluse_cs_gpios;
> /* dmaengine data */
> struct atmel_spi_dmadma;
>
> @@ -321,7 +322,8 @@ static void cs_activate(struct atmel_spi *as, struct
> spi_device *spi)
> }
>
> mr = spi_readl(as, MR);
> - gpio_set_value(asd->npcs_pin, active);
> + if (as->use_cs_gpios)
> + gpio_set_value(asd->npcs_pin, active);
> } else {
> u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
> int i;
> @@ -337,7 +339,7 @@ static void cs_activate(struct atmel_spi *as, struct
> spi_device *spi)
>
> mr = spi_readl(as, MR);
> mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
> - if (spi->chip_select != 0)
> + if (as->use_cs_gpios && spi->chip_select != 0)
> gpio_set_value(asd->npcs_pin, active);
> spi_writel(as, MR, mr);
> }
Maybe in a debug function in cs_activate()...
> @@ -366,7 +368,9 @@ static void cs_deactivate(struct atmel_spi *as, struct
> spi_device *spi)
> asd->npcs_pin, active ? " (low)" : "",
> mr);
>
> - if (atmel_spi_is_v2(as) || spi->chip_select != 0)
> + if (!as->use_cs_gpios)
> + spi_writel(as, CR, SPI_BIT(LASTXFER));
> + else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
> gpio_set_value(asd->npcs_pin, !active);
> }
>
... as well as in cs_deactivate(), you need to change the use of
asd->npcs_pin:
dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
asd->npcs_pin, active ? " (high)" : "",
mr);
so that it is still relevant in the !as->use_cs_gpios case...
Bye,
> @@ -996,6 +1000,8 @@ static int atmel_spi_setup(struct spi_device *spi)
> csr |= SPI_BIT(CPOL);
> if (!(spi->mode & SPI_CPHA))
> csr |= SPI_BIT(NCPHA);
> + if (!as->use_cs_gpios)
> + csr |= SPI_BIT(CSAAT);
>
> /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
>*
> @@ -1009,7 +1015,9 @@ static int atmel_spi_setup(struct spi_device *spi)
> /* chipselect must have been muxed as GPIO (e.g. in board setup) */
> npcs_pin = (unsigned long)spi->controller_data;
>
> - if (gpio_is_valid(spi->cs_gpio))
> + if (!as->use_cs_gpios)
> + npcs_pin = spi->chip_select;
> + else if (gpio_is_valid(spi->cs_gpio))
> npcs_pin = spi->cs_gpio;
>
> asd = spi->controller_state;
> @@ -1018,15 +1026,19 @@ static int atmel_spi_setup(struct spi_device *spi)
> if (
Re: [PATCH] ARM: at91: dt: sama5d4ek: mci0 uses slot 0
Le 28/05/2015 11:55, Ludovic Desroches a écrit :
> mci0 uses slot 0 not 1.
>
> Signed-off-by: Ludovic Desroches
> Fixes: 7a4752677c44 ("ARM: at91: dt: add device tree file for SAMA5D4ek
> board")
Yes:
Acked-by: Nicolas Ferre
Queued in at91-4.2-dt.
Thanks, bye.
> ---
> arch/arm/boot/dts/at91-sama5d4ek.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts
> b/arch/arm/boot/dts/at91-sama5d4ek.dts
> index 89ef4a5..45e7761 100644
> --- a/arch/arm/boot/dts/at91-sama5d4ek.dts
> +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
> @@ -108,8 +108,8 @@
> mmc0: mmc@f800 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
> &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
> - slot@1 {
> - reg = <1>;
> + slot@0 {
> + reg = <0>;
> bus-width = <4>;
> cd-gpios = <&pioE 5 0>;
> };
>
--
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Re: [PATCH 0/2] get pinctrl more flexible for per pin muxing controllers
Le 04/05/2015 10:56, Ludovic Desroches a écrit : > Hi, > > The way pins, groups and functions are tied is too constraining for some > controllers. It concerns mainly the ones we don't care about groups and > functions, each pin can be muxed to any functions. > The goal of these two patches is too remove some of the constraints. > > I have added the prototype of a pin controller and device tree to show the > way I want to use these changes. I couldn't test it on boards using generic > pinconf so I am not sure that I don't break something... > > > Ludovic Desroches (4): > pinctrl: change function behavior for per pin muxing controllers > pinctrl: introduce complex pin description Linus, Ludovic sent this series nearly one month ago. It was posted after a RFC series on the same topic two months ago. As we don't see any comment on neither of them we assume that it's okay to include them. So, is it possible for you to merge these 2 patches in pinmux/pinconf-generic? The driver making use of this work, which was marked a "PROTO" in the series sent by Ludovic, is being finalized and sent: it would be good to have it working early. Best regards, > pinctrl: rough draft for a future controller > ARM: at91/dt: proto dt > > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/at91-sama5d4ek_proto.dts | 243 ++ > arch/arm/boot/dts/sama5d4_proto-pinfunc.h | 463 +++ > arch/arm/boot/dts/sama5d4_proto.dtsi | 716 > + > drivers/pinctrl/Kconfig| 10 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/pinconf-generic.c | 44 +- > drivers/pinctrl/pinctrl-at91-pio4.c| 625 + > drivers/pinctrl/pinmux.c | 58 +-- > include/linux/pinctrl/pinctrl.h| 6 + > include/linux/pinctrl/pinmux.h | 3 + > 11 files changed, 2134 insertions(+), 36 deletions(-) > create mode 100644 arch/arm/boot/dts/at91-sama5d4ek_proto.dts > create mode 100644 arch/arm/boot/dts/sama5d4_proto-pinfunc.h > create mode 100644 arch/arm/boot/dts/sama5d4_proto.dtsi > create mode 100644 drivers/pinctrl/pinctrl-at91-pio4.c > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] USB: atmel: rework clock handling
Le 17/03/2015 17:15, Boris Brezillon a écrit : > Hello, > > This series reworks clock handling in atmel USB host drivers, and while > doing so fixes a regression introduced by 3440ef1 (ARM: at91/dt: fix USB > high-speed clock to select UTMI). > > Best Regards, > > Boris > > Boris Brezillon (5): > USB: ehci-atmel: rework clk handling > USB: host: ohci-at91: remove useless uclk clock Now that these ones are in Linus' tree... ...these patches vvv > USB: atmel: update DT bindings documentation > ARM: at91/dt: remove useless uhpck clock references from ehci > defintions > ARM: at91/dt: remove useless usb clock ^ can be queued in at91-4.2-dt. They will go through the arm-soc route. And BTW: Acked-by: Nicolas Ferre Thanks Boris, bye. > .../devicetree/bindings/usb/atmel-usb.txt | 25 ++ > arch/arm/boot/dts/at91rm9200.dtsi | 4 +-- > arch/arm/boot/dts/at91sam9260.dtsi | 4 +-- > arch/arm/boot/dts/at91sam9261.dtsi | 4 +-- > arch/arm/boot/dts/at91sam9263.dtsi | 4 +-- > arch/arm/boot/dts/at91sam9g45.dtsi | 8 +++--- > arch/arm/boot/dts/at91sam9n12.dtsi | 5 ++-- > arch/arm/boot/dts/at91sam9x5.dtsi | 8 +++--- > arch/arm/boot/dts/sama5d3.dtsi | 9 +++ > arch/arm/boot/dts/sama5d4.dtsi | 9 +++ > drivers/usb/host/ehci-atmel.c | 30 > +++--- > drivers/usb/host/ohci-at91.c | 18 +++-- > 12 files changed, 63 insertions(+), 65 deletions(-) > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: at91: sama5/dts: reduce the NFC command register map
Le 02/04/2015 08:17, Josh Wu a écrit :
> commit 111573ccd89b ("mtd: atmel_nand: check NFC busy flag by HSMC_SR
> instead of NFC cmd regs")
As this commit is not in Linus' tree yet, we can't point to its commit ID.
> check NFC busy by nfc SR instead of NFC cmd regs. So we don't need to
> map NFC cmd registers to include NFCBUSY bit.
> That means we only need map 0x0800 instead of 0x1000 for NFC
> cmd regs.
>
> This patch reduce the NFC cmd regs map for sama5d3 & sama5d4.
>
> Signed-off-by: Josh Wu
Otherwise:
Acked-by: Nicolas Ferre
I'll modify the commit message to adapt the commit ID and send it when
the patch is merged (probably after 4.0-rc1).
Thanks, best regards,
> ---
> This patch is based on linux-next git repo.
>
> arch/arm/boot/dts/sama5d3.dtsi | 2 +-
> arch/arm/boot/dts/sama5d4.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
> index 261311b..5b2c235 100644
> --- a/arch/arm/boot/dts/sama5d3.dtsi
> +++ b/arch/arm/boot/dts/sama5d3.dtsi
> @@ -1445,7 +1445,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <
> - 0x7000 0x1000 /* NFC Command
> Registers */
> + 0x7000 0x0800 /* NFC Command
> Registers */
> 0xc000 0x0070 /* NFC HSMC
> regs */
> 0x0020 0x0010 /* NFC SRAM
> banks */
> >;
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index d986b41..87705ad 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -294,7 +294,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <
> - 0x9000 0x1000 /* NFC Command
> Registers */
> + 0x9000 0x0800 /* NFC Command
> Registers */
> 0xfc05c000 0x0070 /* NFC HSMC
> regs */
> 0x0010 0x0010 /* NFC SRAM
> banks */
> >;
>
--
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[PATCH] devicetree: Add vendor prefix for Shelly, Inc.
Signed-off-by: Nicolas Ferre --- Thierry, Here it is ;-) Bye, Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index a9eeaa0c5867..1b0f5b797cd5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -165,6 +165,7 @@ sbs Smart Battery System schindler Schindler seagateSeagate Technology PLC semtechSemtech Corporation +shelly Shelly, Inc. silSilicon Image silabs Silicon Laboratories siliconmitus Silicon Mitus, Inc. -- 2.1.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] devicetree: Add vendor prefix for Foxlink Group
Signed-off-by: Nicolas Ferre --- Thierry, Boris added the support for a Foxlink panel in this commit: 102932b0e474 (drm/panel: add support for Foxlink FL500WVR00-A0T panel). Here is the vendor prefix. Bye, Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1b0f5b797cd5..e9fca088ba1a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -73,6 +73,7 @@ everspin Everspin Technologies, Inc. excito Excito fcsFairchild Semiconductor fireflyFirefly +foxlinkFoxlink Group fslFreescale Semiconductor GEFanucGE Fanuc Intelligent Platforms Embedded Systems, Inc. gefGE Fanuc Intelligent Platforms Embedded Systems, Inc. -- 2.1.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] USB: host: ohci-at91: remove useless uclk clock
Le 17/03/2015 20:02, Alan Stern a écrit : > On Tue, 17 Mar 2015, Boris Brezillon wrote: > >> Now that the system clock driver is forwarding set_rate request to the >> parent clock, we can safely call clk_set_rate on the system clk and get >> rid of the uclk field. >> >> Signed-off-by: Boris Brezillon > > Acked-by: Alan Stern Acked-by: Nicolas Ferre Hi Alan, As I don't have any other "drivers" patch for 4.1, would you mind taking this patch with your tree? I'll take care of the remaining ones dealing with Device Tree: they are independent anyway. Thanks, bye. -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] drm/panel: simple: Add support for Innolux AT043TN24
The Innolux AT043TN24 4.3" WQVGA TFT LCD panel.
This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for
instance).
Signed-off-by: Nicolas Ferre
---
.../bindings/panel/innolux,at043tn24.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 ++
2 files changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/panel/innolux,at043tn24.txt
diff --git a/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt
b/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt
new file mode 100644
index ..4104226b61bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/innolux,at043tn24.txt
@@ -0,0 +1,7 @@
+Innolux AT043TN24 4.3" WQVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,at043tn24"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 6e4a85f50d71..4088f9bd7973 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -663,6 +663,31 @@ static const struct panel_desc hitachi_tx23d38vm0caa = {
},
};
+static const struct drm_display_mode innolux_at043tn24_mode = {
+ .clock = 9000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 2,
+ .hsync_end = 480 + 2 + 41,
+ .htotal = 480 + 2 + 41 + 2,
+ .vdisplay = 272,
+ .vsync_start = 272 + 2,
+ .vsync_end = 272 + 2 + 11,
+ .vtotal = 272 + 2 + 11 + 2,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+static const struct panel_desc innolux_at043tn24 = {
+ .modes = &innolux_at043tn24_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 95,
+ .height = 54,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+};
+
static const struct drm_display_mode innolux_g121i1_l01_mode = {
.clock = 71000,
.hdisplay = 1280,
@@ -872,6 +897,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "hit,tx23d38vm0caa",
.data = &hitachi_tx23d38vm0caa
}, {
+ .compatible = "innolux,at043tn24",
+ .data = &innolux_at043tn24,
+ }, {
.compatible ="innolux,g121i1-l01",
.data = &innolux_g121i1_l01
}, {
--
2.1.3
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[PATCH 1/2] drm/panel: simple: Add support for Shelly SCA07010-BFN-LNN
From: Boris BREZILLON
The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel.
This panel with backlight is found in PDA 7" LCD screen (TM70xx series for
instance).
Signed-off-by: Boris BREZILLON
Signed-off-by: Nicolas Ferre
---
.../bindings/panel/shelly,sca07010-bfn-lnn.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 26 ++
2 files changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt
diff --git
a/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt
b/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt
new file mode 100644
index ..fc1ea9e26c94
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/shelly,sca07010-bfn-lnn.txt
@@ -0,0 +1,7 @@
+Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "shelly,sca07010-bfn-lnn"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 3e9aa628169c..6e4a85f50d71 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -802,6 +802,29 @@ static const struct panel_desc samsung_ltn101nt05 = {
},
};
+static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
+ .clock = 33300,
+ .hdisplay = 800,
+ .hsync_start = 800 + 1,
+ .hsync_end = 800 + 1 + 64,
+ .htotal = 800 + 1 + 64 + 64,
+ .vdisplay = 480,
+ .vsync_start = 480 + 1,
+ .vsync_end = 480 + 1 + 23,
+ .vtotal = 480 + 1 + 23 + 22,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc shelly_sca07010_bfn_lnn = {
+ .modes = &shelly_sca07010_bfn_lnn_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 152,
+ .height = 91,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct of_device_id platform_of_match[] = {
{
.compatible = "auo,b101aw03",
@@ -867,6 +890,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "samsung,ltn101nt05",
.data = &samsung_ltn101nt05,
}, {
+ .compatible = "shelly,sca07010-bfn-lnn",
+ .data = &shelly_sca07010_bfn_lnn,
+ }, {
/* sentinel */
}
};
--
2.1.3
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Re: [PATCH 1/5] USB: ehci-atmel: rework clk handling
Le 17/03/2015 20:01, Alan Stern a écrit :
> On Tue, 17 Mar 2015, Boris Brezillon wrote:
>
>> The EHCI IP only needs the UTMI/UPLL (uclk) and the peripheral (iclk)
>> clocks to work properly. Remove the useless system clock (fclk).
>>
>> Avoid calling set_rate on the fixed rate UTMI/IPLL clock and remove
>> useless IS_ENABLED(CONFIG_COMMON_CLK) tests (all at91 platforms have been
>> moved to the CCF).
>>
>> This patch also fixes a bug introduced by 3440ef1 (ARM: at91/dt: fix USB
>> high-speed clock to select UTMI), which was leaving the usb clock
>> uninitialized and preventing the OHCI driver from setting the usb clock
>> rate to 48MHz.
>> This bug was caused by several things:
>> 1/ usb clock drivers set the CLK_SET_RATE_GATE flag, which means the rate
>>cannot be changed once the clock is prepared
>> 2/ The EHCI driver was retrieving and preparing/enabling the uhpck
>>clock which was in turn preparing its parent clock (the usb clock),
>>thus preventing any rate change because of 1/
>>
>> Signed-off-by: Boris Brezillon
>
> Acked-by: Alan Stern
Acked-by: Nicolas Ferre
and:
Fixes: 3440ef169100 ("ARM: at91/dt: fix USB high-speed clock to select UTMI")
Alan, Greg,
Can you please take this patch (only this patch 1/5 of the series) as a fix
for the 4.0-rc? It would solve the issue that we see on at91sam9x5/at91sam9n12.
I'll take care of the rest of the series for 4.1.
If you want me to take it of to re-send the patch, tell me.
Thanks, bye,
--
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Re: [PATCH v2 1/1] DT: video: atmel_lcdc: Add example of fixed framebuffer memory
Le 05/03/2015 08:35, Alexander Stein a écrit :
> This drivers allows a fixed framebuffer memory to be set by an additional
> IORESOURCE_MEM resource. Thus add an example to the DT documentation.
>
> Signed-off-by: Alexander Stein
> Acked-by: Nicolas Ferre
Queued in at91-4.1-dt. Thanks!
> ---
> Changes in v2:
> * Fix typo noticed by checkpatch.pl
>
> Documentation/devicetree/bindings/video/atmel,lcdc.txt | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> index f059dd0..ecb8da0 100644
> --- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
> @@ -10,7 +10,9 @@ Required properties:
> "atmel,at91sam9g45es-lcdc" ,
> "atmel,at91sam9rl-lcdc" ,
> "atmel,at32ap-lcdc"
> -- reg : Should contain 1 register ranges(address and length)
> +- reg : Should contain 1 register ranges(address and length).
> + Can contain an additional register range(address and length)
> + for fixed framebuffer memory. Useful for dedicated memories.
> - interrupts : framebuffer controller interrupt
> - display: a phandle pointing to the display node
>
> @@ -38,6 +40,14 @@ Example:
>
> };
>
> +Example for fixed framebuffer memory:
> +
> + fb0: fb@0x0050 {
> + compatible = "atmel,at91sam9263-lcdc";
> + reg = <0x0070 0x1000 0x7000 0x20>;
> + [...]
> + };
> +
> Atmel LCDC Display
> -
> Required properties (as per of_videomode_helper):
>
--
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Re: [PATCH v2 1/3] net/macb: Update DT bindings documentation
Le 06/03/2015 11:24, Boris Brezillon a écrit :
> Add missing "cdns,at91sam9260-macb", "atmel,sama5d3-gem" and
> "atmel,sama5d4-gem" compatible strings.
>
> Signed-off-by: Boris Brezillon
> Reviewed-by: Alexandre Belloni
Acked-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/net/macb.txt | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/net/macb.txt
> b/Documentation/devicetree/bindings/net/macb.txt
> index aaa6964..ba19d67 100644
> --- a/Documentation/devicetree/bindings/net/macb.txt
> +++ b/Documentation/devicetree/bindings/net/macb.txt
> @@ -2,10 +2,13 @@
>
> Required properties:
> - compatible: Should be "cdns,[-]{macb|gem}"
> - Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
> + Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
> + available on sama5d3 SoCs.
>Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
> "cdns,macb".
>Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based
> on
>the Cadence GEM, or the generic form: "cdns,gem".
> + Use "cdns,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
> + Use "cdns,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs.
> - reg: Address and length of the register set for the device
> - interrupts: Should contain macb interrupt
> - phy-mode: See ethernet.txt file in the same directory.
>
--
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Re: [PATCH v2 3/3] net: macb: remove #if defined(CONFIG_ARCH_AT91) sections
Le 06/03/2015 11:24, Boris Brezillon a écrit :
> With multi platform support those sections could lead to unexpected
> behavior if both ARCH_AT91 and another ARM SoC using the MACB IP are
> selected.
> Add two new capabilities to encode the default MII mode and the presence
> of a CLKEN bit in USRIO register.
> Then define the appropriate config for IPs embedded in at91 SoCs.
>
> Signed-off-by: Boris Brezillon
> Reviewed-by: Alexandre Belloni
Acked-by: Nicolas Ferre
> ---
> drivers/net/ethernet/cadence/macb.c | 32 +---
> drivers/net/ethernet/cadence/macb.h | 2 ++
> 2 files changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> index ad76b8e..86e915f 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -2113,6 +2113,10 @@ static const struct net_device_ops macb_netdev_ops = {
> };
>
> #if defined(CONFIG_OF)
> +static struct macb_config at91sam9260_config = {
> + .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
> +};
> +
> static struct macb_config pc302gem_config = {
> .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
> .dma_burst_length = 16,
> @@ -2130,7 +2134,7 @@ static struct macb_config sama5d4_config = {
>
> static const struct of_device_id macb_dt_ids[] = {
> { .compatible = "cdns,at32ap7000-macb" },
> - { .compatible = "cdns,at91sam9260-macb" },
> + { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
> { .compatible = "cdns,macb" },
> { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
> { .compatible = "cdns,gem", .data = &pc302gem_config },
> @@ -2388,21 +2392,19 @@ static int macb_probe(struct platform_device *pdev)
> bp->phy_interface = err;
> }
>
> + config = 0;
> if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
> - macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
> - else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
> -#if defined(CONFIG_ARCH_AT91)
> - macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
> -MACB_BIT(CLKEN)));
> -#else
> - macb_or_gem_writel(bp, USRIO, 0);
> -#endif
> - else
> -#if defined(CONFIG_ARCH_AT91)
> - macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
> -#else
> - macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
> -#endif
> + config = GEM_BIT(RGMII);
> + else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
> + (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> + config = MACB_BIT(RMII);
> + else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
> + config = MACB_BIT(MII);
> +
> + if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
> + config |= MACB_BIT(CLKEN);
> +
> + macb_or_gem_writel(bp, USRIO, config);
>
> err = register_netdev(dev);
> if (err) {
> diff --git a/drivers/net/ethernet/cadence/macb.h
> b/drivers/net/ethernet/cadence/macb.h
> index 31dc080..efe0247 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -389,6 +389,8 @@
>
> /* Capability mask bits */
> #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x0001
> +#define MACB_CAPS_USRIO_HAS_CLKEN0x0002
> +#define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x0004
> #define MACB_CAPS_FIFO_MODE 0x1000
> #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x2000
> #define MACB_CAPS_SG_DISABLED0x4000
>
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Re: [PATCH v2 2/3] ARM: at91/dt: fix macb compatible strings
Le 06/03/2015 11:24, Boris Brezillon a écrit :
> Some at91 SoCs embed a 10/100 Mbit Ethernet IP, that is based on the
> at91sam9260 SoC.
> Fix at91 DTs accordingly.
>
> Signed-off-by: Boris Brezillon
> Reviewed-by: Alexandre Belloni
Acked-by: Nicolas Ferre
> ---
> arch/arm/boot/dts/at91sam9260.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9g45.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 2 +-
> arch/arm/boot/dts/sama5d3_emac.dtsi | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi
> b/arch/arm/boot/dts/at91sam9260.dtsi
> index fff0ee6..9f7c737 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -842,7 +842,7 @@
> };
>
> macb0: ethernet@fffc4000 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xfffc4000 0x100>;
> interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi
> b/arch/arm/boot/dts/at91sam9263.dtsi
> index 1f67bb4..340179e 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -845,7 +845,7 @@
> };
>
> macb0: ethernet@fffbc000 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xfffbc000 0x100>;
> interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi
> b/arch/arm/boot/dts/at91sam9g45.dtsi
> index ee80aa9..586eab7 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -956,7 +956,7 @@
> };
>
> macb0: ethernet@fffbc000 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xfffbc000 0x100>;
> interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> index 57e89d1..73d7e30 100644
> --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> @@ -53,7 +53,7 @@
> };
>
> macb0: ethernet@f802c000 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xf802c000 0x100>;
> interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> index 663676c..d81980c 100644
> --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> @@ -41,7 +41,7 @@
> };
>
> macb1: ethernet@f803 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xf803 0x100>;
> interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi
> b/arch/arm/boot/dts/sama5d3_emac.dtsi
> index fe2af92..b4544cf 100644
> --- a/arch/arm/boot/dts/sama5d3_emac.dtsi
> +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
> @@ -41,7 +41,7 @@
> };
>
> macb1: ethernet@f802c000 {
> - compatible = "cdns,at32ap7000-macb",
> "cdns,macb";
> + compatible = "cdns,at91sam9260-macb",
> "cdns,macb";
> reg = <0xf802c000 0x100>;
> interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
> pinctrl-names = "default";
>
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Re: [PATCH v2 0/3] net: macb: rework at91 specific handling
Le 06/03/2015 11:23, Boris Brezillon a écrit : > Hello, > > This removes the #if defined(ARCH_AT91) sections to prevent any problem > when enabling ARM multi-platform support. > The at91 specific logic is now activated when the "at91sam9260-macb" > compatible string is found. > > Best Regards, > > Boris I'm okay with the whole series: Acked-by: Nicolas Ferre > > Changes since v1: > - avoid changing existing behavior as Alexandre suggested > > Boris Brezillon (3): > net/macb: Update DT bindings documentation > ARM: at91/dt: fix macb compatible strings > net: macb: remove #if defined(CONFIG_ARCH_AT91) sections > > Documentation/devicetree/bindings/net/macb.txt | 5 +++- > arch/arm/boot/dts/at91sam9260.dtsi | 2 +- > arch/arm/boot/dts/at91sam9263.dtsi | 2 +- > arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- > arch/arm/boot/dts/at91sam9x5_macb0.dtsi| 2 +- > arch/arm/boot/dts/at91sam9x5_macb1.dtsi| 2 +- > arch/arm/boot/dts/sama5d3_emac.dtsi| 2 +- > drivers/net/ethernet/cadence/macb.c| 32 > ++ > drivers/net/ethernet/cadence/macb.h| 2 ++ > 9 files changed, 29 insertions(+), 22 deletions(-) > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: dt: at91: new binding
Le 26/02/2015 10:34, Jean-Christophe PLAGNIOL-VILLARD a écrit :
> Today if we want to disable a pio bank we may will siliently break pinctrl
> configuration in the DT. This will be detected only at runtime.
>
> So move the pinctrl configuration to the bank instead of the bus.
> This allow to detect pinctrl issue at DT compiling time when disable a bank.
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> Cc: Linus Walleij
> Cc: devicetree@vger.kernel.org
> ---
> .../bindings/pinctrl/atmel,at91-pinctrl.txt| 66
> ++
> 1 file changed, 66 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> index b7a93e8..78355ee 100644
> --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> @@ -148,3 +148,69 @@ dbgu: serial@f200 {
> pinctrl-0 = <&pinctrl_dbgu>;
> status = "disabled";
> };
> +
> +II) New Bindings per PIO Block
Sorry but NACK.
I don't want to manage another flavor of the pinmux biding with no real
benefit. I would have been good if we had it from day-1. Now it's too late.
Moreover, splitting a binding definition if you have a function given by
multiple banks can be weird and not well understood in regard to our
current group+function definition scheme (Cf. your last example).
> +This allow to detect pinctrl issue at DT compiling time when disable a bank
> +
> +Required properties for iomux controller:
> +- compatible: "atmel,at91rm9200-pio-pinctrl" or
> "atmel,at91sam9x5-pio-pinctrl"
> + or "atmel,sama5d3-pio-pinctrl"
> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
> + configured in this periph mode. All the periph and bank need to be
> describe.
> +
> +How to create such array:
> +
> +Each column will represent the possible peripheral of the pinctrl for the
> bank
> +
> +Take an example on the 9260
> +Peripheral: 2 ( A and B)
> +=>
> +
> + /*A B */
> + 0x 0xffc00c3b /* pioA */
> +
> +For each peripheral/bank we will descibe in a u32 if a pin can be
> +configured in it by putting 1 to the pin bit (1 << pin)
> +
> +Required properties for pin configuration node:
> +- atmel,pins: 3 integers array, represents a group of pins mux and config
> + setting. The format is atmel,pins = .
> + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
> +
> +Bits used for CONFIG:
> +cf atmel,at91-pinctrl
> +
> +pioB: gpio@f600 {
> + compatible = "atmel,at91rm9200-gpio", "atmel,at91rm9200-pio-pinctrl";
> + reg = <0xf600 0x200>;
> + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&pioB_clk>;
> +
> + /*A B */
> + atmel,mux-mask = <0x 0x7fff3ccf>;
> +
> + dbgu {
> + pinctrl_dbgu: dbgu-0 {
> + atmel,pins =
> + <14 0x1 0x0 /* PB14 periph A */
> + 15 0x1 0x1>; /* PB15 periph A with pullup */
> + };
> + };
> +};
> +
> +dbgu: serial@f200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0xf200 0x200>;
> + interrupts = <1 4 7>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_dbgu>;
> + status = "disabled";
> +};
> +
> +if you have to use multiple bank
> + pinctrl-0 = <&pinctrl_ip_piaa>, <&pinctrl_ip_piab>;
>
Best regards,
--
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Re: [PATCH] ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region
Le 05/03/2015 02:52, Josh Wu a écrit : > Hi, Nicolas > > On 3/4/2015 11:19 PM, Nicolas Ferre wrote: >> Le 15/01/2015 11:05, Boris Brezillon a écrit : >>> Hi Josh, >>> >>> On Thu, 15 Jan 2015 17:59:15 +0800 >>> Josh Wu wrote: >>> >>>> Hi， Boris >>>> >>>> Thanks for the review. >>>> >>>> On 1/15/2015 4:45 PM, Boris Brezillon wrote: >>>>> Hi Josh, >>>>> >>>>> On Thu, 15 Jan 2015 15:08:03 +0800 >>>>> Josh Wu wrote: >>>>> >>>>>> To get NFC status, we need to read the NFC command registers, which is a >>>>>> 256M memory mapping address. To check the status, you just read such >>>>>> address from NFC command registers. >>>>>> For example, to check NFCBUSY (bit 27), you need to read 0x0800 >>>>>> (bit 27 is set to 1) of the NFC command register. >>>>>> If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, >>>>>> you need to read 0x0c00 (bit 27 and bit 26 are set to 1). >>>>> Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR >>>>> representing the same thing. >>>> yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is >>>> also refer to NFC_BUSY of HSMC_SR. >>>> >>>>> If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS >>>>> to check the status [1] and drop the last bit in the NFC Command >>>>> Resgiters range. >>>> Thank you. your code works (just need some typo change). >>>> I want to send [1] code with your signed-off and my acked to mtd list. >>>> Is it okay for you? >>> Sure, no problem. >> Hi Josh, >> >> What is the status of this patch set? > > The v2 of this patch is sent. But it's not taken by Brain. > I just ping Brain yesterday. Check the v2 patch here: > http://patchwork.ozlabs.org/patch/431752/ Ok, thanks for the information Josh. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: at91: dts: sama5d3/sama5d4: reduce NFC command registers memory region
Le 15/01/2015 11:05, Boris Brezillon a écrit : > Hi Josh, > > On Thu, 15 Jan 2015 17:59:15 +0800 > Josh Wu wrote: > >> Hi， Boris >> >> Thanks for the review. >> >> On 1/15/2015 4:45 PM, Boris Brezillon wrote: >>> Hi Josh, >>> >>> On Thu, 15 Jan 2015 15:08:03 +0800 >>> Josh Wu wrote: >>> >>>> To get NFC status, we need to read the NFC command registers, which is a >>>> 256M memory mapping address. To check the status, you just read such >>>> address from NFC command registers. >>>> For example, to check NFCBUSY (bit 27), you need to read 0x0800 >>>> (bit 27 is set to 1) of the NFC command register. >>>> If you want to check NFCBUSY (bit 27) and NFCWR (bit 26) in same time, >>>> you need to read 0x0c00 (bit 27 and bit 26 are set to 1). >>> Are NFCBUSY and NFCWR found in NFCDATA_STATUS and those found in HSMC_SR >>> representing the same thing. >> yes. it is. I just check with IP team. The NFCBUSY of NFCDATA_STATUS is >> also refer to NFC_BUSY of HSMC_SR. >> >>> If they are, I think you can just use HSMC_SR instead of NFCDATA_STATUS >>> to check the status [1] and drop the last bit in the NFC Command >>> Resgiters range. >> Thank you. your code works (just need some typo change). >> I want to send [1] code with your signed-off and my acked to mtd list. >> Is it okay for you? > > Sure, no problem. Hi Josh, What is the status of this patch set? Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/4] ARM: at91: sama5d4ek: enable audio support
Le 02/02/2015 07:51, Bo Shen a écrit : > This patch set enable audio support on sama5d4ek. > It depends the patch [1] (ASoC: atmel-pcm-dma: won't check direction > when configure dma) > [1] https://patchwork.kernel.org/patch/5759441/ > > > Bo Shen (4): > ARM: at91: dt: sama5d4: add ssc nodes > ARM: at91: dt: sama5d4ek: enable ssc0 > ARM: at91: dt: sama5d4ek: add and enable wm8904 > ARM: at91: dt: sama5d4ek: enable audio Whole series stacked on top of at91-4.1-dt. Thanks, bye. > arch/arm/boot/dts/at91-sama5d4ek.dts | 31 > arch/arm/boot/dts/sama5d4.dtsi | 70 > > 2 files changed, 101 insertions(+) > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] ARM: at91: dt: sama5d4: add ssc nodes
AT91_PIOB 30
> AT91_PERIPH_B AT91_PINCTRL_NONE /* PB30 periph B RF0 */
> + AT91_PIOB 29
> AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB29 periph B RD0 */
> + };
> + };
> +
> + ssc1 {
> + pinctrl_ssc1_tx: ssc1_tx {
> + atmel,pins =
> + AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B TK1 */
> + AT91_PIOC 20
> AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B TF1 */
> + AT91_PIOC 21
> AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC21 periph B TD1 */
> + };
> +
> + pinctrl_ssc1_rx: ssc1_rx {
> + atmel,pins =
> + AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B RK1 */
> + AT91_PIOC 22
> AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B RF1 */
> + AT91_PIOC 23
> AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B RD1 */
> + };
> + };
Nit: I modified these 2 nodes:
1/ sort alphabetically
2/ removed the "PC22 periph B" part of the comment with is not needed.
No need to re-send.
Thanks, bye.
> };
>
> aic: interrupt-controller@fc06e000 {
>
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Re: [PATCH 0/4] ARM: at91: at91sam9x5: enable ISI and ov2640 support
Le 12/02/2015 10:08, Boris Brezillon a écrit : > On Thu, 12 Feb 2015 16:06:22 +0800 > Josh Wu wrote: > >> This patch series will enable ISI and ov2640 sensor support for >> at91sam9g25ek board. > > This series looks good to me. > > Acked-by: Boris Brezillon Acked-by: Nicolas Ferre 3 first patches stacked on top of at91-4.1-dt. Last one on at91-4.1-defconfig. Thank, bye. >> Josh Wu (4): >> ARM: at91: at91sam9x5/dts: add ISI dt support, include isi node, >> pinctrls >> ARM: at91: at91sam9x5ek/dts: add ov2640 support >> ARM: at91: at91sam9g25ek/dts: enable ISI and ov2640 >> ARM: at91: at91_dt_defconfig: enable ISI and ov2640 support >> >> arch/arm/boot/dts/at91sam9g25.dtsi| 1 + >> arch/arm/boot/dts/at91sam9g25ek.dts | 18 + >> arch/arm/boot/dts/at91sam9x5_isi.dtsi | 46 + >> arch/arm/boot/dts/at91sam9x5ek.dtsi | 48 >> +++ >> arch/arm/configs/at91_dt_defconfig| 6 + >> 5 files changed, 119 insertions(+) >> > > > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/2] ARM: at91: dt: at91sam9n12ek: enable udp device
Le 02/03/2015 10:32, Bo Shen a écrit : > Hi Nicolas, > > On 02/10/2015 09:55 AM, Bo Shen wrote: >> This patch series enable usb device support on at91sam9n12ek board. >> >> Changes in v2: >>- Base on next-20150209 (so, remove the modification of udc driver). >>- Add pinctrl for usb1 vbus sense. >> >> Bo Shen (2): >>ARM: at91: dt: at91sam9n12: add udp device node >>ARM: at91: dt: at91sam9n12ek: enable udp > > Any comments for this patch series? (aka ping?) Hi, For the 2 patches: Acked-by: Nicolas Ferre And I've just taken these 2 patches on top of the at91-4.1-dt branch. Thanks for the "heads up" ! Bye, >> arch/arm/boot/dts/at91sam9n12.dtsi | 9 + >> arch/arm/boot/dts/at91sam9n12ek.dts | 14 ++++++ >> 2 files changed, 23 insertions(+) >> > > Best Regards, > Bo Shen > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/2] ARM: at91: dts: sama5d4: add dts for sama5d4 xplained board
status = "okay";
> +
> + at91bootstrap@0 {
> + label = "at91bootstrap";
> + reg = <0x0 0x4>;
> + };
> +
> + bootloader@4 {
> + label = "bootloader";
> + reg = <0x4 0x8>;
> + };
> +
> + bootloaderenv@c {
> + label = "bootloader env";
> + reg = <0xc 0xc>;
> + };
> +
> + dtb@18 {
> + label = "device tree";
> + reg = <0x18 0x8>;
> + };
> +
> + kernel@20 {
> + label = "kernel";
> + reg = <0x20 0x60>;
> + };
> +
> + rootfs@80 {
> + label = "rootfs";
> + reg = <0x80 0x0f80>;
> + };
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_key_gpio>;
> +
> + pb_user1 {
> + label = "pb_user1";
> + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
> + linux,code = <0x100>;
> + gpio-key,wakeup;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + status = "okay";
> +
> + d8 {
> + label = "d8";
> + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> + };
> +
> + d10 {
> + label = "d10";
> + gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
>
Otherwise, it's okay:
Acked-by: Nicolas Ferre
I take it for at91-4.1-dt (no need to respin it).
Bye,
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Re: [PATCH] ARM: at91: dts: sama5d4ek: add leds in DT node
Le 09/02/2015 10:40, Josh Wu a écrit :
> Add the leds DT node in the dts file.
> In the leds, d10 is set as heartbeat led.
>
> Signed-off-by: Josh Wu
Acked-by: Nicolas Ferre
added to at91-4.1-dt branch.
Thanks.
> ---
>
> arch/arm/boot/dts/at91-sama5d4ek.dts | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts
> b/arch/arm/boot/dts/at91-sama5d4ek.dts
> index 9198b71..0c418be 100644
> --- a/arch/arm/boot/dts/at91-sama5d4ek.dts
> +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
> @@ -257,4 +257,26 @@
> gpio-key,wakeup;
> };
> };
> +
> + leds {
> + compatible = "gpio-leds";
> + status = "okay";
> +
> + d8 {
> + label = "d8";
> + /* PE28, conflicts with usart4 rts pin */
> + gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
> + };
> +
> + d9 {
> + label = "d9";
> + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
> + };
> +
> + d10 {
> + label = "d10";
> + gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> };
>
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Re: [PATCH 1/1] ARM: at91sam9263/dt: Fixup sram1 device tree node
Le 25/02/2015 09:35, Alexander Stein a écrit :
> Commit ff04660e48b20 ("ARM: at91/dt: add SRAM nodes") used the same base
> address for sram0 and sram1 leading to the following warning:
> WARNING: CPU: 0 PID: 1 at fs/sysfs/dir.c:31 sysfs_warn_dup+0x50/0x70()
> sysfs: cannot create duplicate filename '/devices/platform/30.sram'
> Fix the base address for sram1.
>
> Signed-off-by: Alexander Stein
Acked-by: Nicolas Ferre
Added to at91-4.0-fixes. Thanks.
> ---
> arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi
> b/arch/arm/boot/dts/at91sam9263.dtsi
> index cdb7d03..76bb849 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -69,7 +69,7 @@
>
> sram1: sram@0050 {
> compatible = "mmio-sram";
> - reg = <0x0030 0x4000>;
> + reg = <0x0050 0x4000>;
> };
>
> ahb {
>
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Re: [PATCH v3] ARM: at91/dt: sam9263: Add ac97 device node
Le 08/01/2015 20:16, Alexandre Belloni a écrit :
> Hi,
>
>
> On 08/01/2015 at 20:12:04 +0100, Alexander Stein wrote :
>> Now that the implementation has been applied to sound/for-next
>> (https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/log/?h=for-next
>> ), who is going to pick the related patches (this one and the other two
>> adding documentation and default config)?
>>
>
> Nicolas will do it but he has not yet started to create a branch for
> 3.20.
Yes, both first patches added to at91-3.20-dt branch.
Thanks, best regards,
>> Best regards,
>> Alexander
>>
>> On Monday 29 December 2014, 13:08:41 wrote Alexander Stein:
>>> This adds the device node for the ac97 controller.
>>>
>>> Signed-off-by: Alexander Stein
>>> Acked-By Alexandre Belloni
>>> ---
>>> Changes in v3:
>>> * Renamed the compatible string to atmel,at91sam9263-ac97c
>>> * Added 'Acked-By Alexandre Belloni '
>>>
>>> arch/arm/boot/dts/at91sam9263.dtsi | 21 +
>>> 1 file changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi
>>> b/arch/arm/boot/dts/at91sam9263.dtsi
>>> index 6283785..2e67e38 100644
>>> --- a/arch/arm/boot/dts/at91sam9263.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
>>> @@ -700,6 +700,16 @@
>>> };
>>> };
>>>
>>> + ac97 {
>>> + pinctrl_ac97: ac97-0 {
>>> + atmel,pins =
>>> + >> AT91_PERIPH_A AT91_PINCTRL_NONE/* PB12 periph A AC97FS pin */
>>> +AT91_PIOB 1
>>> AT91_PERIPH_A AT91_PINCTRL_NONE/* PB13 periph A AC97CK pin */
>>> +AT91_PIOB 2
>>> AT91_PERIPH_A AT91_PINCTRL_NONE/* PB14 periph A AC97TX pin */
>>> +AT91_PIOB 3
>>> AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */
>>> + };
>>> + };
>>> +
>>> pioA: gpio@f200 {
>>> compatible = "atmel,at91rm9200-gpio";
>>> reg = <0xf200 0x200>;
>>> @@ -828,6 +838,17 @@
>>> status = "disabled";
>>> };
>>>
>>> + ac97: sound@fffa {
>>> + compatible = "atmel,at91sam9263-ac97c";
>>> + reg = <0xfffa 0x4000>;
>>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_ac97>;
>>> + clocks = <&ac97_clk>;
>>> + clock-names = "ac97_clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> macb0: ethernet@fffbc000 {
>>> compatible = "cdns,at32ap7000-macb",
>>> "cdns,macb";
>>> reg = <0xfffbc000 0x100>;
>>>
>>
>
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Re: [PATCH v2 1/3] ASoC: codecs: wm8904: add dt ids table
Le 16/01/2015 02:17, Bo Shen a écrit :
> Hi Mark,
>
> On 01/15/2015 07:54 PM, Mark Brown wrote:
>> On Mon, Dec 15, 2014 at 11:31:11AM +0800, Bo Shen wrote:
>>
>>> +#ifdef CONFIG_OF
>>> +static enum wm8904_type wm8904_data = WM8904;
>>> +static enum wm8904_type wm8912_data = WM8912;
>>> +
>>> +static const struct of_device_id wm8904_of_match[] = {
>>> + {
>>> + .compatible = "wlf,wm8904",
>>> + .data = &wm8904_data,
>>
>> Does this end up in the i2c_driver_id driver data or do we need some
>> extra code when devtype is assigned to check for an of_node and look at
>> the DT data instead? That certainly used to be the case...
>
> At the beginning I think as the same as you, and also add the code to
> get the data as I do in . However, as I
> remember, I2C seems only use the compatible string after the comma, that
> means only for "wlf,wm8904", it uses "wm8904" to match. So, I remove all
> the code I added, and just keep these, and it can get the device type
> correctly.
>
> So, when I submit the patch and keep the code as simple as possible.
>
> Thanks.
>
> Best Regards,
> Bo Shen
I don't understand what's keeping this patch from being applied. Voice,
do you mind re-sending?
On my side, I take the two patches that apply on AT91 DT (2/3 and 3/3).
Bye,
--
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Re: [PATCH v2] ARM: at91: sama5d4: dts: change the nand compatible string
Le 22/01/2015 12:01, Nicolas Ferre a écrit :
> Le 22/01/2015 11:41, Josh Wu a écrit :
>> As we introduce a new "atmel,sama5d4-nand" compatible string for sama5d4,
>> so we need to apply it for sama5d4 chip.
>>
>> Signed-off-by: Josh Wu
>
> Acked-by: Nicolas Ferre
>
> Brian,
> I suppose that it makes sense to keep this patch with the previous one.
> So, can you take it in your tree?
>
> Otherwise, it can take the at91 -> arm-soc route.
Bryan,
I take it with me right now and try to send it to arm-soc for 3.20.
Best regards,
>> ---
>>
>> Changes in v2:
>> - still keep the old rm9200 nand compatible string for compatible old driver.
>>
>> arch/arm/boot/dts/sama5d4.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
>> index 1b0f30c..e40b1da 100644
>> --- a/arch/arm/boot/dts/sama5d4.dtsi
>> +++ b/arch/arm/boot/dts/sama5d4.dtsi
>> @@ -267,7 +267,7 @@
>> };
>>
>> nand0: nand@8000 {
>> -compatible = "atmel,at91rm9200-nand";
>> +compatible = "atmel,sama5d4-nand",
>> "atmel,at91rm9200-nand";
>> #address-cells = <1>;
>> #size-cells = <1>;
>> ranges;
>>
>
>
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Re: [PATCH v3 2/3] ARM: at91/dt: sama5d4: add pioD controller
Le 21/01/2015 10:49, Linus Walleij a écrit : > On Mon, Jan 19, 2015 at 11:46 AM, Nicolas Ferre > wrote: >> Le 16/01/2015 16:31, Ludovic Desroches a écrit : >>> PioD controller was not described in the device tree since we don't use >>> it. As pinctrl-at91 allows disabled gpio controllers in the device >>> tree, we can add it to complete the device description. >>> >>> Signed-off-by: Ludovic Desroches >> >> Acked-by: Nicolas Ferre >> >> Linus, >> >> As there is no dependency with the other patches in the series, I can >> take this patch or you can keep it together with the other ones. Just >> tell me once we agree all on a solution. > > Please take this patch along with other AT91 stuff upstream > through ARM SoC. > Acked-by: Linus Walleij Ok, it is now stacked on top of our at91-3.20-dt branch and I'll send it to arm-soc soon. Thanks, bye. -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: at91: sama5d4: dts: change the nand compatible string
Le 22/01/2015 11:41, Josh Wu a écrit :
> As we introduce a new "atmel,sama5d4-nand" compatible string for sama5d4,
> so we need to apply it for sama5d4 chip.
>
> Signed-off-by: Josh Wu
Acked-by: Nicolas Ferre
Brian,
I suppose that it makes sense to keep this patch with the previous one.
So, can you take it in your tree?
Otherwise, it can take the at91 -> arm-soc route.
Bye,
> ---
>
> Changes in v2:
> - still keep the old rm9200 nand compatible string for compatible old driver.
>
> arch/arm/boot/dts/sama5d4.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 1b0f30c..e40b1da 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -267,7 +267,7 @@
> };
>
> nand0: nand@8000 {
> - compatible = "atmel,at91rm9200-nand";
> + compatible = "atmel,sama5d4-nand",
> "atmel,at91rm9200-nand";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
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Re: [PATCH RFC] pinctrl: at91
Le 19/01/2015 11:30, Ludovic Desroches a écrit : > On Mon, Jan 19, 2015 at 11:12:45AM +0100, Linus Walleij wrote: >> On Wed, Jan 14, 2015 at 4:03 PM, Ludovic Desroches >> wrote: >> >>> From my point of view, it is two distinct topics. One is a very >>> important fix because our SAMA5D4 device is not booting without it. The >>> other one is a proper way to manage gpio ranges but alone I don't think >>> it can solve my issue. >> >> Can you make me a minimal, sane patch that fixes the boot regression? >> >> I hate regressions so these need to be fixed first... >> >> The rest we can discuss I guess. >> >> Or is it not possible to solve the boot regression without the larger >> fix? > > No I don't think we can have a smaller patch than this one to fix it. > Next step is to decide if we go further as you suggested, knowing that we > would have to modify the device tree. Moreover we will have to rework > our pinctrl driver (or write a new one) since we will have new pio > controller on future devices. Yes, all the upcoming AT91 SoCs will embed a totally new pinctrl/pinmux IP. We will write a new driver for it and we will be able to use the up-to-date standards of the framework. In the meantime, this fix allows us to use the SAMA5D4 without too much changes to the original version of our current driver and without modification to all the current SoCs device trees. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/3] ARM: at91/dt: sama5d4: add pioD controller
Le 16/01/2015 16:31, Ludovic Desroches a écrit :
> PioD controller was not described in the device tree since we don't use
> it. As pinctrl-at91 allows disabled gpio controllers in the device
> tree, we can add it to complete the device description.
>
> Signed-off-by: Ludovic Desroches
Acked-by: Nicolas Ferre
Linus,
As there is no dependency with the other patches in the series, I can
take this patch or you can keep it together with the other ones. Just
tell me once we agree all on a solution.
Bye,
> ---
> arch/arm/boot/dts/sama5d4.dtsi | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
> index 1b0f30c..368973e 100644
> --- a/arch/arm/boot/dts/sama5d4.dtsi
> +++ b/arch/arm/boot/dts/sama5d4.dtsi
> @@ -62,6 +62,7 @@
> gpio0 = &pioA;
> gpio1 = &pioB;
> gpio2 = &pioC;
> + gpio3 = &pioD;
> gpio4 = &pioE;
> tcb0 = &tcb0;
> tcb1 = &tcb1;
> @@ -,6 +1112,18 @@
> clocks = <&pioC_clk>;
> };
>
> + pioD: gpio@fc068000 {
> + compatible = "atmel,at91sam9x5-gpio",
> "atmel,at91rm9200-gpio";
> + reg = <0xfc068000 0x100>;
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&pioD_clk>;
> + status = "disabled";
> + };
> +
> pioE: gpio@fc06d000 {
> compatible = "atmel,at91sam9x5-gpio",
> "atmel,at91rm9200-gpio";
> reg = <0xfc06d000 0x100>;
>
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Re: [PATCH v3 1/3] pinctrl: at91: allow to have disabled gpio bank
Le 16/01/2015 16:31, Ludovic Desroches a écrit :
> From: Jean-Christophe PLAGNIOL-VILLARD
>
> Today we expect that all the bank are enabled, and count the number of banks
> used by the pinctrl based on it instead of using the last bank id enabled.
>
> So switch to it, set the chained IRQ at runtime based on enabled banks
> and wait only the number of enabled gpio controllers at probe time.
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> Signed-off-by: Ludovic Desroches
>
> Cc: # 3.18
As I acknowledged a comparable solution previously, and after reading,
this patch seems okay:
Acked-by: Nicolas Ferre
Thanks, bye.
> ---
> drivers/pinctrl/pinctrl-at91.c | 108
> +
> 1 file changed, 55 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index dfd021e..f4cd0b9 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -177,7 +177,7 @@ struct at91_pinctrl {
> struct device *dev;
> struct pinctrl_dev *pctl;
>
> - int nbanks;
> + int nactive_banks;
>
> uint32_t*mux_mask;
> int nmux;
> @@ -653,12 +653,18 @@ static int pin_check_config(struct at91_pinctrl *info,
> const char *name,
> int mux;
>
> /* check if it's a valid config */
> - if (pin->bank >= info->nbanks) {
> + if (pin->bank >= gpio_banks) {
> dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
> - name, index, pin->bank, info->nbanks);
> + name, index, pin->bank, gpio_banks);
> return -EINVAL;
> }
>
> + if (!gpio_chips[pin->bank]) {
> + dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
> + name, index, pin->bank);
> + return -ENXIO;
> + }
> +
> if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
> dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
> name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
> @@ -981,7 +987,8 @@ static void at91_pinctrl_child_count(struct at91_pinctrl
> *info,
>
> for_each_child_of_node(np, child) {
> if (of_device_is_compatible(child, gpio_compat)) {
> - info->nbanks++;
> + if (of_device_is_available(child))
> + info->nactive_banks++;
> } else {
> info->nfunctions++;
> info->ngroups += of_get_child_count(child);
> @@ -1003,11 +1010,11 @@ static int at91_pinctrl_mux_mask(struct at91_pinctrl
> *info,
> }
>
> size /= sizeof(*list);
> - if (!size || size % info->nbanks) {
> - dev_err(info->dev, "wrong mux mask array should be by %d\n",
> info->nbanks);
> + if (!size || size % gpio_banks) {
> + dev_err(info->dev, "wrong mux mask array should be by %d\n",
> gpio_banks);
> return -EINVAL;
> }
> - info->nmux = size / info->nbanks;
> + info->nmux = size / gpio_banks;
>
> info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size,
> GFP_KERNEL);
> if (!info->mux_mask) {
> @@ -1131,7 +1138,7 @@ static int at91_pinctrl_probe_dt(struct platform_device
> *pdev,
> of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
> at91_pinctrl_child_count(info, np);
>
> - if (info->nbanks < 1) {
> + if (gpio_banks < 1) {
> dev_err(&pdev->dev, "you need to specify at least one
> gpio-controller\n");
> return -EINVAL;
> }
> @@ -1144,7 +1151,7 @@ static int at91_pinctrl_probe_dt(struct platform_device
> *pdev,
>
> dev_dbg(&pdev->dev, "mux-mask\n");
> tmp = info->mux_mask;
> - for (i = 0; i < info->nbanks; i++) {
> + for (i = 0; i < gpio_banks; i++) {
> for (j = 0; j < info->nmux; j++, tmp++) {
> dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
> }
> @@ -1162,7 +1169,7 @@ static int at91_pinctrl_probe_dt(struct platform_device
> *pdev,
> if (!info->groups)
> return -ENOMEM;
>
> - dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
> + dev_dbg(&pdev->dev, "nbanks = %d\n&
Re: [PATCH v3 3/3] MAINTAINERS: add maintainer for pinctrl-at91
Le 16/01/2015 16:31, Ludovic Desroches a écrit : > Signed-off-by: Ludovic Desroches > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 3589d67..455630d 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -7406,6 +7406,7 @@ F: include/linux/pinctrl/ > > PIN CONTROLLER - ATMEL AT91 > M: Jean-Christophe Plagniol-Villard > +M: Ludovic Desroches > L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: drivers/pinctrl/pinctrl-at91.* Yes, as I've just said for the v2 of this series: Acked-by: Nicolas Ferre Thanks, bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] MAINTAINERS: add maintainer for pinctrl-at91
Le 19/01/2015 11:02, Linus Walleij a écrit : > On Wed, Jan 14, 2015 at 11:08 AM, Ludovic Desroches > wrote: > >> Signed-off-by: Ludovic Desroches > > The more maintainers the better. > Nicolas & J-C: can you ACK this? Absolutely: Acked-by: Nicolas Ferre Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/8] ARM: at91: dts: sama5d3: add dt support for atmel isi and ov2640 sensor
Le 04/01/2015 10:02, Josh Wu a écrit :
> This patch series add ISI and ov2640 support on dts files.
>
> As the ov2640 driver dt is still in review. The patch is in:
> https://patchwork.linuxtv.org/patch/27554/
> So I want to send this dt patch early for a review.
>
> v1 -> v2:
> 1. add one more patch to change the pin name of ISI_MCK
> 2. rewrite the commit [4/8] ARM: at91: dts: sama5d3: change name of
> pinctrl_isi_{power,reset}.
> 3. move the common chip parts of ISI node to sama5d3.dtsi.
>
> Bo Shen (3):
> ARM: at91: dts: sama5d3: split isi pinctrl
> ARM: at91: dts: sama5d3: add missing pins of isi
> ARM: at91: dts: sama5d3: move the isi mck pin to mb
>
> Josh Wu (5):
> ARM: at91: dts: sama5d3: add isi clock
> ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}
> ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK
> ARM: at91: dts: sama5d3: add ov2640 camera sensor support
> ARM: at91: sama5: enable atmel-isi and ov2640 in defconfig
The whole series:
Acked-by: Nicolas Ferre
stacked on top of at91-3.20-dt.
The defconfig update on his side on at91-3.20-defconfig
Bye,
> arch/arm/boot/dts/sama5d3.dtsi| 24 ++-
> arch/arm/boot/dts/sama5d3xmb.dtsi | 40
> +++
> arch/arm/configs/sama5_defconfig | 6 ++
> 3 files changed, 61 insertions(+), 9 deletions(-)
>
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Re: [PATCH v2 1/5] irqchip: add dumb demultiplexer implementation
irq pattern, except for > those that really have an irq line shared by a timer and several other > devices (not sure yet, but at91 seems to be the only impacted platform > so far). > >> >>> If you have a proper solution for the problem at hand which >>> >>>- avoids the demux dummy >>> >>>- works straight forward with suspend/resume/wakeup >>> >>>- does not add horrible new APIs >>> >>>- does not add conditionals to the interrupt hotpath >>> >>>- does not inflict platform knowledge about interrupt chip details >>> on drivers >>> >>> then I'm happy to take it. >>> >>> But as long as you can't come up with anything sane, the demux dummy >>> is the best solution for this problem we've seen so far. >> >> What if during suspend you move all actions w/o IRQF_NO_SUSPEND to a >> suspended action list? This would leave only the actions with >> IRQF_NO_SUSPEND set in the active action list. The cost would be a >> pointer in irq_desc and moving the actions during suspend and resume. > > That really looks like what I suggested here [1]. > >> >> There are probably ways to do this demux irqchip without a DT change. >> Since we can't just move Linux irq numbers to different irq_chips >> during request_irq, we would have to parse the DT up front to find all >> shared interrupts and create a demux irqchip for them. That wouldn't >> be very efficient, but is straight-forward. Then we'd have to handle >> the translation into Linux irq numbers correctly which is probably the >> more difficult part. > > I'm really interested in seeing how you would do this. Well, it really looks like a ping-pong game and Boris tried hard to explore both options. I suspect that he already made his best to solve this problem. In the meantime, we begin to see people using our (old, badly designed, okay-okay) hardware and have the surprise of hitting this warning on Mainline kernel. As we have several set of timers, they may even not be affected by the core issue by selecting a timer which doesn't have a shared interrupt line. I mean, we discovered this when it was already written (in linux-next actually) and tried to address the issue quickly. But now, we urgently need a solution or a temporary workaround and Boris wrote two. I have the feeling that we have to move on by selecting one. Clearly, if the only issue remaining is that one solution may cause DT changes for AT91, well, we can cope with this and accept it. If we don't come to a conclusion quickly, maybe we would have to consider removing this warning while we are working on the issue: believe me, it's frightening and sometimes even inappropriate when people select a different set of timers for their clocksource/clockevent after boot time. Best regards, > [1]https://lkml.org/lkml/2014/12/15/551 > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] irqchip: add dumb demultiplexer implementation
Le 15/01/2015 10:11, Thomas Gleixner a écrit : > On Wed, 14 Jan 2015, Rob Herring wrote: >> On Wed, Jan 14, 2015 at 4:36 AM, Thomas Gleixner wrote: >>> All attempts to work around that have resulted in horrible bandaids so >>> far. That's why I guided Boris to implement this dummy demultiplexing >>> mechanism. It solves the problem at hand nicely without adding nasty >>> hackarounds into the suspend/resume code and inflicting platform >>> knowledge on multi-platform device drivers. >> >> This change will break on old kernels with a new dtb. Would you be >> happy if a BIOS update required a new kernel? Fixing this for any >> platform requires a dtb update which may not be possible on some >> platforms. I don't have a problem with this breakage for 1 platform >> and the at91 guys may not care, but we'd ultimately be changing how >> all shared irqs are specified for all DT. Maybe we decide that this is >> how we want to describe things, but that needs much wider discussion >> and agreement. > > We do not change shared interrupts in any way. We provide an > alternative mechanism for braindead hardware. And if the at91 folks Let me add subtle details: "Old braindead hardware, with possibility to use alternative set of timers which doesn't have shared interrupt lines" ;-) > are fine with the DT change, then it's their decision. Nothing forces > this on everyone. Yes I do agree to change DT. >>> If you have a proper solution for the problem at hand which >>> >>>- avoids the demux dummy >>> >>>- works straight forward with suspend/resume/wakeup >>> >>>- does not add horrible new APIs >>> >>>- does not add conditionals to the interrupt hotpath >>> >>>- does not inflict platform knowledge about interrupt chip details >>> on drivers >>> >>> then I'm happy to take it. >>> >>> But as long as you can't come up with anything sane, the demux dummy >>> is the best solution for this problem we've seen so far. >> >> What if during suspend you move all actions w/o IRQF_NO_SUSPEND to a >> suspended action list? This would leave only the actions with >> IRQF_NO_SUSPEND set in the active action list. The cost would be a >> pointer in irq_desc and moving the actions during suspend and resume. > > That's exactly what we want NOT. Because it prevents us to do proper > sanity checks for IRQF_NO_SUSPEND. We've been there and I rejected it > for that very reason. > >> There are probably ways to do this demux irqchip without a DT change. > > What's the problem with a DT change for a single platform, if the > maintainers are willing to take it and deal with the fallout? > > And in case of AT91 the new kernel will simply work with the old DT > and just emit the same warning vs. the IRQF_NO_SUSPEND mismatch. Older > kernels won't work with a new DT, but that's about it. > > Aside of that, I'm quite amused about your DT update worries. DTs > break with every kernel version on very popular platforms in very > weird and subtle ways. DT on AT91 is a Work In Progress (for 3.5 years) and the facts have told us that DT updates were absolutely necessary. So, for now, I agree to change DT as far as AT91 is concerned. Bye, -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] irqchip: add dumb demultiplexer implementation
Le 14/01/2015 15:03, Boris Brezillon a écrit :
> On Wed, 14 Jan 2015 14:36:42 +0100
> Nicolas Ferre wrote:
>
>> Le 13/01/2015 19:46, Boris Brezillon a écrit :
>>> Some interrupt controllers are multiplexing several peripheral IRQs on
>>> a single interrupt line.
>>> While this is not a problem for most IRQs (as long as all peripherals
>>> request the interrupt with IRQF_SHARED flag set), multiplexing timers and
>>> other type of peripherals will generate a WARNING (mixing IRQF_NO_SUSPEND
>>> and !IRQF_NO_SUSPEND is prohibited).
>>>
>>> Create a dumb irq demultiplexer which simply forwards interrupts to all
>>> peripherals (exactly what's happening with IRQ_SHARED) but keep a unique
>>> irq number for each peripheral, thus preventing the IRQF_NO_SUSPEND
>>> and !IRQF_NO_SUSPEND mix on a given interrupt.
>>>
>>> Signed-off-by: Boris Brezillon
>>> ---
>>> drivers/irqchip/Kconfig | 4 ++
>>> drivers/irqchip/Makefile | 1 +
>>> drivers/irqchip/irq-dumb-demux.c | 70
>>> include/linux/irq.h | 49 ++
>>> include/linux/irqdomain.h| 1 +
>>> kernel/irq/Kconfig | 5 ++
>>> kernel/irq/Makefile | 1 +
>>> kernel/irq/chip.c| 41
>>> kernel/irq/dumb-demux-chip.c | 140
>>> +++
>>> kernel/irq/handle.c | 31 -
>>> kernel/irq/internals.h | 3 +
>>> 11 files changed, 344 insertions(+), 2 deletions(-)
>>> create mode 100644 drivers/irqchip/irq-dumb-demux.c
>>> create mode 100644 kernel/irq/dumb-demux-chip.c
[..]
>>> +static void irq_dumb_demux_mask(struct irq_data *d)
>>> +{
>>> + struct irq_chip_dumb_demux *demux = irq_data_get_irq_chip_data(d);
>>> +
>>> + clear_bit(d->hwirq, &demux->unmasked);
>>> +
>>> + if (!demux->unmasked)
>>> + disable_irq_nosync(demux->src_irq);
>>> +}
>>> +
>>> +static void irq_dumb_demux_unmask(struct irq_data *d)
>>> +{
>>> + struct irq_chip_dumb_demux *demux = irq_data_get_irq_chip_data(d);
>>> + bool enable_src_irq = !demux->unmasked;
>>
>> Why this additional "bool" unlike the other function above?
>
> Because set_bit will modify the unmasked status and we must check if it
> is equal to 0 (in other terms, all irqs are masked) before modifying it
> in order to know whether we should enable the src irq or not.
pf! ok, sorry for the noise then ;-)
>>> +
>>> + set_bit(d->hwirq, &demux->unmasked);
>>> +
>>> + if (enable_src_irq)
>>> + enable_irq(demux->src_irq);
>>> +}
>>> +
[...]
Bye,
--
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Re: [PATCH v2 5/5] ARM: at91/dt: define a dumb irq demultiplexer chip connected on irq1
Le 13/01/2015 19:46, Boris Brezillon a écrit :
> IRQ is multiplexing several peripheral IRQs, but there's no way to
> properly demultiplex those IRQs.
> Use a dumb irq demux chip to achieve this demultiplexing operation.
>
> Signed-off-by: Boris Brezillon
> ---
> arch/arm/boot/dts/at91sam9260.dtsi | 26 --
> 1 file changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi
> b/arch/arm/boot/dts/at91sam9260.dtsi
> index dd1313c..debe8d2 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -10,7 +10,7 @@
>
> #include "skeleton.dtsi"
> #include
> -#include
> +#include
> #include
> #include
>
> @@ -89,6 +89,7 @@
> atmel,external-irqs = <29 30 31>;
> };
>
> +
> ramc0: ramc@ea00 {
> compatible = "atmel,at91sam9260-sdramc";
> reg = <0xea00 0x200>;
> @@ -97,7 +98,7 @@
> pmc: pmc@fc00 {
> compatible = "atmel,at91sam9260-pmc";
> reg = <0xfc00 0x100>;
> - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + interrupts-extended = <&dumb_irq1_demux
> AIC_IRQ1_PMC>;
> interrupt-controller;
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -364,7 +365,7 @@
> pit: timer@fd30 {
> compatible = "atmel,at91sam9260-pit";
> reg = <0xfd30 0xf>;
> - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + interrupts-extended = <&dumb_irq1_demux
> AIC_IRQ1_PIT>;
> clocks = <&mck>;
> };
>
> @@ -750,7 +751,7 @@
> dbgu: serial@f200 {
> compatible = "atmel,at91sam9260-usart";
> reg = <0xf200 0x200>;
> - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + interrupts-extended = <&dumb_irq1_demux
> AIC_IRQ1_DBGU>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_dbgu>;
> clocks = <&mck>;
> @@ -959,7 +960,7 @@
> rtc@fd20 {
> compatible = "atmel,at91sam9260-rtt";
> reg = <0xfd20 0x10>;
> - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + interrupts-extended = <&dumb_irq1_demux
> AIC_IRQ1_RTT>;
> clocks = <&clk32k>;
> status = "disabled";
> };
> @@ -967,7 +968,7 @@
> watchdog@fd40 {
> compatible = "atmel,at91sam9260-wdt";
> reg = <0xfd40 0x10>;
> - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + interrupts-extended = <&dumb_irq1_demux
> AIC_IRQ1_WATCHDOG>;
> atmel,watchdog-type = "hardware";
> atmel,reset-type = "all";
> atmel,dbg-halt;
> @@ -1010,6 +1011,19 @@
> };
> };
>
> + dumb_irq1_demux: dumb-irq-demux@1 {
> + compatible = "irqchip-dumb-demux";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + irqs = <(AIC_IRQ_MASK(AIC_IRQ1_PMC) |
> + AIC_IRQ_MASK(AIC_IRQ1_PIT) |
> + AIC_IRQ_MASK(AIC_IRQ1_DBGU) |
> + AIC_IRQ_MASK(AIC_IRQ1_RTT) |
> + AIC_IRQ_MASK(AIC_IRQ1_WATCHDOG) |
> + AIC_IRQ_MASK(AIC_IRQ1_RSTC))>;
> + };
> +
Yep, with the modification that you suggested in "Re: [PATCH v2 4/5]
ARM: at91/dt: add AIC irq1 muxed peripheral id definitions" it would be
even simpler.
Acked-by: Nicolas Ferre
> i2c@0 {
> compatible = "i2c-gpio";
> gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
>
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Re: [PATCH v2 3/5] ARM: at91/dt: select DUMB_IRQ_DEMUX for all at91 SoCs
Le 13/01/2015 19:46, Boris Brezillon a écrit : > at91 SoCs need an dumb irq demuxer to gracefully support the fact that "Older AT91 SoCs" please ;-) Nit.: "an dumb demuxer" => "a virtual dumb demuxer" > irq1 is shared by several devices and a timer. > > Signed-off-by: Boris Brezillon As the newer SoCs don't need it, we can't select this option for the whole CONFIG_ARCH_AT91, so indeed: Acked-by: Nicolas Ferre > --- > arch/arm/mach-at91/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig > index 2395c68..8ff2c2a 100644 > --- a/arch/arm/mach-at91/Kconfig > +++ b/arch/arm/mach-at91/Kconfig > @@ -28,6 +28,7 @@ config HAVE_AT91_H32MX > config SOC_AT91SAM9 > bool > select ATMEL_AIC_IRQ > + select DUMB_DEMUX_IRQ > select COMMON_CLK_AT91 > select CPU_ARM926T > select GENERIC_CLOCKEVENTS > @@ -98,6 +99,7 @@ if SOC_SAM_V4_V5 > config SOC_AT91RM9200 > bool "AT91RM9200" > select ATMEL_AIC_IRQ > + select DUMB_DEMUX_IRQ > select COMMON_CLK_AT91 > select CPU_ARM920T > select GENERIC_CLOCKEVENTS > -- Nicolas Ferre -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
