Re: [RFC PATCH v2 3/4] drm: rockchip: hdmi: add RK3229 HDMI support
Hi Yakir, Am Donnerstag, den 07.01.2016, 18:15 +0800 schrieb Yakir Yang: > Hi Philipp, > > Thanks for your fast respond :) > > On 01/07/2016 06:04 PM, Philipp Zabel wrote: > > Am Donnerstag, den 07.01.2016, 17:02 +0800 schrieb Yakir Yang: > >> RK3229 integrate an DesignedWare HDMI2.0 controller and an INNO HDMI2.0 > >> phy, > >> the max output resolution is 4K. > >> > >> Signed-off-by: Yakir Yang > > It sounds like the INNO HDMI2.0 phy is not necessarily specific to > > RK3229 but might also appear in other SoCs? If so, I think this should > > be implemented in a separate phy driver and be used by dw_hdmi-rockchip. > > Do you mean I should create a new phy driver that place in "driver/phy" > directly ? Possibly, yes. The exynos video phys are already there. I have kept the mediatek dsi/hdmi phys together with the DRM driver, but I suppose I could move them there, too. > I have think about this idea, and it would make things much clean. But > INNO PHY > driver need the target pixel clock in drm_display_mode, I didn't find a > good way > to pass this variable to separate phy driver. Do you have some idea ? We'd need to extend the PHY API for this. For the mediatek phys we have side-stepped the issue by wiring up the PLL output to the common clock framework. I expect besides the pixel clock frequency, it might also be necessary to inform the PHY about cycles per pixel for deep color modes. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH v2 3/4] drm: rockchip: hdmi: add RK3229 HDMI support
Am Donnerstag, den 07.01.2016, 17:02 +0800 schrieb Yakir Yang:
> RK3229 integrate an DesignedWare HDMI2.0 controller and an INNO HDMI2.0 phy,
> the max output resolution is 4K.
>
> Signed-off-by: Yakir Yang
It sounds like the INNO HDMI2.0 phy is not necessarily specific to
RK3229 but might also appear in other SoCs? If so, I think this should
be implemented in a separate phy driver and be used by dw_hdmi-rockchip.
regards
Philipp
> ---
> Changes in v2:
> - Split some dw-hdmi driver changes into separate patches [01/04] & [02/04]
>
> drivers/gpu/drm/bridge/dw-hdmi.c| 27 +-
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 367
> ++--
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.h | 137 +++
> include/drm/bridge/dw_hdmi.h| 3 +
> 4 files changed, 507 insertions(+), 27 deletions(-)
> create mode 100644 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.h
>
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c
> b/drivers/gpu/drm/bridge/dw-hdmi.c
> index 5ad72ec..5e03d83 100644
> --- a/drivers/gpu/drm/bridge/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/dw-hdmi.c
> @@ -735,10 +735,12 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
> unsigned char prep,
> {
> unsigned res_idx;
> u8 val, msec;
> + int ret;
> const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
> const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
> const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
> const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
> + int mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
>
> if (prep)
> return -EINVAL;
> @@ -758,27 +760,38 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
> unsigned char prep,
> return -EINVAL;
> }
>
> + if (hdmi->plat_data->extphy_config) {
> + /* gen2 tx power off */
> + dw_hdmi_phy_gen2_txpwron(hdmi, 0);
> + dw_hdmi_phy_gen2_pddq(hdmi, 1);
> +
> + ret = hdmi->plat_data->extphy_config(hdmi->plat_data, res_idx,
> + mpixelclock);
> + /* gen2 tx power on */
> + dw_hdmi_phy_gen2_txpwron(hdmi, 1);
> + dw_hdmi_phy_gen2_pddq(hdmi, 0);
> +
> + return ret;
> + }
> +
> /* PLL/MPLL Cfg - always match on final entry */
> for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
> - if (hdmi->hdmi_data.video_mode.mpixelclock <=
> - mpll_config->mpixelclock)
> + if (mpixelclock <= mpll_config->mpixelclock)
> break;
>
> for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
> - if (hdmi->hdmi_data.video_mode.mpixelclock <=
> - curr_ctrl->mpixelclock)
> + if (mpixelclock <= curr_ctrl->mpixelclock)
> break;
>
> for (; phy_config->mpixelclock != ~0UL; phy_config++)
> - if (hdmi->hdmi_data.video_mode.mpixelclock <=
> - phy_config->mpixelclock)
> + if (mpixelclock <= phy_config->mpixelclock)
> break;
>
> if (mpll_config->mpixelclock == ~0UL ||
> curr_ctrl->mpixelclock == ~0UL ||
> phy_config->mpixelclock == ~0UL) {
> dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
> - hdmi->hdmi_data.video_mode.mpixelclock);
> + mpixelclock);
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> index 8164823..24fffaa 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -7,6 +7,7 @@
> * (at your option) any later version.
> */
>
> +#include
> #include
> #include
> #include
> @@ -21,18 +22,134 @@
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_vop.h"
>
> -#define GRF_SOC_CON60x025c
> -#define HDMI_SEL_VOP_LIT(1 << 4)
> +#include "dw_hdmi-rockchip.h"
>
> struct rockchip_hdmi {
> struct device *dev;
> struct regmap *regmap;
> struct drm_encoder encoder;
> struct dw_hdmi_plat_data plat_data;
> +
> + void __iomem *extphy_regbase;
> + struct clk *extphy_pclk;
> };
>
> #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
>
> +static const struct extphy_config_tab rockchip_extphy_cfg[] = {
> + { .mpixelclock = 16500,
> + .pre_emphasis = 0, .slopeboost = 0, .clk_level = 4,
> + .data0_level = 4, 4, 4,
> + },
> +
> + { .mpixelclock = 22500,
> + .pre_emphasis = 0, .slopeboost = 0, .clk_level = 6,
> + .data0_level = 6, 6, 6,
> + },
> +
> + { .mpixelclock = 34000,
> + .pre_emphasis = 1, .slopeboost = 0, .clk_level = 6,
> + .data0_level = 10, 10, 10,
>
Re: [PATCH v4 5/6] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl
Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
> Add device tree bindings for Hi3519 system controller.
>
> Signed-off-by: Jiancheng Xue
> ---
> Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++
> 1 file changed, 14 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt
> b/Documentation/devicetree/bindings/mfd/hi3519.txt
> new file mode 100644
> index 000..2536edc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
> @@ -0,0 +1,14 @@
> +* Hisilicon Hi3519 System Controller Block
> +
> +This bindings use the following binding:
> +Dcumentation/devicetree/bindings/clock/clock-bindings.txt
Typo: "Documentation"
- but I don't see the clock bindings being used here at all.
Maybe just drop this sentence?
> +
> +Required properties:
> +- compatible: "hisilicon,hi3519-sysctrl".
> +- reg: the register region of this block
> +
> +Examples:
> +sysctrl: system-controller@1201 {
> + compatible = "hisilicon,hi3519-sysctrl", "syscon";
> + reg = <0x1201 0x1000>;
> +};
regards
Philipp
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Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
H Jiancheng,
Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
> The CRG(Clock and Reset Generator) block provides clock
> and reset signals for other modules in hi3519 soc.
>
> Signed-off-by: Jiancheng Xue
> ---
> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
> drivers/clk/hisilicon/Kconfig | 7 +
> drivers/clk/hisilicon/Makefile | 2 +
> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
> drivers/clk/hisilicon/reset.c | 149
> +
> drivers/clk/hisilicon/reset.h | 32 +
> include/dt-bindings/clock/hi3519-clock.h | 43 ++
> 7 files changed, 382 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
> create mode 100644 drivers/clk/hisilicon/reset.c
> create mode 100644 drivers/clk/hisilicon/reset.h
> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> new file mode 100644
> index 000..2d23950
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> @@ -0,0 +1,46 @@
> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
> +
> +The Hi3519 CRG module provides clock and reset signals to various
> +controllers within the SoC.
> +
> +This binding uses the following bindings:
> +Documentation/devicetree/bindings/clock/clock-bindings.txt
> +Documentation/devicetree/bindings/reset/reset.txt
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes use this identifier
> +to specify the clock which they consume.
> +
> +All these identifier could be found in .
> +
> +- #reset-cells: should be 2.
> +
> +A reset signal can be controlled by writing a bit register in the CRG module.
> +The reset specifier consists of two cells. The first cell represents the
> +register offset relative to the base address. The second cell represents the
> +bit index in the register.
Are the resets controlled by single bits spread around the register
space? If so, I'm fine with this binding.
> +Example: CRG nodes
> +CRG: clock-reset-controller@1201 {
> + compatible = "hisilicon,hi3519-crg";
> +reg = <0x1201 0x1>;
> +#clock-cells = <1>;
> +#reset-cells = <2>;
> +};
> +
> +Example: consumer nodes
> +i2c0: i2c@1211 {
> + compatible = "hisilicon,hi3519-i2c";
> +reg = <0x1211 0x1000>;
> +clocks = <&CRG HI3519_I2C0_RST>;*/
> +resets = <&CRG 0xe4 0>;
> +};
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> index e434854..b6baebf 100644
> --- a/drivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -1,3 +1,10 @@
> +config COMMON_CLK_HI3519
> + tristate "Clock Driver for Hi3519"
> + depends on ARCH_HISI
> + default y
> + help
> + Build the clock driver for hi3519.
> +
> config COMMON_CLK_HI6220
> bool "Hi6220 Clock Driver"
> depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 74dba31..3f57b09 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -4,8 +4,10 @@
>
> obj-y+= clk.o clkgate-separated.o clkdivider-hi6220.o
>
> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> obj-$(CONFIG_ARCH_HI3xxx)+= clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
> obj-$(CONFIG_STUB_CLK_HI6220)+= clk-hi6220-stub.o
> +obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
> b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 000..e220234
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Pu
Re: [PATCH v2 6/6] reset: mediatek: mt2701 reset driver
Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao: > From: Shunli Wang > > In infrasys and perifsys, there are many reset > control bits for kinds of modules. These bits are > used as actual reset controllers to be registered > into kernel's generic reset controller framework. > > Signed-off-by: Shunli Wang Acked-by: Philipp Zabel regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/6] reset: mediatek: mt2701 reset controller dt-binding file
Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao: > From: Shunli Wang > > Dt-binding file about reset controller is used to provide > kinds of definition, which is referenced by dts file and > IC-specified reset controller driver code. > > Signed-off-by: Shunli Wang > --- > .../dt-bindings/reset-controller/mt2701-resets.h | 74 > ++ > 1 file changed, 74 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h > b/include/dt-bindings/reset-controller/mt2701-resets.h No new files in include/dt-bindings/reset-controller, please. This should go into include/dt-bindings/reset. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] clk: mediatek: Add MT2701 clock support
Hi James,
Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao:
> From: Shunli Wang
>
> Add MT2701 clock support, include topckgen, apmixedsys,
> infracfg, pericfg and subsystem clocks.
>
> Signed-off-by: Shunli Wang
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/Kconfig |8 +
> drivers/clk/mediatek/Makefile |1 +
> drivers/clk/mediatek/clk-gate.c | 56 ++
> drivers/clk/mediatek/clk-gate.h |2 +
> drivers/clk/mediatek/clk-mt2701.c | 1210
> +
> drivers/clk/mediatek/clk-mtk.c| 25 +
> drivers/clk/mediatek/clk-mtk.h| 35 +-
> 7 files changed, 1334 insertions(+), 3 deletions(-)
> create mode 100644 drivers/clk/mediatek/clk-mt2701.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index dc224e6..6c7cdc0 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
> ---help---
> Mediatek SoCs' clock support.
>
> +config COMMON_CLK_MT2701
> + bool "Clock driver for Mediatek MT2701 and MT7623"
> + depends on COMMON_CLK
> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK
> + ---help---
> + This driver supports Mediatek MT2701 and MT7623 clocks.
> +
> config COMMON_CLK_MT8135
> bool "Clock driver for Mediatek MT8135"
> depends on COMMON_CLK
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 32e7222..5b2b91b 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,4 +1,5 @@
> obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o
> clk-apmixed.o
> obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
> obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 576bdb7..38badb4 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
> regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
> }
>
> +static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_gate *cg = to_clk_gate(hw);
> + u32 val;
> +
> + regmap_read(cg->regmap, cg->sta_ofs, &val);
> + val |= BIT(cg->bit);
> + regmap_write(cg->regmap, cg->sta_ofs, val);
You can use regmap_update_bits here:
u32 bit = BIT(cg->bit);
regmap_update_bits(cg->regmap, cg->sta_ofs, bit, bit);
> +}
> +
> +static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_gate *cg = to_clk_gate(hw);
> + u32 val;
> +
> + regmap_read(cg->regmap, cg->sta_ofs, &val);
> + val &= ~(BIT(cg->bit));
> + regmap_write(cg->regmap, cg->sta_ofs, val);
and here:
u32 bit = BIT(cg->bit);
regmap_update_bits(cg->regmap, cg->sta_ofs, bit, 0);
best regards
Philipp
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Re: [linux-sunxi] Re: [PATCH v2 1/3] reset: Add shared reset_control_[de]assert variants
Am Samstag, den 19.12.2015, 11:55 +0100 schrieb Hans de Goede: > On 18-12-15 12:08, Maxime Ripard wrote: [...] > > I guess we could also have something like this: > > > >* The driver gets the reference to the reset line using > > reset_control_get or its shared variant. > > > > - If you call reset_control_get on a free line, it succeeds, and > >marks the line in exclusive use. > > - If you call reset_control_get on a busy line, it fails with > >EBUSY > > > > - If you call the shared variant on a free line, it succeeds > > - If you call the shared variant on a busy exclusive line, it > >fails with EBUSY > > - If you call the shared variant on a busy !exclusive line, it > >succeeds. >> > >* The customer driver can then call reset_control_assert / deassert: > > > > - If the reset line is in exclusive use, the assertion happens > >right away, it succeeds and returns 0. > > > > - If the reset line is in a !exclusive use, but with a single > >user, the assertion happens right away, it succeeds and returns > >0. > > Ack for all of the above, this is what I had in mind at first, but I started > with a more lightweight version as I'm lazy :) If Philipp likes this > suggestion I can rework my patch-set into this. Seconded, this all sounds good to me. > > - If the reset line is in a !exclusive use with more than 1 user, > >the refcount is modified and an error is returned to notify that > >it didn't happen. > > Also ack, except for returning the error, if a driver has used > reset_control_get_shared, it should simply be aware that doing an assert > might not necessarily actually assert the line, just like doing a clk-disable > does not really necessary disable the clock, etc. If a driver is not prepared > to deal with this, it should simply not use reset_control_get_shared. > > I see returning an error if the assert did not happen due to other users / > deassert_count != 0 as inconsistent compared to how clks, regulators and phys > handle this, these all simply return success in this case. I wouldn't want drivers to have to differentiate between relevant and irrelevant error codes, so in the clock-like refcounting use case reset_assert should not return an error if it just correctly decremented the refcount. I'd still prefer to have separate API for the counted must_deassert/may_assert vs the exclusive must_assert/must_deassert use cases, but I just can't think of a good name. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 06/14] drm/mediatek: Add HDMI support
Am Dienstag, den 29.12.2015, 16:49 +0800 schrieb Yingjoe Chen:
> On Mon, 2015-11-30 at 22:07 +0100, Philipp Zabel wrote:
> > From: Jie Qiu
> >
> > This patch adds drivers for the HDMI bridge connected to the DPI0
> > display subsystem function block, for the HDMI DDC block, and for
> > the HDMI PHY to support HDMI output.
> >
> > Signed-off-by: Jie Qiu
> > Signed-off-by: Philipp Zabel
> > ---
> <...>
> > +static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
> > + struct drm_display_mode *mode)
> > +{
> > + struct hdmi_avi_infoframe frame;
> > + u8 buffer[17];
> > + ssize_t err;
> > +
> > + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
> > + if (err < 0) {
> > + dev_err(hdmi->dev,
> > + "Failed to get AVI infoframe from mode: %ld\n", err);
>
> Please use %zd instead for ssize_t, otherwise you'll see warning message
> when compile this on 32bits platform.
>
> Joe.C
Ok, thanks.
regards
Philipp
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[PATCH v8 08/13] arm64: dts: mt8173: Add display subsystem related nodes
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Add 26 MHz PLL reference input clock and the high-speed output clock to
the MIPI TX D-PHY nodes
- The HS output clock is routed to the DSI encoder module
- Add power-domains property to all nodes in the MM domain
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 237 +++
1 file changed, 237 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4901f13..68c1cb2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -25,6 +25,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -285,6 +302,24 @@
#clock-cells = <1>;
};
+ mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ mipi_tx1: mipi-dphy@10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx1_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
gic: interrupt-controller@1022 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -431,6 +466,14 @@
status = "disabled";
};
+ hdmiddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = ;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
i2c6: i2c@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@@ -525,7 +568,187 @@
mmsys: clock-controller@1400 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
+
+ /* FIXME - remove iommus here */
+ iommus = <&iommu M4U_PORT_DISP_OVL0>,
+<&iommu M4U_PORT_DISP_OVL1>;
+ };
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compati
[PATCH v8 11/13] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 682b275..3ae0b88 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -1091,6 +1091,11 @@ static void __init mtk_apmixedsys_init(struct
device_node *node)
clk_data->clks[cku->id] = clk;
}
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+ base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h
b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1..6094bf7 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
#define CLK_APMIXED_LVDSPLL13
#define CLK_APMIXED_MSDCPLL2 14
#define CLK_APMIXED_REF2USB_TX 15
-#define CLK_APMIXED_NR_CLK 16
+#define CLK_APMIXED_HDMI_REF 16
+#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */
--
2.6.2
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[PATCH v8 09/13] arm64: dts: mt8173: Add HDMI related nodes
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Describe HDMI PHY PLL output in the device tree. The hdmitx_dig_cts
clock is not a child of tvdpll_445p5m, but is an output of the
HDMI PHY module, which is routed back into the TOP clock module
for further divison and muxing.
- The hdmi_sel mux defaults to its 26 MHz input - switch it to the
HDMI PHY PLL output.
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 68c1cb2..eb5210e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -198,6 +198,30 @@
,
;
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux =
;
+ input-enable;
+ bias-pull-down;
+ };
+
+ /*hdmi flt 5v pin*/
+ pins2 {
+ pinmux =
;
+ input-enable;
+ bias-pull-up;
+ };
+
+ /*hdmi 5v pin*/
+ pins3 {
+ pinmux =
;
+ output-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux =
,
@@ -276,6 +300,13 @@
clock-names = "spi", "wrap";
};
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
@@ -302,6 +333,18 @@
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -806,6 +849,38 @@
clock-names = "apb", "smi";
};
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+ assigned-clock-parents = <&hdmi_phy>;
+ status = "disabled";
+
+
[PATCH v8 04/13] drm/mediatek: Add DPI sub driver
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Fix mtk_dpi_power_on reference counting
- Make mtk_dpi_power_off return void
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 737
drivers/gpu/drm/mediatek/mtk_dpi.h | 84
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 1053 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index e1a40f4..218071c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -7,6 +7,7 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..48eafa0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dpi.h"
+#include "mtk_dpi_regs.h"
+
+enum mtk_dpi_polarity {
+ MTK_DPI_POLARITY_RISING,
+ MTK_DPI_POLARITY_FALLING,
+};
+
+struct mtk_dpi_polarities {
+ enum mtk_dpi_polarity de_pol;
+ enum mtk_dpi_polarity ck_pol;
+ enum mtk_dpi_polarity hsync_pol;
+ enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+ u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+ tmp |= (val & mask);
+ writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+ mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+}
+
+static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync,
+u32 width_addr, u32 porch_addr)
+{
+ mtk_dpi_mask(dpi, width_addr,
+sync->sync_width << VSYNC_WIDTH_SHIFT,
+VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, width_addr,
+sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+VSYNC_HALF_LINE_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+VSYNC_FRONT_PORCH_MASK);
+}
+
+static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
+}
+
+static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sy
[PATCH v8 06/13] drm/mediatek: Add HDMI support
From: Jie Qiu This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- Changes since v7: - Fill ELD info - Fix error messages - Replace hpd_event_data with the hdmi encoder device - Rename MT8173 specific HDMI PHY driver, MT2701 has a different PHY. - Register the PLL in the HDMI PHY module with the common clock framework. Its output hdmitx_dig_cts is routed back into the TOP clock module. - Fold contents of public mtk_hdmi_audio.h header into private mtk_hdmi.h header. --- drivers/gpu/drm/mediatek/Kconfig | 7 + drivers/gpu/drm/mediatek/Makefile | 9 + drivers/gpu/drm/mediatek/mtk_cec.c | 245 drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c| 610 drivers/gpu/drm/mediatek/mtk_hdmi.c| 482 drivers/gpu/drm/mediatek/mtk_hdmi.h| 231 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c| 362 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 757 + drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 +++ drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 221 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 506 + 13 files changed, 3532 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index b7e0404..829ab66 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -13,3 +13,10 @@ config DRM_MEDIATEK The module will be called mediatek-drm This driver provides kernel mode setting and buffer management to userspace. + +config DRM_MEDIATEK_HDMI + tristate "DRM HDMI Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select GENERIC_PHY + help + DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 218071c..2a81eeb 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -11,3 +11,12 @@ mediatek-drm-y := mtk_disp_ovl.o \ mtk_dpi.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o + +mediatek-drm-hdmi-objs := mtk_cec.o \ + mtk_drm_hdmi_drv.o \ + mtk_hdmi.o \ + mtk_hdmi_ddc_drv.o \ + mtk_hdmi_hw.o \ + mtk_mt8173_hdmi_phy.o + +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c new file mode 100644 index 000..cba3647 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#include "mtk_cec.h" + +#define TR_CONFIG 0x00 +#define CLEAR_CEC_IRQ BIT(15) + +#define CEC_CKGEN 0x04 +#define CEC_32K_PDNBIT(19) +#define PDNBIT(16) + +#define RX_EVENT 0x54 +#define HDMI_PORD BIT(25) +#define HDMI_HTPLG BIT(24) +#define HDMI_PORD_INT_EN BIT(9) +#define HDMI_HTPLG_INT_EN BIT(8) + +#define RX_GEN_WD 0x58 +#define HDMI_PORD_INT_32K_STATUS BIT(26) +#define RX_RISC_INT_32K_STATUS BIT(25) +#define HDMI_HTPLG_INT_32K_STATUS BIT(24) +#define HDMI_PORD_INT_32K_CLR BIT(18) +#define RX_INT_32K_CLR BIT(17) +#define HDMI_HTPLG_INT_32K_CLR BIT(16) +#define HDMI_PORD_INT_32K_STA_MASK
[PATCH v8 02/13] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
From: CK Hu This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu Signed-off-by: YT Shen Signed-off-by: Daniel Kurtz Signed-off-by: Philipp Zabel --- Changes since v7: - Move PANEL and MIPI_DSI config selection to later patches - Sort object files alphabetically in Makefile - Drop mtk_crtc->pipe, use drm_crtc_handle_vblank instead - Move copied event from mtk_crtc_state back to mtk_crtc - Wait for exclusive fences on incoming framebuffers using reservation_object_wait_timeout_rcu in .atomic_complete(). - Add missing atomic destroy_state callbacks - Rename mtk_crtc_ddp_power_on/of to _clk_enable/disable - Add a pending_planes flag to mtk_crtc so we can atomically update the plane configuration - Fold mtk_drm_crtc_commit into mtk_drm_crtc_atomic_flush - Make all ddp_comp callbacks take a struct mtk_ddp_comp * first parameter. - Fix OD ddp_comp function setup - Defer until iommu is present - Fix probe error path - Relax some writels --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile| 1 + drivers/gpu/drm/mediatek/Kconfig| 12 + drivers/gpu/drm/mediatek/Makefile | 10 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 301 ++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 603 drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 32 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 275 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 148 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 577 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 52 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.c | 165 drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29 ++ drivers/gpu/drm/mediatek/mtk_drm_gem.c | 227 +++ drivers/gpu/drm/mediatek/mtk_drm_gem.h | 55 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.c| 242 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.h| 59 +++ 19 files changed, 3186 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/Kconfig create mode 100644 drivers/gpu/drm/mediatek/Makefile create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4bf9a1..8fdb0c2 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -266,3 +266,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" + +source "drivers/gpu/drm/mediatek/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 1e9ff4c..607a49f 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ +obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig new file mode 100644 index 000..8dad892 --- /dev/null +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -0,0 +1,12 @@ +config DRM_MEDIATEK + tristate "DRM Support for Mediatek SoCs" + depends on DRM + depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST) + select DRM_KMS_HELPER + select IOMMU_DMA + select MTK_SMI + help + Choose this option if you have a Mediatek SoCs. + The module will be called mediatek-drm + This driver provides kernel mode setting and + buffer management to userspace. diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile new file mode 100644 index 000..c7cc41a --- /dev/null +++ b/drivers/gpu/drm/mediate
[PATCH v8 07/13] drm/mediatek: enable hdmi output control bit
From: Jie Qiu
MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 7652266..8bee167 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -19,8 +19,15 @@
#include
#include
#include
+#include
#include
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
{
return readl(hdmi->regs + offset);
@@ -170,6 +177,10 @@ void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
{
+ invoke_psci_fn = __invoke_psci_fn_smc;
+ invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+ 0x14000904, 0x8000, 0);
+
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index de7ee22..8d7d60a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -218,4 +218,5 @@
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x8201
#endif
--
2.6.2
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[PATCH v8 03/13] drm/mediatek: Add DSI sub driver
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Select the PANEL and MIPI_DSI config options
- Separate enabling MIPI TX phy output from enabling the PLL
- Make the PLL controllable via the common clock framework via
the D-PHY's high-speed clock output to the DSI encoder
---
drivers/gpu/drm/mediatek/Kconfig | 3 +
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 847 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 58 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 487 +++
7 files changed, 1402 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 8dad892..b7e0404 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -3,6 +3,9 @@ config DRM_MEDIATEK
depends on DRM
depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST)
select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ select DRM_PANEL_SIMPLE
select IOMMU_DMA
select MTK_SMI
help
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index c7cc41a..e1a40f4 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,8 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_drm_drv.o \
mtk_drm_fb.o \
mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9db22b4..39267f9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -536,6 +536,8 @@ static struct platform_driver mtk_drm_platform_driver = {
static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_drm_platform_driver,
&mtk_disp_ovl_driver,
+ &mtk_dsi_driver,
+ &mtk_mipi_tx_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 75e1b7d..e86c19e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -48,5 +48,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..6ab5a31
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,847 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dsi.h"
+
+#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START 0x00
+
+#define DSI_CON_CTRL 0x10
+#define DSI_RESET BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL 0x14
+#define MODE (3)
+#define CMD_MODE 0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE BIT(16)
+#define MIX_MODE BIT(17)
+
+#define DSI_TXRX_CTRL 0x18
+#define VC_NUM (2 << 0)
+#define LANE_NUM (0xf << 2)
+#define DIS_EOTBIT(6)
+#define NULL_ENBIT(7)
+#define TE_FREERUN BIT(8)
+#define EXT_TE_EN BIT(9)
+#define EXT_TE_EDGEBIT(10)
[PATCH v8 12/13] dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
Add an optional ddc-i2c-bus phandle property that points to an I2C master controller that handles the connector DDC pins. Signed-off-by: Philipp Zabel Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt index acd5668..508aee4 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing Required nodes: - Video port for HDMI input -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 05/13] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v7:
- Add the HDMI PLL clock output that is fed back into the
TOP clock module.
- Switch the hdmi_sel mux to it in the example.
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 148 +
1 file changed, 148 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 000..7b12424
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,148 @@
+Mediatek HDMI Encoder
+=
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+ configuration registers. For mt8173 this must be offset 0x900 into the
+ MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+- port@1: The output port in the ports node should be connected to the input
+ port of a connector node that contains a ddc-i2c-bus property, or to the
+ input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- clock-output-names: must be "hdmitx_dig_cts" on mt8173
+- #phy-cells: must be <0>
+- #clock-cells: must be <0>
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = ;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinc
[PATCH v8 13/13] clk: mediatek: remove hdmitx_dig_cts from TOP clocks
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 3ae0b88..e0d9994 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -61,7 +61,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst =
{
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
- FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3),
FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
--
2.6.2
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[PATCH v8 10/13] clk: mediatek: make dpi0_sel propagate rate changes
This mux is supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
Changes since v7:
- The hdmi_sel mux is kept to propagate rate changes,
selecting the divider from the driver would only be necessary
for deep color modes, which are not supported.
---
drivers/clk/mediatek/clk-mt8173.c | 2 +-
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 227e356..682b275 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -558,7 +558,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090,
24, 4, 31),
/* CLK_CFG_6 */
- MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0,
3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16,
3, 23),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2,
31),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 32d2e45..b607996 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -83,7 +83,7 @@ struct mtk_composite {
signed char num_parents;
};
-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
_flags) {\
.id = _id, \
.name = _name, \
.mux_reg = _reg,\
@@ -94,9 +94,12 @@ struct mtk_composite {
.divider_shift = -1,\
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents),\
- .flags = CLK_SET_RATE_PARENT, \
+ .flags = _flags,\
}
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)\
+ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
CLK_SET_RATE_PARENT)
+
#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
--
2.6.2
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[PATCH v8 00/13] MT8173 DRM support
Hi,
this MT8173 DRM update changes the clock bindings once more, as the MIPI_TX
D-PHY and the HDMI PHY have internal PLLs that are better abstracted using
the common clock framework. The clock outputs of the PHY modules are routed
to the respective encoders, in the HDMI case by way of the TOP clock module.
I'd like it if Michael or Stephen could take a look at the clock patches and
maybe give an Ack or a Nope for this to be merged through the DRM tree.
Various other issues have been fixed, for more details see the individual
patches.
Some changes since v7:
- Added PLL reference input clocks and output clocks to the MIPI TX D-PHY and
HDMI PHY nodes
- Added HS input clocks to the MIPI DSI encoder nodes
- Dropped the hdmitx_dig_cts clock from the TOP dividers, it is not a child
of tvdpll_445p5m anyway. This clock signal really is provided by the HDMI PHY
- Added "power-domains" properties to all nodes in the MM domain
- Documented the merge and split function block bindings
- Merged Daniel's wait for exclusive fences on incoming framebuffers
using reservation_object_wait_timeout_rcu in .atomic_complete() into
the DRM driver patch. This allowed to drop the drm/atomic-helper
wait_for_fences export patch again.
- Added missing atomic destroy_state callbacks, cleaned up reset callbacks
- Added a pending_planes flag to mtk_crtc so we can atomically update the
plane configuration
- Fixed OD ddp_comp function setup
- Separated enabling MIPI TX phy output from enabling the PLL (via CCF),
this allows to keep the pixel clock running separately from the encoder
output when disabling the crtc, to wait for the last vblank.
- Fixed mtk_dpi_power_on reference counting
- Fill ELD info in the HDMI driver, for future audio support.
- Renamed the MT8173 specific HDMI PHY driver, as MT2701 has a different PHY.
- Update iommus binding to v7 IOMMU patches.
The following patches are needed to cleanly apply the device tree changes on
top of v4.4-rc1:
61aee9342514 ("arm64: dts: mt8173: add MT8173 display PWM driver support node")
from https://github.com/mbgg/linux-mediatek.git v4.4-next/arm64
https://patchwork.kernel.org/patch/7880431/ ("dts: mt8173: Add iommu/smi nodes
for mt8173")
And to build:
https://patchwork.kernel.org/patch/7880301/ ("dt-bindings: mediatek: Add smi
dts binding")
https://patchwork.kernel.org/patch/7880321/ ("memory: mediatek: Add SMI driver")
CK Hu (5):
dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
drm/mediatek: Add DSI sub driver
arm64: dts: mt8173: Add display subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (5):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel propagate rate changes
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
clk: mediatek: remove hdmitx_dig_cts from TOP clocks
.../bindings/display/connector/hdmi-connector.txt | 1 +
.../bindings/display/mediatek/mediatek,disp.txt| 203 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35 +
.../bindings/display/mediatek/mediatek,dsi.txt | 60 ++
.../bindings/display/mediatek/mediatek,hdmi.txt| 148
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 312
drivers/clk/mediatek/clk-mt8173.c | 8 +-
drivers/clk/mediatek/clk-mtk.h | 7 +-
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/mediatek/Kconfig | 22 +
drivers/gpu/drm/mediatek/Makefile | 22 +
drivers/gpu/drm/mediatek/mtk_cec.c | 245 ++
drivers/gpu/drm/mediatek/mtk_cec.h | 25 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 301
drivers/gpu/drm/mediatek/mtk_dpi.c | 737 ++
drivers/gpu/drm/mediatek/mtk_dpi.h | 84 ++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h| 228 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 603 +++
drivers/gpu/drm/mediatek/mtk_drm_crtc.h| 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 275 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 148
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 581 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 55 ++
drivers/gpu/drm/mediatek/mtk_drm_fb.c | 165
drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29
[PATCH v8 01/13] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v7:
- Add 26 MHz PLL reference input clocks and DSI high-speed output clocks
to the MIPI TX D-PHY nodes
- Add HS input clocks to the MIPI DSI encoder nodes
- Add power-domains property to all nodes in the MM domain
- Document the merge and split blocks
---
.../bindings/display/mediatek/mediatek,disp.txt| 203 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35
.../bindings/display/mediatek/mediatek,dsi.txt | 60 ++
3 files changed, 298 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000..db6e77e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,203 @@
+Mediatek display subsystem
+==
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+of frame signal are distributed to the other function blocks by a DISP_MUTEX
+function block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,-disp-", one of
+ "mediatek,-disp-ovl" - overlay (4 layers, blending, csc)
+ "mediatek,-disp-rdma" - read DMA / line buffer
+ "mediatek,-disp-wdma" - write DMA
+ "mediatek,-disp-color" - color processor
+ "mediatek,-disp-aal" - adaptive ambient light controller
+ "mediatek,-disp-gamma" - gamma correction
+ "mediatek,-disp-merge" - merge streams from two RDMA sources
+ "mediatek,-disp-split" - split stream to two encoders
+ "mediatek,-disp-ufoe" - data compression engine
+ "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt
+ "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
+ "mediatek,-disp-mutex" - display mutex
+ "mediatek,-disp-od"- overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block (required, except
for
+ merge and split function blocks).
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+ For most function blocks this is just a single clock input. Only the DSI and
+ DPI controller nodes have multiple clock inputs. These are documented in
+ mediatek,dsi.txt and mediatek,dpi.txt, respectively.
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+ "mediatek,-disp-ovl"
+ "mediatek,-disp-rdma"
+ "mediatek,-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as
defined
+ in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: Should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+
+Examples:
+
+mmsys: clock-controller@1400 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+};
+
+ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ power-domains =
Re: [PATCH v2 1/3] reset: Add shared reset_control_[de]assert variants
Hi Maxime, Am Mittwoch, den 16.12.2015, 11:29 +0100 schrieb Maxime Ripard: > On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote: > > Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard: > > > Hi, > > > > > > On Fri, Dec 11, 2015 at 04:41:58PM +0100, Hans de Goede wrote: > > > > diff --git a/include/linux/reset.h b/include/linux/reset.h > > > > index c4c097d..1cca8ce 100644 > > > > --- a/include/linux/reset.h > > > > +++ b/include/linux/reset.h > > > > @@ -11,6 +11,8 @@ int reset_control_reset(struct reset_control *rstc); > > > > int reset_control_assert(struct reset_control *rstc); > > > > int reset_control_deassert(struct reset_control *rstc); > > > > int reset_control_status(struct reset_control *rstc); > > > > +int reset_control_assert_shared(struct reset_control *rstc); > > > > +int reset_control_deassert_shared(struct reset_control *rstc); > > > > > > Shouldn't that be handled in reset_control_get directly? I think I see your point now. Maybe we should add a flags parameter to reset_control_get and/or wrap it in two versions, reset_control_get_exclusive and reset_control_get_shared (or just add the _shared variant). Then reset_control_get(_exclusive) could return -EBUSY if a reset line is already in use. > > This is about different expectations of the caller. > > A driver calling reset_control_assert expects the reset line to be > > asserted after the call. > > Is that behaviour documented explicitly somewhere? /** * reset_control_assert - asserts the reset line * @rstc: reset controller */ Also, that expected behavior matches the function name, which I like. So I still welcome adding new API calls for the shared/refcounting variant. > > A driver calling reset_control_assert_shared > > just signals that it doesn't care about the state of the reset line > > anymore. > > We could just as well call the two new functions > > reset_control_deassert_get and reset_control_deassert_put. > > What happens if you mix them? What happens if you have several drivers > ignoring this API? The core should give useful error messages and disallow non-shared reset calls on shared lines. > The current default API totally allows to have several drivers getting > the same reset line, and happily poking that reset line without any > way for the others to A) know they're not the single users B) let them > know their device has been reset. That's why I'd like the WARN_ON and error return in reset_control_* when the reset_line reference count is > 1. > And not being able to tell at the consumer level if and when our > device is going to be reset behind our back is a big issue. Because > then, we simply have to expect it can be reset at any point in time, > good luck writing a driver with that expectation. Yes, that is unacceptable. > The reset framework should make sure that the shared case is an > exception, and not the default case (and make sure that it cannot > happen in the default case). Just like for any other framework with > similar resources constraints. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 02/14] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Daniel,
Am Dienstag, den 15.12.2015, 02:57 +0800 schrieb Daniel Kurtz:
> HI Philipp,
>
> This driver is looking really good.
>
> But, still some things to think about (mostly small) inline below...
Most of my answers below seem to be "ok" or some form thereof, but I
have one or two questions regarding the layer_config and crtc_reset
suggestions.
[...]
> > diff --git a/drivers/gpu/drm/mediatek/Kconfig
> > b/drivers/gpu/drm/mediatek/Kconfig
> > new file mode 100644
> > index 000..5343cf1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/Kconfig
> > @@ -0,0 +1,16 @@
> > +config DRM_MEDIATEK
> > + tristate "DRM Support for Mediatek SoCs"
> > + depends on DRM
> > + depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST)
> > + select MTK_SMI
> > + select DRM_PANEL
> > + select DRM_MIPI_DSI
> > + select DRM_PANEL_SIMPLE
> > + select DRM_KMS_HELPER
> > + select IOMMU_DMA
>
> nit: alphabetize these selects ?
Ok.
[...]
> > +#define DISP_REG_OVL_CON(n)(0x0030 + 0x20 * n)
>
> nit: it is recommended to always enclose macro arguments in ():
>
> (0x0030 + 0x20 * (n))
>
> > +#define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * n)
> > +#define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * n)
> > +#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * n)
> > +#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * n)
> > +#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * n)
> > +#define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * n)
Thanks for the pointer, I'll change those.
[...]
> > +static void mtk_ovl_enable_vblank(void __iomem *disp_base)
>
> It would be more consistent to pass struct mtk_ddp_comp *comp to all of these
> functions.
Yes.
> > +{
> > + writel(OVL_FME_CPL_INT, disp_base + DISP_REG_OVL_INTEN);
>
> I think most of these can be writel_relaxed() instead of writel().
>
> > +}
> > +
> > +static void mtk_ovl_disable_vblank(void __iomem *disp_base)
> > +{
> > + writel(0x0, disp_base + DISP_REG_OVL_INTEN);
> > +}
> > +
> > +static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> > +{
> > + writel(0x1, comp->regs + DISP_REG_OVL_EN);
> > +}
> > +
> > +static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
> > +{
> > + writel(0x0, comp->regs + DISP_REG_OVL_EN);
> > +}
> > +
> > +static void mtk_ovl_config(void __iomem *ovl_base,
> > + unsigned int w, unsigned int h, unsigned int vrefresh)
> > +{
> > + if (w != 0 && h != 0)
> > + writel(h << 16 | w, ovl_base + DISP_REG_OVL_ROI_SIZE);
> > + writel(0x0, ovl_base + DISP_REG_OVL_ROI_BGCLR);
> > +
> > + writel(0x1, ovl_base + DISP_REG_OVL_RST);
> > + writel(0x0, ovl_base + DISP_REG_OVL_RST);
>
> These two probably do have to be writel().
Ack.
[...]
> > +static void mtk_ovl_layer_on(void __iomem *ovl_base, unsigned int idx)
> > +{
> > + unsigned int reg;
> > +
> > + writel(0x1, ovl_base + DISP_REG_OVL_RDMA_CTRL(idx));
> > + writel(OVL_RDMA_MEM_GMC, ovl_base + DISP_REG_OVL_RDMA_GMC(idx));
> > +
> > + reg = readl(ovl_base + DISP_REG_OVL_SRC_CON);
> > + reg = reg | (1 << idx);
>
> nit(?):
> reg |= BIT(idx);
>
> > + writel(reg, ovl_base + DISP_REG_OVL_SRC_CON);
> > +}
> > +
> > +static void mtk_ovl_layer_off(void __iomem *ovl_base, unsigned int idx)
> > +{
> > + unsigned int reg;
> > +
> > + reg = readl(ovl_base + DISP_REG_OVL_SRC_CON);
> > + reg = reg & ~(1 << idx);
>
> nit(?):
> reg &= ~BIT(idx);
Ok.
[...]
> > +static void mtk_ovl_layer_config(void __iomem *ovl_base, unsigned int idx,
> > + struct mtk_plane_state *state)
> > +{
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int addr = pending->addr;
> > + unsigned int pitch = pending->pitch & 0x;
> > + unsigned int fmt = pending->format;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int src_size = (pending->height << 16) | pending->width;
> > + unsigned int con;
> > +
> > + con = has_rb_swapped(fmt) << 24 | ovl_fmt_convert(fmt) << 12;
>
> Call these conversion routines earlier (during atomic_check) and just add the
> resulting "con" value to pending.
You mean to add a .layer_atomic_check callback to the mtk_ddp_comp ops?
[...]
> > +/**
> > + * struct mtk_drm_crtc - MediaTek specific crtc structure.
> > + * @base: crtc object.
> > + * @pipe: a crtc index created at load() with a new crtc object creation
> > + * and the crtc object would be set to private->crtc array
> > + * to get a crtc object corresponding to this pipe from private->crtc
> > + * array when irq interrupt occurred. the reason of using this pipe is
> > that
> > + * drm framework doesn't support multiple irq yet.
> > + * we can refer to the crtc to current hardware interrupt occurred
> > through
> > + * this pipe valu
Re: [PATCH v2 2/3] ehci-platform: Add support for controllers with multiple reset lines
Am Freitag, den 11.12.2015, 19:28 +0100 schrieb Hans de Goede: [...] > >> diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt > >> b/Documentation/devicetree/bindings/usb/usb-ehci.txt > >> index a12d601..0701812 100644 > >> --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt > >> +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt > >> @@ -18,7 +18,7 @@ Optional properties: > >>- clocks : a list of phandle + clock specifier pairs > >>- phys : phandle + phy specifier pair > >>- phy-names : "usb" > >> - - resets : phandle + reset specifier pair > >> + - resets : a list of phandle + reset specifier pairs > > > > Are there documented names for these resets? > > This binding is a generic ehci controller binding, so even if > the names are documented for the allwinner SoC we should > not use names, just like the binding is deliberately not > using names for the clocks either to keep it generic, so > that we can reuse the binding + driver with many different SoCs. I know, I'm just interested in understanding why this is necessary ... > > Is the companion you > > mention the Port Control? > > Sort of, with USB-2, USB-1 compatibility is handled via a mux on the > datalines (controlled by the EHCI controller Port Control) which muxes > the lines to an USB-1 controller (typically either UHCI or OHCI) when the > device does not connect after USB-2 highspeed handshaking. > > This USB-1 controller (or controller_S_ in some case since the > USB-1 companions may have less root-ports per controller then the EHCI > has root-ports) is called the companion controller. > > The 2 controllers are supposed to be 100% independent but on the H3 > Allwinner has done something (not documented) which requires one to > deassert reset on both before you can talk to either one. ... so thank you for the explanation. Acked-by: Philipp Zabel regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/3] reset: Add shared reset_control_[de]assert variants
Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard: > Hi, > > On Fri, Dec 11, 2015 at 04:41:58PM +0100, Hans de Goede wrote: > > diff --git a/include/linux/reset.h b/include/linux/reset.h > > index c4c097d..1cca8ce 100644 > > --- a/include/linux/reset.h > > +++ b/include/linux/reset.h > > @@ -11,6 +11,8 @@ int reset_control_reset(struct reset_control *rstc); > > int reset_control_assert(struct reset_control *rstc); > > int reset_control_deassert(struct reset_control *rstc); > > int reset_control_status(struct reset_control *rstc); > > +int reset_control_assert_shared(struct reset_control *rstc); > > +int reset_control_deassert_shared(struct reset_control *rstc); > > Shouldn't that be handled in reset_control_get directly? This is about different expectations of the caller. A driver calling reset_control_assert expects the reset line to be asserted after the call. A driver calling reset_control_assert_shared just signals that it doesn't care about the state of the reset line anymore. We could just as well call the two new functions reset_control_deassert_get and reset_control_deassert_put. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/3] reset: Add shared reset_control_[de]assert variants
Hi Hans,
Am Freitag, den 11.12.2015, 19:21 +0100 schrieb Hans de Goede:
[...]
> >> @@ -119,13 +134,55 @@ EXPORT_SYMBOL_GPL(reset_control_assert);
> >> int reset_control_deassert(struct reset_control *rstc)
> >> {
> >
> > Maybe WARN_ON(rstc->line->refcnt > 1) ?
>
> I assume you mean deasser_cnt ? Seems reasonable with that change.
I meant refcnt. Currently drivers sharing reset lines (refcnt > 1)
and then using the non-shared reset control functions are bound to cause
unexpected behaviour. Now we can detect this for the first time.
> >>if (rstc->rcdev->ops->deassert)
> >> - return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id);
> >> + return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->line->id);
> >>
> >>return -ENOTSUPP;
> >> }
> >> EXPORT_SYMBOL_GPL(reset_control_deassert);
> >>
> >> /**
> >> + * reset_control_assert_shared - asserts a shared reset line
> >> + * @rstc: reset controller
> >> + *
> >> + * Assert a shared reset line, this functions decreases the deassert count
> >> + * of the line by one and asserts it if, and only if, the deassert count
> >> + * reaches 0.
> >
> > "After calling this function the shared reset line may be asserted, or
> > it may still be deasserted, as long as other users keep it so."
>
> I take it this is to replace the text about "deassert count" ?
I thought you might append something like it. I just imagine that when
reading the documentation it might be helpful to also see the intended
effect described, especially given that a call to an _assert_ function
might leave the reset line in deasserted state, depending on the
refcount.
> >> + */
> >> +int reset_control_assert_shared(struct reset_control *rstc)
> >> +{
> >> + if (!rstc->rcdev->ops->assert)
> >> + return -ENOTSUPP;
> >
> > WARN_ON(rstc->line->deassert_cnt == 0)
> >
> > Actually, what to do in this case? Assume ops->assert was called, or do
> > it again to be sure? Certainly we don't want to wrap deassert_cnt, or
> > the next deassert_shared will do nothing.
> >
> >> + rstc->line->deassert_cnt--;
> >> + if (rstc->line->deassert_cnt)
> >
> > deassert_cnt isn't protected by any lock.
>
> Right, good catch. I believe the best way to fix this is to change
> deassert_cnt
> into an atomic_t and use atomic_dec_return / atomic_int_return,
Yes, that would work.
> Downside of using an atomic_t is that doing the WARN_ON you are asking for
> above
> will not be race free, then, but since it is a should never happen scenario I
> guess we do not care about the check not being 100% race free. Or we can even
> just leave out the check ?
Since this is only a warning to notify driver developers we don't
support shared resets (apart from the clock-like use)
Not if we warn about refcnt instead of deassert_cnt above.
[...]
> >> + * of the line by one and deasserts the reset line (if it was not already
> >> + * deasserted).
> >
> > "After calling this function, the shared reset line is guaranteed to be
> > deasserted."
>
> Same question as above.
Same imprecise answer. I'd like to see the expected state after calling
this function in the description, in addition to the mechanism. This is
more important for the assert function. After calling deassert, the
reset line is deasserted, no reason to be surprised about that.
regards
Philipp
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Re: [PATCH v7 02/14] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Matthias, thanks for your reply. It would be helpful if you could trim the quoted text a bit when replying to a small part of a huge patch like this. Am Freitag, den 11.12.2015, 18:10 +0100 schrieb Matthias Brugger: > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > new file mode 100644 > > index 000..a34c765 > > --- /dev/null > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -0,0 +1,562 @@ > > +/* > > + * Copyright (c) 2015 MediaTek Inc. > > + * Author: YT SHEN > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > Do we need this include here? No, thank you for noticing. Will be removed in the next version. best regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/3] reset: Add shared reset_control_[de]assert variants
Hi Hans,
thanks for moving this forward.
Am Freitag, den 11.12.2015, 16:41 +0100 schrieb Hans de Goede:
> Add reset_control_deassert_shared / reset_control_assert_shared
> functions which are intended for use by drivers for hw blocks which
> (may) share a reset line with another driver / hw block.
>
> Unlike the regular reset_control_[de]assert functions these functions
> keep track of how often deassert_shared / assert_shared have been called
> and keep the line deasserted as long as deassert has been called more
> times than assert.
>
> Signed-off-by: Hans de Goede
> ---
> Changes in v2:
> -This is a new patch in v2 of this patch-set
> ---
> drivers/reset/core.c | 121
> ---
> include/linux/reset-controller.h | 2 +
> include/linux/reset.h| 2 +
> 3 files changed, 116 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/reset/core.c b/drivers/reset/core.c
> index 9ab9290..8c3436c 100644
> --- a/drivers/reset/core.c
> +++ b/drivers/reset/core.c
> @@ -22,16 +22,29 @@ static DEFINE_MUTEX(reset_controller_list_mutex);
> static LIST_HEAD(reset_controller_list);
>
> /**
> + * struct reset_line - a reset line
> + * @list: list entry for the reset controllers reset line list
> + * @id: ID of the reset line in the reset controller device
> + * @refcnt: Number of reset_control structs referencing this device
> + * @deassert_cnt: Number of times this reset line has been deasserted
> + */
> +struct reset_line {
> + struct list_head list;
> + unsigned int id;
> + unsigned int refcnt;
> + unsigned int deassert_cnt;
> +};
I'd move rcdev into reset_line, too. That way the description is
complete, and we don't duplicate rcdev when there are multiple
reset_controls pointing here.
> +/**
> * struct reset_control - a reset control
> * @rcdev: a pointer to the reset controller device
> * this reset control belongs to
> - * @id: ID of the reset controller in the reset
> - * controller device
> + * @line: reset line for this reset control
> */
> struct reset_control {
> struct reset_controller_dev *rcdev;
> + struct reset_line *line;
> struct device *dev;
> - unsigned int id;
> };
>
> /**
[...]
> @@ -119,13 +134,55 @@ EXPORT_SYMBOL_GPL(reset_control_assert);
> int reset_control_deassert(struct reset_control *rstc)
> {
Maybe WARN_ON(rstc->line->refcnt > 1) ?
> if (rstc->rcdev->ops->deassert)
> - return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id);
> + return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->line->id);
>
> return -ENOTSUPP;
> }
> EXPORT_SYMBOL_GPL(reset_control_deassert);
>
> /**
> + * reset_control_assert_shared - asserts a shared reset line
> + * @rstc: reset controller
> + *
> + * Assert a shared reset line, this functions decreases the deassert count
> + * of the line by one and asserts it if, and only if, the deassert count
> + * reaches 0.
"After calling this function the shared reset line may be asserted, or
it may still be deasserted, as long as other users keep it so."
> + */
> +int reset_control_assert_shared(struct reset_control *rstc)
> +{
> + if (!rstc->rcdev->ops->assert)
> + return -ENOTSUPP;
WARN_ON(rstc->line->deassert_cnt == 0)
Actually, what to do in this case? Assume ops->assert was called, or do
it again to be sure? Certainly we don't want to wrap deassert_cnt, or
the next deassert_shared will do nothing.
> + rstc->line->deassert_cnt--;
> + if (rstc->line->deassert_cnt)
deassert_cnt isn't protected by any lock.
> + return 0;
> +
> + return rstc->rcdev->ops->assert(rstc->rcdev, rstc->line->id);
> +}
> +EXPORT_SYMBOL_GPL(reset_control_assert_shared);
> +
> +/**
> + * reset_control_deassert_shared - deasserts a shared reset line
> + * @rstc: reset controller
> + *
> + * Assert a shared reset line, this functions increases the deassert count
Deassert
> + * of the line by one and deasserts the reset line (if it was not already
> + * deasserted).
"After calling this function, the shared reset line is guaranteed to be
deasserted."
> + */
> +int reset_control_deassert_shared(struct reset_control *rstc)
> +{
> + if (!rstc->rcdev->ops->deassert)
> + return -ENOTSUPP;
> +
> + rstc->line->deassert_cnt++;
> + if (rstc->line->deassert_cnt != 1)
> + return 0;
> +
> + return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->line->id);
> +}
> +EXPORT_SYMBOL_GPL(reset_control_deassert_shared);
> +
> +/**
> * reset_control_status - returns a negative errno if not supported, a
> * positive value if the reset line is asserted, or zero if the reset
> * line is not asserted.
> @@ -134,12 +191,47 @@ EXPORT_SYMBOL_GPL(reset_control_deassert);
> int reset_control_status(struct reset_control *rstc)
> {
> if (rstc->rcdev->ops->status)
> - return rstc->rcdev->ops->status(rstc->rcdev, rstc->id);
>
Re: [PATCH v2 2/3] ehci-platform: Add support for controllers with multiple reset lines
Am Freitag, den 11.12.2015, 16:41 +0100 schrieb Hans de Goede: > From: Reinder de Haan > > At least the EHCI/OHCI found on the Allwinnner H3 SoC needs multiple > reset lines, the controller will not initialize while the reset for > its companion is still asserted, which means we need to de-assert > 2 resets for the controller to work. > > Signed-off-by: Reinder de Haan > Signed-off-by: Hans de Goede > --- > Changes in v2: > -Use the new reset_control_[de]assert_shared reset-controller functions > --- > Documentation/devicetree/bindings/usb/usb-ehci.txt | 2 +- > drivers/usb/host/ehci-platform.c | 47 > +- > 2 files changed, 30 insertions(+), 19 deletions(-) > > diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt > b/Documentation/devicetree/bindings/usb/usb-ehci.txt > index a12d601..0701812 100644 > --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt > +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt > @@ -18,7 +18,7 @@ Optional properties: > - clocks : a list of phandle + clock specifier pairs > - phys : phandle + phy specifier pair > - phy-names : "usb" > - - resets : phandle + reset specifier pair > + - resets : a list of phandle + reset specifier pairs Are there documented names for these resets? Is the companion you mention the Port Control? regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] rtc: add driver for RX6110SA real time clock
Am Dienstag, den 08.12.2015, 10:54 +0100 schrieb Steffen Trumtrar:
> The RX6110 comes in two different variants: SPI and I2C.
> This driver only supports the SPI variant.
>
> If the need ever arises to also support the I2C variant, this driver
> could easily be refactored to support both cases.
>
> Signed-off-by: Steffen Trumtrar
Reviewed-by: Philipp Zabel
I have a few suggestions:
[...]
> diff --git a/drivers/rtc/rtc-rx6110.c b/drivers/rtc/rtc-rx6110.c
> new file mode 100644
> index ..aa9d89d5d2de
> --- /dev/null
> +++ b/drivers/rtc/rtc-rx6110.c
> @@ -0,0 +1,438 @@
> +/*
> + * Driver for the Epson RTC module RX-6110 SA
> + *
> + * Copyright(C) 2015 Pengutronix, Steffen Trumtrar
> + * Copyright(C) SEIKO EPSON CORPORATION 2013. All rights reserved.
> + *
> + * This driver software is distributed as is, without any warranty of any
> kind,
> + * either express or implied as further specified in the GNU Public License.
> + * This software may be used and distributed according to the terms of the
> GNU
> + * Public License, version 2 as published by the Free Software Foundation.
> + * See the file COPYING in the main directory of this archive for more
> details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
I think these three can be dropped.
> +#include
> +#include
> +#include
> +
> +/* RX-6110 Register definitions */
[...]
> +
> +static struct spi_driver rx6110_driver;
Several drivers do this. Instead of the forward declaration and using
rx6110_driver.driver.name in devm_rtc_device_register below, why not
just have a #define RX6110_DRIVER_NAME "rx6110-rtc" and reuse that?
Actually, I think the "-rtc" suffix is superfluous in the rtc name.
I'd just use "rx6110" as a parameter to devm_rtc_device_register.
> +struct rx6110_data {
> + struct rtc_device *rtc;
> + struct regmap *regmap;
> +};
[...]
> +/**
> + * rx6110_init - initialize the rx6110 registers
> + *
> + * @rx6110: pointer to the rx6110 struct in use
> + *
> + */
> +static int rx6110_init(struct rx6110_data *rx6110)
> +{
> + struct rtc_device *rtc = rx6110->rtc;
> + int ext;
> + int flags;
> + int ctrl;
ctrl is unused, except in the dev_dbg to print 0 below.
> + int ret;
> +
> + /* set reserved register 0x17 with specified value of 0xB8 */
> + ret = regmap_write(rx6110->regmap, RX6110_REG_RES1, 0xB8);
> + if (ret)
> + return ret;
> +
> + /* set reserved register 0x30 with specified value of 0x00 */
> + ret = regmap_write(rx6110->regmap, RX6110_REG_RES2, 0x00);
> + if (ret)
> + return ret;
> +
> + /* set reserved register 0x31 with specified value of 0x10 */
> + ret = regmap_write(rx6110->regmap, RX6110_REG_RES3, 0x10);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(rx6110->regmap, RX6110_REG_IRQ, 0x0);
> + if (ret)
> + return ret;
Maybe combine those using regmap_multi_reg_write? Not sure if the
sequence can be reordered to also include the writes below.
> + ret = regmap_update_bits(rx6110->regmap, RX6110_REG_EXT,
> + RX6110_BIT_EXT_TE, 0);
> + if (ret)
> + return ret;
> +
> + /* get current extension, flag, control register values */
> + ret = regmap_read(rx6110->regmap, RX6110_REG_EXT, &ext);
> + if (ret)
> + return ret;
> +
> + ret = regmap_read(rx6110->regmap, RX6110_REG_FLAG, &flags);
> + if (ret)
> + return ret;
> +
> + /* clear ctrl register */
> + ret = regmap_write(rx6110->regmap, RX6110_REG_CTRL, 0);
> + if (ret)
> + return ret;
> +
> + ctrl = 0;
This is unused ...
> + ret = regmap_write(rx6110->regmap, RX6110_REG_ALMIN, 0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(rx6110->regmap, RX6110_REG_ALHOUR, 0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(rx6110->regmap, RX6110_REG_ALWDAY, 0);
> + if (ret)
> + return ret;
> +
> + dev_dbg(&rtc->dev, "ext: %x, flag: %x, ctrl: %x\n", ext, flags, ctrl);
... except here.
> +
> + /* check for VLF Flag (set at power-on) */
> + if ((flags & RX6110_BIT_FLAG_VLF))
> + dev_warn(&rtc->dev, "Voltage low, data loss detected.\n");
> +
>
Re: [PATCH v3 1/2] Documentation: devicetree: add epson rx6110 binding
Am Dienstag, den 08.12.2015, 10:54 +0100 schrieb Steffen Trumtrar: > Add the binding documentation for the Epson RX6110 RTC. > > Acked-by: Rob Herring > Signed-off-by: Steffen Trumtrar Reviewed-by: Philipp Zabel although I'd like a small change to be made below: > --- > Changes since v2: > - removed the size field in i2c binding > > .../devicetree/bindings/rtc/epson,rx6110.txt | 39 > ++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/epson,rx6110.txt > > diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > new file mode 100644 > index ..71353542a59d > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > @@ -0,0 +1,39 @@ > +Epson RX6110 Real Time Clock > + > + > +The Epson RX6110 can be used with SPI or I2C busses. The kind of > +bus depends on the SPISEL pin and can not be configured via software. > + > +I2C mode > + > + > +Required properties: > + - compatible: should be: "epson,rx6110" > + - reg : offset of the register set of the device That should be the I2C address of the device: git grep "reg.*I2C address" Documentation/ regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] Documentation: devicetree: add epson rx6110 binding
Am Dienstag, den 08.12.2015, 10:54 +0100 schrieb Steffen Trumtrar: > Add the binding documentation for the Epson RX6110 RTC. > > Acked-by: Rob Herring > Signed-off-by: Steffen Trumtrar Reviewed-by: Philipp Zabel although I'd like a small change to be made below: > --- > Changes since v2: > - removed the size field in i2c binding > > .../devicetree/bindings/rtc/epson,rx6110.txt | 39 > ++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/epson,rx6110.txt > > diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > new file mode 100644 > index ..71353542a59d > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt > @@ -0,0 +1,39 @@ > +Epson RX6110 Real Time Clock > + > + > +The Epson RX6110 can be used with SPI or I2C busses. The kind of > +bus depends on the SPISEL pin and can not be configured via software. > + > +I2C mode > + > + > +Required properties: > + - compatible: should be: "epson,rx6110" > + - reg : offset of the register set of the device That should be the I2C address of the device, as in: git grep "reg.*I2C address" Documentation/ regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] doc: dt-binding: generic onboard USB HUB
Hi Peter,
Am Dienstag, den 08.12.2015, 09:37 +0800 schrieb Peter Chen:
> Add dt-binding documentation for generic onboard USB HUB.
>
> Signed-off-by: Peter Chen
> ---
> .../bindings/usb/generic-onboard-hub.txt | 28
> ++
> 1 file changed, 28 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/generic-onboard-hub.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/generic-onboard-hub.txt
> b/Documentation/devicetree/bindings/usb/generic-onboard-hub.txt
> new file mode 100644
> index 000..ea92205
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/generic-onboard-hub.txt
> @@ -0,0 +1,28 @@
> +Generic Onboard USB HUB
>+
> +Required properties:
> +- compatible: should be "generic-onboard-hub"
This something we don't have to define ad-hoc. The hub hangs off an USB
controller, right? The "Open Firmware recommended practice: USB"
document already describes how to represent USB devices in a generic
manner:
http://www.firmware.org/1275/bindings/usb/usb-1_0.ps
Is there a reason not to reuse this?
The usb hub node would be a child of the usb controller node, and it
could use
compatible = "usb,class9"; /* bDeviceClass 9 (Hub) */
> +Optional properties:
> +- clocks: the input clock for HUB.
> +
> +- clock-names: Should be "external_clk"
Is clock-names necessary for a single clock?
> +- hub-reset-gpios: Should specify the GPIO for reset.
I'd prefer that to be just "reset-gpios", it is the only reset property
in the hub node after all. And use the GPIO_ACTIVE_HIGH/LOW flags to
indicate polarity.
> +- hub-reset-active-high: the active reset signal is high, if this property is
> + not set, the active reset signal is low.
Then this could be dropped.
> +- hub-reset-duration-us: the duration for assert reset signal, the time unit
> + is microsecond.
And consequently, this could just be called "reset-duration-us".
It might make sense to define the same for other reset GPIOs, too.
The Freescale FEC, for example, has "phy-reset-duration" (in ms)
already.
> +
> +Example:
> +
> + usb_hub1 {
> + compatible = "generic-onboard-hub";
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + clock-names = "external_clk";
> + hub-reset-gpios = <&gpio7 12 0>;
> + hub-reset-active-high;
> + hub-reset-duration-us = <2>;
> + };
best regards
Philipp
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Re: [PATCH v4 1/2] dt-bindings: GPIO: Add gpio-initval
Am Freitag, den 04.12.2015, 14:06 +0100 schrieb Markus Pargmann:
> Add a binding for GPIO initialization.
>
> Signed-off-by: Markus Pargmann
Both patches
Reviewed-by: Philipp Zabel
small nitpick:
> ---
> Documentation/devicetree/bindings/gpio/gpio.txt | 34
> -
> 1 file changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt
> b/Documentation/devicetree/bindings/gpio/gpio.txt
> index 069cdf6f9dac..d11abfa13add 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio.txt
> @@ -155,29 +155,39 @@ gpio-controller@ {
> ngpios = <18>;
> }
>
> -The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
> -providing automatic GPIO request and configuration as part of the
> -gpio-controller's driver probe function.
> +The GPIO chip may contain GPIO definitions. These define properties for
> single
> +GPIOs of this controller.
>
> -Each GPIO hog definition is represented as a child node of the GPIO
> controller.
> +There are two types of GPIO definitions:
> +
> +- GPIO hogging is a mechanism providing automatic GPIO request and
> + configuration as part of the gpio-controller driver's probe function. The
> + GPIO is held until the gpio-controller is removed.
> +- GPIO initialization provides an automatic initialization to known save
safe
regards
Philipp
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Re: [PATCH (v2) 1/2] reset: Add brcm,bcm6345-reset device tree binding
Hi Simon,
Am Mittwoch, den 02.12.2015, 21:03 + schrieb Simon Arlott:
> Add device tree binding for the BCM6345 soft reset controller.
>
> The BCM6345 contains a soft-reset controller activated by setting
> a bit (that must previously have cleared).
>
> Signed-off-by: Simon Arlott
> ---
> Renamed to bcm6345, removed "mask" property.
>
> .../bindings/reset/brcm,bcm6345-reset.txt | 33
> ++
> 1 file changed, 33 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.txt
> b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.txt
> new file mode 100644
> index 000..bb9ca6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.txt
> @@ -0,0 +1,33 @@
> +Broadcom BCM6345 reset controller
> +
> +The BCM6345 contains a basic soft reset controller in the perf register
> +set which resets components using a bit in a register.
> +
> +Please also refer to reset.txt in this directory for common reset
> +controller binding usage.
> +
> +Required properties:
> +- compatible:Should be "brcm,bcm-reset", "brcm,bcm6345-reset"
> +- regmap:The register map phandle
> +- offset:Offset in the register map for the reset register (in bytes)
Is this something the device tree maintainers are happy with?
I see there are already some regmap properties in the device tree, but
in this case it looks to me like the reset controller node should be a
child of the periph_cntl node as that register space is the only means
of controlling it.
> +- #reset-cells: Must be set to 1
> +
> +Example:
> +
> +periph_soft_rst: reset-controller {
> + compatible = "brcm,bcm63168-reset", "brcm,bcm6345-reset";
> + regmap = <&periph_cntl>;
> + offset = <0x10>;
> +
> + #reset-cells = <1>;
> +};
I would have written it something like this:
periph_cntl: ... {
compatible = "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
periph_soft_rst: reset-controller {
compatible = "brcm,bcm6345-reset";
reg = <0x10 0x4>;
#reset-cells = <1>;
};
};
for a device that is only controlled through a syscon.
The driver itself looks good to me.
best regards
Philipp
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[PATCH v7 03/14] drm/mediatek: Add DSI sub driver
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v6:
- Added mtk_dsi_poweron/off refcounting and mtk_ddp_component start/stop
callbacks to keep pixel clock enabled until crtc_disable
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 838 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 57 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 377 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 21 +
7 files changed, 1300 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index bd6e8df..573f209 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,7 +5,9 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_drm_drv.o \
mtk_drm_fb.o \
mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a34c765..739c3e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -521,6 +521,8 @@ static struct platform_driver mtk_drm_platform_driver = {
static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_drm_platform_driver,
&mtk_disp_ovl_driver,
+ &mtk_dsi_driver,
+ &mtk_mipi_tx_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index df421cd..3b5b254 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,5 +49,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..5b7eea4
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,838 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dsi.h"
+#include "mtk_mipi_tx.h"
+
+#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START 0x00
+
+#define DSI_CON_CTRL 0x10
+#define DSI_RESET BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL 0x14
+#define MODE (3)
+#define CMD_MODE 0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE BIT(16)
+#define MIX_MODE BIT(17)
+
+#define DSI_TXRX_CTRL 0x18
+#define VC_NUM (2 << 0)
+#define LANE_NUM (0xf << 2)
+#define DIS_EOTBIT(6)
+#define NULL_ENBIT(7)
+#define TE_FREERUN BIT(8)
+#define EXT_TE_EN BIT(9)
+#define EXT_TE_EDGEBIT(10)
+#define MAX_RTN_SIZE (0xf << 12)
+#define HSTX_CKLP_EN BIT(16)
+
+#define DSI_PSCTRL 0x1c
+#define DSI_PS_WC 0x3fff
+#define DSI_PS_SEL (3 << 16)
+#define PACKED_PS_16BIT_RGB565 (0 << 16)
+#define LOOSELY_PS_18BIT_RGB666(1 << 16)
+#define PACKED_PS_18BIT_RGB666 (2 << 16)
+#define PACKED_PS_24BIT_RGB888 (3 << 16)
+
+#define
[PATCH v7 13/14] drm/atomic-helper: Export drm_atomic_helper_wait_for_fences
From: Daniel Kurtz
This is useful for drivers that want to implement async commits, but
need to wait on per-plane fences.
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/drm_atomic_helper.c | 7 ---
include/drm/drm_atomic_helper.h | 2 ++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 0c6f621..ce84d99 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -886,8 +886,8 @@ void drm_atomic_helper_commit_modeset_enables(struct
drm_device *dev,
}
EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables);
-static void wait_for_fences(struct drm_device *dev,
- struct drm_atomic_state *state)
+void drm_atomic_helper_wait_for_fences(struct drm_device *dev,
+ struct drm_atomic_state *state)
{
struct drm_plane *plane;
struct drm_plane_state *plane_state;
@@ -904,6 +904,7 @@ static void wait_for_fences(struct drm_device *dev,
plane->state->fence = NULL;
}
}
+EXPORT_SYMBOL(drm_atomic_helper_wait_for_fences);
static bool framebuffer_changed(struct drm_device *dev,
struct drm_atomic_state *old_state,
@@ -1049,7 +1050,7 @@ int drm_atomic_helper_commit(struct drm_device *dev,
* current layout.
*/
- wait_for_fences(dev, state);
+ drm_atomic_helper_wait_for_fences(dev, state);
drm_atomic_helper_commit_modeset_disables(dev, state);
diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
index 8cba54a..92b5699 100644
--- a/include/drm/drm_atomic_helper.h
+++ b/include/drm/drm_atomic_helper.h
@@ -42,6 +42,8 @@ int drm_atomic_helper_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool async);
+void drm_atomic_helper_wait_for_fences(struct drm_device *dev,
+ struct drm_atomic_state *state);
void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
struct drm_atomic_state *old_state);
--
2.6.2
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[PATCH v7 11/14] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index b305fa2..d7eadda 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -1091,6 +1091,11 @@ static void __init mtk_apmixedsys_init(struct
device_node *node)
clk_data->clks[cku->id] = clk;
}
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+ base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h
b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1..6094bf7 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
#define CLK_APMIXED_LVDSPLL13
#define CLK_APMIXED_MSDCPLL2 14
#define CLK_APMIXED_REF2USB_TX 15
-#define CLK_APMIXED_NR_CLK 16
+#define CLK_APMIXED_HDMI_REF 16
+#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */
--
2.6.2
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[PATCH v7 02/14] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
From: CK Hu This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu Signed-off-by: YT Shen Signed-off-by: Philipp Zabel --- Changes since v6: - Split disp_ovl driver from mtk_drm_crtc code - Added crtc and plane state atomic reset functions - Toned down debug messages - Improved error handling for hardware initialization - Get/put smi_larb in crtc_enable/disable - Added memory barrier before marking crtc state as ready - Changed crtc_disable to wait for vblank - Renamed component power_on/off to start/stop - Made component ops optional - Moved crtc creation from disp_ovl driver bind callback into mtk_drm_kms_init - Various fixes - Added support for DRIVER_PRIME feature - Moved DISP_OVL, DSI, DPI and component initialization into the respective drivers --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile| 1 + drivers/gpu/drm/mediatek/Kconfig| 16 + drivers/gpu/drm/mediatek/Makefile | 11 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 301 +++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 565 drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 31 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 + drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 275 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 148 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 562 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 53 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.c | 135 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.h | 28 ++ drivers/gpu/drm/mediatek/mtk_drm_gem.c | 227 +++ drivers/gpu/drm/mediatek/mtk_drm_gem.h | 55 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.c| 238 drivers/gpu/drm/mediatek/mtk_drm_plane.h| 58 +++ 19 files changed, 3102 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/Kconfig create mode 100644 drivers/gpu/drm/mediatek/Makefile create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4bf9a1..8fdb0c2 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -266,3 +266,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" + +source "drivers/gpu/drm/mediatek/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 1e9ff4c..607a49f 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ +obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig new file mode 100644 index 000..5343cf1 --- /dev/null +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -0,0 +1,16 @@ +config DRM_MEDIATEK + tristate "DRM Support for Mediatek SoCs" + depends on DRM + depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST) + select MTK_SMI + select DRM_PANEL + select DRM_MIPI_DSI + select DRM_PANEL_SIMPLE + select DRM_KMS_HELPER + select IOMMU_DMA + help + Choose this option if you have a Mediatek SoCs. + The module will be called mediatek-drm + This driver provides kernel mode setting and + buffer management to userspace. + diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile new file mode 100644 index 000..bd6e8df --- /dev/null +++ b/drivers/gpu/drm/mediatek/Makefile @@ -0,0 +1,11 @@ +mediatek-drm-y := mtk_disp_ovl.o \ + mtk_drm_crtc.o \ +
[PATCH v7 14/14] drm/mediatek: Add fence control, wait on GPU fence
Wait on the exclusive fence for the incoming framebuffer, using
"wait_for_fences" from drm_atomic_helper.c, which needs to be exported
first.
Signed-off-by: CK Hu
Signed-off-by: YT Shen
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 36 ++--
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 22 ---
4 files changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ec0540f..69e8fe5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -65,6 +65,8 @@ struct mtk_crtc_state {
struct drm_crtc_state base;
struct drm_pending_vblank_event *event;
+ boolpending_needs_vblank;
+
boolpending_config;
unsigned intpending_width;
unsigned intpending_height;
@@ -100,10 +102,24 @@ static void mtk_drm_crtc_finish_page_flip(struct
mtk_drm_crtc *mtk_crtc)
{
struct drm_crtc *crtc = &mtk_crtc->base;
struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
+ unsigned long flags;
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
drm_send_vblank_event(crtc->dev, state->event->pipe, state->event);
drm_crtc_vblank_put(crtc);
state->event = NULL;
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+}
+
+static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
+{
+ struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
+
+ drm_handle_vblank(mtk_crtc->base.dev, mtk_crtc->pipe);
+ if (state->pending_needs_vblank) {
+ mtk_drm_crtc_finish_page_flip(mtk_crtc);
+ state->pending_needs_vblank = false;
+ }
}
static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
@@ -391,10 +407,26 @@ void mtk_drm_crtc_commit(struct drm_crtc *crtc)
}
}
+void mtk_drm_crtc_check_flush(struct drm_crtc *crtc)
+{
+ struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+
+ if (mtk_crtc->do_flush) {
+ if (state->event)
+ state->pending_needs_vblank = true;
+ mtk_drm_crtc_commit(crtc);
+ mtk_crtc->do_flush = false;
+ }
+}
+
static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
- mtk_drm_crtc_commit(crtc);
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+
+ mtk_crtc->do_flush = true;
+ mtk_drm_crtc_check_flush(crtc);
}
static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -482,7 +514,7 @@ void mtk_crtc_ddp_irq(struct drm_device *drm_dev, struct
mtk_ddp_comp *ovl)
}
}
- drm_handle_vblank(mtk_crtc->base.dev, mtk_crtc->pipe);
+ mtk_drm_finish_page_flip(mtk_crtc);
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index f04854f..94eba3c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -22,6 +22,7 @@
int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe);
void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe);
+void mtk_drm_crtc_check_flush(struct drm_crtc *crtc);
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
void mtk_crtc_ddp_irq(struct drm_device *drm_dev, struct mtk_ddp_comp *ovl);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 2d5bd16..e6d8adf 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -49,6 +49,8 @@ static void mtk_atomic_complete(struct mtk_drm_private
*private,
{
struct drm_device *drm = private->drm;
+ drm_atomic_helper_wait_for_fences(drm, state);
+
drm_atomic_helper_commit_modeset_disables(drm, state);
drm_atomic_helper_commit_planes(drm, state, false);
drm_atomic_helper_commit_modeset_enables(drm, state);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index c0b62d1..343c060 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -123,6 +123,8 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct drm_framebuffer *fb = state
[PATCH v7 04/14] drm/mediatek: Add DPI sub driver
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v6:
- Added mtk_dpi_power_on/off refcounting and mtk_ddp_component start/stop
callbacks to keep pixel clock enabled until crtc_disable
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 744
drivers/gpu/drm/mediatek/mtk_dpi.h | 84
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 1060 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 573f209..cee9b23 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -7,7 +7,8 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..1a2cd9f
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,744 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dpi.h"
+#include "mtk_dpi_regs.h"
+
+enum mtk_dpi_polarity {
+ MTK_DPI_POLARITY_RISING,
+ MTK_DPI_POLARITY_FALLING,
+};
+
+struct mtk_dpi_polarities {
+ enum mtk_dpi_polarity de_pol;
+ enum mtk_dpi_polarity ck_pol;
+ enum mtk_dpi_polarity hsync_pol;
+ enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+ u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+ tmp |= (val & mask);
+ writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+ mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+}
+
+static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync,
+u32 width_addr, u32 porch_addr)
+{
+ mtk_dpi_mask(dpi, width_addr,
+sync->sync_width << VSYNC_WIDTH_SHIFT,
+VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, width_addr,
+sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+VSYNC_HALF_LINE_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+VSYNC_FRONT_PORCH_MASK);
+}
+
+static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
+}
+
+static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
+
[PATCH v7 08/14] arm64: dts: mt8173: Add display subsystem related nodes
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
TODO:
- The power-domain property should be added to all blocks
that are in the MM power domain.
- The iommus property should be removed from the mmsys node.
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 211 +++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 68010d9..e185f88 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -286,6 +303,18 @@
#clock-cells = <1>;
};
+ mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
+ mipi_tx1: mipi-dphy@10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
gic: interrupt-controller@1022 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -432,6 +461,14 @@
status = "disabled";
};
+ hdmiddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = ;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
i2c6: i2c@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@@ -568,7 +605,167 @@
mmsys: clock-controller@1400 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
+
+ /* FIXME - remove iommus here */
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>,
+<&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ };
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x140
[PATCH v7 12/14] dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
Add an optional ddc-i2c-bus phandle property that points to an I2C master controller that handles the connector DDC pins. Signed-off-by: Philipp Zabel Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt index acd5668..508aee4 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing Required nodes: - Video port for HDMI input -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 09/14] arm64: dts: mt8173: Add HDMI related nodes
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index e185f88..13a11ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -199,6 +199,30 @@
,
;
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux =
;
+ input-enable;
+ bias-pull-down;
+ };
+
+ /*hdmi flt 5v pin*/
+ pins2 {
+ pinmux =
;
+ input-enable;
+ bias-pull-up;
+ };
+
+ /*hdmi 5v pin*/
+ pins3 {
+ pinmux =
;
+ output-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux =
,
@@ -277,6 +301,13 @@
clock-names = "spi", "wrap";
};
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
@@ -303,6 +334,16 @@
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+ };
+
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -823,6 +864,36 @@
clock-names = "apb", "smi";
};
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;
--
2.6.2
--
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[PATCH v7 06/14] drm/mediatek: Add HDMI support
From: Jie Qiu This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- Changes since v6: - Removed mtk_hdmi_audio_data / mtk-hdmi-codec platform device creation for now, this will be reworked. --- drivers/gpu/drm/mediatek/Kconfig | 6 + drivers/gpu/drm/mediatek/Makefile| 8 + drivers/gpu/drm/mediatek/mtk_cec.c | 245 + drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c | 609 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 484 + drivers/gpu/drm/mediatek/mtk_hdmi.h | 113 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c | 362 + drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 757 +++ drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 +++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 340 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 20 + drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h | 118 + drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 221 include/drm/mediatek/mtk_hdmi_audio.h| 137 + 16 files changed, 3522 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 include/drm/mediatek/mtk_hdmi_audio.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index 5343cf1..85af51c 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -14,3 +14,9 @@ config DRM_MEDIATEK This driver provides kernel mode setting and buffer management to userspace. +config DRM_MEDIATEK_HDMI + tristate "DRM HDMI Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select GENERIC_PHY + help + DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index cee9b23..d02cc19 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -12,3 +12,11 @@ mediatek-drm-y := mtk_disp_ovl.o \ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o +mediatek-drm-hdmi-objs := mtk_drm_hdmi_drv.o \ + mtk_cec.o \ + mtk_hdmi_ddc_drv.o \ + mtk_hdmi.o \ + mtk_hdmi_hw.o \ + mtk_hdmi_phy.o + +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c new file mode 100644 index 000..c339d2f --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#include "mtk_cec.h" + +#define TR_CONFIG 0x00 +#define CLEAR_CEC_IRQ BIT(15) + +#define CEC_CKGEN 0x04 +#define CEC_32K_PDNBIT(19) +#define PDNBIT(16) + +#define RX_EVENT 0x54 +#define HDMI_PORD BIT(25) +#define HDMI_HTPLG BIT(24) +#define HDMI_PORD_INT_EN BIT(9) +#define HDMI_HTPLG_INT_EN BIT(8) + +#define RX_GEN_WD 0x58 +#define HDMI_PORD_INT_32K_STATUS BIT(26) +#define RX_RISC_INT_32K_STATUS BIT(25) +#define HDMI_HTPLG_INT_32K_STATUS BIT(24) +#define HDMI_PORD_INT_32K_CLR BIT(18) +#define RX_INT_32K_CLR BIT(17) +#define HDMI_HTPLG_INT_32K_CLR BIT(16) +#define HDMI_PORD_INT_32K_STA_MASK BIT(10) +#define RX_RISC_INT_32K_STA_MASK
[PATCH v7 10/14] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 227e356..b305fa2 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -558,7 +558,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090,
24, 4, 31),
/* CLK_CFG_6 */
- MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0,
3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16,
3, 23),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2,
31),
@@ -569,7 +569,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
/* CLK_CFG_12 */
MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents,
0x00c0, 0, 3, 7),
- MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
+ MUX_GATE_FLAGS(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8,
2, 15, 0),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0,
24, 3, 31),
/* CLK_CFG_13 */
MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
0x00d0, 0, 3, 7),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 32d2e45..b607996 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -83,7 +83,7 @@ struct mtk_composite {
signed char num_parents;
};
-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
_flags) {\
.id = _id, \
.name = _name, \
.mux_reg = _reg,\
@@ -94,9 +94,12 @@ struct mtk_composite {
.divider_shift = -1,\
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents),\
- .flags = CLK_SET_RATE_PARENT, \
+ .flags = _flags,\
}
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)\
+ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
CLK_SET_RATE_PARENT)
+
#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
--
2.6.2
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[PATCH v7 07/14] drm/mediatek: enable hdmi output control bit
From: Jie Qiu
MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 7652266..8bee167 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -19,8 +19,15 @@
#include
#include
#include
+#include
#include
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
{
return readl(hdmi->regs + offset);
@@ -170,6 +177,10 @@ void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
{
+ invoke_psci_fn = __invoke_psci_fn_smc;
+ invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+ 0x14000904, 0x8000, 0);
+
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index de7ee22..8d7d60a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -218,4 +218,5 @@
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x8201
#endif
--
2.6.2
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[PATCH v7 01/14] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v6:
- Clarify single clock in clocks property
- Improve iommus property description
---
.../bindings/display/mediatek/mediatek,disp.txt| 187 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
3 files changed, 275 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000..e1b3ce9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,187 @@
+Mediatek display subsystem
+==
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+of frame signal are distributed to the other function blocks by a DISP_MUTEX
+function block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,-disp-", one of
+ "mediatek,-disp-ovl" - overlay (4 layers, blending, csc)
+ "mediatek,-disp-rdma" - read DMA / line buffer
+ "mediatek,-disp-wdma" - write DMA
+ "mediatek,-disp-color" - color processor
+ "mediatek,-disp-aal" - adaptive ambient light controller
+ "mediatek,-disp-gamma" - gamma correction
+ "mediatek,-disp-ufoe" - data compression engine
+ "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt
+ "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
+ "mediatek,-disp-mutex" - display mutex
+ "mediatek,-disp-od"- overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+ For most function blocks this is just a single clock input. Only the DSI and
+ DPI controller nodes have multiple clock inputs. These are documented in
+ mediatek,dsi.txt and mediatek,dpi.txt, respectively.
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+ "mediatek,-disp-ovl"
+ "mediatek,-disp-rdma"
+ "mediatek,-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as
defined
+ in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: Should point to the respective IOMMU block with local arbiter id and
+ master port, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+
+Examples:
+
+mmsys: clock-controller@1400 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+};
+
+ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+};
+
+ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommu
[PATCH v7 00/14] MT8173 DRM support
Hi,
this MT8173 DRM update addresses some issues, mostly reported by Tomasz
Figa, Daniel Kurtz, and YT Shen. It also adds is PRIME support and
two new patches to export drm_atomic_helper's wait_for_fences and use it
in mtk_atomic_complete.
Changes since v6:
- Improved binding documentation
- Split disp_ovl driver from mtk_drm_crtc code
- Added crtc and plane state atomic reset functions
- Toned down debug messages
- Improved error handling for hardware initialization
- Get/put smi_larb in crtc_enable/disable
- Added memory barrier before marking crtc state as ready
- Changed crtc_disable to wait for vblank
- Renamed component power_on/off to start/stop
- Made component ops optional
- Moved crtc creation from disp_ovl driver bind callback into mtk_drm_kms_init
- Added support for DRIVER_PRIME feature
- Moved DISP_OVL, DSI, DPI and component initialization into the respective
drivers
- Added DPI/DSI poweron/off refcounting and mtk_ddp_component start/stop
callbacks to keep pixel clock enabled until crtc_disable, as suggested by CK
- Removed mtk_hdmi_audio_data / mtk-hdmi-codec platform device creation
for now, hdmi audio will be reworked.
The following patches are still needed to apply this on top of v4.4-rc1:
https://patchwork.kernel.org/patch/6825601/ ("arm64: dts: mt8173: add MT8173
display PWM driver support node"),
https://patchwork.kernel.org/patch/7138531/ ("arm64: dts: mediatek: add xHCI &
usb phy for mt8173"),
https://patchwork.kernel.org/patch/6928651/ ("dts: mt8173: Add iommu/smi nodes
for mt8173"), and
And to build:
https://patchwork.kernel.org/patch/6928621/ ("memory: mediatek: Add SMI
driver"),
regards
Philipp
CK Hu (5):
dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
drm/mediatek: Add DSI sub driver
arm64: dts: mt8173: Add display subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Daniel Kurtz (1):
drm/atomic-helper: Export drm_atomic_helper_wait_for_fences
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (5):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
drm/mediatek: Add fence control, wait on GPU fence
.../bindings/display/connector/hdmi-connector.txt | 1 +
.../bindings/display/mediatek/mediatek,disp.txt| 187 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35 +
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
.../bindings/display/mediatek/mediatek,hdmi.txt| 142
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 282 +++
drivers/clk/mediatek/clk-mt8173.c | 9 +-
drivers/clk/mediatek/clk-mtk.h | 7 +-
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/drm_atomic_helper.c| 7 +-
drivers/gpu/drm/mediatek/Kconfig | 22 +
drivers/gpu/drm/mediatek/Makefile | 22 +
drivers/gpu/drm/mediatek/mtk_cec.c | 245 ++
drivers/gpu/drm/mediatek/mtk_cec.h | 25 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 301
drivers/gpu/drm/mediatek/mtk_dpi.c | 744 ++
drivers/gpu/drm/mediatek/mtk_dpi.h | 84 +++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h| 228 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 597 +++
drivers/gpu/drm/mediatek/mtk_drm_crtc.h| 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 275 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 148
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 568 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 56 ++
drivers/gpu/drm/mediatek/mtk_drm_fb.c | 135
drivers/gpu/drm/mediatek/mtk_drm_fb.h | 28 +
drivers/gpu/drm/mediatek/mtk_drm_gem.c | 227 ++
drivers/gpu/drm/mediatek/mtk_drm_gem.h | 55 ++
drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c| 609 +++
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 254 +++
drivers/gpu/drm/mediatek/mtk_drm_plane.h | 58 ++
drivers/gpu/drm/mediatek/mtk_dsi.c | 838 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 57 ++
drivers/gpu/drm/mediatek/mtk_hdmi.c| 484
drivers/gpu/drm/mediatek/mtk_hdmi.h| 113
[PATCH v7 05/14] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 142 +
1 file changed, 142 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 000..e3dde29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,142 @@
+Mediatek HDMI Encoder
+=
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+ configuration registers. For mt8173 this must be offset 0x900 into the
+ MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+- port@1: The output port in the ports node should be connected to the input
+ port of a connector node that contains a ddc-i2c-bus property, or to the
+ input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- #phy-cells: must be <0>.
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = ;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+
Re: [PATCH 1/2] Documentation: devicetree: add epson rx6110 binding
Am Dienstag, den 24.11.2015, 11:38 +0100 schrieb Steffen Trumtrar:
> Add the binding documentation for the Epson RX6110 RTC.
>
> Signed-off-by: Steffen Trumtrar
> ---
> I'm not sure what the current policy for such simple SPI bindings is.
> Are they necessary?
Like for i2c there is trivial-devices.txt? Although in this case it's
not just a compatible. Here you have a certain spi configuration that is
necessary for the rtc to work.
> .../devicetree/bindings/rtc/epson,rtc-rx6110.txt | 25
> ++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
>
> diff --git a/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> b/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> new file mode 100644
> index ..7ce7ae761657
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/epson,rtc-rx6110.txt
> @@ -0,0 +1,25 @@
> +Epson RX6110 Real Time Clock
> +
> +
> +The Epson RX6110 can be used with SPI or I2C busses. The kind of
> +bus depends on the SPISEL pin and can not be configured via software.
> +
> +SPI mode
> +
> +
> +Required properties:
> +- compatible: should be: "epson,rtc-rx6110"
Should this just be "epson,rx6110" ?
> +- reg: chip select number
> +- spi-cs-high: RX6110 needs chipselect high
> +- spi-cpha: RX6110 works with SPI shifted clock phase
> +- spi-cpol: RX6110 works with SPI inverse clock polarity
> +
> +Example:
> +
> + rtc: rtc@3 {
> + compatible = "epson,rtc-rx6110"
> + reg = <3>
> + spi-cs-high;
> + spi-cpba;
s/b/h/
> + spi-cpol;
> + };
regards
Philipp
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Re: [PATCH v6 00/12] MT8173 DRM support
Hi Daniel, Am Donnerstag, den 19.11.2015, 09:40 +0100 schrieb Daniel Vetter: > On Wed, Nov 18, 2015 at 06:34:08PM +0100, Philipp Zabel wrote: > > Hi, > > > > another update to the MT8173 DRM support patchset. Since the device tree > > bindings are now in order, I have dropped the RFC. > > The irq handler is still writing to hardware registers, as on MT8173 vblank > > synchronised register updates need help from a separate hardware command > > queue unit. A driver for that is currently being written, so this will be > > fixed later. > > Imo this is minor enough that it shouldn't block merging, and otherwise > the driver looks rather neat. Once you have acks for the arm/clk parts I > think you should just send a pull requests for this to Dave for 4.5. And > yes, that means Acked-by: Daniel Vetter (too lazy > to do a full review again) for the drm side. > > Cheers, Daniel Thank you. Given Tomasz' review and the fact that this driver needs the mtk-smi code, I think I'll still send at least one more version. Once ready, I'll do as you suggest. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 01/12] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
Hi Tomasz, Am Dienstag, den 24.11.2015, 14:32 +0900 schrieb Tomasz Figa: > Hi Philipp, CK, > > Please see my comments inline. > > On Thu, Nov 19, 2015 at 2:34 AM, Philipp Zabel wrote: [...] > > +Required properties (all function blocks): > > +- compatible: "mediatek,-disp-", one of > > + "mediatek,-disp-ovl" - overlay (4 layers, blending, csc) > > + "mediatek,-disp-rdma" - read DMA / line buffer > > + "mediatek,-disp-wdma" - write DMA > > + "mediatek,-disp-color" - color processor > > + "mediatek,-disp-aal" - adaptive ambient light controller > > + "mediatek,-disp-gamma" - gamma correction > > + "mediatek,-disp-ufoe" - data compression engine > > + "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt > > + "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt > > + "mediatek,-disp-mutex" - display mutex > > + "mediatek,-disp-od"- overdrive > > +- reg: Physical base address and length of the function block register > > space > > +- interrupts: The interrupt signal from the function block. > > Do all the blocks have only one interrupt signal? As far as I am aware, yes. They all have their own multiplexer, with single output to the GIC each. > > +- clocks: device clocks > > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for > > details. > > What about clock-names? Also all required clocks for particular > compatible strings should be listed in documentation, All the internal blocks just have a single clock gate. The exceptions are the DSI and DPI controllers, which are documented separately. I'll add a note. > > +- compatible: "mediatek,-ddp" > > Is this a rebase error? compatible property was already described few > lines above and also missing description. Yes, I'll drop this line. > > + > > +Required properties (DMA function blocks): > > +- compatible: Should be one of > > + "mediatek,-disp-ovl" > > + "mediatek,-disp-rdma" > > + "mediatek,-disp-wdma" > > Perhaps these 3 could also have some short description like the ones > listed above? These three are already included in the list above. Should I make this "Additional required properties (DMA function blocks):" to clarify? > > +- larb: Should contain a phandle pointing to the local arbiter device as > > defined > > + in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt > > +- iommus: required a iommu node > > Maybe rewrite to: "Should point to respective IOMMU block as defined > in "? I'll change this. thank you Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 02/12] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Tomasz,
Am Dienstag, den 24.11.2015, 17:27 +0900 schrieb Tomasz Figa:
> Hi Philipp, CK,
>
> Please see my comments inline.
Thank you for your comments.
> On Thu, Nov 19, 2015 at 2:34 AM, Philipp Zabel wrote:
> [snip]
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > new file mode 100644
> > index 000..508c8f3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -0,0 +1,596 @@
[...]
> > +struct mtk_crtc_ddp_context;
>
> Is this forward declaration really necessary?
Leftover, will remove.
> > +/*
> > + * MediaTek specific crtc structure.
> > + *
> > + * @base: crtc object.
> > + * @pipe: a crtc index created at load() with a new crtc object creation
> > + * and the crtc object would be set to private->crtc array
> > + * to get a crtc object corresponding to this pipe from private->crtc
> > + * array when irq interrupt occurred. the reason of using this pipe is
> > that
> > + * drm framework doesn't support multiple irq yet.
> > + * we can refer to the crtc to current hardware interrupt occurred
> > through
> > + * this pipe value.
>
> Only first two fields documented? Also this isn't proper kerneldoc
> syntax (see Documentation/kernel-doc-nano-HOWTO.txt).
I'll fix that.
> > + */
> > +struct mtk_drm_crtc {
> > + struct drm_crtc base;
> > + unsigned intpipe;
> > +
> > + booldo_flush;
> > +
> > + struct mtk_drm_planeplanes[OVL_LAYER_NR];
> > +
> > + void __iomem*config_regs;
> > + struct mtk_disp_mutex *mutex;
> > + u32 ddp_comp_nr;
>
> I assume this is size of ddp_comp array? Why not just unsigned int then?
And that.
> > + struct mtk_ddp_comp **ddp_comp;
> > +};
> [snip]
> > +static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
> > + const struct drm_display_mode *mode,
> > + struct drm_display_mode *adjusted_mode)
> > +{
> > + /* drm framework doesn't check NULL */
>
> Maybe rephrase the comment to "Nothing to do here, but the callback is
> mandatory."?
Ok.
> > + return true;
> > +}
> [snip]
> > +static void mtk_crtc_ddp_power_on(struct mtk_drm_crtc *mtk_crtc)
> > +{
> > + int ret;
> > + int i;
> > +
> > + DRM_INFO("mtk_crtc_ddp_power_on\n");
>
> DRM_DEBUG_DRIVER()
Yes, and the same for the following instances of this issue you point
out below.
> > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > + ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
> > + if (ret)
> > + DRM_ERROR("Failed to enable clock %d: %d\n", i,
> > ret);
>
> This is unsafe, because even if we fail here, mtk_crtc_ddp_power_off()
> will try to disable the clocks anyway, which will lead to negative
> enable counts (and a WARN() in best case). Can we add proper error
> handling to this function and other functions in the call stack?
Ultimately these are called by the enable/disable drm_crtc_helper_funcs,
which aren't allowed to fail. And clk_enable of core SoC clocks should
never fail either. If we hit this error, something else is very wrong
with the system already.
I'll have mtk_crtc_ddp_power_on propagate the error and
mtk_crtc_ddp_hw_init below bail out, and I'll also re-add the
mtk_crtc->enabled bool again to let crtc_disable warn and bail out in
case crtc_enable failed.
[...]
> > +static void mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> > +{
> > + struct drm_crtc *crtc = &mtk_crtc->base;
> > + unsigned int width, height, vrefresh;
> > + int ret;
> > + int i;
> > +
> > + if (crtc->state) {
> > + width = crtc->state->adjusted_mode.hdisplay;
> > + height = crtc->state->adjusted_mode.vdisplay;
> > + vrefresh = crtc->state->adjusted_mode.vrefresh;
> > + } else {
> > + WARN_ON(true);
> > + width = 1920;
> > + height = 1080;
> > + vrefresh = 60;
>
> When can crtc->state be NULL? Also shouldn't we just fail here instead
> of carrying on?
> > + }
>
> nit: The if above can be replaced with the following.
>
> if (WARN_
Re: [PATCH 1/3] dt-bindings: add multidomain support to i.MX GPC DT binding
Am Montag, den 23.11.2015, 16:07 +0100 schrieb Lucas Stach: > This adds a new binding for the Freescale i.MX GPC block, which allows > to describe multiple power domains in a more natural way. The driver > will continue to support the old binding for existing DTBs, but new > features like the additional domains present on i.MX6SX will only be > usable with the new binding. > > Signed-off-by: Lucas Stach > --- > .../devicetree/bindings/power/fsl,imx-gpc.txt | 81 > ++ > 1 file changed, 54 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > index 65cc0345747d..0b777b623812 100644 > --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt > @@ -1,22 +1,41 @@ > Freescale i.MX General Power Controller > === > > -The i.MX6Q General Power Control (GPC) block contains DVFS load tracking > -counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power > -domains. > +The i.MX6 General Power Control (GPC) block contains DVFS load tracking > +counters and Power Gating Control (PGC). > > Required properties: > - compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc" > - reg: should be register base and length as documented in the >datasheet > -- interrupts: Should contain GPC interrupt request 1 > -- pu-supply: Link to the LDO regulator powering the PU power domain > -- clocks: Clock phandles to devices in the PU power domain that need > - to be enabled during domain power-up for reset propagation. > -- #power-domain-cells: Should be 1, see below: > +- interrupts: Should contain GPC interrupts > +- clocks: Must contain an entry for each entry in clock-names. > + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for > details. > +- clock-names: Must include the following entries: > + - ipg As long as there is just a single clock input, shouldn't we just remove the clock-names property? Otherwise Acked-by: Philipp Zabel regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: imx6: rework GPC to support mutiple power domains
Am Montag, den 23.11.2015, 16:07 +0100 schrieb Lucas Stach:
> This largely reworks the GPC driver to better accomodate mutiple
accommodate multiple
> power domains. This allows to extend the driver to support more domains
> (like present on i.MX6SX) easily later on.
>
> Compatibility to the old DT bindings is provided to keep the currently
> supported i.MX6 devices working with the same feature level as before.
> New DTs and SoC support should only use the new binding from now on.
>
> Signed-off-by: Lucas Stach
> ---
> arch/arm/mach-imx/gpc.c | 435
>
> 1 file changed, 329 insertions(+), 106 deletions(-)
>
> diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
> index 8e7976a4c3e7..a3272b62d0b9 100644
> --- a/arch/arm/mach-imx/gpc.c
> +++ b/arch/arm/mach-imx/gpc.c
[...]
> static int imx_gpc_probe(struct platform_device *pdev)
> {
> - struct regulator *pu_reg;
> + const struct of_device_id *of_id =
> + of_match_device(imx_gpc_dt_ids, &pdev->dev);
> + const struct imx_gpc_dt_data *of_id_data = of_id->data;
> + struct device_node *pgc_node;
> + struct regmap *regmap;
> + struct resource *res;
> + void __iomem *base;
> int ret;
>
> + pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
> +
> /* bail out if DT too old and doesn't provide the necessary info */
> - if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
> + if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
> + !pgc_node)
> return 0;
>
> - pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
> - if (PTR_ERR(pu_reg) == -ENODEV)
> - pu_reg = NULL;
> - if (IS_ERR(pu_reg)) {
> - ret = PTR_ERR(pu_reg);
> - dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
> +&imx_gpc_regmap_config);
> + if (IS_ERR(regmap)) {
> + ret = PTR_ERR(regmap);
> + dev_err(&pdev->dev, "failed to init regmap: %d\n",
> + ret);
> return ret;
> }
>
> - return imx_gpc_genpd_init(&pdev->dev, pu_reg);
> -}
> + if (!pgc_node) {
> + /* old DT layout is only supported for mx6q aka 2 domains */
> + if (of_id_data->num_domains != 2) {
> + dev_err(&pdev->dev, "could not find pgc DT node\n");
> + return -ENODEV;
> + }
>
> -static const struct of_device_id imx_gpc_dt_ids[] = {
> - { .compatible = "fsl,imx6q-gpc" },
> - { .compatible = "fsl,imx6sl-gpc" },
> - { }
> -};
> + ret = imx_gpc_old_dt_init(&pdev->dev, regmap);
> + if (ret)
> + return ret;
> + } else {
> + struct imx_pm_domain *domain;
> + struct platform_device *pd_pdev;
> + struct device_node *np;
> + struct clk *ipg_clk;
> + unsigned int ipg_rate_mhz;
> + int domain_index;
> +
> + ipg_clk = devm_clk_get(&pdev->dev, "ipg");
This is just a single clock, why not just devm_clk_get(&pdev->dev,
NULL) ?
regards
Philipp
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Re: [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
Am Freitag, den 20.11.2015, 10:10 +0800 schrieb Chen Feng: > Add reset driver for hi6220-hikey board,this driver supply deassert > of IP on hi6220 SoC. > > Signed-off-by: Chen Feng Applied all three, thank you. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 09/12] arm64: dts: mt8173: Add HDMI related nodes
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index e185f88..13a11ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -199,6 +199,30 @@
,
;
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux =
;
+ input-enable;
+ bias-pull-down;
+ };
+
+ /*hdmi flt 5v pin*/
+ pins2 {
+ pinmux =
;
+ input-enable;
+ bias-pull-up;
+ };
+
+ /*hdmi 5v pin*/
+ pins3 {
+ pinmux =
;
+ output-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux =
,
@@ -277,6 +301,13 @@
clock-names = "spi", "wrap";
};
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
@@ -303,6 +334,16 @@
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+ };
+
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -823,6 +864,36 @@
clock-names = "apb", "smi";
};
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;
--
2.6.2
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[PATCH v6 10/12] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 227e356..b305fa2 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -558,7 +558,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090,
24, 4, 31),
/* CLK_CFG_6 */
- MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0,
3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16,
3, 23),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2,
31),
@@ -569,7 +569,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
/* CLK_CFG_12 */
MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents,
0x00c0, 0, 3, 7),
- MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
+ MUX_GATE_FLAGS(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8,
2, 15, 0),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0,
24, 3, 31),
/* CLK_CFG_13 */
MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
0x00d0, 0, 3, 7),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 32d2e45..b607996 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -83,7 +83,7 @@ struct mtk_composite {
signed char num_parents;
};
-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
_flags) {\
.id = _id, \
.name = _name, \
.mux_reg = _reg,\
@@ -94,9 +94,12 @@ struct mtk_composite {
.divider_shift = -1,\
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents),\
- .flags = CLK_SET_RATE_PARENT, \
+ .flags = _flags,\
}
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)\
+ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
CLK_SET_RATE_PARENT)
+
#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
--
2.6.2
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[PATCH v6 00/12] MT8173 DRM support
Hi,
another update to the MT8173 DRM support patchset. Since the device tree
bindings are now in order, I have dropped the RFC.
The irq handler is still writing to hardware registers, as on MT8173 vblank
synchronised register updates need help from a separate hardware command
queue unit. A driver for that is currently being written, so this will be
fixed later.
Changes since v5:
- Updated DISP_MUTEX description in binding documentation
- Register and unregister drivers in a loop
- Combined mtk_drm_crtc and mtk_crtc_ddp_context, added mtk_disp_ovl
structure to contain ovl ddp component
- Reworked component callbacks (removed comp_ prefix from
mtk_ddp_comp_funcs, move id into mtk_ddp_comp added inline
functions to wrap callbacks)
- Use non-sync pm_runtime_put variant
- Use RGB888 as fallback format
- Removed unused pipe parameter from mtk_ddp_add_comp_to_path
- Renamed mtk_drm_private->pipe to ->num_pipes
- Updated mtk specific crtc and plane atomic state handling
- Moved mtk_drm_crtc_plane_config to plane local mtk_plane_config
- Let layer_config take a struct mtk_plane_state
- Use writel_relaxed in mtk_ddp_add_comp_to_path
- Removed some unused parameters, functions, and local variables
- Removed custom crtc enable flag
- Removed unnecessary comp->funcs NULL checks
- Moved LARB handling out of drm driver code into crtc code,
request LARB during component initialization
- Updated display data path / mutex code
- Moved initialization of driverless ddp components into the drm driver
- Commented crtc_disable
- Removed support for multiplanar framebuffers
- Configure width/height of the color engine even if it is bypassed
- Added static keyword to unexported structures and functions
- Unlink display data path in hw_fini
- Added static keyword to unexported structures and functions
The following patches are still needed to apply this on top of v4.4-rc1:
https://patchwork.kernel.org/patch/6825601/ ("arm64: dts: mt8173: add MT8173
display PWM driver support node"),
https://patchwork.kernel.org/patch/7138531/ ("arm64: dts: mediatek: add xHCI &
usb phy for mt8173"),
https://patchwork.kernel.org/patch/6928651/ ("dts: mt8173: Add iommu/smi nodes
for mt8173"), and
And to build:
https://patchwork.kernel.org/patch/6928621/ ("memory: mediatek: Add SMI
driver"),
regards
Philipp
CK Hu (5):
dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
drm/mediatek: Add DSI sub driver
arm64: dts: mt8173: Add display subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (4):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
.../bindings/display/connector/hdmi-connector.txt | 1 +
.../bindings/display/mediatek/mediatek,disp.txt| 183 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35 +
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
.../bindings/display/mediatek/mediatek,hdmi.txt| 142
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 282
drivers/clk/mediatek/clk-mt8173.c | 9 +-
drivers/clk/mediatek/clk-mtk.h | 7 +-
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/mediatek/Kconfig | 22 +
drivers/gpu/drm/mediatek/Makefile | 21 +
drivers/gpu/drm/mediatek/mtk_cec.c | 245 +++
drivers/gpu/drm/mediatek/mtk_cec.h | 25 +
drivers/gpu/drm/mediatek/mtk_dpi.c | 683 ++
drivers/gpu/drm/mediatek/mtk_dpi.h | 80 +++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h| 228 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 596
drivers/gpu/drm/mediatek/mtk_drm_crtc.h| 41 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 362 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 431 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 152
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 561 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 58 ++
drivers/gpu/drm/mediatek/mtk_drm_fb.c | 139
drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29 +
drivers/gpu/drm/mediatek/mtk_drm_gem.c | 187 +
drivers/gpu/drm/mediatek/mtk_drm_gem.h | 54 ++
drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c| 633 +
dri
[PATCH v6 01/12] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v5:
- Updated DISP_MUTEX description
- Fixed DSI and DPI documentation path
---
.../bindings/display/mediatek/mediatek,disp.txt| 183 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
3 files changed, 271 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000..a311019
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,183 @@
+Mediatek display subsystem
+==
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+of frame signal are distributed to the other function blocks by a DISP_MUTEX
+function block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,-disp-", one of
+ "mediatek,-disp-ovl" - overlay (4 layers, blending, csc)
+ "mediatek,-disp-rdma" - read DMA / line buffer
+ "mediatek,-disp-wdma" - write DMA
+ "mediatek,-disp-color" - color processor
+ "mediatek,-disp-aal" - adaptive ambient light controller
+ "mediatek,-disp-gamma" - gamma correction
+ "mediatek,-disp-ufoe" - data compression engine
+ "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt
+ "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
+ "mediatek,-disp-mutex" - display mutex
+ "mediatek,-disp-od"- overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- compatible: "mediatek,-ddp"
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+ "mediatek,-disp-ovl"
+ "mediatek,-disp-rdma"
+ "mediatek,-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as
defined
+ in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: required a iommu node
+
+Examples:
+
+mmsys: clock-controller@1400 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+};
+
+ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+};
+
+ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+};
+
+rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = &
[PATCH v6 06/12] drm/mediatek: Add HDMI support
From: Jie Qiu This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- Changes since v5: - Register and unregister hdmi drivers in a loop - Add static keyword to unexported structures and functions - Remove unused functions --- drivers/gpu/drm/mediatek/Kconfig | 6 + drivers/gpu/drm/mediatek/Makefile| 8 + drivers/gpu/drm/mediatek/mtk_cec.c | 245 + drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c | 633 ++ drivers/gpu/drm/mediatek/mtk_hdmi.c | 515 ++ drivers/gpu/drm/mediatek/mtk_hdmi.h | 118 + drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c | 362 + drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 757 +++ drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 +++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 340 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 20 + drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h | 118 + drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 221 include/drm/mediatek/mtk_hdmi_audio.h| 150 ++ 16 files changed, 3595 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 include/drm/mediatek/mtk_hdmi_audio.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index 5343cf1..85af51c 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -14,3 +14,9 @@ config DRM_MEDIATEK This driver provides kernel mode setting and buffer management to userspace. +config DRM_MEDIATEK_HDMI + tristate "DRM HDMI Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select GENERIC_PHY + help + DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 93380fe..e2a5c5c 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -11,3 +11,11 @@ mediatek-drm-y := mtk_drm_drv.o \ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o +mediatek-drm-hdmi-objs := mtk_drm_hdmi_drv.o \ + mtk_cec.o \ + mtk_hdmi_ddc_drv.o \ + mtk_hdmi.o \ + mtk_hdmi_hw.o \ + mtk_hdmi_phy.o + +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c new file mode 100644 index 000..c339d2f --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#include "mtk_cec.h" + +#define TR_CONFIG 0x00 +#define CLEAR_CEC_IRQ BIT(15) + +#define CEC_CKGEN 0x04 +#define CEC_32K_PDNBIT(19) +#define PDNBIT(16) + +#define RX_EVENT 0x54 +#define HDMI_PORD BIT(25) +#define HDMI_HTPLG BIT(24) +#define HDMI_PORD_INT_EN BIT(9) +#define HDMI_HTPLG_INT_EN BIT(8) + +#define RX_GEN_WD 0x58 +#define HDMI_PORD_INT_32K_STATUS BIT(26) +#define RX_RISC_INT_32K_STATUS BIT(25) +#define HDMI_HTPLG_INT_32K_STATUS BIT(24) +#define HDMI_PORD_INT_32K_CLR BIT(18) +#define RX_INT_32K_CLR BIT(17) +#define HDMI_HTPLG_INT_32K_CLR BIT(16) +#define HDMI_PORD_INT_32K_STA_MASK BIT(10) +#define RX_RISC_INT_32K_
[PATCH v6 07/12] drm/mediatek: enable hdmi output control bit
From: Jie Qiu
MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 7652266..8bee167 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -19,8 +19,15 @@
#include
#include
#include
+#include
#include
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
{
return readl(hdmi->regs + offset);
@@ -170,6 +177,10 @@ void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
{
+ invoke_psci_fn = __invoke_psci_fn_smc;
+ invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+ 0x14000904, 0x8000, 0);
+
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index de7ee22..8d7d60a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -218,4 +218,5 @@
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x8201
#endif
--
2.6.2
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[PATCH v6 08/12] arm64: dts: mt8173: Add display subsystem related nodes
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
TODO:
- The power-domain property should be added to all blocks
that are in the MM power domain.
- The iommus property should be removed from the mmsys node.
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 211 +++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 68010d9..e185f88 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -286,6 +303,18 @@
#clock-cells = <1>;
};
+ mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
+ mipi_tx1: mipi-dphy@10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
gic: interrupt-controller@1022 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -432,6 +461,14 @@
status = "disabled";
};
+ hdmiddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = ;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
i2c6: i2c@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@@ -568,7 +605,167 @@
mmsys: clock-controller@1400 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
+
+ /* FIXME - remove iommus here */
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>,
+<&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ };
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x140
[PATCH v6 03/12] drm/mediatek: Add DSI sub driver
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v5:
- Register and unregister drivers in a loop
- Added static keyword to unexported structures and functions
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 787 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 54 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 377
drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 21 +
7 files changed, 1246 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index ba6d3fc..0d4aeeb 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,7 +4,9 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_ddp_comp.o \
mtk_drm_fb.o \
mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index acc0cfc..55f599c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -516,6 +516,8 @@ static struct platform_driver mtk_drm_platform_driver = {
static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_drm_platform_driver,
&mtk_disp_ovl_driver,
+ &mtk_dsi_driver,
+ &mtk_mipi_tx_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 4740f84..02cc330 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,5 +51,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..fdcfd4c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dsi.h"
+#include "mtk_mipi_tx.h"
+
+#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START 0x00
+
+#define DSI_CON_CTRL 0x10
+#define DSI_RESET BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL 0x14
+#define MODE (3)
+#define CMD_MODE 0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE BIT(16)
+#define MIX_MODE BIT(17)
+
+#define DSI_TXRX_CTRL 0x18
+#define VC_NUM (2 << 0)
+#define LANE_NUM (0xf << 2)
+#define DIS_EOTBIT(6)
+#define NULL_ENBIT(7)
+#define TE_FREERUN BIT(8)
+#define EXT_TE_EN BIT(9)
+#define EXT_TE_EDGEBIT(10)
+#define MAX_RTN_SIZE (0xf << 12)
+#define HSTX_CKLP_EN BIT(16)
+
+#define DSI_PSCTRL 0x1c
+#define DSI_PS_WC 0x3fff
+#define DSI_PS_SEL (3 << 16)
+#define PACKED_PS_16BIT_RGB565 (0 << 16)
+#define LOOSELY_PS_18BIT_RGB666(1 << 16)
+#define PACKED_PS_18BIT_RGB666 (2 << 16)
+#define PACKED_PS_24BIT_RGB888 (3 << 16)
+
+#define DSI_VSA_NL 0x2
[PATCH v6 12/12] dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
Add an optional ddc-i2c-bus phandle property that points to an I2C master controller that handles the connector DDC pins. Signed-off-by: Philipp Zabel Acked-by: Rob Herring --- Changes since v5: - Rebased onto v4.4-rc1 --- Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt index acd5668..508aee4 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing Required nodes: - Video port for HDMI input -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 11/12] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index b305fa2..d7eadda 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -1091,6 +1091,11 @@ static void __init mtk_apmixedsys_init(struct
device_node *node)
clk_data->clks[cku->id] = clk;
}
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+ base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h
b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1..6094bf7 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
#define CLK_APMIXED_LVDSPLL13
#define CLK_APMIXED_MSDCPLL2 14
#define CLK_APMIXED_REF2USB_TX 15
-#define CLK_APMIXED_NR_CLK 16
+#define CLK_APMIXED_HDMI_REF 16
+#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */
--
2.6.2
--
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[PATCH v6 05/12] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 142 +
1 file changed, 142 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 000..e3dde29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,142 @@
+Mediatek HDMI Encoder
+=
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+ configuration registers. For mt8173 this must be offset 0x900 into the
+ MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+- port@1: The output port in the ports node should be connected to the input
+ port of a connector node that contains a ddc-i2c-bus property, or to the
+ input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- #phy-cells: must be <0>.
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = ;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+
[PATCH v6 04/12] drm/mediatek: Add DPI sub driver
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v5:
- Register and unregister drivers in a loop
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 683
drivers/gpu/drm/mediatek/mtk_dpi.h | 80
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 0d4aeeb..93380fe 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,7 +6,8 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..43eaf33
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dpi.h"
+#include "mtk_dpi_regs.h"
+
+enum mtk_dpi_polarity {
+ MTK_DPI_POLARITY_RISING,
+ MTK_DPI_POLARITY_FALLING,
+};
+
+struct mtk_dpi_polarities {
+ enum mtk_dpi_polarity de_pol;
+ enum mtk_dpi_polarity ck_pol;
+ enum mtk_dpi_polarity hsync_pol;
+ enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+ u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+ tmp |= (val & mask);
+ writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+ mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+}
+
+static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync,
+u32 width_addr, u32 porch_addr)
+{
+ mtk_dpi_mask(dpi, width_addr,
+sync->sync_width << VSYNC_WIDTH_SHIFT,
+VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, width_addr,
+sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+VSYNC_HALF_LINE_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+VSYNC_FRONT_PORCH_MASK);
+}
+
+static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
+}
+
+static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
+
[PATCH v6 02/12] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
From: CK Hu This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu Signed-off-by: YT Shen Signed-off-by: Philipp Zabel --- Changes since v5: - Combined mtk_drm_crtc and mtk_crtc_ddp_context, added mtk_disp_ovl structure to contain ovl ddp component - Reworke component callbacks (removed comp_ prefix from mtk_ddp_comp_funcs, move id into mtk_ddp_comp added inline functions to wrap callbacks) - Use non-sync pm_runtime_put variant - Warn and use RGB888 as fallback format in case of driver bug - Removed unused pipe parameter from mtk_ddp_add_comp_to_path - Renamed mtk_drm_private->pipe ->num_pipes - Updated mtk specific crtc and plane atomic state handling - Moved mtk_drm_crtc_plane_config to plane local mtk_plane_config - Let layer_config take a struct mtk_plane_state - Use writel_relaxed in mtk_ddp_add_comp_to_path - Removed some unused parameters, functions, and local variables - Removed custom crtc enable flag - Removed unnecessary comp->funcs NULL checks - Register and unregister subdrivers in a loop - Moved LARB handling out of drm driver code into crtc code, request LARB during component initialization - Updated display data path / mutex code - Moved initialization of driverless ddp components into the drm driver - Commented crtc_disable - Removed support for multiplanar framebuffers - Configure width/height of the color engine even if it is bypassed - Added static keyword to unexported structures and functions - Unlink display data path in hw_fini --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile| 1 + drivers/gpu/drm/mediatek/Kconfig| 16 + drivers/gpu/drm/mediatek/Makefile | 10 + drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 596 drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 41 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 362 + drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 431 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 152 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 557 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 55 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.c | 139 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29 ++ drivers/gpu/drm/mediatek/mtk_drm_gem.c | 187 + drivers/gpu/drm/mediatek/mtk_drm_gem.h | 54 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.c| 235 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.h| 61 +++ 18 files changed, 2969 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/Kconfig create mode 100644 drivers/gpu/drm/mediatek/Makefile create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4bf9a1..8fdb0c2 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -266,3 +266,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" + +source "drivers/gpu/drm/mediatek/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 1e9ff4c..607a49f 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ +obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig new file mode 100644 index 000..5343cf1 --- /dev/null +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -0,0 +1,16 @@ +config DRM_MEDIATEK + tristate "DRM Support for Mediatek SoCs" + depends on DRM + depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST) + select MTK_SMI + select DRM_PANEL + select DRM_MIPI_DSI + s
Re: [PATCH] MAINTAINERS: update DT binding doc locations
Am Donnerstag, den 05.11.2015, 13:41 -0600 schrieb Rob Herring: > After the recent moving of DT binding documents, some maintainers entries > are stale. Update them to the new locations. > > In bindings/fb/, there were only 2 files and I'm assuming the FB > maintainers don't want to be copied on all of bindings/display/. So I've > dropped them. > > Reported-by: Thierry Reding > Cc: Thierry Reding > Cc: Jianwei Wang > Cc: Alison Wang > Cc: Philipp Zabel Acked-by: Philipp Zabel regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC v3 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Am Mittwoch, den 11.11.2015, 20:53 +0800 schrieb Jitao Shi: > Add documentation for DT properties supported by > ps8640 DSI-eDP converter. > > Signed-off-by: Jitao Shi > Acked-by: Rob Herring Reviewed-by: Philipp Zabel best regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC v5 01/12] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
Am Mittwoch, den 04.11.2015, 21:28 -0600 schrieb Rob Herring: > On Wed, Nov 04, 2015 at 12:44:58PM +0100, Philipp Zabel wrote: > > From: CK Hu > > > > Add device tree binding documentation for the display subsystem in > > Mediatek MT8173 SoCs. > > > > Signed-off-by: CK Hu > > Signed-off-by: Philipp Zabel > > If this wasn't an RFC, I'd ack it. :) One thing you missed below though. Alright, thanks for your help in sorting these bindings out. [...] > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > new file mode 100644 > > index 000..cc3d884 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt [...] > > +DISP function blocks > > + > > + > > +A display stream starts at a source function block that reads pixel data > > from > > +memory and ends with a sink function block that drives pixels on a display > > +interface, or writes pixels back to memory. All DISP function blocks have > > +their own register space, interrupt, and clock gate. The blocks that can > > +access memory additionally have to list the IOMMU and local arbiter they > > are > > +connected to. > > + > > +For a description of the display interface sink function blocks, see > > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt and > > +Documentation/devicetree/bindings/drm/mediatek/mediatek,dpi.txt. > > Need to update these paths. Will do. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC v5 02/12] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Daniel,
Am Donnerstag, den 05.11.2015, 02:49 +0800 schrieb Daniel Kurtz:
> Hi Philipp,
>
> A bunch of review comments inline.
A bunch indeed. Thank you for the feedback.
> On Wed, Nov 4, 2015 at 7:44 PM, Philipp Zabel wrote:
[...]
> > +struct mtk_drm_crtc {
> > + struct drm_crtc base;
> > + unsigned intpipe;
>
> There is one pipe too many :-)
> I think this one is not used."
>
> > + boolenabled;
> > + struct mtk_crtc_ddp_context *ctx;
>
> I think you should be able to just embed the "mtk_crtc_ddp_context"
> right into mtk_drm_crtc.
> Or maybe just get rid of mtk_crtc_ddp_context completely and just use
> mtk_drm_crtc eveywhere.
I'll combine them and get rid of the superfluous pipe.
[...]
> > +static void mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *crtc)
> > +{
[...]
> > + /* disp_mtcmos */
> > + ret = pm_runtime_get_sync(drm->dev);
> > + if (ret < 0)
> > + DRM_ERROR("Failed to enable power domain: %d\n", ret);
> > +
> > + mtk_ddp_clock_on(ctx->mutex_dev);
> > + mtk_crtc_ddp_power_on(ctx);
>
> get_sync(), clock_on() and ddp_power_on() really can fail; we are just
> ignoring errors here.
> Since they can fail, shouldn't they be moved out of the atomic
> "->enable()" path into the ->check() path that is allowed to fail?
You suggest I move them into atomic_check?
To me it sounds like this should not be called from check, but from the
drm_mode_config_funcs atomic_commit callback, right after calling
drm_atomic_helper_prepare_planes. But there is no prepare equivalent to
drm_atomic_helper_commit_modeset_enables.
> > +
> > + DRM_INFO("mediatek_ddp_ddp_path_setup\n");
> > + for (i = 0; i < (ctx->ddp_comp_nr - 1); i++) {
>
> nit: the inner () are not necessary.
Will remove those.
> > + mtk_ddp_add_comp_to_path(ctx->config_regs, ctx->pipe,
> > +ctx->ddp_comp[i].funcs->comp_id,
> > +ctx->ddp_comp[i+1].funcs->comp_id);
> > + mtk_ddp_add_comp_to_mutex(ctx->mutex_dev, ctx->pipe,
> > + ctx->ddp_comp[i].funcs->comp_id,
> > +
> > ctx->ddp_comp[i+1].funcs->comp_id);
> > + }
>
> Do you really have to do this here in the enable path? This looks
> like something that should be done in bind()?
>
> Perhaps all we really need here is to walk the path and write to
> DISP_REG_MUTEX_EN at the end of mtk_ddp_add_comp_to_mutex().
> By the way, where are those bits cleared in the disable path?
Disabling or changing the path is not implemented, the currently static
setup could well be moved into bind().
[...]
> > +static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *crtc)
> > +{
[...]
> > + pm_runtime_put_sync(drm->dev);
>
> Why sync?
I can think of no reason, will use the async version here.
[...]
> > +static void mtk_drm_crtc_disable(struct drm_crtc *crtc)
> > +{
> > + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> > + struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
> > +
> > + DRM_INFO("mtk_drm_crtc_disable %d\n", crtc->base.id);
> > + if (WARN_ON(!mtk_crtc->enabled))
> > + return;
> > +
> > + mtk_crtc_ddp_hw_fini(mtk_crtc);
> > + mtk_crtc->do_flush = false;
> > + if (state->event)
> > + mtk_drm_crtc_finish_page_flip(mtk_crtc);
>
> It is a bit awkward to send the page flip event before the actual page
> flip has completed (in this case, for a page flip that you are
> canceling by disabling the crtc).
> Would it be better to wait for vblank here in crtc_disable instead?
Yes, I will wait for vblank here instead.
[...]
> > +static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
> > + struct drm_crtc_state *old_crtc_state)
> > +{
> > + struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
> > +
> > + if (state->base.event) {
> > + state->base.event->pipe = drm_crtc_index(crtc);
> > + WARN_ON(drm_crtc_vblank_get(crtc) != 0);
> > + state->event = state->base.event;
> > + state->base.event = NULL;
>
> Hmm. Why are we "stealing" event from drm_crtc_stat
Re: [RFC v2 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
Hi Jitao,
some things I missed before.
Am Montag, den 02.11.2015, 10:09 +0800 schrieb Jitao Shi:
[...]
> +static int ps8640_regr(struct i2c_client *client, u16 i2c_addr,
> +u8 reg, u8 *value)
> +{
> + int ret;
> +
> + client->addr = i2c_addr;
I think i2c_new_dummy should be used to create additional clients for
the secondary addresses, instead of changing the address of the client
with every transfer.
> + ret = i2c_master_send(client, ®, 1);
> + if (ret <= 0) {
> + DRM_ERROR("Failed to send i2c command, ret=%d\n", ret);
> + return ret;
> + }
> +
> + ret = i2c_master_recv(client, value, 1);
> + if (ret <= 0) {
> + DRM_ERROR("Failed to recv i2c data, ret=%d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
[...]
> +static int ps8640_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct device *dev = &client->dev;
> + struct ps8640 *ps_bridge;
> + struct device_node *np = dev->of_node;
> + struct device_node *in_ep, *out_ep;
> + struct device_node *panel_node = NULL;
> + int ret;
> + u32 temp_reg;
> +
> + ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
> + if (!ps_bridge)
> + return -ENOMEM;
> +
> + in_ep = of_graph_get_next_endpoint(np, NULL);
> + if (in_ep) {
> + out_ep = of_graph_get_next_endpoint(np, in_ep);
> + of_node_put(in_ep);
> + if (out_ep) {
> + panel_node = of_graph_get_remote_port_parent(out_ep);
> + of_node_put(out_ep);
> + }
> + }
> + if (panel_node) {
> + ps_bridge->panel = of_drm_find_panel(panel_node);
> + of_node_put(panel_node);
> + if (!ps_bridge->panel)
> + return -EPROBE_DEFER;
> + }
> +
> + ps_bridge->client = client;
> +
> + ps_bridge->pwr_3v3_supply = devm_regulator_get(dev, "vdd33-supply");
Should be "vdd3", regulator_get will add the "-supply" suffix.
> + if (IS_ERR(ps_bridge->pwr_3v3_supply)) {
> + dev_err(dev, "cannot get ps_bridge->pwr_3v3_supply\n");
> + return PTR_ERR(ps_bridge->pwr_3v3_supply);
> + }
> +
> + ps_bridge->pwr_1v2_supply = devm_regulator_get(dev, "vdd12-supply");
Same here, "vdd12".
> + if (IS_ERR(ps_bridge->pwr_1v2_supply)) {
> + dev_err(dev, "cannot get ps_bridge->pwr_1v2_supply\n");
> + return PTR_ERR(ps_bridge->pwr_1v2_supply);
> + }
> +
> + ps_bridge->gpio_mode_sel_n = devm_gpiod_get(&client->dev, "mode-sel",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(ps_bridge->gpio_mode_sel_n)) {
> + ret = PTR_ERR(ps_bridge->gpio_mode_sel_n);
> + DRM_ERROR("cannot get gpio_mode_sel_n %d\n", ret);
> + return ret;
> + }
> +
> + ret = gpiod_direction_output(ps_bridge->gpio_mode_sel_n, 1);
> + if (ret) {
> + DRM_ERROR("cannot configure gpio_mode_sel_n\n");
> + return ret;
> + }
> +
> + ps_bridge->gpio_slp_n = devm_gpiod_get(&client->dev, "sleep-gpios",
> +GPIOD_OUT_HIGH);
Should be "sleep", gpiod_get will add the "-gpios" suffix.
> + if (IS_ERR(ps_bridge->gpio_slp_n)) {
> + ret = PTR_ERR(ps_bridge->gpio_slp_n);
> + DRM_ERROR("cannot get gpio_slp_n %d\n", ret);
> + return ret;
> + }
> +
> + ret = gpiod_direction_output(ps_bridge->gpio_slp_n, 1);
> + if (ret) {
> + DRM_ERROR("cannot configure gpio_slp_n\n");
> + return ret;
> + }
This can be removed, the "devm_gpiod_get(..., GPIOD_OUT_HIGH);" already
does the same.
> +
> + ps_bridge->gpio_rst_n = devm_gpiod_get(&client->dev, "reset",
> +GPIOD_OUT_HIGH);
> + if (IS_ERR(ps_bridge->gpio_rst_n)) {
> + ret = PTR_ERR(ps_bridge->gpio_rst_n);
> + DRM_ERROR("cannot get gpio_rst_n %d\n", ret);
> + return ret;
> + }
> +
> + ret = gpiod_direction_output(ps_bridge->gpio_rst_n, 1);
> + if (ret) {
> + DRM_ERROR("cannot configure gpio_rst_n\n");
> + return ret;
> + }
Same here, the gpiod_direction_output can be removed.
best regards
Philipp
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[RFC v5 02/12] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
From: CK Hu This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu Signed-off-by: YT Shen Signed-off-by: Philipp Zabel --- Changes since v4: - Add mtk_crtc_state to keep pending state - Move drm pending vblank event into mtk_crtc_state - Make mtk_drm_crtc private - Use drm_dev_alloc and drm_dev_register directly instead of drm_platform_init - Drop unnecessary locking in mtk_drm_gem_dump_map_offset - Remove currently unused mtk_drm_gem_mmap_buf - Stop referencing plane framebuffers manually - Set RDMA FIFO output threshold depending on frame width/height/rate --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile| 1 + drivers/gpu/drm/mediatek/Kconfig| 16 + drivers/gpu/drm/mediatek/Makefile | 10 + drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 590 drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 56 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 218 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 39 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 424 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 86 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 572 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 61 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.c | 151 +++ drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29 ++ drivers/gpu/drm/mediatek/mtk_drm_gem.c | 189 + drivers/gpu/drm/mediatek/mtk_drm_gem.h | 56 +++ drivers/gpu/drm/mediatek/mtk_drm_plane.c| 167 drivers/gpu/drm/mediatek/mtk_drm_plane.h| 41 ++ 18 files changed, 2708 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/Kconfig create mode 100644 drivers/gpu/drm/mediatek/Makefile create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 1a0a8df..9e9987b 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -264,3 +264,5 @@ source "drivers/gpu/drm/sti/Kconfig" source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" + +source "drivers/gpu/drm/mediatek/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 45e7719..af6b592 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ +obj-$(CONFIG_DRM_MEDIATEK) += mediatek/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig new file mode 100644 index 000..5343cf1 --- /dev/null +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -0,0 +1,16 @@ +config DRM_MEDIATEK + tristate "DRM Support for Mediatek SoCs" + depends on DRM + depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST) + select MTK_SMI + select DRM_PANEL + select DRM_MIPI_DSI + select DRM_PANEL_SIMPLE + select DRM_KMS_HELPER + select IOMMU_DMA + help + Choose this option if you have a Mediatek SoCs. + The module will be called mediatek-drm + This driver provides kernel mode setting and + buffer management to userspace. + diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile new file mode 100644 index 000..ba6d3fc --- /dev/null +++ b/drivers/gpu/drm/mediatek/Makefile @@ -0,0 +1,10 @@ +mediatek-drm-y := mtk_drm_drv.o \ + mtk_drm_crtc.o \ + mtk_drm_ddp.o \ + mtk_drm_ddp_comp.o \ + mtk_drm_fb.o \ + mtk_drm_gem.o \ + mtk_drm_plane.o + +obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o + diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c new file mode 100644 index 000
[RFC v5 06/12] drm/mediatek: Add HDMI support
From: Jie Qiu This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- Changes since v4: - Always set mode during bridge enable - Move HDMI PHY registers into a separate file - Make port@1 required, use of_graph_get_port_by_id - Move ddc-i2c-bus property into the output connector node - Enable the clock later in CEC probe --- drivers/gpu/drm/mediatek/Kconfig | 6 + drivers/gpu/drm/mediatek/Makefile| 8 + drivers/gpu/drm/mediatek/mtk_cec.c | 251 + drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c | 642 ++ drivers/gpu/drm/mediatek/mtk_hdmi.c | 515 ++ drivers/gpu/drm/mediatek/mtk_hdmi.h | 118 + drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c | 362 + drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 762 +++ drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 +++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 340 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 20 + drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h | 118 + drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 221 include/drm/mediatek/mtk_hdmi_audio.h| 150 ++ 16 files changed, 3615 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 include/drm/mediatek/mtk_hdmi_audio.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index 5343cf1..85af51c 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -14,3 +14,9 @@ config DRM_MEDIATEK This driver provides kernel mode setting and buffer management to userspace. +config DRM_MEDIATEK_HDMI + tristate "DRM HDMI Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select GENERIC_PHY + help + DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 93380fe..e2a5c5c 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -11,3 +11,11 @@ mediatek-drm-y := mtk_drm_drv.o \ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o +mediatek-drm-hdmi-objs := mtk_drm_hdmi_drv.o \ + mtk_cec.o \ + mtk_hdmi_ddc_drv.o \ + mtk_hdmi.o \ + mtk_hdmi_hw.o \ + mtk_hdmi_phy.o + +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c new file mode 100644 index 000..65f4d60 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#define TR_CONFIG 0x00 +#define CLEAR_CEC_IRQ BIT(15) + +#define CEC_CKGEN 0x04 +#define CEC_32K_PDNBIT(19) +#define PDNBIT(16) + +#define RX_EVENT 0x54 +#define HDMI_PORD BIT(25) +#define HDMI_HTPLG BIT(24) +#define HDMI_PORD_INT_EN BIT(9) +#define HDMI_HTPLG_INT_EN BIT(8) + +#define RX_GEN_WD 0x58 +#define HDMI_PORD_INT_32K_STATUS BIT(26) +#define RX_RISC_INT_32K_STATUS BIT(25) +#define HDMI_HTPLG_INT_32K_STATUS BIT(24) +#define HDMI_PORD_INT_32K_CLR BIT(18) +#define RX_INT_32K_CLR BIT(17) +#define HDMI_HTPLG_INT_32K_CLR BIT(16
[RFC v5 09/12] arm64: dts: mt8173: Add HDMI related nodes
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Drop mediatek,cec DT property
- Add mediatek, prefix to ibias DT properties
- Remove ddc-i2c-bus property, that goes into the
board specific connector node
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 9874ab1..2eb5ca1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -199,6 +199,30 @@
,
;
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux =
;
+ input-enable;
+ bias-pull-down;
+ };
+
+ /*hdmi flt 5v pin*/
+ pins2 {
+ pinmux =
;
+ input-enable;
+ bias-pull-up;
+ };
+
+ /*hdmi 5v pin*/
+ pins3 {
+ pinmux =
;
+ output-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux =
,
@@ -275,6 +299,13 @@
clock-names = "spi", "wrap";
};
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
@@ -301,6 +332,16 @@
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+ };
+
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -808,6 +849,36 @@
clock-names = "apb", "smi";
};
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;
--
2.6.1
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[RFC v5 03/12] drm/mediatek: Add DSI sub driver
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 19 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 787 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 54 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 375
drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 21 +
7 files changed, 1261 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index ba6d3fc..0d4aeeb 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,7 +4,9 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_ddp_comp.o \
mtk_drm_fb.o \
mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index fbca99f..cbaf208 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -550,8 +550,25 @@ static int __init mtk_drm_init(void)
goto drm_err;
}
+ ret = platform_driver_register(&mtk_dsi_driver);
+ if (ret < 0) {
+ pr_err("Failed to register DSI platform driver: %d\n!", ret);
+ goto disp_ovl_err;
+ }
+
+ ret = platform_driver_register(&mtk_mipi_tx_driver);
+ if (ret < 0) {
+ pr_err("Failed to register MIPI TX platform driver: %d\n!",
+ ret);
+ goto dsi_err;
+ }
+
return 0;
+dsi_err:
+ platform_driver_unregister(&mtk_dsi_driver);
+disp_ovl_err:
+ platform_driver_unregister(&mtk_disp_ovl_driver);
drm_err:
platform_driver_unregister(&mtk_drm_platform_driver);
err:
@@ -560,6 +577,8 @@ err:
static void __exit mtk_drm_exit(void)
{
+ platform_driver_unregister(&mtk_mipi_tx_driver);
+ platform_driver_unregister(&mtk_dsi_driver);
platform_driver_unregister(&mtk_disp_ovl_driver);
platform_driver_unregister(&mtk_drm_platform_driver);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 5e5128e..9c81abe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -57,5 +57,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..fe3c450
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dsi.h"
+#include "mtk_mipi_tx.h"
+
+#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START 0x00
+
+#define DSI_CON_CTRL 0x10
+#define DSI_RESET BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL 0x14
+#define MODE (3)
+#define CMD_MODE 0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE BIT(16)
+#define MIX_MODE BIT(17)
+
+#define DSI_TXRX_CTRL 0x18
+#define VC_NUM (2 << 0)
+#define LANE_NUM (0xf << 2)
+#define DIS_EOTBIT(6)
+#define NULL_EN
[RFC v5 00/12] MT8173 DRM support
Hi,
another update to the MT8173 DRM support RFC.
Changes since v4:
- Fixed author for the HDMI driver patch
- Moved device tree binding documentation to
Documentation/devicetree/bindings/display/mediatek
- Added mtk_crtc_state to keep pending state, made mtk_drm_crtc private
- Now using drm_dev_alloc and drm_dev_register directly instead of
drm_platform_init, drop drm_driver->load callback
- Dropped unnecessary locking in mtk_drm_gem_dump_map_offset
- Removed currently unused mtk_drm_gem_mmap_buf
- Stopped referencing plane framebuffers manually
- Set RDMA FIFO output threshold depending on frame width/height/rate
- Removed mediatek,cec and ddc-i2c-bus properties from hdmi node
- Added ddc-i2c-bus property to the output connector node
- Made output port@1 required in hdmi node, using of_graph_get_port_by_id
- Add mediatek, prefix to ibias properties in the hdmi-phy node
- Always set HDMI mode during bridge enable
- Move HDMI PHY registers into a separate file
- Enable the CEC clock later in the probe function
Due to the locking changes this now depends on drm-next to function,
but otherwise the patch dependencies are still the same. To apply:
https://patchwork.kernel.org/patch/6980951/ ("arm64: dts: mt8173: Add subsystem
clock controller device nodes"),
https://patchwork.kernel.org/patch/6825601/ ("arm64: dts: mt8173: add MT8173
display PWM driver support node"),
https://patchwork.kernel.org/patch/7138531/ ("arm64: dts: mediatek: add xHCI &
usb phy for mt8173"),
https://patchwork.kernel.org/patch/6928651/ ("dts: mt8173: Add iommu/smi nodes
for mt8173"), and
https://patchwork.kernel.org/patch/6983351/ ("clk: mediatek: Add USB clock
support in MT8173 APMIXEDSYS").
And to build,
https://patchwork.kernel.org/patch/6914941/ ("iommu: Implement common IOMMU ops
for DMA mapping"),
https://patchwork.kernel.org/patch/6928621/ ("memory: mediatek: Add SMI
driver"),
https://patchwork.kernel.org/patch/6928561/ ("dt-bindings: iommu: Add binding
for mediatek IOMMU"),
https://patchwork.kernel.org/patch/6980911/ ("clk: mediatek: Removed unused
dpi_ck clock from MT8173"),
https://patchwork.kernel.org/patch/6980981/ ("clk: mediatek: Add __initdata and
__init for data and functions"),
https://patchwork.kernel.org/patch/6981021/ ("clk: mediatek: Add fixed clocks
support for Mediatek SoC."),
https://patchwork.kernel.org/patch/6980961/ ("clk: mediatek: Fix rate and
dependency of MT8173 clocks"),
https://patchwork.kernel.org/patch/6981031/ ("dt-bindings: ARM: Mediatek:
Document devicetree bindings for clock controllers"), and
https://patchwork.kernel.org/patch/6981041/ ("clk: mediatek: Add subsystem
clocks of MT8173").
regards
Philipp
CK Hu (5):
dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
drm/mediatek: Add DSI sub driver
arm64: dts: mt8173: Add display subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (4):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
.../bindings/display/mediatek/mediatek,disp.txt| 183 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35 +
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
.../bindings/display/mediatek/mediatek,hdmi.txt| 142
.../devicetree/bindings/video/hdmi-connector.txt | 1 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 282
drivers/clk/mediatek/clk-mt8173.c | 9 +-
drivers/clk/mediatek/clk-mtk.h | 7 +-
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/mediatek/Kconfig | 22 +
drivers/gpu/drm/mediatek/Makefile | 21 +
drivers/gpu/drm/mediatek/mtk_cec.c | 251 +++
drivers/gpu/drm/mediatek/mtk_cec.h | 25 +
drivers/gpu/drm/mediatek/mtk_dpi.c | 683 ++
drivers/gpu/drm/mediatek/mtk_dpi.h | 80 +++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h| 228 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 590 +++
drivers/gpu/drm/mediatek/mtk_drm_crtc.h| 56 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 218 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 39 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 424 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 86 +
[RFC v5 10/12] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 01f7365..e7b3997 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -550,7 +550,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090,
24, 4, 31),
/* CLK_CFG_6 */
- MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0,
3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16,
3, 23),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2,
31),
@@ -561,7 +561,7 @@ static const struct mtk_composite top_muxes[] __initconst =
{
MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
/* CLK_CFG_12 */
MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents,
0x00c0, 0, 3, 7),
- MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
+ MUX_GATE_FLAGS(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8,
2, 15, 0),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0,
24, 3, 31),
/* CLK_CFG_13 */
MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
0x00d0, 0, 3, 7),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f390cb0..1acb046 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -66,7 +66,7 @@ struct mtk_composite {
signed char num_parents;
};
-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
_flags) {\
.id = _id, \
.name = _name, \
.mux_reg = _reg,\
@@ -77,9 +77,12 @@ struct mtk_composite {
.divider_shift = -1,\
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents),\
- .flags = CLK_SET_RATE_PARENT, \
+ .flags = _flags,\
}
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)\
+ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate,
CLK_SET_RATE_PARENT)
+
#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
--
2.6.1
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[RFC v5 11/12] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index e7b3997..fe7a91b 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -901,6 +901,11 @@ static void __init mtk_apmixedsys_init(struct device_node
*node)
clk_data->clks[cku->id] = clk;
}
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+ base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h
b/include/dt-bindings/clock/mt8173-clk.h
index bf1302e..784e987 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -173,7 +173,8 @@
#define CLK_APMIXED_LVDSPLL13
#define CLK_APMIXED_MSDCPLL2 14
#define CLK_APMIXED_REF2USB_TX 15
-#define CLK_APMIXED_NR_CLK 16
+#define CLK_APMIXED_HDMI_REF 16
+#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */
--
2.6.1
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[RFC v5 01/12] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Move device tree binding documentation to
Documentation/devicetree/bindings/display/mediatek
- Clarified display function block nodes are siblings to mmsys
---
.../bindings/display/mediatek/mediatek,disp.txt| 183 +
.../bindings/display/mediatek/mediatek,dpi.txt | 35
.../bindings/display/mediatek/mediatek,dsi.txt | 53 ++
3 files changed, 271 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000..cc3d884
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,183 @@
+Mediatek display subsystem
+==
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space and register updates can
+be synchronized to video frame boundaries with help of a DISP_MUTEX function
+block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/drm/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,-disp-", one of
+ "mediatek,-disp-ovl" - overlay (4 layers, blending, csc)
+ "mediatek,-disp-rdma" - read DMA / line buffer
+ "mediatek,-disp-wdma" - write DMA
+ "mediatek,-disp-color" - color processor
+ "mediatek,-disp-aal" - adaptive ambient light controller
+ "mediatek,-disp-gamma" - gamma correction
+ "mediatek,-disp-ufoe" - data compression engine
+ "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt
+ "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
+ "mediatek,-disp-mutex" - display mutex
+ "mediatek,-disp-od"- overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- compatible: "mediatek,-ddp"
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+ "mediatek,-disp-ovl"
+ "mediatek,-disp-rdma"
+ "mediatek,-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as
defined
+ in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: required a iommu node
+
+Examples:
+
+mmsys: clock-controller@1400 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+};
+
+ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+};
+
+ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+};
+
+rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clock
[RFC v5 12/12] dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
Add an optional ddc-i2c-bus phandle property that points to an I2C master controller that handles the connector DDC pins. Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/video/hdmi-connector.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/video/hdmi-connector.txt b/Documentation/devicetree/bindings/video/hdmi-connector.txt index acd5668..508aee4 100644 --- a/Documentation/devicetree/bindings/video/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/video/hdmi-connector.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing Required nodes: - Video port for HDMI input -- 2.6.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v5 05/12] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Remove mediatek,cec and ddc-i2c-bus from hdmi node
- Make output port required
- Add mediatek, prefix to phy node current bias
properties
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 142 +
1 file changed, 142 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 000..e3dde29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,142 @@
+Mediatek HDMI Encoder
+=
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+ See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+ configuration registers. For mt8173 this must be offset 0x900 into the
+ MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+ definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port@0: The input port in the ports node should be connected to a DPI output
+ port.
+- port@1: The output port in the ports node should be connected to the input
+ port of a connector node that contains a ddc-i2c-bus property, or to the
+ input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- #phy-cells: must be <0>.
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy@10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0 0x11012000 0 0x1c>;
+ interrupts = ;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x9
[RFC v5 04/12] drm/mediatek: Add DPI sub driver
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 683
drivers/gpu/drm/mediatek/mtk_dpi.h | 80
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 1003 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 0d4aeeb..93380fe 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,7 +6,8 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..43eaf33
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dpi.h"
+#include "mtk_dpi_regs.h"
+
+enum mtk_dpi_polarity {
+ MTK_DPI_POLARITY_RISING,
+ MTK_DPI_POLARITY_FALLING,
+};
+
+struct mtk_dpi_polarities {
+ enum mtk_dpi_polarity de_pol;
+ enum mtk_dpi_polarity ck_pol;
+ enum mtk_dpi_polarity hsync_pol;
+ enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+ u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+ tmp |= (val & mask);
+ writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+ mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+}
+
+static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync,
+u32 width_addr, u32 porch_addr)
+{
+ mtk_dpi_mask(dpi, width_addr,
+sync->sync_width << VSYNC_WIDTH_SHIFT,
+VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, width_addr,
+sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+VSYNC_HALF_LINE_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+VSYNC_FRONT_PORCH_MASK);
+}
+
+static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
+}
+
+static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
+ struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
+DPI_TGEN_VPORCH_LEVEN);
+}
+
+static void mtk_dpi_config_vsyn
[RFC v5 07/12] drm/mediatek: enable hdmi output control bit
From: Jie Qiu
MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 6e91706..fbf6ecb 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -19,8 +19,15 @@
#include
#include
#include
+#include
#include
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
{
return readl(hdmi->regs + offset);
@@ -170,6 +177,10 @@ void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
{
+ invoke_psci_fn = __invoke_psci_fn_smc;
+ invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+ 0x14000904, 0x8000, 0);
+
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index de7ee22..8d7d60a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -218,4 +218,5 @@
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x8201
#endif
--
2.6.1
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[RFC v5 08/12] arm64: dts: mt8173: Add display subsystem related nodes
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
---
TODO:
- The power-domain property should be added to all blocks
that are in the MM power domain.
- The iommus property should be removed from the mmsys node.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 211 +++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 85ec24f..9874ab1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -284,6 +301,18 @@
#clock-cells = <1>;
};
+ mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
+ mipi_tx1: mipi-dphy@10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ #phy-cells = <0>;
+ };
+
gic: interrupt-controller@1022 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -417,6 +446,14 @@
status = "disabled";
};
+ hdmiddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = ;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
i2c6: i2c6@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@@ -553,7 +590,167 @@
mmsys: clock-controller@1400 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
+
+ /* FIXME - remove iommus here */
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>,
+<&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ };
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_LARB4_ID M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_LARB0_ID M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x140
Re: [RFC v2 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Hi Jitao,
Am Montag, den 02.11.2015, 10:09 +0800 schrieb Jitao Shi:
> Add documentation for DT properties supported by
> ps8640 DSI-eDP converter.
>
> Signed-off-by: Jitao Shi
> ---
> .../devicetree/bindings/display/bridge/ps8640.txt | 43
>
> 1 file changed, 43 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/ps8640.txt
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt
> b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
> new file mode 100644
> index 000..7edc547
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
> @@ -0,0 +1,43 @@
> +ps8640-bridge bindings
> +
> +Required properties:
> + - compatible: "parade,ps8640"
> + - reg: first page address of the bridge.
> + - sleep-gpios: OF device-tree gpio specification for PD_ pin.
> + - reset-gpios: OF device-tree gpio specification for reset pin.
> + - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
> + - vdd12-supply: OF device-tree regulator specification for 1.2V power.
> + - vdd33-supply: OF device-tree regulator specification for 3.3V power.
> + - ports: The device node can contain video interface port nodes per
> + the video-interfaces bind[1]. For port@0,set the reg = <0> as
> + ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
> +
> +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +Example:
> + edp-bridge@18 {
> + compatible = "parade,ps8640";
> + reg = <0x18>;
> + sleep-gpios = <&pio 116 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&pio 115 GPIO_ACTIVE_HIGH>;
> + mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
> + ps8640-1v2-supply = <&ps8640_fixed_1v2>;
> + ps8640-3v3-supply = <&mt6397_vgp2_reg>;
These two should be updated to the new regulator property names.
regards
Philipp
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Re: [RFC v2 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
Hi Jitao,
a few comments below.
Am Montag, den 02.11.2015, 11:54 +0800 schrieb jitao shi:
[...]
> > +static int ps8640_check_valid_id(struct ps8640 *ps_bridge)
This could be bool and return true/false.
> > +{
> > + struct i2c_client *client = ps_bridge->client;
> > + u8 rev_id_low, rev_id_high, chip_id_low, chip_id_high;
> > + int retry_cnt = 0;
> > +
> > + do {
> > + ps8640_regr(client, ps_bridge->base_reg + 4, PAGE4_CHIP_H,
> > + &chip_id_high);
> > + if (chip_id_high != 0x30)
> > + DRM_INFO("chip_id_high = 0x%x\n", chip_id_high);
> > + } while ((retry_cnt++ < 2) && (chip_id_high != 0x30));
> > +
> > + ps8640_regr(client, ps_bridge->base_reg + 4, PAGE4_REV_L, &rev_id_low);
> > + ps8640_regr(client, ps_bridge->base_reg + 4, PAGE4_REV_H, &rev_id_high);
> > + ps8640_regr(client, ps_bridge->base_reg + 4, PAGE4_CHIP_L,
> > + &chip_id_low);
> > +
> > + if ((rev_id_low == 0x00) && (rev_id_high == 0x0a) &&
> > + (chip_id_low == 0x00) && (chip_id_high == 0x30))
> > + return 1;
> > +
> > + return 0;
> > +}
> > +
> > +static void ps8640_show_mcu_fw_version(struct ps8640 *ps_bridge)
> > +{
> > + struct i2c_client *client = ps_bridge->client;
> > + u8 major_ver, minor_ver;
> > +
> > + ps8640_regr(client, ps_bridge->base_reg + 5, 0x4, &major_ver);
> > + ps8640_regr(client, ps_bridge->base_reg + 5, 0x5, &minor_ver);
> > +
> > + DRM_INFO_ONCE("ps8640 rom fw version %d.%d\n", major_ver, minor_ver);
> > +}
> > +
> > +static int ps8640_bdg_enable(struct ps8640 *ps_bridge)
> > +{
> > + struct i2c_client *client = ps_bridge->client;
> > +
> > + if (ps8640_check_valid_id(ps_bridge)) {
> > + ps8640_regw(client, ps_bridge->base_reg + 3, 0xfe, 0x13);
> > + ps8640_regw(client, ps_bridge->base_reg + 3, 0xff, 0x18);
> > + ps8640_regw(client, ps_bridge->base_reg + 3, 0xfe, 0x13);
> > + ps8640_regw(client, ps_bridge->base_reg + 3, 0xff, 0x1c);
Can you introduce #defines with descriptive names for those magic
constants and register offsets, and maybe also i2c address offsets?
> > +
> > + return 0;
> > + }
> > +
> > + return -1;
Never return -1 to signal a problem.
If there was an error, use a proper error code.
> > +}
> > +
> > +static void ps8640_prepare(struct ps8640 *ps_bridge)
> > +{
> > + struct i2c_client *client = ps_bridge->client;
> > + int err, retry_cnt = 0;
> > + u8 set_vdo_done;
> > +
> > + if (ps_bridge->enabled)
> > + return;
> > +
> > + if (drm_panel_prepare(ps_bridge->panel)) {
> > + DRM_ERROR("failed to prepare panel\n");
> > + return;
> > + }
> > +
> > + err = regulator_enable(ps_bridge->pwr_1v2_supply);
> > + if (err < 0) {
> > + DRM_ERROR("failed to enable pwr_1v2_supply: %d\n", err);
Missing panel unprepare.
> > + return;
> > + }
> > +
> > + err = regulator_enable(ps_bridge->pwr_3v3_supply);
> > + if (err < 0) {
> > + DRM_ERROR("failed to enable pwr_3v3_supply: %d\n", err);
Missing panel unprepare and vdd12 regulator disable.
> > + return;
> > + }
> > +
> > + gpiod_set_value(ps_bridge->gpio_slp_n, 1);
> > + gpiod_set_value(ps_bridge->gpio_rst_n, 0);
> > + usleep_range(500, 700);
> > + gpiod_set_value(ps_bridge->gpio_rst_n, 1);
> > +
> > + do {
> > + msleep(50);
> > + ps8640_regr(client, ps_bridge->base_reg + 2, PAGE2_GPIO_H,
> > + &set_vdo_done);
> > + } while ((retry_cnt++ < 70) && ((set_vdo_done & PS_GPIO9) != PS_GPIO9));
> > +
> > + ps8640_show_mcu_fw_version(ps_bridge);
> > + ps_bridge->enabled = true;
> > +}
> > +
> > +static void ps8640_pre_enable(struct drm_bridge *bridge)
> > +{
> > + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> > +
> > + ps8640_prepare(ps_bridge);
> > +}
> > +
> > +static void ps8640_enable(struct drm_bridge *bridge)
> > +{
> > + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> > +
> > + ps8640_bdg_enable(ps_bridge);
> > +
> > + if (drm_panel_enable(ps_bridge->panel)) {
> > + DRM_ERROR("failed to enable panel\n");
> > + return;
The return is superfluous.
> > + }
> > +}
> > +
> > +static void ps8640_disable(struct drm_bridge *bridge)
> > +{
> > + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> > +
> > + if (!ps_bridge->enabled)
> > + return;
> > +
> > + ps_bridge->enabled = false;
> > +
> > + if (drm_panel_disable(ps_bridge->panel)) {
> > + DRM_ERROR("failed to disable panel\n");
> > + return;
Shouldn't we still disable the bridge, even if panel disable fails?
> > + }
> > +
> > + regulator_disable(ps_bridge->pwr_1v2_supply);
> > + regulator_disable(ps_bridge->pwr_3v3_supply);
> > + gpiod_set_value(ps_bridge->gpio_rst_n, 0);
> > + gpiod_set_value(ps_bridge->gpio_slp_n, 0);
> > +}
> > +
> > +static void ps8640_post_disable(struct drm_bridge *bridge)
Re: [RFC v2 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
Hi Jitao,
Am Montag, den 02.11.2015, 11:53 +0800 schrieb jitao shi:
[...]
> > +Example:
> > + edp-bridge@18 {
> > + compatible = "parade,ps8640";
> > + reg = <0x18>;
> > + sleep-gpios = <&pio 116 GPIO_ACTIVE_HIGH>;
> > + reset-gpios = <&pio 115 GPIO_ACTIVE_HIGH>;
> > + mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
> > + ps8640-1v2-supply = <&ps8640_fixed_1v2>;
This should be vdd12-supply now.
> > + ps8640-3v3-supply = <&mt6397_vgp2_reg>;
Should be vdd33-supply now.
regards
Philipp
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Re: [RFC v4 05/11] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
Hi Rob, thank you for the comments. Am Freitag, den 23.10.2015, 07:29 -0500 schrieb Rob Herring: [...] > > +Mediatek HDMI Encoder > > += > > + > > +The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from > > +its parallel input. > > How do you know whether it is HDMI or MHL on a given board? You should > have a connector node perhaps. Sounds sensible. I haven't really thought about MHL, my test board has a slimport bridge. For HDMI we already have the "hdmi-connector" compatible. I suppose for MHL we'd have to add a new "usb-connector"? > > + > > +Required properties: > > +- compatible: Should be "mediatek,-hdmi". > > +- reg: Physical base address and length of the controller's registers > > +- interrupts: The interrupt signal from the function block. > > +- clocks: device clocks > > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for > > details. > > +- clock-names: must contain "pixel", "pll", "bclk", and "spdif". > > +- mediatek,cec: phandle link to the HDMI CEC node. > > Do you have more than 1 CEC block? If not, just find the compatible > node with of_find_compatible_node. MT8173 only has one CEC block, so I will drop this property again. > > +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing > > This really should be part of a connector node as I2C bus goes to the > connector, not the HDMI block. So I should add that as an optional property to the hdmi-connector binding. I'll have to check how DDC is handled for MHL. [...] > > +HDMI PHY > > + > > + > > +The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > > +output and drives the HDMI pads. > > + > > +Required properties: [...] > > + > > +Optional properties: > > +- ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > > +- ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > > prefix with "mediatek," Will do. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC v4 02/11] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Daniel,
Am Montag, den 19.10.2015, 10:56 +0200 schrieb Daniel Vetter:
> On Fri, Oct 16, 2015 at 10:12:04PM +0200, Philipp Zabel wrote:
> > From: CK Hu
> >
> > This patch adds an initial DRM driver for the Mediatek MT8173 DISP
> > subsystem. It currently supports two fixed output streams from the
> > OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
> >
> > Signed-off-by: CK Hu
> > Signed-off-by: YT Shen
> > Signed-off-by: Philipp Zabel
>
> Bunch of drive-by comments below to point out deprecated functions and
> more common approaches used by other drivers. Don't consider this a full
> review ;-)
Much appreciated all the same.
> Cheers, Daniel
>
> > ---
> > Changes since v3:
> > - Removed crtc enabling/disabling on bind/unbind, the enable/disable
> >callbacks should suffice.
> > - Find sibling components in the device tree via compatible value
>
> btw for DT components stuff there's piles of RFCs floating around to
> extract this into helper libraries. Would be great we could push one of
> them forward.
The non-mediatek-specific part currently is the
for_each_child_of_node(bus_node, node) {
of_id = of_match_node(dt_ids, node);
if (!of_id)
continue;
if (!of_device_is_available(node))
continue;
/* ... */
}
loop. This is somewhat similar to a combination of
for_each_matching_node_and_match and for_each_available_child_of_node.
for_each_available_matching_child_of_node_and_match would be quite a
mouthful though.
[...]
> > +struct mtk_drm_crtc {
> > + struct drm_crtc base;
> > + unsigned intpipe;
> > + boolenabled;
> > + struct mtk_crtc_ddp_context *ctx;
> > +
> > + struct drm_pending_vblank_event *event;
> > + boolpending_needs_vblank;
> > +};
> > +
> > +struct mtk_crtc_ddp_context {
> > + struct device *dev;
> > + struct drm_device *drm_dev;
> > + struct mtk_drm_crtc *crtc;
> > + struct mtk_drm_planeplanes[OVL_LAYER_NR];
> > + int pipe;
> > +
> > + void __iomem*config_regs;
> > + struct device *mutex_dev;
> > + u32 ddp_comp_nr;
> > + struct mtk_ddp_comp *ddp_comp;
>
> All the above probably should just be moved into mtk_drm_crtc. At least I
> don't understand why you need this indirection.
Agreed. This was needed for a debugfs patch that I have left out for
now.
> > +
> > + boolpending_config;
> > + unsigned intpending_width;
> > + unsigned intpending_height;
> > +
> > + boolpending_ovl_config[OVL_LAYER_NR];
> > + boolpending_ovl_enable[OVL_LAYER_NR];
> > + unsigned intpending_ovl_addr[OVL_LAYER_NR];
> > + unsigned intpending_ovl_pitch[OVL_LAYER_NR];
> > + unsigned intpending_ovl_format[OVL_LAYER_NR];
> > + int pending_ovl_x[OVL_LAYER_NR];
> > + int pending_ovl_y[OVL_LAYER_NR];
> > + unsigned intpending_ovl_size[OVL_LAYER_NR];
> > + boolpending_ovl_dirty[OVL_LAYER_NR];
>
> This works since you only touch these in the atomic_commit phase, but the
> recommend way to do this with atomic is to subclass drm_crtc_state:
>
> struct mtk_crtc_state {
> struct drm_crtc_state base;
>
> /* all the pending_ stuff above */
> };
>
> Then you just pass the mtk to your irq handler to do the update.
I'll move these into mtk_crtc_state, but I'm not sure what you mean with
the last sentence. Currently I pass the mtk_crtc_ddp_context to the irq
handler. I can get to the mtk_crtc_state from that.
> > +static int mtk_drm_bind(struct device *dev)
> > +{
> > + return drm_platform_init(&mtk_drm_driver, to_platform_device(dev));
>
> This is deprecated, please use drm_dev_alloc/drm_dev_register instead and
> remove your ->load driver callback.
Will replace drm_platform_init with drm_dev_alloc/drm_dev_register and
integrate mtk_drm_load into mtk_drm_bind.
> > +int mtk_drm_gem_dumb_map_offset(struct drm_file *file_priv,
> > + struct drm_device *dev, uint32
Re: [RFC v4 02/11] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
Hi Daniel,
Am Montag, den 19.10.2015, 10:56 +0200 schrieb Daniel Vetter:
> On Fri, Oct 16, 2015 at 10:12:04PM +0200, Philipp Zabel wrote:
> > From: CK Hu
> >
> > This patch adds an initial DRM driver for the Mediatek MT8173 DISP
> > subsystem. It currently supports two fixed output streams from the
> > OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
> >
> > Signed-off-by: CK Hu
> > Signed-off-by: YT Shen
> > Signed-off-by: Philipp Zabel
>
> Bunch of drive-by comments below to point out deprecated functions and
> more common approaches used by other drivers. Don't consider this a full
> review ;-)
Much appreciated all the same.
> Cheers, Daniel
>
> > ---
> > Changes since v3:
> > - Removed crtc enabling/disabling on bind/unbind, the enable/disable
> >callbacks should suffice.
> > - Find sibling components in the device tree via compatible value
>
> btw for DT components stuff there's piles of RFCs floating around to
> extract this into helper libraries. Would be great we could push one of
> them forward.
The non-mediatek-specific part currently is the
for_each_child_of_node(bus_node, node) {
of_id = of_match_node(dt_ids, node);
if (!of_id)
continue;
if (!of_device_is_available(node))
continue;
/* ... */
}
loop. This is somewhat similar to a combination of
for_each_matching_node_and_match and for_each_available_child_of_node.
for_each_available_matching_child_of_node_and_match would be quite a
mouthful though.
[...]
> > +struct mtk_drm_crtc {
> > + struct drm_crtc base;
> > + unsigned intpipe;
> > + boolenabled;
> > + struct mtk_crtc_ddp_context *ctx;
> > +
> > + struct drm_pending_vblank_event *event;
> > + boolpending_needs_vblank;
> > +};
> > +
> > +struct mtk_crtc_ddp_context {
> > + struct device *dev;
> > + struct drm_device *drm_dev;
> > + struct mtk_drm_crtc *crtc;
> > + struct mtk_drm_planeplanes[OVL_LAYER_NR];
> > + int pipe;
> > +
> > + void __iomem*config_regs;
> > + struct device *mutex_dev;
> > + u32 ddp_comp_nr;
> > + struct mtk_ddp_comp *ddp_comp;
>
> All the above probably should just be moved into mtk_drm_crtc. At least I
> don't understand why you need this indirection.
Agreed. This was needed for a debugfs patch that I have left out for
now.
> > +
> > + boolpending_config;
> > + unsigned intpending_width;
> > + unsigned intpending_height;
> > +
> > + boolpending_ovl_config[OVL_LAYER_NR];
> > + boolpending_ovl_enable[OVL_LAYER_NR];
> > + unsigned intpending_ovl_addr[OVL_LAYER_NR];
> > + unsigned intpending_ovl_pitch[OVL_LAYER_NR];
> > + unsigned intpending_ovl_format[OVL_LAYER_NR];
> > + int pending_ovl_x[OVL_LAYER_NR];
> > + int pending_ovl_y[OVL_LAYER_NR];
> > + unsigned intpending_ovl_size[OVL_LAYER_NR];
> > + boolpending_ovl_dirty[OVL_LAYER_NR];
>
> This works since you only touch these in the atomic_commit phase, but the
> recommend way to do this with atomic is to subclass drm_crtc_state:
>
> struct mtk_crtc_state {
> struct drm_crtc_state base;
>
> /* all the pending_ stuff above */
> };
>
> Then you just pass the mtk to your irq handler to do the update.
I'll move these into mtk_crtc_state, but I'm not sure what you mean with
the last sentence. Currently I pass the mtk_crtc_ddp_context to the irq
handler. I can get to the mtk_crtc_state from that.
> > +static int mtk_drm_bind(struct device *dev)
> > +{
> > + return drm_platform_init(&mtk_drm_driver, to_platform_device(dev));
>
> This is deprecated, please use drm_dev_alloc/drm_dev_register instead and
> remove your ->load driver callback.
Will replace drm_platform_init with drm_dev_alloc/drm_dev_register and
integrate mtk_drm_load into mtk_drm_bind.
> > +int mtk_drm_gem_dumb_map_offset(struct drm_file *file_priv,
> > + struct drm_device *dev, uint32
Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets
Hi Jens,
Am Dienstag, den 27.10.2015, 17:50 +0100 schrieb Jens Kuske:
[...]
> --- a/drivers/reset/reset-sunxi.c
> +++ b/drivers/reset/reset-sunxi.c
> @@ -75,7 +75,9 @@ static struct reset_control_ops sunxi_reset_ops = {
> .deassert = sunxi_reset_deassert,
> };
>
> -static int sunxi_reset_init(struct device_node *np)
> +static int sunxi_reset_init(struct device_node *np,
> + int (*of_xlate)(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *reset_spec))
I'd add a tab to the indentation and drop the of_xlate parameter names.
If you agree to this change, I'll fix it up when I apply it.
best regards
Philipp
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[RFC v4 03/11] drm/mediatek: Add DSI sub driver
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v3:
- Simplified bind function
- Removed superfluous module_platform_driver
- Fixed phy power refcounting (double phy_power_off)
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 19 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 787 +
drivers/gpu/drm/mediatek/mtk_dsi.h | 54 +++
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 375
drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 21 +
7 files changed, 1261 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index ba6d3fc..0d4aeeb 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,7 +4,9 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_ddp_comp.o \
mtk_drm_fb.o \
mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index bb03b4a..6a6c792 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -534,8 +534,25 @@ static int __init mtk_drm_init(void)
goto drm_err;
}
+ ret = platform_driver_register(&mtk_dsi_driver);
+ if (ret < 0) {
+ pr_err("Failed to register DSI platform driver: %d\n!", ret);
+ goto disp_ovl_err;
+ }
+
+ ret = platform_driver_register(&mtk_mipi_tx_driver);
+ if (ret < 0) {
+ pr_err("Failed to register MIPI TX platform driver: %d\n!",
+ ret);
+ goto dsi_err;
+ }
+
return 0;
+dsi_err:
+ platform_driver_unregister(&mtk_dsi_driver);
+disp_ovl_err:
+ platform_driver_unregister(&mtk_disp_ovl_driver);
drm_err:
platform_driver_unregister(&mtk_drm_platform_driver);
err:
@@ -544,6 +561,8 @@ err:
static void __exit mtk_drm_exit(void)
{
+ platform_driver_unregister(&mtk_mipi_tx_driver);
+ platform_driver_unregister(&mtk_dsi_driver);
platform_driver_unregister(&mtk_disp_ovl_driver);
platform_driver_unregister(&mtk_drm_platform_driver);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 5e5128e..9c81abe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -57,5 +57,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..fe3c450
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dsi.h"
+#include "mtk_mipi_tx.h"
+
+#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START 0x00
+
+#define DSI_CON_CTRL 0x10
+#define DSI_RESET BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL 0x14
+#define MODE (3)
+#define CMD_MODE 0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE BIT(16)
+#define MIX_MODE BIT(17)
+
+#define DSI_TXRX_CTRL 0x18
+#define VC_NUM
[RFC v4 04/11] drm/mediatek: Add DPI sub driver
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
- Removed unused mtk_dpi_config_bit_swap function
- Enable/disable pixel clock instead of its ancestor PLL
- Instead of manually setting the dpi0_sel mux to the different divider
parents, call clk_set_rate on the leaf pixel clock.
This currently looks more complicated than it needs to be, it can
be simplified when the dpi0_sel mux gets changed to round_closest
- Drop the div and sel clock inputs
- Do not enable the pixel clock in the probe function. This allows to actually
power down the TVDPLL while HDMI output is disabled.
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 683
drivers/gpu/drm/mediatek/mtk_dpi.h | 80
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 9 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 1003 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 0d4aeeb..93380fe 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,7 +6,8 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..43eaf33
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_dpi.h"
+#include "mtk_dpi_regs.h"
+
+enum mtk_dpi_polarity {
+ MTK_DPI_POLARITY_RISING,
+ MTK_DPI_POLARITY_FALLING,
+};
+
+struct mtk_dpi_polarities {
+ enum mtk_dpi_polarity de_pol;
+ enum mtk_dpi_polarity ck_pol;
+ enum mtk_dpi_polarity hsync_pol;
+ enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+ u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+ tmp |= (val & mask);
+ writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+ mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync)
+{
+ mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
+ HFP_MASK);
+}
+
+static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
+struct mtk_dpi_sync_param *sync,
+u32 width_addr, u32 porch_addr)
+{
+ mtk_dpi_mask(dpi, width_addr,
+sync->sync_width << VSYNC_WIDTH_SHIFT,
+VSYNC_WIDTH_MASK);
+ mtk_dpi_mask(dpi, width_addr,
+sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+VSYNC_HALF_LINE_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+VSYNC_BACK_PORCH_MASK);
+ mtk_dpi_mask(dpi, porch_addr,
+sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
[RFC v4 06/11] drm/mediatek: Add HDMI support
From: Daniel Kurtz This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- Changes since v3: - Split CEC register access out into a separate driver, I suppose this will grow CEC I/O functionality in the future. The hotplug interrupt is handled by the CEC module. - Dropped DT configurable min_clock and max_clock - Changed MMSYS_CONFIG access to syscon/regmap - Use clk_set_rate on the pll_ck input instead of manually setting the hdmi_sel parent, dropped sel, div, cec and dpi clocks from the hdmi driver - Moved hotplug irq handling into the CEC driver, stopped disabling the hotplug irq on hdmi_power_off - Removed direct register access to the undocumented apmixedsys register, this turned out to be the divider feeding the hdmi_ref PLL reference input to the PHY. - Add PLL reference clock handling to the PHY. - Disable hdmi_pll and pll_ref clock inputs while HDMI output is disabled. --- drivers/gpu/drm/mediatek/Kconfig| 6 + drivers/gpu/drm/mediatek/Makefile | 8 + drivers/gpu/drm/mediatek/mtk_cec.c | 252 + drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c | 630 ++ drivers/gpu/drm/mediatek/mtk_hdmi.c | 515 ++ drivers/gpu/drm/mediatek/mtk_hdmi.h | 119 + drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c | 362 + drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 778 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 +++ drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 339 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 20 + drivers/gpu/drm/mediatek/mtk_hdmi_regs.h| 320 include/drm/mediatek/mtk_hdmi_audio.h | 150 ++ 15 files changed, 3601 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 include/drm/mediatek/mtk_hdmi_audio.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index 5343cf1..85af51c 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -14,3 +14,9 @@ config DRM_MEDIATEK This driver provides kernel mode setting and buffer management to userspace. +config DRM_MEDIATEK_HDMI + tristate "DRM HDMI Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select GENERIC_PHY + help + DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 93380fe..e2a5c5c 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -11,3 +11,11 @@ mediatek-drm-y := mtk_drm_drv.o \ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o +mediatek-drm-hdmi-objs := mtk_drm_hdmi_drv.o \ + mtk_cec.o \ + mtk_hdmi_ddc_drv.o \ + mtk_hdmi.o \ + mtk_hdmi_hw.o \ + mtk_hdmi_phy.o + +obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c new file mode 100644 index 000..5fa7888 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Jie Qiu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include + +#define TR_CONFIG 0x00 +#define CLEAR_CEC_IRQ BIT(15) + +#define CEC_CKGEN 0x04 +#define CEC_32K_PDNBIT(19) +#define PDNBIT(16) + +#define RX_EVENT 0x54 +#define HDMI_PORD BIT(25
