Re: [PATCH 1/3] pinctrl: Broadcom NSP GPIO-a device tree bindings
Hi Rob, On 12/2/2015 7:07 AM, Rob Herring wrote: On Tue, Dec 01, 2015 at 11:46:38PM -0500, Yendapally Reddy Dhananjaya Reddy wrote: Device tree binding documentation for Broadcom NSP GPIO-a driver Bindings are for h/w, not drivers... Signed-off-by: Yendapally Reddy Dhananjaya Reddy --- .../devicetree/bindings/pinctrl/brcm,nsp-gpio.txt | 80 ++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt new file mode 100644 index 000..bea4211 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt @@ -0,0 +1,80 @@ +Broadcom Northstar plus (NSP) GPIO/PINCONF Controller + +Required properties: +- compatible: +Must be "brcm,nsp-gpio-a" + +- reg: +Should contain the register physical address and length for each of +GPIO base, IO control registers + +- #gpio-cells: +Must be two. The first cell is the GPIO pin number (within the +controller's pin space) and the second cell is used for the following: +bit[0]: polarity (0 for active high and 1 for active low) + +- gpio-controller: +Specifies that the node is a GPIO controller + +- ngpios: +Number of gpios supported (58x25 supports 32 and 58x23 supports 24) 2 chips? You should have 2 compatible strings. I think this is incorrect use of ngpios which AIUI is not for how many lines there are, but how many can be used (e.g. not reserved). I believe this is the identical GPIO controller IP that is integrated into two different SoC chip variants. The only difference is the supported number of GPIO pins. In this case, I believe this is what Linus prefers: 1) Using a single compatible string (tied to the GPIO controller IP); 2) Addressing difference in number of GPIOs using DT property 'ngpios'. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Enable PCIe PHY support in Cygnus
On 12/1/2015 3:12 PM, Florian Fainelli wrote: On 24/11/15 16:12, Florian Fainelli wrote: On 18/11/15 10:16, Ray Jui wrote: This patch enales PCIe PHY in device tree for Broadcom Cygnus based platforms This patch is developed based on v4.4-rc1 and available here: https://github.com/Broadcom/cygnus-linux/tree/cygnus-pcie-phy-dt-v1 Ray Jui (1): ARM: dts: enable PCIe PHY support for Cygnus Applied to devicetree/next with Scott's Acked-by, thanks! This caused the DTC compiler to warn: Warning (reg_format): "reg" property in /axi/phy@0301d0a0/phy@0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (reg_format): "reg" property in /axi/phy@0301d0a0/phy@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /axi/phy@0301d0a0/phy@0 Warning (avoid_default_addr_size): Relying on default #size-cells value for /axi/phy@0301d0a0/phy@0 Warning (avoid_default_addr_size): Relying on default #address-cells value for /axi/phy@0301d0a0/phy@1 Warning (avoid_default_addr_size): Relying on default #size-cells value for /axi/phy@0301d0a0/phy@1 CC drivers/base/power/runtime.o DTC arch/arm/boot/dts/bcm911360k.dtb CC lib/bitmap.o I added an #address-cells = <0> and #size-cells = <1> to fix this, since your reg property is a single digit. Sorry I missed that. Both are required properties. Thanks! Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: dts: enable pinctrl for Broadcom NSP
On 12/1/2015 8:05 AM, Scott Branden wrote: Hi Linus, On 15-12-01 02:00 AM, Linus Walleij wrote: On Wed, Nov 25, 2015 at 1:08 AM, Florian Fainelli wrote: On 20/11/15 09:58, Yendapally Reddy Dhananjaya Reddy wrote: This enables the pinctrl support for Broadcom NSP SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Looks like a sane pinctrl node here, unless there are objections, I would like to go ahead and apply this for v4.5, thanks! I'm waiting for an indication from the other BCM pinctrl maintainers to tell whether this SoC is unique enough to deserve its own driver. If Stephen Warren is the other maintainer you are talking about he does not work at Broadcom. I don't think he is familiar with the variety of pinctrl implementations present. But yes, the pinctrl implementations have been rather unique in these Socs. As Ray indicated we're trying to get the silicon designers to standardize more going forward so we don't have to create unique drivers for these SoCs. Yes. Hopefully NSP and NS2 will be the last iProc based SoCs that require unique pinmux driver. Yours, Linus Walleij Regards, Scott Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: enable PCIe PHY support for Cygnus
Any comment on this DT change to enable PCIe PHY support for Cygnus?
Note the PHY driver has been accepted and is in v4.4.
Thanks,
Ray
On 11/18/2015 10:16 AM, Ray Jui wrote:
Enable PCIe PHY for both PCIe root complexes on Cygnus
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 2778533..5df5300 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -91,6 +91,21 @@
#address-cells = <1>;
#size-cells = <1>;
+ pcie_phy: phy@0301d0a0 {
+ compatible = "brcm,cygnus-pcie-phy";
+ reg = <0x0301d0a0 0x14>;
+
+ pcie0_phy: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
@@ -161,6 +176,9 @@
ranges = <0x8100 0 0 0x2800 0 0x0001
0x8200 0 0x2000 0x2000 0
0x0400>;
+ phys = <&pcie0_phy>;
+ phy-names = "pcie-phy";
+
status = "disabled";
};
@@ -182,6 +200,9 @@
ranges = <0x8100 0 0 0x4800 0 0x0001
0x8200 0 0x4000 0x4000 0
0x0400>;
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+
status = "disabled";
};
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Re: [PATCH v3 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks
Hi Jon, On 11/20/2015 7:17 AM, Jon Mason wrote: Changes in v3: Tweaked the NSP entry names, per Ray Jui Changes in v2: Rebased off of outstanding NSP DT patches and tweaked the entry names per Ray Jui This patch series adds device tree support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to the inability to merge because of the driver dependencies. Those necessary driver changes were merged into 4.4. All comments have been addressed and it is ready to be pulled in. Jon Mason (3): ARM: dts: enable clock support for BCM5301X ARM: dts: enable clock support for Broadcom NSP ARM64: dts: enable clock support for Broadcom NS2 arch/arm/boot/dts/bcm-nsp.dtsi| 81 -- arch/arm/boot/dts/bcm5301x.dtsi | 92 +++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +- 3 files changed, 216 insertions(+), 37 deletions(-) This entire patch series looks good to me! Thanks! Reviewed-by: Ray Jui -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/3] ARM: dts: enable clock support for Broadcom NSP
On 11/19/2015 3:05 PM, Jon Mason wrote:
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 77 +++---
1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b74438c..361c2a6 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,16 +59,23 @@
};
};
+ a9pll: arm_clk@ {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x 0x1000>;
+ };
+
timer@0200 {
timer@20200. Or is this addressed in another patch? I completely lose
track of these
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
twd-timer@0600 {
twd-timer@20600
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -75,7 +83,7 @@
twd-watchdog@0620 {
same here
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -86,13 +94,13 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
cache-level = <2>;
};
@@ -103,10 +111,34 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
@@ -118,17 +150,17 @@
uart0: serial@0300 {
compatible = "ns16550a";
- reg = <0x0300 0x100>;
+ reg = <0x000300 0x100>;
interrupts = ;
- clock-frequency = <62499840>;
+ clocks = <&osc>;
status = "disabled";
};
uart1: serial@0400 {
compatible = "ns16550a";
- reg = <0x0400 0x100>;
+ reg = <0x000400 0x100>;
interrupts = ;
- clock-frequency = <62499840>;
+ clocks = <&osc>;
status = "disabled";
};
@@ -226,5 +258,24 @@
interrupts = ;
clock-fre
Re: [PATCH 2/3] ARM: dts: enable clock support for Broadcom NSP
On 11/19/2015 7:48 AM, Jon Mason wrote:
On Wed, Nov 18, 2015 at 03:57:36PM -0800, Ray Jui wrote:
Would this patch merge properly with the other NSP DT clean up patch
+ I2C DT patch that you worked out internally but have not sent out?
I thought it's going to make the maintainers' life easier if you can
group DT changes per platform and send them out in the same series.
I also have some inline comments below.
On 11/18/2015 3:13 PM, Jon Mason wrote:
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 99 --
1 file changed, 75 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 4bcdd28..f85a4f1 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
Why does this have anything to do with clocks? Shouldn't it be a
separate patch?
No, this is correct (though the patch is a little odd to look at).
The a9pll starts at 0x1900 instead of 0x1902. So, everything
needs to be adjusted.
Okay.
#address-cells = <1>;
#size-cells = <1>;
@@ -58,32 +59,23 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ a9pll: arm_clk@1900 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
};
timer@19020200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
twd-timer@19020600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -91,11 +83,27 @@
twd-watchdog@19020620 {
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
+
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
From here and above, all labels are wrong. You are moving them into
a bus that has translated bus addresses, but you still use absolute
addresses for all labels.
Please fix all the labels.
And again, 1) Why is this change imbedded in a patch meant for
adding DT clock support according to the commit message; 2) how does
the dependency work with the other patches that you are about to
send out?
This was already discussed in the original series. See
http://www.spinics.net/lists/arm-kernel/msg451580.html
The discussion explains my first question. But what about my second
question? How does the dependency work with other NSP DT patches that
you have on hand? Will there be conflicts? If so, do you expect the
maintainers need to manually fix all t
Re: [PATCH 3/3] ARM64: dts: enable clock support for Broadcom NS2
On 11/18/2015 4:07 PM, Florian Fainelli wrote:
On 18/11/15 16:03, Ray Jui wrote:
On 11/18/2015 3:13 PM, Jon Mason wrote:
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 80
++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 9610822..a510d3a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -109,6 +110,33 @@
<&A57_3>;
};
+clocks {
Is this a new convention? That is, group all clocks without a base
register address in a node named "clocks", but at the same time, put all
other clocks with base register address under a bus node.
I do not think that is new, lots of platforms do that. The clock
providers/controllers would typically be in the 'bus' nodes because it
has a register interface, while the synthetic clocks would be under
'clocks'.
Okay that's very good to know. Thanks!
Ray
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Re: [PATCH 3/3] ARM64: dts: enable clock support for Broadcom NS2
On 11/18/2015 3:13 PM, Jon Mason wrote:
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 ++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 9610822..a510d3a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -109,6 +110,33 @@
<&A57_3>;
};
+ clocks {
Is this a new convention? That is, group all clocks without a base
register address in a node named "clocks", but at the same time, put all
other clocks with base register address under a bus node.
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -156,6 +184,56 @@
mmu-masters;
};
+ lcpll_ddr: lcpll_ddr@6501d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x6501d058 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+"ddr", "ddr_ch2_unused",
+"ddr_ch3_unused", "ddr_ch4_unused",
+"ddr_ch5_unused";
+ };
+
+ lcpll_ports: lcpll_ports@6501d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x6501d078 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+"ports_ch2_unused",
+"ports_ch3_unused",
+"ports_ch4_unused",
+"ports_ch5_unused";
+ };
+
+ genpll_scr: genpll_scr@6501d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x6501d098 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+"audio_ref", "scr_ch3_unused",
+"scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: genpll_sw@6501d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x6501d0c4 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+"chimp", "port", "sdio";
+ };
+
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
@@ -204,7 +282,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <23961600>;
+ clocks = <&osc>;
status = "disabled";
};
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Re: [PATCH 2/3] ARM: dts: enable clock support for Broadcom NSP
Would this patch merge properly with the other NSP DT clean up patch +
I2C DT patch that you worked out internally but have not sent out?
I thought it's going to make the maintainers' life easier if you can
group DT changes per platform and send them out in the same series.
I also have some inline comments below.
On 11/18/2015 3:13 PM, Jon Mason wrote:
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 99 --
1 file changed, 75 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 4bcdd28..f85a4f1 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
Why does this have anything to do with clocks? Shouldn't it be a
separate patch?
#address-cells = <1>;
#size-cells = <1>;
@@ -58,32 +59,23 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ a9pll: arm_clk@1900 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
};
timer@19020200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
twd-timer@19020600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -91,11 +83,27 @@
twd-watchdog@19020620 {
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
+
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
From here and above, all labels are wrong. You are moving them into a
bus that has translated bus addresses, but you still use absolute
addresses for all labels.
And again, 1) Why is this change imbedded in a patch meant for adding DT
clock support according to the commit message; 2) how does the
dependency work with the other patches that you are about to send out?
};
clocks {
@@ -103,10 +111,34 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult
[PATCH] ARM: dts: enable PCIe PHY support for Cygnus
Enable PCIe PHY for both PCIe root complexes on Cygnus
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 2778533..5df5300 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -91,6 +91,21 @@
#address-cells = <1>;
#size-cells = <1>;
+ pcie_phy: phy@0301d0a0 {
+ compatible = "brcm,cygnus-pcie-phy";
+ reg = <0x0301d0a0 0x14>;
+
+ pcie0_phy: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
@@ -161,6 +176,9 @@
ranges = <0x8100 0 0 0x2800 0
0x0001
0x8200 0 0x2000 0x2000 0
0x0400>;
+ phys = <&pcie0_phy>;
+ phy-names = "pcie-phy";
+
status = "disabled";
};
@@ -182,6 +200,9 @@
ranges = <0x8100 0 0 0x4800 0
0x0001
0x8200 0 0x4000 0x4000 0
0x0400>;
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+
status = "disabled";
};
--
1.9.1
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[PATCH] Enable PCIe PHY support in Cygnus
This patch enales PCIe PHY in device tree for Broadcom Cygnus based platforms This patch is developed based on v4.4-rc1 and available here: https://github.com/Broadcom/cygnus-linux/tree/cygnus-pcie-phy-dt-v1 Ray Jui (1): ARM: dts: enable PCIe PHY support for Cygnus arch/arm/boot/dts/bcm-cygnus.dtsi | 21 + 1 file changed, 21 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 11/17/2015 5:55 AM, Marc Zyngier wrote:
On 17/11/15 13:27, Bharat Kumar Gogada wrote:
On Tue, 17 Nov 2015 04:59:39 +
Bharat Kumar Gogada wrote:
On 11/16/2015 7:14 AM, Marc Zyngier wrote:
On 11/11/15 06:33, Bharat Kumar Gogada wrote:
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
---
Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc
function.
Moved MSI functionality to separate functions.
Changed error return values.
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 68 ++
drivers/pci/host/Kconfig | 16 +-
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx-nwl.c | 1062
4 files changed, 1144 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/pci/xilinx-nwl-
pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
[...]
+static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct
+pci_bus
+*bus) {
+ struct platform_device *pdev = to_platform_device(pcie-
dev);
+ struct nwl_msi *msi = &pcie->msi;
+ unsigned long base;
+ int ret;
+
+ mutex_init(&msi->lock);
+
+ /* Check for msii_present bit */
+ ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) &
MSII_PRESENT;
+ if (!ret) {
+ dev_err(pcie->dev, "MSI not present\n");
+ ret = -EIO;
+ goto err;
+ }
+
+ /* Enable MSII */
+ nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
I_MSII_CONTROL) |
+ MSII_ENABLE, I_MSII_CONTROL);
+
+ /* Enable MSII status */
+ nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
I_MSII_CONTROL) |
+ MSII_STATUS_ENABLE, I_MSII_CONTROL);
+
+ /* setup AFI/FPCI range */
+ msi->pages = __get_free_pages(GFP_KERNEL, 0);
+ base = virt_to_phys((void *)msi->pages);
+ nwl_bridge_writel(pcie, lower_32_bits(base),
I_MSII_BASE_LO);
+ nwl_bridge_writel(pcie, upper_32_bits(base),
I_MSII_BASE_HI);
BTW, you still haven't answered my question as to why you need to
waste a page of memory here, and why putting a device address
doesn't
work.
As this is (to the best of my knowledge) the only driver doing so,
I'd really like you to explain the rational behind this.
Might not be the only driver doing so after I start sending out
patches for the iProc MSI support (soon), :)
I'm not sure how it works for the Xilinx NWL controller, which
Bharat should be able to help to explain. But for the iProc MSI
controller, there's no device I/O memory reserved for MSI posted writes
in the ASIC.
Therefore one needs to reserve host memory for these writes.
Our SoC doesn't reserve any memory for MSI, hence we need to assign a
memory space for it out of RAM.
Question to both of you: Does the write make it to memory? Or is it sampled
by the bridge and dropped?
No, write will not do any modification in memory, it is consumed by bridge.
Then you do not need to allocate memory at all. Use whatever memory you
already have. CC-ing Robin, as this may have interaction with the SMMU.
What happens if you replace the page in RAM with a dummy address?
What do you mean by dummy address ?
Any random (and suitably aligned) address. 0x0deadbeef000 for example.
In our case, I'm pretty sure the writes make it to memory (RAM). I can
try replacing it with a dummy address, but I'm pretty sure that will not
work.
Thanks,
Ray
Thanks,
M.
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Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 11/10/2015 10:33 PM, Bharat Kumar Gogada wrote:
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
---
Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc function.
Moved MSI functionality to separate functions.
Changed error return values.
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 68 ++
drivers/pci/host/Kconfig | 16 +-
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx-nwl.c | 1062
4 files changed, 1144 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
new file mode 100644
index 000..3b2a9ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -0,0 +1,68 @@
+* Xilinx NWL PCIe Root Port Bridge DT description
+
+Required properties:
+- compatible: Should contain "xlnx,nwl-pcie-2.11"
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- reg: Should contain Bridge, PCIe Controller registers location,
+ configuration sapce, and length
+- reg-names: Must include the following entries:
+ "breg": bridge registers
+ "pcireg": PCIe controller registers
+ "cfg": configuration space region
+- device_type: must be "pci"
+- interrupts: Should contain NWL PCIe interrupt
+- interrupt-names: Must include the following entries:
+ "msi1, msi0": interrupt asserted when msi is received
+ "intx": interrupt that is asserted when an legacy interrupt is received
+ "misc": interrupt asserted when miscellaneous is received
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+ mapping of the PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+- msi-controller: indicates that this is MSI controller node
+- msi-parent: MSI parent of the root complex itself
+- legacy-interrupt-controller: Interrupt controller device node for Legacy
interrupts
+ - interrupt-controller: identifies the node as an interrupt controller
+ - #interrupt-cells: should be set to 1
+ - #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+
+
+Example:
+
+
+nwl_pcie: pcie@fd0e {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "xlnx,nwl-pcie-2.11";
+ #interrupt-cells = <1>;
+ msi-controller;
+ device_type = "pci";
+ interrupt-parent = <&gic>;
+ interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
+ interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+
+ msi-parent = <&nwl_pcie>;
+ reg = <0x0 0xfd0e 0x1000>,
+ <0x0 0xfd48 0x1000>,
+ <0x0 0xe000 0x100>;
+ reg-names = "breg", "pcireg", "cfg";
+ ranges = <0x0200 0x 0xe100 0x 0xe100 0
0x0f00>;
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..39799cf 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -15,12 +15,22 @@ config PCI_MVEBU
depends on ARCH_MVEBU || ARCH_DOVE
depends on OF
+config PCIE_XILINX_NWL
+ bool "NWL PCIe Core"
+ depends on ARCH_ZYNQMP
+ select PCI_MSI_IRQ_DOMAIN if PCI_MSI
+ help
+Say 'Y' here if you want kernel to support for Xilinx
+NWL PCIe controller. The controller can act as Root Port
+or End Point. The current option selection will only
+support root port enabling.
+
config PCIE_DW
- bool
+bool
config PCI_EXYNOS
- bool "Samsung Exynos PCIe controller"
- depends on SOC_EXYNOS5440
+bool "Samsung Exynos PCIe controller"
+depends on SOC_EXYNOS5440
select PCIEPORTBUS
select PCIE_DW
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d
Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 11/16/2015 7:14 AM, Marc Zyngier wrote:
On 11/11/15 06:33, Bharat Kumar Gogada wrote:
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
---
Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc function.
Moved MSI functionality to separate functions.
Changed error return values.
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 68 ++
drivers/pci/host/Kconfig | 16 +-
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx-nwl.c | 1062
4 files changed, 1144 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
[...]
+static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
+{
+ struct platform_device *pdev = to_platform_device(pcie->dev);
+ struct nwl_msi *msi = &pcie->msi;
+ unsigned long base;
+ int ret;
+
+ mutex_init(&msi->lock);
+
+ /* Check for msii_present bit */
+ ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
+ if (!ret) {
+ dev_err(pcie->dev, "MSI not present\n");
+ ret = -EIO;
+ goto err;
+ }
+
+ /* Enable MSII */
+ nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
+ MSII_ENABLE, I_MSII_CONTROL);
+
+ /* Enable MSII status */
+ nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
+ MSII_STATUS_ENABLE, I_MSII_CONTROL);
+
+ /* setup AFI/FPCI range */
+ msi->pages = __get_free_pages(GFP_KERNEL, 0);
+ base = virt_to_phys((void *)msi->pages);
+ nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
+ nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
BTW, you still haven't answered my question as to why you need to waste
a page of memory here, and why putting a device address doesn't work.
As this is (to the best of my knowledge) the only driver doing so, I'd
really like you to explain the rational behind this.
Might not be the only driver doing so after I start sending out patches
for the iProc MSI support (soon), :)
I'm not sure how it works for the Xilinx NWL controller, which Bharat
should be able to help to explain. But for the iProc MSI controller,
there's no device I/O memory reserved for MSI posted writes in the ASIC.
Therefore one needs to reserve host memory for these writes.
Ray
Thanks,
M.
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Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for NS2
On 10/30/2015 11:49 AM, Brian Norris wrote: On Wed, Oct 28, 2015 at 09:08:02AM -0700, Ray Jui wrote: On 10/28/2015 2:06 AM, Anup Patel wrote: I think for a newly created OF devices the Linux device driver framework will match the platform drivers in the order in which they are registered by module init functions. Now the order of module init function calls will be based how the .initcall section is formed by linker and order in which objects are linked. Yes, what you said is my understanding as well, but then here is the mystery. This is the link order in brcmnand/Makefile: 1 # link order matters; don't link the more generic brcmstb_nand.o before the 2 # more specific iproc_nand.o, for instance 3 obj-$(CONFIG_MTD_NAND_BRCMNAND) += iproc_nand.o 4 obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm63138_nand.o 5 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o 6 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o Based on the order above, probe from iproc_nand should always be called first if a matching compatible string is found. If so, then why having both compatible strings "brcm,brcmnand" and "brcm,nand-iproc" causes issues for NS2 (I remember it broke smoketest in the past when you submitted the change)? I'm not saying we should have "brcm,brcmnand" for iProc devices, but I don't get why it would cause any issue. FWIW, the above hack doesn't do anything if these are built as modules, AFAICT. So I guess udev's (or similar) module rules would be another point of failure here? Not that any of us probably care too much about this driver as a module, but just throwing it out there... I have a feeling we'll have to solve this locally, by avoiding having "independent" drivers handling similar compatible properties, as I expect (despite our expectation that compatible ordering should matter) this problem will not be solved any time soon in the generic infrastructure. Or we can just use a hack (as Anup is doing) to leave off the "brcm,brcmnand" compatibility property. Unless someone has brilliant ideas, I guess we go with Anup's hack for now. I'm fine with that, :) Ray Brian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for NS2
On 10/28/2015 2:06 AM, Anup Patel wrote:
-Original Message-
From: Ray Jui [mailto:r...@broadcom.com]
Sent: 28 October 2015 06:17
To: Brian Norris
Cc: Anup Patel; David Woodhouse; Linux MTD; Rob Herring; Pawel Moll; Mark
Rutland; Catalin Marinas; Will Deacon; Sudeep Holla; Ian Campbell; Kumar Gala;
Scott Branden; Florian Fainelli; Pramod Kumar; Vikram Prakash; Sandeep
Tripathy; Linux ARM Kernel; Device Tree; Linux Kernel; bcm-kernel-feedback-list
Subject: Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for
NS2
On 10/27/2015 5:39 PM, Brian Norris wrote:
On Tue, Oct 27, 2015 at 05:25:32PM -0700, Ray Jui wrote:
On 10/27/2015 5:19 PM, Brian Norris wrote:
On Fri, Oct 23, 2015 at 10:46:13AM +0530, Anup Patel wrote:
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index f603277..9610822 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -212,5 +212,19 @@
compatible = "brcm,iproc-rng200";
reg = <0x6622 0x28>;
};
+
+ nand: nand@6646 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-
v6.1";
Technically, the binding says you should also have "brcm,brcmnand"
as a last resort. Otherwise (for the NAND parts):
I believe Anup was seeing issues when both "brcm,nand-iproc" and
"brcm,brcmnand" are present.
Note "brcm,nand-iproc" invokes 'iproc_nand_probe', which calls
'brcmnand_probe' in the end.
"brcm,brcmnand" invokes 'brcmstb_nand_probe', which also calls
'brcmstb_probe', but without all the prep configuration required for
"brcm,nand-iproc".
Ah, I forgot about that problem. That seems like an OF infrastructure
issue that could be fixed. We could lump these drivers back together,
and make sure that "brcm,nand-iproc" gets the priority in the
of_device_id list.
Or we could just relax the DT binding.
But wait, wouldn't cygnus already have that problem? You're using the
binding I suggested in arch/arm/boot/dts/bcm-cygnus.dtsi.
Interestingly, we do not see this problem with Cygnus or NSP, but only on NS2
(arm64 based). There may be a difference between how OF devices are
instantiated between arm and arm64?
Alternately, it could be also about order in-which platform drivers are matched
for newly created OF device.
Oh, and I see we hacked this one in drivers/mtd/nand/brcmnand/Makefile:
# link order matters; don't link the more generic brcmstb_nand.o before the
# more specific iproc_nand.o, for instance
Yes, I see that too (after sending out my previous email, :)). Maybe
Anup can help to elaborate on the problem. I'm now getting a bit
confused on how the problem can surface on NS2.
I think for a newly created OF devices the Linux device driver framework will
match the platform drivers in the order in which they are registered by module
init functions. Now the order of module init function calls will be based how
the .initcall section is formed by linker and order in which objects are linked.
Yes, what you said is my understanding as well, but then here is the
mystery. This is the link order in brcmnand/Makefile:
1 # link order matters; don't link the more generic brcmstb_nand.o
before the
2 # more specific iproc_nand.o, for instance
3 obj-$(CONFIG_MTD_NAND_BRCMNAND) += iproc_nand.o
4 obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm63138_nand.o
5 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o
6 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
Based on the order above, probe from iproc_nand should always be called
first if a matching compatible string is found. If so, then why having
both compatible strings "brcm,brcmnand" and "brcm,nand-iproc" causes
issues for NS2 (I remember it broke smoketest in the past when you
submitted the change)? I'm not saying we should have "brcm,brcmnand" for
iProc devices, but I don't get why it would cause any issue.
Does the order of the compatible string matter when they are assigned to
the same 'compatible' property like this?
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1","brcm,brcmnand";
IMHO, if multiple platform drivers match given OF device then platform driver
with longest matching compatible string should only be probed. I don't know
how big change this would be for OF framework.
But in general, I think it's a good idea to relax the requirement in the
DT binding document to not require "brcm,brcmnand", in the case when
"brcm,nand-iproc" and "brcm,nand-bcm63138" are present.
Even I think, it will be good to relax the DT bindings requirement for
BRCM NAND driver.
Regards,
Anup
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Re: [PATCH 07/11] pinctrl: use ngpios propety from DT
On 10/28/2015 4:52 AM, Pramod Kumar wrote: Hi Linus, -Original Message- From: Linus Walleij [mailto:linus.wall...@linaro.org] Sent: 27 October 2015 15:22 To: Pramod Kumar Cc: Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Ray Jui; Scott Branden; Russell King; linux-g...@vger.kernel.org; bcm-kernel-feedback- list; Jason Uy; Masahiro Yamada; Thomas Gleixner; Laurent Pinchart; devicetree@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- ker...@vger.kernel.org; Jonas Gorski Subject: Re: [PATCH 07/11] pinctrl: use ngpios propety from DT On Mon, Oct 19, 2015 at 7:43 AM, Pramod Kumar wrote: Since identical hardware is used in several instances and all pins are not routed to pinctrl hence getting total number of gpios from DT make more sense hence stop using total number of gpios pins from drivers and extract it from DT. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden This patch is wrong. Keep this per-compatible code, and only overrid the ngpios if and only if: - The ngpios is set in the DT node - The ngpios in the DT node is *smaller* than the hardware defined number of GPIOs. ngpios is for restricting the number of available lines due to routing etc, not to define what the hardware has, because the hardware most certainly have all the lines, it's just that you're not using all of them. Yours, Linus Walleij I discussed with ASIC team regarding this iProc GPIO block. They use a library to create the GPIOs block where "total number of GPIO pins( let say N) in GPIO block" is used as an parameter. Library uses a construct for *a* GPIO pin. This gets instantiated N times to create a complete GPIO block with N pins. Just to confirm, N can be *any number*, and when it exceeds 32, additional registers will be created by the library, correct? I think that's what I saw with Cygnus, where 3 instances of this GPIO controller was used, with two of them less supporting less than 32 GPIOs and one of them (ASIU) supporting 146 GPIOs, in which case, 5 register banks are used with 0x200 segment each. All iProc based SoCs uses this library. So I'm not sure whether attaching "total number of GPIOs pins" to compatible-string make sense in this case. The closest I can think of is to tie a very large number of N to the "brcm,iproc-gpio" compatible string for all new iProc SoCs, but even that, one can argue how large is *large* I personally feel that passing this number from the DT makes more sense here. Any iProc based future as well as current SoCs would be able to use this driver without any change. Please advise us in this case. Regards, Pramod -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for NS2
On 10/27/2015 5:39 PM, Brian Norris wrote:
On Tue, Oct 27, 2015 at 05:25:32PM -0700, Ray Jui wrote:
On 10/27/2015 5:19 PM, Brian Norris wrote:
On Fri, Oct 23, 2015 at 10:46:13AM +0530, Anup Patel wrote:
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index f603277..9610822 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -212,5 +212,19 @@
compatible = "brcm,iproc-rng200";
reg = <0x6622 0x28>;
};
+
+ nand: nand@6646 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
Technically, the binding says you should also have "brcm,brcmnand" as a
last resort. Otherwise (for the NAND parts):
I believe Anup was seeing issues when both "brcm,nand-iproc" and
"brcm,brcmnand" are present.
Note "brcm,nand-iproc" invokes 'iproc_nand_probe', which calls
'brcmnand_probe' in the end.
"brcm,brcmnand" invokes 'brcmstb_nand_probe', which also calls
'brcmstb_probe', but without all the prep configuration required for
"brcm,nand-iproc".
Ah, I forgot about that problem. That seems like an OF infrastructure
issue that could be fixed. We could lump these drivers back together,
and make sure that "brcm,nand-iproc" gets the priority in the
of_device_id list.
Or we could just relax the DT binding.
But wait, wouldn't cygnus already have that problem? You're using the
binding I suggested in arch/arm/boot/dts/bcm-cygnus.dtsi.
Interestingly, we do not see this problem with Cygnus or NSP, but only
on NS2 (arm64 based). There may be a difference between how OF devices
are instantiated between arm and arm64?
Oh, and I see we hacked this one in drivers/mtd/nand/brcmnand/Makefile:
# link order matters; don't link the more generic brcmstb_nand.o before the
# more specific iproc_nand.o, for instance
Yes, I see that too (after sending out my previous email, :)). Maybe
Anup can help to elaborate on the problem. I'm now getting a bit
confused on how the problem can surface on NS2.
But in general, I think it's a good idea to relax the requirement in the
DT binding document to not require "brcm,brcmnand", in the case when
"brcm,nand-iproc" and "brcm,nand-bcm63138" are present.
Brian
Thanks,
Ray
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Re: [PATCH v3 2/2] arm64: dts: Add BRCM IPROC NAND DT node for NS2
On 10/27/2015 5:19 PM, Brian Norris wrote:
On Fri, Oct 23, 2015 at 10:46:13AM +0530, Anup Patel wrote:
The NAND controller on NS2 SoC is compatible with existing
BRCM IPROC NAND driver so let's enable it in NS2 DT and
NS2 SVK DT.
This patch also fixes use of node labels in ns2-svk.dts.
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 30 --
arch/arm64/boot/dts/broadcom/ns2.dtsi| 14 ++
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index e5950d5..6bb3d4d 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -50,18 +50,28 @@
device_type = "memory";
reg = <0x0 0x8000 0x 0x4000>;
};
+};
- soc: soc {
- i2c0: i2c@6608 {
- status = "ok";
- };
+&i2c0 {
+ status = "ok";
+};
- i2c1: i2c@660b {
- status = "ok";
- };
+&i2c1 {
+ status = "ok";
+};
+
+&uart3 {
+ status = "ok";
+};
- uart3: serial@6613 {
- status = "ok";
- };
+&nand {
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index f603277..9610822 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -212,5 +212,19 @@
compatible = "brcm,iproc-rng200";
reg = <0x6622 0x28>;
};
+
+ nand: nand@6646 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
Technically, the binding says you should also have "brcm,brcmnand" as a
last resort. Otherwise (for the NAND parts):
I believe Anup was seeing issues when both "brcm,nand-iproc" and
"brcm,brcmnand" are present.
Note "brcm,nand-iproc" invokes 'iproc_nand_probe', which calls
'brcmnand_probe' in the end.
"brcm,brcmnand" invokes 'brcmstb_nand_probe', which also calls
'brcmstb_probe', but without all the prep configuration required for
"brcm,nand-iproc".
Reviewed-by: Brian Norris
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Re: [PATCH v2 0/3] clk: Broadcom BCM63138 support
On 10/26/2015 8:53 PM, Florian Fainelli wrote:
Hi all,
This patch series adds support for the Broadcom BCM63138 DSL SoCs
clocking framework.
Since the HW is identical to the one found in Broadcom iProc SoCs, but the
integration is different (obviously), there is still a new compatible string
introduced just in case we happen to find issues in the future.
This applies on top of clk/next as of
679c51cffc3b316bd89ecc91ef92603dd6d4fc68 ("clk: Add stubs for of_clk_*() APIs when
CONFIG_OF=n")
Since there is an obvious dependency between patch 2 and 3, we can either
merge this through the Clock tree or via a future arm-soc pull requests
for Broadcom SoCs.
Florian Fainelli (3):
clk: iproc: Extend binding to cover BCM63138
clk: bcm: Add BCM63138 clock support
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
.../bindings/clock/brcm,iproc-clocks.txt | 5 +++
arch/arm/boot/dts/bcm63138.dtsi| 39 --
drivers/clk/bcm/Kconfig| 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22
5 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
The entire patch set looks good to me.
Reviewed-by: Ray Jui
Thanks,
Ray
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Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node
Hi Pramod, On 10/26/2015 11:06 AM, Pramod Kumar wrote: Hi Ray, -Original Message- From: Ray Jui [mailto:r...@broadcom.com] Sent: 26 October 2015 22:43 To: Pramod Kumar; Laurent Pinchart; Rob Herring Cc: Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Scott Branden; Russell King; Linus Walleij; linux-g...@vger.kernel.org; bcm-kernel-feedback-list; Jason Uy; Masahiro Yamada; Thomas Gleixner; devicetree@vger.kernel.org; linux- arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org; Jonas Gorski Subject: Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node Hi Pramod, On 10/26/2015 10:08 AM, Pramod Kumar wrote: -Original Message- From: Ray Jui [mailto:r...@broadcom.com] Sent: 23 October 2015 21:38 To: Laurent Pinchart; Rob Herring Cc: Pramod Kumar; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Scott Branden; Russell King; Linus Walleij; linux-g...@vger.kernel.org; bcm-kernel- feedback-list; Jason Uy; Masahiro Yamada; Thomas Gleixner; devicetree@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- ker...@vger.kernel.org; Jonas Gorski Subject: Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node On 10/23/2015 6:02 AM, Laurent Pinchart wrote: Hi Rob, On Friday 23 October 2015 06:51:28 Rob Herring wrote: On Fri, Oct 23, 2015 at 4:08 AM, Laurent Pinchart wrote: On Thursday 22 October 2015 18:41:05 Rob Herring wrote: On Thu, Oct 22, 2015 at 1:52 PM, Ray Jui wrote: On 10/22/2015 11:43 AM, Rob Herring wrote: On Mon, Oct 19, 2015 at 12:43 AM, Pramod Kumar wrote: Add ngpios property to the gpio controller's DT node so that controller driver extracts total number of gpio lines present in controller from DT and removes dependency on driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt | 5 +++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.t xt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.t xt index f92b833..655a8d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.t xt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gp +++ io +++ .txt @@ -10,6 +10,9 @@ Required properties: Define the base and range of the I/O address space that contains the Cygnus GPIO/PINCONF controller registers +- ngpios: +Total number of GPIOs the controller provides This must be optional for compatibility and the driver needs to handle it not present. You meant to be compatible with existing Cygnus devices, correct? Just to clarify, here you suggest we still leave the existing hard coded ngpios in the driver, in order to be compatible with all existing Cygnus devices (while the Cygnus device tree changes to use ngpio is still being merged and through different maintainer), and have all new iProc SoCs switch to use ngpios from device tree, right? Yes, an existing dtb should continue to work with a new kernel. You can add the DT property to the older devices too and then eventually remove the hard coded values some time in the future. That could be immediately (don't care about compatibility at all), a couple of kernel cycles, never... It all depends on users of the impacted platforms. But shouldn't the property still be documented as required to ensure that new DTs always include it ? Good point. If the intent is to eventually remove it from the driver, then yes. We probably need "required for new designs" as a category or maybe "recommended"? The wording is not so important here, but I'm thinking about as we try to standardize the naming. Required for new designs sounds better than recommended. Or maybe something like "Required (optional for backward compatibility)". Yes, it should be phrased as "required for new designs" because all new iProc SoCs using this GPIO driver need to have this in DT. Thanks, Ray Thanks for providing feedback. I'll make sure to use this property under phrase " required for new designs " in next patch set. Regards, Pramod To confirm, is your plan: 1) Continue to support hardcoded ngpios in the driver for the current SoC Cygnus 2) Proceed with Cygnus DTS changes to switch to DT based ngpios configuration 3) Modify the document to make DT ngpios a required property for all new SoCs including NSP, NS2, and etc. ? Thanks, Ray Ok. This patch-set is to make this driver more generic so that all future SoCs , as you mentioned like NS2, NSP, Stingray, could use it. Since This Cygnus is in very very early stage and No customer is using it so we can afford it to address ngpio from DT and remove Cygnus hard coded values immediately from this patch. Otherwise we will see the same issue with "gpios-ranges" property and this will be highly inter-dependent as well
Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node
Hi Pramod, On 10/26/2015 10:08 AM, Pramod Kumar wrote: -Original Message- From: Ray Jui [mailto:r...@broadcom.com] Sent: 23 October 2015 21:38 To: Laurent Pinchart; Rob Herring Cc: Pramod Kumar; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Scott Branden; Russell King; Linus Walleij; linux-g...@vger.kernel.org; bcm-kernel- feedback-list; Jason Uy; Masahiro Yamada; Thomas Gleixner; devicetree@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- ker...@vger.kernel.org; Jonas Gorski Subject: Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node On 10/23/2015 6:02 AM, Laurent Pinchart wrote: Hi Rob, On Friday 23 October 2015 06:51:28 Rob Herring wrote: On Fri, Oct 23, 2015 at 4:08 AM, Laurent Pinchart wrote: On Thursday 22 October 2015 18:41:05 Rob Herring wrote: On Thu, Oct 22, 2015 at 1:52 PM, Ray Jui wrote: On 10/22/2015 11:43 AM, Rob Herring wrote: On Mon, Oct 19, 2015 at 12:43 AM, Pramod Kumar wrote: Add ngpios property to the gpio controller's DT node so that controller driver extracts total number of gpio lines present in controller from DT and removes dependency on driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt | 5 +++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index f92b833..655a8d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio +++ .txt @@ -10,6 +10,9 @@ Required properties: Define the base and range of the I/O address space that contains the Cygnus GPIO/PINCONF controller registers +- ngpios: +Total number of GPIOs the controller provides This must be optional for compatibility and the driver needs to handle it not present. You meant to be compatible with existing Cygnus devices, correct? Just to clarify, here you suggest we still leave the existing hard coded ngpios in the driver, in order to be compatible with all existing Cygnus devices (while the Cygnus device tree changes to use ngpio is still being merged and through different maintainer), and have all new iProc SoCs switch to use ngpios from device tree, right? Yes, an existing dtb should continue to work with a new kernel. You can add the DT property to the older devices too and then eventually remove the hard coded values some time in the future. That could be immediately (don't care about compatibility at all), a couple of kernel cycles, never... It all depends on users of the impacted platforms. But shouldn't the property still be documented as required to ensure that new DTs always include it ? Good point. If the intent is to eventually remove it from the driver, then yes. We probably need "required for new designs" as a category or maybe "recommended"? The wording is not so important here, but I'm thinking about as we try to standardize the naming. Required for new designs sounds better than recommended. Or maybe something like "Required (optional for backward compatibility)". Yes, it should be phrased as "required for new designs" because all new iProc SoCs using this GPIO driver need to have this in DT. Thanks, Ray Thanks for providing feedback. I'll make sure to use this property under phrase " required for new designs " in next patch set. Regards, Pramod To confirm, is your plan: 1) Continue to support hardcoded ngpios in the driver for the current SoC Cygnus 2) Proceed with Cygnus DTS changes to switch to DT based ngpios configuration 3) Modify the document to make DT ngpios a required property for all new SoCs including NSP, NS2, and etc. ? Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] clk: Broadcom BCM63138 support
Hi Florian,
On 10/23/2015 10:30 AM, Florian Fainelli wrote:
Hi all,
This patch series adds support for the Broadcom BCM63138 DSL SoCs
clocking framework.
Since the HW is identical to the one found in Broadcom iProc SoCs, but the
integration is different (obviously), there is still a new compatible string
introduced just in case we happen to find issues in the future.
This applies on top of clk/next as of
f63d19ef52aa66e97fca2425974845177ce02b0a ("Merge branch 'clk-iproc' into
clk-next")
Since there is an obvious dependency between patch 2 and 3, we can either
merge this through the Clock tree or via a future arm-soc pull requests
for Broadcom SoCs.
Thanks!
Florian Fainelli (3):
clk: iproc: Extend binding to cover BCM63138
clk: bcm: Add BCM63138 clock support
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
.../bindings/clock/brcm,iproc-clocks.txt | 5 +++
arch/arm/boot/dts/bcm63138.dtsi| 39 --
drivers/clk/bcm/Kconfig| 10 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 22
5 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
The entire patch set looks good to me (- Scott's comment of adding
COMPILE_TEST to increase build test coverage).
Thanks,
Ray
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Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node
On 10/23/2015 6:02 AM, Laurent Pinchart wrote: Hi Rob, On Friday 23 October 2015 06:51:28 Rob Herring wrote: On Fri, Oct 23, 2015 at 4:08 AM, Laurent Pinchart wrote: On Thursday 22 October 2015 18:41:05 Rob Herring wrote: On Thu, Oct 22, 2015 at 1:52 PM, Ray Jui wrote: On 10/22/2015 11:43 AM, Rob Herring wrote: On Mon, Oct 19, 2015 at 12:43 AM, Pramod Kumar wrote: Add ngpios property to the gpio controller's DT node so that controller driver extracts total number of gpio lines present in controller from DT and removes dependency on driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt | 5 +++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index f92b833..655a8d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -10,6 +10,9 @@ Required properties: Define the base and range of the I/O address space that contains the Cygnus GPIO/PINCONF controller registers +- ngpios: +Total number of GPIOs the controller provides This must be optional for compatibility and the driver needs to handle it not present. You meant to be compatible with existing Cygnus devices, correct? Just to clarify, here you suggest we still leave the existing hard coded ngpios in the driver, in order to be compatible with all existing Cygnus devices (while the Cygnus device tree changes to use ngpio is still being merged and through different maintainer), and have all new iProc SoCs switch to use ngpios from device tree, right? Yes, an existing dtb should continue to work with a new kernel. You can add the DT property to the older devices too and then eventually remove the hard coded values some time in the future. That could be immediately (don't care about compatibility at all), a couple of kernel cycles, never... It all depends on users of the impacted platforms. But shouldn't the property still be documented as required to ensure that new DTs always include it ? Good point. If the intent is to eventually remove it from the driver, then yes. We probably need "required for new designs" as a category or maybe "recommended"? The wording is not so important here, but I'm thinking about as we try to standardize the naming. Required for new designs sounds better than recommended. Or maybe something like "Required (optional for backward compatibility)". Yes, it should be phrased as "required for new designs" because all new iProc SoCs using this GPIO driver need to have this in DT. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/11] dt-binding: Add ngpios property to GPIO controller node
On 10/22/2015 11:43 AM, Rob Herring wrote: On Mon, Oct 19, 2015 at 12:43 AM, Pramod Kumar wrote: Add ngpios property to the gpio controller's DT node so that controller driver extracts total number of gpio lines present in controller from DT and removes dependency on driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index f92b833..655a8d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -10,6 +10,9 @@ Required properties: Define the base and range of the I/O address space that contains the Cygnus GPIO/PINCONF controller registers +- ngpios: +Total number of GPIOs the controller provides This must be optional for compatibility and the driver needs to handle it not present. You meant to be compatible with existing Cygnus devices, correct? Just to clarify, here you suggest we still leave the existing hard coded ngpios in the driver, in order to be compatible with all existing Cygnus devices (while the Cygnus device tree changes to use ngpio is still being merged and through different maintainer), and have all new iProc SoCs switch to use ngpios from device tree, right? Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/4] mtd: nand: Allow MTD_NAND_BRCMNAND to be selected for ARM64
This patch is the same. I thought it has already been merged by Brian? On 10/16/2015 2:08 AM, Anup Patel wrote: > The BRCM NAND driver can be re-used for Broadcom ARM64 SoCs hence > this patch updates Kconfig to allow selection of MTD_NAND_BRCMNAND > for ARM64. > > Signed-off-by: Anup Patel > Reviewed-by: Vikram Prakash > Reviewed-by: Ray Jui > Reviewed-by: Pramod KUMAR > Reviewed-by: Scott Branden > --- > drivers/mtd/nand/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 3324281..a1b5819 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -393,7 +393,7 @@ config MTD_NAND_GPMI_NAND > > config MTD_NAND_BRCMNAND > tristate "Broadcom STB NAND controller" > - depends on ARM || MIPS > + depends on ARM || ARM64 || MIPS > help > Enables the Broadcom NAND controller driver. The controller was > originally designed for Set-Top Box but is used on various BCM7xxx, > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/4] mtd: brcmnand: Fix pointer type-cast in brcmnand_write()
Correct me if I remember it wrong, but I thought this patch has already
been merged by Brian?
Thanks,
Ray
On 10/16/2015 2:08 AM, Anup Patel wrote:
> We should always type-cast pointer to "long" or "unsigned long"
> because size of pointer is same as machine word size. This will
> avoid pointer type-cast issues on both 32bit and 64bit systems.
>
> This patch fixes pointer type-cast issue in brcmnand_write()
> as-per above info.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Vikram Prakash
> Reviewed-by: Ray Jui
> Reviewed-by: Scott Branden
> ---
> drivers/mtd/nand/brcmnand/brcmnand.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
> b/drivers/mtd/nand/brcmnand/brcmnand.c
> index fddb795..4cba03d 100644
> --- a/drivers/mtd/nand/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
> @@ -1544,9 +1544,9 @@ static int brcmnand_write(struct mtd_info *mtd, struct
> nand_chip *chip,
>
> dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
>
> - if (unlikely((u32)buf & 0x03)) {
> + if (unlikely((unsigned long)buf & 0x03)) {
> dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
> - buf = (u32 *)((u32)buf & ~0x03);
> + buf = (u32 *)((unsigned long)buf & ~0x03);
> }
>
> brcmnand_wp(mtd, 0);
>
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Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On 10/15/2015 2:10 PM, Jon Mason wrote: > On Thu, Oct 15, 2015 at 02:04:09PM -0700, Scott Branden wrote: >> Hi Ray, >> >> Comment at near end. >> >> On 15-10-15 01:55 PM, Ray Jui wrote: >>> >>> >>> On 10/15/2015 1:40 PM, Scott Branden wrote: >>>> We need some sort of kconfig option to differentiate NS2 clock driver >>> >from being pulled in all the time. >>>> >>>> On 15-10-15 12:48 PM, Jon Mason wrote: >>>>> The Broadcom Northstar 2 SoC is architected under the iProc >>>>> architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, >>>>> LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. >>>>> >>>>> Signed-off-by: Jon Mason >>>>> --- >>>>> drivers/clk/Makefile| 2 +- >>>>> drivers/clk/bcm/Makefile| 1 + >>>>> drivers/clk/bcm/clk-ns2.c | 288 >>>>> >>>>> include/dt-bindings/clock/bcm-ns2.h | 72 + >>>>> 4 files changed, 362 insertions(+), 1 deletion(-) >>>>> create mode 100644 drivers/clk/bcm/clk-ns2.c >>>>> create mode 100644 include/dt-bindings/clock/bcm-ns2.h >>>>> >>>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile >>>>> index d08b3e5..6124bd3 100644 >>>>> --- a/drivers/clk/Makefile >>>>> +++ b/drivers/clk/Makefile >>>>> @@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)+= clk-wm831x.o >>>>> obj-$(CONFIG_COMMON_CLK_XGENE)+= clk-xgene.o >>>>> obj-$(CONFIG_COMMON_CLK_PWM)+= clk-pwm.o >>>>> obj-$(CONFIG_COMMON_CLK_AT91)+= at91/ >>>>> -obj-$(CONFIG_ARCH_BCM)+= bcm/ >>>>> +obj-y+= bcm/ >>>>> obj-$(CONFIG_ARCH_BERLIN)+= berlin/ >>>>> obj-$(CONFIG_ARCH_HISI)+= hisilicon/ >>>>> obj-$(CONFIG_ARCH_MXC)+= imx/ >>>>> diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile >>>>> index e258b28..2d1cbc5 100644 >>>>> --- a/drivers/clk/bcm/Makefile >>>>> +++ b/drivers/clk/bcm/Makefile >>>>> @@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA)+= clk-kona-setup.o >>>>> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm281xx.o >>>>> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm21664.o >>>>> obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-iproc-armpll.o >>>>> clk-iproc-pll.o clk-iproc-asiu.o >>>>> +obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-ns2.o >>>> >>>> NS2 code is dragged in for all IPROC SoCs. We need a config option for >>>> NS2 (CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 >>>> processors... ?). >>>> >>>> You can see below ARMv7 processors don't have this problem. >>>> >>> >>> The arm64 maintainers (Catalin, Mark, and etc.) stated they only want >>> one ARCH options per chip family. >>> >>>> If not we need to add CONFIG_CLK_NS2. >>> >>> If using CONFIG_CLK_NS2, how is it going to be enabled/selected? >> >> Since CONFIG_ARCH_BCM_NS2 isn't "allowed" to be introduced we will >> need to create and select a CONFIG_CLK_BCM_NS2 in the defconfig >> instead. > > Is this better than the binary becoming slightly bigger? I thought > the extra complexity was worse than having an unused chunk of clk code > (and Kona is already doing the same thing above). I believe Ray was > in agreement with me during the internal review of this code. > > Thanks, > Jon > Yes, I'm okay with leaving it as it is. I even prefer changing the current Makefile to make all iProc based core clock drivers and SoC specific clock tables under CONFIG_COMMON_CLK_IPROC, which is what some of the other vendors do. >>> >>> Ray >>> >> >> Regards, >> Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On 10/15/2015 1:40 PM, Scott Branden wrote: > We need some sort of kconfig option to differentiate NS2 clock driver > from being pulled in all the time. > > On 15-10-15 12:48 PM, Jon Mason wrote: >> The Broadcom Northstar 2 SoC is architected under the iProc >> architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, >> LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. >> >> Signed-off-by: Jon Mason >> --- >> drivers/clk/Makefile| 2 +- >> drivers/clk/bcm/Makefile| 1 + >> drivers/clk/bcm/clk-ns2.c | 288 >> >> include/dt-bindings/clock/bcm-ns2.h | 72 + >> 4 files changed, 362 insertions(+), 1 deletion(-) >> create mode 100644 drivers/clk/bcm/clk-ns2.c >> create mode 100644 include/dt-bindings/clock/bcm-ns2.h >> >> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile >> index d08b3e5..6124bd3 100644 >> --- a/drivers/clk/Makefile >> +++ b/drivers/clk/Makefile >> @@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)+= clk-wm831x.o >> obj-$(CONFIG_COMMON_CLK_XGENE)+= clk-xgene.o >> obj-$(CONFIG_COMMON_CLK_PWM)+= clk-pwm.o >> obj-$(CONFIG_COMMON_CLK_AT91)+= at91/ >> -obj-$(CONFIG_ARCH_BCM)+= bcm/ >> +obj-y+= bcm/ >> obj-$(CONFIG_ARCH_BERLIN)+= berlin/ >> obj-$(CONFIG_ARCH_HISI)+= hisilicon/ >> obj-$(CONFIG_ARCH_MXC)+= imx/ >> diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile >> index e258b28..2d1cbc5 100644 >> --- a/drivers/clk/bcm/Makefile >> +++ b/drivers/clk/bcm/Makefile >> @@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA)+= clk-kona-setup.o >> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm281xx.o >> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm21664.o >> obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-iproc-armpll.o >> clk-iproc-pll.o clk-iproc-asiu.o >> +obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-ns2.o > > NS2 code is dragged in for all IPROC SoCs. We need a config option for > NS2 (CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 > processors... ?). > > You can see below ARMv7 processors don't have this problem. > The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family. > If not we need to add CONFIG_CLK_NS2. If using CONFIG_CLK_NS2, how is it going to be enabled/selected? Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding
On 10/14/2015 8:44 AM, Jon Mason wrote: > On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote: >> Same as this patch. I thought device tree binding document should go >> with the clock driver changes. >> >> Strictly speaking, device tree binding document should always go before >> the driver changes. In the binding document the DT interface is defined, >> then changes are implemented in the driver. > > I split them off this way due to the clk maintainer not wanting to > pull in any device tree changes. Since the documentation is for the > device tree enties, it makes logical sense to me that they be in the > same device tree series. If Stephen will pull these in with the clk > changes, I am more than happy to have it done by him :) > > Thanks, > Jon Yeah the clock maintainers do not pull in device tree changes like *.dtsi and *.dts. But they do take changes including the binding documents and clock driver changes. You can confirm with Stephen. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On 10/13/2015 2:38 PM, Jon Mason wrote:
> On Sat, Oct 10, 2015 at 04:39:00PM +0200, Hauke Mehrtens wrote:
>> On 10/03/2015 12:22 AM, Jon Mason wrote:
>>> Add device tree files for Broadcom Northstar based SVKs. Since the
>>> bcm5301x.dtsi already exists, all that is necessary is the dts files to
>>> enable the UARTs (and specify the RAM size for the 4708/9). With these
>>> files, the SVKs are able to boot to shell.
>>>
>>> Signed-off-by: Jon Mason
>>> ---
>>> arch/arm/boot/dts/Makefile | 5 +++-
>>> arch/arm/boot/dts/bcm94708.dts | 52 +++
>>> arch/arm/boot/dts/bcm94709.dts | 52 +++
>>> arch/arm/boot/dts/bcm953012k.dts | 59
>>>
>>> 4 files changed, 167 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm/boot/dts/bcm94708.dts
>>> create mode 100644 arch/arm/boot/dts/bcm94709.dts
>>> create mode 100644 arch/arm/boot/dts/bcm953012k.dts
>>>
>>> +&uart0 {
>>> + clock-frequency = <62499840>;
>>
>> Just out of curiosity on what does this clock frequency depend? I saw
>> your patch adding a real clock driver which should make this obsolete.
>
> Better to add this now, as the device tree part might be out of sync
> for a time.
Sure, this can potentially be a reason to not using the real clock node
and just use a hardcoded clock frequency for now, until the other clock
change is merged, then you can submit another patch to use it.
Also, is it not better to make the UARTs a static clock
> and not dependent on the clk driver?
>
I disagree. You should always use the real clock driver for querying the
clock frequency, in the case when the clock driver is available.
Today one can change the core clock for UART in the bootloader for
various reasons (and we saw that happening a lot in the past), which in
this case will make your kernel not seeing any console output.
By always querying the clock rate based on real registers instead of a
hardcoded value, you don't have that issue and your kernel is less
dependent on any changes in the bootloader.
> Thanks,
> Jon
>
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Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding
Same as this patch. I thought device tree binding document should go with the clock driver changes. Strictly speaking, device tree binding document should always go before the driver changes. In the binding document the DT interface is defined, then changes are implemented in the driver. Ray On 10/13/2015 2:22 PM, Jon Mason wrote: > Document the device tree bindings for Broadcom Northstar 2 architecture > based clock controller > > Signed-off-by: Jon Mason > --- > .../bindings/clock/brcm,iproc-clocks.txt | 48 > ++ > 1 file changed, 48 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > index b3c3e9d..ede65a5 100644 > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > @@ -160,3 +160,51 @@ Northstar Plus. These clock IDs are defined in: > pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK > sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK > ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK > + > +Northstar 2 > +--- > +PLL and leaf clock compatible strings for Northstar 2 are: > +"brcm,ns2-genpll-scr" > +"brcm,ns2-genpll-sw" > +"brcm,ns2-lcpll-ddr" > +"brcm,ns2-lcpll-ports" > + > +The following table defines the set of PLL/clock index and ID for Northstar > 2. > +These clock IDs are defined in: > +"include/dt-bindings/clock/bcm-ns2.h" > + > +ClockSource Index ID > +--- - - - > +crystal N/A N/A N/A > + > +genpll_scr crystal 0 BCM_NS2_GENPLL_SCR > +scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK > +fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK > +audio_refgenpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK > +ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED > +ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED > +ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED > + > +genpll_swcrystal 0 BCM_NS2_GENPLL_SW > +rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK > +250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK > +nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK > +chimpgenpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK > +port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK > +sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK > + > +lcpll_ddrcrystal 0 BCM_NS2_LCPLL_DDR > +pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK > +ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK > +ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED > +ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED > +ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED > +ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED > + > +lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS > +wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK > +rgmiilcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK > +ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED > +ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED > +ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED > +ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding
Shouldn't the device tree binding document go with the other patch series since both the binding document and drivers are merged by Michael or Stephen? On 10/13/2015 2:22 PM, Jon Mason wrote: > Document the device tree bindings for Broadcom Northstar Plus > architecture based clock controller > > Signed-off-by: Jon Mason > --- > .../bindings/clock/brcm,iproc-clocks.txt | 30 > ++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > index da8d9bb..b3c3e9d 100644 > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > @@ -130,3 +130,33 @@ These clock IDs are defined in: > ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED > ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED > ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED > + > +Northstar and Northstar Plus > +-- > +PLL and leaf clock compatible strings for Northstar and Northstar Plus are: > + "brcm,nsp-armpll" > + "brcm,nsp-genpll" > + "brcm,nsp-lcpll0" So the current clock driver also supports NS? That will be nice and that indicates all the clock related registers/offsets are exactly the same between NS and NSP? > + > +The following table defines the set of PLL/clock index and ID for Northstar > and > +Northstar Plus. These clock IDs are defined in: > +"include/dt-bindings/clock/bcm-nsp.h" > + > +ClockSource Index ID > +--- - - - > +crystal N/A N/A N/A > + > +armpll crystal N/A N/A > + > +genpll crystal 0 BCM_NSP_GENPLL > +phy genpll 1 BCM_NSP_GENPLL_PHY_CLK > +ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK > +usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK > +iprocfastgenpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK > +sata1genpll 5 BCM_NSP_GENPLL_SATA1_CLK > +sata2genpll 6 BCM_NSP_GENPLL_SATA2_CLK > + > +lcpll0 crystal 0 BCM_NSP_LCPLL0 > +pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK > +sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK > +ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 10/2/2015 3:36 PM, Arnd Bergmann wrote:
> On Thursday 01 October 2015 17:44:36 Ray Jui wrote:
>>
>> Sorry for stealing this discussion, :)
>>
>> I have some questions here, since this affects how I should implement
>> the MSI support for iProc based PCIe controller. I understand it makes
>> more sense to use separate device node for MSI and have "msi-parent"
>> from the pci node points to the MSI node, and that MSI node can be
>> gicv2m or gicv3 based on more advanced ARMv8 platforms.
>>
>> Then I would assume the MSI controller would deserve its own driver?
>> Which is a lot of people do nowadays. In that case, how I should handle
>> the case when the iProc MSI support is handled through some event queue
>> mechanism with their registers embedded in the PCIe controller register
>> space?
>>
>> Does the following logic make sense to you?
>>
>> 1. parse phandle of "msi-parent"
>> 2. Call of_pci_find_msi_chip_by_node to hook it up to msi chip already
>> registered (in the gicv2m and gicv3 case)
>> 3. If failed, fall back to use the iProc's own event queue logic by
>> calling iproc_pcie_msi_init.
>>
>> The iProc MSI still has its own node that looks like this:
>> 141 msi0: msi@2002 {
>> 142 msi-controller;
>> 143 interrupt-parent = <&gic>;
>> 144 interrupts = ,
>> 145 ,
>> 146 ,
>> 147 ,
>> 148 ,
>> 149 ;
>> 150 brcm,num-eq-region = <1>;
>> 151 brcm,num-msi-msg-region = <1>;
>> 152 };
>>
>> But it does not have its own "reg" since they are embedded in the PCI
>> controller's registers and it relies on one calling iproc_pcie_msi_init
>> to pass in base register value and some other information.
>
> I don't think I have a perfect answer to this. One way would be to
> separate the actual PCI root device node from the IP block that
> contains both the PCI root and the MSI catcher, but I guess that
> would require an incompatible change to your binding and it's not
> worth the pain.
Indeed, that's going to be very painful given that this iProc PCIe
controller driver is used on multiple platforms including Northstar,
Cygnus, Northstar+, and Northstar 2.
>
> It's probably also ok to make the PCI host node itself be the msi-controller
> node and have an msi-parent phandle that points to the node itself. Not
> sure if that violates any rules that we may want or need to follow though.
>
> Having a device node without registers is also a bit problematic,
> especially the 'msi@2002' name doesn't make sense if 0x2002
> is not the first number in the reg property. Maybe it's best to
> put that node directly under the PCI host controller and not assign
> any registers. This is still a bit ugly because we'd expect devices
> under the host bridge to be PCI devices rather than random other things,
> but it may be the least of the evils.
This is what I have right now. With the msi node under the PCIe
controller node and have msi-parent points to the msi node. Maybe it
will be a lot easier to discuss this when I submit the code for review
within the next couple weeks.
>
> Arnd
>
Thanks,
Ray
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Re: [PATCH v2] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Hi Arnd,
On 10/1/2015 2:52 AM, Arnd Bergmann wrote:
> On Thursday 01 October 2015 14:29:21 Bharat Kumar Gogada wrote:
>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>
>> Signed-off-by: Bharat Kumar Gogada
>> Signed-off-by: Ravi Kiran Gummaluri
>> ---
>> Removed unneccessary comments
>> Modified setup_sspl implementation
>> Added more details in binding Documentation
>> ---
>> .../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 49 +
>> drivers/pci/host/Kconfig |9 +
>> drivers/pci/host/Makefile |1 +
>> drivers/pci/host/pcie-xilinx-nwl.c | 1029
>>
>> 4 files changed, 1088 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>> create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
>>
>> diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>> b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>> new file mode 100644
>> index 000..ed87184
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>> @@ -0,0 +1,49 @@
>> +* Xilinx NWL PCIe Root Port Bridge DT description
>> +
>> +Required properties:
>> +- compatible: Should contain "xlnx,nwl-pcie-2.11"
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to <2>
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> +interrupt source. The value must be 1.
>> +- reg: Should contain Bridge, PCIe Controller registers location,
>> +configuration sapce, and length
>> +- reg-names: Must include the following entries:
>> +"breg": bridge registers
>> +"pcireg": PCIe controller registers
>> +"cfg": configuration space region
>> +- device_type: must be "pci"
>> +- interrupts: Should contain NWL PCIe interrupt
>> +- interrupt-names: Must include the following entries:
>> +"misc": interrupt asserted when miscellaneous is recieved
>> +"intx": interrupt that is asserted when an legacy interrupt is received
>> +"msi_1, msi_0": interrupt asserted when msi is recieved
>
> The msi and intx interrupts don't really belong here: For intx, please
> use an interrupt-map property as the other host drivers do.
>
> For MSI, the usual answer is that there should be a separate device node
> for the MSI controller, and an msi-parent property in the PCI host.
>
> This lets you use the same code for hosts that have a GICv2m or GICv3
> that comes with its own MSI controller.
>
Sorry for stealing this discussion, :)
I have some questions here, since this affects how I should implement
the MSI support for iProc based PCIe controller. I understand it makes
more sense to use separate device node for MSI and have "msi-parent"
from the pci node points to the MSI node, and that MSI node can be
gicv2m or gicv3 based on more advanced ARMv8 platforms.
Then I would assume the MSI controller would deserve its own driver?
Which is a lot of people do nowadays. In that case, how I should handle
the case when the iProc MSI support is handled through some event queue
mechanism with their registers embedded in the PCIe controller register
space?
Does the following logic make sense to you?
1. parse phandle of "msi-parent"
2. Call of_pci_find_msi_chip_by_node to hook it up to msi chip already
registered (in the gicv2m and gicv3 case)
3. If failed, fall back to use the iProc's own event queue logic by
calling iproc_pcie_msi_init.
The iProc MSI still has its own node that looks like this:
141 msi0: msi@2002 {
142 msi-controller;
143 interrupt-parent = <&gic>;
144 interrupts = ,
145 ,
146 ,
147 ,
148 ,
149 ;
150 brcm,num-eq-region = <1>;
151 brcm,num-msi-msg-region = <1>;
152 };
But it does not have its own "reg" since they are embedded in the PCI
controller's registers and it relies on one calling iproc_pcie_msi_init
to pass in base register value and some other information.
Thanks,
Ray
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Re: [PATCH v2 1/9] ARM: dts: consolidate aliases for Cygnus dt files
On 9/23/2015 2:48 PM, Florian Fainelli wrote: > On 23/09/15 14:46, Ray Jui wrote: >> >> >> On 9/23/2015 2:31 PM, Arnd Bergmann wrote: >>> On Friday 18 September 2015 14:44:54 Ray Jui wrote: >>>> On 9/18/2015 2:27 PM, Arnd Bergmann wrote: >>>>> On Friday 18 September 2015 14:24:06 Ray Jui wrote: >>>>> >>>>> The SoC has at least four uarts according to this, so it seems unlikely >>>>> that >>>>> each board really only uses only the fourth one of them and labels it '0' >>>>> on the board. As soon as you get one board that has more than one uart >>>>> wired >>>>> up, you would need to undo this. >>>>> >>>> >>>> I think Scott might have explained this in the past. uart3 is going to >>>> be used on all Cygnus boards (including all future boards) because the >>>> bootrom was designed to use uart3 as console and that won't change. >>>> >>>> Let me know if you still think I need to move this back to the dts. >>> >>> I would still like to see them stay in the .dts file, if only for >>> consistency with other platforms. >>> >>> Also, even if you can guarantee that uart3 is always used for the >>> console, that doesn't prevent board designers from adding more than >>> one uart, right? >>> >>> Arnd >>> >> >> Okay. Given that this patch series has been merged by Florian, I'll >> submit another patch to move it back to .dts files. > > You could send me either a replacement patch series (all 9), or an > individual patch to replace a previous version (e.g; replace v2 with a > v3), or an incremental one, whatever works for you. > > Thanks! > Hi Florian, I just sent you an incremental patch to move the alias back to .dts files. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: move aliases back to .dts in Cygnus
Move aliases from bcm-cygnus.dtsi back to individual .dts files. Also
clean up the chosen node to have the stdout-path using the proper alias
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 4
arch/arm/boot/dts/bcm911360k.dts | 7 +--
arch/arm/boot/dts/bcm958300k.dts | 7 +--
arch/arm/boot/dts/bcm958305k.dts | 7 +--
4 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index b5f9f34..2778533 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -41,10 +41,6 @@
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
- aliases {
- serial0 = &uart3;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
index 814011c..091c73a 100644
--- a/arch/arm/boot/dts/bcm911360k.dts
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -38,9 +38,12 @@
model = "Cygnus SVK (BCM911360K)";
compatible = "brcm,bcm11360", "brcm,cygnus";
+ aliases {
+ serial0 = &uart3;
+ };
+
chosen {
- stdout-path = &uart3;
- bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index 2e31581..b4a1392 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -39,9 +39,12 @@
model = "Cygnus SVK (BCM958300K)";
compatible = "brcm,bcm58300", "brcm,cygnus";
+ aliases {
+ serial0 = &uart3;
+ };
+
chosen {
- stdout-path = &uart3;
- bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
};
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 288a637..3378683 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -39,9 +39,12 @@
model = "Cygnus Wireless Audio (BCM958305K)";
compatible = "brcm,bcm58305", "brcm,cygnus";
+ aliases {
+ serial0 = &uart3;
+ };
+
chosen {
- stdout-path = &uart3;
- bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
};
--
1.9.1
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Re: [PATCH v2 5/9] ARM: dts: Move all Cygnus peripherals into soc bus
On 9/23/2015 2:55 PM, Ray Jui wrote:
>
>
> On 9/23/2015 2:29 PM, Arnd Bergmann wrote:
>> On Friday 18 September 2015 15:11:27 Ray Jui wrote:
>>> On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
>>>> On Friday 18 September 2015 14:24:10 Ray Jui wrote:
>>>>> + soc {
>>>>> + compatible = "simple-bus";
>>>>> + ranges;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>
>>>>> + pinctrl: pinctrl@0301d0c8 {
>>>>>
>>>>
>>>> Similarly to the core bus, this seems to have address ranges 0x03xx and
>>>> 0x18xx on it, so put those into the ranges.
>>>>
>>>
>>> Okay we have an issue here. For whatever reason, the Cygnus ASIC team
>>> decided to put registers for the same block in random locations. We see
>>> similar issues in all of our other iProc based SoCs. We have
>>> communicated this to our ASIC team, and hopefully they can revert the
>>> trend for the next SoC.
>>>
>>> For example, the gpio_ccm has registers in the following regions:
>>>
>>> gpio_ccm: gpio@1800a000 {
>>> compatible = "brcm,cygnus-ccm-gpio";
>>> reg = <0x1800a000 0x50>,
>>> <0x0301d164 0x20>;
>>>
>>> NAND is worse, it has registers in 3 different separate regions:
>>>
>>> nand: nand@18046000 {
>>> compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
>>> "brcm,brcmnand";
>>> reg = <0x18046000 0x600>, <0xf8105408 0x600>,
>>> <0x18046f00 0x20>;
>>>
>>> As you can see, this makes it impossible to define a proper address
>>> range for the bus; therefore, I'll have to keep the ranges undefined and
>>> a simple 1:1 mapping under this bus.
>>
>> Hmm, you could still try to list them as non-overlapping with other
>> buses on the root node like
>>
>> ranges = <0x0300 0x0300 0x0100>,
>> <0x1800 0x1800 0x0100>,
>> <0xf800 0xf800 0x0100>;
>>
>> which clarifies how the bus is wired up in hardware.
>>
>> Alternatively, you could make a more elaborate mapping, if there
>> are in fact multiple hardware ranges, like
>>
>> #address-cells = <2>; # space:offset
>> ranges = <1 0 0x0300 0x0100>,
>> <2 0 0x1800 0x0100>,
>> <3 0 0xf800 0x0100>;
>>
>> It really depends on what the hardware designers were thinking. If
>> the AXI bus actually decodes the entire 32-bit address range and devices
>> are just located at random addresses in there, your current scheme is
>> probably closest to reality.
>>
>
> I see. Let me talk to our ASIC team to get this clarified. If in the end
> the AXI bus decodes the entire 32-bit address space, no change will be
> made. Otherwise, I'll submit another patch to list the actual address
> space that the AXI bus decodes.
>
> Thanks for the review. It's very helpful!
>
> Ray
>
I just got feedback from our ASIC team. The NIC-301 is the main AXI
fabric that decodes the entire 32-bit address space on Cygnus.
I'll keep this as it is for now.
Thanks,
Ray
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Re: [PATCH v2 5/9] ARM: dts: Move all Cygnus peripherals into soc bus
On 9/23/2015 2:29 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 15:11:27 Ray Jui wrote:
>> On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
>>> On Friday 18 September 2015 14:24:10 Ray Jui wrote:
>>>> + soc {
>>>> + compatible = "simple-bus";
>>>> + ranges;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>
>>>> + pinctrl: pinctrl@0301d0c8 {
>>>>
>>>
>>> Similarly to the core bus, this seems to have address ranges 0x03xx and
>>> 0x18xx on it, so put those into the ranges.
>>>
>>
>> Okay we have an issue here. For whatever reason, the Cygnus ASIC team
>> decided to put registers for the same block in random locations. We see
>> similar issues in all of our other iProc based SoCs. We have
>> communicated this to our ASIC team, and hopefully they can revert the
>> trend for the next SoC.
>>
>> For example, the gpio_ccm has registers in the following regions:
>>
>> gpio_ccm: gpio@1800a000 {
>> compatible = "brcm,cygnus-ccm-gpio";
>> reg = <0x1800a000 0x50>,
>> <0x0301d164 0x20>;
>>
>> NAND is worse, it has registers in 3 different separate regions:
>>
>> nand: nand@18046000 {
>> compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
>> "brcm,brcmnand";
>> reg = <0x18046000 0x600>, <0xf8105408 0x600>,
>> <0x18046f00 0x20>;
>>
>> As you can see, this makes it impossible to define a proper address
>> range for the bus; therefore, I'll have to keep the ranges undefined and
>> a simple 1:1 mapping under this bus.
>
> Hmm, you could still try to list them as non-overlapping with other
> buses on the root node like
>
> ranges = <0x0300 0x0300 0x0100>,
><0x1800 0x1800 0x0100>,
><0xf800 0xf800 0x0100>;
>
> which clarifies how the bus is wired up in hardware.
>
> Alternatively, you could make a more elaborate mapping, if there
> are in fact multiple hardware ranges, like
>
> #address-cells = <2>; # space:offset
> ranges = <1 0 0x0300 0x0100>,
><2 0 0x1800 0x0100>,
><3 0 0xf800 0x0100>;
>
> It really depends on what the hardware designers were thinking. If
> the AXI bus actually decodes the entire 32-bit address range and devices
> are just located at random addresses in there, your current scheme is
> probably closest to reality.
>
I see. Let me talk to our ASIC team to get this clarified. If in the end
the AXI bus decodes the entire 32-bit address space, no change will be
made. Otherwise, I'll submit another patch to list the actual address
space that the AXI bus decodes.
Thanks for the review. It's very helpful!
Ray
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Re: [PATCH v2 1/9] ARM: dts: consolidate aliases for Cygnus dt files
On 9/23/2015 2:31 PM, Arnd Bergmann wrote: > On Friday 18 September 2015 14:44:54 Ray Jui wrote: >> On 9/18/2015 2:27 PM, Arnd Bergmann wrote: >>> On Friday 18 September 2015 14:24:06 Ray Jui wrote: >>> >>> The SoC has at least four uarts according to this, so it seems unlikely that >>> each board really only uses only the fourth one of them and labels it '0' >>> on the board. As soon as you get one board that has more than one uart wired >>> up, you would need to undo this. >>> >> >> I think Scott might have explained this in the past. uart3 is going to >> be used on all Cygnus boards (including all future boards) because the >> bootrom was designed to use uart3 as console and that won't change. >> >> Let me know if you still think I need to move this back to the dts. > > I would still like to see them stay in the .dts file, if only for > consistency with other platforms. > > Also, even if you can guarantee that uart3 is always used for the > console, that doesn't prevent board designers from adding more than > one uart, right? > > Arnd > Okay. Given that this patch series has been merged by Florian, I'll submit another patch to move it back to .dts files. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 6/9] ARM: dts: Enable various peripherals on bcm958305k
This patch enables various peripherals on Broadcom Cygnus wireless audio
board (bcm958305k). These peripherals include I2C, PCIe, and NAND
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm958305k.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index af11a8e..9863a19 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -44,6 +44,38 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH v3 0/9] Broadcom Cygnus device tree changes
This patch series cleans up the Broadcom Cygnus device tree files and makes it more consistent with the rest of Broadcom iProc device tree files. This patch series also enables various peripherals on Cygnus boards. They include: bcm11360_entphn: NAND bcm958300k: touchscreen bcm958305k: I2C, PCIe, NAND, touchscreen Code is based on v4.3-rc1 and is available on GITHUB: https://github.com/Broadcom/cygnus-linux/tree/cygnus-dt-v3 Changes from V2: - Drop PCIe device node change that removes the I/O resource - Set up appropriate address range for the 'core' bus - Rename the 'soc' bus node to 'axi' - Remove incorrect 3rd compatible string 'brcm,brcmnand' in the NAND node Chages from V1: - Break the major clean up change into separate patches Ray Jui (9): ARM: dts: consolidate aliases for Cygnus dt files ARM: dts: Use label for device nodes in Cygnus dts ARM: dts: Put Cygnus core components under core bus ARM: dts: Move all Cygnus peripherals into axi bus ARM: dts: Reorder Cygnus peripherals ARM: dts: Enable various peripherals on bcm958305k ARM: dts: Enable NAND support on bcm911360_entphn ARM: dts: enable touchscreen support on Cygnus ARM: dts: fix Cygnus nand device node arch/arm/boot/dts/bcm-cygnus.dtsi | 338 + arch/arm/boot/dts/bcm911360_entphn.dts | 28 ++- arch/arm/boot/dts/bcm911360k.dts | 10 +- arch/arm/boot/dts/bcm958300k.dts | 45 ++--- arch/arm/boot/dts/bcm958305k.dts | 41 +++- arch/arm/boot/dts/bcm9hmidc.dtsi | 42 6 files changed, 300 insertions(+), 204 deletions(-) create mode 100644 arch/arm/boot/dts/bcm9hmidc.dtsi -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/9] ARM: dts: Put Cygnus core components under core bus
Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 54 ++-
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 30903ba..97fd305 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -58,6 +58,36 @@
/include/ "bcm-cygnus-clock.dtsi"
+ core {
+ compatible = "simple-bus";
+ ranges = <0x 0x1900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
+
+ gic: interrupt-controller@21000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
@@ -227,28 +257,4 @@
brcm,nand-has-wp;
};
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x19021000 0x1000>,
- <0x19020100 0x100>;
- };
-
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x19022000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- timer@19020200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x19020200 0x100>;
- interrupts = ;
- clocks = <&periph_clk>;
- };
-
};
--
1.9.1
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[PATCH v3 5/9] ARM: dts: Reorder Cygnus peripherals
Reorder all Cygnus peripherals based on base register addresses in
bcm-cygnus.dtsi
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 56 +++
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 5ee7543..33ec6a5 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -108,26 +108,14 @@
gpio-controller;
};
- gpio_ccm: gpio@1800a000 {
- compatible = "brcm,cygnus-ccm-gpio";
- reg = <0x1800a000 0x50>,
- <0x0301d164 0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupts = ;
- interrupt-controller;
- };
-
- gpio_asiu: gpio@180a5000 {
- compatible = "brcm,cygnus-asiu-gpio";
- reg = <0x180a5000 0x668>;
- #gpio-cells = <2>;
- gpio-controller;
-
- pinmux = <&pinctrl>;
-
- interrupt-controller;
- interrupts = ;
+ i2c0: i2c@18008000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x18008000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clock-frequency = <10>;
+ status = "disabled";
};
wdt0: wdt@18009000 {
@@ -138,14 +126,14 @@
clock-names = "apb_pclk";
};
- i2c0: i2c@18008000 {
- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
- reg = <0x18008000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = ;
- clock-frequency = <10>;
- status = "disabled";
+ gpio_ccm: gpio@1800a000 {
+ compatible = "brcm,cygnus-ccm-gpio";
+ reg = <0x1800a000 0x50>,
+ <0x0301d164 0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupts = ;
+ interrupt-controller;
};
i2c1: i2c@1800b000 {
@@ -257,5 +245,17 @@
brcm,nand-has-wp;
};
+
+ gpio_asiu: gpio@180a5000 {
+ compatible = "brcm,cygnus-asiu-gpio";
+ reg = <0x180a5000 0x668>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ pinmux = <&pinctrl>;
+
+ interrupt-controller;
+ interrupts = ;
+ };
};
};
--
1.9.1
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[PATCH v3 4/9] ARM: dts: Move all Cygnus peripherals into axi bus
Move all Cygnus peripherals to be under the "axi" bus node of type
"simple-bus"
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 279 +++---
1 file changed, 140 insertions(+), 139 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 97fd305..5ee7543 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -88,173 +88,174 @@
};
};
- pinctrl: pinctrl@0x0301d0c8 {
- compatible = "brcm,cygnus-pinmux";
- reg = <0x0301d0c8 0x30>,
- <0x0301d24c 0x2c>;
- };
+ axi {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
- gpio_crmu: gpio@03024800 {
- compatible = "brcm,cygnus-crmu-gpio";
- reg = <0x03024800 0x50>,
- <0x03024008 0x18>;
- #gpio-cells = <2>;
- gpio-controller;
- };
+ pinctrl: pinctrl@0x0301d0c8 {
+ compatible = "brcm,cygnus-pinmux";
+ reg = <0x0301d0c8 0x30>,
+ <0x0301d24c 0x2c>;
+ };
- gpio_ccm: gpio@1800a000 {
- compatible = "brcm,cygnus-ccm-gpio";
- reg = <0x1800a000 0x50>,
- <0x0301d164 0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupts = ;
- interrupt-controller;
- };
+ gpio_crmu: gpio@03024800 {
+ compatible = "brcm,cygnus-crmu-gpio";
+ reg = <0x03024800 0x50>,
+ <0x03024008 0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
- gpio_asiu: gpio@180a5000 {
- compatible = "brcm,cygnus-asiu-gpio";
- reg = <0x180a5000 0x668>;
- #gpio-cells = <2>;
- gpio-controller;
+ gpio_ccm: gpio@1800a000 {
+ compatible = "brcm,cygnus-ccm-gpio";
+ reg = <0x1800a000 0x50>,
+ <0x0301d164 0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupts = ;
+ interrupt-controller;
+ };
- pinmux = <&pinctrl>;
+ gpio_asiu: gpio@180a5000 {
+ compatible = "brcm,cygnus-asiu-gpio";
+ reg = <0x180a5000 0x668>;
+ #gpio-cells = <2>;
+ gpio-controller;
- interrupt-controller;
- interrupts = ;
- };
+ pinmux = <&pinctrl>;
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus", "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ interrupt-controller;
+ interrupts = ;
+ };
- wdt@18009000 {
-compatible = "arm,sp805" , "arm,primecell";
-reg = <0x18009000 0x1000>;
-interrupts = ;
-clocks = <&axi81_clk>;
-clock-names = "apb_pclk";
+ wdt0: wdt@18009000 {
+ compatible = "arm,sp805" , "arm,primecell";
+ reg = <0x18009000 0x1000>;
+ interrupts = ;
+ clocks = <&axi81_clk>;
+ clock-names = "apb_pclk";
};
- };
- i2c0: i2c@18008000 {
- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
- reg = <0x18008000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = ;
- clock-frequency = <10>;
- status = "disabled";
- };
+ i2c0: i2c@18008000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x18008000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ inte
[PATCH v3 2/9] ARM: dts: Use label for device nodes in Cygnus dts
Use label instead of full path to reference device nodes in Cygnus dts
files
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm911360_entphn.dts | 8 +++
arch/arm/boot/dts/bcm911360k.dts | 6 ++---
arch/arm/boot/dts/bcm958300k.dts | 40 +-
arch/arm/boot/dts/bcm958305k.dts | 6 ++---
4 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index 0e1320e..f791a3b 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -44,10 +44,6 @@
bootargs = "console=ttyS0,115200";
};
- uart3: serial@18023000 {
- status = "okay";
- };
-
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -60,3 +56,7 @@
};
};
};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
index 2af40c6..814011c 100644
--- a/arch/arm/boot/dts/bcm911360k.dts
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -42,8 +42,8 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index 75e50f0..d8dc9f0 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -42,32 +42,32 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- pcie0: pcie@18012000 {
- status = "okay";
- };
+&pcie0 {
+ status = "okay";
+};
- pcie1: pcie@18013000 {
- status = "okay";
- };
+&pcie1 {
+ status = "okay";
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
+};
- nand: nand@18046000 {
- nandcs@1 {
- compatible = "brcm,nandcs";
- reg = <0>;
- nand-on-flash-bbt;
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- nand-ecc-strength = <24>;
- nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
- brcm,nand-oob-sector-size = <27>;
- };
+ brcm,nand-oob-sector-size = <27>;
};
};
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index bf62e1b..af11a8e 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -42,8 +42,8 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
};
--
1.9.1
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[PATCH v3 9/9] ARM: dts: fix Cygnus nand device node
The third compatible string "brcm,brcmnand" in bcm-cygnus.dtsi nand node
is incorrect, redundant and should be removed. "brcm,brcmnand" is meant to
be used by STB based Broadcom SoCs. All iProc based SoCs should use
"brcm,nand-iproc".
Signed-off-by: Ray Jui
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 24e058c..b5f9f34 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -234,8 +234,7 @@
};
nand: nand@18046000 {
- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
-"brcm,brcmnand";
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
--
1.9.1
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[PATCH v3 7/9] ARM: dts: Enable NAND support on bcm911360_entphn
This patch enables NAND support on Broadcom Cygnus form factor board
(bcm911360_entphn)
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm911360_entphn.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index f791a3b..8b3800f 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -60,3 +60,19 @@
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH v3 8/9] ARM: dts: enable touchscreen support on Cygnus
This patch enables touchscreen support on bcm958300k and bcm958305k.
Touchscreen is connected to these boards through the bcm9hmidc daughter
card, and therefore also adding bcm9hmidc.dtsi that describes the
daughter card
Signed-off-by: Ray Jui
Reviewed-by: Vikram Prakash
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 10 ++
arch/arm/boot/dts/bcm958300k.dts | 1 +
arch/arm/boot/dts/bcm958305k.dts | 1 +
arch/arm/boot/dts/bcm9hmidc.dtsi | 42 +++
4 files changed, 54 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm9hmidc.dtsi
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 33ec6a5..24e058c 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -257,5 +258,14 @@
interrupt-controller;
interrupts = ;
};
+
+ touchscreen: tsc@180a6000 {
+ compatible = "brcm,iproc-touchscreen";
+ reg = <0x180a6000 0x40>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = ;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index d8dc9f0..2e31581 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus SVK (BCM958300K)";
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 9863a19..288a637 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus Wireless Audio (BCM958305K)";
diff --git a/arch/arm/boot/dts/bcm9hmidc.dtsi b/arch/arm/boot/dts/bcm9hmidc.dtsi
new file mode 100644
index 000..65397c0
--- /dev/null
+++ b/arch/arm/boot/dts/bcm9hmidc.dtsi
@@ -0,0 +1,42 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Broadcom human machine interface daughter card (bcm9hmidc) installed on
+ * bcm958300k/bcm958305k boards
+ */
+
+&touchscreen {
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ status = "okay";
+};
--
1.9.1
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[PATCH v3 1/9] ARM: dts: consolidate aliases for Cygnus dt files
Move aliases into bcm-cygnus.dtsi to avoid duplications in Cygnus dts
files
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 4
arch/arm/boot/dts/bcm911360_entphn.dts | 4
arch/arm/boot/dts/bcm911360k.dts | 4
arch/arm/boot/dts/bcm958300k.dts | 4
arch/arm/boot/dts/bcm958305k.dts | 4
5 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index e1ac07a..30903ba 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -40,6 +40,10 @@
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
+ aliases {
+ serial0 = &uart3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index 7db4843..0e1320e 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -39,10 +39,6 @@
model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
compatible = "brcm,bcm11360", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
index 9658d4f..2af40c6 100644
--- a/arch/arm/boot/dts/bcm911360k.dts
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -38,10 +38,6 @@
model = "Cygnus SVK (BCM911360K)";
compatible = "brcm,bcm11360", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index 2f63052..75e50f0 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -38,10 +38,6 @@
model = "Cygnus SVK (BCM958300K)";
compatible = "brcm,bcm58300", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 56b429a..bf62e1b 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -38,10 +38,6 @@
model = "Cygnus Wireless Audio (BCM958305K)";
compatible = "brcm,bcm58305", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
--
1.9.1
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Re: [PATCH v2 5/9] ARM: dts: Move all Cygnus peripherals into soc bus
On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 14:24:10 Ray Jui wrote:
>> + soc {
>> + compatible = "simple-bus";
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
>> + pinctrl: pinctrl@0301d0c8 {
>>
>
> Similarly to the core bus, this seems to have address ranges 0x03xx and
> 0x18xx on it, so put those into the ranges.
>
Okay we have an issue here. For whatever reason, the Cygnus ASIC team
decided to put registers for the same block in random locations. We see
similar issues in all of our other iProc based SoCs. We have
communicated this to our ASIC team, and hopefully they can revert the
trend for the next SoC.
For example, the gpio_ccm has registers in the following regions:
gpio_ccm: gpio@1800a000 {
compatible = "brcm,cygnus-ccm-gpio";
reg = <0x1800a000 0x50>,
<0x0301d164 0x20>;
NAND is worse, it has registers in 3 different separate regions:
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
"brcm,brcmnand";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;
As you can see, this makes it impossible to define a proper address
range for the bus; therefore, I'll have to keep the ranges undefined and
a simple 1:1 mapping under this bus.
> It probably also makes sense to name the bus according to what kind of
> bus (axi, ahb, plb, ...) is used here. If the soc has nested buses
> (e.g. an ahb connected to an axi bus,) then model both of them in the DT.
Based on the block diagram from the ASIC team, it looks like all of them
are connected to one major AXI fabric. I can rename the bus to AXI.
>
> Arnd
>
Thanks,
Ray
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Re: [PATCH v2 4/9] ARM: dts: Put Cygnus core components under core bus
On 9/18/2015 2:30 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 14:24:09 Ray Jui wrote:
>>
>> + core {
>> + compatible = "simple-bus";
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + timer@19020200 {
>> + compatible = "arm,cortex-a9-global-timer";
>> + reg = <0x19020200 0x100>;
>> + interrupts = ;
>> + clocks = <&periph_clk>;
>> + };
>> +
>> + gic: interrupt-controller@19021000 {
>>
>
> Could it be that all 'core' components are in the 0x19xx address range?
> If so, please set up an appropriate ranges property for the bus. Also
> add the address field for the bus according to which addresses are routed
> to it.
>
> Arnd
>
Yes all 'core' components are in the 0x19x address range for Cygnus.
It's fine and makes sense to set up proper ranges for this bus. But I
might have some issues with the 'soc' components and the 'soc' bus,
which I'll explain and discuss on the next email.
Ray
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Re: [PATCH v2 3/9] ARM: dts: Remove unused PCI I/O resource in Cygnus
On 9/18/2015 2:28 PM, Arnd Bergmann wrote: > On Friday 18 September 2015 14:24:08 Ray Jui wrote: >> Remove unused PCI I/O resource in bcm-cygnus.dtsi >> >> Signed-off-by: Ray Jui >> Reviewed-by: Scott Branden >> > > Why? How do you know that nobody ever plugs in a card with I/O ports? > > Arnd > I'll drop this change. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/9] ARM: dts: consolidate aliases for Cygnus dt files
On 9/18/2015 2:27 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 14:24:06 Ray Jui wrote:
>> Move aliases into bcm-cygnus.dtsi to avoid duplications in Cygnus dts
>> files
>>
>
> We generally recommend keeping them separate:
>
>> diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
>> b/arch/arm/boot/dts/bcm-cygnus.dtsi
>> index e1ac07a..30903ba 100644
>> --- a/arch/arm/boot/dts/bcm-cygnus.dtsi
>> +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
>> @@ -40,6 +40,10 @@
>> model = "Broadcom Cygnus SoC";
>> interrupt-parent = <&gic>;
>>
>> + aliases {
>> + serial0 = &uart3;
>> + };
>> +
>
> The SoC has at least four uarts according to this, so it seems unlikely that
> each board really only uses only the fourth one of them and labels it '0'
> on the board. As soon as you get one board that has more than one uart wired
> up, you would need to undo this.
>
> Arnd
>
I think Scott might have explained this in the past. uart3 is going to
be used on all Cygnus boards (including all future boards) because the
bootrom was designed to use uart3 as console and that won't change.
Let me know if you still think I need to move this back to the dts.
Thanks,
Ray
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[PATCH v2 3/9] ARM: dts: Remove unused PCI I/O resource in Cygnus
Remove unused PCI I/O resource in bcm-cygnus.dtsi Signed-off-by: Ray Jui Reviewed-by: Scott Branden --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 30903ba..0a5898b 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -145,8 +145,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x8100 0 0 0x2800 0 0x0001 - 0x8200 0 0x2000 0x2000 0 0x0400>; + ranges = <0x8200 0 0x2000 0x2000 0 0x0400>; status = "disabled"; }; @@ -166,8 +165,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x8100 0 0 0x4800 0 0x0001 - 0x8200 0 0x4000 0x4000 0 0x0400>; + ranges = <0x8200 0 0x4000 0x4000 0 0x0400>; status = "disabled"; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/9] ARM: dts: Use label for device nodes in Cygnus dts
Use label instead of full path to reference device nodes in Cygnus dts
files
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm911360_entphn.dts | 8 +++
arch/arm/boot/dts/bcm911360k.dts | 6 ++---
arch/arm/boot/dts/bcm958300k.dts | 40 +-
arch/arm/boot/dts/bcm958305k.dts | 6 ++---
4 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index 0e1320e..f791a3b 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -44,10 +44,6 @@
bootargs = "console=ttyS0,115200";
};
- uart3: serial@18023000 {
- status = "okay";
- };
-
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -60,3 +56,7 @@
};
};
};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
index 2af40c6..814011c 100644
--- a/arch/arm/boot/dts/bcm911360k.dts
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -42,8 +42,8 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index 75e50f0..d8dc9f0 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -42,32 +42,32 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- pcie0: pcie@18012000 {
- status = "okay";
- };
+&pcie0 {
+ status = "okay";
+};
- pcie1: pcie@18013000 {
- status = "okay";
- };
+&pcie1 {
+ status = "okay";
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
+};
- nand: nand@18046000 {
- nandcs@1 {
- compatible = "brcm,nandcs";
- reg = <0>;
- nand-on-flash-bbt;
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- nand-ecc-strength = <24>;
- nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
- brcm,nand-oob-sector-size = <27>;
- };
+ brcm,nand-oob-sector-size = <27>;
};
};
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index bf62e1b..af11a8e 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -42,8 +42,8 @@
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
+};
- uart3: serial@18023000 {
- status = "okay";
- };
+&uart3 {
+ status = "okay";
};
--
1.9.1
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[PATCH v2 6/9] ARM: dts: Reorder Cygnus peripherals
Reorder all Cygnus peripherals based on base register addresses in
bcm-cygnus.dtsi
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 56 +++
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 3d29b77..dfa9a3c 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -108,26 +108,14 @@
gpio-controller;
};
- gpio_ccm: gpio@1800a000 {
- compatible = "brcm,cygnus-ccm-gpio";
- reg = <0x1800a000 0x50>,
- <0x0301d164 0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupts = ;
- interrupt-controller;
- };
-
- gpio_asiu: gpio@180a5000 {
- compatible = "brcm,cygnus-asiu-gpio";
- reg = <0x180a5000 0x668>;
- #gpio-cells = <2>;
- gpio-controller;
-
- pinmux = <&pinctrl>;
-
- interrupt-controller;
- interrupts = ;
+ i2c0: i2c@18008000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x18008000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clock-frequency = <10>;
+ status = "disabled";
};
wdt0: wdt@18009000 {
@@ -138,14 +126,14 @@
clock-names = "apb_pclk";
};
- i2c0: i2c@18008000 {
- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
- reg = <0x18008000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = ;
- clock-frequency = <10>;
- status = "disabled";
+ gpio_ccm: gpio@1800a000 {
+ compatible = "brcm,cygnus-ccm-gpio";
+ reg = <0x1800a000 0x50>,
+ <0x0301d164 0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupts = ;
+ interrupt-controller;
};
i2c1: i2c@1800b000 {
@@ -255,5 +243,17 @@
brcm,nand-has-wp;
};
+
+ gpio_asiu: gpio@180a5000 {
+ compatible = "brcm,cygnus-asiu-gpio";
+ reg = <0x180a5000 0x668>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ pinmux = <&pinctrl>;
+
+ interrupt-controller;
+ interrupts = ;
+ };
};
};
--
1.9.1
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[PATCH v2 5/9] ARM: dts: Move all Cygnus peripherals into soc bus
Move all Cygnus peripherals to be under the "soc" bus node of type
"simple-bus"
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 275 +++---
1 file changed, 138 insertions(+), 137 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index d4e2d04..3d29b77 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -88,171 +88,172 @@
};
};
- pinctrl: pinctrl@0x0301d0c8 {
- compatible = "brcm,cygnus-pinmux";
- reg = <0x0301d0c8 0x30>,
- <0x0301d24c 0x2c>;
- };
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
- gpio_crmu: gpio@03024800 {
- compatible = "brcm,cygnus-crmu-gpio";
- reg = <0x03024800 0x50>,
- <0x03024008 0x18>;
- #gpio-cells = <2>;
- gpio-controller;
- };
+ pinctrl: pinctrl@0301d0c8 {
+ compatible = "brcm,cygnus-pinmux";
+ reg = <0x0301d0c8 0x30>,
+ <0x0301d24c 0x2c>;
+ };
- gpio_ccm: gpio@1800a000 {
- compatible = "brcm,cygnus-ccm-gpio";
- reg = <0x1800a000 0x50>,
- <0x0301d164 0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupts = ;
- interrupt-controller;
- };
+ gpio_crmu: gpio@03024800 {
+ compatible = "brcm,cygnus-crmu-gpio";
+ reg = <0x03024800 0x50>,
+ <0x03024008 0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
- gpio_asiu: gpio@180a5000 {
- compatible = "brcm,cygnus-asiu-gpio";
- reg = <0x180a5000 0x668>;
- #gpio-cells = <2>;
- gpio-controller;
+ gpio_ccm: gpio@1800a000 {
+ compatible = "brcm,cygnus-ccm-gpio";
+ reg = <0x1800a000 0x50>,
+ <0x0301d164 0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupts = ;
+ interrupt-controller;
+ };
- pinmux = <&pinctrl>;
+ gpio_asiu: gpio@180a5000 {
+ compatible = "brcm,cygnus-asiu-gpio";
+ reg = <0x180a5000 0x668>;
+ #gpio-cells = <2>;
+ gpio-controller;
- interrupt-controller;
- interrupts = ;
- };
+ pinmux = <&pinctrl>;
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus", "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ interrupt-controller;
+ interrupts = ;
+ };
- wdt@18009000 {
-compatible = "arm,sp805" , "arm,primecell";
-reg = <0x18009000 0x1000>;
-interrupts = ;
-clocks = <&axi81_clk>;
-clock-names = "apb_pclk";
+ wdt0: wdt@18009000 {
+ compatible = "arm,sp805" , "arm,primecell";
+ reg = <0x18009000 0x1000>;
+ interrupts = ;
+ clocks = <&axi81_clk>;
+ clock-names = "apb_pclk";
};
- };
- i2c0: i2c@18008000 {
- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
- reg = <0x18008000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = ;
- clock-frequency = <10>;
- status = "disabled";
- };
+ i2c0: i2c@18008000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x18008000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ inte
[PATCH v2 9/9] ARM: dts: enable touchscreen support on Cygnus
This patch enables touchscreen support on bcm958300k and bcm958305k.
Touchscreen is connected to these boards through the bcm9hmidc daughter
card, and therefore also adding bcm9hmidc.dtsi that describes the
daughter card
Signed-off-by: Ray Jui
Reviewed-by: Vikram Prakash
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 10 ++
arch/arm/boot/dts/bcm958300k.dts | 1 +
arch/arm/boot/dts/bcm958305k.dts | 1 +
arch/arm/boot/dts/bcm9hmidc.dtsi | 42 +++
4 files changed, 54 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm9hmidc.dtsi
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index dfa9a3c..d898838 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -255,5 +256,14 @@
interrupt-controller;
interrupts = ;
};
+
+ touchscreen: tsc@180a6000 {
+ compatible = "brcm,iproc-touchscreen";
+ reg = <0x180a6000 0x40>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = ;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index d8dc9f0..2e31581 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus SVK (BCM958300K)";
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 9863a19..288a637 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus Wireless Audio (BCM958305K)";
diff --git a/arch/arm/boot/dts/bcm9hmidc.dtsi b/arch/arm/boot/dts/bcm9hmidc.dtsi
new file mode 100644
index 000..65397c0
--- /dev/null
+++ b/arch/arm/boot/dts/bcm9hmidc.dtsi
@@ -0,0 +1,42 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Broadcom human machine interface daughter card (bcm9hmidc) installed on
+ * bcm958300k/bcm958305k boards
+ */
+
+&touchscreen {
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ status = "okay";
+};
--
1.9.1
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[PATCH v2 8/9] ARM: dts: Enable NAND support on bcm911360_entphn
This patch enables NAND support on Broadcom Cygnus form factor board
(bcm911360_entphn)
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm911360_entphn.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index f791a3b..8b3800f 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -60,3 +60,19 @@
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH v2 7/9] ARM: dts: Enable various peripherals on bcm958305k
This patch enables various peripherals on Broadcom Cygnus wireless audio
board (bcm958305k). These peripherals include I2C, PCIe, and NAND
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm958305k.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index af11a8e..9863a19 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -44,6 +44,38 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH v2 4/9] ARM: dts: Put Cygnus core components under core bus
Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 54 ++-
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 0a5898b..d4e2d04 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -58,6 +58,36 @@
/include/ "bcm-cygnus-clock.dtsi"
+ core {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ timer@19020200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x19020200 0x100>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
+
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x19021000 0x1000>,
+ <0x19020100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x19022000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
@@ -225,28 +255,4 @@
brcm,nand-has-wp;
};
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x19021000 0x1000>,
- <0x19020100 0x100>;
- };
-
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x19022000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- timer@19020200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x19020200 0x100>;
- interrupts = ;
- clocks = <&periph_clk>;
- };
-
};
--
1.9.1
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[PATCH v2 0/9] Broadcom Cygnus device tree changes
This patch series cleans up the Broadcom Cygnus device tree files and makes it more consistent with the rest of Broadcom iProc device tree files. This patch series also enables various peripherals on Cygnus boards. They include: bcm11360_entphn: NAND bcm958300k: touchscreen bcm958305k: I2C, PCIe, NAND, touchscreen Code is based on v4.3-rc1 and is available on GITHUB: https://github.com/Broadcom/cygnus-linux/tree/cygnus-dt-v2 Chages from V1: - Break the major clean up change into separate patches Ray Jui (9): ARM: dts: consolidate aliases for Cygnus dt files ARM: dts: Use label for device nodes in Cygnus dts ARM: dts: Remove unused PCI I/O resource in Cygnus ARM: dts: Put Cygnus core components under core bus ARM: dts: Move all Cygnus peripherals into soc bus ARM: dts: Reorder Cygnus peripherals ARM: dts: Enable various peripherals on bcm958305k ARM: dts: Enable NAND support on bcm911360_entphn ARM: dts: enable touchscreen support on Cygnus arch/arm/boot/dts/bcm-cygnus.dtsi | 337 + arch/arm/boot/dts/bcm911360_entphn.dts | 28 ++- arch/arm/boot/dts/bcm911360k.dts | 10 +- arch/arm/boot/dts/bcm958300k.dts | 45 ++--- arch/arm/boot/dts/bcm958305k.dts | 41 +++- arch/arm/boot/dts/bcm9hmidc.dtsi | 42 6 files changed, 299 insertions(+), 204 deletions(-) create mode 100644 arch/arm/boot/dts/bcm9hmidc.dtsi -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/9] ARM: dts: consolidate aliases for Cygnus dt files
Move aliases into bcm-cygnus.dtsi to avoid duplications in Cygnus dts
files
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 4
arch/arm/boot/dts/bcm911360_entphn.dts | 4
arch/arm/boot/dts/bcm911360k.dts | 4
arch/arm/boot/dts/bcm958300k.dts | 4
arch/arm/boot/dts/bcm958305k.dts | 4
5 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index e1ac07a..30903ba 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -40,6 +40,10 @@
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
+ aliases {
+ serial0 = &uart3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index 7db4843..0e1320e 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -39,10 +39,6 @@
model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
compatible = "brcm,bcm11360", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
index 9658d4f..2af40c6 100644
--- a/arch/arm/boot/dts/bcm911360k.dts
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -38,10 +38,6 @@
model = "Cygnus SVK (BCM911360K)";
compatible = "brcm,bcm11360", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index 2f63052..75e50f0 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -38,10 +38,6 @@
model = "Cygnus SVK (BCM958300K)";
compatible = "brcm,bcm58300", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 56b429a..bf62e1b 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -38,10 +38,6 @@
model = "Cygnus Wireless Audio (BCM958305K)";
compatible = "brcm,bcm58305", "brcm,cygnus";
- aliases {
- serial0 = &uart3;
- };
-
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
--
1.9.1
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Re: [PATCH 1/4] ARM: dts: clean up Cygnus DT files
On 9/17/2015 6:16 PM, Florian Fainelli wrote: > On 17/09/15 16:57, Ray Jui wrote: >> This patch cleans up Cygnus DT files and makes the format consistent >> with the rest of Broadcom iProc based SoCs. >> >> Changes include: >> - Put core components into "core" node of type "simple-bus" >> - Put all other peripherals into "soc" node of type "simple-bus" >> - Move aliases into bcm-cygnus.dtsi to avoid duplications in all dts >> files >> - Ordered all device nodes under buses based on their base register >> addresses >> - Remove unused PCI I/O resource >> - Use label instead of full path to reference device nodes in dts >> files > > I am fine with the changes per-se, but the review is made largely more > difficult because you mix multiple changes at the same time, this really > ought to be separate patches to ease the review process. Sorry for not > picking that up earlier. Sure! I'll break them up into individual patches as follows: - Put core components into "core" node of type "simple-bus" - Put all other peripherals into "soc" node of type "simple-bus" - Move aliases into bcm-cygnus.dtsi to avoid duplications in all dts files - Ordered all device nodes under buses based on their base register addresses - Remove unused PCI I/O resources - Use label instead of full path to reference device nodes in dts files Thanks! Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: dts: clean up Cygnus DT files
This patch cleans up Cygnus DT files and makes the format consistent
with the rest of Broadcom iProc based SoCs.
Changes include:
- Put core components into "core" node of type "simple-bus"
- Put all other peripherals into "soc" node of type "simple-bus"
- Move aliases into bcm-cygnus.dtsi to avoid duplications in all dts
files
- Ordered all device nodes under buses based on their base register
addresses
- Remove unused PCI I/O resource
- Use label instead of full path to reference device nodes in dts
files
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 328 +
arch/arm/boot/dts/bcm911360_entphn.dts | 12 +-
arch/arm/boot/dts/bcm911360k.dts | 10 +-
arch/arm/boot/dts/bcm958300k.dts | 44 ++---
arch/arm/boot/dts/bcm958305k.dts | 10 +-
5 files changed, 199 insertions(+), 205 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index e1ac07a..1f56b18 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -40,6 +41,10 @@
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
+ aliases {
+ serial0 = &uart3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -54,197 +59,202 @@
/include/ "bcm-cygnus-clock.dtsi"
- pinctrl: pinctrl@0x0301d0c8 {
- compatible = "brcm,cygnus-pinmux";
- reg = <0x0301d0c8 0x30>,
- <0x0301d24c 0x2c>;
- };
-
- gpio_crmu: gpio@03024800 {
- compatible = "brcm,cygnus-crmu-gpio";
- reg = <0x03024800 0x50>,
- <0x03024008 0x18>;
- #gpio-cells = <2>;
- gpio-controller;
- };
-
- gpio_ccm: gpio@1800a000 {
- compatible = "brcm,cygnus-ccm-gpio";
- reg = <0x1800a000 0x50>,
- <0x0301d164 0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupts = ;
- interrupt-controller;
- };
+ core {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
- gpio_asiu: gpio@180a5000 {
- compatible = "brcm,cygnus-asiu-gpio";
- reg = <0x180a5000 0x668>;
- #gpio-cells = <2>;
- gpio-controller;
+ timer@19020200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x19020200 0x100>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
- pinmux = <&pinctrl>;
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x19021000 0x1000>,
+ <0x19020100 0x100>;
+ };
- interrupt-controller;
- interrupts = ;
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x19022000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
- amba {
+ soc {
+ compatible = "simple-bus";
+ ranges;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "arm,amba-bus", "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
- wdt@18009000 {
-compatible = "arm,sp805" , "arm,primecell";
-reg = <0x18009000 0x1000>;
-interrupts = ;
-clocks = <&axi81_clk>;
-clock-names = "apb_pclk";
+ pinctrl: pinctrl@0301d0c8 {
+ compatible = "brcm,cygnus-pinmux";
+ reg = <0x0301d0c8 0x30>,
+ <0x0301d24c 0x2c>;
};
- };
- i2c0: i2c@18008000 {
- compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc
[PATCH 2/4] ARM: dts: Enable various peripherals on bcm958305k
This patch enables various peripherals on Broadcom Cygnus wireless audio
board (bcm958305k). These peripherals include I2C, PCIe, and NAND
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm958305k.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index af11a8e..9863a19 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -44,6 +44,38 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH 3/4] ARM: dts: Enable NAND support on bcm911360_entphn
This patch enables NAND support on Broadcom Cygnus form factor board
(bcm911360_entphn)
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm911360_entphn.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts
b/arch/arm/boot/dts/bcm911360_entphn.dts
index f791a3b..8b3800f 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -60,3 +60,19 @@
&uart3 {
status = "okay";
};
+
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+ };
+};
--
1.9.1
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[PATCH 0/4] Broadcom Cygnus device tree changes
This patch series cleans up the Broadcom Cygnus device tree files and makes it more consistent with the rest of Broadcom iProc device tree files. This patch series also enables various peripherals on Cygnus boards. They include: bcm11360_entphn: NAND bcm958300k: touchscreen bcm958305k: I2C, PCIe, NAND, touchscreen Code is based on v4.3-rc1 and is available on GITHUB: https://github.com/Broadcom/cygnus-linux/tree/cygnus-dt-v1 Ray Jui (4): ARM: dts: clean up Cygnus DT files ARM: dts: Enable various peripherals on bcm958305k ARM: dts: Enable NAND support on bcm911360_entphn ARM: dts: enable touchscreen support on Cygnus arch/arm/boot/dts/bcm-cygnus.dtsi | 337 + arch/arm/boot/dts/bcm911360_entphn.dts | 28 ++- arch/arm/boot/dts/bcm911360k.dts | 10 +- arch/arm/boot/dts/bcm958300k.dts | 45 ++--- arch/arm/boot/dts/bcm958305k.dts | 41 +++- 5 files changed, 257 insertions(+), 204 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] ARM: dts: enable touchscreen support on Cygnus
This patch enables touchscreen support on bcm958300k and bcm958305k.
Touchscreen is connected to these boards through the bcm9hmidc daughter
card
Signed-off-by: Ray Jui
Reviewed-by: Vikram Prakash
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 9 +
arch/arm/boot/dts/bcm958300k.dts | 1 +
arch/arm/boot/dts/bcm958305k.dts | 1 +
3 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 1f56b18..d898838 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -256,5 +256,14 @@
interrupt-controller;
interrupts = ;
};
+
+ touchscreen: tsc@180a6000 {
+ compatible = "brcm,iproc-touchscreen";
+ reg = <0x180a6000 0x40>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = ;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index d8dc9f0..2e31581 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus SVK (BCM958300K)";
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
index 9863a19..288a637 100644
--- a/arch/arm/boot/dts/bcm958305k.dts
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
+#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus Wireless Audio (BCM958305K)";
--
1.9.1
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Re: [PATCH v4 2/5] ARM: NSP: add minimal Northstar Plus device tree
<0x0100 0x100>;
> + };
> +
> + timer@19020200 {
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0x0200 0x100>;
> + interrupts = ;
> + clocks = <&periph_clk>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + periph_clk: periph_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <5>;
> + };
> + };
> +
> + axi {
> + compatible = "simple-bus";
> + ranges = <0x 0x1800 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: serial@18000300 {
> + compatible = "ns16550a";
> + reg = <0x0300 0x100>;
> + interrupts = ;
> + clock-frequency = <62499840>;
> + status = "disabled";
> + };
> +
> + uart1: serial@18000400 {
> + compatible = "ns16550a";
> + reg = <0x0400 0x100>;
> + interrupts = ;
> + clock-frequency = <62499840>;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/bcm958625k.dts
> b/arch/arm/boot/dts/bcm958625k.dts
> new file mode 100644
> index 000..16303db
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625k.dts
> @@ -0,0 +1,57 @@
> +/*
> + * BSD LICENSE
> + *
> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + ** Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + ** Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in
> + * the documentation and/or other materials provided with the
> + * distribution.
> + ** Neither the name of Broadcom Corporation nor the names of its
> + * contributors may be used to endorse or promote products derived
> + * from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm-nsp.dtsi"
> +
> +/ {
> + model = "NorthStar Plus SVK (BCM958625K)";
> + compatible = "brcm,bcm58625", "brcm,nsp";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
>
Looks good to me!
Reviewed-by: Ray Jui
Thanks,
Ray
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Re: [PATCH v3 2/5] ARM: NSP: add minimal Northstar Plus device tree
On 8/30/2015 7:24 PM, Jon Mason wrote:
> On Fri, Aug 28, 2015 at 05:20:20PM -0700, Ray Jui wrote:
>>
>>
>> On 8/28/2015 4:47 PM, Jon Mason wrote:
>>> Add a very minimalistic set of Northstar Plus Device Tree files which
>>> describes the SoC and the BCM958625 implementation. The perpherials
>>> described are:
>>>
>>> ARM Cortex A9 CPU
>>> 2 8250 UARTs
>>> ARM GIC
>>> PL310 L2 Cache
>>> ARM A9 Global timer
>>>
>>> Signed-off-by: Kapil Hali
>>> Signed-off-by: Jon Mason
>>> ---
>>> arch/arm/boot/dts/Makefile | 2 +
>>> arch/arm/boot/dts/bcm-nsp.dtsi | 120
>>> +++
>>> arch/arm/boot/dts/bcm958625k.dts | 57 +++
>>> 3 files changed, 179 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
>>> create mode 100644 arch/arm/boot/dts/bcm958625k.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index 246473a..adb5732 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
>>> dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
>>> bcm28155-ap.dtb \
>>> bcm21664-garnet.dtb
>>> +dtb-$(CONFIG_ARCH_BCM_NSP) += \
>>> + bcm958625k.dtb
>>> dtb-$(CONFIG_ARCH_BERLIN) += \
>>> berlin2-sony-nsz-gs7.dtb \
>>> berlin2cd-google-chromecast.dtb \
>>> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
>>> new file mode 100644
>>> index 000..f5f494f
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
>>> @@ -0,0 +1,120 @@
>>> +/*
>>> + * BSD LICENSE
>>> + *
>>> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
>>> + *
>>> + * Redistribution and use in source and binary forms, with or without
>>> + * modification, are permitted provided that the following conditions
>>> + * are met:
>>> + *
>>> + ** Redistributions of source code must retain the above copyright
>>> + * notice, this list of conditions and the following disclaimer.
>>> + ** Redistributions in binary form must reproduce the above copyright
>>> + * notice, this list of conditions and the following disclaimer in
>>> + * the documentation and/or other materials provided with the
>>> + * distribution.
>>> + ** Neither the name of Broadcom Corporation nor the names of its
>>> + * contributors may be used to endorse or promote products derived
>>> + * from this software without specific prior written permission.
>>> + *
>>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
>>> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
>>> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
>>> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
>>> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
>>> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
>>> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
>>> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
>>> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>>> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +
>>> +#include "skeleton.dtsi"
>>> +
>>> +/ {
>>> + compatible = "brcm,nsp";
>>> + model = "Broadcom Northstar Plus SoC";
>>> + interrupt-parent = <&gic>;
>>> +
>>> + mpcore {
>>> + compatible = "simple-bus";
>>> + ranges = <0x 0x1902 0x3000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu@0 {
>>> + device_type = "cpu";
>>> +
Re: [PATCH v3 2/5] ARM: NSP: add minimal Northstar Plus device tree
On 8/28/2015 4:47 PM, Jon Mason wrote:
> Add a very minimalistic set of Northstar Plus Device Tree files which
> describes the SoC and the BCM958625 implementation. The perpherials
> described are:
>
> ARM Cortex A9 CPU
> 2 8250 UARTs
> ARM GIC
> PL310 L2 Cache
> ARM A9 Global timer
>
> Signed-off-by: Kapil Hali
> Signed-off-by: Jon Mason
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/bcm-nsp.dtsi | 120
> +++
> arch/arm/boot/dts/bcm958625k.dts | 57 +++
> 3 files changed, 179 insertions(+)
> create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
> create mode 100644 arch/arm/boot/dts/bcm958625k.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 246473a..adb5732 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
> bcm28155-ap.dtb \
> bcm21664-garnet.dtb
> +dtb-$(CONFIG_ARCH_BCM_NSP) += \
> + bcm958625k.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> berlin2cd-google-chromecast.dtb \
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> new file mode 100644
> index 000..f5f494f
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -0,0 +1,120 @@
> +/*
> + * BSD LICENSE
> + *
> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + ** Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + ** Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in
> + * the documentation and/or other materials provided with the
> + * distribution.
> + ** Neither the name of Broadcom Corporation nor the names of its
> + * contributors may be used to endorse or promote products derived
> + * from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#include
> +#include
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "brcm,nsp";
> + model = "Broadcom Northstar Plus SoC";
> + interrupt-parent = <&gic>;
> +
> + mpcore {
> + compatible = "simple-bus";
> + ranges = <0x 0x1902 0x3000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0x0>;
> + };
> + };
> +
> + L2: l2-cache {
> + compatible = "arm,pl310-cache";
> + reg = <0x2000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller@19021000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x1000 0x1000>,
> + <0x0100 0x100>;
> + };
> +
> + timer@19020200 {
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0x0200 0x100>;
> + interrupts = ;
> + clocks = <&periph_clk>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + periph_clk: periph_clk {
> + compatible = "fi
Re: [PATCH v7 0/6] Add common clock support for Broadcom iProc architecture
Hi Mike/Stephen, Ping. Do you think you will be able to review this patch set some time in the near future? Thanks! Ray On 5/11/2015 2:23 PM, Ray Jui wrote: > Hi Mike, > > Have you had a chance to review the iProc clock patches? If possible, > I'd like to get feedback from you as early as possible so I can make > changes if required. It would be really nice if we can get the iProc > clock patches going into v4.2. > > A lot of our iProc drivers depend on these clock patches. > > Thanks, > > Ray > > On 5/5/2015 11:13 AM, Ray Jui wrote: >> This patchset contains the initial common clock support for Broadcom's iProc >> family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., >> ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the >> basic reference clock for these PLLs. Each PLL may have several leaf clocks. >> One special group of clocks is the ASIU clocks, which are dervied directly >> from the crystal reference clock. >> >> This patchset also contains the basic clock support for the Broadcom Cygnus >> SoC, which implements the iProc clock architecture >> >> Changes from v6: >> - Rebase to v4.1-rc2 >> - Consolidate iProc PLL and its leaf clocks into a single device node, based >>on feedback from Mike Turquette. The PLL and its leaf clocks are now >> exposed >>a clock consumer through indices of the same device node phandle >> - Update iProc device tree binding document based on the above change >> - Add SW override support to iProc PLL clocks >> >> Changes from v5: >> - Rebase to v4.0-rc4 >> - Drop of_clk_get_parent_rate helper function from the clock framework >> - Get rid of custom "clock-frequency" support in iProc PLL code. Instead, >> add >>standard clock set_rate and round_rate support and make use of DT >> properties >>"assigned-clocks" and "assigned-clock-rates" to initialize PLL to the >>desired rate when registering to the clock framework >> - Add SW workaround for ASIC bug on MIPI PLL to always read back the same >>register following a write transaction, to ensure value is written to the >>correct register >> >> Changes from v4: >> - Add of_clk_get_parent_rate helper function into the clock framework >> - Switch to use of_clk_get_parent_rate in the iProc PLL clock driver >> >> Changes from v3: >> - Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL >>and other iProc PLLs as clock provider. These PLLs have zero cells in DT >> and >>thefore of_clk_src_simple_get should be used instead >> - Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED >>to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has >> been >>integrated into Cygnus revision B0 and has its core clock running off >>MIPI PLL Channel 2 >> - Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This >> allows >>us to derive 300 MHz V3D clock from channel 2 through the post divisor >> >> Changes from v2: >> - Re-arrange Cygnus clock/pll init functions so each init function is right >>next to its clock table >> - Removed #defines for number of clocks in Cygnus. Have the number of clocks >>automatically determined based on array size of the clock table >> >> Changes from v1: >> - Separate drivers/clk/Makefile change for drivers/clk/bcm out to a >> standalone patch >> >> Ray Jui (6): >> clk: iproc: define Broadcom iProc clock binding >> clk: iproc: add initial common clock support >> clk: Change bcm clocks build dependency >> clk: cygnus: add clock support for Broadcom Cygnus >> ARM: dts: enable clock support for Broadcom Cygnus >> clk: cygnus: remove Cygnus dummy clock binding >> >> .../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34 - >> .../bindings/clock/brcm,iproc-clocks.txt | 132 >> arch/arm/boot/dts/bcm-cygnus-clock.dtsi| 89 ++- >> drivers/clk/Makefile |2 +- >> drivers/clk/bcm/Kconfig|9 + >> drivers/clk/bcm/Makefile |2 + >> drivers/clk/bcm/clk-cygnus.c | 265 >> drivers/clk/bcm/clk-iproc-armpll.c | 282 >> drivers/clk/bcm/clk-iproc-asiu.c | 276 >> drivers/clk/bcm/clk-iproc-pll.c| 716 >> >> drivers/cl
Re: [PATCH 5/7] mtd: brcmnand: add bcma driver
Hi Hauke, On 5/20/2015 3:10 PM, Hauke Mehrtens wrote: > On 05/20/2015 08:40 PM, Brian Norris wrote: >> On Wed, May 20, 2015 at 08:39:06AM +0200, Rafał Miłecki wrote: >>> On 20 May 2015 at 02:34, Brian Norris wrote: On Sun, May 17, 2015 at 05:41:04PM +0200, Hauke Mehrtens wrote: > This driver registers at the bcma bus and drives the NAND core if it > was found on this bus. The bcma bus with this NAND core is used on the > bcm53xx and bcm47xx Northstar SoC with ARM CPU cores. The memory ranges > are automatically detected by bcma and the irq numbers read from device > tree by bcma bus driver. If you're going to use device tree for part of it (IRQs) why not the whole thing? > This is based on the iproc driver. This looks like you could probably get by with just using iproc_nand.c as-is. The main NAND core is apparently MMIO-accessible on your chips, so aren't the BCMA bits you're touching also? > > I will try this, I do not know if I have to reset or active the core > before using it, at least the vendor driver does so and I added it also. > >>> That's right, in case of SoCs cores are MMIO-accessible, however I see >>> few reasons for writing this driver as bcma based: >>> 1) MMIO access isn't available for bcma bus /hosted/ on PCIe devices. >>> By using bcma layer we write generic drivers. >> >> I strongly doubt that this NAND core is ever put on a PCIe endpoint. > > Me too and then my driver would not work, because I am forwarding the > memory directly to the driver and nothing would change the active core. > >>> 2) bcma detects cores and their MMIO addresses automatically, if we >>> are a bit lazy, it's easier to use it rather than keep hardcoding all >>> addresses >> >> Laziness is a pretty bad excuse. You already have to do 60% of the work >> by putting the IRQs and base NAND register range into the device tree. >> Finding those remaining two register addresses is not so hard. >> >>> 3) There are some dependencies in cores initialization, e.g. >>> ChipCommon core usually has to be initialized first >> >> Are you aware of any important dependencies? Isn't it safe to assume >> that the ChipCommon core would have to be initialized way before any >> peripherals? > > I think ChipCommon is less important on ARM, I do not came up with an > dependencies. > >> >>> 4) bcma provides some helpers like bcma_core_enable so we don't have >>> to duplicate it in driver code >> >> I don't see why we need to reset/re-enable the NAND core in the kernel >> at all, but if we do, this is touching the exact same registers as >> iproc_nand.c is already. So it makes sense to *share* that code, and do >> the same thing on both Cygnus and Northstar, etc. (And no, Cygnus can't >> convert to BCMA, so we can't do 100% sharing either way.) > > Will this Broadcom plugin to the AXI bus which bcma uses be removed from > all newer SoCs or just from some SoC lines? If it will not be there in > any more recent SoC then we should also go for the older arm SoCs to a > more device tree only approach. Is Cygnus related to Northstar Plus or > Northstar 2? I don't think I can give you a certain answer on this. But to my best knowledge, I don't think we have BCMA for several of our next gen ARMv8 based SoCs. A set of peripherals (e.g., NAND, PCIe RC, I2C, etc) are shared between Cygnus, NS+, and NS2. Thanks, Ray -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding
Hi Mike,
On 4/16/2015 12:20 PM, Michael Turquette wrote:
> Quoting Ray Jui (2015-04-14 12:10:35)
>> Hi Mike,
>>
>> On 4/13/2015 12:40 PM, Ray Jui wrote:
>>> Hi Mike,
>>>
>>> On 4/12/2015 11:02 PM, Michael Turquette wrote:
>>>> Quoting Ray Jui (2015-04-12 21:08:32)
>>>>>
>>>>>
>>>>> On 4/10/2015 5:12 PM, Michael Turquette wrote:
>>>>>> Quoting Ray Jui (2015-03-17 22:45:17)
>>>>>>> Document the device tree binding for Broadcom iProc architecture based
>>>>>>> clock controller
>>>>>>>
>>>>>>> Signed-off-by: Ray Jui
>>>>>>> Reviewed-by: Scott Branden
>>>>>>> ---
>>>>>>> .../bindings/clock/brcm,iproc-clocks.txt | 171
>>>>>>>
>>>>>>> 1 file changed, 171 insertions(+)
>>>>>>> create mode 100644
>>>>>>> Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>>>>
>>>>>>> diff --git
>>>>>>> a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>>>> b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>>>> new file mode 100644
>>>>>>> index 000..bf2316b
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>>>> @@ -0,0 +1,171 @@
>>>>>>> +Broadcom iProc Family Clocks
>>>>>>> +
>>>>>>> +This binding uses the common clock binding:
>>>>>>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>> +
>>>>>>> +The iProc clock controller manages clocks that are common to the iProc
>>>>>>> family.
>>>>>>> +An SoC from the iProc family may have several PPLs, e.g., ARMPLL,
>>>>>>> GENPLL,
>>>>>>> +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each
>>>>>>> PLL
>>>>>>> +comprises of several leaf clocks
>>>>>>> +
>>>>>>> +Required properties for PLLs:
>>>>>>> +- compatible:
>>>>>>> +Should have a value of the form "brcm,-". For example,
>>>>>>> GENPLL on
>>>>>>> +Cygnus has a compatible string of "brcm,cygnus-genpll"
>>>>>>> +
>>>>>>> +- #clock-cells:
>>>>>>> +Must be <0>
>>>>>>> +
>>>>>>> +- reg:
>>>>>>> +Define the base and range of the I/O address space that contain
>>>>>>> the iProc
>>>>>>> +clock control registers required for the PLL
>>>>>>> +
>>>>>>> +- clocks:
>>>>>>> +The input parent clock phandle for the PLL. For all iProc PLLs,
>>>>>>> this is an
>>>>>>> +onboard crystal with a fixed rate
>>>>>>> +
>>>>>>> +Example:
>>>>>>> +
>>>>>>> + osc: oscillator {
>>>>>>> + #clock-cells = <0>;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + clock-frequency = <2500>;
>>>>>>> + };
>>>>>>> +
>>>>>>> + genpll: genpll {
>>>>>>> + #clock-cells = <0>;
>>>>>>> + compatible = "brcm,cygnus-genpll";
>>>>>>> + reg = <0x0301d000 0x2c>,
>>>>>>> + <0x0301c020 0x4>;
>>>>>>> + clocks = <&osc>;
>>>>>>> + };
>>>>>>> +
>>>>>>> +Required properties for leaf clocks of a PLL:
>>>>>>> +
>>>>>>> +- compatible:
>>>>>>> +Should have a value of the form "brcm,--clk". For
>>>>>>> example, leaf
>>>>>>> +clocks derived from the GENPLL on Cygnus SoC have a compatible string
>>>>>>> of
>>>>>>> +"brcm,cygnus-genpll-clk"
>>>>>&
Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding
Hi Mike,
On 4/13/2015 12:40 PM, Ray Jui wrote:
> Hi Mike,
>
> On 4/12/2015 11:02 PM, Michael Turquette wrote:
>> Quoting Ray Jui (2015-04-12 21:08:32)
>>>
>>>
>>> On 4/10/2015 5:12 PM, Michael Turquette wrote:
>>>> Quoting Ray Jui (2015-03-17 22:45:17)
>>>>> Document the device tree binding for Broadcom iProc architecture based
>>>>> clock controller
>>>>>
>>>>> Signed-off-by: Ray Jui
>>>>> Reviewed-by: Scott Branden
>>>>> ---
>>>>> .../bindings/clock/brcm,iproc-clocks.txt | 171
>>>>>
>>>>> 1 file changed, 171 insertions(+)
>>>>> create mode 100644
>>>>> Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>> b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>> new file mode 100644
>>>>> index 000..bf2316b
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>> @@ -0,0 +1,171 @@
>>>>> +Broadcom iProc Family Clocks
>>>>> +
>>>>> +This binding uses the common clock binding:
>>>>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>> +
>>>>> +The iProc clock controller manages clocks that are common to the iProc
>>>>> family.
>>>>> +An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
>>>>> +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
>>>>> +comprises of several leaf clocks
>>>>> +
>>>>> +Required properties for PLLs:
>>>>> +- compatible:
>>>>> +Should have a value of the form "brcm,-". For example,
>>>>> GENPLL on
>>>>> +Cygnus has a compatible string of "brcm,cygnus-genpll"
>>>>> +
>>>>> +- #clock-cells:
>>>>> +Must be <0>
>>>>> +
>>>>> +- reg:
>>>>> +Define the base and range of the I/O address space that contain the
>>>>> iProc
>>>>> +clock control registers required for the PLL
>>>>> +
>>>>> +- clocks:
>>>>> +The input parent clock phandle for the PLL. For all iProc PLLs, this
>>>>> is an
>>>>> +onboard crystal with a fixed rate
>>>>> +
>>>>> +Example:
>>>>> +
>>>>> + osc: oscillator {
>>>>> + #clock-cells = <0>;
>>>>> + compatible = "fixed-clock";
>>>>> + clock-frequency = <2500>;
>>>>> + };
>>>>> +
>>>>> + genpll: genpll {
>>>>> + #clock-cells = <0>;
>>>>> + compatible = "brcm,cygnus-genpll";
>>>>> + reg = <0x0301d000 0x2c>,
>>>>> + <0x0301c020 0x4>;
>>>>> + clocks = <&osc>;
>>>>> + };
>>>>> +
>>>>> +Required properties for leaf clocks of a PLL:
>>>>> +
>>>>> +- compatible:
>>>>> +Should have a value of the form "brcm,--clk". For example,
>>>>> leaf
>>>>> +clocks derived from the GENPLL on Cygnus SoC have a compatible string of
>>>>> +"brcm,cygnus-genpll-clk"
>>>>> +
>>>>> +- #clock-cells:
>>>>> +Have a value of <1> since there are more than 1 leaf clock of a
>>>>> +given PLL
>>>>> +
>>>>> +- reg:
>>>>> +Define the base and range of the I/O address space that contain the
>>>>> iProc
>>>>> +clock control registers required for the PLL leaf clocks
>>>>> +
>>>>> +- clocks:
>>>>> +The input parent PLL phandle for the leaf clock
>>>>> +
>>>>> +- clock-output-names:
>>>>> +An ordered list of strings defining the names of the leaf clocks
>>>>> +
>>>>> +Example:
>>>>> +
>>>>> + genpll: genpll {
>>>>> +
Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding
Hi Mike,
On 4/12/2015 11:02 PM, Michael Turquette wrote:
> Quoting Ray Jui (2015-04-12 21:08:32)
>>
>>
>> On 4/10/2015 5:12 PM, Michael Turquette wrote:
>>> Quoting Ray Jui (2015-03-17 22:45:17)
>>>> Document the device tree binding for Broadcom iProc architecture based
>>>> clock controller
>>>>
>>>> Signed-off-by: Ray Jui
>>>> Reviewed-by: Scott Branden
>>>> ---
>>>> .../bindings/clock/brcm,iproc-clocks.txt | 171
>>>>
>>>> 1 file changed, 171 insertions(+)
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>> b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>> new file mode 100644
>>>> index 000..bf2316b
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>>> @@ -0,0 +1,171 @@
>>>> +Broadcom iProc Family Clocks
>>>> +
>>>> +This binding uses the common clock binding:
>>>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>> +
>>>> +The iProc clock controller manages clocks that are common to the iProc
>>>> family.
>>>> +An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
>>>> +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
>>>> +comprises of several leaf clocks
>>>> +
>>>> +Required properties for PLLs:
>>>> +- compatible:
>>>> +Should have a value of the form "brcm,-". For example,
>>>> GENPLL on
>>>> +Cygnus has a compatible string of "brcm,cygnus-genpll"
>>>> +
>>>> +- #clock-cells:
>>>> +Must be <0>
>>>> +
>>>> +- reg:
>>>> +Define the base and range of the I/O address space that contain the
>>>> iProc
>>>> +clock control registers required for the PLL
>>>> +
>>>> +- clocks:
>>>> +The input parent clock phandle for the PLL. For all iProc PLLs, this
>>>> is an
>>>> +onboard crystal with a fixed rate
>>>> +
>>>> +Example:
>>>> +
>>>> + osc: oscillator {
>>>> + #clock-cells = <0>;
>>>> + compatible = "fixed-clock";
>>>> + clock-frequency = <2500>;
>>>> + };
>>>> +
>>>> + genpll: genpll {
>>>> + #clock-cells = <0>;
>>>> + compatible = "brcm,cygnus-genpll";
>>>> + reg = <0x0301d000 0x2c>,
>>>> + <0x0301c020 0x4>;
>>>> + clocks = <&osc>;
>>>> + };
>>>> +
>>>> +Required properties for leaf clocks of a PLL:
>>>> +
>>>> +- compatible:
>>>> +Should have a value of the form "brcm,--clk". For example,
>>>> leaf
>>>> +clocks derived from the GENPLL on Cygnus SoC have a compatible string of
>>>> +"brcm,cygnus-genpll-clk"
>>>> +
>>>> +- #clock-cells:
>>>> +Have a value of <1> since there are more than 1 leaf clock of a
>>>> +given PLL
>>>> +
>>>> +- reg:
>>>> +Define the base and range of the I/O address space that contain the
>>>> iProc
>>>> +clock control registers required for the PLL leaf clocks
>>>> +
>>>> +- clocks:
>>>> +The input parent PLL phandle for the leaf clock
>>>> +
>>>> +- clock-output-names:
>>>> +An ordered list of strings defining the names of the leaf clocks
>>>> +
>>>> +Example:
>>>> +
>>>> + genpll: genpll {
>>>> + #clock-cells = <0>;
>>>> + compatible = "brcm,cygnus-genpll";
>>>> + reg = <0x0301d000 0x2c>,
>>>> + <0x0301c020 0x4>;
>>>> + clocks = <&osc>;
>>>> + };
>>>> +
>>>> + genpll_clks: genpll_clks {
>>>> + #clock-cells = <1>;
>>&g
Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding
On 4/10/2015 5:12 PM, Michael Turquette wrote:
> Quoting Ray Jui (2015-03-17 22:45:17)
>> Document the device tree binding for Broadcom iProc architecture based
>> clock controller
>>
>> Signed-off-by: Ray Jui
>> Reviewed-by: Scott Branden
>> ---
>> .../bindings/clock/brcm,iproc-clocks.txt | 171
>>
>> 1 file changed, 171 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>> b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>> new file mode 100644
>> index 000..bf2316b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
>> @@ -0,0 +1,171 @@
>> +Broadcom iProc Family Clocks
>> +
>> +This binding uses the common clock binding:
>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +The iProc clock controller manages clocks that are common to the iProc
>> family.
>> +An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
>> +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
>> +comprises of several leaf clocks
>> +
>> +Required properties for PLLs:
>> +- compatible:
>> +Should have a value of the form "brcm,-". For example, GENPLL
>> on
>> +Cygnus has a compatible string of "brcm,cygnus-genpll"
>> +
>> +- #clock-cells:
>> +Must be <0>
>> +
>> +- reg:
>> +Define the base and range of the I/O address space that contain the
>> iProc
>> +clock control registers required for the PLL
>> +
>> +- clocks:
>> +The input parent clock phandle for the PLL. For all iProc PLLs, this is
>> an
>> +onboard crystal with a fixed rate
>> +
>> +Example:
>> +
>> + osc: oscillator {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <2500>;
>> + };
>> +
>> + genpll: genpll {
>> + #clock-cells = <0>;
>> + compatible = "brcm,cygnus-genpll";
>> + reg = <0x0301d000 0x2c>,
>> + <0x0301c020 0x4>;
>> + clocks = <&osc>;
>> + };
>> +
>> +Required properties for leaf clocks of a PLL:
>> +
>> +- compatible:
>> +Should have a value of the form "brcm,--clk". For example,
>> leaf
>> +clocks derived from the GENPLL on Cygnus SoC have a compatible string of
>> +"brcm,cygnus-genpll-clk"
>> +
>> +- #clock-cells:
>> +Have a value of <1> since there are more than 1 leaf clock of a
>> +given PLL
>> +
>> +- reg:
>> +Define the base and range of the I/O address space that contain the
>> iProc
>> +clock control registers required for the PLL leaf clocks
>> +
>> +- clocks:
>> +The input parent PLL phandle for the leaf clock
>> +
>> +- clock-output-names:
>> +An ordered list of strings defining the names of the leaf clocks
>> +
>> +Example:
>> +
>> + genpll: genpll {
>> + #clock-cells = <0>;
>> + compatible = "brcm,cygnus-genpll";
>> + reg = <0x0301d000 0x2c>,
>> + <0x0301c020 0x4>;
>> + clocks = <&osc>;
>> + };
>> +
>> + genpll_clks: genpll_clks {
>> + #clock-cells = <1>;
>> + compatible = "brcm,cygnus-genpll-clk";
>> + reg = <0x0301d000 0x2c>;
>> + clocks = <&genpll>;
>> + clock-output-names = "axi21", "250mhz", "ihost_sys",
>> + "enet_sw", "audio_125", "can";
>> + };
>
> Hi Ray,
>
> Thanks for submitting the patch. It was nice meeting you at ELC as well.
>
> This binding doesn't conform to the norms for clock bindings. It looks
> like for each type of controllable clock node (e.g. pll, leaf clock,
> etc) you have a dts node. Looking at the above example it seems that
> those two nodes (genpll and genpll_clks) share the same register.
>
> /me checks patch #5
>
> Yup, you re-use the same register address for the *pll and *pll_clks
> nodes. I'm not
Re: [PATCH v6 0/6] Add common clock support for Broadcom iProc architecture
Hi Mike, This is the latest patch series of the Broadcom iProc clock driver that I was talking about. I believe it has addressed your previous code review comments by switching to use assigned-clocks/assigned-clock-rates for configuring PLL clock at the time of clock registration. Please have a look and let us know if this can be pulled in. Thanks, Ray On 3/17/2015 10:45 PM, Ray Jui wrote: > This patchset contains the initial common clock support for Broadcom's iProc > family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., > ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the > basic reference clock for these PLLs. Each PLL may have several leaf clocks. > One special group of clocks is the ASIU clocks, which are dervied directly > from the crystal reference clock. > > This patchset also contains the basic clock support for the Broadcom Cygnus > SoC, which implements the iProc clock architecture > > Changes from v5: > - Rebase to v4.0-rc4 > - Drop of_clk_get_parent_rate helper function from the clock framework > - Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add >standard clock set_rate and round_rate support and make use of DT > properties >"assigned-clocks" and "assigned-clock-rates" to initialize PLL to the >desired rate when registering to the clock framework > - Add SW workaround for ASIC bug on MIPI PLL to always read back the same >register following a write transaction, to ensure value is written to the >correct register > > Changes from v4: > - Add of_clk_get_parent_rate helper function into the clock framework > - Switch to use of_clk_get_parent_rate in the iProc PLL clock driver > > Changes from v3: > - Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL >and other iProc PLLs as clock provider. These PLLs have zero cells in DT > and >thefore of_clk_src_simple_get should be used instead > - Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED >to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been >integrated into Cygnus revision B0 and has its core clock running off >MIPI PLL Channel 2 > - Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This > allows >us to derive 300 MHz V3D clock from channel 2 through the post divisor > > Changes from v2: > - Re-arrange Cygnus clock/pll init functions so each init function is right >next to its clock table > - Removed #defines for number of clocks in Cygnus. Have the number of clocks >automatically determined based on array size of the clock table > > Changes from v1: > - Separate drivers/clk/Makefile change for drivers/clk/bcm out to a > standalone patch > > Ray Jui (6): > clk: iproc: define Broadcom iProc clock binding > clk: iproc: add initial common clock support > clk: Change bcm clocks build dependency > clk: cygnus: add clock support for Broadcom Cygnus > ARM: dts: enable clock support for Broadcom Cygnus > clk: cygnus: remove Cygnus dummy clock binding > > .../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34 -- > .../bindings/clock/brcm,iproc-clocks.txt | 171 +++ > arch/arm/boot/dts/bcm-cygnus-clock.dtsi| 112 - > arch/arm/boot/dts/bcm-cygnus.dtsi |2 +- > drivers/clk/Makefile |2 +- > drivers/clk/bcm/Kconfig|9 + > drivers/clk/bcm/Makefile |2 + > drivers/clk/bcm/clk-cygnus.c | 284 > drivers/clk/bcm/clk-iproc-armpll.c | 282 +++ > drivers/clk/bcm/clk-iproc-asiu.c | 275 +++ > drivers/clk/bcm/clk-iproc-clk.c| 244 ++ > drivers/clk/bcm/clk-iproc-pll.c| 490 > > drivers/clk/bcm/clk-iproc.h| 164 +++ > include/dt-bindings/clock/bcm-cygnus.h | 65 +++ > 14 files changed, 2075 insertions(+), 61 deletions(-) > delete mode 100644 > Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt > create mode 100644 > Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > create mode 100644 drivers/clk/bcm/clk-cygnus.c > create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c > create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c > create mode 100644 drivers/clk/bcm/clk-iproc-clk.c > create mode 100644 drivers/clk/bcm/clk-iproc-pll.c > create mode 100644 drivers/clk/bcm/clk-iproc.h > create mode 100644 include/dt-bindings/clock/bcm-cygnus.h > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding
Document the device tree binding for Broadcom iProc architecture based
clock controller
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
.../bindings/clock/brcm,iproc-clocks.txt | 171
1 file changed, 171 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
new file mode 100644
index 000..bf2316b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -0,0 +1,171 @@
+Broadcom iProc Family Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The iProc clock controller manages clocks that are common to the iProc family.
+An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
+LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
+comprises of several leaf clocks
+
+Required properties for PLLs:
+- compatible:
+Should have a value of the form "brcm,-". For example, GENPLL on
+Cygnus has a compatible string of "brcm,cygnus-genpll"
+
+- #clock-cells:
+Must be <0>
+
+- reg:
+Define the base and range of the I/O address space that contain the iProc
+clock control registers required for the PLL
+
+- clocks:
+The input parent clock phandle for the PLL. For all iProc PLLs, this is an
+onboard crystal with a fixed rate
+
+Example:
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ genpll: genpll {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
+ };
+
+Required properties for leaf clocks of a PLL:
+
+- compatible:
+Should have a value of the form "brcm,--clk". For example, leaf
+clocks derived from the GENPLL on Cygnus SoC have a compatible string of
+"brcm,cygnus-genpll-clk"
+
+- #clock-cells:
+Have a value of <1> since there are more than 1 leaf clock of a
+given PLL
+
+- reg:
+Define the base and range of the I/O address space that contain the iProc
+clock control registers required for the PLL leaf clocks
+
+- clocks:
+The input parent PLL phandle for the leaf clock
+
+- clock-output-names:
+An ordered list of strings defining the names of the leaf clocks
+
+Example:
+
+ genpll: genpll {
+ #clock-cells = <0>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
+ };
+
+ genpll_clks: genpll_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll-clk";
+ reg = <0x0301d000 0x2c>;
+ clocks = <&genpll>;
+ clock-output-names = "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+
+Required properties for ASIU clocks:
+
+ASIU clocks are a special case. These clocks are derived directly from the
+reference clock of the onboard crystal
+
+- compatible:
+Should have a value of the form "brcm,-asiu-clk". For example, ASIU
+clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
+
+- #clock-cells:
+Have a value of <1> since there are more than 1 ASIU clocks
+
+- reg:
+Define the base and range of the I/O address space that contain the iProc
+clock control registers required for ASIU clocks
+
+- clocks:
+The input parent clock phandle for the ASIU clock, i.e., the onboard
+crystal
+
+- clock-output-names:
+An ordered list of strings defining the names of the ASIU clocks
+
+Example:
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ asiu_clks: asiu_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x0301d048 0xc>,
+ <0x180aa024 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
+ };
+
+Cygnus
+--
+PLL and leaf clock compatible strings for Cygnus are:
+"brcm,cygnus-armpll"
+"brcm,cygnus-genpll"
+"brcm,cygnus-lcpll0"
+"brcm,cygnus-mipipll"
+"brcm,cygnus-genpll-cl
[PATCH v6 5/6] ARM: dts: enable clock support for Broadcom Cygnus
Replace current device tree dummy clocks with real clock support for
Broadcom Cygnus SoC
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 112 ---
arch/arm/boot/dts/bcm-cygnus.dtsi |2 +-
2 files changed, 88 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
index 60d8389..92aab3d 100644
--- a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -36,56 +36,118 @@ clocks {
ranges;
osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
- #clock-cells = <1>;
clock-frequency = <2500>;
};
- apb_clk: apb_clk {
- compatible = "fixed-clock";
+ /* Cygnus ARM PLL */
+ armpll: armpll {
#clock-cells = <0>;
- clock-frequency = <10>;
+ compatible = "brcm,cygnus-armpll";
+ clocks = <&osc>;
+ reg = <0x1900 0x1000>;
};
- periph_clk: periph_clk {
- compatible = "fixed-clock";
+ /* peripheral clock for system timer */
+ arm_periph_clk: arm_periph_clk {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- sdio_clk: lcpll_ch2 {
- compatible = "fixed-clock";
+ /* APB bus clock */
+ apb_clk: apb_clk {
#clock-cells = <0>;
- clock-frequency = <2>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- axi81_clk: axi81_clk {
- compatible = "fixed-clock";
+ genpll: genpll {
#clock-cells = <0>;
- clock-frequency = <1>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
};
- keypad_clk: keypad_clk {
- compatible = "fixed-clock";
+ /* various clocks running off the GENPLL */
+ genpll_clks: genpll_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll-clk";
+ reg = <0x0301d000 0x2c>;
+ clocks = <&genpll>;
+ clock-output-names = "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+
+ /* always 1/2 of the axi21 clock */
+ axi41_clk: axi41_clk {
#clock-cells = <0>;
- clock-frequency = <31806>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_clks 0>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- adc_clk: adc_clk {
- compatible = "fixed-clock";
+ /* always 1/4 of the axi21 clock */
+ axi81_clk: axi81_clk {
#clock-cells = <0>;
- clock-frequency = <1562500>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_clks 0>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- pwm_clk: pwm_clk {
- compatible = "fixed-clock";
+ lcpll0: lcpll0 {
#clock-cells = <0>;
- clock-frequency = <100>;
+ compatible = "brcm,cygnus-lcpll0";
+ reg = <0x0301d02c 0x1c>,
+ <0x0301c020 0x4>;
+ clocks = <&osc>;
};
- lcd_clk: mipipll_ch1 {
- compatible = "fixed-clock";
+ /* various clocks running off the LCPLL0 */
+ lcpll0_clks: lcpll0_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-lcpll0-clk";
+ reg = <0x0301d02c 0x1c>;
+ clocks = <&lcpll0>;
+ clock-output-names = "pcie_phy", "ddr_phy", "sdio",
+ "usb_phy", "smart_card", "ch5";
+ };
+
+ mipipll: mipipll {
#clock-cells = <0>;
-
[PATCH v6 6/6] clk: cygnus: remove Cygnus dummy clock binding
Remove old Cygnus dummy clock binding document, as it's replaced by
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
Signed-off-by: Ray Jui
---
.../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34
1 file changed, 34 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
deleted file mode 100644
index 00d26ed..000
--- a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Broadcom Cygnus Clocks
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Currently various "fixed" clocks are declared for peripheral drivers that use
-the common clock framework to reference their core clocks. Proper support of
-these clocks will be added later
-
-Device tree example:
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <1>;
- clock-frequency = <2500>;
- };
-
- apb_clk: apb_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <10>;
- };
-
- periph_clk: periph_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <5>;
- };
- };
--
1.7.9.5
--
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[PATCH v6 4/6] clk: cygnus: add clock support for Broadcom Cygnus
The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/clk/bcm/Makefile |1 +
drivers/clk/bcm/clk-cygnus.c | 284
include/dt-bindings/clock/bcm-cygnus.h | 65
3 files changed, 350 insertions(+)
create mode 100644 drivers/clk/bcm/clk-cygnus.c
create mode 100644 include/dt-bindings/clock/bcm-cygnus.h
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6926636..afcbe55 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-clk.o clk-iproc-asiu.o
+obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
new file mode 100644
index 000..fe3013b
--- /dev/null
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "clk-iproc.h"
+
+#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define asiu_div_val(o, es, hs, hw, ls, lw) \
+ { .offset = o, .en_shift = es, .high_shift = hs, \
+ .high_width = hw, .low_shift = ls, .low_width = lw }
+
+#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+ .ka_width = kaw }
+
+#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+
+#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+
+static void __init cygnus_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
+
+static const struct iproc_pll_ctrl genpll = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC,
+ .aon = aon_val(0x0, 2, 1, 0),
+ .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .ndiv_int = reg_val(0x10, 20, 10),
+ .ndiv_frac = reg_val(0x10, 0, 20),
+ .pdiv = reg_val(0x14, 0, 4),
+ .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
+ .status = reg_val(0x28, 12, 1),
+};
+
+static void __init cygnus_genpll_init(struct device_node *node)
+{
+ iproc_pll_setup(node, &genpll, NULL, 0);
+}
+CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_init);
+
+static const struct iproc_pll_ctrl lcpll0 = {
+ .flags = IPROC_CLK_AON,
+ .aon = aon_val(0x0, 2, 5, 4),
+ .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
+ .ndiv_int = reg_val(0x4, 16, 10),
+ .pdiv = reg_val(0x4, 26, 4),
+ .vco_ctrl = vco_ctrl_val(0x10, 0x14),
+ .status = reg_val(0x18, 12, 1),
+};
+
+static void __init cygnus_lcpll0_init(struct device_node *node)
+{
+ iproc_pll_setup(node, &lcpll0, NULL, 0);
+}
+CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_init);
+
+/*
+ * MIPI PLL VCO frequency parameter table
+ */
+static const struct iproc_pll_vco_freq_param mipipll_vco_params[] = {
+ /* rate (Hz) ndiv_int ndiv_frac pdiv */
+ { 75000UL, 30, 0,1 },
+ { 10UL, 40, 0,1 },
+ { 135000ul, 54, 0,1 },
+ { 20UL, 80, 0,1 },
+ { 21UL, 84, 0,1 },
+ { 225000UL, 90, 0,1 },
+ { 25UL, 100,0,1 },
+ { 27UL, 54, 0,0 },
+ { 297500UL, 119,0,1 },
+ { 31UL, 124,0,1 },
+ { 315000UL, 126,0,1 },
+};
+
+static const struct iproc_pll_ctrl mipipll = {
+
[PATCH v6 3/6] clk: Change bcm clocks build dependency
The clock code under drivers/clk/bcm now contains code for both the Broadcom mobile SoCs and the iProc SoCs. Change the the makefile dependency to be under config flag CONFIG_ARCH_BCM that's enabled for both families of SoCs Signed-off-by: Ray Jui --- drivers/clk/Makefile |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d478ceb..1dde3c8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_WM831X)+= clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/ +obj-$(CONFIG_ARCH_BCM) += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ obj-$(CONFIG_ARCH_HIP04) += hisilicon/ -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 0/6] Add common clock support for Broadcom iProc architecture
This patchset contains the initial common clock support for Broadcom's iProc family of SoCs. The iProc clock architecture comprises of various PLLs, e.g., ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the basic reference clock for these PLLs. Each PLL may have several leaf clocks. One special group of clocks is the ASIU clocks, which are dervied directly from the crystal reference clock. This patchset also contains the basic clock support for the Broadcom Cygnus SoC, which implements the iProc clock architecture Changes from v5: - Rebase to v4.0-rc4 - Drop of_clk_get_parent_rate helper function from the clock framework - Get rid of custom "clock-frequency" support in iProc PLL code. Instead, add standard clock set_rate and round_rate support and make use of DT properties "assigned-clocks" and "assigned-clock-rates" to initialize PLL to the desired rate when registering to the clock framework - Add SW workaround for ASIC bug on MIPI PLL to always read back the same register following a write transaction, to ensure value is written to the correct register Changes from v4: - Add of_clk_get_parent_rate helper function into the clock framework - Switch to use of_clk_get_parent_rate in the iProc PLL clock driver Changes from v3: - Fix incorrect use of passing in of_clk_src_onecell_get when adding ARM PLL and other iProc PLLs as clock provider. These PLLs have zero cells in DT and thefore of_clk_src_simple_get should be used instead - Rename Cygnus MIPI PLL Channel 2 clock from BCM_CYGNUS_MIPIPLL_CH2_UNUSED to BCM_CYGNUS_MIPIPLL_CH2_V3D, since a 3D graphic rendering engine has been integrated into Cygnus revision B0 and has its core clock running off MIPI PLL Channel 2 - Changed default MIPI PLL VCO frequency from 1.75 GHz to 2.1 GHz. This allows us to derive 300 MHz V3D clock from channel 2 through the post divisor Changes from v2: - Re-arrange Cygnus clock/pll init functions so each init function is right next to its clock table - Removed #defines for number of clocks in Cygnus. Have the number of clocks automatically determined based on array size of the clock table Changes from v1: - Separate drivers/clk/Makefile change for drivers/clk/bcm out to a standalone patch Ray Jui (6): clk: iproc: define Broadcom iProc clock binding clk: iproc: add initial common clock support clk: Change bcm clocks build dependency clk: cygnus: add clock support for Broadcom Cygnus ARM: dts: enable clock support for Broadcom Cygnus clk: cygnus: remove Cygnus dummy clock binding .../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34 -- .../bindings/clock/brcm,iproc-clocks.txt | 171 +++ arch/arm/boot/dts/bcm-cygnus-clock.dtsi| 112 - arch/arm/boot/dts/bcm-cygnus.dtsi |2 +- drivers/clk/Makefile |2 +- drivers/clk/bcm/Kconfig|9 + drivers/clk/bcm/Makefile |2 + drivers/clk/bcm/clk-cygnus.c | 284 drivers/clk/bcm/clk-iproc-armpll.c | 282 +++ drivers/clk/bcm/clk-iproc-asiu.c | 275 +++ drivers/clk/bcm/clk-iproc-clk.c| 244 ++ drivers/clk/bcm/clk-iproc-pll.c| 490 drivers/clk/bcm/clk-iproc.h| 164 +++ include/dt-bindings/clock/bcm-cygnus.h | 65 +++ 14 files changed, 2075 insertions(+), 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt create mode 100644 drivers/clk/bcm/clk-cygnus.c create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c create mode 100644 drivers/clk/bcm/clk-iproc-clk.c create mode 100644 drivers/clk/bcm/clk-iproc-pll.c create mode 100644 drivers/clk/bcm/clk-iproc.h create mode 100644 include/dt-bindings/clock/bcm-cygnus.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 2/6] clk: iproc: add initial common clock support
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions
Derived from code originally provided by Jonathan Richardson
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/clk/bcm/Kconfig|9 +
drivers/clk/bcm/Makefile |1 +
drivers/clk/bcm/clk-iproc-armpll.c | 282 +
drivers/clk/bcm/clk-iproc-asiu.c | 275
drivers/clk/bcm/clk-iproc-clk.c| 244 ++
drivers/clk/bcm/clk-iproc-pll.c| 490
drivers/clk/bcm/clk-iproc.h| 164
7 files changed, 1465 insertions(+)
create mode 100644 drivers/clk/bcm/clk-iproc-armpll.c
create mode 100644 drivers/clk/bcm/clk-iproc-asiu.c
create mode 100644 drivers/clk/bcm/clk-iproc-clk.c
create mode 100644 drivers/clk/bcm/clk-iproc-pll.c
create mode 100644 drivers/clk/bcm/clk-iproc.h
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 75506e5..131a3af 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -7,3 +7,12 @@ config CLK_BCM_KONA
Enable common clock framework support for Broadcom SoCs
using "Kona" style clock control units, including those
in the BCM281xx and BCM21664 families.
+
+config COMMON_CLK_IPROC
+ bool "Broadcom iProc clock support"
+ depends on ARCH_BCM_IPROC
+ depends on COMMON_CLK
+ default ARCH_BCM_IPROC
+ help
+ Enable common clock framework support for Broadcom SoCs
+ based on the "iProc" architecture
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6297d05..6926636 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-clk.o clk-iproc-asiu.o
diff --git a/drivers/clk/bcm/clk-iproc-armpll.c
b/drivers/clk/bcm/clk-iproc-armpll.c
new file mode 100644
index 000..965cd4e
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc-armpll.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPROC_CLK_MAX_FREQ_POLICY0x3
+#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
+#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
+#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
+
+#define IPROC_CLK_PLLARMA_OFFSET 0xc00
+#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
+#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
+#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
+#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
+#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
+
+#define IPROC_CLK_PLLARMB_OFFSET 0xc04
+#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xf
+
+#define IPROC_CLK_PLLARMC_OFFSET 0xc08
+#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT8
+#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
+
+#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
+#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
+
+#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
+#define IPROC_CLK_PLLARM_SW_CTL_SHIFT29
+#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
+#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK0xff
+#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xf
+
+#define IPROC_CLK_ARM_DIV_OFFSET 0xe00
+#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK0xf
+
+#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
+#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
+#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
+
+enum iproc_arm_pll_fid {
+ ARM_PLL_FID_CRYSTAL_CLK = 0,
+ ARM_PLL_FID_SYS_CLK = 2,
+ ARM_PLL_FID_CH0_SLOW_CLK = 6,
+ ARM
[PATCH v7 4/4] ARM: dts: enable PCIe support for Cygnus
Add PCIe device nodes in bcm-cygnus.dtsi but keep them disabled there.
Only enable them for bcm958300k where PCIe interfaces are populated
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 42 +
arch/arm/boot/dts/bcm958300k.dts |8 +++
2 files changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index ff5fb6a..ee0c6e4 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -90,6 +90,48 @@
status = "disabled";
};
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18012000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x2800 0 0x0001
+ 0x8200 0 0x2000 0x2000 0 0x0400>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18013000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x4800 0 0x0001
+ 0x8200 0 0x4000 0x4000 0 0x0400>;
+
+ status = "disabled";
+ };
+
uart0: serial@1802 {
compatible = "snps,dw-apb-uart";
reg = <0x1802 0x100>;
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index f1bb36f..c9eb856 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -47,6 +47,14 @@
bootargs = "console=ttyS0,115200";
};
+ pcie0: pcie@18012000 {
+ status = "okay";
+ };
+
+ pcie1: pcie@18013000 {
+ status = "okay";
+ };
+
uart3: serial@18023000 {
status = "okay";
};
--
1.7.9.5
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[PATCH v7 1/4] PCI: Export symbols of PCI functions
Export symbols of the following PCI functions so they can be referenced
by a PCI driver compiled as a kernel loadable module:
pci_common_swizzle
pci_create_root_bus
pci_stop_root_bus
pci_remove_root_bus
pci_assign_unassigned_bus_resources
pci_fixup_irqs
Signed-off-by: Ray Jui
---
drivers/pci/pci.c |1 +
drivers/pci/probe.c |1 +
drivers/pci/remove.c|2 ++
drivers/pci/setup-bus.c |1 +
drivers/pci/setup-irq.c |1 +
5 files changed, 6 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 81f06e8..14e7f3c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2492,6 +2492,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
*pinp = pin;
return PCI_SLOT(dev->devfn);
}
+EXPORT_SYMBOL_GPL(pci_common_swizzle);
/**
* pci_release_region - Release a PCI bar
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 8d2f400..f13a78a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1993,6 +1993,7 @@ err_out:
kfree(b);
return NULL;
}
+EXPORT_SYMBOL_GPL(pci_create_root_bus);
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
{
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 8bd76c9..8a280e9 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -139,6 +139,7 @@ void pci_stop_root_bus(struct pci_bus *bus)
/* stop the host bridge */
device_release_driver(&host_bridge->dev);
}
+EXPORT_SYMBOL_GPL(pci_stop_root_bus);
void pci_remove_root_bus(struct pci_bus *bus)
{
@@ -158,3 +159,4 @@ void pci_remove_root_bus(struct pci_bus *bus)
/* remove the host bridge */
device_unregister(&host_bridge->dev);
}
+EXPORT_SYMBOL_GPL(pci_remove_root_bus);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index e3e17f3..8169597 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1750,3 +1750,4 @@ void pci_assign_unassigned_bus_resources(struct pci_bus
*bus)
__pci_bus_assign_resources(bus, &add_list, NULL);
BUG_ON(!list_empty(&add_list));
}
+EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index 4e2d595..95c225b 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -65,3 +65,4 @@ void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
for_each_pci_dev(dev)
pdev_fixup_irq(dev, swizzle, map_irq);
}
+EXPORT_SYMBOL_GPL(pci_fixup_irqs);
--
1.7.9.5
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[PATCH v7 3/4] pci: iproc: Add Broadcom iProc PCIe support
This adds the support for Broadcom iProc PCIe controller
pcie-iproc.c servers as the common core driver, and front-end bus
interface needs to be added to support different bus interfaces
pcie-iproc-pltfm.c contains the support for the platform bus interface
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/Kconfig| 17 +++
drivers/pci/host/Makefile |2 +
drivers/pci/host/pcie-iproc-pltfm.c | 108 ++
drivers/pci/host/pcie-iproc.c | 268 +++
drivers/pci/host/pcie-iproc.h | 42 ++
5 files changed, 437 insertions(+)
create mode 100644 drivers/pci/host/pcie-iproc-pltfm.c
create mode 100644 drivers/pci/host/pcie-iproc.c
create mode 100644 drivers/pci/host/pcie-iproc.h
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 7b892a9..feccd0d 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -106,4 +106,21 @@ config PCI_VERSATILE
bool "ARM Versatile PB PCI controller"
depends on ARCH_VERSATILE
+config PCIE_IPROC
+ tristate "Broadcom iProc PCIe controller"
+ help
+ This enables the iProc PCIe core controller support for Broadcom's
+ iProc family of SoCs. An appropriate bus interface driver also needs
+ to be enabled
+
+config PCIE_IPROC_PLTFM
+ tristate "Broadcom iProc PCIe platform bus driver"
+ depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
+ depends on OF
+ select PCIE_IPROC
+ default ARCH_BCM_IPROC
+ help
+ Say Y here if you want to use the Broadcom iProc PCIe controller
+ through the generic platform bus interface
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index e61d91c..2e02d20 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
+obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
+obj-$(CONFIG_PCIE_IPROC_PLTFM) += pcie-iproc-pltfm.o
diff --git a/drivers/pci/host/pcie-iproc-pltfm.c
b/drivers/pci/host/pcie-iproc-pltfm.c
new file mode 100644
index 000..afad6c2
--- /dev/null
+++ b/drivers/pci/host/pcie-iproc-pltfm.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-iproc.h"
+
+static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
+{
+ struct iproc_pcie *pcie;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource reg;
+ resource_size_t iobase = 0;
+ LIST_HEAD(res);
+ int ret;
+
+ pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pcie);
+
+ ret = of_address_to_resource(np, 0, ®);
+ if (ret < 0) {
+ dev_err(pcie->dev, "unable to obtain controller resources\n");
+ return ret;
+ }
+
+ pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
+ if (!pcie->base) {
+ dev_err(pcie->dev, "unable to map controller registers\n");
+ return -ENOMEM;
+ }
+
+ /* PHY use is optional */
+ pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
+ if (IS_ERR(pcie->phy)) {
+ if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ pcie->phy = NULL;
+ }
+
+ ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
+ if (ret) {
+ dev_err(pcie->dev,
+ "unable to get PCI host bridge resources\n");
+ return ret;
+ }
+
+ pcie->resources = &res;
+
+ ret = iproc_pcie_setup(pcie);
+ if (ret) {
+ dev_err(pcie->dev, "PCIe controller setup failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
+{
+ struct iproc_pcie *pcie = platform_get_drvd
[PATCH v7 0/4] pci: iproc: Add Broadcom iProc PCIe support
This patch series adds the support for Broadcom iProc PCIe controller pcie-iproc.c servers as the common core driver, and front-end bus interface needs to be added to support different bus interfaces pcie-iproc-pltfm.c contains the support for the platform bus interface Changes from v6: - Fix print formatting - Fix section mismatch warning by removing __init from the probe function - Fix Kconfig to force it only compiling for ARM based platforms Changes from v5: - Sync code base to v4.0-rc2 - Change export symbols of common PCI functions to GPL only - Add comment to describe how configuration register access are protected at the higher layer through 'pci_lock' - Use generic PCI functions for configuration register access and implement 'map_bus' callback to support it - Move 'pci_fixup_irqs' to before devices are added to the bus - Remove 'extern' from function prototype declared in the header Changes from v4: - iProc PCIe driver module support was not included in patch series v4. This patch series (v5) fixes it Changes from v3: - Export symbols of several PCI functions so they can be used by drivers compiled as kernel module - Add additional support to the Broadcom iProc PCIe driver so it can be installed/uninstalled as kernel loadable module Changes from v2: - Major rework of the PCIe driver to factor out common generic code from front-end bus interface. Support for generic platform bus interface is also added - Adapt to several new PCI APIs that have been introduced lately Changes from v1: - Add standard PCI interrupt DT properties "#interrupt-cells", "interrupt-map-mask" and "interrupt-map" so legacy INTx interrupts can be supported by using standard PCI OF IRQ parsing function - Get rid of custom IRQ mapping function in the driver. Use of_irq_parse_and_map_pci instead Ray Jui (4): PCI: Export symbols of PCI functions pci: iProc: define iProc PCIe platform bus binding pci: iproc: Add Broadcom iProc PCIe support ARM: dts: enable PCIe support for Cygnus .../devicetree/bindings/pci/brcm,iproc-pcie.txt| 63 + arch/arm/boot/dts/bcm-cygnus.dtsi | 42 +++ arch/arm/boot/dts/bcm958300k.dts |8 + drivers/pci/host/Kconfig | 17 ++ drivers/pci/host/Makefile |2 + drivers/pci/host/pcie-iproc-pltfm.c| 108 drivers/pci/host/pcie-iproc.c | 268 drivers/pci/host/pcie-iproc.h | 42 +++ drivers/pci/pci.c |1 + drivers/pci/probe.c|1 + drivers/pci/remove.c |2 + drivers/pci/setup-bus.c|1 + drivers/pci/setup-irq.c|1 + 13 files changed, 556 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt create mode 100644 drivers/pci/host/pcie-iproc-pltfm.c create mode 100644 drivers/pci/host/pcie-iproc.c create mode 100644 drivers/pci/host/pcie-iproc.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/4] pci: iProc: define iProc PCIe platform bus binding
Document the Broadcom iProc PCIe platform interface device tree binding
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
.../devicetree/bindings/pci/brcm,iproc-pcie.txt| 63
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
new file mode 100644
index 000..f7ce50e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
@@ -0,0 +1,63 @@
+* Broadcom iProc PCIe controller with the platform bus interface
+
+Required properties:
+- compatible: Must be "brcm,iproc-pcie"
+- reg: base address and length of the PCIe controller I/O register space
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+ mapping of the PCIe interface to interrupt numbers
+- linux,pci-domain: PCI domain ID. Should be unique for each host controller
+- bus-range: PCI bus numbers covered
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+
+Optional properties:
+- phys: phandle of the PCIe PHY device
+- phy-names: must be "pcie-phy"
+
+Example:
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18012000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x2800 0 0x0001
+ 0x8200 0 0x2000 0x2000 0 0x0400>;
+
+ phys = <&phy 0 5>;
+ phy-names = "pcie-phy";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18013000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x4800 0 0x0001
+ 0x8200 0 0x4000 0x4000 0 0x0400>;
+
+ phys = <&phy 1 6>;
+ phy-names = "pcie-phy";
+ };
--
1.7.9.5
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Re: [PATCH v6 3/4] pci: iproc: Add Broadcom iProc PCIe support
On 3/12/2015 2:08 PM, Bjorn Helgaas wrote:
> On Wed, Mar 11, 2015 at 11:06:08AM -0700, Ray Jui wrote:
>> This adds the support for Broadcom iProc PCIe controller
>>
>> pcie-iproc.c servers as the common core driver, and front-end bus
>> interface needs to be added to support different bus interfaces
>>
>> pcie-iproc-pltfm.c contains the support for the platform bus interface
>>
>> Signed-off-by: Ray Jui
>> Reviewed-by: Scott Branden
>> ...
>
>> +static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus
>> *bus)
>> +{
>> +u8 hdr_type;
>> +u32 link_ctrl;
>> +u16 pos, link_status;
>> +int link_is_active = 0;
>> +
>> +/* make sure we are not in EP mode */
>> +pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
>> +if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
>> +dev_err(pcie->dev, "in EP mode, hdr=0x08%x\n", hdr_type);
>
> "0x08%x" doesn't look right. I changed it to "%#02x"; is that what you
> intended?
>
You are right. Will fix it along with the Kconfig fix (so it won't get
compiled for non-ARM platforms). I'll submit v7?
Thanks,
Ray
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Re: [PATCH v6 6/8] pinctrl: cygnus: add gpio/pinconf driver
Hi Linus,
On 3/10/2015 3:20 AM, Linus Walleij wrote:
> On Mon, Mar 9, 2015 at 9:45 PM, Ray Jui wrote:
>
>> This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
>> that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
>> controller, the chipCommonG GPIO controller, and the always-on GPIO
>> controller. Basic PINCONF configurations such as bias pull up/down, and
>> drive strength are also supported in this driver.
>>
>> Pins from the ASIU GPIO controller can be individually muxed to GPIO
>> function, through interaction with the Cygnus IOMUX controller
>>
>> Signed-off-by: Ray Jui
>> Reviewed-by: Scott Branden
>> Tested-by: Dmitry Torokhov
>
> Patch applied! But please look at this:
>
>> +#include
>
> Doesn't just #include work?
>
I think I need linux/gpio.h for gpiochip_add_pin_range and some related
APIs.
>> +static int __init cygnus_gpio_init(void)
>> +{
>> + return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe);
>> +}
>> +arch_initcall_sync(cygnus_gpio_init);
>
> arch_initcall_sync() is a bit brutal.
>
> Can you please investigate if you can have this as a normal device_initcall()
> utilizing deferred probe if necessary?
>
> Follow-up patches accepted!
>
I understand. Further investigation is needed and this may take a while,
since a lot of our Cygnus drivers depend on GPIO and regulators (and all
need to be converted to check against deferred probe errors). If
possible, I'll definitely fix this.
> Yours,
> Linus Walleij
>
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[PATCH v6 2/4] pci: iProc: define iProc PCIe platform bus binding
Document the Broadcom iProc PCIe platform interface device tree binding
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
.../devicetree/bindings/pci/brcm,iproc-pcie.txt| 63
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
new file mode 100644
index 000..f7ce50e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
@@ -0,0 +1,63 @@
+* Broadcom iProc PCIe controller with the platform bus interface
+
+Required properties:
+- compatible: Must be "brcm,iproc-pcie"
+- reg: base address and length of the PCIe controller I/O register space
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+ mapping of the PCIe interface to interrupt numbers
+- linux,pci-domain: PCI domain ID. Should be unique for each host controller
+- bus-range: PCI bus numbers covered
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+
+Optional properties:
+- phys: phandle of the PCIe PHY device
+- phy-names: must be "pcie-phy"
+
+Example:
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18012000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x2800 0 0x0001
+ 0x8200 0 0x2000 0x2000 0 0x0400>;
+
+ phys = <&phy 0 5>;
+ phy-names = "pcie-phy";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18013000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x4800 0 0x0001
+ 0x8200 0 0x4000 0x4000 0 0x0400>;
+
+ phys = <&phy 1 6>;
+ phy-names = "pcie-phy";
+ };
--
1.7.9.5
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[PATCH v6 3/4] pci: iproc: Add Broadcom iProc PCIe support
This adds the support for Broadcom iProc PCIe controller
pcie-iproc.c servers as the common core driver, and front-end bus
interface needs to be added to support different bus interfaces
pcie-iproc-pltfm.c contains the support for the platform bus interface
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/pci/host/Kconfig| 17 +++
drivers/pci/host/Makefile |2 +
drivers/pci/host/pcie-iproc-pltfm.c | 108 ++
drivers/pci/host/pcie-iproc.c | 268 +++
drivers/pci/host/pcie-iproc.h | 42 ++
5 files changed, 437 insertions(+)
create mode 100644 drivers/pci/host/pcie-iproc-pltfm.c
create mode 100644 drivers/pci/host/pcie-iproc.c
create mode 100644 drivers/pci/host/pcie-iproc.h
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 7b892a9..f4d9c90 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -106,4 +106,21 @@ config PCI_VERSATILE
bool "ARM Versatile PB PCI controller"
depends on ARCH_VERSATILE
+config PCIE_IPROC
+ tristate "Broadcom iProc PCIe controller"
+ help
+ This enables the iProc PCIe core controller support for Broadcom's
+ iProc family of SoCs. An appropriate bus interface driver also needs
+ to be enabled
+
+config PCIE_IPROC_PLTFM
+ tristate "Broadcom iProc PCIe platform bus driver"
+ depends on ARCH_BCM_IPROC || COMPILE_TEST
+ depends on OF
+ select PCIE_IPROC
+ default ARCH_BCM_IPROC
+ help
+ Say Y here if you want to use the Broadcom iProc PCIe controller
+ through the generic platform bus interface
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index e61d91c..2e02d20 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
+obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
+obj-$(CONFIG_PCIE_IPROC_PLTFM) += pcie-iproc-pltfm.o
diff --git a/drivers/pci/host/pcie-iproc-pltfm.c
b/drivers/pci/host/pcie-iproc-pltfm.c
new file mode 100644
index 000..af935ea
--- /dev/null
+++ b/drivers/pci/host/pcie-iproc-pltfm.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-iproc.h"
+
+static int __init iproc_pcie_pltfm_probe(struct platform_device *pdev)
+{
+ struct iproc_pcie *pcie;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource reg;
+ resource_size_t iobase = 0;
+ LIST_HEAD(res);
+ int ret;
+
+ pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pcie);
+
+ ret = of_address_to_resource(np, 0, ®);
+ if (ret < 0) {
+ dev_err(pcie->dev, "unable to obtain controller resources\n");
+ return ret;
+ }
+
+ pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
+ if (!pcie->base) {
+ dev_err(pcie->dev, "unable to map controller registers\n");
+ return -ENOMEM;
+ }
+
+ /* PHY use is optional */
+ pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
+ if (IS_ERR(pcie->phy)) {
+ if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ pcie->phy = NULL;
+ }
+
+ ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
+ if (ret) {
+ dev_err(pcie->dev,
+ "unable to get PCI host bridge resources\n");
+ return ret;
+ }
+
+ pcie->resources = &res;
+
+ ret = iproc_pcie_setup(pcie);
+ if (ret) {
+ dev_err(pcie->dev, "PCIe controller setup failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
+{
+ struct iproc_pcie *pcie = platform_get_drvdata(pdev
[PATCH v6 1/4] PCI: Export symbols of PCI functions
Export symbols of the following PCI functions so they can be referenced
by a PCI driver compiled as a kernel loadable module:
pci_common_swizzle
pci_create_root_bus
pci_stop_root_bus
pci_remove_root_bus
pci_assign_unassigned_bus_resources
pci_fixup_irqs
Signed-off-by: Ray Jui
---
drivers/pci/pci.c |1 +
drivers/pci/probe.c |1 +
drivers/pci/remove.c|2 ++
drivers/pci/setup-bus.c |1 +
drivers/pci/setup-irq.c |1 +
5 files changed, 6 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 81f06e8..14e7f3c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2492,6 +2492,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
*pinp = pin;
return PCI_SLOT(dev->devfn);
}
+EXPORT_SYMBOL_GPL(pci_common_swizzle);
/**
* pci_release_region - Release a PCI bar
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 8d2f400..f13a78a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1993,6 +1993,7 @@ err_out:
kfree(b);
return NULL;
}
+EXPORT_SYMBOL_GPL(pci_create_root_bus);
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
{
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 8bd76c9..8a280e9 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -139,6 +139,7 @@ void pci_stop_root_bus(struct pci_bus *bus)
/* stop the host bridge */
device_release_driver(&host_bridge->dev);
}
+EXPORT_SYMBOL_GPL(pci_stop_root_bus);
void pci_remove_root_bus(struct pci_bus *bus)
{
@@ -158,3 +159,4 @@ void pci_remove_root_bus(struct pci_bus *bus)
/* remove the host bridge */
device_unregister(&host_bridge->dev);
}
+EXPORT_SYMBOL_GPL(pci_remove_root_bus);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index e3e17f3..8169597 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1750,3 +1750,4 @@ void pci_assign_unassigned_bus_resources(struct pci_bus
*bus)
__pci_bus_assign_resources(bus, &add_list, NULL);
BUG_ON(!list_empty(&add_list));
}
+EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index 4e2d595..95c225b 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -65,3 +65,4 @@ void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
for_each_pci_dev(dev)
pdev_fixup_irq(dev, swizzle, map_irq);
}
+EXPORT_SYMBOL_GPL(pci_fixup_irqs);
--
1.7.9.5
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[PATCH v6 4/4] ARM: dts: enable PCIe support for Cygnus
Add PCIe device nodes in bcm-cygnus.dtsi but keep them disabled there.
Only enable them for bcm958300k where PCIe interfaces are populated
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 42 +
arch/arm/boot/dts/bcm958300k.dts |8 +++
2 files changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index ff5fb6a..ee0c6e4 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -90,6 +90,48 @@
status = "disabled";
};
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18012000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x2800 0 0x0001
+ 0x8200 0 0x2000 0x2000 0 0x0400>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x18013000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x4800 0 0x0001
+ 0x8200 0 0x4000 0x4000 0 0x0400>;
+
+ status = "disabled";
+ };
+
uart0: serial@1802 {
compatible = "snps,dw-apb-uart";
reg = <0x1802 0x100>;
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index f1bb36f..c9eb856 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -47,6 +47,14 @@
bootargs = "console=ttyS0,115200";
};
+ pcie0: pcie@18012000 {
+ status = "okay";
+ };
+
+ pcie1: pcie@18013000 {
+ status = "okay";
+ };
+
uart3: serial@18023000 {
status = "okay";
};
--
1.7.9.5
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[PATCH v6 0/4] pci: iproc: Add Broadcom iProc PCIe support
This patch series adds the support for Broadcom iProc PCIe controller pcie-iproc.c servers as the common core driver, and front-end bus interface needs to be added to support different bus interfaces pcie-iproc-pltfm.c contains the support for the platform bus interface Changes from v5: - Sync code base to v4.0-rc2 - Change export symbols of common PCI functions to GPL only - Add comment to describe how configuration register access are protected at the higher layer through 'pci_lock' - Use generic PCI functions for configuration register access and implement 'map_bus' callback to support it - Move 'pci_fixup_irqs' to before devices are added to the bus - Remove 'extern' from function prototype declared in the header Changes from v4: - iProc PCIe driver module support was not included in patch series v4. This patch series (v5) fixes it Changes from v3: - Export symbols of several PCI functions so they can be used by drivers compiled as kernel module - Add additional support to the Broadcom iProc PCIe driver so it can be installed/uninstalled as kernel loadable module Changes from v2: - Major rework of the PCIe driver to factor out common generic code from front-end bus interface. Support for generic platform bus interface is also added - Adapt to several new PCI APIs that have been introduced lately Changes from v1: - Add standard PCI interrupt DT properties "#interrupt-cells", "interrupt-map-mask" and "interrupt-map" so legacy INTx interrupts can be supported by using standard PCI OF IRQ parsing function - Get rid of custom IRQ mapping function in the driver. Use of_irq_parse_and_map_pci instead Ray Jui (4): PCI: Export symbols of PCI functions pci: iProc: define iProc PCIe platform bus binding pci: iproc: Add Broadcom iProc PCIe support ARM: dts: enable PCIe support for Cygnus .../devicetree/bindings/pci/brcm,iproc-pcie.txt| 63 + arch/arm/boot/dts/bcm-cygnus.dtsi | 42 +++ arch/arm/boot/dts/bcm958300k.dts |8 + drivers/pci/host/Kconfig | 17 ++ drivers/pci/host/Makefile |2 + drivers/pci/host/pcie-iproc-pltfm.c| 108 drivers/pci/host/pcie-iproc.c | 268 drivers/pci/host/pcie-iproc.h | 42 +++ drivers/pci/pci.c |1 + drivers/pci/probe.c|1 + drivers/pci/remove.c |2 + drivers/pci/setup-bus.c|1 + drivers/pci/setup-irq.c|1 + 13 files changed, 556 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt create mode 100644 drivers/pci/host/pcie-iproc-pltfm.c create mode 100644 drivers/pci/host/pcie-iproc.c create mode 100644 drivers/pci/host/pcie-iproc.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
