Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 03/12/15 11:52, Brian Norris wrote:
> Hi,
>
> On Thu, Dec 03, 2015 at 11:38:14AM +0530, Roger Quadros wrote:
>> On 03/12/15 10:39, Brian Norris wrote:
>>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>>>> We do a couple of things in this series which result in
>>>> cleaner device tree implementation, faster perfomance and
>>>> multi-platform support. As an added bonus we get new GPI/Interrupt pins
>>>> for use in the system.
>>>>
>>>> - Establish a custom interface between NAND and GPMC driver. This is
>>>> needed because all of the NAND registers sit in the GPMC register space.
>>>> Some bits like NAND IRQ are even shared with GPMC.
>>>>
>>>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ
>>>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver.
>>>> This causes performance increase when using prefetch-irq mode.
>>>> 30% increase in read, 17% increase in write in prefetch-irq mode.
>>>>
>>>> - Clean up device tree support so that omap-gpmc IP and the omap2 NAND
>>>> driver can be used on non-OMAP platforms. e.g. Keystone.
>>>>
>>>> - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain
>>>> 2 to 4 of these and most of them would be unused otherwise. It also
>>>> allows a cleaner implementation of NAND Ready pin status for the NAND
>>>> driver.
>>>>
>>>> - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver.
>>>>
>>>> This series is available at
>>>> g...@github.com:rogerq/linux.git
>>>> in branch
>>>> for-v4.4/gpmc-v3
>>>>
>>>> cheers,
>>>> -roger
>>>>
>>>> Changelog:
>>>> v3:
>>>> -Fixed and tested NAND using legacy boot on omap3-beagle.
>>>> -Support rising and falling edge interrupts on WAITpins.
>>>> -Update DT node of all gpmc users.
>>>
>>> The MTD stuff looks mostly good to me know. I've made all my comments
>>> for now, but I'm not sure how you're going to end up rebasing/splitting
>>> and what you're going to do with the irqchip removal, so I'll refrain
>>> from ack's for now. Hopefully I can either ack or merge v4.
>>
>> I'll retain the irqchip model for now and send a v4 with all comments
>> addressed and better subsystem wise patch split.
>>
>>>
>>> I brought it up on one other patch, but it's not really clear to me what
>>> the split is on board file vs. device tree handling, since you seem to
>>> have a combination of both (i.e., platform data that passes along device
>>> nodes). What's the plan on that?
>>
>> Platform data no longer passes device nodes. We're either true device tree
>> or plain legacy. The deprecated fields are no longer used once the series is
>> applied.
>
> Well, they're still sorta used (you assign info->of_node =
> pdata->of_node, for instance). As dicussed in the other thread, I think
> we can avoid the deprecation part and just kill the fields though, and
> that would make things clearer.
>
>>> And of course, there's the question of how exactly to merge this, given
>>> the:
>>> (1) conflicts already existing in the MTD dev tree
>>
>> I'll rebase the series on top of MTD dev tree.
>
> OK. FWIW, we so far only need to base them on commit a61ae81a1907 ("mtd:
> nand: drop unnecessary partition parser data"). Maybe when queueing up a
> branch, that'd be the best starting point for Tony, so he doesn't need
> to have all of MTD's stuff in his tree too? I can set up a signed tag or
> something, if that would be helpful.
>
> But for sending patches, the latest l2-mtd.git is fine too.
>
>>> (2) this touches several trees, often in the same patch and
>>
>> I'll try my best to split the patches but not sure if this could be 100%
>> clean split without functional breakage.
>>
>>> (3) even if the patches were split out a little better into MTD and
>>> non-MTD stuff, I think there would still be dependencies such that
>>> we'd need at least 1 (probably 2) cross merges to get it all
>>> straight
>>
>> That is correct.
>> Is it OK if functionality breaks if for example only MTD changes are
>> considered?
>
> I think I may have misunderstood the branch proposal. If Tony queues up:
>
> l2-mtd.git (or just up to commit a61ae81a1907)
> +
> your patches
>
> and I pull that back into l2-mtd.git as well, then we don't need to
> worry about patches that touch multiple "trees". Just do whatever makes
> things clearest, including disregarding some of my comments along the
> line of (3).
Tony,
Are you fine with this?
cheers,
-roger
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Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Brian, On 03/12/15 10:39, Brian Norris wrote: > Hi, > > On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote: >> Hi, >> >> We do a couple of things in this series which result in >> cleaner device tree implementation, faster perfomance and >> multi-platform support. As an added bonus we get new GPI/Interrupt pins >> for use in the system. >> >> - Establish a custom interface between NAND and GPMC driver. This is >> needed because all of the NAND registers sit in the GPMC register space. >> Some bits like NAND IRQ are even shared with GPMC. >> >> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >> This causes performance increase when using prefetch-irq mode. >> 30% increase in read, 17% increase in write in prefetch-irq mode. >> >> - Clean up device tree support so that omap-gpmc IP and the omap2 NAND >> driver can be used on non-OMAP platforms. e.g. Keystone. >> >> - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain >> 2 to 4 of these and most of them would be unused otherwise. It also >> allows a cleaner implementation of NAND Ready pin status for the NAND driver. >> >> - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. >> >> This series is available at >> g...@github.com:rogerq/linux.git >> in branch >> for-v4.4/gpmc-v3 >> >> cheers, >> -roger >> >> Changelog: >> v3: >> -Fixed and tested NAND using legacy boot on omap3-beagle. >> -Support rising and falling edge interrupts on WAITpins. >> -Update DT node of all gpmc users. > > The MTD stuff looks mostly good to me know. I've made all my comments > for now, but I'm not sure how you're going to end up rebasing/splitting > and what you're going to do with the irqchip removal, so I'll refrain > from ack's for now. Hopefully I can either ack or merge v4. I'll retain the irqchip model for now and send a v4 with all comments addressed and better subsystem wise patch split. > > I brought it up on one other patch, but it's not really clear to me what > the split is on board file vs. device tree handling, since you seem to > have a combination of both (i.e., platform data that passes along device > nodes). What's the plan on that? Platform data no longer passes device nodes. We're either true device tree or plain legacy. The deprecated fields are no longer used once the series is applied. > > And of course, there's the question of how exactly to merge this, given > the: > (1) conflicts already existing in the MTD dev tree I'll rebase the series on top of MTD dev tree. > (2) this touches several trees, often in the same patch and I'll try my best to split the patches but not sure if this could be 100% clean split without functional breakage. > (3) even if the patches were split out a little better into MTD and > non-MTD stuff, I think there would still be dependencies such that > we'd need at least 1 (probably 2) cross merges to get it all > straight That is correct. Is it OK if functionality breaks if for example only MTD changes are considered? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 11/27] mtd: nand: omap: Clean up device tree support
Brian,
On 03/12/15 09:59, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Oct 06, 2015 at 01:35:48PM +0300, Roger Quadros wrote:
>> Move NAND specific device tree parsing to NAND driver.
>>
>> The NAND controller node must have a compatible id, register space
>> resource and interrupt resource.
>>
>> Signed-off-by: Roger Quadros
>
> This one's going to need rebased, as there are some conflicting of_node
> changes in l2-mtd.git.
Al right. I'll rebase on top of l2-mtd.git
>
>> ---
>> v4: Warn if using older incompatible DT i.e. compatible property not present
>> in nand node.
>>
>> arch/arm/mach-omap2/gpmc-nand.c | 5 +-
>> drivers/memory/omap-gpmc.c | 143
>> +++
>> drivers/mtd/nand/omap2.c | 136 +
>> include/linux/platform_data/mtd-nand-omap2.h | 3 +-
>> 4 files changed, 155 insertions(+), 132 deletions(-)
>
> Also, this is going to be hard to manage across trees, as you touch
> three drivers all at once. Is it not possible to split any of this apart
> better?
Will need some more effort and I can do it. Butm if we're going to start
an with immutable branch with everything in, is it worth the effort?
>
>>
>> diff --git a/arch/arm/mach-omap2/gpmc-nand.c
>> b/arch/arm/mach-omap2/gpmc-nand.c
>> index ffe646a..e07ca27 100644
>> --- a/arch/arm/mach-omap2/gpmc-nand.c
>> +++ b/arch/arm/mach-omap2/gpmc-nand.c
>> @@ -95,10 +95,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
>> *gpmc_nand_data,
>> gpmc_nand_res[1].start = gpmc_get_irq();
>>
>> memset(&s, 0, sizeof(struct gpmc_settings));
>> -if (gpmc_nand_data->of_node)
>> -gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
>> -else
>> -gpmc_set_legacy(gpmc_nand_data, &s);
>> +gpmc_set_legacy(gpmc_nand_data, &s);
>>
>> s.device_nand = true;
>>
>> diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
>> index e75226d..318c187 100644
>> --- a/drivers/memory/omap-gpmc.c
>> +++ b/drivers/memory/omap-gpmc.c
>> @@ -29,7 +29,6 @@
>> #include
>> #include
>> #include
>> -#include
>> #include
>>
>>
>> -ppdata.of_node = pdata->of_node;
>> -mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
>> - pdata->nr_parts);
>> +if (dev->of_node) {
>> +ppdata.of_node = dev->of_node;
>
> The latest l2-mtd.git changed how the partitions' of_node is passed. Now
> this is handled by nand_set_flash_node().
OK.
>
>> +mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>> +
>> +} else {
>> +mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
>> +}
>>
>> platform_set_drvdata(pdev, mtd);
>>
>> @@ -2083,11 +2173,17 @@ static int omap_nand_remove(struct platform_device
>> *pdev)
>> return 0;
>> }
>>
>> +static const struct of_device_id omap_nand_ids[] = {
>> +{ .compatible = "ti,omap2-nand", },
>> +{},
>> +};
>> +
>> static struct platform_driver omap_nand_driver = {
>> .probe = omap_nand_probe,
>> .remove = omap_nand_remove,
>> .driver = {
>> .name = DRIVER_NAME,
>> +.of_match_table = of_match_ptr(omap_nand_ids),
>> },
>> };
>>
>> diff --git a/include/linux/platform_data/mtd-nand-omap2.h
>> b/include/linux/platform_data/mtd-nand-omap2.h
>> index a067f58..ff27e5a 100644
>> --- a/include/linux/platform_data/mtd-nand-omap2.h
>> +++ b/include/linux/platform_data/mtd-nand-omap2.h
>> @@ -76,11 +76,10 @@ struct omap_nand_platform_data {
>> int devsize;
>> enum omap_ecc ecc_opt;
>>
>> -/* for passing the partitions */
>> -struct device_node *of_node;
>> struct device_node *elm_of_node;
>>
>> /* deprecated */
>> struct gpmc_nand_regs reg;
>> +struct device_node *of_node;
>
> I'm a little confused here. Do you have a mixed platform data / device
> tree setup here? That's odd. (It also seems if that was really
> necessary, you could have the board file set pdev->dev.of_node before
> registering it, then you don't need this field.) But really, if you're
> partly using device tree, can&#x
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Brian, On 02/12/15 08:56, Brian Norris wrote: > Hi Roger, > > On Tue, Dec 01, 2015 at 04:41:16PM +0200, Roger Quadros wrote: >> On 30/11/15 21:54, Brian Norris wrote: >>> On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote: >>>> On 26/10/15 23:23, Brian Norris wrote: >>>>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote: >>>>>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >>>>>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >>>>>> This causes performance increase when using prefetch-irq mode. >>>>>> 30% increase in read, 17% increase in write in prefetch-irq mode. >>>>> >>>>> Have you pinpointed the exact causes for the performance increase, or >>>>> can you give an educated guess? AIUI, you're reducing the number of >>>>> interrupts needed for NAND prefetch mode, but you're also removing a bit >>>>> of abstraction and implementing hooks that look awfully like the >>>>> existing abstractions: >>>>> >>>>> + int (*nand_irq_enable)(enum gpmc_nand_irq irq); >>>>> + int (*nand_irq_disable)(enum gpmc_nand_irq irq); >>>>> + void (*nand_irq_clear)(enum gpmc_nand_irq irq); >>>>> + u32 (*nand_irq_status)(void); >>>>> >>>>> That's not really a problem if there's a good reason for them (brcmnand >>>>> implements similar hooks because of quirks in the implementation of >>>>> interrupts across various BRCM SoCs, and it's not worth writing irqchip >>>>> drivers for those cases). I'm mainly curious for an explanation. >>>> >>>> I have both implementations with me. My guess is that the 20% performance >>>> gain is due to absence of irqchip/irqdomain translation code. >>>> I haven't investigated further though. >>> >>> I don't have much context for whether this makes sense or not. According >>> to your tests, you're getting ~800K interrupts over ~15 seconds. So >>> should you start noticing performance hits due to abstraction at 53K >>> interrupts per second? >> >> Yes, this was my understanding. > > Am I computing wrong, or is that a pretty insane rate of interrupts? I don't have the test board with me right now and so can't tell you for sure if the mtd tests took 15 seconds or more. I can try it out on a different board that I have and let you know for sure about how many interrupts we get per second. > >>> But anyway, I'm not sure that completely answered my question. My >>> question was whether you were removing the irqchip code solely for >>> performance reasons, or are there others? >> >> Yes. Only for performance reasons. > > Hmm, that's not my favorite answer. I'd prefer that more analysis was > done here before scrapping irqchip... I agree. We could retain the irqchip model till we have more satisfying analysis. > > But maybe that's not too bad. It seems like your patch set overall is a > net positive for disentangling some of arch/ and drivers/. :) > > I'll take another pass over your patch set, but if things are looking > better, how do you expect to merge this? There are significant portions > that touch at least 2 or 3 different subsystem trees, AFAICT. Tony could create an immutable branch with all the dts and memory changes. You could base the mtd changes on top of that? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Hi Brian, On 30/11/15 21:54, Brian Norris wrote: > Hi Roger, > > On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote: >> On 26/10/15 23:23, Brian Norris wrote: >>> I'm not too familiar with OMAP platforms, and I might have missed out on >>> prior discussions/context, so please forgive if I'm asking silly or old >>> questions here. >> >> No worries at all. >> >>> >>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote: >>>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >>>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >>>> This causes performance increase when using prefetch-irq mode. >>>> 30% increase in read, 17% increase in write in prefetch-irq mode. >>> >>> Have you pinpointed the exact causes for the performance increase, or >>> can you give an educated guess? AIUI, you're reducing the number of >>> interrupts needed for NAND prefetch mode, but you're also removing a bit >>> of abstraction and implementing hooks that look awfully like the >>> existing abstractions: >>> >>> + int (*nand_irq_enable)(enum gpmc_nand_irq irq); >>> + int (*nand_irq_disable)(enum gpmc_nand_irq irq); >>> + void (*nand_irq_clear)(enum gpmc_nand_irq irq); >>> + u32 (*nand_irq_status)(void); >>> >>> That's not really a problem if there's a good reason for them (brcmnand >>> implements similar hooks because of quirks in the implementation of >>> interrupts across various BRCM SoCs, and it's not worth writing irqchip >>> drivers for those cases). I'm mainly curious for an explanation. >> >> I have both implementations with me. My guess is that the 20% performance >> gain is due to absence of irqchip/irqdomain translation code. >> I haven't investigated further though. > > I don't have much context for whether this makes sense or not. According > to your tests, you're getting ~800K interrupts over ~15 seconds. So > should you start noticing performance hits due to abstraction at 53K > interrupts per second? Yes, this was my understanding. > > But anyway, I'm not sure that completely answered my question. My > question was whether you were removing the irqchip code solely for > performance reasons, or are there others? Yes. Only for performance reasons. > >> Another concern I have is that I'm not using any locking around >> gpmc_nand_irq_enable/disable(). Could this pose problems in multiple NAND >> use cases? My understanding is that it should not as the controller access >> is serialized between multiple NAND chips. > > Right, if you're touching just a NAND interrupt, and it's only used by a > single instance of this NAND controller, then the NAND controller > serialization code will handle this for you. OK. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Brian, On 27/10/15 11:37, Roger Quadros wrote: > Hi Brian, > > On 26/10/15 23:23, Brian Norris wrote: >> Hi Roger, >> >> I'm not too familiar with OMAP platforms, and I might have missed out on >> prior discussions/context, so please forgive if I'm asking silly or old >> questions here. > > No worries at all. > >> >> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote: >>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >>> This causes performance increase when using prefetch-irq mode. >>> 30% increase in read, 17% increase in write in prefetch-irq mode. >> >> Have you pinpointed the exact causes for the performance increase, or >> can you give an educated guess? AIUI, you're reducing the number of >> interrupts needed for NAND prefetch mode, but you're also removing a bit >> of abstraction and implementing hooks that look awfully like the >> existing abstractions: >> >> + int (*nand_irq_enable)(enum gpmc_nand_irq irq); >> + int (*nand_irq_disable)(enum gpmc_nand_irq irq); >> + void (*nand_irq_clear)(enum gpmc_nand_irq irq); >> + u32 (*nand_irq_status)(void); >> >> That's not really a problem if there's a good reason for them (brcmnand >> implements similar hooks because of quirks in the implementation of >> interrupts across various BRCM SoCs, and it's not worth writing irqchip >> drivers for those cases). I'm mainly curious for an explanation. > > I have both implementations with me. My guess is that the 20% performance > gain is due to absence of irqchip/irqdomain translation code. > I haven't investigated further though. > > Another concern I have is that I'm not using any locking around > gpmc_nand_irq_enable/disable(). Could this pose problems in multiple NAND > use cases? My understanding is that it should not as the controller access > is serialized between multiple NAND chips. > > However I do need to add some locking as the GPMC_IRQENABLE register is shared > between NAND and GPMC driver. > > NOTE: We are not using prefetch-irq mode for any of the OMAP boards because > of lesser performance than prefetch-polled mode. So if the less performance > for an unused mode is a lesser concern compared to cleaner code then > I can resend this with the irqdomain implementation. > > Below are performance logs of irqdomain vs hooks. Any further comments? cheers, -roger > > -- > cheers, > -roger > > test logs. > > for-v4.4/gpmc-v2 - irqdomain with prefetch-irq. No ready pin. > > > [ 67.696631] > [ 67.698201] = > [ 67.704254] mtd_speedtest: MTD device: 8 > [ 67.708373] mtd_speedtest: MTD device size 8388608, eraseblock size > 131072, page size 2048, count of eraseblocks 64, pages per eraseblock 64, OOB > size 64 > [ 67.723701] mtd_test: scanning for bad eraseblocks > [ 67.735468] mtd_test: scanned 64 eraseblocks, 0 are bad > [ 67.772861] mtd_speedtest: testing eraseblock write speed > [ 70.372903] mtd_speedtest: eraseblock write speed is 3156 KiB/s > [ 70.379104] mtd_speedtest: testing eraseblock read speed > [ 72.594169] mtd_speedtest: eraseblock read speed is 3708 KiB/s > [ 72.656375] mtd_speedtest: testing page write speed > [ 75.213646] mtd_speedtest: page write speed is 3208 KiB/s > [ 75.219311] mtd_speedtest: testing page read speed > [ 77.343639] mtd_speedtest: page read speed is 3865 KiB/s > [ 77.405236] mtd_speedtest: testing 2 page write speed > [ 80.039702] mtd_speedtest: 2 page write speed is 3114 KiB/s > [ 80.045561] mtd_speedtest: testing 2 page read speed > [ 82.175098] mtd_speedtest: 2 page read speed is 3856 KiB/s > [ 82.180849] mtd_speedtest: Testing erase speed > [ 82.241548] mtd_speedtest: erase speed is 146285 KiB/s > [ 82.246920] mtd_speedtest: Testing 2x multi-block erase speed > [ 82.284789] mtd_speedtest: 2x multi-block erase speed is 264258 KiB/s > [ 82.291551] mtd_speedtest: Testing 4x multi-block erase speed > [ 82.329358] mtd_speedtest: 4x multi-block erase speed is 264258 KiB/s > [ 82.336116] mtd_speedtest: Testing 8x multi-block erase speed > [ 82.373903] mtd_speedtest: 8x multi-block erase speed is 264258 KiB/s > [ 82.380648] mtd_speedtest: Testing 16x multi-block erase speed > [ 82.418503] mtd_speedtest: 16x multi-block erase speed is 264258 KiB/s > [ 82.425356] mtd_speedtest: Testing 32x multi-block erase speed > [ 82.463227] mtd_speedtest: 32x multi-block erase speed is 264258 KiB/s >
Re: [PATCH v2 16/16] mmc: host: omap_hsmmc: use "mmc_of_parse_voltage" to get ocr_avail
Hi,
On 25/08/15 17:50, Ulf Hansson wrote:
> On 3 August 2015 at 14:26, Kishon Vijay Abraham I wrote:
>> From: Roger Quadros
>>
>> For platforms that doesn't have explicit regulator control in MMC,
>> populate voltage-ranges in MMC device tree node and use
>> mmc_of_parse_voltage to get ocr_avail
>
> I don't like this.
>
> If we are able to fetch the OCR mask via an external regulator, that
> shall be done.
Agreed.
>
> I think the mmc_of_parse_voltage() API and the corresponding DT
> binding it parses, should be used for those HW when we don't have an
> external regulator to use. For example if the MMC controller itself
> somehow controls the voltage levels. Is that really the case for you?
What shall be done if there is no software control of the external regulator
and it is fixed at a certain voltage?
cheers,
-roger
>
> Kind regards
> Uffe
>
>>
>> Signed-off-by: Roger Quadros
>> Signed-off-by: Lokesh Vutla
>> Signed-off-by: Murali Karicheri
>> Signed-off-by: Franklin S Cooper Jr
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> .../devicetree/bindings/mmc/ti-omap-hsmmc.txt |2 ++
>> drivers/mmc/host/omap_hsmmc.c |9 -
>> 2 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> index 76bf087..2408e87 100644
>> --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> @@ -22,6 +22,8 @@ ti,dual-volt: boolean, supports dual voltage cards
>> ti,non-removable: non-removable slot (like eMMC)
>> ti,needs-special-reset: Requires a special softreset sequence
>> ti,needs-special-hs-handling: HSMMC IP needs special setting for handling
>> High Speed
>> +voltage-ranges: Specify the voltage range supported if regulator framework
>> +isn't enabled.
>> dmas: List of DMA specifiers with the controller specific format
>> as described in the generic DMA client binding. A tx and rx
>> specifier is required.
>> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
>> index 15973f1..d884d8f 100644
>> --- a/drivers/mmc/host/omap_hsmmc.c
>> +++ b/drivers/mmc/host/omap_hsmmc.c
>> @@ -2184,7 +2184,13 @@ static int omap_hsmmc_probe(struct platform_device
>> *pdev)
>> goto err_irq;
>> }
>>
>> - mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
>> + if (!mmc_pdata(host)->ocr_mask) {
>> + ret = mmc_of_parse_voltage(pdev->dev.of_node,
>> &mmc->ocr_avail);
>> + if (ret)
>> + goto err_parse_voltage;
>> + } else {
>> + mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
>> + }
>>
>> omap_hsmmc_disable_irq(host);
>>
>> @@ -2224,6 +2230,7 @@ static int omap_hsmmc_probe(struct platform_device
>> *pdev)
>>
>> err_slot_name:
>> mmc_remove_host(mmc);
>> +err_parse_voltage:
>> omap_hsmmc_reg_put(host);
>> err_irq:
>> device_init_wakeup(&pdev->dev, false);
>> --
>> 1.7.9.5
>>
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Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Hi Brian, On 26/10/15 23:23, Brian Norris wrote: > Hi Roger, > > I'm not too familiar with OMAP platforms, and I might have missed out on > prior discussions/context, so please forgive if I'm asking silly or old > questions here. No worries at all. > > On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote: >> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >> This causes performance increase when using prefetch-irq mode. >> 30% increase in read, 17% increase in write in prefetch-irq mode. > > Have you pinpointed the exact causes for the performance increase, or > can you give an educated guess? AIUI, you're reducing the number of > interrupts needed for NAND prefetch mode, but you're also removing a bit > of abstraction and implementing hooks that look awfully like the > existing abstractions: > > + int (*nand_irq_enable)(enum gpmc_nand_irq irq); > + int (*nand_irq_disable)(enum gpmc_nand_irq irq); > + void (*nand_irq_clear)(enum gpmc_nand_irq irq); > + u32 (*nand_irq_status)(void); > > That's not really a problem if there's a good reason for them (brcmnand > implements similar hooks because of quirks in the implementation of > interrupts across various BRCM SoCs, and it's not worth writing irqchip > drivers for those cases). I'm mainly curious for an explanation. I have both implementations with me. My guess is that the 20% performance gain is due to absence of irqchip/irqdomain translation code. I haven't investigated further though. Another concern I have is that I'm not using any locking around gpmc_nand_irq_enable/disable(). Could this pose problems in multiple NAND use cases? My understanding is that it should not as the controller access is serialized between multiple NAND chips. However I do need to add some locking as the GPMC_IRQENABLE register is shared between NAND and GPMC driver. NOTE: We are not using prefetch-irq mode for any of the OMAP boards because of lesser performance than prefetch-polled mode. So if the less performance for an unused mode is a lesser concern compared to cleaner code then I can resend this with the irqdomain implementation. Below are performance logs of irqdomain vs hooks. -- cheers, -roger test logs. for-v4.4/gpmc-v2 - irqdomain with prefetch-irq. No ready pin. [ 67.696631] [ 67.698201] = [ 67.704254] mtd_speedtest: MTD device: 8 [ 67.708373] mtd_speedtest: MTD device size 8388608, eraseblock size 131072, page size 2048, count of eraseblocks 64, pages per eraseblock 64, OOB size 64 [ 67.723701] mtd_test: scanning for bad eraseblocks [ 67.735468] mtd_test: scanned 64 eraseblocks, 0 are bad [ 67.772861] mtd_speedtest: testing eraseblock write speed [ 70.372903] mtd_speedtest: eraseblock write speed is 3156 KiB/s [ 70.379104] mtd_speedtest: testing eraseblock read speed [ 72.594169] mtd_speedtest: eraseblock read speed is 3708 KiB/s [ 72.656375] mtd_speedtest: testing page write speed [ 75.213646] mtd_speedtest: page write speed is 3208 KiB/s [ 75.219311] mtd_speedtest: testing page read speed [ 77.343639] mtd_speedtest: page read speed is 3865 KiB/s [ 77.405236] mtd_speedtest: testing 2 page write speed [ 80.039702] mtd_speedtest: 2 page write speed is 3114 KiB/s [ 80.045561] mtd_speedtest: testing 2 page read speed [ 82.175098] mtd_speedtest: 2 page read speed is 3856 KiB/s [ 82.180849] mtd_speedtest: Testing erase speed [ 82.241548] mtd_speedtest: erase speed is 146285 KiB/s [ 82.246920] mtd_speedtest: Testing 2x multi-block erase speed [ 82.284789] mtd_speedtest: 2x multi-block erase speed is 264258 KiB/s [ 82.291551] mtd_speedtest: Testing 4x multi-block erase speed [ 82.329358] mtd_speedtest: 4x multi-block erase speed is 264258 KiB/s [ 82.336116] mtd_speedtest: Testing 8x multi-block erase speed [ 82.373903] mtd_speedtest: 8x multi-block erase speed is 264258 KiB/s [ 82.380648] mtd_speedtest: Testing 16x multi-block erase speed [ 82.418503] mtd_speedtest: 16x multi-block erase speed is 264258 KiB/s [ 82.425356] mtd_speedtest: Testing 32x multi-block erase speed [ 82.463227] mtd_speedtest: 32x multi-block erase speed is 264258 KiB/s [ 82.470066] mtd_speedtest: Testing 64x multi-block erase speed [ 82.507908] mtd_speedtest: 64x multi-block erase speed is 264258 KiB/s [ 82.514758] mtd_speedtest: finished [ 82.518417] = root@rockdesk:~# cat /proc/interrupts CPU0 CPU1 324: 798720 0 CBAR 15 Level gpmc 397: 798720 0 gpmc 0 Edge gpmc-nand-fifo 398: 24576 0 gpmc 1 Edge gpmc-nand-count root@rockde
Re: [PATCH v3 18/27] mtd: nand: omap2: Implement NAND ready using gpiolib
Boris, On 27/10/15 10:12, Boris Brezillon wrote: > Hi Roger, > > On Tue, 27 Oct 2015 10:03:02 +0200 > Roger Quadros wrote: > >> On 26/10/15 22:49, Brian Norris wrote: >>> >>> Others have been looking at using GPIOs for the ready/busy pin too. At a >>> minimum, we need an updated DT binding doc for this, since I see you're >>> adding this via device tree in a later patch (I don't see any DT binding >>> patch for this; but I could just be overlooking it). It'd also be great >>> if this support was moved to nand_dt_init() so other platforms can >>> benefit, but I won't require that. >>> >>> Also, previous [0] proposers had suggested 'rb-gpios', not 'ready-gpio' >>> (the hardware docs typically call it 'rb' for ready/busy, FWIW). I don't >>> really care, but the name should be going into a doc, so we can choose >>> the same one everywhere. >>> >>> EDIT: looks like the discussion was partly here [1] and it seems we're >>> landing on "rb-gpios" in the latest version [2]. Can we stick with that? >> >> Why should it be "rb-gpios" and not "rb-gpio"? >> I don't think there are multiple gpios for r/b# function. > > Because it's supposed to be a generic binding, and some NAND chips > embed several dies, thus exposing several CS and RB pins, hence the > rb-gpios name. > Also, as described here [1], the convention is to name your property > -gpios even if you only need one gpio. Makes sense now. Thanks for the explanation. I'll update this patch to use rb-gpios and update the binding doc as well. -- cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 18/27] mtd: nand: omap2: Implement NAND ready using gpiolib
On 26/10/15 22:49, Brian Norris wrote:
> + others
>
> A few comments below.
>
> On Fri, Sep 18, 2015 at 05:53:40PM +0300, Roger Quadros wrote:
>> The GPMC WAIT pin status are now available over gpiolib.
>> Update the omap_dev_ready() function to use gpio instead of
>> directly accessing GPMC register space.
>>
>> Signed-off-by: Roger Quadros
>> ---
>> drivers/mtd/nand/omap2.c | 29
>> +---
>> include/linux/platform_data/mtd-nand-omap2.h | 2 +-
>> 2 files changed, 19 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
>> index 228f498..d0f2620 100644
>> --- a/drivers/mtd/nand/omap2.c
>> +++ b/drivers/mtd/nand/omap2.c
>> @@ -12,6 +12,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -184,6 +185,8 @@ struct omap_nand_info {
>> /* fields specific for BCHx_HW ECC scheme */
>> struct device *elm_dev;
>> struct device_node *of_node;
>> +/* NAND ready gpio */
>> +struct gpio_desc*ready_gpiod;
>> };
>>
>> /**
>> @@ -1047,22 +1050,17 @@ static int omap_wait(struct mtd_info *mtd, struct
>> nand_chip *chip)
>> }
>>
>> /**
>> - * omap_dev_ready - calls the platform specific dev_ready function
>> + * omap_dev_ready - checks the NAND Ready GPIO line
>> * @mtd: MTD device structure
>> + *
>> + * Returns true if ready and false if busy.
>> */
>> static int omap_dev_ready(struct mtd_info *mtd)
>> {
>> -unsigned int val = 0;
>> struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
>> mtd);
>>
>> -val = readl(info->reg.gpmc_status);
>> -
>> -if ((val & 0x100) == 0x100) {
>> -return 1;
>> -} else {
>> -return 0;
>> -}
>> +return gpiod_get_value(info->ready_gpiod);
>> }
>>
>> /**
>> @@ -1782,7 +1780,9 @@ static int omap_nand_probe(struct platform_device
>> *pdev)
>> info->reg = pdata->reg;
>> info->of_node = pdata->of_node;
>> info->ecc_opt = pdata->ecc_opt;
>> -info->dev_ready = pdata->dev_ready;
>> +if (pdata->dev_ready)
>> +dev_info(&pdev->dev, "pdata->dev_ready is
>> deprecated\n");
>> +
>> info->xfer_type = pdata->xfer_type;
>> info->devsize = pdata->devsize;
>> info->elm_of_node = pdata->elm_of_node;
>> @@ -1815,6 +1815,13 @@ static int omap_nand_probe(struct platform_device
>> *pdev)
>> nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
>> nand_chip->cmd_ctrl = omap_hwcontrol;
>>
>> +info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "ready",
>> +GPIOD_IN);
>
> Others have been looking at using GPIOs for the ready/busy pin too. At a
> minimum, we need an updated DT binding doc for this, since I see you're
> adding this via device tree in a later patch (I don't see any DT binding
> patch for this; but I could just be overlooking it). It'd also be great
> if this support was moved to nand_dt_init() so other platforms can
> benefit, but I won't require that.
>
> Also, previous [0] proposers had suggested 'rb-gpios', not 'ready-gpio'
> (the hardware docs typically call it 'rb' for ready/busy, FWIW). I don't
> really care, but the name should be going into a doc, so we can choose
> the same one everywhere.
>
> EDIT: looks like the discussion was partly here [1] and it seems we're
> landing on "rb-gpios" in the latest version [2]. Can we stick with that?
Why should it be "rb-gpios" and not "rb-gpio"?
I don't think there are multiple gpios for r/b# function.
cheers,
-roger
>
> Regards,
> Brian
>
> [0] "Previous" may be subject to debate, as both series have been going
> for several revisions.
> [1] http://patchwork.ozlabs.org/patch/515327/
> [2] http://patchwork.ozlabs.org/patch/526819/
>
>> +if (IS_ERR(info->ready_gpiod)) {
>> +dev_err(dev, "failed to get ready gpio\n");
>> +return PTR_ERR(info->ready_gpiod);
>> +}
>
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 21/10/15 18:20, Tony Lindgren wrote: > * Roger Quadros [151021 01:31]: >> On 19/10/15 10:08, Roger Quadros wrote: >>> On 17/10/15 00:25, Tony Lindgren wrote: >>>> * Roger Quadros [151006 04:13]: >>>>> >>>>> Fine. The updated series is now at >>>>> >>>>> g...@github.com:rogerq/linux.git >>>>> * [new branch] for-v4.4/gpmc-v4 >>>> >>>> Looks like it produces some build errors, this with RMKs 3430 and 4430 >>>> only .configs: >>>> >>>> drivers/memory/omap-gpmc.c:2035:43: error: ‘struct gpio_chip’ has no >>>> member named ‘irqdomain’ >>>> drivers/memory/omap-gpmc.c:2116:8: error: implicit declaration of >>>> function ‘gpiochip_irqchip_add’ [-Werror=implicit-function-declaration] >>>> >>> >>> Good catch. We'll have to select GPIOLIB_IRQCHIP for this driver. >>> >>>> Maybe run randconfig builds on it for overnight? >>> >>> OK. I'll do that. >> >> I couldn't run randconfig beyond few iterations as it keeps failing >> everywhere. How do we limit the randconfig options to OMAP only >> platforms? > > You can use Felipe's scripts from github. Thanks. I used his scripts and ran 10 randconfigs per platform. Didn't find any issues with this series. How can we proceed? Patches are on https://github.com/rogerq/linux/commits/for-v4.4/gpmc-v4 cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 19/10/15 10:08, Roger Quadros wrote: > On 17/10/15 00:25, Tony Lindgren wrote: >> * Roger Quadros [151006 04:13]: >>> >>> Fine. The updated series is now at >>> >>> g...@github.com:rogerq/linux.git >>> * [new branch] for-v4.4/gpmc-v4 >> >> Looks like it produces some build errors, this with RMKs 3430 and 4430 >> only .configs: >> >> drivers/memory/omap-gpmc.c:2035:43: error: ‘struct gpio_chip’ has no >> member named ‘irqdomain’ >> drivers/memory/omap-gpmc.c:2116:8: error: implicit declaration of >> function ‘gpiochip_irqchip_add’ [-Werror=implicit-function-declaration] >> > > Good catch. We'll have to select GPIOLIB_IRQCHIP for this driver. > >> Maybe run randconfig builds on it for overnight? > > OK. I'll do that. I couldn't run randconfig beyond few iterations as it keeps failing everywhere. How do we limit the randconfig options to OMAP only platforms? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 17/10/15 00:25, Tony Lindgren wrote: > * Roger Quadros [151006 04:13]: >> >> Fine. The updated series is now at >> >> g...@github.com:rogerq/linux.git >> * [new branch] for-v4.4/gpmc-v4 > > Looks like it produces some build errors, this with RMKs 3430 and 4430 > only .configs: > > drivers/memory/omap-gpmc.c:2035:43: error: ‘struct gpio_chip’ has no > member named ‘irqdomain’ > drivers/memory/omap-gpmc.c:2116:8: error: implicit declaration of > function ‘gpiochip_irqchip_add’ [-Werror=implicit-function-declaration] > Good catch. We'll have to select GPIOLIB_IRQCHIP for this driver. > Maybe run randconfig builds on it for overnight? OK. I'll do that. > > Other than that your series seems to behave for me now, so feel > free to add: > > Acked-by: Tony Lindgren Thanks for the tests :) cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/5] mtd: nand: Fix support for NAND DMA prefetch
On 15/10/15 20:37, Franklin S Cooper Jr wrote: > NAND DMA prefetch has been broken for awhile and seems to have only > worked for SDMA based devices > > This patchset fixes DMA prefetch to work on both EDMA and SDMA devices > > Test on: > am335x gp evm > am437x gp evm > am37x gp evm > > This patchset depends on Roger Quadros recent v4 GPMC/NAND patchset > https://github.com/rogerq/linux.git > branch: for-v4.4/gpmc-v4 > > Franklin S Cooper Jr (5): > mtd: nand: omap2: Support parsing dma channel information from DT > mtd: nand: omap2: Start dma request before enabling prefetch > mtd: nand: omap2: Fix high memory dma prefetch transfer > ARM: dts: am437x/am33xx/omap/dm816x: Add gpmc dma channel > ARM: OMAP2+: Update GPMC and NAND DT binding documentation > > .../bindings/memory-controllers/omap-gpmc.txt | 7 +- > .../devicetree/bindings/mtd/gpmc-nand.txt | 2 ++ > arch/arm/boot/dts/am33xx.dtsi | 2 ++ > arch/arm/boot/dts/am4372.dtsi | 2 ++ > arch/arm/boot/dts/dm816x.dtsi | 2 ++ > arch/arm/boot/dts/omap3.dtsi | 2 ++ > arch/arm/boot/dts/omap4.dtsi | 2 ++ > arch/arm/boot/dts/omap5.dtsi | 2 ++ > drivers/mtd/nand/omap2.c | 27 > +----- > 9 files changed, 31 insertions(+), 17 deletions(-) > For all patches, Acked-by: Roger Quadros -- cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: keystone: dts: add PCI serdes driver bindings
WingMan,
On 15/10/15 17:27, WingMan Kwok wrote:
> This patch adds the required PCI serdes bindings whcih can then be
> enabled by setting the corresponding statuses to "ok" in order to
> configure and start the PCI serdes.
>
> This patch depends on the updates to the Keystone PCIe host driver
> and common serdes driver patch series that is submitted separately.
>
> Signed-off-by: WingMan Kwok
> ---
> arch/arm/boot/dts/k2e.dtsi | 21 +
> arch/arm/boot/dts/keystone.dtsi | 21 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
> index 675fb8e..3b36575 100644
> --- a/arch/arm/boot/dts/k2e.dtsi
> +++ b/arch/arm/boot/dts/k2e.dtsi
> @@ -86,6 +86,16 @@
> gpio,syscon-dev = <&devctrl 0x240>;
> };
>
> + pcie1_phy: pciephy@2326000 {
Should be
pcie1_phy: phy@2326000 {
> + #phy-cells = <0>;
> + compatible = "ti,keystone-serdes-pcie";
> + reg = <0x02326000 0x4000>;
> + reg-names = "serdes";
> + link-rate-kbps = <500>;
> + num-lanes = <2>;
> + status = "disabled";
> + };
> +
> pcie1: pcie@2102 {
> compatible = "ti,keystone-pcie","snps,dw-pcie";
> clocks = <&clkpcie1>;
> @@ -130,6 +140,17 @@
> ,
> ;
> };
> +
> + /* PCIE phy */
> + serdeses {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + serdes@0 {
> + reg = <0>;
> + phys = <&pcie1_phy>;
> + };
> + };
> +
> };
>
> mdio: mdio@24200f00 {
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 72816d6..6566cc4 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -275,6 +275,16 @@
> ti,syscon-dev = <&devctrl 0x2a0>;
> };
>
> + pcie0_phy: pciephy@232 {
ditto.
> + #phy-cells = <0>;
> + compatible = "ti,keystone-serdes-pcie";
> + reg = <0x0232 0x4000>;
> + reg-names = "serdes";
> + link-rate-kbps = <500>;
> + num-lanes = <2>;
> + status = "disabled";
> + };
> +
> pcie0: pcie@2180 {
> compatible = "ti,keystone-pcie", "snps,dw-pcie";
> clocks = <&clkpcie>;
> @@ -319,6 +329,17 @@
> ,
> ;
> };
> +
> + /* PCIE phy */
> + serdeses {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + serdes@0 {
> + reg = <0>;
> + phys = <&pcie0_phy>;
> + };
> + };
> +
> };
> };
> };
>
--
cheers,
-roger
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Re: [PATCH 1/5] mtd: nand: omap2: Support parsing dma channel information from DT
On 14/10/15 23:03, Franklin S Cooper Jr. wrote: > > > On 10/14/2015 01:13 PM, Tony Lindgren wrote: >> * Franklin S Cooper Jr. [151014 09:27]: >>> >>> On 10/14/2015 11:18 AM, Tony Lindgren wrote: >>>> * Franklin S Cooper Jr. [151014 07:37]: >>>>> On 10/14/2015 09:11 AM, Roger Quadros wrote: >>>>>> On 14/10/15 16:26, Franklin S Cooper Jr. wrote: >>>>>>> On 10/14/2015 06:52 AM, Roger Quadros wrote: >>>>>>>> Franklin, >>>>>>>> >>>>>>>> On 14/10/15 14:36, Roger Quadros wrote: >>>>>>>>> On 13/10/15 04:38, Franklin S Cooper Jr wrote: >>>>>>>>>> Switch from dma_request_channel to allow passing dma channel >>>>>>>>>> information from DT rather than hardcoding a value. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Franklin S Cooper Jr >>>>>>>>> Acked-by: Roger Quadros >>>>>>>>> >>>>>>>>>> --- >>>>>>>>>> drivers/mtd/nand/omap2.c | 4 +++- >>>>>>>>>> 1 file changed, 3 insertions(+), 1 deletion(-) >>>>>>>>>> >>>>>>>>>> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c >>>>>>>>>> index d0f2620..957c32f 100644 >>>>>>>>>> --- a/drivers/mtd/nand/omap2.c >>>>>>>>>> +++ b/drivers/mtd/nand/omap2.c >>>>>>>>>> @@ -1866,7 +1866,9 @@ static int omap_nand_probe(struct >>>>>>>>>> platform_device *pdev) >>>>>>>>>> dma_cap_zero(mask); >>>>>>>>>> dma_cap_set(DMA_SLAVE, mask); >>>>>>>>>> sig = OMAP24XX_DMA_GPMC; >>>>>>>>>> -info->dma = dma_request_channel(mask, >>>>>>>>>> omap_dma_filter_fn, &sig); >>>>>>>>>> +info->dma = dma_request_slave_channel_compat(mask, >>>>>>>>>> +omap_dma_filter_fn, &sig, pdev->dev.parent, >>>>>>>>>> "rxtx"); >>>>>>>>>> + >>>>>>>> Just discovered that you are using the parent device node. >>>>>>>> >>>>>>>> How about moving the dma bindings to the nand node instead and using >>>>>>>> pdev->dev here? >>>>>>> Roger, >>>>>>> >>>>>>> From what I can tell the interrupt number and the dma channel will >>>>>>> always be >>>>>>> the same no matter what. Doesn't matter if you have multiple nands or a >>>>>>> combination of nands and nors. Since that is the case I think it just >>>>>>> makes >>>>>>> sense to leave it in the gpmc parent node and define it once. >>>>>> Is prefetch/writepost dma used for NOR or any other GPMC peripheral >>>>>> or only for NAND? >>>>> The dma seems tied to the prefetch. From what I can tell the prefetch is >>>>> only >>>>> used by nand. >>>>>> Let's also get Tony's inputs on this. >>>>> Sure. >>>> Hmm so what would keep other devices from using the prefetch >>> Looking at the TRM any references to the prefetch are always with respect to >>> NAND. >>> >>> I also see the below mentioned in the TRM. >>> Pre-fetch and write posting engine associated with system DMA to get full >>> performance from NAND >>> device with minimum impact on NOR/SRAM concurrent access. >> OK up to you guys to figure out if it may be usable in a generic way then :) > Ok I just got clarification from hw folks. DMA for GPMC can be used for any > of the > various modes. But the prefetch is specific to NAND. In that case the dma information must be in the GPMC node. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 20/27] ARM: dts: dra7: Fix NAND device nodes.
On 14/10/15 16:34, Franklin S Cooper Jr. wrote:
>
>
> On 09/18/2015 09:53 AM, Roger Quadros wrote:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller and interrupt-controller properties.
>>
>> With this the interrupt parent of NAND node changes so fix it
>> accordingly.
>>
>> Signed-off-by: Roger Quadros
>> ---
>> arch/arm/boot/dts/dra7-evm.dts | 5 -
>> arch/arm/boot/dts/dra7.dtsi | 4
>> arch/arm/boot/dts/dra72-evm.dts | 5 -
>> 3 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index a6c82e5..8a31161 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -585,9 +585,12 @@
>> status = "okay";
>> pinctrl-names = "default";
>> pinctrl-0 = <&nand_flash_x16>;
>> -ranges = <0 0 0 0x0100>;/* minimum GPMC partition = 16MB */
>> +ranges = <0 0 0x0800 0x0100>; /* minimum GPMC partition =
>> 16MB */
>> nand@0,0 {
>> +compatible = "ti,omap2-nand";
>> reg = <0 0 4>; /* device IO registers */
>> +interrupt-parent = <&crossbar_mpu>;
>> +interrupts = ;
>> ti,nand-ecc-opt = "bch8";
>> ti,elm-id = <&elm>;
>> nand-bus-width = <16>;
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 5d65db9..f0a3616 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -1389,6 +1389,10 @@
>> gpmc,num-waitpins = <2>;
>> #address-cells = <2>;
>> #size-cells = <1>;
>> +gpio-controller;
>> +#gpio-cells = <2>;
>> +interrupt-controller;
>> +#interrupt-cells = <2>;
>> status = "disabled";
>> };
> Based on the discussion on my patchset I noticed that the nand node defines
> the
> interrupt but it is also defined in the parent node. Similar to the dma
> channel we
> should conclude where the best place for it to be defined. But to me it
> seems at
> least it should only be defined once.
The interrupt is defined at both places because it is used at both places.
It is used as a shared interrupt. Wait_pin interrupts are managed by the
gpmc driver and NAND specific interrupts are managed by the NAND driver.
If GPMC dma channel is going to be used only by the NAND driver then
we should define the channel in the NAND node.
>
> This is true for your other patches making similar changes to the dt.
Yes, GPMC IRQ is defined in both GPMC and NAND nodes.
--
cheers,
-roger
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Re: [PATCH 1/5] mtd: nand: omap2: Support parsing dma channel information from DT
On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 06:52 AM, Roger Quadros wrote:
>> Franklin,
>>
>> On 14/10/15 14:36, Roger Quadros wrote:
>>> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>>>> Switch from dma_request_channel to allow passing dma channel
>>>> information from DT rather than hardcoding a value.
>>>>
>>>> Signed-off-by: Franklin S Cooper Jr
>>> Acked-by: Roger Quadros
>>>
>>>> ---
>>>> drivers/mtd/nand/omap2.c | 4 +++-
>>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
>>>> index d0f2620..957c32f 100644
>>>> --- a/drivers/mtd/nand/omap2.c
>>>> +++ b/drivers/mtd/nand/omap2.c
>>>> @@ -1866,7 +1866,9 @@ static int omap_nand_probe(struct platform_device
>>>> *pdev)
>>>>dma_cap_zero(mask);
>>>>dma_cap_set(DMA_SLAVE, mask);
>>>>sig = OMAP24XX_DMA_GPMC;
>>>> - info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
>>>> + info->dma = dma_request_slave_channel_compat(mask,
>>>> + omap_dma_filter_fn, &sig, pdev->dev.parent, "rxtx");
>>>> +
>> Just discovered that you are using the parent device node.
>>
>> How about moving the dma bindings to the nand node instead and using
>> pdev->dev here?
> Roger,
>
> From what I can tell the interrupt number and the dma channel will always be
> the same no matter what. Doesn't matter if you have multiple nands or a
> combination of nands and nors. Since that is the case I think it just makes
> sense to leave it in the gpmc parent node and define it once.
Is prefetch/writepost dma used for NOR or any other GPMC peripheral
or only for NAND?
Let's also get Tony's inputs on this.
>>>>if (!info->dma) {
>>>>dev_err(&pdev->dev, "DMA engine request failed\n");
>>>>err = -ENXIO;
>>>>
--
cheers,
-roger
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Re: [PATCH 1/5] mtd: nand: omap2: Support parsing dma channel information from DT
Franklin,
On 14/10/15 14:36, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> Switch from dma_request_channel to allow passing dma channel
>> information from DT rather than hardcoding a value.
>>
>> Signed-off-by: Franklin S Cooper Jr
>
> Acked-by: Roger Quadros
>
>> ---
>> drivers/mtd/nand/omap2.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
>> index d0f2620..957c32f 100644
>> --- a/drivers/mtd/nand/omap2.c
>> +++ b/drivers/mtd/nand/omap2.c
>> @@ -1866,7 +1866,9 @@ static int omap_nand_probe(struct platform_device
>> *pdev)
>> dma_cap_zero(mask);
>> dma_cap_set(DMA_SLAVE, mask);
>> sig = OMAP24XX_DMA_GPMC;
>> -info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
>> +info->dma = dma_request_slave_channel_compat(mask,
>> +omap_dma_filter_fn, &sig, pdev->dev.parent, "rxtx");
>> +
Just discovered that you are using the parent device node.
How about moving the dma bindings to the nand node instead and using
pdev->dev here?
>> if (!info->dma) {
>> dev_err(&pdev->dev, "DMA engine request failed\n");
>> err = -ENXIO;
>>
>
cheers,
-roger
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Re: [PATCH 5/5] ARM: OMAP2+: Update gpmc and nand DT binding documentation
On 13/10/15 04:38, Franklin S Cooper Jr wrote: > Add additional details to the gpmc and nand documentation to clarify > what is needed to enable nand dma prefetch. > > Signed-off-by: Franklin S Cooper Jr > --- > Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 7 > ++- > Documentation/devicetree/bindings/mtd/gpmc-nand.txt| 2 ++ > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt > b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt > index 704be93..b1e2802 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt > @@ -33,6 +33,10 @@ Required properties: > As this will change in the future, filling correct > values here is a requirement. > > +GPMC DMA information. Required only when GPMC nand prefetch is enabled. > + - dmas GPMC nand prefetch dma channel s/nand/NAND > + - dma-names DMA channel name use as a reference within the Nand > driver s/Nand/NAND This is inevitably going to be "rxtx". So why not say that it should be "rxtx" Should these bindings go in bindings/mtd/gpmc-nand.txt instead? > + > Timing properties for child nodes. All are optional and default to 0. > > - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in > picoseconds > @@ -119,7 +123,8 @@ Example for an AM33xx board: > ti,hwmods = "gpmc"; > reg = <0x5000 0x2000>; > interrupts = <100>; > - > + dmas = <&edma 52>; > + dma-names = "rxtx"; Why not define these in the NAND node instead of gpmc node? > gpmc,num-cs = <8>; > gpmc,num-waitpins = <2>; > #address-cells = <2>; > diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt > b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt > index 253e6de..4b0c240 100644 > --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt > +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt > @@ -61,6 +61,8 @@ Example for an AM33xx board: > ti,hwmods = "gpmc"; > reg = <0x5000 0x36c>; > interrupts = <100>; > + dmas = <&edma 52>; > + dma-names = "rxtx"; > gpmc,num-cs = <8>; > gpmc,num-waitpins = <2>; > #address-cells = <2>; > cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/5] ARM: dts: am437x/am33xx/omap3/dm816x: Add gpmc dma channel
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add dma channel information to the gpmc. Although not enabled by
> default this will allow prefetch-dma to be used.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> arch/arm/boot/dts/am33xx.dtsi | 2 ++
> arch/arm/boot/dts/am4372.dtsi | 2 ++
> arch/arm/boot/dts/dm816x.dtsi | 2 ++
> arch/arm/boot/dts/omap3.dtsi | 2 ++
How about fixing up omap4/5 and dra7 as well?
cheers,
-roger
> 4 files changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index e065f21..f2d8eed 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -819,6 +819,8 @@
> ti,no-idle-on-init;
> reg = <0x5000 0x2000>;
> interrupts = <100>;
> + dmas = <&edma 52>;
> + dma-names = "rxtx";
> gpmc,num-cs = <7>;
> gpmc,num-waitpins = <2>;
> #address-cells = <2>;
> diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
> index ec8b7a3..c02061b 100644
> --- a/arch/arm/boot/dts/am4372.dtsi
> +++ b/arch/arm/boot/dts/am4372.dtsi
> @@ -841,6 +841,8 @@
> gpmc: gpmc@5000 {
> compatible = "ti,am3352-gpmc";
> ti,hwmods = "gpmc";
> + dmas = <&edma 52>;
> + dma-names = "rxtx";
> clocks = <&l3s_gclk>;
> clock-names = "fck";
> reg = <0x5000 0x2000>;
> diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
> index 68fb444..d2e5d31 100644
> --- a/arch/arm/boot/dts/dm816x.dtsi
> +++ b/arch/arm/boot/dts/dm816x.dtsi
> @@ -180,6 +180,8 @@
> #address-cells = <2>;
> #size-cells = <1>;
> interrupts = <100>;
> + dmas = <&edma 52>;
> + dma-names = "rxtx";
> gpmc,num-cs = <6>;
> gpmc,num-waitpins = <2>;
> gpio-controller;
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 7f212b6..9dbbcf6 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -717,6 +717,8 @@
> ti,hwmods = "gpmc";
> reg = <0x6e00 0x02d0>;
> interrupts = <20>;
> + dmas = <&sdma 4>;
> + dma-names = "rxtx";
> gpmc,num-cs = <8>;
> gpmc,num-waitpins = <4>;
> #address-cells = <2>;
>
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Re: [PATCH 2/5] mtd: nand: omap2: Start dma request before enabling prefetch
On 13/10/15 04:38, Franklin S Cooper Jr wrote: > The prefetch engine sends a dma request once a FIFO threshold has > been met. No other requests are received until the previous request > is handled. > > Starting an edma transfer (dma_async_issue_pending) results in any > previous event for the dma channel to be cleared. Therefore, starting > the prefetch engine before initiating the dma transfer may result in > the prefetch triggering a dma request but instead of it being handled > it can end up being cleared. This will result in a hang since the code > will continue to wait for the dma request to complete. > > By initiating the dma request before enabling the prefetch engine this > race condition is avoided and no dma request are missed/cleared. > > Signed-off-by: Franklin S Cooper Jr > --- > drivers/mtd/nand/omap2.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c > index 957c32f..94d11de 100644 > --- a/drivers/mtd/nand/omap2.c > +++ b/drivers/mtd/nand/omap2.c > @@ -509,6 +509,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info > *mtd, void *addr, > tx->callback_param = &info->comp; > dmaengine_submit(tx); > > + init_completion(&info->comp); > + dma_async_issue_pending(info->dma); > + > /* configure and start prefetch transfer */ > ret = omap_prefetch_enable(info->gpmc_cs, > PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); > @@ -516,9 +519,6 @@ static inline int omap_nand_dma_transfer(struct mtd_info > *mtd, void *addr, > /* PFPW engine is busy, use cpu copy method */ > goto out_copy_unmap; > > - init_completion(&info->comp); > - dma_async_issue_pending(info->dma); > - > /* setup and start DMA using dma_addr */ Is the above comment misplaced after this change? > wait_for_completion(&info->comp); > tim = 0; > cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] mtd: nand: omap2: Support parsing dma channel information from DT
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Switch from dma_request_channel to allow passing dma channel
> information from DT rather than hardcoding a value.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
> ---
> drivers/mtd/nand/omap2.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index d0f2620..957c32f 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -1866,7 +1866,9 @@ static int omap_nand_probe(struct platform_device *pdev)
> dma_cap_zero(mask);
> dma_cap_set(DMA_SLAVE, mask);
> sig = OMAP24XX_DMA_GPMC;
> - info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
> + info->dma = dma_request_slave_channel_compat(mask,
> + omap_dma_filter_fn, &sig, pdev->dev.parent, "rxtx");
> +
> if (!info->dma) {
> dev_err(&pdev->dev, "DMA engine request failed\n");
> err = -ENXIO;
>
cheers,
-roger
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Re: [PATCH] ARM: dts: am437x-gp-evm: Add wakeup interrupt source for pixcir_i2c_ts
Vignesh,
On 14/10/15 12:12, Vignesh R wrote:
>
>
> On 10/14/2015 02:16 PM, Roger Quadros wrote:
>
>>
>> On 14/10/15 08:52, Vignesh R wrote:
>>> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
>>> state via pinctrl and IO daisy chain using generic wakeirq framework.
>>> With commit 3fffd1283927 ("i2c: allow specifying separate wakeup
>>> interrupt in device tree") i2c core allows optional wakeirq to be
>>> specified via device tree. Add wakeup irq entry to enable pixcir_i2c_ts
>>> to wake the system from low power state.
>>>
>>> Signed-off-by: Vignesh R
>>> ---
>>> arch/arm/boot/dts/am437x-gp-evm.dts | 5 +
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
>>> b/arch/arm/boot/dts/am437x-gp-evm.dts
>>> index 22038f21f228..69e93af7df0d 100644
>>> --- a/arch/arm/boot/dts/am437x-gp-evm.dts
>>> +++ b/arch/arm/boot/dts/am437x-gp-evm.dts
>>> @@ -581,8 +581,13 @@
>>>
>>> attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>>>
>>> + interrupts-extended = <&gpio3 22 GPIO_ACTIVE_HIGH>,
>>> + <&am43xx_pinmux 0x264>;
>>
>> How does this work?
>>
>> interrupts-extended property must have
>> 1) interrupt parent
>> 2) interrupt number
>> 3) interrupt flags
>>
>> Your change doesn't seem to comply with those requirements.
>
> AFAIU, interrupts-extended has two parts: interrupt parent phandle and
> interrupt specifier.
> The number of cells in interrupt specifier is determined by
> interrupt-cells property of interrupt parent node.
Got it.
> In above case, gpio3 has interrupt-cells = 2 hence interrupt specifier
> has interrupt number and interrupt flag field.
But is GPIO_ACTIVE_HIGH an interrupt flag?
> But in case am43xx_pinmux node, interrupt-cells is 1 hence has no
> interrupt flag field.
>
Understood, thanks. Might be worth adding a comment as to what 0x264 means
though.
cheers,
-roger
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[PATCH v4 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
v4: Applied Tony's patch to fix broken ethernet on torpedo.
updated v4 series available at
g...@github.com:rogerq/linux.git
* [branch] for-v4.4/gpmc-v4
arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 3 ++-
arch/arm/boot/dts/logicpd-torpedo-som.dtsi| 7 +--
arch/arm/boot/dts/omap3-beagle.dts| 2 ++
arch/arm/boot/dts/omap3-cm-t3x.dtsi | 5 -
arch/arm/boot/dts/omap3-devkit8000-common.dtsi| 3 +++
arch/arm/boot/dts/omap3-evm-37xx.dts | 7 +--
arch/arm/boot/dts/omap3-gta04.dtsi| 3 +++
arch/arm/boot/dts/omap3-igep.dtsi | 5 -
arch/arm/boot/dts/omap3-igep0020-common.dtsi | 4 ++--
arch/arm/boot/dts/omap3-igep0030-common.dtsi | 4
arch/arm/boot/dts/omap3-ldp.dts | 9 ++---
arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 5 -
arch/arm/boot/dts/omap3-pandora-common.dtsi | 3 +++
arch/arm/boot/dts/omap3-tao3530.dtsi | 5 -
arch/arm/boot/dts/omap3.dtsi | 4
arch/arm/boot/dts/omap3430-sdp.dts| 5 -
16 files changed, 59 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
index 91146c3..20e157d 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
@@ -73,7 +73,8 @@
};
&gpmc {
- ranges = <1 0 0x0800 0x100>;/* CS1: 16MB for LAN9221 */
+ ranges = <0 0 0x3000 0x100 /* CS0: 16MB for NAND */
+ 1 0 0x2c00 0x100>;/* CS1: 16MB for LAN9221 */
ethernet@gpmc {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 36387b1..f108e55 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -35,11 +35,14 @@
};
&gpmc {
- ranges = <0 0 0x 0x100>;/* CS0: 16MB for NAND */
+ ranges = <0 0 0x3000 0x100>;/* CS0: 16MB for NAND */
nand@0,0 {
- linux,mtd-name = "micron,mt29f4g16abbda3w";
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+ linux,mtd-name = "micron,mt29f4g16abbda3w";
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 67659a0..9b145dd 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -384,7 +384,9 @@
/* Chip select 0 */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
+ interrupt-parent = <&intc>;
interrupts = <20>;
ti,nand-ecc-opt = "ham1";
nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index 4d091ca..e9d7e28 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -261,10 +261,13 @@
};
&gpmc {
- ranges = <0 0 0x 0x0100>;
+ ranges = <0 0 0x3000 0x0100>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index 9ca2865..e7b46ad 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -204,7 +204,10 @@
ranges = <0 0 0x3000 0x100>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts
Re: [PATCH] ARM: dts: am437x-gp-evm: Add wakeup interrupt source for pixcir_i2c_ts
+Dave
On 14/10/15 08:52, Vignesh R wrote:
> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
> state via pinctrl and IO daisy chain using generic wakeirq framework.
> With commit 3fffd1283927 ("i2c: allow specifying separate wakeup
> interrupt in device tree") i2c core allows optional wakeirq to be
> specified via device tree. Add wakeup irq entry to enable pixcir_i2c_ts
> to wake the system from low power state.
>
> Signed-off-by: Vignesh R
> ---
> arch/arm/boot/dts/am437x-gp-evm.dts | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
> b/arch/arm/boot/dts/am437x-gp-evm.dts
> index 22038f21f228..69e93af7df0d 100644
> --- a/arch/arm/boot/dts/am437x-gp-evm.dts
> +++ b/arch/arm/boot/dts/am437x-gp-evm.dts
> @@ -581,8 +581,13 @@
>
> attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>
> + interrupts-extended = <&gpio3 22 GPIO_ACTIVE_HIGH>,
> + <&am43xx_pinmux 0x264>;
How does this work?
interrupts-extended property must have
1) interrupt parent
2) interrupt number
3) interrupt flags
Your change doesn't seem to comply with those requirements.
> + interrupt-names = "tsc", "wakeup";
> +
> touchscreen-size-x = <1024>;
> touchscreen-size-y = <600>;
> + wakeup-source;
> };
>
> ov2659@30 {
>
cheers,
-roger
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Re: [PATCH v3 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes
Tony,
On 13/10/15 18:18, Tony Lindgren wrote:
> * Roger Quadros [151012 23:33]:
>> On 13/10/15 03:43, Tony Lindgren wrote:
>>> * Roger Quadros [150918 08:00]:
>>>> Add compatible id, GPMC register resource and interrupt
>>>> resource to NAND controller nodes.
>>>>
>>>> The GPMC driver now implements gpiochip and irqchip so
>>>> enable gpio-controller and interrupt-controller properties.
>>>>
>>>> With this the interrupt parent of NAND node changes so fix it
>>>> accordingly.
>>> ...
>>>> --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>>>> +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>>>> @@ -35,11 +35,14 @@
>>>> };
>>>>
>>>> &gpmc {
>>>> - ranges = <0 0 0x 0x100>;/* CS0: 16MB for NAND */
>>>> + ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
>>>>
>>>>nand@0,0 {
>>>> - linux,mtd-name = "micron,mt29f4g16abbda3w";
>>>> + compatible = "ti,omap2-nand";
>>>>reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
>>>> + interrupt-parent = <&intc>;
>>>> + interrupts = <20>;
>>>> + linux,mtd-name = "micron,mt29f4g16abbda3w";
>>>>nand-bus-width = <16>;
>>>>ti,nand-ecc-opt = "bch8";
>>>>gpmc,sync-clk-ps = <0>;
>>>
>>> At least torpedo breaks for NFSroot as NAND now overlaps with
>>> Ethernet.. What's the policy you have for moving the addresses
>>> around?
>>
>> For OMAP3 I intended to use 0x3000 for NAND but incorrectly
>> used 0x0800 for the torpedo.
>
> Might be worth adding some documentation of suggested standardized
> mappings.. For most of theme we could just add them as 16MB chunks,
> then reserve some larger area for NOR?
As GPMC peripherals are not plug and play the GPMC map is specific to
the board and need not necessarily apply to all boards.
So I don't think we need to have any standardized mappings.
>
>> Does setting it to 0x3000 work? If not what is the original
>> NAND address for this board?
>
> The u-boot addresses are probably what were used in the .dts* files.
> Setting NAND to 0x3000 is not enough though, looks like there's
> a bug where the logicpd-torpedo-37xx-devkit.dts ranges is missing
> the NAND range in logicpd-torpedo-som.dtsi. Something like the
> patch below seems to make things work again, might be worth
> checking what ranges make sense to standardize on though. Please
> feel free to fold it into your patches.
Thanks. I'll post a revised patch.
>
>>> There may be other similar cases to check too.
>>
>> Just checked that all other OMAP3 boards I've set to 0x3000
>> if they were 0x0.
>
> Do you want to reserve a large chunk for NOR at cs0 or what's
> the reason for picking 0x3000 for NAND?
All of the OMAP3 boards were using 0x3000. Probably copy paste effect? :)
What's the point of reserving anything for NOR. If the board doesn't already
have NOR it never will. Future board having NOR can have its own GPMC map.
>
> I guess NOR can be also on other chipselects.. Not sure we can
> standardize on any specific partition scheme?
Exactly.
cheers,
-roger
>
> Regards,
>
> Tony
>
> 8<
> --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
> +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
> @@ -73,7 +73,8 @@
> };
>
> &gpmc {
> - ranges = <1 0 0x0800 0x100>;/* CS1: 16MB for LAN9221 */
> + ranges = <0 0 0x3000 0x100 /* CS0: 16MB for NAND */
> + 1 0 0x2c00 0x100>;/* CS1: 16MB for LAN9221 */
>
> ethernet@gpmc {
> pinctrl-names = "default";
> --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
> +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
> @@ -35,7 +35,7 @@
> };
>
> &gpmc {
> - ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
> + ranges = <0 0 0x3000 0x100>;/* CS0: 16MB for NAND */
>
> nand@0,0 {
> compatible = "ti,omap2-nand";
>
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Re: [PATCH] mfd: omap-usb-host: AM3715 OHCI needs 120m functional clock
Ben,
On 13/10/15 11:23, Ben Dooks wrote:
> On 12/10/15 20:19, Tony Lindgren wrote:
>> * Ben Dooks [151012 11:22]:
>>> On 12/10/15 18:45, Tony Lindgren wrote:
* Ben Dooks [151012 10:38]:
> The AM3715 OHCI controller will not function without the EHCI
> unit's 120m fclk being enabled. If all the ports in the system
> are set to OHCI then the 120m_fclk will not get enabled and no
> devices are detected.
>
> Add a new (optional) property to signal the system must enable
> the 120m_fck for OHCI so that if no EHCI ports are signalled
> then the 120m_fclk should be enabled.
>
> We have found no information about why this is necessary, but
> it is suspected the EHCI controller does not complete the initial
> reset sequence and therefore does not hand control of the USB
> port back.
>
> Signed-off-by: Ben Dooks
> ---
> Documentation/devicetree/bindings/usb/omap-usb.txt | 3 +++
> drivers/mfd/omap-usb-host.c| 4
> 2 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
> b/Documentation/devicetree/bindings/usb/omap-usb.txt
> index 38d9bb8..fb5fea5 100644
> --- a/Documentation/devicetree/bindings/usb/omap-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
> @@ -23,6 +23,9 @@ OMAP MUSB GLUE
> Optional properties:
> - ctrl-module : phandle of the control module this glue uses to write to
> mailbox
> + - ti,ohci-needs-120m-fck : bool, enable the 120m ehci clock even if just
> + using ohci. Needed for AM3517 in OHCI only mode.
> +
>
> SOC specific device node entry
> usb_otg_hs: usb_otg_hs@4a0ab000 {
> diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
> index 1d924d1..13880cf 100644
> --- a/drivers/mfd/omap-usb-host.c
> +++ b/drivers/mfd/omap-usb-host.c
> @@ -680,6 +680,10 @@ static int usbhs_omap_probe(struct platform_device
> *pdev)
> need_logic_fck |= true;
> }
>
> + /* The AM3517 requries the 120m-fck active to allow the OHCI to
> work */
> + if (of_property_read_bool(dev->of_node,
> "ti,ohci-needs-120m-fck"))
> + need_logic_fck |= true;
> +
> if (need_logic_fck) {
> omap->ehci_logic_fck = devm_clk_get(dev,
> "usbhost_120m_fck");
Hmm why not just use the standard device tree clocks property and then do
clk_get_rate() on the clock?
>>>
>>> I don't see that helps enabling the clock. The code decideds if
>>> no EHCI ports in use that it doesn't need to enable the EHCI fclk.
>>
>> Right, you need to do clk_prepare_enable() in it first? :)
>
> No, if that was the case the driver would never work for the EHCI case.
>
> The issue is:
>
> 1) All ports on the system are set to OHCI
> 2) The omap-usb-host.c does not touch usbhost_120m_fck if no EHCI ports
> 3) The OHCI fails to detect any devices due to point 2.
>
Instead of your existing approach why not just modify the preceeding
if condition that sets need_logic_fck to suit the OHCI case.
That way you don't need to add a new DT binding.
The old assumption was that 120m_fck logic clock is only needed for
EHCI mode but it looks like OHCI mode needs it as well.
You should also rename omap->ehci_logic_fck to omap->hci_logic_fck
as it is no longer ehci specific.
cheers,
-roger
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Re: [PATCH v3 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes
On 13/10/15 03:43, Tony Lindgren wrote:
> * Roger Quadros [150918 08:00]:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller and interrupt-controller properties.
>>
>> With this the interrupt parent of NAND node changes so fix it
>> accordingly.
> ...
>> --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>> +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>> @@ -35,11 +35,14 @@
>> };
>>
>> &gpmc {
>> -ranges = <0 0 0x 0x100>;/* CS0: 16MB for NAND */
>> +ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
>>
>> nand@0,0 {
>> -linux,mtd-name = "micron,mt29f4g16abbda3w";
>> +compatible = "ti,omap2-nand";
>> reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
>> +interrupt-parent = <&intc>;
>> +interrupts = <20>;
>> +linux,mtd-name = "micron,mt29f4g16abbda3w";
>> nand-bus-width = <16>;
>> ti,nand-ecc-opt = "bch8";
>> gpmc,sync-clk-ps = <0>;
>
> At least torpedo breaks for NFSroot as NAND now overlaps with
> Ethernet.. What's the policy you have for moving the addresses
> around?
For OMAP3 I intended to use 0x3000 for NAND but incorrectly
used 0x0800 for the torpedo.
Does setting it to 0x3000 work? If not what is the original
NAND address for this board?
>
> There may be other similar cases to check too.
Just checked that all other OMAP3 boards I've set to 0x3000
if they were 0x0.
cheers,
-roger
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Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 06/10/15 14:01, Tony Lindgren wrote: > * Roger Quadros [151006 03:32]: >> On 06/10/15 13:05, Roger Quadros wrote: >>> On 06/10/15 13:00, Tony Lindgren wrote: >>>> * Roger Quadros [151006 02:59]: >>>>> On 06/10/15 11:33, Tony Lindgren wrote: >>>>>> Does build and boot and use NAND work throughtout the series? >>>>>> Otherwise we'll have hard time bisecting anything.. >>>>> >>>>> Yes it does with the following exceptions. >>>>> >>>>> - Patch 7 "memory: omap-gpmc: Remove NAND IRQ code" breaks prefetch-irq >>>>> mode >>>>> but none of the boards seem to be using it so it shouldn't break NAND on >>>>> existing boards. >>>>> At patch 9 "mtd: nand: omap2: manage NAND interrupts" prefetch-irq mode >>>>> is working again. >>>>> Do you want me to squash patches 7,8,9 so that pre-fetch irq is not >>>>> broken at any point? >>>> >>>> OK, no that's fine, no need to squash them together then. >>>> >>>>> - Then at patch 11 "mtd: nand: omap: Clean up device tree support" we >>>>> break NAND on all DT >>>>> boards as we expect NAND to be a real child node with compatible id. >>>>> Simply applying the >>>>> DT patch at this point makes it work again. >>>> >>>> Hmm can we at least warn about incompatible DT entry when somebody boots >>>> with an older dtb? >>> >>> Yes that could be done. It looks like we can use the missing compatible >>> property to identify >>> that it is and old DT entry. >>> >>> I'll send a v4 of patch 11. >> >> There is another issue. Some of the old DT nodes set the NAND IO address to >> 0. >> As we prevent mapping into first 16MB we see the following message for those >> nodes. e.g. dra7-evm >> >> [1.727598] omap-gpmc 5000.gpmc: cannot remap GPMC CS 0 to 0x >> [1.727605] omap-gpmc 5000.gpmc: GPMC CS 0 start cannot be lesser >> than 0x100 >> [1.727611] omap-gpmc 5000.gpmc: failed to probe DT children >> >> Hope this is good enough information that DT needs to be updated? > > Yes I think that should allow users update the out of tree dts file > easily. Fine. The updated series is now at g...@github.com:rogerq/linux.git * [new branch] for-v4.4/gpmc-v4 cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 11/27] mtd: nand: omap: Clean up device tree support
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
v4: Warn if using older incompatible DT i.e. compatible property not present
in nand node.
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 143 +++
drivers/mtd/nand/omap2.c | 136 +
include/linux/platform_data/mtd-nand-omap2.h | 3 +-
4 files changed, 155 insertions(+), 132 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index ffe646a..e07ca27 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -95,10 +95,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_nand_res[1].start = gpmc_get_irq();
memset(&s, 0, sizeof(struct gpmc_settings));
- if (gpmc_nand_data->of_node)
- gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
- else
- gpmc_set_legacy(gpmc_nand_data, &s);
+ gpmc_set_legacy(gpmc_nand_data, &s);
s.device_nand = true;
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index e75226d..318c187 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -29,7 +29,6 @@
#include
#include
#include
-#include
#include
#include
@@ -1716,105 +1715,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
of_property_read_bool(np, "gpmc,time-para-granularity");
}
-#if IS_ENABLED(CONFIG_MTD_NAND)
-
-static const char * const nand_xfer_types[] = {
- [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
- [NAND_OMAP_POLLED] = "polled",
- [NAND_OMAP_PREFETCH_DMA]= "prefetch-dma",
- [NAND_OMAP_PREFETCH_IRQ]= "prefetch-irq",
-};
-
-static int gpmc_probe_nand_child(struct platform_device *pdev,
-struct device_node *child)
-{
- u32 val;
- const char *s;
- struct gpmc_timings gpmc_t;
- struct omap_nand_platform_data *gpmc_nand_data;
-
- if (of_property_read_u32(child, "reg", &val) < 0) {
- dev_err(&pdev->dev, "%s has no 'reg' property\n",
- child->full_name);
- return -ENODEV;
- }
-
- gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
- GFP_KERNEL);
- if (!gpmc_nand_data)
- return -ENOMEM;
-
- gpmc_nand_data->cs = val;
- gpmc_nand_data->of_node = child;
-
- /* Detect availability of ELM module */
- gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
- if (gpmc_nand_data->elm_of_node == NULL)
- gpmc_nand_data->elm_of_node =
- of_parse_phandle(child, "elm_id", 0);
-
- /* select ecc-scheme for NAND */
- if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
- pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
- return -ENODEV;
- }
-
- if (!strcmp(s, "sw"))
- gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
- else if (!strcmp(s, "ham1") ||
-!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_HAM1_CODE_HW;
- else if (!strcmp(s, "bch4"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch8"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch16"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH16_CODE_HW;
- else
- pr_err("%s: BCH16 requires ELM support\n", __func__);
- else
- pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
-
- /* select data transfer mode for NAND controller */
-
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 06/10/15 13:05, Roger Quadros wrote: > On 06/10/15 13:00, Tony Lindgren wrote: >> * Roger Quadros [151006 02:59]: >>> On 06/10/15 11:33, Tony Lindgren wrote: >>>> Does build and boot and use NAND work throughtout the series? >>>> Otherwise we'll have hard time bisecting anything.. >>> >>> Yes it does with the following exceptions. >>> >>> - Patch 7 "memory: omap-gpmc: Remove NAND IRQ code" breaks prefetch-irq mode >>> but none of the boards seem to be using it so it shouldn't break NAND on >>> existing boards. >>> At patch 9 "mtd: nand: omap2: manage NAND interrupts" prefetch-irq mode is >>> working again. >>> Do you want me to squash patches 7,8,9 so that pre-fetch irq is not broken >>> at any point? >> >> OK, no that's fine, no need to squash them together then. >> >>> - Then at patch 11 "mtd: nand: omap: Clean up device tree support" we break >>> NAND on all DT >>> boards as we expect NAND to be a real child node with compatible id. Simply >>> applying the >>> DT patch at this point makes it work again. >> >> Hmm can we at least warn about incompatible DT entry when somebody boots >> with an older dtb? > > Yes that could be done. It looks like we can use the missing compatible > property to identify > that it is and old DT entry. > > I'll send a v4 of patch 11. There is another issue. Some of the old DT nodes set the NAND IO address to 0. As we prevent mapping into first 16MB we see the following message for those nodes. e.g. dra7-evm [1.727598] omap-gpmc 5000.gpmc: cannot remap GPMC CS 0 to 0x [1.727605] omap-gpmc 5000.gpmc: GPMC CS 0 start cannot be lesser than 0x100 [1.727611] omap-gpmc 5000.gpmc: failed to probe DT children Hope this is good enough information that DT needs to be updated? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 06/10/15 13:00, Tony Lindgren wrote: > * Roger Quadros [151006 02:59]: >> On 06/10/15 11:33, Tony Lindgren wrote: >>> Does build and boot and use NAND work throughtout the series? >>> Otherwise we'll have hard time bisecting anything.. >> >> Yes it does with the following exceptions. >> >> - Patch 7 "memory: omap-gpmc: Remove NAND IRQ code" breaks prefetch-irq mode >> but none of the boards seem to be using it so it shouldn't break NAND on >> existing boards. >> At patch 9 "mtd: nand: omap2: manage NAND interrupts" prefetch-irq mode is >> working again. >> Do you want me to squash patches 7,8,9 so that pre-fetch irq is not broken >> at any point? > > OK, no that's fine, no need to squash them together then. > >> - Then at patch 11 "mtd: nand: omap: Clean up device tree support" we break >> NAND on all DT >> boards as we expect NAND to be a real child node with compatible id. Simply >> applying the >> DT patch at this point makes it work again. > > Hmm can we at least warn about incompatible DT entry when somebody boots > with an older dtb? Yes that could be done. It looks like we can use the missing compatible property to identify that it is and old DT entry. I'll send a v4 of patch 11. cheers, -roger > >>>> Test procedure was to read an existing ubifs partition, >>>> create a new one and read it back. >>>> >>>> Need you to Ack if it looks good. >>>> Do you mind taking it via omap-soc once MTD maintainers ack their relevant >>>> parts? >>> >>> Sure. I'll try to do some testing on the series first too. >>> >> Thanks. >> >>> Can the dts changes be merged separtely? Otherwise we'll have >>> a dependency between dts branch and the GPMC/NAND changes. >> >> I'm afraid no. Patch 11 makes us incompatible with the old DT. > > OK. If we can warn about that, then the out of tree users will > have easier time to update their dts file. > > Regards, > > Tony > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 06/10/15 11:33, Tony Lindgren wrote: > * Roger Quadros [150930 04:04]: >> Tony, >> >> On 18/09/15 17:53, Roger Quadros wrote: >>> Hi, >>> >>> We do a couple of things in this series which result in >>> cleaner device tree implementation, faster perfomance and >>> multi-platform support. As an added bonus we get new GPI/Interrupt pins >>> for use in the system. >>> >>> - Establish a custom interface between NAND and GPMC driver. This is >>> needed because all of the NAND registers sit in the GPMC register space. >>> Some bits like NAND IRQ are even shared with GPMC. >>> >>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >>> This causes performance increase when using prefetch-irq mode. >>> 30% increase in read, 17% increase in write in prefetch-irq mode. >>> >>> - Clean up device tree support so that omap-gpmc IP and the omap2 NAND >>> driver can be used on non-OMAP platforms. e.g. Keystone. >>> >>> - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain >>> 2 to 4 of these and most of them would be unused otherwise. It also >>> allows a cleaner implementation of NAND Ready pin status for the NAND >>> driver. >>> >>> - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. >>> >>> This series is available at >>> g...@github.com:rogerq/linux.git >>> in branch >>> for-v4.4/gpmc-v3 > > In general, very nice work :) Thanks :) > >> I've verified this series with the following boards >> -dra7-evm >> -am437x-gp-evm >> -am335x-evm >> -beagleboard-c4 >> >> For legacy boot I've checked only on beagleboard-c4. > > Great. > > Does build and boot and use NAND work throughtout the series? > Otherwise we'll have hard time bisecting anything.. Yes it does with the following exceptions. - Patch 7 "memory: omap-gpmc: Remove NAND IRQ code" breaks prefetch-irq mode but none of the boards seem to be using it so it shouldn't break NAND on existing boards. At patch 9 "mtd: nand: omap2: manage NAND interrupts" prefetch-irq mode is working again. Do you want me to squash patches 7,8,9 so that pre-fetch irq is not broken at any point? - Then at patch 11 "mtd: nand: omap: Clean up device tree support" we break NAND on all DT boards as we expect NAND to be a real child node with compatible id. Simply applying the DT patch at this point makes it work again. > >> Test procedure was to read an existing ubifs partition, >> create a new one and read it back. >> >> Need you to Ack if it looks good. >> Do you mind taking it via omap-soc once MTD maintainers ack their relevant >> parts? > > Sure. I'll try to do some testing on the series first too. > Thanks. > Can the dts changes be merged separtely? Otherwise we'll have > a dependency between dts branch and the GPMC/NAND changes. I'm afraid no. Patch 11 makes us incompatible with the old DT. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Tony, On 18/09/15 17:53, Roger Quadros wrote: > Hi, > > We do a couple of things in this series which result in > cleaner device tree implementation, faster perfomance and > multi-platform support. As an added bonus we get new GPI/Interrupt pins > for use in the system. > > - Establish a custom interface between NAND and GPMC driver. This is > needed because all of the NAND registers sit in the GPMC register space. > Some bits like NAND IRQ are even shared with GPMC. > > - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ > with the omap2-nand driver and handle NAND IRQ events in the NAND driver. > This causes performance increase when using prefetch-irq mode. > 30% increase in read, 17% increase in write in prefetch-irq mode. > > - Clean up device tree support so that omap-gpmc IP and the omap2 NAND > driver can be used on non-OMAP platforms. e.g. Keystone. > > - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain > 2 to 4 of these and most of them would be unused otherwise. It also > allows a cleaner implementation of NAND Ready pin status for the NAND driver. > > - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. > > This series is available at > g...@github.com:rogerq/linux.git > in branch > for-v4.4/gpmc-v3 I've verified this series with the following boards -dra7-evm -am437x-gp-evm -am335x-evm -beagleboard-c4 For legacy boot I've checked only on beagleboard-c4. Test procedure was to read an existing ubifs partition, create a new one and read it back. Need you to Ack if it looks good. Do you mind taking it via omap-soc once MTD maintainers ack their relevant parts? cheers, -roger > > Changelog: > v3: > -Fixed and tested NAND using legacy boot on omap3-beagle. > -Support rising and falling edge interrupts on WAITpins. > -Update DT node of all gpmc users. > > Roger Quadros (27): > ARM: OMAP2+: gpmc: Add platform data > ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data > memory: omap-gpmc: Introduce GPMC to NAND interface > mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers > memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status > mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty > check > memory: omap-gpmc: Remove NAND IRQ code > memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface > mtd: nand: omap2: manage NAND interrupts > mtd: nand: omap: Copy platform data parameters to omap_nand_info data > mtd: nand: omap: Clean up device tree support > mtd: nand: omap: Update DT binding documentation > memory: omap-gpmc: Prevent mapping into 1st 16MB > memory: omap-gpmc: Move device tree binding to correct location > memory: omap-gpmc: Support general purpose input for WAITPINs > memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring > memory: omap-gpmc: Add irqchip support to the gpiochip > mtd: nand: omap2: Implement NAND ready using gpiolib > memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via > gpmc_regs > ARM: dts: dra7: Fix NAND device nodes. > ARM: dts: dra7x-evm: Provide NAND ready pin > ARM: dts: am437x: Fix NAND device nodes > ARM: dts: am437x-gp-evm: Provide NAND ready pin > ARM: dts: am335x: Fix NAND device nodes > ARM: dts: am335x: Provide NAND ready pin > ARM: dts: dm816x: Fix gpmc and NAND node > ARM: dts: omap3: Fix gpmc and NAND nodes > > Documentation/devicetree/bindings/bus/ti-gpmc.txt | 130 - > .../bindings/memory-controllers/omap-gpmc.txt | 130 + > .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- > arch/arm/boot/dts/am335x-chilisom.dtsi | 7 +- > arch/arm/boot/dts/am335x-evm.dts | 7 +- > arch/arm/boot/dts/am335x-igep0033.dtsi | 7 +- > arch/arm/boot/dts/am33xx.dtsi | 4 + > arch/arm/boot/dts/am4372.dtsi | 4 + > arch/arm/boot/dts/am437x-gp-evm.dts| 8 +- > arch/arm/boot/dts/am43x-epos-evm.dts | 8 +- > arch/arm/boot/dts/dm8168-evm.dts | 7 +- > arch/arm/boot/dts/dm816x.dtsi | 4 + > arch/arm/boot/dts/dra7-evm.dts | 6 +- > arch/arm/boot/dts/dra7.dtsi| 4 + > arch/arm/boot/dts/dra72-evm.dts| 6 +- > arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +- > arch/arm/boot/dts/omap3-beagle.dts | 2 + > arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 +- > arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 + > arch/arm/boot/dts/omap3-evm-37xx.dts | 7 +- > arch/ar
Re: [PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Brian/David, On 18/09/15 17:53, Roger Quadros wrote: > Hi, > > We do a couple of things in this series which result in > cleaner device tree implementation, faster perfomance and > multi-platform support. As an added bonus we get new GPI/Interrupt pins > for use in the system. > > - Establish a custom interface between NAND and GPMC driver. This is > needed because all of the NAND registers sit in the GPMC register space. > Some bits like NAND IRQ are even shared with GPMC. > > - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ > with the omap2-nand driver and handle NAND IRQ events in the NAND driver. > This causes performance increase when using prefetch-irq mode. > 30% increase in read, 17% increase in write in prefetch-irq mode. > > - Clean up device tree support so that omap-gpmc IP and the omap2 NAND > driver can be used on non-OMAP platforms. e.g. Keystone. > > - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain > 2 to 4 of these and most of them would be unused otherwise. It also > allows a cleaner implementation of NAND Ready pin status for the NAND driver. > > - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. > > This series is available at > g...@github.com:rogerq/linux.git > in branch > for-v4.4/gpmc-v3 Could you please ack the patches affecting the omap2 nand driver? These would be patches 4, 6, 9, 10, 11, 12, 18. Thanks. cheers, -roger > > Changelog: > v3: > -Fixed and tested NAND using legacy boot on omap3-beagle. > -Support rising and falling edge interrupts on WAITpins. > -Update DT node of all gpmc users. > > Roger Quadros (27): > ARM: OMAP2+: gpmc: Add platform data > ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data > memory: omap-gpmc: Introduce GPMC to NAND interface > mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers > memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status > mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty > check > memory: omap-gpmc: Remove NAND IRQ code > memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface > mtd: nand: omap2: manage NAND interrupts > mtd: nand: omap: Copy platform data parameters to omap_nand_info data > mtd: nand: omap: Clean up device tree support > mtd: nand: omap: Update DT binding documentation > memory: omap-gpmc: Prevent mapping into 1st 16MB > memory: omap-gpmc: Move device tree binding to correct location > memory: omap-gpmc: Support general purpose input for WAITPINs > memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring > memory: omap-gpmc: Add irqchip support to the gpiochip > mtd: nand: omap2: Implement NAND ready using gpiolib > memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via > gpmc_regs > ARM: dts: dra7: Fix NAND device nodes. > ARM: dts: dra7x-evm: Provide NAND ready pin > ARM: dts: am437x: Fix NAND device nodes > ARM: dts: am437x-gp-evm: Provide NAND ready pin > ARM: dts: am335x: Fix NAND device nodes > ARM: dts: am335x: Provide NAND ready pin > ARM: dts: dm816x: Fix gpmc and NAND node > ARM: dts: omap3: Fix gpmc and NAND nodes > > Documentation/devicetree/bindings/bus/ti-gpmc.txt | 130 - > .../bindings/memory-controllers/omap-gpmc.txt | 130 + > .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- > arch/arm/boot/dts/am335x-chilisom.dtsi | 7 +- > arch/arm/boot/dts/am335x-evm.dts | 7 +- > arch/arm/boot/dts/am335x-igep0033.dtsi | 7 +- > arch/arm/boot/dts/am33xx.dtsi | 4 + > arch/arm/boot/dts/am4372.dtsi | 4 + > arch/arm/boot/dts/am437x-gp-evm.dts| 8 +- > arch/arm/boot/dts/am43x-epos-evm.dts | 8 +- > arch/arm/boot/dts/dm8168-evm.dts | 7 +- > arch/arm/boot/dts/dm816x.dtsi | 4 + > arch/arm/boot/dts/dra7-evm.dts | 6 +- > arch/arm/boot/dts/dra7.dtsi| 4 + > arch/arm/boot/dts/dra72-evm.dts| 6 +- > arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +- > arch/arm/boot/dts/omap3-beagle.dts | 2 + > arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 +- > arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 + > arch/arm/boot/dts/omap3-evm-37xx.dts | 7 +- > arch/arm/boot/dts/omap3-gta04.dtsi | 3 + > arch/arm/boot/dts/omap3-igep.dtsi | 5 +- > arch/arm/boot/dts/omap3-igep0020-common.dtsi | 4 +- > arch/arm/boot/dts/omap3-igep0030-common.dtsi | 4 + > arc
[PATCH v3 02/27] ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 ---
include/linux/platform_data/gpmc-omap.h | 137
2 files changed, 137 insertions(+), 134 deletions(-)
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 5c79190..2dcef1c 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -14,140 +14,6 @@
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
-#define GPMC_BURST_4 4 /* 4 word burst */
-#define GPMC_BURST_8 8 /* 8 word burst */
-#define GPMC_BURST_16 16 /* 16 word burst */
-#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
-#define GPMC_DEVWIDTH_16BIT2 /* 16-bit device width */
-#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
-#define GPMC_MUX_AD2 /* Addr-Data multiplex */
-
-/* bool type time settings */
-struct gpmc_bool_timings {
- bool cycle2cyclediffcsen;
- bool cycle2cyclesamecsen;
- bool we_extra_delay;
- bool oe_extra_delay;
- bool adv_extra_delay;
- bool cs_extra_delay;
- bool time_para_granularity;
-};
-
-/*
- * Note that all values in this struct are in nanoseconds except sync_clk
- * (which is in picoseconds), while the register values are in gpmc_fck cycles.
- */
-struct gpmc_timings {
- /* Minimum clock period for synchronous mode (in picoseconds) */
- u32 sync_clk;
-
- /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
- u32 cs_on; /* Assertion time */
- u32 cs_rd_off; /* Read deassertion time */
- u32 cs_wr_off; /* Write deassertion time */
-
- /* ADV signal timings corresponding to GPMC_CONFIG3 */
- u32 adv_on; /* Assertion time */
- u32 adv_rd_off; /* Read deassertion time */
- u32 adv_wr_off; /* Write deassertion time */
-
- /* WE signals timings corresponding to GPMC_CONFIG4 */
- u32 we_on; /* WE assertion time */
- u32 we_off; /* WE deassertion time */
-
- /* OE signals timings corresponding to GPMC_CONFIG4 */
- u32 oe_on; /* OE assertion time */
- u32 oe_off; /* OE deassertion time */
-
- /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
- u32 page_burst_access; /* Multiple access word delay */
- u32 access; /* Start-cycle to first data valid delay */
- u32 rd_cycle; /* Total read cycle time */
- u32 wr_cycle; /* Total write cycle time */
-
- u32 bus_turnaround;
- u32 cycle2cycle_delay;
-
- u32 wait_monitoring;
- u32 clk_activation;
-
- /* The following are only on OMAP3430 */
- u32 wr_access; /* WRACCESSTIME */
- u32 wr_data_mux_bus;/* WRDATAONADMUXBUS */
-
- struct gpmc_bool_timings bool_timings;
-};
-
-/* Device timings in picoseconds */
-struct gpmc_device_timings {
- u32 t_ceasu;/* address setup to CS valid */
- u32 t_avdasu; /* address setup to ADV valid */
- /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
-* of tusb using these timings even for sync whilst
-* ideally for adv_rd/(wr)_off it should have considered
-* t_avdh instead. This indirectly necessitates r/w
-* variations of t_avdp as it is possible to have one
-* sync & other async
-*/
- u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
- u32 t_avdp_w;
- u32 t_aavdh;/* address hold time */
- u32 t_oeasu;/* address setup to OE valid */
- u32 t_aa; /* access time from ADV assertion */
- u32 t_iaa; /* initial access time */
- u32 t_oe; /* access time from OE assertion */
- u32 t_ce; /* access time from CS asertion */
- u32 t_rd_cycle; /* read cycle time */
- u32 t_cez_r;/* read CS deassertion to high Z */
- u32 t_cez_w;/* write CS deassertion to high Z */
- u32 t_oez; /* OE deassertion to high Z */
- u32 t_weasu;/* address setup to WE valid */
- u32 t_wpl; /* write assertion time */
- u32 t_wph; /* write deassertion time */
- u32 t_wr_cycle; /* write cycle time */
-
- u32 clk;
- u32 t_bacc; /* burst access valid clock to output delay */
- u32 t_ces; /* CS setup time to clk */
- u32 t_avds; /* ADV setup time to clk */
- u32 t_avdh; /* ADV hold time from clk */
- u32 t_ach; /* address hold time from clk */
- u32 t_rdyo; /* clk to ready valid */
-
- u32 t_ce_rdyz; /* XXX: description ?, or use t_cez
[PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Hi, We do a couple of things in this series which result in cleaner device tree implementation, faster perfomance and multi-platform support. As an added bonus we get new GPI/Interrupt pins for use in the system. - Establish a custom interface between NAND and GPMC driver. This is needed because all of the NAND registers sit in the GPMC register space. Some bits like NAND IRQ are even shared with GPMC. - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ with the omap2-nand driver and handle NAND IRQ events in the NAND driver. This causes performance increase when using prefetch-irq mode. 30% increase in read, 17% increase in write in prefetch-irq mode. - Clean up device tree support so that omap-gpmc IP and the omap2 NAND driver can be used on non-OMAP platforms. e.g. Keystone. - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain 2 to 4 of these and most of them would be unused otherwise. It also allows a cleaner implementation of NAND Ready pin status for the NAND driver. - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. This series is available at g...@github.com:rogerq/linux.git in branch for-v4.4/gpmc-v3 cheers, -roger Changelog: v3: -Fixed and tested NAND using legacy boot on omap3-beagle. -Support rising and falling edge interrupts on WAITpins. -Update DT node of all gpmc users. Roger Quadros (27): ARM: OMAP2+: gpmc: Add platform data ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data memory: omap-gpmc: Introduce GPMC to NAND interface mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty check memory: omap-gpmc: Remove NAND IRQ code memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface mtd: nand: omap2: manage NAND interrupts mtd: nand: omap: Copy platform data parameters to omap_nand_info data mtd: nand: omap: Clean up device tree support mtd: nand: omap: Update DT binding documentation memory: omap-gpmc: Prevent mapping into 1st 16MB memory: omap-gpmc: Move device tree binding to correct location memory: omap-gpmc: Support general purpose input for WAITPINs memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring memory: omap-gpmc: Add irqchip support to the gpiochip mtd: nand: omap2: Implement NAND ready using gpiolib memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs ARM: dts: dra7: Fix NAND device nodes. ARM: dts: dra7x-evm: Provide NAND ready pin ARM: dts: am437x: Fix NAND device nodes ARM: dts: am437x-gp-evm: Provide NAND ready pin ARM: dts: am335x: Fix NAND device nodes ARM: dts: am335x: Provide NAND ready pin ARM: dts: dm816x: Fix gpmc and NAND node ARM: dts: omap3: Fix gpmc and NAND nodes Documentation/devicetree/bindings/bus/ti-gpmc.txt | 130 - .../bindings/memory-controllers/omap-gpmc.txt | 130 + .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- arch/arm/boot/dts/am335x-chilisom.dtsi | 7 +- arch/arm/boot/dts/am335x-evm.dts | 7 +- arch/arm/boot/dts/am335x-igep0033.dtsi | 7 +- arch/arm/boot/dts/am33xx.dtsi | 4 + arch/arm/boot/dts/am4372.dtsi | 4 + arch/arm/boot/dts/am437x-gp-evm.dts| 8 +- arch/arm/boot/dts/am43x-epos-evm.dts | 8 +- arch/arm/boot/dts/dm8168-evm.dts | 7 +- arch/arm/boot/dts/dm816x.dtsi | 4 + arch/arm/boot/dts/dra7-evm.dts | 6 +- arch/arm/boot/dts/dra7.dtsi| 4 + arch/arm/boot/dts/dra72-evm.dts| 6 +- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +- arch/arm/boot/dts/omap3-beagle.dts | 2 + arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 +- arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 + arch/arm/boot/dts/omap3-evm-37xx.dts | 7 +- arch/arm/boot/dts/omap3-gta04.dtsi | 3 + arch/arm/boot/dts/omap3-igep.dtsi | 5 +- arch/arm/boot/dts/omap3-igep0020-common.dtsi | 4 +- arch/arm/boot/dts/omap3-igep0030-common.dtsi | 4 + arch/arm/boot/dts/omap3-ldp.dts| 9 +- arch/arm/boot/dts/omap3-lilly-a83x.dtsi| 5 +- arch/arm/boot/dts/omap3-pandora-common.dtsi| 3 + arch/arm/boot/dts/omap3-tao3530.dtsi | 5 +- arch/arm/boot/dts/omap3.dtsi | 4 + arch/arm/boot/dts/omap3430-sdp.dts | 5 +- arch/arm/mach-omap2/gpmc-nand.c| 11 +- drivers/memory/omap-gpmc.c | 640 - drivers/mtd/nand/omap2.c | 261 ++--- include/linux/omap-gpmc.h | 183 ++ include/linux
[PATCH v3 03/27] memory: omap-gpmc: Introduce GPMC to NAND interface
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1) FIFOEVENT and TERMCOUNT from GPMC_IRQENABLE and GPMC_IRQSTATUS
2) EMPTYWRITEBUFFERSTATUS from GPMC_STATUS
For accessing these bits we introduce the struct gpmc_nand_ops.
Rename the gpmc_update_nand_reg() API to gpmc_omap_get_nand_ops()
and make it return the gpmc_nand_ops along with updating the
gpmc_nand_regs. This API will be called by the OMAP NAND driver
to access the necessary bits in GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 21
include/linux/omap-gpmc.h | 49 --
2 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 32ac049..a80c53e 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1099,6 +1099,27 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg,
int cs)
}
}
+static struct gpmc_nand_ops nand_ops;
+
+/**
+ * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
+ * @regs: the GPMC NAND register map exclusive for NAND use.
+ * @cs: GPMC chip select number on which the NAND sits. The
+ * register map returned will be specific to this chip select.
+ *
+ * Returns NULL on error e.g. invalid cs.
+ */
+struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int
cs)
+{
+ if (cs >= gpmc_cs_num)
+ return NULL;
+
+ gpmc_update_nand_reg(reg, cs);
+
+ return &nand_ops;
+}
+EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
+
int gpmc_get_client_irq(unsigned irq_config)
{
int i;
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 2dcef1c..7de9f9b 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -14,14 +14,59 @@
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
+enum gpmc_nand_irq {
+ GPMC_NAND_IRQ_FIFOEVENT = 0,
+ GPMC_NAND_IRQ_TERMCOUNT,
+};
+
+/**
+ * gpmc_nand_ops - Interface between NAND and GPMC
+ * @nand_irq_enable: enable the requested GPMC NAND interrupt event.
+ * @nand_irq_disable: disable the requested GPMC NAND interrupt event.
+ * @nand_irq_clear: clears the GPMC NAND interrupt event status.
+ * @nand_irq_status: get the NAND interrupt event status.
+ * @nand_write_buffer_empty: get the NAND write buffer empty status.
+ */
+struct gpmc_nand_ops {
+ int (*nand_irq_enable)(enum gpmc_nand_irq irq);
+ int (*nand_irq_disable)(enum gpmc_nand_irq irq);
+ void (*nand_irq_clear)(enum gpmc_nand_irq irq);
+ u32 (*nand_irq_status)(void);
+ bool (*nand_writebuffer_empty)(void);
+};
+
+struct gpmc_nand_regs;
+
+#if IS_ENABLED(CONFIG_OMAP_GPMC)
+struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
+int cs);
+#else
+static inline gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs
*regs,
+ int cs)
+{
+ return NULL;
+}
+#endif /* CONFIG_OMAP_GPMC */
+
+/**/
+
+/* deprecated APIs */
+#if IS_ENABLED(CONFIG_OMAP_GPMC)
+void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+#else
+static inline void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+{
+ reg = NULL;
+}
+#endif /* CONFIG_OMAP_GPMC */
+/**/
+
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
struct gpmc_settings *gpmc_s,
struct gpmc_device_timings *dev_t);
-struct gpmc_nand_regs;
struct device_node;
-extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
extern int gpmc_get_client_irq(unsigned irq_config);
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
--
2.1.4
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[PATCH v3 04/27] mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 72918c4..04e6998 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -121,8 +121,6 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
if (err < 0)
goto out_free_cs;
- gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
-
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
err = -EINVAL;
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 60fa899..f214fe2 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#defineDRIVER_NAME "omap2-nand"
@@ -169,7 +170,9 @@ struct omap_nand_info {
} iomode;
u_char *buf;
int buf_len;
+ /* Interface to GPMC */
struct gpmc_nand_regs reg;
+ struct gpmc_nand_ops*ops;
/* generated at runtime depending on ECC algorithm and layout selected
*/
struct nand_ecclayout oobinfo;
/* fields specific for BCHx_HW ECC scheme */
@@ -1677,9 +1680,13 @@ static int omap_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info);
+ info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
+ if (!info->ops) {
+ dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
+ return -ENODEV;
+ }
info->pdev = pdev;
info->gpmc_cs = pdata->cs;
- info->reg = pdata->reg;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
mtd = &info->mtd;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 090bbab..a067f58 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -75,10 +75,12 @@ struct omap_nand_platform_data {
enum nand_ioxfer_type;
int devsize;
enum omap_ecc ecc_opt;
- struct gpmc_nand_regs reg;
/* for passing the partitions */
struct device_node *of_node;
struct device_node *elm_of_node;
+
+ /* deprecated */
+ struct gpmc_nand_regs reg;
};
#endif
--
2.1.4
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[PATCH v3 05/27] memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index a80c53e..174c45b 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -81,6 +81,8 @@
#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
+#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
+
#defineGPMC_CONFIG2_CSEXTRADELAY BIT(7)
#defineGPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#defineGPMC_CONFIG4_OEEXTRADELAY BIT(7)
@@ -1099,7 +1101,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg,
int cs)
}
}
-static struct gpmc_nand_ops nand_ops;
+static bool gpmc_nand_writebuffer_empty(void)
+{
+ if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
+ return true;
+
+ return false;
+}
+
+static struct gpmc_nand_ops nand_ops = {
+ .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
+};
/**
* gpmc_omap_get_nand_ops - Get the GPMC NAND interface
--
2.1.4
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[PATCH v3 06/27] mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty check
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f214fe2..0eb0b8c 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -289,14 +289,13 @@ static void omap_write_buf8(struct mtd_info *mtd, const
u_char *buf, int len)
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u_char *p = (u_char *)buf;
- u32 status = 0;
+ bool status;
while (len--) {
iowrite8(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
do {
- status = readl(info->reg.gpmc_status) &
- STATUS_BUFF_EMPTY;
+ status = info->ops->nand_writebuffer_empty();
} while (!status);
}
}
@@ -325,7 +324,7 @@ static void omap_write_buf16(struct mtd_info *mtd, const
u_char * buf, int len)
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u16 *p = (u16 *) buf;
- u32 status = 0;
+ bool status;
/* FIXME try bursts of writesw() or DMA ... */
len >>= 1;
@@ -333,8 +332,7 @@ static void omap_write_buf16(struct mtd_info *mtd, const
u_char * buf, int len)
iowrite16(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
do {
- status = readl(info->reg.gpmc_status) &
- STATUS_BUFF_EMPTY;
+ status = info->ops->nand_writebuffer_empty();
} while (!status);
}
}
--
2.1.4
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[PATCH v3 08/27] memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4
2 files changed, 54 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index a9071bb..e75226d 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1078,8 +1078,58 @@ static bool gpmc_nand_writebuffer_empty(void)
return false;
}
+static int gpmc_nand_irq_enable(enum gpmc_nand_irq irq)
+{
+ u32 reg;
+
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return -EINVAL;
+
+ reg = gpmc_read_reg(GPMC_IRQENABLE);
+ reg |= BIT(irq);
+ gpmc_write_reg(GPMC_IRQENABLE, reg);
+
+ return 0;
+}
+
+static int gpmc_nand_irq_disable(enum gpmc_nand_irq irq)
+{
+ u32 reg;
+
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return -EINVAL;
+
+ reg = gpmc_read_reg(GPMC_IRQENABLE);
+ reg &= ~BIT(irq);
+ gpmc_write_reg(GPMC_IRQENABLE, reg);
+
+ return 0;
+}
+
+static void gpmc_nand_irq_clear(enum gpmc_nand_irq irq)
+{
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return;
+
+ /* setting bit to 1 clears the bit in IRQSTATUS */
+ gpmc_write_reg(GPMC_IRQSTATUS, BIT(irq));
+}
+
+static u32 gpmc_nand_irq_status(void)
+{
+ u32 reg = gpmc_read_reg(GPMC_IRQSTATUS);
+
+ /* Mask out non-NAND bits */
+ reg &= GPMC_IRQENABLE_FIFOEVENT | GPMC_IRQENABLE_TERMCOUNT;
+ return reg;
+}
+
static struct gpmc_nand_ops nand_ops = {
.nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
+ .nand_irq_enable = gpmc_nand_irq_enable,
+ .nand_irq_disable = gpmc_nand_irq_disable,
+ .nand_irq_clear = gpmc_nand_irq_clear,
+ .nand_irq_status = gpmc_nand_irq_status,
};
/**
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 58f6bd2..b76cec3 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -11,6 +11,10 @@
#define GPMC_CONFIG_WP 0x0005
+/* GPMC IRQENABLE/IRQSTATUS BIT defs */
+#define GPMC_IRQENABLE_FIFOEVENT BIT(0)
+#define GPMC_IRQENABLE_TERMCOUNT BIT(1)
+
enum gpmc_nand_irq {
GPMC_NAND_IRQ_FIFOEVENT = 0,
GPMC_NAND_IRQ_TERMCOUNT,
--
2.1.4
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[PATCH v3 10/27] mtd: nand: omap: Copy platform data parameters to omap_nand_info data
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 267bcdd..c35405c 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -152,14 +152,18 @@ static struct nand_hw_control omap_gpmc_controller = {
};
struct omap_nand_info {
- struct omap_nand_platform_data *pdata;
struct mtd_info mtd;
struct nand_chipnand;
struct platform_device *pdev;
int gpmc_cs;
- unsigned long phys_base;
+ booldev_ready;
+ enum nand_ioxfer_type;
+ int devsize;
enum omap_ecc ecc_opt;
+ struct device_node *elm_of_node;
+
+ unsigned long phys_base;
struct completion comp;
struct dma_chan *dma;
int gpmc_irq;
@@ -1656,7 +1660,7 @@ static bool omap2_nand_ecc_check(struct omap_nand_info
*info,
"CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
return false;
}
- if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) {
+ if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
dev_err(&info->pdev->dev, "ELM not available\n");
return false;
}
@@ -1701,6 +1705,11 @@ static int omap_nand_probe(struct platform_device *pdev)
info->gpmc_cs = pdata->cs;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
+ info->dev_ready = pdata->dev_ready;
+ info->xfer_type = pdata->xfer_type;
+ info->devsize = pdata->devsize;
+ info->elm_of_node = pdata->elm_of_node;
+
mtd = &info->mtd;
mtd->priv = &info->nand;
mtd->name = dev_name(&pdev->dev);
@@ -1727,7 +1736,7 @@ static int omap_nand_probe(struct platform_device *pdev)
* chip delay which is slightly more than tR (AC Timing) of the NAND
* device and read status register until you get a failure or success
*/
- if (pdata->dev_ready) {
+ if (info->dev_ready) {
nand_chip->dev_ready = omap_dev_ready;
nand_chip->chip_delay = 0;
} else {
@@ -1741,15 +1750,16 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->options |= NAND_SKIP_BBTSCAN;
/* scan NAND device connected to chip controller */
- nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
+ nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
if (nand_scan_ident(mtd, 1, NULL)) {
- dev_err(&info->pdev->dev, "scan failed, may be bus-width
mismatch\n");
+ dev_err(&info->pdev->dev,
+ "scan failed, may be bus-width mismatch\n");
err = -ENXIO;
goto return_error;
}
/* re-populate low-level callbacks based on xfer modes */
- switch (pdata->xfer_type) {
+ switch (info->xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
nand_chip->read_buf = omap_read_buf_pref;
nand_chip->write_buf = omap_write_buf_pref;
@@ -1812,7 +1822,7 @@ static int omap_nand_probe(struct platform_device *pdev)
default:
dev_err(&pdev->dev,
- "xfer_type(%d) not supported!\n", pdata->xfer_type);
+ "xfer_type(%d) not supported!\n", info->xfer_type);
err = -EINVAL;
goto return_error;
}
--
2.1.4
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[PATCH v3 09/27] mtd: nand: omap2: manage NAND interrupts
Manage NAND interrupts here using the GPMC IRQ ops.
This causes performance in prefetch-irq mode to be increased
from
[ 38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[ 39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s
to
[ 35.666446] mtd_speedtest: eraseblock write speed is 6537 KiB/s
[ 36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s
Test results on dra7-evm using mtd_speedtest.ko
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 65 +++-
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 0eb0b8c..267bcdd 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -162,8 +162,7 @@ struct omap_nand_info {
enum omap_ecc ecc_opt;
struct completion comp;
struct dma_chan *dma;
- int gpmc_irq_fifo;
- int gpmc_irq_count;
+ int gpmc_irq;
enum {
OMAP_NAND_IO_READ = 0, /* read */
OMAP_NAND_IO_WRITE, /* write */
@@ -579,12 +578,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
{
struct omap_nand_info *info = (struct omap_nand_info *) dev;
u32 bytes;
+ u32 irqstatus;
+
+ irqstatus = info->ops->nand_irq_status();
+ if (!irqstatus)
+ return IRQ_NONE;
bytes = readl(info->reg.gpmc_prefetch_status);
bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
- if (this_irq == info->gpmc_irq_count)
+ if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
goto done;
if (info->buf_len && (info->buf_len < bytes))
@@ -601,17 +605,25 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
(u32 *)info->buf, bytes >> 2);
info->buf = info->buf + bytes;
- if (this_irq == info->gpmc_irq_count)
+ if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
goto done;
}
+ /* Clear FIFOEVENT STATUS */
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+
return IRQ_HANDLED;
done:
complete(&info->comp);
- disable_irq_nosync(info->gpmc_irq_fifo);
- disable_irq_nosync(info->gpmc_irq_count);
+ /* Clear FIFOEVENT and TERMCOUNT STATUS */
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_TERMCOUNT);
+
+ /* Disable Interrupt generation */
+ info->ops->nand_irq_disable(GPMC_NAND_IRQ_FIFOEVENT);
+ info->ops->nand_irq_disable(GPMC_NAND_IRQ_TERMCOUNT);
return IRQ_HANDLED;
}
@@ -646,8 +658,9 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd,
u_char *buf, int len)
info->buf_len = len;
- enable_irq(info->gpmc_irq_count);
- enable_irq(info->gpmc_irq_fifo);
+ /* Enable Interrupt generation */
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
/* waiting for read to complete */
wait_for_completion(&info->comp);
@@ -696,8 +709,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
info->buf_len = len;
- enable_irq(info->gpmc_irq_count);
- enable_irq(info->gpmc_irq_fifo);
+ /* Enable Interrupt generation */
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
/* waiting for write to complete */
wait_for_completion(&info->comp);
@@ -1776,35 +1790,18 @@ static int omap_nand_probe(struct platform_device *pdev)
break;
case NAND_OMAP_PREFETCH_IRQ:
- info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
- if (info->gpmc_irq_fifo <= 0) {
- dev_err(&pdev->dev, "error getting fifo irq\n");
- err = -ENODEV;
- goto return_error;
- }
- err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
- omap_nand_irq, IRQF_SHARED,
- "gpmc-nand-fifo", info);
- if (err) {
- dev_err(&pdev->dev, "requesting irq(%d) error:%d",
- info->gpmc_irq_fifo, err);
- info->gpmc_irq_fifo = 0
[PATCH v3 11/27] mtd: nand: omap: Clean up device tree support
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135 ++
drivers/mtd/nand/omap2.c | 136 +++
include/linux/platform_data/mtd-nand-omap2.h | 3 +-
4 files changed, 147 insertions(+), 132 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index ffe646a..e07ca27 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -95,10 +95,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_nand_res[1].start = gpmc_get_irq();
memset(&s, 0, sizeof(struct gpmc_settings));
- if (gpmc_nand_data->of_node)
- gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
- else
- gpmc_set_legacy(gpmc_nand_data, &s);
+ gpmc_set_legacy(gpmc_nand_data, &s);
s.device_nand = true;
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index e75226d..b09e1bc 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -29,7 +29,6 @@
#include
#include
#include
-#include
#include
#include
@@ -1716,105 +1715,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
of_property_read_bool(np, "gpmc,time-para-granularity");
}
-#if IS_ENABLED(CONFIG_MTD_NAND)
-
-static const char * const nand_xfer_types[] = {
- [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
- [NAND_OMAP_POLLED] = "polled",
- [NAND_OMAP_PREFETCH_DMA]= "prefetch-dma",
- [NAND_OMAP_PREFETCH_IRQ]= "prefetch-irq",
-};
-
-static int gpmc_probe_nand_child(struct platform_device *pdev,
-struct device_node *child)
-{
- u32 val;
- const char *s;
- struct gpmc_timings gpmc_t;
- struct omap_nand_platform_data *gpmc_nand_data;
-
- if (of_property_read_u32(child, "reg", &val) < 0) {
- dev_err(&pdev->dev, "%s has no 'reg' property\n",
- child->full_name);
- return -ENODEV;
- }
-
- gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
- GFP_KERNEL);
- if (!gpmc_nand_data)
- return -ENOMEM;
-
- gpmc_nand_data->cs = val;
- gpmc_nand_data->of_node = child;
-
- /* Detect availability of ELM module */
- gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
- if (gpmc_nand_data->elm_of_node == NULL)
- gpmc_nand_data->elm_of_node =
- of_parse_phandle(child, "elm_id", 0);
-
- /* select ecc-scheme for NAND */
- if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
- pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
- return -ENODEV;
- }
-
- if (!strcmp(s, "sw"))
- gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
- else if (!strcmp(s, "ham1") ||
-!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_HAM1_CODE_HW;
- else if (!strcmp(s, "bch4"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch8"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch16"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH16_CODE_HW;
- else
- pr_err("%s: BCH16 requires ELM support\n", __func__);
- else
- pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
-
- /* select data transfer mode for NAND controller */
- if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
- for
[PATCH v3 13/27] memory: omap-gpmc: Prevent mapping into 1st 16MB
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index b09e1bc..bcf4b05 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -93,6 +93,14 @@
#define GPMC_CS_SIZE 0x30
#defineGPMC_BCH_SIZE 0x10
+/*
+ * The first 1MB of GPMC address space is typically mapped to
+ * the internal ROM. Never allocate the first page, to
+ * facilitate bug detection; even if we didn't boot from ROM.
+ * As GPMC minimum partition size is 16MB we can only start from
+ * there.
+ */
+#define GPMC_MEM_START 0x100
#define GPMC_MEM_END 0x3FFF
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
@@ -1171,12 +1179,7 @@ static void gpmc_mem_init(void)
{
int cs;
- /*
-* The first 1MB of GPMC address space is typically mapped to
-* the internal ROM. Never allocate the first page, to
-* facilitate bug detection; even if we didn't boot from ROM.
-*/
- gpmc_mem_root.start = SZ_1M;
+ gpmc_mem_root.start = GPMC_MEM_START;
gpmc_mem_root.end = GPMC_MEM_END;
/* Reserve all regions that has been set up by bootloader */
@@ -1830,6 +1833,15 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
if (ret < 0) {
dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
cs, &res.start);
+ if (res.start < GPMC_MEM_START) {
+ dev_info(&pdev->dev,
+"GPMC CS %d start cannot be lesser than
0x%x\n",
+cs, GPMC_MEM_START);
+ } else if (res.end > GPMC_MEM_END) {
+ dev_info(&pdev->dev,
+"GPMC CS %d end cannot be greater than 0x%x\n",
+cs, GPMC_MEM_END);
+ }
goto err;
}
--
2.1.4
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[PATCH v3 16/27] memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 518b418..fdf19eeb 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1779,6 +1779,8 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
const char *name;
int ret, cs;
u32 val;
+ struct gpio_desc *waitpin_desc = NULL;
+ struct gpmc_device *gpmc = platform_get_drvdata(pdev);
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%s has no 'reg' property\n",
@@ -1880,15 +1882,28 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
goto err;
}
+ /* Reserve wait pin if it is required and valid */
+ if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
+ unsigned wait_pin = gpmc_s.wait_pin;
+
+ waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
+wait_pin, "WAITPIN");
+ if (IS_ERR(waitpin_desc)) {
+ dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
+ ret = PTR_ERR(waitpin_desc);
+ goto err;
+ }
+ }
+
ret = gpmc_cs_program_settings(cs, &gpmc_s);
if (ret < 0)
- goto err;
+ goto err_cs;
ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
if (ret) {
dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
child->name);
- goto err;
+ goto err_cs;
}
/* Clear limited address i.e. enable A26-A11 */
@@ -1919,6 +1934,10 @@ err_child_fail:
dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
ret = -ENODEV;
+err_cs:
+ if (waitpin_desc)
+ gpiochip_free_own_desc(waitpin_desc);
+
err:
gpmc_cs_free(cs);
--
2.1.4
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[PATCH v3 12/27] mtd: nand: omap: Update DT binding documentation
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4..253e6de 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt
Required properties:
- - reg:The CS line the peripheral is connected to
+ - compatible: "ti,omap2-nand"
+ - reg:range id (CS number), base offset and length of the
+ NAND I/O space
+ - interrupt-parent: must point to gpmc node
+ - interrupts: gpmc interrupt
Optional properties:
@@ -55,20 +59,24 @@ Example for an AM33xx board:
gpmc: gpmc@5000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
- reg = <0x5000 0x100>;
+ reg = <0x5000 0x36c>;
interrupts = <100>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 0x0800 0x2000>; /* CS0: NAND */
+ ranges = <0 0 0x0800 0x100>;/* CS0 space, 16MB */
elm_id = <&elm>;
nand@0,0 {
- reg = <0 0 0>; /* CS0, offset 0 */
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, NAND I/O
window 4 */
+ interrupts = <100>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
+ interrupt-parent = <&gpmc>;
+ interrupts = <0>, <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
--
2.1.4
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[PATCH v3 14/27] memory: omap-gpmc: Move device tree binding to correct location
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.txt =>
memory-controllers/omap-gpmc.txt} (100%)
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/bus/ti-gpmc.txt
rename to Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
--
2.1.4
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[PATCH v3 15/27] memory: omap-gpmc: Support general purpose input for WAITPINs
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 130 +
1 file changed, 120 insertions(+), 10 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index bcf4b05..518b418 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -223,6 +224,11 @@ struct omap3_gpmc_regs {
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
+struct gpmc_device {
+ struct device *dev;
+ struct gpio_chip gpio_chip;
+};
+
static struct resource gpmc_mem_root;
static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -1919,10 +1925,69 @@ err:
return ret;
}
+static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ return 1; /* we're input only */
+}
+
+static int gpmc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ return 0; /* we're input only */
+}
+
+static int gpmc_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ return -EINVAL; /* we're input only */
+}
+
+static void gpmc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+}
+
+static int gpmc_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ u32 reg;
+
+ offset += 8;
+
+ reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
+
+ return !!reg;
+}
+
+static int gpmc_gpio_init(struct gpmc_device *gpmc)
+{
+ int ret;
+
+ gpmc->gpio_chip.dev = gpmc->dev;
+ gpmc->gpio_chip.owner = THIS_MODULE;
+ gpmc->gpio_chip.label = DEVICE_NAME;
+ gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
+ gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
+ gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
+ gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
+ gpmc->gpio_chip.set = gpmc_gpio_set;
+ gpmc->gpio_chip.get = gpmc_gpio_get;
+ gpmc->gpio_chip.base = -1;
+
+ ret = gpiochip_add(&gpmc->gpio_chip);
+ if (ret < 0) {
+ dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void gpmc_gpio_exit(struct gpmc_device *gpmc)
+{
+ gpiochip_remove(&gpmc->gpio_chip);
+}
+
static int gpmc_probe_dt(struct platform_device *pdev)
{
int ret;
- struct device_node *child;
const struct of_device_id *of_id =
of_match_device(gpmc_dt_ids, &pdev->dev);
@@ -1950,6 +2015,14 @@ static int gpmc_probe_dt(struct platform_device *pdev)
return ret;
}
+ return 0;
+}
+
+static int gpmc_probe_dt_children(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *child;
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
if (!child->name)
@@ -1959,6 +2032,9 @@ static int gpmc_probe_dt(struct platform_device *pdev)
ret = gpmc_probe_onenand_child(pdev, child);
else
ret = gpmc_probe_generic_child(pdev, child);
+
+ if (ret)
+ return ret;
}
return 0;
@@ -1968,6 +2044,11 @@ static int gpmc_probe_dt(struct platform_device *pdev)
{
return 0;
}
+
+static int gpmc_probe_dt_children(struct platform_device *pdev)
+{
+ return 0;
+}
#endif
static int gpmc_probe(struct platform_device *pdev)
@@ -1975,6 +2056,7 @@ static int gpmc_probe(struct platform_device *pdev)
int rc;
u32 l;
struct resource *res;
+ struct gpmc_device *gpmc;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
@@ -2005,6 +2087,24 @@ static int gpmc_probe(struct platform_device *pdev)
return -EINVAL;
}
+
+ if (pdev->dev.of_node) {
+ rc = gpmc_probe_dt(pdev);
+ if (rc)
+ return rc;
+ } else {
+ gpmc_cs_num = GPMC_CS_NUM;
+ gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+ }
+
+
+ gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
+ if (!gpmc)
+ return -ENOMEM;
+
+ gpmc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, gpmc);
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
@@ -2032,24 +2132,34 @@ static int gpmc_probe(struct platform_device *pdev)
GPMC_REVISION_MINOR(l));
[PATCH v3 17/27] memory: omap-gpmc: Add irqchip support to the gpiochip
The WAIT pins support either rising or falling edge interrupts
so add irqchip support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 132 +
1 file changed, 132 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index fdf19eeb..764e24a 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
#include
+#include
#include
#include
#include
@@ -227,6 +228,7 @@ struct omap3_gpmc_regs {
struct gpmc_device {
struct device *dev;
struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
};
static struct resource gpmc_mem_root;
@@ -1944,6 +1946,99 @@ err:
return ret;
}
+static int gpmc_irq_endis(unsigned long hwirq, bool endis)
+{
+ u32 regval;
+
+ /* WAITPIN starts at BIT 8 */
+ hwirq += 8;
+
+ regval = gpmc_read_reg(GPMC_IRQENABLE);
+ if (endis)
+ regval |= BIT(hwirq);
+ else
+ regval &= ~BIT(hwirq);
+ gpmc_write_reg(GPMC_IRQENABLE, regval);
+
+ return 0;
+}
+
+static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
+{
+ u32 regval;
+
+ /* WAITPIN starts at BIT 8 */
+ hwirq += 8;
+
+ regval = gpmc_read_reg(GPMC_CONFIG);
+ if (rising_edge)
+ regval &= ~BIT(hwirq);
+ else
+ regval |= BIT(hwirq);
+
+ gpmc_write_reg(GPMC_CONFIG, regval);
+}
+
+static void gpmc_irq_mask(struct irq_data *d)
+{
+ gpmc_irq_endis(d->hwirq, false);
+}
+
+static void gpmc_irq_unmask(struct irq_data *d)
+{
+ gpmc_irq_endis(d->hwirq, true);
+}
+
+static void gpmc_irq_ack(struct irq_data *d)
+{
+ unsigned hwirq = d->hwirq + 8;
+
+ /* Setting bit to 1 clears (or Acks) the interrupt */
+ gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
+}
+
+static int gpmc_irq_set_type(struct irq_data *d, unsigned trigger)
+{
+ /* We can support either rising or falling edge at a time */
+ if (trigger == IRQ_TYPE_EDGE_FALLING)
+ gpmc_irq_edge_config(d->hwirq, false);
+ else if (trigger == IRQ_TYPE_EDGE_RISING)
+ gpmc_irq_edge_config(d->hwirq, true);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+static irqreturn_t gpmc_handle_irq(int irq, void *data)
+{
+ int hwirq, virq;
+ u32 regval;
+ struct gpmc_device *gpmc = data;
+
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+ regval >>= 8; /* we're only interested in WAIT pins */
+
+ if (!regval)
+ return IRQ_NONE;
+
+ for (hwirq = 0; hwirq < gpmc->gpio_chip.ngpio; hwirq++) {
+ if (regval & BIT(hwirq)) {
+ virq = irq_find_mapping(gpmc->gpio_chip.irqdomain,
+ hwirq);
+ if (!virq) {
+ dev_warn(gpmc_dev,
+"spurious irq detected hwirq %d, virq
%d\n",
+hwirq, virq);
+ }
+
+ generic_handle_irq(virq);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
return 1; /* we're input only */
@@ -1978,6 +2073,7 @@ static int gpmc_gpio_get(struct gpio_chip *chip, unsigned
offset)
static int gpmc_gpio_init(struct gpmc_device *gpmc)
{
int ret;
+ u32 regval;
gpmc->gpio_chip.dev = gpmc->dev;
gpmc->gpio_chip.owner = THIS_MODULE;
@@ -1996,7 +2092,43 @@ static int gpmc_gpio_init(struct gpmc_device *gpmc)
return ret;
}
+ /* Disable interrupts */
+ gpmc_write_reg(GPMC_IRQENABLE, 0);
+
+ /* clear interrupts */
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+ gpmc_write_reg(GPMC_IRQSTATUS, regval);
+
+ gpmc->irq_chip.name = DEVICE_NAME;
+ gpmc->irq_chip.irq_ack = gpmc_irq_ack;
+ gpmc->irq_chip.irq_mask = gpmc_irq_mask;
+ gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
+ gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
+
+ ret = gpiochip_irqchip_add(&gpmc->gpio_chip, &gpmc->irq_chip, 0,
+ handle_edge_irq, IRQ_TYPE_NONE);
+
+ if (ret) {
+ dev_err(gpmc->dev, "could not add irqchip to gpiochip: %d\n",
+ ret);
+ goto fail;
+ }
+
+ /* We're sharing this IRQ with OMAP NAND driver */
+ ret = devm_request_irq(gpmc->dev, gpmc_irq, gpmc_handle_irq,
+ IRQF_SHARED, DEVICE_NAME, gpmc);
+ if (ret) {
+ dev_err(gpmc->dev, "could not reque
[PATCH v3 19/27] memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand-omap2.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 764e24a..4c630ad 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1051,7 +1051,7 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int
cs)
{
int i;
- reg->gpmc_status = gpmc_base + GPMC_STATUS;
+ reg->gpmc_status = NULL;/* deprecated */
reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 19e509d..17d57a1 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -45,7 +45,6 @@ enum omap_ecc {
};
struct gpmc_nand_regs {
- void __iomem*gpmc_status;
void __iomem*gpmc_nand_command;
void __iomem*gpmc_nand_address;
void __iomem*gpmc_nand_data;
@@ -64,6 +63,8 @@ struct gpmc_nand_regs {
void __iomem*gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
+ /* Deprecated. Do not use */
+ void __iomem*gpmc_status;
};
struct omap_nand_platform_data {
--
2.1.4
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[PATCH v3 20/27] ARM: dts: dra7: Fix NAND device nodes.
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 5 -
arch/arm/boot/dts/dra7.dtsi | 4
arch/arm/boot/dts/dra72-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a6c82e5..8a31161 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -585,9 +585,12 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
- ranges = <0 0 0 0x0100>;/* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x0800 0x0100>; /* minimum GPMC partition =
16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&crossbar_mpu>;
+ interrupts = ;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5d65db9..f0a3616 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1389,6 +1389,10 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 6f6bd98..245f5f9 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -395,13 +395,16 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
- ranges = <0 0 0 0x0100>;/* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x0800 0x0100>; /* minimum GPMC partition =
16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&crossbar_mpu>;
+ interrupts = ;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
--
2.1.4
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[PATCH v3 18/27] mtd: nand: omap2: Implement NAND ready using gpiolib
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux/platform_data/mtd-nand-omap2.h | 2 +-
2 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 228f498..d0f2620 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -184,6 +185,8 @@ struct omap_nand_info {
/* fields specific for BCHx_HW ECC scheme */
struct device *elm_dev;
struct device_node *of_node;
+ /* NAND ready gpio */
+ struct gpio_desc*ready_gpiod;
};
/**
@@ -1047,22 +1050,17 @@ static int omap_wait(struct mtd_info *mtd, struct
nand_chip *chip)
}
/**
- * omap_dev_ready - calls the platform specific dev_ready function
+ * omap_dev_ready - checks the NAND Ready GPIO line
* @mtd: MTD device structure
+ *
+ * Returns true if ready and false if busy.
*/
static int omap_dev_ready(struct mtd_info *mtd)
{
- unsigned int val = 0;
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
- val = readl(info->reg.gpmc_status);
-
- if ((val & 0x100) == 0x100) {
- return 1;
- } else {
- return 0;
- }
+ return gpiod_get_value(info->ready_gpiod);
}
/**
@@ -1782,7 +1780,9 @@ static int omap_nand_probe(struct platform_device *pdev)
info->reg = pdata->reg;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
- info->dev_ready = pdata->dev_ready;
+ if (pdata->dev_ready)
+ dev_info(&pdev->dev, "pdata->dev_ready is
deprecated\n");
+
info->xfer_type = pdata->xfer_type;
info->devsize = pdata->devsize;
info->elm_of_node = pdata->elm_of_node;
@@ -1815,6 +1815,13 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
nand_chip->cmd_ctrl = omap_hwcontrol;
+ info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "ready",
+ GPIOD_IN);
+ if (IS_ERR(info->ready_gpiod)) {
+ dev_err(dev, "failed to get ready gpio\n");
+ return PTR_ERR(info->ready_gpiod);
+ }
+
/*
* If RDY/BSY line is connected to OMAP then use the omap ready
* function and the generic nand_wait function which reads the status
@@ -1822,7 +1829,7 @@ static int omap_nand_probe(struct platform_device *pdev)
* chip delay which is slightly more than tR (AC Timing) of the NAND
* device and read status register until you get a failure or success
*/
- if (info->dev_ready) {
+ if (info->ready_gpiod) {
nand_chip->dev_ready = omap_dev_ready;
nand_chip->chip_delay = 0;
} else {
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index ff27e5a..19e509d 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -70,7 +70,6 @@ struct omap_nand_platform_data {
int cs;
struct mtd_partition*parts;
int nr_parts;
- booldev_ready;
boolflash_bbt;
enum nand_ioxfer_type;
int devsize;
@@ -81,5 +80,6 @@ struct omap_nand_platform_data {
/* deprecated */
struct gpmc_nand_regs reg;
struct device_node *of_node;
+ booldev_ready;
};
#endif
--
2.1.4
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[PATCH v3 24/27] ARM: dts: am335x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 3 +++
arch/arm/boot/dts/am335x-evm.dts | 3 +++
arch/arm/boot/dts/am335x-igep0033.dtsi | 3 +++
arch/arm/boot/dts/am33xx.dtsi | 4
4 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi
b/arch/arm/boot/dts/am335x-chilisom.dtsi
index 7e9a34d..e2b5e22 100644
--- a/arch/arm/boot/dts/am335x-chilisom.dtsi
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -208,7 +208,10 @@
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x0800 0x0100>; /* CS0 0 @addr 0x0800, size
0x0100 */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 1942a5c..bea36e1 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -519,7 +519,10 @@
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi
b/arch/arm/boot/dts/am335x-igep0033.dtsi
index c0e1135..9252ff1 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -129,7 +129,10 @@
ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index d23e252..e065f21 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -823,6 +823,10 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
status = "disabled";
};
--
2.1.4
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[PATCH v3 21/27] ARM: dts: dra7x-evm: Provide NAND ready pin
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged at 7123 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-evm.dts | 1 + arch/arm/boot/dts/dra72-evm.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 8a31161..4760562 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -591,6 +591,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = ; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 245f5f9..a11a646 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -405,6 +405,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = ; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 23/27] ARM: dts: am437x-gp-evm: Provide NAND ready pin
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. For NAND we don't use GPMC wait pin monitoring but get the NAND Ready/Busy# status using GPIOlib. GPMC driver provides the WAIT0 pin status over GPIOlib. Read speed increases from 16516 KiB/ to 18813 KiB/s and write speed was unchanged at 9941 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/am437x-gp-evm.dts | 3 +-- arch/arm/boot/dts/am43x-epos-evm.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index aa96c99..d7bfe9f 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -800,6 +800,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&gic>; interrupts = ; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>;/* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -818,11 +819,9 @@ gpmc,access-ns = <30>; gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; - gpmc,wait-pin = <0>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 9a7786d..4b26762 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -567,6 +567,7 @@ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gic>; interrupts = ; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>;/* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -585,11 +586,9 @@ gpmc,access-ns = <30>; /* tCEA + 4*/ gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; - gpmc,wait-pin = <0>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +--
arch/arm/boot/dts/omap3-beagle.dts | 2 ++
arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 -
arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 +++
arch/arm/boot/dts/omap3-evm-37xx.dts | 7 +--
arch/arm/boot/dts/omap3-gta04.dtsi | 3 +++
arch/arm/boot/dts/omap3-igep.dtsi | 5 -
arch/arm/boot/dts/omap3-igep0020-common.dtsi | 4 ++--
arch/arm/boot/dts/omap3-igep0030-common.dtsi | 4
arch/arm/boot/dts/omap3-ldp.dts| 9 ++---
arch/arm/boot/dts/omap3-lilly-a83x.dtsi| 5 -
arch/arm/boot/dts/omap3-pandora-common.dtsi| 3 +++
arch/arm/boot/dts/omap3-tao3530.dtsi | 5 -
arch/arm/boot/dts/omap3.dtsi | 4
arch/arm/boot/dts/omap3430-sdp.dts | 5 -
15 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 36387b1..4ba73c9 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -35,11 +35,14 @@
};
&gpmc {
- ranges = <0 0 0x 0x100>;/* CS0: 16MB for NAND */
+ ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
nand@0,0 {
- linux,mtd-name = "micron,mt29f4g16abbda3w";
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+ linux,mtd-name = "micron,mt29f4g16abbda3w";
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index a547411..bb4df5d 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -384,7 +384,9 @@
/* Chip select 0 */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
+ interrupt-parent = <&intc>;
interrupts = <20>;
ti,nand-ecc-opt = "ham1";
nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index 4d091ca..e9d7e28 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -261,10 +261,13 @@
};
&gpmc {
- ranges = <0 0 0x 0x0100>;
+ ranges = <0 0 0x3000 0x0100>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index 9ca2865..e7b46ad 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -204,7 +204,10 @@
ranges = <0 0 0x3000 0x100>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts
b/arch/arm/boot/dts/omap3-evm-37xx.dts
index 16e8ce3..7081e07 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,12 +154,15 @@
};
&gpmc {
- ranges = <0 0 0x 0x100>,/* CS0: 16MB for NAND */
+ ranges = <0 0 0x3000 0x100>,/* CS0: 16MB for NAND */
<5 0 0x2c00 0x0100>;
nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
linux,mtd-nam
[PATCH v3 26/27] ARM: dts: dm816x: Fix gpmc and NAND node
Make gpmc node gpio+interrupt capable.
Add compatible id, interrupt and wait pin to NAND node.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dm8168-evm.dts | 7 ---
arch/arm/boot/dts/dm816x.dtsi| 4
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 169a855..faa7abe 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -85,8 +85,12 @@
ranges = <0 0 0x0400 0x0100>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
linux,mtd-name= "micron,mt29f2g16aadwp";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
+ ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";
@@ -106,12 +110,9 @@
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
- gpmc,wait-on-read = "true";
- gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
partition@0 {
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 3c99cfa..68fb444 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -182,6 +182,10 @@
interrupts = <100>;
gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
i2c1: i2c@48028000 {
--
2.1.4
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[PATCH v3 22/27] ARM: dts: am437x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am4372.dtsi| 4
arch/arm/boot/dts/am437x-gp-evm.dts | 5 -
arch/arm/boot/dts/am43x-epos-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 0447c04a..ec8b7a3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -849,6 +849,10 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 22038f2..aa96c99 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -794,9 +794,12 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
- ranges = <0 0 0 0x0100>;/* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x0800 0x0100>; /* CS0 space. Min partition =
16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gic>;
+ interrupts = ;
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 86c2dfb..9a7786d 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -561,9 +561,12 @@
status = "okay";/* Disable QSPI when enabling GPMC (NAND) */
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
- ranges = <0 0 0x0800 0x100>;/* CS0: 16MB for NAND */
+ ranges = <0 0 0x0800 0x0100>; /* CS0 space. Min partition =
16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gic>;
+ interrupts = ;
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
--
2.1.4
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[PATCH v3 25/27] ARM: dts: am335x: Provide NAND ready pin
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. For NAND we don't use GPMC wait pin monitoring but get the NAND Ready/Busy# status using GPIOlib. GPMC driver provides the WAIT0 pin status over GPIOlib. Read speed increases from 7869 KiB/ to 8875 KiB/s and write speed was unchanged at 5100 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/am335x-chilisom.dtsi | 4 +--- arch/arm/boot/dts/am335x-evm.dts | 4 +--- arch/arm/boot/dts/am335x-igep0033.dtsi | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index e2b5e22..3c71c5d 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -212,6 +212,7 @@ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&intc>; interrupts = <100>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -230,12 +231,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index bea36e1..c7dfc21 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -523,6 +523,7 @@ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&intc>; interrupts = <100>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -541,12 +542,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 9252ff1..84d4d50 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -133,6 +133,7 @@ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&intc>; interrupts = <100>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; @@ -150,12 +151,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 07/27] memory: omap-gpmc: Remove NAND IRQ code
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 163 +---
include/linux/omap-gpmc.h | 11 +--
3 files changed, 10 insertions(+), 168 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 04e6998..ffe646a 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -80,7 +80,6 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
struct resource gpmc_nand_res[] = {
{ .flags = IORESOURCE_MEM, },
{ .flags = IORESOURCE_IRQ, },
- { .flags = IORESOURCE_IRQ, },
};
BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
@@ -93,8 +92,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
return err;
}
gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
- gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
- gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+ gpmc_nand_res[1].start = gpmc_get_irq();
memset(&s, 0, sizeof(struct gpmc_settings));
if (gpmc_nand_data->of_node)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 174c45b..a9071bb 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -123,12 +123,6 @@
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
-/* Control Commands */
-#define GPMC_CONFIG_RDY_BSY0x0001
-#define GPMC_CONFIG_DEV_SIZE 0x0002
-#define GPMC_CONFIG_DEV_TYPE 0x0003
-#define GPMC_SET_IRQ_STATUS0x0004
-
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -176,17 +170,11 @@
#define GPMC_CONFIG_WRITEPROTECT 0x0010
#define WR_RD_PIN_MONITORING 0x0060
-#define GPMC_ENABLE_IRQ0x000d
-
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
-/* XXX: Only NAND irq has been considered,currently these are the only ones
used
- */
-#defineGPMC_NR_IRQ 2
-
enum gpmc_clk_domain {
GPMC_CD_FCLK,
GPMC_CD_CLK
@@ -201,11 +189,6 @@ struct gpmc_cs_data {
struct resource mem;
};
-struct gpmc_client_irq {
- unsignedirq;
- u32 bitmask;
-};
-
/* Structure to save gpmc cs context */
struct gpmc_cs_config {
u32 config1;
@@ -233,10 +216,6 @@ struct omap3_gpmc_regs {
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
-static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
-static struct irq_chip gpmc_irq_chip;
-static int gpmc_irq_start;
-
static struct resource gpmc_mem_root;
static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -244,15 +223,13 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned int gpmc_cs_num = GPMC_CS_NUM;
static unsigned int gpmc_nr_waitpins;
static struct device *gpmc_dev;
-static int gpmc_irq;
+static int gpmc_irq = -EINVAL;
static resource_size_t phys_base, mem_size;
static unsigned gpmc_capability;
static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk;
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
-
static void gpmc_write_reg(int idx, u32 val)
{
writel_relaxed(val, gpmc_base + idx);
@@ -1037,14 +1014,6 @@ int gpmc_configure(int cmd, int wval)
u32 regval;
switch (cmd) {
- case GPMC_ENABLE_IRQ:
- gpmc_write_reg(GPMC_IRQENABLE, wval);
- break;
-
- case GPMC_SET_IRQ_STATUS:
- gpmc_write_reg(GPMC_IRQSTATUS, wval);
- break;
-
case GPMC_CONFIG_WP:
regval = gpmc_read_reg(GPMC_CONFIG);
if (wval)
@@ -1132,112 +1101,9 @@ struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct
gpmc_nand_regs *reg, int cs)
}
EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
-int gpmc_get_client_irq(unsigned irq_config)
-{
- int i;
-
- if (hweight32(irq_config) > 1)
- return 0;
-
- for (i = 0; i < GPMC_NR_IRQ; i++)
- if (gpmc_client_irq[i].bitmask & irq_config)
- return gpmc_client_irq[i].irq;
-
- return 0;
-}
-
-static int gpmc_irq_endis(unsigned irq, bool endis)
-{
- int i;
- u32 regval;
-
- for (i = 0; i < GPMC_NR_IRQ; i++)
- if (irq == gpmc_client_irq[i].irq) {
-
[PATCH v3 01/27] ARM: OMAP2+: gpmc: Add platform data
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30 ++
2 files changed, 31 insertions(+), 2 deletions(-)
create mode 100644 include/linux/platform_data/gpmc-omap.h
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 7dee0014..5c79190 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -7,8 +7,7 @@
* option) any later version.
*/
-/* Maximum Number of Chip Selects */
-#define GPMC_CS_NUM8
+#include
#define GPMC_CONFIG_WP 0x0005
diff --git a/include/linux/platform_data/gpmc-omap.h
b/include/linux/platform_data/gpmc-omap.h
new file mode 100644
index 000..d32d9de
--- /dev/null
+++ b/include/linux/platform_data/gpmc-omap.h
@@ -0,0 +1,30 @@
+/*
+ * OMAP GPMC Platform data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc. - http://www.ti.com
+ * Roger Quadros
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _GPMC_OMAP_H_
+#define _GPMC_OMAP_H_
+
+/* Maximum Number of Chip Selects */
+#define GPMC_CS_NUM8
+
+/* Data for each chip select */
+struct gpmc_omap_cs_data {
+ bool valid; /* data is valid */
+ bool is_nand; /* device within this CS is NAND */
+ struct platform_device *pdev; /* device within this CS region */
+ unsigned pdata_size;
+};
+
+struct gpmc_omap_platform_data {
+ struct gpmc_omap_cs_data cs[GPMC_CS_NUM];
+};
+
+#endif /* _GPMC_OMAP_H */
--
2.1.4
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Re: Myir AM437x Rico board support for Linux 4.1 kernel
+Tony, Tomi, linux-omap Hi Pavel, On 25/08/15 16:39, Pavel Pisa wrote: > Hello everybody, > > I have been asked to help with Linux on Myir Rico board. > I have decided to try actual stable kernel from Ti tree > > git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git > branch ti-linux-4.1.y > > instead of delivered dated 3.12.10 one to solve some issues > and have chance to port possible enhancements to mainline. > > I have successfully prepared environment which loads kernel > over TFTP and boot actual Debian Jessie armhf from NFS export. > > Because I have not found up to date device tree for this > board I have analyzed delivered sources against best matching > Ti kernel and then prepared DTS which works on the board > and I want to know if somebody works on this support, can help > to finish/better tune parameters and if there is chance > that configs are included into mainline or some other public > repository. Because I do not know who is working on this support > and who is right maintainer I send only pointers to my files. Tony Lindgren is the OMAP platform maintainer and you must include linux-omap mailing list in in the discussion. > > http://cmp.felk.cvut.cz/~pisa/arm/myir-rico/am437x-myir-ricoboard.dts > based on Ti am437x-gp-evm.dts > > http://cmp.felk.cvut.cz/~pisa/arm/myir-rico/am437x-myir-ricoboard-hdmi.dts > based on Ti am437x-gp-evm-hdmi.dts > > http://cmp.felk.cvut.cz/~pisa/arm/myir-rico/am437x-myir-ricoboard_defconfig > > If there is interrest for discussion and inclusion, I send usual > inlined GIT patches series. Please send patches for the new board so that we can review. > > As for DTS, I expect that the regulators section does not match correctly > Rico board HW but it works for what client company needs > evm_v3_3d: fixedregulator-v3_3d > vtt_fixed: fixedregulator-vtt > > Ethernet, serials, cameras, local MTD, SDcard and most of other devices works. > SPI Flash does not work. I have not invested time to that. > > The client needs to connect special camera (infrared) to the VPFE so I have > spent some time on AM437x VPFE support enhancement. > > I have added V4L2_PIX_FMT_Y10 pixel format and some minimal/stub > implementation of vpfe_enum_frameintervals, vpfe_g_parm, vvpfe_s_parm, > pfe_s_parm and I would be happy if my work can help to somebody other > as well. But work has been driven strict deadline to provide working > solution in one week so if there is interrest then most has to be > rewritten/clean up. > > Generally, I am quite pleased by Ti's Linux tree state and support. > That week has been my first time with AM chips we used other archs > (powerpc and multiple i.MXs for most of our other projects till now). > > Probably off topic for these lists but what are suggested options > for graphic configuration when Qt4/E or Qt5 is run on framebuffer. > Is it better to use CONFIG_DRM_OMAP or CONFIG_FB_OMAP2 ? > Is SGX driver available for 4.1 Linux kernel (reply offlist, please, > if proprietary only)? Are there other possibilities how to use > OMAP AM437xx hardware to accelerate video color and formats > transformations? Can be VPFE planes used somehow to embed > video in Qt application? I, personally, prefer strongly > opensource only options but target company has probably minimal > requirements in this area. Tomi might be able to answer video related questions. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/22] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 13/08/15 11:36, Tony Lindgren wrote: > * Roger Quadros [150813 00:17]: >> On 11/08/15 15:48, Tony Lindgren wrote: >>> >>> OK. Yeah let's make sure no regressions are caused by this.. We also >>> still have the omap3 legacy booting around, have you checked that it >>> keeps on working? >> >> I don't have any omap3 board with legacy support with me. I have omap3-beagle >> but looks like legacy boot is dropped for it already. >> >> I'll try to revert the patch that drops beagle support and test it on that >> one. > > OK yeah that should work just fine. > Just verified that with the change in patch 6 it works on omap3-beagle legacy boot. I have fixed some checkpatch issues in this series as well. Will post a v3 after you have gone one pass over this series. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 16/22] memory: omap-gpmc: Support general purpose input for WAITPINs
On 07/08/15 12:12, Roger Quadros wrote:
> OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
> input if not used for memory wait state insertion.
>
> The first user will be the OMAP NAND chip to get the NAND
> read/busy status using gpiolib.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/memory/omap-gpmc.c | 122
> +++--
> 1 file changed, 117 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
> index 30d9c21..264009d 100644
> --- a/drivers/memory/omap-gpmc.c
> +++ b/drivers/memory/omap-gpmc.c
> @@ -21,6 +21,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -223,6 +224,11 @@ struct omap3_gpmc_regs {
> struct gpmc_cs_config cs_context[GPMC_CS_NUM];
> };
>
> +struct gpmc_device {
> + struct device *dev;
> + struct gpio_chip gpio_chip;
> +};
> +
> static struct resource gpmc_mem_root;
> static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
> static DEFINE_SPINLOCK(gpmc_mem_lock);
> @@ -1919,10 +1925,69 @@ err:
> return ret;
> }
>
> +static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
> +{
> + return 1; /* we're input only */
> +}
> +
> +static int gpmc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
> +{
> + return 0; /* we're input only */
> +}
> +
> +static int gpmc_gpio_direction_output(struct gpio_chip *chip, unsigned
> offset,
> + int value)
> +{
> + return -EINVAL; /* we're input only */
> +}
> +
> +static void gpmc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
> +{
> +}
> +
> +static int gpmc_gpio_get(struct gpio_chip *chip, unsigned offset)
> +{
> + u32 reg;
> +
> + offset += 8;
> +
> + reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
> +
> + return !!reg;
> +}
> +
> +static int gpmc_gpio_init(struct gpmc_device *gpmc)
> +{
> + int ret;
> +
> + gpmc->gpio_chip.dev = gpmc->dev;
> + gpmc->gpio_chip.owner = THIS_MODULE;
> + gpmc->gpio_chip.label = DEVICE_NAME;
> + gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
> + gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
> + gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
> + gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
> + gpmc->gpio_chip.set = gpmc_gpio_set;
> + gpmc->gpio_chip.get = gpmc_gpio_get;
> + gpmc->gpio_chip.base = -1;
> +
> + ret = gpiochip_add(&gpmc->gpio_chip);
> + if (ret < 0) {
> + dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void gpmc_gpio_exit(struct gpmc_device *gpmc)
> +{
> + gpiochip_remove(&gpmc->gpio_chip);
> +}
> +
> static int gpmc_probe_dt(struct platform_device *pdev)
> {
> int ret;
> - struct device_node *child;
> const struct of_device_id *of_id =
> of_match_device(gpmc_dt_ids, &pdev->dev);
>
> @@ -1950,6 +2015,17 @@ static int gpmc_probe_dt(struct platform_device *pdev)
> return ret;
> }
>
> + dev_info(&pdev->dev, "num-cs %d, num-wait %d\n",
> + gpmc_cs_num, gpmc_nr_waitpins);
> +
> + return 0;
> +}
> +
> +static int gpmc_probe_dt_children(struct platform_device *pdev)
> +{
> + int ret;
> + struct device_node *child;
> +
> for_each_available_child_of_node(pdev->dev.of_node, child) {
>
> if (!child->name)
> @@ -1959,6 +2035,9 @@ static int gpmc_probe_dt(struct platform_device *pdev)
> ret = gpmc_probe_onenand_child(pdev, child);
> else
> ret = gpmc_probe_generic_child(pdev, child);
> +
> + if (ret)
> + return ret;
> }
>
> return 0;
> @@ -1968,6 +2047,11 @@ static int gpmc_probe_dt(struct platform_device *pdev)
> {
> return 0;
> }
> +
> +static int gpmc_probe_dt_children(struct platform_device *pdev)
> +{
> + return 0;
> +}
> #endif
>
> static int gpmc_probe(struct platform_device *pdev)
> @@ -1975,6 +2059,7 @@ static int gpmc_probe(struct platform_device *pdev)
> int rc;
> u32 l;
> struct resource *res;
> + struct gpmc_device *gpmc;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>
Re: [PATCH v2 06/22] mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty check
On 07/08/15 12:12, Roger Quadros wrote:
> Instead of accessing the gpmc_status register directly start
> using the gpmc_nand_ops->nand_writebuffer_empty() helper
> to check write buffer empty status.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/omap2.c | 12 ++--
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index f214fe2..5c2f6df 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -289,15 +289,11 @@ static void omap_write_buf8(struct mtd_info *mtd, const
> u_char *buf, int len)
> struct omap_nand_info *info = container_of(mtd,
> struct omap_nand_info, mtd);
> u_char *p = (u_char *)buf;
> - u32 status = 0;
>
> while (len--) {
> iowrite8(*p++, info->nand.IO_ADDR_W);
> /* wait until buffer is available for write */
> - do {
> - status = readl(info->reg.gpmc_status) &
> - STATUS_BUFF_EMPTY;
> - } while (!status);
> + while (info->ops->nand_writebuffer_empty());
This should be
while (!info->ops->nand_writebuffer_empty());
> }
> }
>
> @@ -325,17 +321,13 @@ static void omap_write_buf16(struct mtd_info *mtd,
> const u_char * buf, int len)
> struct omap_nand_info *info = container_of(mtd,
> struct omap_nand_info, mtd);
> u16 *p = (u16 *) buf;
> - u32 status = 0;
> /* FIXME try bursts of writesw() or DMA ... */
> len >>= 1;
>
> while (len--) {
> iowrite16(*p++, info->nand.IO_ADDR_W);
> /* wait until buffer is available for write */
> - do {
> - status = readl(info->reg.gpmc_status) &
> - STATUS_BUFF_EMPTY;
> - } while (!status);
> + while (info->ops->nand_writebuffer_empty());
here as well.
> }
> }
>
>
cheers,
-roger
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Re: [PATCH v2 00/22] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
On 11/08/15 15:48, Tony Lindgren wrote: > * Roger Quadros [150807 02:15]: >> Hi, >> >> We do a couple of things in this series which result in >> cleaner device tree implementation, faster perfomance and >> multi-platform support. As an added bonus we get new GPI/Interrupt pins >> for use in the system. >> >> - Establish a custom interface between NAND and GPMC driver. This is >> needed because all of the NAND registers sit in the GPMC register space. >> Some bits like NAND IRQ are even shared with GPMC. >> >> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >> This causes performance increase when using prefetch-irq mode. >> 30% increase in read, 17% increase in write in prefetch-irq mode. >> >> - Clean up device tree support so that omap-gpmc IP and the omap2 NAND >> driver can be used on non-OMAP platforms. e.g. Keystone. >> >> - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain >> 2 to 4 of these and most of them would be unused otherwise. It also >> allows a cleaner implementation of NAND Ready pin status for the NAND driver. >> >> - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. > > Nice job :) Using GPIOCHIP + IRQCHIP allows us to make the GPMC > using drivers pretty much generic eventually. Thanks :) > >> NOTE: I've only adapted dra7.dtsi and dra7x-evms for this series. >> I will adapt all other boards when the series is in a shape to be accepted. > > OK. Yeah let's make sure no regressions are caused by this.. We also > still have the omap3 legacy booting around, have you checked that it > keeps on working? I don't have any omap3 board with legacy support with me. I have omap3-beagle but looks like legacy boot is dropped for it already. I'll try to revert the patch that drops beagle support and test it on that one. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 02/22] ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 --
include/linux/platform_data/gpmc-omap.h | 139
2 files changed, 139 insertions(+), 134 deletions(-)
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 5c79190..2dcef1c 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -14,140 +14,6 @@
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
-#define GPMC_BURST_4 4 /* 4 word burst */
-#define GPMC_BURST_8 8 /* 8 word burst */
-#define GPMC_BURST_16 16 /* 16 word burst */
-#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
-#define GPMC_DEVWIDTH_16BIT2 /* 16-bit device width */
-#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
-#define GPMC_MUX_AD2 /* Addr-Data multiplex */
-
-/* bool type time settings */
-struct gpmc_bool_timings {
- bool cycle2cyclediffcsen;
- bool cycle2cyclesamecsen;
- bool we_extra_delay;
- bool oe_extra_delay;
- bool adv_extra_delay;
- bool cs_extra_delay;
- bool time_para_granularity;
-};
-
-/*
- * Note that all values in this struct are in nanoseconds except sync_clk
- * (which is in picoseconds), while the register values are in gpmc_fck cycles.
- */
-struct gpmc_timings {
- /* Minimum clock period for synchronous mode (in picoseconds) */
- u32 sync_clk;
-
- /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
- u32 cs_on; /* Assertion time */
- u32 cs_rd_off; /* Read deassertion time */
- u32 cs_wr_off; /* Write deassertion time */
-
- /* ADV signal timings corresponding to GPMC_CONFIG3 */
- u32 adv_on; /* Assertion time */
- u32 adv_rd_off; /* Read deassertion time */
- u32 adv_wr_off; /* Write deassertion time */
-
- /* WE signals timings corresponding to GPMC_CONFIG4 */
- u32 we_on; /* WE assertion time */
- u32 we_off; /* WE deassertion time */
-
- /* OE signals timings corresponding to GPMC_CONFIG4 */
- u32 oe_on; /* OE assertion time */
- u32 oe_off; /* OE deassertion time */
-
- /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
- u32 page_burst_access; /* Multiple access word delay */
- u32 access; /* Start-cycle to first data valid delay */
- u32 rd_cycle; /* Total read cycle time */
- u32 wr_cycle; /* Total write cycle time */
-
- u32 bus_turnaround;
- u32 cycle2cycle_delay;
-
- u32 wait_monitoring;
- u32 clk_activation;
-
- /* The following are only on OMAP3430 */
- u32 wr_access; /* WRACCESSTIME */
- u32 wr_data_mux_bus;/* WRDATAONADMUXBUS */
-
- struct gpmc_bool_timings bool_timings;
-};
-
-/* Device timings in picoseconds */
-struct gpmc_device_timings {
- u32 t_ceasu;/* address setup to CS valid */
- u32 t_avdasu; /* address setup to ADV valid */
- /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
-* of tusb using these timings even for sync whilst
-* ideally for adv_rd/(wr)_off it should have considered
-* t_avdh instead. This indirectly necessitates r/w
-* variations of t_avdp as it is possible to have one
-* sync & other async
-*/
- u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
- u32 t_avdp_w;
- u32 t_aavdh;/* address hold time */
- u32 t_oeasu;/* address setup to OE valid */
- u32 t_aa; /* access time from ADV assertion */
- u32 t_iaa; /* initial access time */
- u32 t_oe; /* access time from OE assertion */
- u32 t_ce; /* access time from CS asertion */
- u32 t_rd_cycle; /* read cycle time */
- u32 t_cez_r;/* read CS deassertion to high Z */
- u32 t_cez_w;/* write CS deassertion to high Z */
- u32 t_oez; /* OE deassertion to high Z */
- u32 t_weasu;/* address setup to WE valid */
- u32 t_wpl; /* write assertion time */
- u32 t_wph; /* write deassertion time */
- u32 t_wr_cycle; /* write cycle time */
-
- u32 clk;
- u32 t_bacc; /* burst access valid clock to output delay */
- u32 t_ces; /* CS setup time to clk */
- u32 t_avds; /* ADV setup time to clk */
- u32 t_avdh; /* ADV hold time from clk */
- u32 t_ach; /* address hold time from clk */
- u32 t_rdyo; /* clk to ready valid */
-
- u32 t_ce_rdyz; /* XXX: description ?, or use t_cez
[PATCH v2 01/22] ARM: OMAP2+: gpmc: Add platform data
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30 ++
2 files changed, 31 insertions(+), 2 deletions(-)
create mode 100644 include/linux/platform_data/gpmc-omap.h
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 7dee0014..5c79190 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -7,8 +7,7 @@
* option) any later version.
*/
-/* Maximum Number of Chip Selects */
-#define GPMC_CS_NUM8
+#include
#define GPMC_CONFIG_WP 0x0005
diff --git a/include/linux/platform_data/gpmc-omap.h
b/include/linux/platform_data/gpmc-omap.h
new file mode 100644
index 000..d32d9de
--- /dev/null
+++ b/include/linux/platform_data/gpmc-omap.h
@@ -0,0 +1,30 @@
+/*
+ * OMAP GPMC Platform data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc. - http://www.ti.com
+ * Roger Quadros
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _GPMC_OMAP_H_
+#define _GPMC_OMAP_H_
+
+/* Maximum Number of Chip Selects */
+#define GPMC_CS_NUM8
+
+/* Data for each chip select */
+struct gpmc_omap_cs_data {
+ bool valid; /* data is valid */
+ bool is_nand; /* device within this CS is NAND */
+ struct platform_device *pdev; /* device within this CS region */
+ unsigned pdata_size;
+};
+
+struct gpmc_omap_platform_data {
+ struct gpmc_omap_cs_data cs[GPMC_CS_NUM];
+};
+
+#endif /* _GPMC_OMAP_H */
--
2.1.4
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[PATCH v2 03/22] memory: omap-gpmc: Introduce GPMC to NAND interface
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1) FIFOEVENT and TERMCOUNT from GPMC_IRQENABLE and GPMC_IRQSTATUS
2) EMPTYWRITEBUFFERSTATUS from GPMC_STATUS
For accessing these bits we introduce the struct gpmc_nand_ops.
Rename the gpmc_update_nand_reg() API to gpmc_omap_get_nand_ops()
and make it return the gpmc_nand_ops along with updating the
gpmc_nand_regs. This API will be called by the OMAP NAND driver
to access the necessary bits in GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 21 +
include/linux/omap-gpmc.h | 42 --
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 3a27a84..79d78ab 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1099,6 +1099,27 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg,
int cs)
}
}
+static struct gpmc_nand_ops nand_ops;
+
+/**
+ * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
+ * @regs: the GPMC NAND register map exclusive for NAND use.
+ * @cs: GPMC chip select number on which the NAND sits. The
+ * register map returned will be specific to this chip select.
+ *
+ * Returns NULL on error e.g. invalid cs.
+ */
+struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int
cs)
+{
+ if (cs >= gpmc_cs_num)
+ return NULL;
+
+ gpmc_update_nand_reg(reg, cs);
+
+ return &nand_ops;
+}
+EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
+
int gpmc_get_client_irq(unsigned irq_config)
{
int i;
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 2dcef1c..a811c91 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -14,14 +14,52 @@
#define GPMC_IRQ_FIFOEVENTENABLE 0x01
#define GPMC_IRQ_COUNT_EVENT 0x02
+enum gpmc_nand_irq {
+ GPMC_NAND_IRQ_FIFOEVENT = 0,
+ GPMC_NAND_IRQ_TERMCOUNT,
+};
+
+/**
+ * gpmc_nand_ops - Interface between NAND and GPMC
+ * @nand_irq_enable: enable the requested GPMC NAND interrupt event.
+ * @nand_irq_disable: disable the requested GPMC NAND interrupt event.
+ * @nand_irq_clear: clears the GPMC NAND interrupt event status.
+ * @nand_irq_status: get the NAND interrupt event status.
+ * @nand_write_buffer_empty: get the NAND write buffer empty status.
+ */
+struct gpmc_nand_ops {
+ int (*nand_irq_enable)(enum gpmc_nand_irq irq);
+ int (*nand_irq_disable)(enum gpmc_nand_irq irq);
+ void (*nand_irq_clear)(enum gpmc_nand_irq irq);
+ u32 (*nand_irq_status)(void);
+ bool (*nand_writebuffer_empty)(void);
+};
+
+struct gpmc_nand_regs;
+
+#if IS_ENABLED(CONFIG_OMAP_GPMC)
+struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
+int cs);
+#else
+static inline gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs
*regs,
+ int cs);
+{
+ return NULL;
+}
+#endif /* CONFIG_OMAP_GPMC */
+
+/**/
+
+/* deprecated APIs */
+extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+/**/
+
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
struct gpmc_settings *gpmc_s,
struct gpmc_device_timings *dev_t);
-struct gpmc_nand_regs;
struct device_node;
-extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
extern int gpmc_get_client_irq(unsigned irq_config);
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
--
2.1.4
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[PATCH v2 05/22] memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 79d78ab..41df030 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -81,6 +81,8 @@
#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
+#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
+
#defineGPMC_CONFIG2_CSEXTRADELAY BIT(7)
#defineGPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#defineGPMC_CONFIG4_OEEXTRADELAY BIT(7)
@@ -1099,7 +1101,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg,
int cs)
}
}
-static struct gpmc_nand_ops nand_ops;
+static bool gpmc_nand_writebuffer_empty(void)
+{
+ if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
+ return true;
+
+ return false;
+}
+
+static struct gpmc_nand_ops nand_ops = {
+ .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
+};
/**
* gpmc_omap_get_nand_ops - Get the GPMC NAND interface
--
2.1.4
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[PATCH v2 04/22] mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 72918c4..04e6998 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -121,8 +121,6 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
if (err < 0)
goto out_free_cs;
- gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
-
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
err = -EINVAL;
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 60fa899..f214fe2 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#defineDRIVER_NAME "omap2-nand"
@@ -169,7 +170,9 @@ struct omap_nand_info {
} iomode;
u_char *buf;
int buf_len;
+ /* Interface to GPMC */
struct gpmc_nand_regs reg;
+ struct gpmc_nand_ops*ops;
/* generated at runtime depending on ECC algorithm and layout selected
*/
struct nand_ecclayout oobinfo;
/* fields specific for BCHx_HW ECC scheme */
@@ -1677,9 +1680,13 @@ static int omap_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info);
+ info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
+ if (!info->ops) {
+ dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
+ return -ENODEV;
+ }
info->pdev = pdev;
info->gpmc_cs = pdata->cs;
- info->reg = pdata->reg;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
mtd = &info->mtd;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 090bbab..a067f58 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -75,10 +75,12 @@ struct omap_nand_platform_data {
enum nand_ioxfer_type;
int devsize;
enum omap_ecc ecc_opt;
- struct gpmc_nand_regs reg;
/* for passing the partitions */
struct device_node *of_node;
struct device_node *elm_of_node;
+
+ /* deprecated */
+ struct gpmc_nand_regs reg;
};
#endif
--
2.1.4
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[PATCH v2 06/22] mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty check
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f214fe2..5c2f6df 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -289,15 +289,11 @@ static void omap_write_buf8(struct mtd_info *mtd, const
u_char *buf, int len)
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u_char *p = (u_char *)buf;
- u32 status = 0;
while (len--) {
iowrite8(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
- do {
- status = readl(info->reg.gpmc_status) &
- STATUS_BUFF_EMPTY;
- } while (!status);
+ while (info->ops->nand_writebuffer_empty());
}
}
@@ -325,17 +321,13 @@ static void omap_write_buf16(struct mtd_info *mtd, const
u_char * buf, int len)
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u16 *p = (u16 *) buf;
- u32 status = 0;
/* FIXME try bursts of writesw() or DMA ... */
len >>= 1;
while (len--) {
iowrite16(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
- do {
- status = readl(info->reg.gpmc_status) &
- STATUS_BUFF_EMPTY;
- } while (!status);
+ while (info->ops->nand_writebuffer_empty());
}
}
--
2.1.4
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[PATCH v2 07/22] memory: omap-gpmc: Remove NAND IRQ code
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 164 +---
include/linux/omap-gpmc.h | 5 +-
3 files changed, 5 insertions(+), 168 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 04e6998..ffe646a 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -80,7 +80,6 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
struct resource gpmc_nand_res[] = {
{ .flags = IORESOURCE_MEM, },
{ .flags = IORESOURCE_IRQ, },
- { .flags = IORESOURCE_IRQ, },
};
BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
@@ -93,8 +92,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
return err;
}
gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
- gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
- gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+ gpmc_nand_res[1].start = gpmc_get_irq();
memset(&s, 0, sizeof(struct gpmc_settings));
if (gpmc_nand_data->of_node)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 41df030..e70a8df 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -123,12 +123,6 @@
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
-/* Control Commands */
-#define GPMC_CONFIG_RDY_BSY0x0001
-#define GPMC_CONFIG_DEV_SIZE 0x0002
-#define GPMC_CONFIG_DEV_TYPE 0x0003
-#define GPMC_SET_IRQ_STATUS0x0004
-
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -176,17 +170,11 @@
#define GPMC_CONFIG_WRITEPROTECT 0x0010
#define WR_RD_PIN_MONITORING 0x0060
-#define GPMC_ENABLE_IRQ0x000d
-
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
-/* XXX: Only NAND irq has been considered,currently these are the only ones
used
- */
-#defineGPMC_NR_IRQ 2
-
enum gpmc_clk_domain {
GPMC_CD_FCLK,
GPMC_CD_CLK
@@ -201,11 +189,6 @@ struct gpmc_cs_data {
struct resource mem;
};
-struct gpmc_client_irq {
- unsignedirq;
- u32 bitmask;
-};
-
/* Structure to save gpmc cs context */
struct gpmc_cs_config {
u32 config1;
@@ -233,10 +216,6 @@ struct omap3_gpmc_regs {
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
-static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
-static struct irq_chip gpmc_irq_chip;
-static int gpmc_irq_start;
-
static struct resource gpmc_mem_root;
static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -244,15 +223,13 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned int gpmc_cs_num = GPMC_CS_NUM;
static unsigned int gpmc_nr_waitpins;
static struct device *gpmc_dev;
-static int gpmc_irq;
+static int gpmc_irq = -EINVAL;
static resource_size_t phys_base, mem_size;
static unsigned gpmc_capability;
static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk;
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
-
static void gpmc_write_reg(int idx, u32 val)
{
writel_relaxed(val, gpmc_base + idx);
@@ -1037,14 +1014,6 @@ int gpmc_configure(int cmd, int wval)
u32 regval;
switch (cmd) {
- case GPMC_ENABLE_IRQ:
- gpmc_write_reg(GPMC_IRQENABLE, wval);
- break;
-
- case GPMC_SET_IRQ_STATUS:
- gpmc_write_reg(GPMC_IRQSTATUS, wval);
- break;
-
case GPMC_CONFIG_WP:
regval = gpmc_read_reg(GPMC_CONFIG);
if (wval)
@@ -1132,113 +1101,9 @@ struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct
gpmc_nand_regs *reg, int cs)
}
EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
-int gpmc_get_client_irq(unsigned irq_config)
-{
- int i;
-
- if (hweight32(irq_config) > 1)
- return 0;
-
- for (i = 0; i < GPMC_NR_IRQ; i++)
- if (gpmc_client_irq[i].bitmask & irq_config)
- return gpmc_client_irq[i].irq;
-
- return 0;
-}
-
-static int gpmc_irq_endis(unsigned irq, bool endis)
-{
- int i;
- u32 regval;
-
- for (i = 0; i < GPMC_NR_IRQ; i++)
- if (irq == gpmc_client_irq[i].irq) {
-
[PATCH v2 08/22] memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4
2 files changed, 54 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index e70a8df..713d7af 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1078,8 +1078,58 @@ static bool gpmc_nand_writebuffer_empty(void)
return false;
}
+static int gpmc_nand_irq_enable(enum gpmc_nand_irq irq)
+{
+ u32 reg;
+
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return -EINVAL;
+
+ reg = gpmc_read_reg(GPMC_IRQENABLE);
+ reg |= BIT(irq);
+ gpmc_write_reg(GPMC_IRQENABLE, reg);
+
+ return 0;
+}
+
+static int gpmc_nand_irq_disable(enum gpmc_nand_irq irq)
+{
+ u32 reg;
+
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return -EINVAL;
+
+ reg = gpmc_read_reg(GPMC_IRQENABLE);
+ reg &= ~BIT(irq);
+ gpmc_write_reg(GPMC_IRQENABLE, reg);
+
+ return 0;
+}
+
+static void gpmc_nand_irq_clear(enum gpmc_nand_irq irq)
+{
+ if (irq > GPMC_NAND_IRQ_TERMCOUNT)
+ return;
+
+ /* setting bit to 1 clears the bit in IRQSTATUS */
+ gpmc_write_reg(GPMC_IRQSTATUS, BIT(irq));
+}
+
+static u32 gpmc_nand_irq_status(void)
+{
+ u32 reg = gpmc_read_reg(GPMC_IRQSTATUS);
+
+ /* Mask out non-NAND bits */
+ reg &= GPMC_IRQENABLE_FIFOEVENT | GPMC_IRQENABLE_TERMCOUNT;
+ return reg;
+}
+
static struct gpmc_nand_ops nand_ops = {
.nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
+ .nand_irq_enable = gpmc_nand_irq_enable,
+ .nand_irq_disable = gpmc_nand_irq_disable,
+ .nand_irq_clear = gpmc_nand_irq_clear,
+ .nand_irq_status = gpmc_nand_irq_status,
};
/**
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
index 44e322f..063a84f 100644
--- a/include/linux/omap-gpmc.h
+++ b/include/linux/omap-gpmc.h
@@ -11,6 +11,10 @@
#define GPMC_CONFIG_WP 0x0005
+/* GPMC IRQENABLE/IRQSTATUS BIT defs */
+#define GPMC_IRQENABLE_FIFOEVENT BIT(0)
+#define GPMC_IRQENABLE_TERMCOUNT BIT(1)
+
enum gpmc_nand_irq {
GPMC_NAND_IRQ_FIFOEVENT = 0,
GPMC_NAND_IRQ_TERMCOUNT,
--
2.1.4
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[PATCH v2 12/22] mtd: nand: omap: Update DT binding documentation
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4..253e6de 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt
Required properties:
- - reg:The CS line the peripheral is connected to
+ - compatible: "ti,omap2-nand"
+ - reg:range id (CS number), base offset and length of the
+ NAND I/O space
+ - interrupt-parent: must point to gpmc node
+ - interrupts: gpmc interrupt
Optional properties:
@@ -55,20 +59,24 @@ Example for an AM33xx board:
gpmc: gpmc@5000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
- reg = <0x5000 0x100>;
+ reg = <0x5000 0x36c>;
interrupts = <100>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 0x0800 0x2000>; /* CS0: NAND */
+ ranges = <0 0 0x0800 0x100>;/* CS0 space, 16MB */
elm_id = <&elm>;
nand@0,0 {
- reg = <0 0 0>; /* CS0, offset 0 */
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, NAND I/O
window 4 */
+ interrupts = <100>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
+ interrupt-parent = <&gpmc>;
+ interrupts = <0>, <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
--
2.1.4
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[PATCH v2 10/22] mtd: nand: omap: Copy platform data parameters to omap_nand_info data
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index cabc5ea..589404c 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -152,14 +152,18 @@ static struct nand_hw_control omap_gpmc_controller = {
};
struct omap_nand_info {
- struct omap_nand_platform_data *pdata;
struct mtd_info mtd;
struct nand_chipnand;
struct platform_device *pdev;
int gpmc_cs;
- unsigned long phys_base;
+ booldev_ready;
+ enum nand_ioxfer_type;
+ int devsize;
enum omap_ecc ecc_opt;
+ struct device_node *elm_of_node;
+
+ unsigned long phys_base;
struct completion comp;
struct dma_chan *dma;
int gpmc_irq;
@@ -1650,7 +1654,7 @@ static bool omap2_nand_ecc_check(struct omap_nand_info
*info,
"CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
return false;
}
- if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) {
+ if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
dev_err(&info->pdev->dev, "ELM not available\n");
return false;
}
@@ -1695,6 +1699,11 @@ static int omap_nand_probe(struct platform_device *pdev)
info->gpmc_cs = pdata->cs;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
+ info->dev_ready = pdata->dev_ready;
+ info->xfer_type = pdata->xfer_type;
+ info->devsize = pdata->devsize;
+ info->elm_of_node = pdata->elm_of_node;
+
mtd = &info->mtd;
mtd->priv = &info->nand;
mtd->name = dev_name(&pdev->dev);
@@ -1721,7 +1730,7 @@ static int omap_nand_probe(struct platform_device *pdev)
* chip delay which is slightly more than tR (AC Timing) of the NAND
* device and read status register until you get a failure or success
*/
- if (pdata->dev_ready) {
+ if (info->dev_ready) {
nand_chip->dev_ready = omap_dev_ready;
nand_chip->chip_delay = 0;
} else {
@@ -1735,15 +1744,16 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->options |= NAND_SKIP_BBTSCAN;
/* scan NAND device connected to chip controller */
- nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
+ nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
if (nand_scan_ident(mtd, 1, NULL)) {
- dev_err(&info->pdev->dev, "scan failed, may be bus-width
mismatch\n");
+ dev_err(&info->pdev->dev,
+ "scan failed, may be bus-width mismatch\n");
err = -ENXIO;
goto return_error;
}
/* re-populate low-level callbacks based on xfer modes */
- switch (pdata->xfer_type) {
+ switch (info->xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
nand_chip->read_buf = omap_read_buf_pref;
nand_chip->write_buf = omap_write_buf_pref;
@@ -1806,7 +1816,7 @@ static int omap_nand_probe(struct platform_device *pdev)
default:
dev_err(&pdev->dev,
- "xfer_type(%d) not supported!\n", pdata->xfer_type);
+ "xfer_type(%d) not supported!\n", info->xfer_type);
err = -EINVAL;
goto return_error;
}
--
2.1.4
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[PATCH v2 14/22] ARM: dts: OMAP2+: Fix NAND device nodes.
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
TODO: For now only dra7-evm and omap3-beagle are fixed.
Once series is reviewed I'll update this patch to
fix all omap boards.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 4 +++-
arch/arm/boot/dts/omap3-beagle.dts | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 096f68b..ce11b0f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -569,9 +569,11 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
- ranges = <0 0 0 0x0100>;/* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x0800 0x0100>; /* minimum GPMC partition =
16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupts = ;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index a547411..34cf55e 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -384,7 +384,8 @@
/* Chip select 0 */
nand@0,0 {
- reg = <0 0 4>; /* NAND I/O window, 4 bytes */
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupts = <20>;
ti,nand-ecc-opt = "ham1";
nand-bus-width = <16>;
--
2.1.4
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[PATCH v2 11/22] mtd: nand: omap: Clean up device tree support
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135 ++
drivers/mtd/nand/omap2.c | 136 +++
include/linux/platform_data/mtd-nand-omap2.h | 3 +-
4 files changed, 147 insertions(+), 132 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index ffe646a..e07ca27 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -95,10 +95,7 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_nand_res[1].start = gpmc_get_irq();
memset(&s, 0, sizeof(struct gpmc_settings));
- if (gpmc_nand_data->of_node)
- gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
- else
- gpmc_set_legacy(gpmc_nand_data, &s);
+ gpmc_set_legacy(gpmc_nand_data, &s);
s.device_nand = true;
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 713d7af..1c87252 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -29,7 +29,6 @@
#include
#include
#include
-#include
#include
#include
@@ -1716,105 +1715,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
of_property_read_bool(np, "gpmc,time-para-granularity");
}
-#if IS_ENABLED(CONFIG_MTD_NAND)
-
-static const char * const nand_xfer_types[] = {
- [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
- [NAND_OMAP_POLLED] = "polled",
- [NAND_OMAP_PREFETCH_DMA]= "prefetch-dma",
- [NAND_OMAP_PREFETCH_IRQ]= "prefetch-irq",
-};
-
-static int gpmc_probe_nand_child(struct platform_device *pdev,
-struct device_node *child)
-{
- u32 val;
- const char *s;
- struct gpmc_timings gpmc_t;
- struct omap_nand_platform_data *gpmc_nand_data;
-
- if (of_property_read_u32(child, "reg", &val) < 0) {
- dev_err(&pdev->dev, "%s has no 'reg' property\n",
- child->full_name);
- return -ENODEV;
- }
-
- gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
- GFP_KERNEL);
- if (!gpmc_nand_data)
- return -ENOMEM;
-
- gpmc_nand_data->cs = val;
- gpmc_nand_data->of_node = child;
-
- /* Detect availability of ELM module */
- gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
- if (gpmc_nand_data->elm_of_node == NULL)
- gpmc_nand_data->elm_of_node =
- of_parse_phandle(child, "elm_id", 0);
-
- /* select ecc-scheme for NAND */
- if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
- pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
- return -ENODEV;
- }
-
- if (!strcmp(s, "sw"))
- gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
- else if (!strcmp(s, "ham1") ||
-!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_HAM1_CODE_HW;
- else if (!strcmp(s, "bch4"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch8"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW;
- else
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
- else if (!strcmp(s, "bch16"))
- if (gpmc_nand_data->elm_of_node)
- gpmc_nand_data->ecc_opt =
- OMAP_ECC_BCH16_CODE_HW;
- else
- pr_err("%s: BCH16 requires ELM support\n", __func__);
- else
- pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
-
- /* select data transfer mode for NAND controller */
- if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
- for
[PATCH v2 17/22] memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 264009d..0df70ab 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1779,6 +1779,8 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
const char *name;
int ret, cs;
u32 val;
+ struct gpio_desc *waitpin_desc = NULL;
+ struct gpmc_device *gpmc = platform_get_drvdata(pdev);
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%s has no 'reg' property\n",
@@ -1880,15 +1882,28 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
goto err;
}
+ /* Reserve wait pin if it is required and valid */
+ if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
+ unsigned wait_pin = gpmc_s.wait_pin;
+
+ waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
+wait_pin, "WAITPIN");
+ if (IS_ERR(waitpin_desc)) {
+ dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
+ ret = PTR_ERR(waitpin_desc);
+ goto err;
+ }
+ }
+
ret = gpmc_cs_program_settings(cs, &gpmc_s);
if (ret < 0)
- goto err;
+ goto err_cs;
ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
if (ret) {
dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
child->name);
- goto err;
+ goto err_cs;
}
/* Clear limited address i.e. enable A26-A11 */
@@ -1919,6 +1934,10 @@ err_child_fail:
dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
ret = -ENODEV;
+err_cs:
+ if (waitpin_desc)
+ gpiochip_free_own_desc(waitpin_desc);
+
err:
gpmc_cs_free(cs);
--
2.1.4
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[PATCH v2 13/22] memory: omap-gpmc: Prevent mapping into 1st 16MB
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 1c87252..30d9c21 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -93,6 +93,14 @@
#define GPMC_CS_SIZE 0x30
#defineGPMC_BCH_SIZE 0x10
+/*
+ * The first 1MB of GPMC address space is typically mapped to
+ * the internal ROM. Never allocate the first page, to
+ * facilitate bug detection; even if we didn't boot from ROM.
+ * As GPMC minimum partition size is 16MB we can only start from
+ * there.
+ */
+#define GPMC_MEM_START 0x100
#define GPMC_MEM_END 0x3FFF
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
@@ -1171,12 +1179,7 @@ static void gpmc_mem_init(void)
{
int cs;
- /*
-* The first 1MB of GPMC address space is typically mapped to
-* the internal ROM. Never allocate the first page, to
-* facilitate bug detection; even if we didn't boot from ROM.
-*/
- gpmc_mem_root.start = SZ_1M;
+ gpmc_mem_root.start = GPMC_MEM_START;
gpmc_mem_root.end = GPMC_MEM_END;
/* Reserve all regions that has been set up by bootloader */
@@ -1830,6 +1833,15 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
if (ret < 0) {
dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
cs, &res.start);
+ if (res.start < GPMC_MEM_START) {
+ dev_info(&pdev->dev,
+"GPMC CS %d start cannot be lesser than
0x%x\n",
+cs, GPMC_MEM_START);
+ } else if (res.end > GPMC_MEM_END) {
+ dev_info(&pdev->dev,
+"GPMC CS %d end cannot be greater than 0x%x\n",
+cs, GPMC_MEM_END);
+ }
goto err;
}
--
2.1.4
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[PATCH v2 15/22] memory: omap-gpmc: Move device tree binding to correct location
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.txt =>
memory-controllers/omap-gpmc.txt} (100%)
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/bus/ti-gpmc.txt
rename to Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
--
2.1.4
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[PATCH v2 16/22] memory: omap-gpmc: Support general purpose input for WAITPINs
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 122 +++--
1 file changed, 117 insertions(+), 5 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 30d9c21..264009d 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -223,6 +224,11 @@ struct omap3_gpmc_regs {
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
+struct gpmc_device {
+ struct device *dev;
+ struct gpio_chip gpio_chip;
+};
+
static struct resource gpmc_mem_root;
static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -1919,10 +1925,69 @@ err:
return ret;
}
+static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ return 1; /* we're input only */
+}
+
+static int gpmc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ return 0; /* we're input only */
+}
+
+static int gpmc_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ return -EINVAL; /* we're input only */
+}
+
+static void gpmc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+}
+
+static int gpmc_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ u32 reg;
+
+ offset += 8;
+
+ reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
+
+ return !!reg;
+}
+
+static int gpmc_gpio_init(struct gpmc_device *gpmc)
+{
+ int ret;
+
+ gpmc->gpio_chip.dev = gpmc->dev;
+ gpmc->gpio_chip.owner = THIS_MODULE;
+ gpmc->gpio_chip.label = DEVICE_NAME;
+ gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
+ gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
+ gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
+ gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
+ gpmc->gpio_chip.set = gpmc_gpio_set;
+ gpmc->gpio_chip.get = gpmc_gpio_get;
+ gpmc->gpio_chip.base = -1;
+
+ ret = gpiochip_add(&gpmc->gpio_chip);
+ if (ret < 0) {
+ dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void gpmc_gpio_exit(struct gpmc_device *gpmc)
+{
+ gpiochip_remove(&gpmc->gpio_chip);
+}
+
static int gpmc_probe_dt(struct platform_device *pdev)
{
int ret;
- struct device_node *child;
const struct of_device_id *of_id =
of_match_device(gpmc_dt_ids, &pdev->dev);
@@ -1950,6 +2015,17 @@ static int gpmc_probe_dt(struct platform_device *pdev)
return ret;
}
+ dev_info(&pdev->dev, "num-cs %d, num-wait %d\n",
+gpmc_cs_num, gpmc_nr_waitpins);
+
+ return 0;
+}
+
+static int gpmc_probe_dt_children(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *child;
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
if (!child->name)
@@ -1959,6 +2035,9 @@ static int gpmc_probe_dt(struct platform_device *pdev)
ret = gpmc_probe_onenand_child(pdev, child);
else
ret = gpmc_probe_generic_child(pdev, child);
+
+ if (ret)
+ return ret;
}
return 0;
@@ -1968,6 +2047,11 @@ static int gpmc_probe_dt(struct platform_device *pdev)
{
return 0;
}
+
+static int gpmc_probe_dt_children(struct platform_device *pdev)
+{
+ return 0;
+}
#endif
static int gpmc_probe(struct platform_device *pdev)
@@ -1975,6 +2059,7 @@ static int gpmc_probe(struct platform_device *pdev)
int rc;
u32 l;
struct resource *res;
+ struct gpmc_device *gpmc;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
@@ -2005,6 +2090,17 @@ static int gpmc_probe(struct platform_device *pdev)
return -EINVAL;
}
+ rc = gpmc_probe_dt(pdev);
+ if (rc)
+ return rc;
+
+ gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
+ if (!gpmc)
+ return -ENOMEM;
+
+ gpmc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, gpmc);
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
@@ -2032,24 +2128,40 @@ static int gpmc_probe(struct platform_device *pdev)
GPMC_REVISION_MINOR(l));
gpmc_mem_init();
+ rc = gpmc_gpio_init(gpm
[PATCH v2 18/22] memory: omap-gpmc: Add irqchip support to the gpiochip
The WAIT pins support falling edge interrupts so add irqchip
support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 0df70ab..417acce 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
#include
+#include
#include
#include
#include
@@ -227,6 +228,7 @@ struct omap3_gpmc_regs {
struct gpmc_device {
struct device *dev;
struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
};
static struct resource gpmc_mem_root;
@@ -1944,6 +1946,79 @@ err:
return ret;
}
+static int gpmc_irq_endis(unsigned long hwirq, bool endis)
+{
+ u32 regval;
+
+ /* WAITPIN starts at BIT 8 */
+ hwirq += 8;
+
+ regval = gpmc_read_reg(GPMC_IRQENABLE);
+ if (endis)
+ regval |= BIT(hwirq);
+ else
+ regval &= ~BIT(hwirq);
+ gpmc_write_reg(GPMC_IRQENABLE, regval);
+
+ return 0;
+}
+
+static void gpmc_irq_mask(struct irq_data *d)
+{
+ gpmc_irq_endis(d->hwirq, false);
+}
+
+static void gpmc_irq_unmask(struct irq_data *d)
+{
+ gpmc_irq_endis(d->hwirq, true);
+}
+
+static void gpmc_irq_ack(struct irq_data *d)
+{
+ unsigned hwirq = d->hwirq + 8;
+
+ /* Setting bit to 1 clears (or Acks) the interrupt */
+ gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
+}
+
+static int gpmc_irq_set_type(struct irq_data *d, unsigned trigger)
+{
+ /* We only support falling edge interrupts */
+ if (trigger & ~IRQ_TYPE_EDGE_FALLING)
+ return -EINVAL;
+
+ return 0;
+}
+
+static irqreturn_t gpmc_handle_irq(int irq, void *data)
+{
+ int hwirq, virq;
+ u32 regval;
+ struct gpmc_device *gpmc = data;
+
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+ regval >>= 8; /* we're only interested in WAIT pins */
+
+ if (!regval)
+ return IRQ_NONE;
+
+ for (hwirq = 0; hwirq < gpmc->gpio_chip.ngpio; hwirq++) {
+ if (regval & BIT(hwirq)) {
+ virq = irq_find_mapping(gpmc->gpio_chip.irqdomain,
+ hwirq);
+ if (!virq) {
+ dev_warn(gpmc_dev,
+"spurious irq detected hwirq %d, virq
%d\n",
+hwirq, virq);
+ }
+
+ generic_handle_irq(virq);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
return 1; /* we're input only */
@@ -1978,6 +2053,7 @@ static int gpmc_gpio_get(struct gpio_chip *chip, unsigned
offset)
static int gpmc_gpio_init(struct gpmc_device *gpmc)
{
int ret;
+ u32 regval;
gpmc->gpio_chip.dev = gpmc->dev;
gpmc->gpio_chip.owner = THIS_MODULE;
@@ -1996,7 +2072,42 @@ static int gpmc_gpio_init(struct gpmc_device *gpmc)
return ret;
}
+ /* Disable interrupts */
+ gpmc_write_reg(GPMC_IRQENABLE, 0);
+
+ /* clear interrupts */
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+ gpmc_write_reg(GPMC_IRQSTATUS, regval);
+
+ gpmc->irq_chip.name = DEVICE_NAME;
+ gpmc->irq_chip.irq_ack = gpmc_irq_ack;
+ gpmc->irq_chip.irq_mask = gpmc_irq_mask;
+ gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
+ gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
+
+ ret = gpiochip_irqchip_add(&gpmc->gpio_chip, &gpmc->irq_chip, 0,
+ handle_edge_irq, IRQ_TYPE_NONE);
+
+ if (ret) {
+ dev_err(gpmc->dev, "could not add irqchip to gpiochip: %d\n",
+ ret);
+ goto fail;
+ }
+
+ /* We're sharing this IRQ with OMAP NAND driver */
+ ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc);
+ if (ret) {
+ dev_err(gpmc->dev, "could not request gpmc irq (%d): %d\n",
+ gpmc_irq, ret);
+ goto fail;
+ }
+
return 0;
+
+fail:
+ gpiochip_remove(&gpmc->gpio_chip);
+
+ return ret;
}
static void gpmc_gpio_exit(struct gpmc_device *gpmc)
--
2.1.4
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[PATCH v2 19/22] ARM: dts: dra7: Enable gpio & interrupt controller for gpmc node
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra7.dtsi | 4
arch/arm/boot/dts/dra72-evm.dts | 1 +
3 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ce11b0f..3fb1ced 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -573,6 +573,7 @@
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&crossbar_mpu>;
interrupts = ;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8f1e25b..a4ab66d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1369,6 +1369,10 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 8037384..fc0677a 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -386,6 +386,7 @@
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&crossbar_mpu>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
--
2.1.4
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[PATCH v2 20/22] mtd: nand: omap2: Implement NAND ready using gpiolib
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux/platform_data/mtd-nand-omap2.h | 2 +-
2 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index b009d1d..8ace767 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -184,6 +185,8 @@ struct omap_nand_info {
/* fields specific for BCHx_HW ECC scheme */
struct device *elm_dev;
struct device_node *of_node;
+ /* NAND ready gpio */
+ struct gpio_desc*ready_gpiod;
};
/**
@@ -1041,22 +1044,17 @@ static int omap_wait(struct mtd_info *mtd, struct
nand_chip *chip)
}
/**
- * omap_dev_ready - calls the platform specific dev_ready function
+ * omap_dev_ready - checks the NAND Ready GPIO line
* @mtd: MTD device structure
+ *
+ * Returns true if ready and false if busy.
*/
static int omap_dev_ready(struct mtd_info *mtd)
{
- unsigned int val = 0;
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
- val = readl(info->reg.gpmc_status);
-
- if ((val & 0x100) == 0x100) {
- return 1;
- } else {
- return 0;
- }
+ return gpiod_get_value(info->ready_gpiod);
}
/**
@@ -1776,7 +1774,9 @@ static int omap_nand_probe(struct platform_device *pdev)
info->reg = pdata->reg;
info->of_node = pdata->of_node;
info->ecc_opt = pdata->ecc_opt;
- info->dev_ready = pdata->dev_ready;
+ if (pdata->dev_ready)
+ dev_info(&pdev->dev, "pdata->dev_ready is
deprecated\n");
+
info->xfer_type = pdata->xfer_type;
info->devsize = pdata->devsize;
info->elm_of_node = pdata->elm_of_node;
@@ -1809,6 +1809,13 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
nand_chip->cmd_ctrl = omap_hwcontrol;
+ info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "ready",
+ GPIOD_IN);
+ if (IS_ERR(info->ready_gpiod)) {
+ dev_err(dev, "failed to get ready gpio\n");
+ return PTR_ERR(info->ready_gpiod);
+ }
+
/*
* If RDY/BSY line is connected to OMAP then use the omap ready
* function and the generic nand_wait function which reads the status
@@ -1816,7 +1823,7 @@ static int omap_nand_probe(struct platform_device *pdev)
* chip delay which is slightly more than tR (AC Timing) of the NAND
* device and read status register until you get a failure or success
*/
- if (info->dev_ready) {
+ if (info->ready_gpiod) {
nand_chip->dev_ready = omap_dev_ready;
nand_chip->chip_delay = 0;
} else {
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index ff27e5a..19e509d 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -70,7 +70,6 @@ struct omap_nand_platform_data {
int cs;
struct mtd_partition*parts;
int nr_parts;
- booldev_ready;
boolflash_bbt;
enum nand_ioxfer_type;
int devsize;
@@ -81,5 +80,6 @@ struct omap_nand_platform_data {
/* deprecated */
struct gpmc_nand_regs reg;
struct device_node *of_node;
+ booldev_ready;
};
#endif
--
2.1.4
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[PATCH v2 21/22] ARM: dts: dra7x-evm: Provide NAND ready pin
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged at 7123 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-evm.dts | 1 + arch/arm/boot/dts/dra72-evm.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 3fb1ced..b717fd0 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -575,6 +575,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = ; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index fc0677a..c1a3397 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -387,6 +387,7 @@ */ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 22/22] memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand-omap2.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 417acce..bdd1533 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -1051,7 +1051,7 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int
cs)
{
int i;
- reg->gpmc_status = gpmc_base + GPMC_STATUS;
+ reg->gpmc_status = NULL;/* deprecated */
reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 19e509d..17d57a1 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -45,7 +45,6 @@ enum omap_ecc {
};
struct gpmc_nand_regs {
- void __iomem*gpmc_status;
void __iomem*gpmc_nand_command;
void __iomem*gpmc_nand_address;
void __iomem*gpmc_nand_data;
@@ -64,6 +63,8 @@ struct gpmc_nand_regs {
void __iomem*gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
+ /* Deprecated. Do not use */
+ void __iomem*gpmc_status;
};
struct omap_nand_platform_data {
--
2.1.4
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[PATCH v2 09/22] mtd: nand: omap2: manage NAND interrupts
Manage NAND interrupts here using the GPMC IRQ ops.
This causes performance in prefetch-irq mode to be increased
from
[ 38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[ 39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s
to
[ 35.666446] mtd_speedtest: eraseblock write speed is 6537 KiB/s
[ 36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s
Test results on dra7-evm using mtd_speedtest.ko
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 63 +++-
1 file changed, 30 insertions(+), 33 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 5c2f6df..cabc5ea 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -162,8 +162,7 @@ struct omap_nand_info {
enum omap_ecc ecc_opt;
struct completion comp;
struct dma_chan *dma;
- int gpmc_irq_fifo;
- int gpmc_irq_count;
+ int gpmc_irq;
enum {
OMAP_NAND_IO_READ = 0, /* read */
OMAP_NAND_IO_WRITE, /* write */
@@ -573,12 +572,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
{
struct omap_nand_info *info = (struct omap_nand_info *) dev;
u32 bytes;
+ u32 irqstatus;
+
+ irqstatus = info->ops->nand_irq_status();
+ if (!irqstatus)
+ return IRQ_NONE;
bytes = readl(info->reg.gpmc_prefetch_status);
bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
- if (this_irq == info->gpmc_irq_count)
+ if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
goto done;
if (info->buf_len && (info->buf_len < bytes))
@@ -595,17 +599,25 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
(u32 *)info->buf, bytes >> 2);
info->buf = info->buf + bytes;
- if (this_irq == info->gpmc_irq_count)
+ if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
goto done;
}
+ /* Clear FIFOEVENT STATUS */
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+
return IRQ_HANDLED;
done:
complete(&info->comp);
- disable_irq_nosync(info->gpmc_irq_fifo);
- disable_irq_nosync(info->gpmc_irq_count);
+ /* Clear FIFOEVENT and TERMCOUNT STATUS */
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+ info->ops->nand_irq_clear(GPMC_NAND_IRQ_TERMCOUNT);
+
+ /* Disable Interrupt generation */
+ info->ops->nand_irq_disable(GPMC_NAND_IRQ_FIFOEVENT);
+ info->ops->nand_irq_disable(GPMC_NAND_IRQ_TERMCOUNT);
return IRQ_HANDLED;
}
@@ -640,8 +652,9 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd,
u_char *buf, int len)
info->buf_len = len;
- enable_irq(info->gpmc_irq_count);
- enable_irq(info->gpmc_irq_fifo);
+ /* Enable Interrupt generation */
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
/* waiting for read to complete */
wait_for_completion(&info->comp);
@@ -690,8 +703,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
info->buf_len = len;
- enable_irq(info->gpmc_irq_count);
- enable_irq(info->gpmc_irq_fifo);
+ /* Enable Interrupt generation */
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+ info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
/* waiting for write to complete */
wait_for_completion(&info->comp);
@@ -1770,35 +1784,18 @@ static int omap_nand_probe(struct platform_device *pdev)
break;
case NAND_OMAP_PREFETCH_IRQ:
- info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
- if (info->gpmc_irq_fifo <= 0) {
- dev_err(&pdev->dev, "error getting fifo irq\n");
- err = -ENODEV;
- goto return_error;
- }
- err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
- omap_nand_irq, IRQF_SHARED,
- "gpmc-nand-fifo", info);
- if (err) {
- dev_err(&pdev->dev, "requesting irq(%d) error:%d",
- info->gpmc_irq_fifo, err);
- info->gpmc_irq_fifo = 0
[PATCH v2 00/22] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms
Hi,
We do a couple of things in this series which result in
cleaner device tree implementation, faster perfomance and
multi-platform support. As an added bonus we get new GPI/Interrupt pins
for use in the system.
- Establish a custom interface between NAND and GPMC driver. This is
needed because all of the NAND registers sit in the GPMC register space.
Some bits like NAND IRQ are even shared with GPMC.
- Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ
with the omap2-nand driver and handle NAND IRQ events in the NAND driver.
This causes performance increase when using prefetch-irq mode.
30% increase in read, 17% increase in write in prefetch-irq mode.
- Clean up device tree support so that omap-gpmc IP and the omap2 NAND
driver can be used on non-OMAP platforms. e.g. Keystone.
- Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain
2 to 4 of these and most of them would be unused otherwise. It also
allows a cleaner implementation of NAND Ready pin status for the NAND driver.
- Implement GPIOlib based NAND ready pin checking for OMAP NAND driver.
NOTE: I've only adapted dra7.dtsi and dra7x-evms for this series.
I will adapt all other boards when the series is in a shape to be accepted.
cheers,
-roger
This is done in patches 1 to 14
Roger Quadros (22):
ARM: OMAP2+: gpmc: Add platform data
ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
memory: omap-gpmc: Introduce GPMC to NAND interface
mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers
memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status
mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty
check
memory: omap-gpmc: Remove NAND IRQ code
memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface
mtd: nand: omap2: manage NAND interrupts
mtd: nand: omap: Copy platform data parameters to omap_nand_info data
mtd: nand: omap: Clean up device tree support
mtd: nand: omap: Update DT binding documentation
memory: omap-gpmc: Prevent mapping into 1st 16MB
ARM: dts: OMAP2+: Fix NAND device nodes.
memory: omap-gpmc: Move device tree binding to correct location
memory: omap-gpmc: Support general purpose input for WAITPINs
memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring
memory: omap-gpmc: Add irqchip support to the gpiochip
ARM: dts: dra7: Enable gpio & interrupt controller for gpmc node
mtd: nand: omap2: Implement NAND ready using gpiolib
ARM: dts: dra7x-evm: Provide NAND ready pin
memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via
gpmc_regs
.../omap-gpmc.txt} | 0
.../devicetree/bindings/mtd/gpmc-nand.txt | 16 +-
arch/arm/boot/dts/dra7-evm.dts | 6 +-
arch/arm/boot/dts/dra7.dtsi| 4 +
arch/arm/boot/dts/dra72-evm.dts| 2 +
arch/arm/boot/dts/omap3-beagle.dts | 3 +-
arch/arm/mach-omap2/gpmc-nand.c| 11 +-
drivers/memory/omap-gpmc.c | 610 -
drivers/mtd/nand/omap2.c | 261 ++---
include/linux/omap-gpmc.h | 172 ++
include/linux/platform_data/gpmc-omap.h| 169 ++
include/linux/platform_data/mtd-nand-omap2.h | 12 +-
12 files changed, 782 insertions(+), 484 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.txt =>
memory-controllers/omap-gpmc.txt} (100%)
create mode 100644 include/linux/platform_data/gpmc-omap.h
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Re: [PATCH 6/7] phy: omap-usb2: Add a new compatible string for USB2 PHY2
On 05/08/15 17:18, Kishon Vijay Abraham I wrote:
> Hi Roger,
>
> On Wednesday 05 August 2015 01:55 PM, Roger Quadros wrote:
>> On 05/08/15 11:23, Roger Quadros wrote:
>>>
>>> On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
>>>> The USB2 PHY2 has a different register map compared to USB2 PHY1
>>>> to power on/off the PHY. In order to handle it, add a new
>>>> "compatible" string.
>>>>
>>>> Signed-off-by: Kishon Vijay Abraham I
>>>> ---
>>>> Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
>>>> drivers/phy/phy-omap-usb2.c |9 +
>>>> 2 files changed, 11 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>> index 49e5b0c..a061077 100644
>>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>> @@ -31,6 +31,8 @@ OMAP USB2 PHY
>>>>
>>>> Required properties:
>>>> - compatible: Should be "ti,omap-usb2"
>>>> + Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
>>>> + in DRA7x
>>>> - reg : Address and length of the register set for the device.
>>>> - #phy-cells: determine the number of cells that should be given in the
>>>> phandle while referencing this phy.
>>>> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
>>>> index b5c266a..2f7220f 100644
>>>> --- a/drivers/phy/phy-omap-usb2.c
>>>> +++ b/drivers/phy/phy-omap-usb2.c
>>>> @@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
>>>>.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
>>>> };
>>>>
>>>> +static const struct usb_phy_data dra7x_usb2_phy2_data = {
>>>> + .label = "dra7x_usb2_phy2",
>>>> + .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
>>>> +};
>>>> +
>>>> static const struct usb_phy_data am437x_usb2_data = {
>>>>.label = "am437x_usb2",
>>>>.flags = 0,
>>>> @@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[]
>>>> = {
>>>>.data = &dra7x_usb2_data,
>>>>},
>>>>{
>>>> + .compatible = "ti,dra7x-usb2-phy2",
>>>> + .data = &dra7x_usb2_phy2_data,
>>>
>>> Why is this needed? You can reuse dra7x_usb2_data as is.
>>
>> OK. I see why we need it in the next patch.
>> Probably both patches could be squashed.
>>
>> What does .label indicate?
>
> it's actually used only in usb_add_phy() (drivers/usb/phy/phy.c). I don't
> think
> it's actually important unless you strongly feel so.
I leave it to you then :).
cheers,
-roger
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Re: [PATCH 7/7] phy: omap-usb2: use *syscon* framework API to power on/off the PHY
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
> Deprecate using phy-omap-control driver to power on/off the PHY,
> and use *syscon* framework to do the same. This handles
> powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
> drivers/phy/phy-omap-usb2.c | 85
> +-
> include/linux/phy/omap_usb.h | 23 ++
> 3 files changed, 96 insertions(+), 18 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
> b/Documentation/devicetree/bindings/phy/ti-phy.txt
> index a061077..a3b3945 100644
> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
> @@ -42,10 +42,14 @@ Required properties:
> * "wkupclk" - wakeup clock.
> * "refclk" - reference clock (optional).
>
> -Optional properties:
> +Deprecated properties:
> - ctrl-module : phandle of the control module used by PHY driver to power on
> the PHY.
>
> +Recommended properies:
> +- syscon-phy-power : phandle/offset pair. Phandle to the system control
> + module and the register offset to power on/off the PHY.
> +
> This is usually a subnode of ocp2scp to which it is connected.
>
> usb2phy@4a0ad080 {
> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
> index 2f7220f..531fe04 100644
> --- a/drivers/phy/phy-omap-usb2.c
> +++ b/drivers/phy/phy-omap-usb2.c
> @@ -29,6 +29,8 @@
> #include
> #include
> #include
> +#include
> +#include
> #include
>
> #define USB2PHY_DISCON_BYP_LATCH (1 << 31)
> @@ -97,22 +99,40 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
> return 0;
> }
>
> -static int omap_usb_power_off(struct phy *x)
> +static int omap_usb_phy_power(struct omap_usb *phy, int on)
> {
> - struct omap_usb *phy = phy_get_drvdata(x);
> + u32 val = 0;
No need to initialize val.
> + int ret;
>
> - omap_control_phy_power(phy->control_dev, 0);
> + if (phy->syscon_phy_power) {
> + if (on)
> + val = phy->power_on;
> + else
> + val = phy->power_off;
> +
> + ret = regmap_update_bits(phy->syscon_phy_power, phy->power_reg,
> + phy->mask, val);
> + if (ret < 0)
> + return ret;
> + } else {
> + omap_control_phy_power(phy->control_dev, on);
> + }
>
> return 0;
> }
>
> -static int omap_usb_power_on(struct phy *x)
> +static int omap_usb_power_off(struct phy *x)
> {
> struct omap_usb *phy = phy_get_drvdata(x);
>
> - omap_control_phy_power(phy->control_dev, 1);
> + return omap_usb_phy_power(phy, false);
> +}
>
> - return 0;
> +static int omap_usb_power_on(struct phy *x)
> +{
> + struct omap_usb *phy = phy_get_drvdata(x);
> +
> + return omap_usb_phy_power(phy, true);
> }
>
> static int omap_usb_init(struct phy *x)
> @@ -147,26 +167,38 @@ static struct phy_ops ops = {
> static const struct usb_phy_data omap_usb2_data = {
> .label = "omap_usb2",
> .flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
> + .mask = OMAP_DEV_PHY_PD,
> + .power_off = OMAP_DEV_PHY_PD,
> };
>
> static const struct usb_phy_data omap5_usb2_data = {
> .label = "omap5_usb2",
> .flags = 0,
> + .mask = OMAP_DEV_PHY_PD,
> + .power_off = OMAP_DEV_PHY_PD,
> };
>
> static const struct usb_phy_data dra7x_usb2_data = {
> .label = "dra7x_usb2",
> .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
> + .mask = OMAP_DEV_PHY_PD,
> + .power_off = OMAP_DEV_PHY_PD,
> };
>
> static const struct usb_phy_data dra7x_usb2_phy2_data = {
> .label = "dra7x_usb2_phy2",
> .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
> + .mask = OMAP_USB2_PHY_PD,
> + .power_off = OMAP_USB2_PHY_PD,
> };
>
> static const struct usb_phy_data am437x_usb2_data = {
> .label = "am437x_usb2",
> .flags = 0,
> + .mask = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD |
> + AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
> + .power_on = AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
> + .power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD,
We're combining some OTG operations with PHY on/off. This is probably OK
for now but looks like we need a OTG phy driver for this?
> };
>
> static const struct of_device_id omap_usb2_id_table[] = {
> @@ -228,6 +260,9 @@ static int omap_usb2_probe(struct platform_device *pdev)
> phy->phy.label = phy_data->label;
> phy->phy.otg= otg;
> phy->phy.type = USB_PHY_TYPE_USB2;
> + phy->mask = phy_data->mask;
> + phy->power_on = phy_data->power_on;
> + phy->power_off = phy_data->power_off;
>
> if (phy_data->flags & OMAP_U
Re: [PATCH 6/7] phy: omap-usb2: Add a new compatible string for USB2 PHY2
On 05/08/15 11:23, Roger Quadros wrote:
>
> On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
>> The USB2 PHY2 has a different register map compared to USB2 PHY1
>> to power on/off the PHY. In order to handle it, add a new
>> "compatible" string.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
>> drivers/phy/phy-omap-usb2.c |9 +
>> 2 files changed, 11 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> index 49e5b0c..a061077 100644
>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> @@ -31,6 +31,8 @@ OMAP USB2 PHY
>>
>> Required properties:
>> - compatible: Should be "ti,omap-usb2"
>> + Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
>> + in DRA7x
>> - reg : Address and length of the register set for the device.
>> - #phy-cells: determine the number of cells that should be given in the
>> phandle while referencing this phy.
>> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
>> index b5c266a..2f7220f 100644
>> --- a/drivers/phy/phy-omap-usb2.c
>> +++ b/drivers/phy/phy-omap-usb2.c
>> @@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
>> .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
>> };
>>
>> +static const struct usb_phy_data dra7x_usb2_phy2_data = {
>> +.label = "dra7x_usb2_phy2",
>> +.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
>> +};
>> +
>> static const struct usb_phy_data am437x_usb2_data = {
>> .label = "am437x_usb2",
>> .flags = 0,
>> @@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[] =
>> {
>> .data = &dra7x_usb2_data,
>> },
>> {
>> +.compatible = "ti,dra7x-usb2-phy2",
>> +.data = &dra7x_usb2_phy2_data,
>
> Why is this needed? You can reuse dra7x_usb2_data as is.
OK. I see why we need it in the next patch.
Probably both patches could be squashed.
What does .label indicate?
IMO the .label of both usb2 phys should be the same.
i.e. "dra7x_usb2"
cheers,
-roger
>
>> +},
>> +{
>> .compatible = "ti,am437x-usb2",
>> .data = &am437x_usb2_data,
>> },
>>
>
> cheers,
> -roger
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Re: [PATCH 6/7] phy: omap-usb2: Add a new compatible string for USB2 PHY2
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
> The USB2 PHY2 has a different register map compared to USB2 PHY1
> to power on/off the PHY. In order to handle it, add a new
> "compatible" string.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
> drivers/phy/phy-omap-usb2.c |9 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
> b/Documentation/devicetree/bindings/phy/ti-phy.txt
> index 49e5b0c..a061077 100644
> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
> @@ -31,6 +31,8 @@ OMAP USB2 PHY
>
> Required properties:
> - compatible: Should be "ti,omap-usb2"
> +Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
> +in DRA7x
> - reg : Address and length of the register set for the device.
> - #phy-cells: determine the number of cells that should be given in the
> phandle while referencing this phy.
> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
> index b5c266a..2f7220f 100644
> --- a/drivers/phy/phy-omap-usb2.c
> +++ b/drivers/phy/phy-omap-usb2.c
> @@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
> .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
> };
>
> +static const struct usb_phy_data dra7x_usb2_phy2_data = {
> + .label = "dra7x_usb2_phy2",
> + .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
> +};
> +
> static const struct usb_phy_data am437x_usb2_data = {
> .label = "am437x_usb2",
> .flags = 0,
> @@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
> .data = &dra7x_usb2_data,
> },
> {
> + .compatible = "ti,dra7x-usb2-phy2",
> + .data = &dra7x_usb2_phy2_data,
Why is this needed? You can reuse dra7x_usb2_data as is.
> + },
> + {
> .compatible = "ti,am437x-usb2",
> .data = &am437x_usb2_data,
> },
>
cheers,
-roger
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Re: [PATCH 10/10] ARM: dts: omap4: Use "syscon-otghs" instead of "ctrl-module" in USB node
On 05/08/15 11:02, Roger Quadros wrote:
> Kishon,
>
> On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
>> Add "syscon-otghs" property and remove the deprecated "ctrl-module"
>> property from MUSB devicetree node.
>>
>> Since "omap_control_usbotg" devicetree node is no longer used, remove
>> it.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/boot/dts/omap4.dtsi |8 +---
>> 1 file changed, 1 insertion(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index b27634d..2fb49a5 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -854,12 +854,6 @@
>> };
>> };
>>
>> -omap_control_usbotg: control-phy@4a00233c {
>> -compatible = "ti,control-phy-otghs";
>> -reg = <0x4a00233c 0x4>;
>> -reg-names = "otghs_control";
>> -};
>> -
>> usb_otg_hs: usb_otg_hs@4a0ab000 {
>> compatible = "ti,omap4-musb";
>> reg = <0x4a0ab000 0x7ff>;
>> @@ -872,7 +866,7 @@
>> multipoint = <1>;
>> num-eps = <16>;
>> ram-bits = <12>;
>> -ctrl-module = <&omap_control_usbotg>;
>> +syscon-otghs = <&scm_conf 0x33c>;
>
> All other properties were of the format "syscon-phy-foo".
> Why use a different format here?
>
Ah, looks like we don't have a dedicated phy driver for this?
We will need to add a PHY driver I guess then and handle this register
in that driver rather than in the musb driver.
cheers,
-roger
>
>
>> };
>>
>> aes: aes@4b501000 {
>>
> --
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Re: [PATCH 10/10] ARM: dts: omap4: Use "syscon-otghs" instead of "ctrl-module" in USB node
Kishon,
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
> Add "syscon-otghs" property and remove the deprecated "ctrl-module"
> property from MUSB devicetree node.
>
> Since "omap_control_usbotg" devicetree node is no longer used, remove
> it.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> arch/arm/boot/dts/omap4.dtsi |8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index b27634d..2fb49a5 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -854,12 +854,6 @@
> };
> };
>
> - omap_control_usbotg: control-phy@4a00233c {
> - compatible = "ti,control-phy-otghs";
> - reg = <0x4a00233c 0x4>;
> - reg-names = "otghs_control";
> - };
> -
> usb_otg_hs: usb_otg_hs@4a0ab000 {
> compatible = "ti,omap4-musb";
> reg = <0x4a0ab000 0x7ff>;
> @@ -872,7 +866,7 @@
> multipoint = <1>;
> num-eps = <16>;
> ram-bits = <12>;
> - ctrl-module = <&omap_control_usbotg>;
> + syscon-otghs = <&scm_conf 0x33c>;
All other properties were of the format "syscon-phy-foo".
Why use a different format here?
Other than that
Acked-by: Roger Quadros
cheers,
-roger
> };
>
> aes: aes@4b501000 {
>
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Re: [PATCH 09/10] ARM: dts: omap4: Use "syscon-phy-power" instead of "ctrl-module" in USB PHY node
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
> Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
> property from USB PHY dt node.
>
> Since "omap_control_usb2phy" devicetree node is no longer used,
> remove it.
>
> Signed-off-by: Kishon Vijay Abraham I
Acked-by: Roger Quadros
cheers,
-roger
> ---
> arch/arm/boot/dts/omap4.dtsi |8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 7d31c6f..b27634d 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -703,7 +703,7 @@
> usb2_phy: usb2phy@4a0ad080 {
> compatible = "ti,omap-usb2";
> reg = <0x4a0ad080 0x58>;
> - ctrl-module = <&omap_control_usb2phy>;
> + syscon-phy-power = <&scm_conf 0x300>;
> clocks = <&usb_phy_cm_clk32k>;
> clock-names = "wkupclk";
> #phy-cells = <0>;
> @@ -854,12 +854,6 @@
> };
> };
>
> - omap_control_usb2phy: control-phy@4a002300 {
> - compatible = "ti,control-phy-usb2";
> - reg = <0x4a002300 0x4>;
> - reg-names = "power";
> - };
> -
> omap_control_usbotg: control-phy@4a00233c {
> compatible = "ti,control-phy-otghs";
> reg = <0x4a00233c 0x4>;
>
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Re: [PATCH 08/10] ARM: dts: OMAP5: Use "syscon-phy-power" instead of "ctrl-module" in SATA PHY node
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
> Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
> property from SATA PHY node.
>
> Since "omap_control_sata" devicetree node is no longer used, remove it.
>
> Signed-off-by: Kishon Vijay Abraham I
Acked-by: Roger Quadros
cheers,
-roger
> ---
> arch/arm/boot/dts/omap5.dtsi | 10 +-
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index f0b6cd6..c3ca5b7 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -946,14 +946,6 @@
> #thermal-sensor-cells = <1>;
> };
>
> - omap_control_sata: control-phy@4a002374 {
> - compatible = "ti,control-phy-pipe3";
> - reg = <0x4a002374 0x4>;
> - reg-names = "power";
> - clocks = <&sys_clkin>;
> - clock-names = "sysclk";
> - };
> -
> /* OCP2SCP3 */
> ocp2scp@4a09 {
> compatible = "ti,omap-ocp2scp";
> @@ -968,7 +960,7 @@
> <0x4A096400 0x64>, /* phy_tx */
> <0x4A096800 0x40>; /* pll_ctrl */
> reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> - ctrl-module = <&omap_control_sata>;
> + syscon-phy-power = <&scm_conf 0x374>;
> clocks = <&sys_clkin>, <&sata_ref_clk>;
> clock-names = "sysclk", "refclk";
> #phy-cells = <0>;
>
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