Re: [PATCH 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

On 2015/10/19 18:54, Ulf Hansson wrote:

[...]



[...]






2) Considering the runtime PM case for the sdhci device. Typically you
can gate clocks etc at runtime suspend to save power, but what about
the phy? Can you power off it in runtime suspend?



yes, we can power off it in runtime suspend. So we can append some patches
later to introduce runtime pm for sdhci-of-arasan?


Yes, that's fine. I would thus expect that you want to do phy power
off/on from the runtime PM callbacks, right!?

If that's the case I think $subject patch should deal with *both* phy
init and phy power on during ->probe().



yes. I will do phy power_off/on from runtime pm for the next version of 
$subject patchset.


Thanks.


Kind regards
Uffe
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Re: [PATCH 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

On 2015/10/19 15:50, Ulf Hansson wrote:

[...]


I understand the phy is optional, but you still need to handle the
EPROBE_DEFER case.

Perhaps you should also use devm_phy_optional_get() instead!?



I already changed it in version-2 [1]. :)
phy is mandatory for sdhci-arasan,5.1.

[1]: https://patchwork.kernel.org/patch/7173251/


Oh, apologize for reviewing the old version!






+   ret = phy_power_on(sdhci_arasan->phy);



This looks a bit weird. Shouldn't you do phy_init() prior phy_power_on()?

Similar comment applies to phy_exit() and phy_power_off().



Both are okay. It depends how the phy-driver implement the four interfaces.
 From my case, power_on for arasan's phy driver firstly enable phy's clk and
open power-domain, then programme phy internal registers to activate phy.
Without enabling phy's clk and power-domain, we cannot do phy_init since phy
can't be accessed by CPU.

But here, I think you are right. It does look a bit weird.
I think the better way is to remove phy_power_on here, and let phy-driver do
power_on in phy_init internally. Similarly in the remove call.


That makes sense to me! I think it would also follow other phy clients
use of the phy API.

What makes me wonder though is from a power management point of view.
*When* do you need to have phy initialized and powered?



Whenever controller need to communicate with card, must init/power_on 
phy firstly.



1) For a removable card can leave the phy uninitialised or powered
off, but still detect card insertion/removal via GPIO? Is that a valid
scenario for you?



Theoretically, it is.  Although my soc don't use phy for removable card, 
I also consider how to handle this case. Should we add a hook
for sdhci_get_cd, and initialize phy if it's non-removeable device or 
removeable card in slot ? Doesn't seem like a good idea.


Also seems not always work if we just use SDHCI_PRESENT_STATE to detect 
card insertion/removal without phy in active state.



2) Considering the runtime PM case for the sdhci device. Typically you
can gate clocks etc at runtime suspend to save power, but what about
the phy? Can you power off it in runtime suspend?


yes, we can power off it in runtime suspend. So we can append some 
patches later to introduce runtime pm for sdhci-of-arasan?




[...]

Kind regards
Uffe






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Shawn Lin

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Re: [PATCH 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

On 2015/10/16 20:35, Ulf Hansson wrote:

On 11 September 2015 at 10:54, Shawn Lin  wrote:

This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.

Signed-off-by: Shawn Lin 
---

  drivers/mmc/host/sdhci-of-arasan.c | 90 ++
  1 file changed, 90 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index 621c3f4..fdd71c7 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -21,6 +21,7 @@

  #include 
  #include 
+#include 
  #include "sdhci-pltfm.h"

  #define SDHCI_ARASAN_CLK_CTRL_OFFSET   0x2c
@@ -35,6 +36,7 @@
   */
  struct sdhci_arasan_data {
 struct clk  *clk_ahb;
+   struct phy  *phy;
  };

  static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
@@ -67,6 +69,62 @@ static struct sdhci_pltfm_data sdhci_arasan_pdata = {

  #ifdef CONFIG_PM_SLEEP
  /**
+  * sdhci_arasan_suspend_phy - Suspend phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a deactive state.
+  */
+static int sdhci_arasan_suspend_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_exit(phy);
+   if (ret < 0)
+   goto err_phy_exit;


This odd to me. First you do phy_exit() then phy_power_off(). It seems
like it should be in the opposite order.



yep, there is no need to use phy_exit/init for suspend/resume.
I will do it.


Moreover I wonder why phy_exit() is needed, I expected that to be
called at ->remove() only!?


+
+   ret = phy_power_off(phy);
+   if (ret < 0)
+   goto err_phy_pwr_off;
+
+   return 0;
+
+err_phy_pwr_off:
+   phy_power_on(phy);
+err_phy_exit:
+   phy_init(phy);
+   return ret;
+}
+
+/**
+  * sdhci_arasan_resume_phy - Resume phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a active state.
+  */
+static int sdhci_arasan_resume_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_power_on(phy);
+   if (ret < 0)
+   goto err_phy_pwr_on;
+
+   ret = phy_init(phy);
+   if (ret < 0)
+   goto err_phy_init;
+


Similar comment as above.


+   return 0;
+
+err_phy_init:
+   phy_exit(phy);
+err_phy_pwr_on:
+   phy_power_off(phy);
+   return ret;
+}
+
+/**
   * sdhci_arasan_suspend - Suspend method for the driver
   * @dev:   Address of the device structure
   * Returns 0 on success and error value on error
@@ -88,6 +146,12 @@ static int sdhci_arasan_suspend(struct device *dev)
 clk_disable(pltfm_host->clk);
 clk_disable(sdhci_arasan->clk_ahb);

+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_suspend_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }


This means you will suspend the phy after you have disabled the
clocks. Of course I can't tell whether that okay, but it doesn't
follow the same sequence as in ->probe(). To me that indicates that
either probe or suspend/resume could be broken.



phy has a seperate clk for itself, and it's controlled by phy driver. 
So, there is no any relationship between controller's clk and phy's clk. 
We disable or enable phy's clk internally in 
phy_int/exit/power_off/power_on.


Of course if it makes odd to you, I would put suspend_phy before 
clk_disable.  :)



+
 return 0;
  }

@@ -119,6 +183,12 @@ static int sdhci_arasan_resume(struct device *dev)
 return ret;
 }

+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_resume_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }
+
 return sdhci_resume_host(host);
  }
  #endif /* ! CONFIG_PM_SLEEP */
@@ -163,6 +233,26 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 goto clk_dis_ahb;
 }

+   sdhci_arasan->phy = devm_phy_get(&pdev->dev, "phy_arasan");
+   if (!IS_ERR(sdhci_arasan->phy)) {


I understand the phy is optional, but you still need to handle the
EPROBE_DEFER case.

Perhaps you should also use devm_phy_optional_get() instead!?


I already changed it in version-2 [1]. :)
phy is mandatory for sdhci-arasan,5.1.

[1]: https://patchwork.kernel.org/patch/7173251/




+   ret = phy_power_on(sdhci_arasan->phy);


This looks a bit weird. Shouldn't you do phy_init() prior phy_power_on()?

Similar comment applies to phy_exit() and phy_power_off().


Both are okay. It depends how the phy-driver implement the four 
interfaces. From my case, power_on for arasan's phy driver firstly 
enab

Re: [RFC PATCH v8 0/10] Add external dma support for Synopsys MSHC

[Shawn Lin]

On 2015/10/5 9:36, Jaehoon Chung wrote:

Hi, Shawn.

On 10/02/2015 06:49 PM, Shawn Lin wrote:

On 2015/10/1 17:14, Jaehoon Chung wrote:

Dear, All.

I will apply patch 01-03 at my repository on today.
But i don't know better how i do about other patches relevant to config file.



Thanks, Jaehoon. :)

I guess it would be acceptable to pick the config changes, already they were 
acked by the soc maintainers, via dw_mmc tree when ulf merge dw_mmc tree into 
his mmc-tree.


Some patches didn't get the maintainer's acked-by.
I will wait for that..until this week. How about?



No problem, take your time. ：）


Best Regards,
Jaehoon Chung





Best Regards,
Jaehoon Chung

On 09/16/2015 03:40 PM, Shawn Lin wrote:

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc

Test emmc throughput on my platform with edmac support and without edmac 
support(pio only)
iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile -Rb 
out.xls > /mnt/result.txt
(light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
in total)
   ___
|   external dma mode   |
|---|
|blksz | Random Read | Random Write | Seq Read   | Seq Write|
|---|
|4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
|---|
|64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
|---|
|128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
|---|
 VS
   ___
|  pio mode |
|---|
|blksz | Random Read  | Random Write | Seq Read  | Seq Write|
|---|
|4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
|---|
|64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
|---|
|128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
|---|


Changes in v8:
- remove trans_mode variable
- remove unnecessary dma_ops check
- remove unnecessary comment
- fix coding style based on latest ulf's next
- add Acked-by: Jaehoon Chung 
for HCON's changes

Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
"Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
transfer mode.
- remove all bt-bindings' c

Re: [RFC PATCH v8 0/10] Add external dma support for Synopsys MSHC

[Shawn Lin]

On 2015/10/1 17:14, Jaehoon Chung wrote:

Dear, All.

I will apply patch 01-03 at my repository on today.
But i don't know better how i do about other patches relevant to config file.



Thanks, Jaehoon. :)

I guess it would be acceptable to pick the config changes, already they 
were acked by the soc maintainers, via dw_mmc tree when ulf merge dw_mmc 
tree into his mmc-tree.




Best Regards,
Jaehoon Chung

On 09/16/2015 03:40 PM, Shawn Lin wrote:

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
   at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc

Test emmc throughput on my platform with edmac support and without edmac 
support(pio only)
iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile -Rb 
out.xls > /mnt/result.txt
(light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
in total)
  ___
|   external dma mode   |
|---|
|blksz | Random Read | Random Write | Seq Read   | Seq Write|
|---|
|4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
|---|
|64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
|---|
|128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
|---|
VS
  ___
|  pio mode |
|---|
|blksz | Random Read  | Random Write | Seq Read  | Seq Write|
|---|
|4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
|---|
|64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
|---|
|128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
|---|


Changes in v8:
- remove trans_mode variable
- remove unnecessary dma_ops check
- remove unnecessary comment
- fix coding style based on latest ulf's next
- add Acked-by: Jaehoon Chung 
   for HCON's changes

Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
   suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
   "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
   transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
-

Re: [RFC PATCH v3 1/3] mmc: sprd: Add MMC host driver for Spreadtrum SoC

[Shawn Lin]

On 2015/9/28 15:18, Hongtao Wu wrote:

 >>

On Thu, Sep 10, 2015 at 9:28 PM, Ulf Hansson mailto:ulf.hans...@linaro.org>> wrote:
 >
 > On 14 August 2015 at 18:55, Hongtao Wu mailto:wuh...@gmail.com>> wrote:


[...]



Yes, most of this data can be removed, such as caps, caps2, base_clk.
However ocr_avail and signal_default_voltage are useful for us.
We can't fetch ocr_avail from external regulator via
mmc_regulator_get_supply,
because our regulator driver can't supply mmc_regulator_get_ocrmask()
interface for MMC driver.


Sorry for the noise but... IMO, your need to quirk your regulator driver 
stuffs rather than mmc.



And sometimes our external regulator can not supply 3.0v or 1.8v default
signal voltage that we expect. So this 3.0v or 1.8v default signal
voltage are
mandatory.





--
Best Regards
Shawn Lin

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Re: [PATCH v2 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

On 2015/9/17 19:44, Ulf Hansson wrote:

On 14 September 2015 at 08:29, Shawn Lin  wrote:

This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.
Currently, it's just mandatory for arasan,sdhci-5.1.


I am trying to understand how a PHY can be used together with a
MMC/SD/SDIO controller. Normally the card connector doesn't hold any
intelligence, so I wonder if PHY is correctly used here.

Could you try to explain, HW-wise, what role the PHY has for you?



Thanks for comment, Ulf.

It's the first time we introduce phy into mmc subsystem,also it's my 
first time to use phy for emmc in real Soc.

so definitely we need to discuss it deliberately.

From my view, phy is an active-power, differential sampling and more
well-designed analog *IO component* for ultra-highspeed device to 
guarantee its signal integrity, like USB, UFS, DDR-RAM,MIPI and so on.


(1)Firstly it contains DLL to generate delayline and phase for sampling 
data from mmc devices. When sdhci controller executes tuning and sends 
out tuning sequence, and PHY can auto change its delayline and phase
in order to test if this "sample timing" is okay. If not, CRC err is 
generate back to the controller. Then after SDHCI tune timing for 40 
times, also PHY have scanned all the "sample windows" by trying 
different delayline and phase combination, and finally auto-select the 
best sample timing for the "sample windows". And sdhci HOST CONTROL

2 Register[6:7] is controlled by PHY in my case.

(2)Then phy can programming source/sink impedance to avoid signal 
reflex. Given that JEDEC has come to HS533(highspeed 533MHz), this 
function is imperative to be implemented just like the role of ODT for 
DDR-RAM's PHY.


(3)Phy is integrated with diff pull-up/down resistance value and 
open-drain type for HW design.


(4)Phy can also have some enable-bit to decide whether all mmc 
signal(clk/data/cmd/strobe) can output to the devices or not.



For the card, even for host controller itself, phy can just be regarded 
as a need-to-do-something-before-used GPIO.
So, before we start initializing card, we need to power up PHY, enable 
clk for it and configure all the stuffs. Also we need to power down it 
for power-saving when into suspend. That's all we need to do and that's 
all the generic phy framework had provided by four interface: 
phy_init/phy_exit/phy_power_on/phy_power_off.



Sincerely welcome any comments here to make things better. :)



Kind regards
Uffe



Signed-off-by: Shawn Lin 

Serise-changes: 2
- Keep phy as a mandatory requirement for arasan,sdhci-5.1

---

Changes in v2: None

  drivers/mmc/host/sdhci-of-arasan.c | 97 ++
  1 file changed, 97 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index 75379cb..2c13ef8 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -21,6 +21,7 @@

  #include 
  #include 
+#include 
  #include "sdhci-pltfm.h"

  #define SDHCI_ARASAN_CLK_CTRL_OFFSET   0x2c
@@ -35,6 +36,7 @@
   */
  struct sdhci_arasan_data {
 struct clk  *clk_ahb;
+   struct phy  *phy;
  };

  static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
@@ -70,6 +72,62 @@ static struct sdhci_pltfm_data sdhci_arasan_pdata = {

  #ifdef CONFIG_PM_SLEEP
  /**
+  * sdhci_arasan_suspend_phy - Suspend phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a deactive state.
+  */
+static int sdhci_arasan_suspend_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_exit(phy);
+   if (ret < 0)
+   goto err_phy_exit;
+
+   ret = phy_power_off(phy);
+   if (ret < 0)
+   goto err_phy_pwr_off;
+
+   return 0;
+
+err_phy_pwr_off:
+   phy_power_on(phy);
+err_phy_exit:
+   phy_init(phy);
+   return ret;
+}
+
+/**
+  * sdhci_arasan_resume_phy - Resume phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a active state.
+  */
+static int sdhci_arasan_resume_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_power_on(phy);
+   if (ret < 0)
+   goto err_phy_pwr_on;
+
+   ret = phy_init(phy);
+   if (ret < 0)
+   goto err_phy_init;
+
+   return 0;
+
+err_phy_init:
+   phy_exit(phy);
+err_phy_pwr_on:
+   phy_power_off(phy);
+   return ret;
+}
+
+/**
   * sdhci_arasan_suspend - Suspend method for the driver
   * @dev:   Address of the device structure
   * Returns 0 on success and error value on error
@@ -91,6 +149,12 @@ static int sdhci_arasan_suspend(struct device *dev)

[RFC PATCH v8 05/10] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Vineet Gupta 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig | 1 -
 arch/arc/configs/axs103_defconfig | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig 
b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig 
b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig 
b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
-- 
2.3.7


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[RFC PATCH v8 01/10] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK31xx
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v8:
- remove trans_mode variable
- remove unnecessary dma_ops check
- remove unnecessary comment
- fix coding style based on latest ulf's next
- add Acked-by: Jaehoon Chung 
  for HCON's changes

Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig|  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c   | 268 
 drivers/mmc/host/dw_mmc.h   |   6 +
 include/linux/mmc/dw_mmc.h  |  23 +++-
 5 files changed, 246 insertions(+), 64 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8a1e349..515527e 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -615,15 +615,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA mode.
 
 config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -652,7 +644,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..5d7a8729 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,6 @@
 #define DW_MCI_FREQ_MAX2   /* unit: HZ */
 #define DW_MCI_FREQ_MIN40  /* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
 #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -102,7 +101,6 @@ struct idmac_desc {
 
 /* 

[RFC PATCH v8 04/10] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Govindraj Raja 
Acked-by: Ralf Baechle 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig 
b/arch/mips/configs/pistachio_defconfig
index 642b509..8b74291 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7


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[RFC PATCH v8 09/10] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 03deb7f..ad929ea 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -539,7 +539,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
-- 
2.3.7


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[RFC PATCH v8 08/10] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Joachim Eastwood 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/lpc18xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/lpc18xx_defconfig 
b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
-- 
2.3.7


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[RFC PATCH v8 10/10] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/zx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7


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[RFC PATCH v8 06/10] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Krzysztof Kozlowski 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/exynos_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 1ff2bfa..13ba48c 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -166,7 +166,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
-- 
2.3.7


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[RFC PATCH v8 07/10] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Wei Xu 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/hisi_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
2.3.7


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[RFC PATCH v8 03/10] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.

Signed-off-by: Shawn Lin 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 25 ++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+  Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
 
+[board specific internal DMA resources]
+
+   dwmmc0@1220 {
+   clock-frequency = <4>;
+   clock-freq-min-max = <40 2>;
+   num-slots = <1>;
+   broken-cd;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   vmmc-supply = <&buck8>;
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+   dmas = <&pdma 12>;
+   dma-names = "rx-tx";
};
-- 
2.3.7


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[RFC PATCH v8 02/10] mmc: dw_mmc: use macro for HCON register operations

[Shawn Lin]

This patch add some macros for HCON register operations
to make code more readable.

Signed-off-by: Shawn Lin 
Acked-by: Jaehoon Chung 
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/mmc/host/dw_mmc.c | 6 +++---
 drivers/mmc/host/dw_mmc.h | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 5d7a8729..100f56e 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2674,7 +2674,7 @@ static void dw_mci_init_dma(struct dw_mci *host)
* Check ADDR_CONFIG bit in HCON to find
* IDMAC address bus width
*/
-   addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
+   addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
 
if (addr_config == 1) {
/* host supports IDMAC in 64-bit address mode */
@@ -3051,7 +3051,7 @@ int dw_mci_probe(struct dw_mci *host)
 * Get the host data width - this assumes that HCON has been set with
 * the correct values.
 */
-   i = (mci_readl(host, HCON) >> 7) & 0x7;
+   i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
if (!i) {
host->push_data = dw_mci_push_data16;
host->pull_data = dw_mci_pull_data16;
@@ -3133,7 +3133,7 @@ int dw_mci_probe(struct dw_mci *host)
if (host->pdata->num_slots)
host->num_slots = host->pdata->num_slots;
else
-   host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
+   host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
 
/*
 * Enable interrupts for command done, data over, data empty,
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 811d467..f2a88d4 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -154,6 +154,9 @@
 #define DMA_INTERFACE_GDMA (0x2)
 #define DMA_INTERFACE_NODMA(0x3)
 #define SDMMC_GET_TRANS_MODE(x)(((x)>>16) & 0x3)
+#define SDMMC_GET_SLOT_NUM(x)  x)>>1) & 0x1F) + 1)
+#define SDMMC_GET_HDATA_WIDTH(x)   (((x)>>7) & 0x7)
+#define SDMMC_GET_ADDR_CONFIG(x)   (((x)>>27) & 0x1)
 /* Internal DMAC interrupt defines */
 #define SDMMC_IDMAC_INT_AI BIT(9)
 #define SDMMC_IDMAC_INT_NI BIT(8)
-- 
2.3.7


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[RFC PATCH v8 0/10] Add external dma support for Synopsys MSHC

[Shawn Lin]

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc

Test emmc throughput on my platform with edmac support and without edmac 
support(pio only)
iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile -Rb 
out.xls > /mnt/result.txt
(light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
in total)
 ___
|   external dma mode   |
|---|
|blksz | Random Read | Random Write | Seq Read   | Seq Write|
|---|
|4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
|---|
|64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
|---|
|128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
|---|
   VS
 ___
|  pio mode |
|---|
|blksz | Random Read  | Random Write | Seq Read  | Seq Write|
|---|
|4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
|---|
|64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
|---|
|128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
|---|


Changes in v8:
- remove trans_mode variable
- remove unnecessary dma_ops check
- remove unnecessary comment
- fix coding style based on latest ulf's next
- add Acked-by: Jaehoon Chung 
  for HCON's changes

Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (10):
  mmc: dw_mmc: Add external dma interface support
  mmc: dw_mmc: use macro for HCON register operations
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig:

Re: [RFC PATCH v7 01/10] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

 *host, u32 reset)
@@ -2650,10 +2821,9 @@ static bool dw_mci_reset(struct dw_mci *host)
}
}

-#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
-   /* It is also recommended that we reset and reprogram idmac */
-   dw_mci_idmac_reset(host);
-#endif
+   if (host->use_dma == TRANS_MODE_IDMAC)
+   /* It is also recommended that we reset and reprogram idmac */
+   dw_mci_idmac_reset(host);

ret = true;

@@ -3067,6 +3237,9 @@ EXPORT_SYMBOL(dw_mci_remove);
   */
  int dw_mci_suspend(struct dw_mci *host)
  {
+   if (host->use_dma && host->dma_ops->exit)
+   host->dma_ops->exit(host);
+
return 0;
  }
  EXPORT_SYMBOL(dw_mci_suspend);
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 8ce4674..811d467 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -148,6 +148,12 @@
  #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
 ((r) & 0xFFF) << 16 | \
 ((t) & 0xFFF))
+/* HCON register defines */
+#define DMA_INTERFACE_IDMA (0x0)
+#define DMA_INTERFACE_DWDMA(0x1)
+#define DMA_INTERFACE_GDMA (0x2)
+#define DMA_INTERFACE_NODMA(0x3)
+#define SDMMC_GET_TRANS_MODE(x)(((x)>>16) & 0x3)
  /* Internal DMAC interrupt defines */
  #define SDMMC_IDMAC_INT_AIBIT(9)
  #define SDMMC_IDMAC_INT_NIBIT(8)
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 134c574..f67b2ec 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -16,6 +16,7 @@

  #include 
  #include 
+#include 

  #define MAX_MCI_SLOTS 2

@@ -40,6 +41,17 @@ enum {

  struct mmc_data;

+enum {
+   TRANS_MODE_PIO = 0,
+   TRANS_MODE_IDMAC,
+   TRANS_MODE_EDMAC
+};
+
+struct dw_mci_dma_slave {
+   struct dma_chan *ch;
+   enum dma_transfer_direction direction;
+};
+
  /**
   * struct dw_mci - MMC controller state shared between all slots
   * @lock: Spinlock protecting the queue and associated data.
@@ -154,7 +166,14 @@ struct dw_mci {
dma_addr_t  sg_dma;
void*sg_cpu;
const struct dw_mci_dma_ops *dma_ops;
+   /* For idmac */
unsigned intring_size;
+
+   /* For edmac */
+   struct dw_mci_dma_slave *dms;
+   /* Registers's physical base address */
+   void*phy_regs;
+
u32 cmd_status;
u32 data_status;
u32 stop_cmdr;
@@ -208,8 +227,8 @@ struct dw_mci {
  struct dw_mci_dma_ops {
/* DMA Ops */
int (*init)(struct dw_mci *host);
-   void (*start)(struct dw_mci *host, unsigned int sg_len);
-   void (*complete)(struct dw_mci *host);
+   int (*start)(struct dw_mci *host, unsigned int sg_len);
+   void (*complete)(void *host);
void (*stop)(struct dw_mci *host);
void (*cleanup)(struct dw_mci *host);
void (*exit)(struct dw_mci *host);









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Re: [PATCH v2 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

On 2015/9/14 23:07, Sören Brinkmann wrote:

Hi Shawn,

overall, it looks good to me. I have some questions though.

On Mon, 2015-09-14 at 02:29PM +0800, Shawn Lin wrote:


[...]


+err_phy_exit:
+   phy_init(phy);


Just to confirm, are these actions in the error path correct? E.g.
if the power_off() call fails, is it safe to call power_on()? Isn't
the phy still powered on? (this would apply to other error paths too)



Cool question!

While writing this, I had read generic phy stuffs deliberately to find a 
solution for a case: how to deal with ping-pong fails? In another word, 
if power_off call fails, then we should call power_on, but unfortunately 
it fails again then we call power_off... so endless nested err 
handling... No answer yet.


So, I assumed two cases happened when power_off call fails:
(1) *real power_off* is done, but some other stuffs in the calling path 
fail, so phy is really power_off in theory. We need to power_on it 
again, but if it fail, we don't know PHY is on or off since we don't 
know power_on fails for what? *real power on* ? some other stuffs?


(2) *real power_off* isn't completed, so indeed it's *still* in power_on 
state. The reason we never need to check the return value of power_on 
cross the err handling is that whether power_on call successfully or 
not, it's always make phy in power_on state.


Now, let's think about case(1).
After reading dozens of sample codes(such as USB, UFS, MBUS) that adopt 
generic phy framework for PHY management, real thing should be like 
that: they NEVER deal with case(1).


It's a trick of sub-phy drivers themself. power_on/off calling path 
return err for two case:

<1>  phy_runtime callback fails. It's after *real power on/off*, so
definitely *real power on/off* is conpleted. That is the case(2) I 
mentioned above.

<2>  sub-phy drivers return err for  phy->ops->power_off(phy); Look
into all the sub-phy drivers twice, we find that they always return 
success for phy->ops->power_off hook. Why? Because all of them
write registers to enable/disable something, always consider things 
going well. Actually if we write value into a register, we have to think 
that it's functional.


Anyway, back to this patch.
Indeed we also write value into arasan phy's register to do 
phy_power_on/off/init/exit to make things work. Right, we return success 
state for all of these them just as all the other sub-phy drivers do.


Feel free to let me know if I make mistakes or misunderstanding above.


+   return ret;
+}


[...]


+   }
+   }


I assume you looked at options for having the error paths in a
consolidated location? I guess this may be the nicest solution since all
of this is in this conditional block?



yep, otherwise we should add some *if* statements to check 
sdhci_arasan->phy cross the err handles. And I intent to strictly limit

the phy stuffs under the scope of arasan,sdhci-5.1 currently.


Feel free to add my
Acked-by: Sören Brinkmann 



Thanks, Sören. :)


Sören






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[PATCH v2 2/2] Documentation: bindings: add description of phy for sdhci-of-arasan

[Shawn Lin]

This patch adds phys and phy-names for sdhci-of-arasan as required
properties for arasan,sdhci-5.1, and details the example as well.

Signed-off-by: Shawn Lin 

---

Changes in v2:
- Keep phy as a mandatory requirement for arasan,sdhci-5.1

 .../devicetree/bindings/mmc/arasan,sdhci.txt | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index da541c3..31b35c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -1,11 +1,12 @@
 Device Tree Bindings for the Arasan SDHCI Controller
 
-  The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. Only
-  deviations are documented here.
+  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+  Only deviations are documented here.
 
   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
@@ -17,6 +18,10 @@ Required Properties:
   - interrupt-parent: Phandle for the interrupt controller that services
  interrupts for this device.
 
+Required Properties for "arasan,sdhci-5.1":
+  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
+  - phy-names:  MUST be "phy_arasan".
+
 Example:
sdhci@e010 {
compatible = "arasan,sdhci-8.9a";
@@ -26,3 +31,14 @@ Example:
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
} ;
+
+   sdhci@e280 {
+   compatible = "arasan,sdhci-5.1";
+   reg = <0xe280 0x1000>;
+   clock-names = "clk_xin", "clk_ahb";
+   clocks = <&cru 8>, <&cru 18>;
+   interrupt-parent = <&gic>;
+   interrupts = <0 24 4>;
+   phys = <&emmc_phy>;
+   phy-names = "phy_arasan";
+   } ;
-- 
2.3.7


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[PATCH v2 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.
Currently, it's just mandatory for arasan,sdhci-5.1.

Signed-off-by: Shawn Lin 

Serise-changes: 2
- Keep phy as a mandatory requirement for arasan,sdhci-5.1

---

Changes in v2: None

 drivers/mmc/host/sdhci-of-arasan.c | 97 ++
 1 file changed, 97 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index 75379cb..2c13ef8 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -21,6 +21,7 @@
 
 #include 
 #include 
+#include 
 #include "sdhci-pltfm.h"
 
 #define SDHCI_ARASAN_CLK_CTRL_OFFSET   0x2c
@@ -35,6 +36,7 @@
  */
 struct sdhci_arasan_data {
struct clk  *clk_ahb;
+   struct phy  *phy;
 };
 
 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
@@ -70,6 +72,62 @@ static struct sdhci_pltfm_data sdhci_arasan_pdata = {
 
 #ifdef CONFIG_PM_SLEEP
 /**
+  * sdhci_arasan_suspend_phy - Suspend phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a deactive state.
+  */
+static int sdhci_arasan_suspend_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_exit(phy);
+   if (ret < 0)
+   goto err_phy_exit;
+
+   ret = phy_power_off(phy);
+   if (ret < 0)
+   goto err_phy_pwr_off;
+
+   return 0;
+
+err_phy_pwr_off:
+   phy_power_on(phy);
+err_phy_exit:
+   phy_init(phy);
+   return ret;
+}
+
+/**
+  * sdhci_arasan_resume_phy - Resume phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a active state.
+  */
+static int sdhci_arasan_resume_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_power_on(phy);
+   if (ret < 0)
+   goto err_phy_pwr_on;
+
+   ret = phy_init(phy);
+   if (ret < 0)
+   goto err_phy_init;
+
+   return 0;
+
+err_phy_init:
+   phy_exit(phy);
+err_phy_pwr_on:
+   phy_power_off(phy);
+   return ret;
+}
+
+/**
  * sdhci_arasan_suspend - Suspend method for the driver
  * @dev:   Address of the device structure
  * Returns 0 on success and error value on error
@@ -91,6 +149,12 @@ static int sdhci_arasan_suspend(struct device *dev)
clk_disable(pltfm_host->clk);
clk_disable(sdhci_arasan->clk_ahb);
 
+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_suspend_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }
+
return 0;
 }
 
@@ -122,6 +186,12 @@ static int sdhci_arasan_resume(struct device *dev)
return ret;
}
 
+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_resume_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }
+
return sdhci_resume_host(host);
 }
 #endif /* ! CONFIG_PM_SLEEP */
@@ -166,6 +236,33 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_dis_ahb;
}
 
+   sdhci_arasan->phy = NULL;
+   if (of_device_is_compatible(pdev->dev.of_node,
+   "arasan,sdhci-5.1")) {
+   sdhci_arasan->phy = devm_phy_get(&pdev->dev,
+"phy_arasan");
+   if (IS_ERR(sdhci_arasan->phy)) {
+   ret = -ENODEV;
+   dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
+   goto clk_dis_ahb;
+   }
+
+   ret = phy_power_on(sdhci_arasan->phy);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "phy_power_on err.\n");
+   phy_power_off(sdhci_arasan->phy);
+   goto clk_dis_ahb;
+   }
+
+   ret = phy_init(sdhci_arasan->phy);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "phy_init err.\n");
+   phy_exit(sdhci_arasan->phy);
+   phy_power_off(sdhci_arasan->phy);
+   goto clk_dis_ahb;
+   }
+   }
+
host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 0);
if (IS_ERR(host)) {
ret = PTR_ERR(host);
-- 
2.3.7


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Re: [PATCH 2/2] Documentation: bindings: add description of phy for sdhci-of-arasan

[Shawn Lin]

在 2015/9/14 10:47, Sören Brinkmann 写道:

Hi Shawn,

On Fri, 2015-09-11 at 04:55PM +0800, Shawn Lin wrote:

This patch adds phys and phy-names for sdhci-of-arasan as optional
properties, and details the example as well.

Signed-off-by: Shawn Lin 
---

  Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index da541c3..0264d5f 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -1,11 +1,12 @@
  Device Tree Bindings for the Arasan SDHCI Controller

-  The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. Only
-  deviations are documented here.
+  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+  Only deviations are documented here.

[1] Documentation/devicetree/bindings/mmc/mmc.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt

  Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
@@ -16,6 +17,9 @@ Required Properties:
- interrupts: Interrupt specifier
- interrupt-parent: Phandle for the interrupt controller that services
  interrupts for this device.
+Optional Properties:
+  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
+  - phy-names:  MUST be "phy_arasan".


This might be a dumb question, but, is the external phy actually
optional? Or is it mandatory for certain implementations of the IP.
In the latter case, it should probably be a mandatory property depending
on the compatible string matching an implementation that requires an
external phy (accordingly, the implementation might have to treat it


From my soc team's reponse, there is no way to bypass controller to IO 
if no phy supported. So it should be the latter case you mentioned for 
arasan.sdhci-5.1.


Thanks for point out it, really helpful.

I will fix it in v2.


that way too).

Sören






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[PATCH 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Shawn Lin]

This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.

Signed-off-by: Shawn Lin 
---

 drivers/mmc/host/sdhci-of-arasan.c | 90 ++
 1 file changed, 90 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index 621c3f4..fdd71c7 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -21,6 +21,7 @@
 
 #include 
 #include 
+#include 
 #include "sdhci-pltfm.h"
 
 #define SDHCI_ARASAN_CLK_CTRL_OFFSET   0x2c
@@ -35,6 +36,7 @@
  */
 struct sdhci_arasan_data {
struct clk  *clk_ahb;
+   struct phy  *phy;
 };
 
 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
@@ -67,6 +69,62 @@ static struct sdhci_pltfm_data sdhci_arasan_pdata = {
 
 #ifdef CONFIG_PM_SLEEP
 /**
+  * sdhci_arasan_suspend_phy - Suspend phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a deactive state.
+  */
+static int sdhci_arasan_suspend_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_exit(phy);
+   if (ret < 0)
+   goto err_phy_exit;
+
+   ret = phy_power_off(phy);
+   if (ret < 0)
+   goto err_phy_pwr_off;
+
+   return 0;
+
+err_phy_pwr_off:
+   phy_power_on(phy);
+err_phy_exit:
+   phy_init(phy);
+   return ret;
+}
+
+/**
+  * sdhci_arasan_resume_phy - Resume phy method for the driver
+  * @phy:Handler of phy structure
+  * Returns 0 on success and error value on error
+  *
+  * Put the phy in a active state.
+  */
+static int sdhci_arasan_resume_phy(struct phy *phy)
+{
+   int ret;
+
+   ret = phy_power_on(phy);
+   if (ret < 0)
+   goto err_phy_pwr_on;
+
+   ret = phy_init(phy);
+   if (ret < 0)
+   goto err_phy_init;
+
+   return 0;
+
+err_phy_init:
+   phy_exit(phy);
+err_phy_pwr_on:
+   phy_power_off(phy);
+   return ret;
+}
+
+/**
  * sdhci_arasan_suspend - Suspend method for the driver
  * @dev:   Address of the device structure
  * Returns 0 on success and error value on error
@@ -88,6 +146,12 @@ static int sdhci_arasan_suspend(struct device *dev)
clk_disable(pltfm_host->clk);
clk_disable(sdhci_arasan->clk_ahb);
 
+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_suspend_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }
+
return 0;
 }
 
@@ -119,6 +183,12 @@ static int sdhci_arasan_resume(struct device *dev)
return ret;
}
 
+   if (sdhci_arasan->phy) {
+   ret = sdhci_arasan_resume_phy(sdhci_arasan->phy);
+   if (ret < 0)
+   return ret;
+   }
+
return sdhci_resume_host(host);
 }
 #endif /* ! CONFIG_PM_SLEEP */
@@ -163,6 +233,26 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_dis_ahb;
}
 
+   sdhci_arasan->phy = devm_phy_get(&pdev->dev, "phy_arasan");
+   if (!IS_ERR(sdhci_arasan->phy)) {
+   ret = phy_power_on(sdhci_arasan->phy);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "phy_power_on err.\n");
+   phy_power_off(sdhci_arasan->phy);
+   goto clk_dis_ahb;
+   }
+
+   ret = phy_init(sdhci_arasan->phy);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "phy_init err.\n");
+   phy_exit(sdhci_arasan->phy);
+   phy_power_off(sdhci_arasan->phy);
+   goto clk_dis_ahb;
+   }
+   } else {
+   sdhci_arasan->phy = NULL;
+   }
+
host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 0);
if (IS_ERR(host)) {
ret = PTR_ERR(host);
-- 
2.3.7


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[PATCH 2/2] Documentation: bindings: add description of phy for sdhci-of-arasan

[Shawn Lin]

This patch adds phys and phy-names for sdhci-of-arasan as optional
properties, and details the example as well.

Signed-off-by: Shawn Lin 
---

 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index da541c3..0264d5f 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -1,11 +1,12 @@
 Device Tree Bindings for the Arasan SDHCI Controller
 
-  The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. Only
-  deviations are documented here.
+  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+  Only deviations are documented here.
 
   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
@@ -16,6 +17,9 @@ Required Properties:
   - interrupts: Interrupt specifier
   - interrupt-parent: Phandle for the interrupt controller that services
  interrupts for this device.
+Optional Properties:
+  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
+  - phy-names:  MUST be "phy_arasan".
 
 Example:
sdhci@e010 {
@@ -25,4 +29,6 @@ Example:
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
+   phys = <&emmc_phy>;
+   phy-names = "phy_arasan";
} ;
-- 
2.3.7


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[RFC PATCH v7 03/10] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.

Signed-off-by: Shawn Lin 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 25 ++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+  Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
 
+[board specific internal DMA resources]
+
+   dwmmc0@1220 {
+   clock-frequency = <4>;
+   clock-freq-min-max = <40 2>;
+   num-slots = <1>;
+   broken-cd;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   vmmc-supply = <&buck8>;
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+   dmas = <&pdma 12>;
+   dma-names = "rx-tx";
};
-- 
2.3.7


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[RFC PATCH v7 10/10] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/zx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7


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[RFC PATCH v7 04/10] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Govindraj Raja 
Acked-by: Ralf Baechle 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig 
b/arch/mips/configs/pistachio_defconfig
index 1646cce..013c62c 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7


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[RFC PATCH v7 07/10] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Wei Xu 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/hisi_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
2.3.7


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[RFC PATCH v7 05/10] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Vineet Gupta 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig | 1 -
 arch/arc/configs/axs103_defconfig | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig 
b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig 
b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig 
b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
-- 
2.3.7


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[RFC PATCH v7 09/10] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..a3734b5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
-- 
2.3.7


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[RFC PATCH v7 08/10] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Joachim Eastwood 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/lpc18xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/lpc18xx_defconfig 
b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
-- 
2.3.7


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[RFC PATCH v7 06/10] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Krzysztof Kozlowski 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/exynos_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 9504e77..7e4af6e 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
-- 
2.3.7


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[RFC PATCH v7 02/10] mmc: dw_mmc: use macro for HCON register operations

[Shawn Lin]

This patch add some macros for HCON register operations
to make code more readable.

Signed-off-by: Shawn Lin 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/mmc/host/dw_mmc.c | 6 +++---
 drivers/mmc/host/dw_mmc.h | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 9c91983..0a3c63c 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2678,7 +2678,7 @@ static void dw_mci_init_dma(struct dw_mci *host)
* Check ADDR_CONFIG bit in HCON to find
* IDMAC address bus width
*/
-   addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
+   addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
 
if (addr_config == 1) {
/* host supports IDMAC in 64-bit address mode */
@@ -3060,7 +3060,7 @@ int dw_mci_probe(struct dw_mci *host)
 * Get the host data width - this assumes that HCON has been set with
 * the correct values.
 */
-   i = (mci_readl(host, HCON) >> 7) & 0x7;
+   i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
if (!i) {
host->push_data = dw_mci_push_data16;
host->pull_data = dw_mci_pull_data16;
@@ -3142,7 +3142,7 @@ int dw_mci_probe(struct dw_mci *host)
if (host->pdata->num_slots)
host->num_slots = host->pdata->num_slots;
else
-   host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
+   host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
 
/*
 * Enable interrupts for command done, data over, data empty,
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 811d467..f2a88d4 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -154,6 +154,9 @@
 #define DMA_INTERFACE_GDMA (0x2)
 #define DMA_INTERFACE_NODMA(0x3)
 #define SDMMC_GET_TRANS_MODE(x)(((x)>>16) & 0x3)
+#define SDMMC_GET_SLOT_NUM(x)  x)>>1) & 0x1F) + 1)
+#define SDMMC_GET_HDATA_WIDTH(x)   (((x)>>7) & 0x7)
+#define SDMMC_GET_ADDR_CONFIG(x)   (((x)>>27) & 0x1)
 /* Internal DMAC interrupt defines */
 #define SDMMC_IDMAC_INT_AI BIT(9)
 #define SDMMC_IDMAC_INT_NI BIT(8)
-- 
2.3.7


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[RFC PATCH v7 0/10] Add external dma support for Synopsys MSHC

[Shawn Lin]

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc

Test emmc throughput on my platform with edmac support and without edmac 
support(pio only)
iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile -Rb 
out.xls > /mnt/result.txt
(light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
in total)
 ___
|   external dma mode   |
|---|
|blksz | Random Read | Random Write | Seq Read   | Seq Write|
|---|
|4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
|---|
|64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
|---|
|128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
|---|
   VS
 ___
|  pio mode |
|---|
|blksz | Random Read  | Random Write | Seq Read  | Seq Write|
|---|
|4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
|---|
|64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
|---|
|128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
|---|


Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (10):
  mmc: dw_mmc: Add external dma interface support
  mmc: dw_mmc: use macro for HCON register operations
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: multi_v7_defconfig: remove CON

[RFC PATCH v7 01/10] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK31xx
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v7:
- rebased on Ulf's next
- combine condition state
- elaborate more about DMA_INTERFACE
- define some macro for DMA_INERFACE value
- spilt HCON ops' changes into another patch

Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig|  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c   | 273 
 drivers/mmc/host/dw_mmc.h   |   6 +
 include/linux/mmc/dw_mmc.h  |  23 +++-
 5 files changed, 253 insertions(+), 62 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..539b1a6 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA mode.
 
 config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..9c91983 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,6 @@
 #define DW_MCI_FREQ_MAX2   /* unit: HZ */
 #define DW_MCI_FREQ_MIN40  /* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
 #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -102,7 +101,6 @@ struct idmac_desc {
 
 /* Each descriptor can transfer up to 4KB of data in chained mode */
 #define DW_MCI_DESC_DATA_LENGTH0x1000
-#endif /* CONFIG_MMC_DW_IDMAC */
 
 static bool dw_mci_reset(struct dw_mci *host);
 static bool dw_mci_ctrl_

Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

On 2015/8/21 15:38, Jaehoon Chung wrote:

On 08/21/2015 04:27 PM, Shawn Lin wrote:

On 2015/8/21 14:35, Jaehoon Chung wrote:

On 08/21/2015 03:30 PM, Shawn Lin wrote:

On 2015/8/21 14:27, Jaehoon Chung wrote:

Hi, Shawn.

Is this based on Ulf's repository?



no, it's based on "https://github.com/jh80chung/dw-mmc.git 
tags/dw-mmc-for-ulf-v4.2" ：）


Oh..I will rebase to Ulf's next branch on this weekend.
Then could you rebase this patch? And i added more comments at below.. :)



Okay, I will rebase to Ulf's next.


Best Regards,
Jaehoon Chung





[...]


index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;

regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+/* Get registers' physical base address */
+host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);


Is this board specific code? If so, separate the patch.


It's might not board specific code.
dmaengine need dw_mmc's *physical* fifo address for data transfer, so I get 
controller physical address  here in order to calculate physical fifo address.

regs is from dt-bindings, for instance:
  dwmmc0@1220 {
  compatible = "snps,dw-mshc";
   clocks = <&clock 351>, <&clock 132>;
  clock-names = "biu", "ciu";
  reg = <0x1220 0x1000>;
  interrupts = <0 75 0>;
  #address-cells = <1>;
  #size-cells = <0>;
  };

so, host->phy_regs will be 0x1220 .

[...]


+static void dw_mci_dmac_complete_dma(void *arg)
{
+struct dw_mci *host = arg;
struct mmc_data *data = host->data;

dev_vdbg(host->dev, "DMA complete\n");

+if (host->use_dma == TRANS_MODE_EDMAC)
+if (data && (data->flags & MMC_DATA_READ))


Combine one condition.


okay.

[...]


+u32 fifo_offset = host->fifo_reg - host->regs;
+int ret = 0;
+
+/* Set external dma config: burst size, burst width */
+cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);


host->phy_regs is not assigned?


we got it at dw_mci_pltfm_register. See comments above. :)

[...]


mmc->max_blk_count = mmc->max_req_size / 512;
+} else if (host->use_dma == TRANS_MODE_EDMAC) {
+mmc->max_segs = 64;
+mmc->max_blk_size = 65536;
+mmc->max_blk_count = 65535;
+mmc->max_req_size =
+mmc->max_blk_size * mmc->max_blk_count;
+mmc->max_seg_size = mmc->max_req_size;


Fix the indention


Hmm..I check it attentively but can't find the indention . Might it's because 
you apply it against Ulf's repo?





[...]



-/* Alloc memory for sg translation */
-host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
-  &host->sg_dma, GFP_KERNEL);
-if (!host->sg_cpu) {
-dev_err(host->dev, "%s: could not alloc DMA memory\n",
-__func__);
+/* Check tansfer mode */
+trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
+if (trans_mode == 0) {
+trans_mode = TRANS_MODE_IDMAC;
+} else if (trans_mode == 1 || trans_mode == 2) {
+trans_mode = TRANS_MODE_EDMAC;
+} else {
+trans_mode = TRANS_MODE_PIO;


what are trans_mode "0, 1, 2"?
(00 - none) is NO-DMA interface, isn't? is it IDMAC mode?



No, I guess the databook's ambiguous description confuse everybody.

I got double comfirm from my ASCI team as well as Synoposys
2b'00: NO-DMA interface -->  It support IDMAC actually
2b'01 & 2b'02: DW_DMA & GENERIC_DMA --> Support 2 types of external dma.
2b'02: NON-DW-DMA --> only support PIO


Then Could you add the comment about this?
Use definition instead of "0, 1, 2". Developer don't know meaning that is 0, 1, 
2.



Okay. :)))


Best Regards,
Jaehoon Chung



refer to the description below:
Parameter Name: DMA_INTERFACE
Legal Values: 0-3
Default Value: 0
Description:
  0- No DMA Interface
  1- DesignWare DMA Interface
  2- Generic DMA Interface
  3- Non DW DMA Interface
In DesignWare DMA mode, request/acknowledge protocol meets DW_ahb_dmac
controller protocol. In this mode, host data bus is also used for DMA 
transfers.Generic DMA-type interface has simpler request/acknowledge handshake 
and has dedicated read/write data bus for DMA transfers. Non DW DMAC interface 
uses dw_dma_single interface in addition to the existing interface and use

Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

On 2015/8/21 14:35, Jaehoon Chung wrote:

On 08/21/2015 03:30 PM, Shawn Lin wrote:

On 2015/8/21 14:27, Jaehoon Chung wrote:

Hi, Shawn.

Is this based on Ulf's repository?



no, it's based on "https://github.com/jh80chung/dw-mmc.git 
tags/dw-mmc-for-ulf-v4.2" ：）


Oh..I will rebase to Ulf's next branch on this weekend.
Then could you rebase this patch? And i added more comments at below.. :)



Okay, I will rebase to Ulf's next.


Best Regards,
Jaehoon Chung





[...]


index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
   host->pdata = pdev->dev.platform_data;

   regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+/* Get registers' physical base address */
+host->phy_regs = (void *)(regs->start);
   host->regs = devm_ioremap_resource(&pdev->dev, regs);
   if (IS_ERR(host->regs))
   return PTR_ERR(host->regs);


Is this board specific code? If so, separate the patch.


It's might not board specific code.
dmaengine need dw_mmc's *physical* fifo address for data transfer, so I 
get controller physical address  here in order to calculate physical 
fifo address.


regs is from dt-bindings, for instance:
 dwmmc0@1220 {
 compatible = "snps,dw-mshc";
  clocks = <&clock 351>, <&clock 132>;
 clock-names = "biu", "ciu";
 reg = <0x1220 0x1000>;
 interrupts = <0 75 0>;
 #address-cells = <1>;
 #size-cells = <0>;
 };

so, host->phy_regs will be 0x1220 .

[...]


+static void dw_mci_dmac_complete_dma(void *arg)
   {
+struct dw_mci *host = arg;
   struct mmc_data *data = host->data;

   dev_vdbg(host->dev, "DMA complete\n");

+if (host->use_dma == TRANS_MODE_EDMAC)
+if (data && (data->flags & MMC_DATA_READ))


Combine one condition.


okay.

[...]


+u32 fifo_offset = host->fifo_reg - host->regs;
+int ret = 0;
+
+/* Set external dma config: burst size, burst width */
+cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);


host->phy_regs is not assigned?


we got it at dw_mci_pltfm_register. See comments above. :)

[...]


   mmc->max_blk_count = mmc->max_req_size / 512;
+} else if (host->use_dma == TRANS_MODE_EDMAC) {
+mmc->max_segs = 64;
+mmc->max_blk_size = 65536;
+mmc->max_blk_count = 65535;
+mmc->max_req_size =
+mmc->max_blk_size * mmc->max_blk_count;
+mmc->max_seg_size = mmc->max_req_size;


Fix the indention


Hmm..I check it attentively but can't find the indention . Might it's 
because you apply it against Ulf's repo?






[...]



-/* Alloc memory for sg translation */
-host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
-  &host->sg_dma, GFP_KERNEL);
-if (!host->sg_cpu) {
-dev_err(host->dev, "%s: could not alloc DMA memory\n",
-__func__);
+/* Check tansfer mode */
+trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
+if (trans_mode == 0) {
+trans_mode = TRANS_MODE_IDMAC;
+} else if (trans_mode == 1 || trans_mode == 2) {
+trans_mode = TRANS_MODE_EDMAC;
+} else {
+trans_mode = TRANS_MODE_PIO;


what are trans_mode "0, 1, 2"?
(00 - none) is NO-DMA interface, isn't? is it IDMAC mode?



No, I guess the databook's ambiguous description confuse everybody.

I got double comfirm from my ASCI team as well as Synoposys
2b'00: NO-DMA interface -->  It support IDMAC actually
2b'01 & 2b'02: DW_DMA & GENERIC_DMA --> Support 2 types of external dma.
2b'02: NON-DW-DMA --> only support PIO

refer to the description below:
Parameter Name: DMA_INTERFACE
Legal Values: 0-3
Default Value: 0
Description:
 0- No DMA Interface
 1- DesignWare DMA Interface
 2- Generic DMA Interface
 3- Non DW DMA Interface
In DesignWare DMA mode, request/acknowledge protocol meets DW_ahb_dmac
controller protocol. In this mode, host data bus is also used for DMA 
transfers.Generic DMA-type interface has simpler request/acknowledge 
handshake and has dedicated read/write data bus for DMA transfers. Non 
DW DMAC interface uses dw_dma_single interface in addition to the 
existing interface and uses host data bus for DMA transfers. This is 
configurable only if INTERNAL_DMAC=0.



   goto no_dma;
   }



+dev_info(host->dev, "Using external DMA controller.\n");
+}

   if (!host->dma_ops)
   goto no_dma;
@@ -2562,12 +2720,1

Re: [RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

On 2015/8/21 14:27, Jaehoon Chung wrote:

Hi, Shawn.

Is this based on Ulf's repository?



no, it's based on "https://github.com/jh80chung/dw-mmc.git 
tags/dw-mmc-for-ulf-v4.2" ：）




On 08/20/2015 05:43 PM, Shawn Lin wrote:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK31xx
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v6:
- add trans_mode condition for IDMAC initialization
   suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
   "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
   transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

  drivers/mmc/host/Kconfig|  11 +-
  drivers/mmc/host/dw_mmc-pltfm.c |   2 +
  drivers/mmc/host/dw_mmc.c   | 264 
  drivers/mmc/host/dw_mmc.h   |   5 +
  include/linux/mmc/dw_mmc.h  |  27 +++-
  5 files changed, 242 insertions(+), 67 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.

  config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;

regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);


Is this board specific code? If so, separate the patch.


diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..f943619 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,6 @@
  #define DW_MCI_FREQ_MAX   2   /* unit: HZ */
  #define DW_MCI_FREQ_MIN   40  /* unit: HZ */

-#ifdef CONFIG_MMC_DW_IDMAC
  #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -102,7 +101,6 @@ struct idmac_desc {

  /* Each descriptor can transfer up to 4KB of data in chained mode */
  #define DW_MCI_DESC_DATA_LENGT

[RFC PATCH v6 2/9] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.

Signed-off-by: Shawn Lin 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 25 ++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+  Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
 
+[board specific internal DMA resources]
+
+   dwmmc0@1220 {
+   clock-frequency = <4>;
+   clock-freq-min-max = <40 2>;
+   num-slots = <1>;
+   broken-cd;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   vmmc-supply = <&buck8>;
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+   dmas = <&pdma 12>;
+   dma-names = "rx-tx";
};
-- 
2.3.7


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[RFC PATCH v6 4/9] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Vineet Gupta 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig | 1 -
 arch/arc/configs/axs103_defconfig | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig 
b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig 
b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig 
b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
-- 
2.3.7


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[RFC PATCH v6 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK31xx
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig|  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c   | 264 
 drivers/mmc/host/dw_mmc.h   |   5 +
 include/linux/mmc/dw_mmc.h  |  27 +++-
 5 files changed, 242 insertions(+), 67 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
 
 config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..f943619 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,6 @@
 #define DW_MCI_FREQ_MAX2   /* unit: HZ */
 #define DW_MCI_FREQ_MIN40  /* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
 #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -102,7 +101,6 @@ struct idmac_desc {
 
 /* Each descriptor can transfer up to 4KB of data in chained mode */
 #define DW_MCI_DESC_DATA_LENGTH0x1000
-#endif /* CONFIG_MMC_DW_IDMAC */
 
 static bool dw_mci_reset(struct dw_mci *host);
 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -407,7 +405,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
 }
 
-#ifdef CONFIG_MMC_DW_IDMAC
 

[RFC PATCH v6 6/9] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Wei Xu 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/hisi_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
2.3.7


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[RFC PATCH v6 5/9] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Krzysztof Kozlowski 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/exynos_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 9504e77..7e4af6e 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
-- 
2.3.7


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[RFC PATCH v6 7/9] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Joachim Eastwood 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/lpc18xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/lpc18xx_defconfig 
b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
-- 
2.3.7


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[RFC PATCH v6 8/9] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..a3734b5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
-- 
2.3.7


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[RFC PATCH v6 9/9] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/zx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7


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[RFC PATCH v6 3/9] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Govindraj Raja 
Acked-by: Ralf Baechle 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig 
b/arch/mips/configs/pistachio_defconfig
index 1646cce..013c62c 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7


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[RFC PATCH v6 0/9] Add external dma support for Synopsys MSHC

[Shawn Lin]

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch v1~v4 is based on next of git://git.linaro.org/people/ulf.hansson/mmc
Patch v5~v6 is rebased on dw-mmc-for-ulf-v4.2 of 
https://github.com/jh80chung/dw-mmc.git

Test emmc throughput on my platform with edmac support and without edmac 
support(pio only)
iozone -L64 -S32 -azecwI -+n -r4k -r64k -r128k -s1g -i0 -i1 -i2 -f datafile -Rb 
out.xls > /mnt/result.txt
(light cpu loading, Direct IO, fixed line size, all pattern recycle, 1GB data 
in total)
 ___
|   external dma mode   |
|---|
|blksz | Random Read | Random Write | Seq Read   | Seq Write|
|---|
|4kB   |  13953kB/s  |8602kB/s  | 13672kB/s  |  9785kB/s|
|---|
|64kB  |  46058kB/s  |   24794kB/s  | 48058kB/s  | 25418kB/s|
|---|
|128kB |  57026kB/s  |   35117kB/s  | 57375kB/s  | 35183kB/s|
|---|
   VS
 ___
|  pio mode |
|---|
|blksz | Random Read  | Random Write | Seq Read  | Seq Write|
|---|
|4kB   |  11720kB/s   |8644kB/s  | 11549kB/s |  9624kB/s|
|---|
|64kB  |  21869kB/s   |   24414kB/s  | 22031kB/s | 27986kB/s|
|---|
|128kB |  23718kB/s   |   34495kB/s  | 24698kB/s | 34637kB/s|
|---|


Changes in v6:
- add trans_mode condition for IDMAC initialization
  suggested by Heiko
- re-test my patch on rk3188 platform and update commit msg
- update performance of pio vs edmac in cover letter

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (9):
  mmc: dw_mmc: Add external dma interface support
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 ++
 arch/arc/configs/axs101

Re: [RFC PATCH v1] mmc: sdhci-of-arasan: Add the support for sdhci-5.1

[Shawn Lin]

Hi Ulf,

On 2015/8/12 13:07, Michal Simek wrote:

+linux-mmc

On 08/11/2015 04:53 PM, Michal Simek wrote:

On 08/11/2015 09:46 AM, Shawn Lin wrote:

This patch adds the compatible string in sdhci-of-arasan.c to
support sdhci-arasan5.1 version of controller. No documented
controller IP version is found in the TRM, so we use ths version
of command queueing engine integrated into this controller by arasan
to specify our controller.

Signed-off-by: Shawn Lin 

---

Changes in v1:
- Remove redundant SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN for "arasan, sdhci-5.1" 
since
   SDHCI will check "host->max_clk == 0" and let driver get it from 
host->ops->get_max_clock.

  Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
  drivers/mmc/host/sdhci-of-arasan.c | 1 +
  2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller

  Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..75379cb 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -217,6 +217,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)

  static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+   { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
    { }
  };



Acked-by: Michal Simek 


Could you pull this patch into your repository?



Thanks,
Michal










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Re: [RFC PATCH v5 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/17 5:10, Doug Anderson 写道:

Heiko,

On Fri, Aug 14, 2015 at 3:13 PM, Heiko Stübner  wrote:

Hi Shawn,

Am Freitag, 14. August 2015, 16:34:35 schrieb Shawn Lin:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 


judging by your "from", I guess you're running this on some older Rockchip soc
without the idma? Because I tried testing this on a Radxa Rock, but only got
failures, from the start (failed to read card status register). In PIO mode
everything works again.


I guess I overlooked just some tiny detail, but to me the dma channel ids seem
correct after all. Maybe you have any hints what I'm doing wrong?


If I were a guessing man (which I'm not), I'd guess that perhaps
you're running into troubles with our friend the PL330.

There appear to be strange issues with the PL330 on Rockchip SoCs.  I
was only peripherally involved with them, but I know at least about
some of the patches in our tree, like:



Thanks, Doug, that's the root cause. PL330 on Rockchip Socs need your 
patches, and we might need another patch to limit pl330 burst_len to 
16(Hmm...seems another quirks for rockchip but not on your tree);


Hi Heiko,
I just get a Radxa Rock luckily and test my patch based on 
http://radxa.com/Rock/Linux_Mainline. Yes, it can't work.


If you test my patchset on Rockchip platform, pls apply pl330 patch from 
my tree based on kernel 4.2-RC3. AND, temporary hack dw_mmc to limit 
pl330 burst_len to 16.
This is a dmaengine or pl330 problem(I guest it should be upstreamed 
later?), but my patchset is for *generic* dw_mmc to support emdac, so 
other platforms should never need the hack of pl330.


pl330.patch is for pl330 changes
r3xxx.patch is for pl330 quirks

AND pls limit burst_len to 16 for BROKRN pl330 of rockchips.
static int dw_mci_edmac_start_dma(
...
+u32 burst_limit = 0;
+u32 mburst;
+u32 idx, rx_wmark, tx_wmark;

...
/* Match burst msize with external dma config */
fifoth_val = mci_readl(host, FIFOTH);
-   cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
-   cfg.src_maxburst = cfg.dst_maxburst;
+   /* HACK for BROKEN pl330 */
+   mburst = mszs[(fifoth_val >> 28) & 0x7];
+   burst_limit = 16;
+   if (mburst > burst_limit) {
+   mburst = burst_limit;
+   idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
+   rx_wmark = mszs[idx] - 1;
+   tx_wmark = (host->fifo_depth) / 2;
+   fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
+   mci_writel(host, FIFOTH, fifoth_val);
+   }
+   cfg.dst_maxburst = mburst;
+   cfg.src_maxburst = cfg.dst_maxburst;



https://chromium-review.googlesource.com/237607
FROMLIST: DMA: pl330: support burst mode for dev-to-mem and mem-to-dev transmit

https://chromium-review.googlesource.com/237393
CHROMIUM: dmaengine: pl330: support quirks for some broken

https://chromium-review.googlesource.com/237396
CHROMIUM: dmaengine: pl330: add quirk for broken no flushp

https://chromium-review.googlesource.com/237394
CHROMIUM: ARM: dts: rockchip: Add broken-no-flushp into rk3288.dtsi

https://chromium-review.googlesource.com/242063
CHROMIUM: ASoC: rockchip_i2s: modify DMA max burst to 1






--
Shawn Lin
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index ecab4ea..b2a950c 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -34,6 +34,14 @@
 #define PL330_MAX_IRQS 32
 #define PL330_MAX_PERI 32
 
+#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
+
+enum pl330_cond {
+   SINGLE,
+   BURST,
+   ALWAYS,
+};
+
 enum pl330_cachectrl {
CCTRL0, /* Noncacheable and nonbufferable */
CCTRL1, /* Bufferable only */
@@ -344,12 +352,6 @@ enum pl330_dst {
DST,
 };
 
-enum pl330_cond {
-   SINGLE,
-   BURST,
-   ALWAYS,
-};
-
 struct dma_pl330_desc;
 
 struct _pl330_req {
@@ -488,6 +490,17 @@ struct pl330_dmac {
/* Peripheral channels connected to this DMAC */
unsigned int num_peripherals;
struct dma_pl330_chan *peripherals; /* keep at end */
+   int quirks;
+};
+
+static struct pl330_of_quirks {
+   char *quirk;
+   int id;
+} of_quirks[] = {
+   {
+   .quirk = "broken-no-flushp",
+   .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
+   }
 };
 
 struct dma_pl330_desc {
@@ -1137,47 +1150,64 @@ static inline int _ldst_memtomem(unsigned dry_run, u8 
buf[],
return off;
 }
 
-static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
+static inline int _ldst_devtomem(struct pl330_dmac *pi,unsigned dry_run, u8 
buf[],
  

Re: [RFC PATCH v5 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/15 6:13, Heiko Stübner 写道:

Hi Shawn,

Am Freitag, 14. August 2015, 16:34:35 schrieb Shawn Lin:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 


judging by your "from", I guess you're running this on some older Rockchip soc
without the idma? Because I tried testing this on a Radxa Rock, but only got
failures, from the start (failed to read card status register). In PIO mode
everything works again.


I guess I overlooked just some tiny detail, but to me the dma channel ids seem
correct after all. Maybe you have any hints what I'm doing wrong?



Thanks, HeiKo.

yes, I'm running a quite older low-end Rockchip soc w/o idma.

Hmm... from your failure to read CSR, I think generic DMA of Radxa Rock 
was not runing properly. Your dma channel ids is correct, but it 
certainly work on my platform。 I will try to find a Radxa Rock to 
re-test my patch ASAP.





diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 4497d28..92d7156 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -217,6 +217,8 @@
 interrupts = ;
 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 clock-names = "biu", "ciu";
+ dmas = <&dmac2 1>;
+ dma-names = "rx-tx";
 fifo-depth = <256>;
 status = "disabled";
 };
@@ -227,6 +229,8 @@
 interrupts = ;
 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 clock-names = "biu", "ciu";
+ dmas = <&dmac2 3>;
+ dma-names = "rx-tx";
 fifo-depth = <256>;
 status = "disabled";
 };
@@ -237,6 +241,8 @@
 interrupts = ;
 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 clock-names = "biu", "ciu";
+ dmas = <&dmac2 4>;
+ dma-names = "rx-tx";
 fifo-depth = <256>;
 status = "disabled";
 };


[...]


diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..e01ead3 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2517,8 +2642,23 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot, unsigned int id) static void dw_mci_init_dma(struct dw_mci *host)
  {
int addr_config;
+   int trans_mode;
+   struct device *dev = host->dev;
+   struct device_node *np = dev->of_node;
+
+   /* Check tansfer mode */
+   trans_mode = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
+   if (trans_mode == 0) {
+   trans_mode = TRANS_MODE_IDMAC;
+   } else if (trans_mode == 1 || trans_mode == 2) {
+   trans_mode = TRANS_MODE_EDMAC;
+   } else {
+   trans_mode = TRANS_MODE_PIO;
+   goto no_dma;
+   }
+
/* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
-   addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
+   addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));

if (addr_config == 1) {
/* host supports IDMAC in 64-bit address mode */


I guess the idmac address size checking block

 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));

 if (addr_config == 1) {
 /* host supports IDMAC in 64-bit address mode */
 host->dma_64bit_address = 1;
 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
 } else {
 /* host supports IDMAC in 32-bit address mode */
 host->dma_64bit_address = 0;
     dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
 }

could either live inside the trans_mode == 0 conditional above or get its own
if (trans_mode == 0) conditional. Either way I guess it should not talk about
idmac when either pio or extdmac are used.


Thanks
Heiko






--
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[RFC PATCH v5 2/9] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.

Signed-off-by: Shawn Lin 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 25 ++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+  Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
 
+[board specific internal DMA resources]
+
+   dwmmc0@1220 {
+   clock-frequency = <4>;
+   clock-freq-min-max = <40 2>;
+   num-slots = <1>;
+   broken-cd;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   vmmc-supply = <&buck8>;
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+   dmas = <&pdma 12>;
+   dma-names = "rx-tx";
};
-- 
2.3.7


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[RFC PATCH v5 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig|  11 +--
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c   | 209 ++--
 drivers/mmc/host/dw_mmc.h   |   5 +
 include/linux/mmc/dw_mmc.h  |  27 +-
 5 files changed, 210 insertions(+), 44 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
 
 config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..e01ead3 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,6 @@
 #define DW_MCI_FREQ_MAX2   /* unit: HZ */
 #define DW_MCI_FREQ_MIN40  /* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
 #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -102,7 +101,6 @@ struct idmac_desc {
 
 /* Each descriptor can transfer up to 4KB of data in chained mode */
 #define DW_MCI_DESC_DATA_LENGTH0x1000
-#endif /* CONFIG_MMC_DW_IDMAC */
 
 static bool dw_mci_reset(struct dw_mci *host);
 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -407,7 +405,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
 }
 
-#ifdef CONFIG_MMC_DW_IDMAC
 static void dw_mci_dma_cleanup(struct dw_mci *host)
 {
struct mmc_data *data = host->data;
@@ -445,12 +442,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
mci_writel(host, BM

[RFC PATCH v5 4/9] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Vineet Gupta 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig | 1 -
 arch/arc/configs/axs103_defconfig | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig 
b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig 
b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig 
b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
-- 
2.3.7


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[RFC PATCH v5 3/9] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Govindraj Raja 
Acked-by: Ralf Baechle 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig 
b/arch/mips/configs/pistachio_defconfig
index 1646cce..013c62c 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7


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[RFC PATCH v5 5/9] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Krzysztof Kozlowski 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/exynos_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 9504e77..7e4af6e 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
-- 
2.3.7


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[RFC PATCH v5 6/9] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Wei Xu 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/hisi_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
2.3.7


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[RFC PATCH v5 7/9] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
Acked-by: Joachim Eastwood 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/lpc18xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/lpc18xx_defconfig 
b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
-- 
2.3.7


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[RFC PATCH v5 9/9] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/zx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7


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[RFC PATCH v5 8/9] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..a3734b5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
-- 
2.3.7


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[RFC PATCH v5 0/9] Add external dma support for Synopsys MSHC

[Shawn Lin]

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch v1~v4 is based on next of git://git.linaro.org/people/ulf.hansson/mmc
Patch v5 is rebased on dw-mmc-for-ulf-v4.2 of 
https://github.com/jh80chung/dw-mmc.git


Changes in v5:
- add the title of cover letter
- fix typo of comment
- add macro for reading HCON register
- add "Acked-by: Krzysztof Kozlowski " for 
exynos_defconfig patch
- add "Acked-by: Vineet Gupta " for axs10x_defconfig patch
- add "Acked-by: Govindraj Raja " and
  "Acked-by: Ralf Baechle " for pistachio_defconfig patch
- add "Acked-by: Joachim Eastwood " for lpc18xx_defconfig 
patch
- add "Acked-by: Wei Xu " for hisi_defconfig patch
- rebase on "https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" 
for merging easily

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (9):
  mmc: dw_mmc: Add external dma interface support
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 +++
 arch/arc/configs/axs101_defconfig  |   1 -
 arch/arc/configs/axs103_defconfig  |   1 -
 arch/arc/configs/axs103_smp_defconfig  |   1 -
 arch/arm/configs/exynos_defconfig  |   1 -
 arch/arm/configs/hisi_defconfig|   1 -
 arch/arm/configs/lpc18xx_defconfig |   1 -
 arch/arm/configs/multi_v7_defconfig|   1 -
 arch/arm/configs/zx_defconfig  |   1 -
 arch/mips/configs/pistachio_defconfig  |   1 -
 drivers/mmc/host/Kconfig   |  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c|   2 +
 drivers/mmc/host/dw_mmc.c  | 209 ++---
 drivers/mmc/host/dw_mmc.h  |   5 +
 include/linux/mmc/dw_mmc.h |  27 ++-
 15 files changed, 235 insertions(+), 53 deletions(-)

-- 
2.3.7


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Re: [RFC PATCH v4 3/9] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

在 2015/8/13 6:05, Ralf Baechle 写道:

On Thu, Aug 06, 2015 at 02:45:15PM +0800, Shawn Lin wrote:


DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

  arch/mips/configs/pistachio_defconfig | 1 -


Acked-by: Ralf Baechle 

Please feel free to merge this patch with the remainder
of the series.



Thanks, Ralf. :)

v5 is coming which will be rebased on 
"https://github.com/jh80chung/dw-mmc.git tags/dw-mmc-for-ulf-v4.2" for 
the next merge window

that make Jeahoon do it easier. Also define new macro for reading
HCON register suggested by Joachim.



   Ralf






--
Shawn Lin

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[RFC PATCH v1] mmc: sdhci-of-arasan: Add the support for sdhci-5.1

[Shawn Lin]

This patch adds the compatible string in sdhci-of-arasan.c to
support sdhci-arasan5.1 version of controller. No documented
controller IP version is found in the TRM, so we use ths version
of command queueing engine integrated into this controller by arasan
to specify our controller.

Signed-off-by: Shawn Lin 

---

Changes in v1:
- Remove redundant SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN for "arasan, sdhci-5.1" 
since
  SDHCI will check "host->max_clk == 0" and let driver get it from 
host->ops->get_max_clock.

 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
 drivers/mmc/host/sdhci-of-arasan.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
   - reg: From mmc bindings: Register location and length.
   - clocks: From clock bindings: Handles to clock inputs.
   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..75379cb 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -217,6 +217,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
 
 static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+   { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
 };
-- 
2.3.7


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[RFC PATCH v1] mmc: sdhci-of-arasan: Add the support for sdhci-5.1

[Shawn Lin]

This patch adds the compatible string in sdhci-of-arasan.c to
support sdhci-arasan5.1 version of controller. No documented
controller IP version is found in the TRM, so we use ths version
of command queueing engine integrated into this controller by arasan
to specify our controller.

Signed-off-by: Shawn Lin 

---

Changes in v1:
- Remove redundant SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN for "arasan, sdhci-5.1" 
since
  SDHCI will check "host->max_clk == 0" and let driver get it from 
host->ops->get_max_clock.

 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
 drivers/mmc/host/sdhci-of-arasan.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
   - reg: From mmc bindings: Register location and length.
   - clocks: From clock bindings: Handles to clock inputs.
   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..75379cb 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -217,6 +217,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
 
 static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+   { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
 };
-- 
2.3.7


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Re: [PATCH] mmc: sdhci-of-arasan: Add the support for sdhci-5.1

[Shawn Lin]

On 2015/8/11 9:14, Shawn Lin wrote:

This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan5.1 version of controller.



Sorry for wrong send-email ops, pls ignore this patch :(


Signed-off-by: Shawn Lin 
---

  Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
  drivers/mmc/host/sdhci-of-arasan.c | 4 
  2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller

  Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..c9012f5 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -175,6 +175,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+   } else if (of_device_is_compatible(pdev->dev.of_node,
+  "arasan,sdhci-5.1")) {
+   host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
}

sdhci_get_of_property(pdev);
@@ -217,6 +220,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)

  static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+   { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
  };




--
Shawn Lin
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[PATCH] mmc: sdhci-of-arasan: Add the support for sdhci-5.1

[Shawn Lin]

This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan5.1 version of controller.

Signed-off-by: Shawn Lin 
---

 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
 drivers/mmc/host/sdhci-of-arasan.c | 4 
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
 
 Required Properties:
   - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-'arasan,sdhci-4.9a'
+'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
   - reg: From mmc bindings: Register location and length.
   - clocks: From clock bindings: Handles to clock inputs.
   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
b/drivers/mmc/host/sdhci-of-arasan.c
index ef5a7d2..c9012f5 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -175,6 +175,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+   } else if (of_device_is_compatible(pdev->dev.of_node,
+  "arasan,sdhci-5.1")) {
+   host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
}
 
sdhci_get_of_property(pdev);
@@ -217,6 +220,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
 
 static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+   { .compatible = "arasan,sdhci-5.1" },
{ .compatible = "arasan,sdhci-4.9a" },
{ }
 };
-- 
2.3.7


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Re: [RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/11 2:03, Alim Akhtar 写道:

Hi Shawn

On Thu, Aug 6, 2015 at 12:14 PM, Shawn Lin  wrote:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.


Just curious to know if their are any performance (read/write)
difference with Idmac and edmac?



yes, actually the performance with edmac is worse than that does with 
idmac since other peripheral blocks(e.g:I2C/uart/i2s etc.) share generic 
DMA with it that means dw_mmc has to compete with them to request the 
free channel and be shceduled if generic DMA is busy.



Signed-off-by: Shawn Lin 

---

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
   transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

  drivers/mmc/host/Kconfig|  11 +-
  drivers/mmc/host/dw_mmc-pltfm.c |   2 +
  drivers/mmc/host/dw_mmc.c   | 258 
  include/linux/mmc/dw_mmc.h  |  27 -
  4 files changed, 232 insertions(+), 66 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
 help
   This selects support for the Synopsys DesignWare Mobile Storage IP
   block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.

  config MMC_DW_PLTFM
 tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
 tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
 depends on MMC_DW
 select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
 help
   This selects support for Hisilicon K3 SoC specific extensions to the
   Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 host->pdata = pdev->dev.platform_data;

 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
 host->regs = devm_ioremap_resource(&pdev->dev, regs);
 if (IS_ERR(host->regs))
 return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..5d6cdff 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
  #define DW_MCI_FREQ_MAX2   /* unit: HZ */
  #define DW_MCI_FREQ_MIN40  /* unit: HZ */

-#ifdef CONFIG_MMC_DW_IDMAC
+
  #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {

 __le32  des3;   /* buffer 2 physical address */
  };
-#endif /* CONFIG_MMC_DW_IDMAC */

  static bool dw_mci_reset(struct dw_mci *host);
  static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
 return DMA_FROM_DEVICE;
  }

-#ifdef CONFIG_MMC_DW_IDMAC
  static void dw_mci_dma_cleanup(struct dw_mci *host)
  {
 struct mmc_data *data = host->data;
@@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 mci_writel(host, BMOD, temp);
  }

-static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+static void dw_mci_dmac_complete_dma(void *arg)
  {
+   struct dw_mci *host = arg;
 struct mmc_data *data = 

Re: [RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/8 5:32, Joachim Eastwood 写道:

Hi Shawn,

On 6 August 2015 at 08:44, Shawn Lin  wrote:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 



@@ -2256,26 +2373,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void 
*dev_id)

 }

-#ifdef CONFIG_MMC_DW_IDMAC
-   /* Handle DMA interrupts */
-   if (host->dma_64bit_address == 1) {
-   pending = mci_readl(host, IDSTS64);
-   if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
-   mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
-   SDMMC_IDMAC_INT_RI);
-   mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
-   host->dma_ops->complete(host);
-   }
-   } else {
-   pending = mci_readl(host, IDSTS);
-   if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
-   mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
-   SDMMC_IDMAC_INT_RI);
-   mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
-   host->dma_ops->complete(host);
+   if (host->use_dma == TRANS_MODE_IDMAC) {


Doing:
if (host->use_dma != TRANS_MODE_IDMAC)
 return IRQ_HANDLED;



Okay.


Could save you the extra level of identation you add below.


+   /* Handle DMA interrupts */
+   if (host->dma_64bit_address == 1) {
+   pending = mci_readl(host, IDSTS64);
+   if (pending & (SDMMC_IDMAC_INT_TI |
+  SDMMC_IDMAC_INT_RI)) {
+   mci_writel(host, IDSTS64,
+  SDMMC_IDMAC_INT_TI |
+  SDMMC_IDMAC_INT_RI);
+   mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
+   host->dma_ops->complete((void *)host);
+   }
+   } else {
+   pending = mci_readl(host, IDSTS);
+   if (pending & (SDMMC_IDMAC_INT_TI |
+  SDMMC_IDMAC_INT_RI)) {
+   mci_writel(host, IDSTS,
+  SDMMC_IDMAC_INT_TI |
+  SDMMC_IDMAC_INT_RI);
+   mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
+   host->dma_ops->complete((void *)host);
+   }
 }
 }
-#endif

 return IRQ_HANDLED;
  }




@@ -2437,6 +2567,21 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot 
*slot, unsigned int id)
  static void dw_mci_init_dma(struct dw_mci *host)
  {
 int addr_config;
+   int trans_mode;
+   struct device *dev = host->dev;
+   struct device_node *np = dev->of_node;
+
+   /* Check tansfer mode */
+   trans_mode = (mci_readl(host, HCON) >> 16) & 0x3;


I think it would be nice if you could add some defines for 16 and 0x03
or add a macro like SDMMC_GET_FCNT() that is in dw_mmc.h.



yes, it's better to avoid magic number for register operation to make
others understand w/o checking databook for details. And might more than 
one (e.g "Check ADDR_CONFIG bit in HCON to find IDMAC address bus 
width") should be modified.


Although one patch only do one thing, I will drop by to make it in v5.


+   if (trans_mode == 0) {
+   trans_mode = TRANS_MODE_IDMAC;
+   } else if (trans_mode == 1 || trans_mode == 2) {
+   trans_mode = TRANS_MODE_EDMAC;
+   } else {
+   trans_mode = TRANS_MODE_PIO;
+   goto no_dma;
+   }
+
 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;


I'll try to get this patch tested on my lpc18xx platform soon.
btw, the HCON reg on lpc18xx reads as 0x00e42cc1 (address 0x40004070).



yes, HCON[17:16] is 2b'00 means your lpc18xx use IDMAC.



regard,
Joachim Eastwood






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Re: [RFC PATCH v4 0/9]

[Shawn Lin]

在 2015/8/6 15:08, Jaehoon Chung 写道:

Hi, Shawn.

I remembered that Krzysztof has mentioned "Fix the title of cover letter."
Your cover letter's title is nothing.. "[RFC PATCH v4 0/9] " ??
[RFC PATCH v4 0/9] your title...

 Sorry, I forgot it, and will fix in next version...


Best Regards,
Jaehoon Chung

On 08/06/2015 03:44 PM, Shawn Lin wrote:

Add external dma support for Synopsys MSHC

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
   at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc


Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
   transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (9):
   mmc: dw_mmc: Add external dma interface support
   Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
   mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
   arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
   arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

  .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 ++
  arch/arc/configs/axs101_defconfig  |   1 -
  arch/arc/configs/axs103_defconfig  |   1 -
  arch/arc/configs/axs103_smp_defconfig  |   1 -
  arch/arm/configs/exynos_defconfig  |   1 -
  arch/arm/configs/hisi_defconfig|   1 -
  arch/arm/configs/lpc18xx_defconfig |   1 -
  arch/arm/configs/multi_v7_defconfig|   1 -
  arch/arm/configs/zx_defconfig  |   1 -
  arch/mips/configs/pistachio_defconfig  |   1 -
  drivers/mmc/host/Kconfig   |  11 +-
  drivers/mmc/host/dw_mmc-pltfm.c|   2 +
  drivers/mmc/host/dw_mmc.c  | 258 +
  include/linux/mmc/dw_mmc.h         |  27 ++-
  14 files changed, 257 insertions(+), 75 deletions(-)








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Re: [RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/6 15:08, Krzysztof Kozlowski 写道:

On 06.08.2015 15:44, Shawn Lin wrote:

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
   transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter

How did you fixed the title? It is still empty :)
Subject: [RFC PATCH v4 0/9]

  I mentioned that in ChangeLog-v4 but unfortunately I forgot it.
  Thanks, Krzysztof.  I will be more careful and add it for next version.




- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

  drivers/mmc/host/Kconfig|  11 +-
  drivers/mmc/host/dw_mmc-pltfm.c |   2 +
  drivers/mmc/host/dw_mmc.c   | 258 
  include/linux/mmc/dw_mmc.h  |  27 -
  4 files changed, 232 insertions(+), 66 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
  
  config MMC_DW_PLTFM

tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
  
  	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);

+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..5d6cdff 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
  #define DW_MCI_FREQ_MAX   2   /* unit: HZ */
  #define DW_MCI_FREQ_MIN   40  /* unit: HZ */
  
-#ifdef CONFIG_MMC_DW_IDMAC

+
  #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {
  
  	__le32		des3;	/* buffer 2 physical address */

  };
-#endif /* CONFIG_MMC_DW_IDMAC */
  
  static bool dw_mci_reset(struct dw_mci *host);

  static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
  }
  
-#ifdef CONFIG_MMC_DW_IDMAC

  static void dw_mci_dma_cleanup(struct dw_mci *host)
  {
struct mmc_data *data = host->data;
@@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
mci_writel(host, BMOD, temp);
  }
  
-static void dw_mci_idmac_complete_dma(struct dw_mci *host)

+static void dw_mci_dmac_complete_dma(void *arg)
  {
+   struct dw_mci *host = arg;

Why changing the argument to void*?


This function will be used as callback hook of dmaengine, and the 
prototype is

"typedef void (*dma_async_tx_callback)(void *dma_async_param);".
w/o this change, we m

[RFC PATCH v4 7/9] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/lpc18xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/lpc18xx_defconfig 
b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
-- 
2.3.7


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[RFC PATCH v4 6/9] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/hisi_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
-- 
2.3.7


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[RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin 

---

Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig|  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c   | 258 
 include/linux/mmc/dw_mmc.h  |  27 -
 4 files changed, 232 insertions(+), 66 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
  This selects support for the Synopsys DesignWare Mobile Storage IP
  block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-   bool "Internal DMAC interface"
-   depends on MMC_DW
-   help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
 
 config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
-   select MMC_DW_IDMAC
help
  This selects support for Hisilicon K3 SoC specific extensions to the
  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   /* Get registers' physical base address */
+   host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..5d6cdff 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
 #define DW_MCI_FREQ_MAX2   /* unit: HZ */
 #define DW_MCI_FREQ_MIN40  /* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
+
 #define IDMAC_INT_CLR  (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {
 
__le32  des3;   /* buffer 2 physical address */
 };
-#endif /* CONFIG_MMC_DW_IDMAC */
 
 static bool dw_mci_reset(struct dw_mci *host);
 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
 }
 
-#ifdef CONFIG_MMC_DW_IDMAC
 static void dw_mci_dma_cleanup(struct dw_mci *host)
 {
struct mmc_data *data = host->data;
@@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
mci_writel(host, BMOD, temp);
 }
 
-static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+static void dw_mci_dmac_complete_dma(void *arg)
 {
+   struct dw_mci *host = arg;
struct mmc_data *data = host->data;
 
dev_vdbg(host->dev, "DMA complete\n");
 
+   if (host->use_dma == TRANS_MODE_EDMAC)
+   if (data && (data->flags & MMC_DATA_READ))
+   /* Invalidate cache after read */
+   dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
+   data->sg,
+   data->sg_len,
+   DMA_FROM_DEVICE);

[RFC PATCH v4 8/9] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..a3734b5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
-- 
2.3.7


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[RFC PATCH v4 9/9] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/zx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7


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[RFC PATCH v4 5/9] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/configs/exynos_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 9504e77..7e4af6e 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
-- 
2.3.7


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[RFC PATCH v4 2/9] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 25 ++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+  Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
 
+[board specific internal DMA resources]
+
+   dwmmc0@1220 {
+   clock-frequency = <4>;
+   clock-freq-min-max = <40 2>;
+   num-slots = <1>;
+   broken-cd;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   vmmc-supply = <&buck8>;
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+   dmas = <&pdma 12>;
+   dma-names = "rx-tx";
};
-- 
2.3.7


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[RFC PATCH v4 4/9] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig | 1 -
 arch/arc/configs/axs103_defconfig | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig 
b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig 
b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig 
b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
-- 
2.3.7


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[RFC PATCH v4 3/9] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.

Signed-off-by: Shawn Lin 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig 
b/arch/mips/configs/pistachio_defconfig
index 1646cce..013c62c 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7


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[RFC PATCH v4 0/9]

[Shawn Lin]

Add external dma support for Synopsys MSHC

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched since
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode by reading
dw_mmc's HCON reg at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc


Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
  transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (9):
  mmc: dw_mmc: Add external dma interface support
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  25 ++
 arch/arc/configs/axs101_defconfig  |   1 -
 arch/arc/configs/axs103_defconfig  |   1 -
 arch/arc/configs/axs103_smp_defconfig  |   1 -
 arch/arm/configs/exynos_defconfig  |   1 -
 arch/arm/configs/hisi_defconfig|   1 -
 arch/arm/configs/lpc18xx_defconfig |   1 -
 arch/arm/configs/multi_v7_defconfig|   1 -
 arch/arm/configs/zx_defconfig  |   1 -
 arch/mips/configs/pistachio_defconfig  |   1 -
 drivers/mmc/host/Kconfig   |  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c|   2 +
 drivers/mmc/host/dw_mmc.c  | 258 +
 include/linux/mmc/dw_mmc.h |  27 ++-
 14 files changed, 257 insertions(+), 75 deletions(-)

-- 
2.3.7


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Re: [PATCH v2] mmc: sunxi: Don't start commands while the card is busy

[Shawn Lin]

在 2015/7/29 3:22, Arend van Spriel 写道:

On 07/21/2015 02:15 PM, Ulf Hansson wrote:

On 10 July 2015 at 17:14, Hans de Goede  wrote:

Some sdio wifi modules have not been working reliable with the sunxi-mmc
host code. This turns out to be caused by it starting new commands while
the card signals that it is still busy processing a previous command.


Which are those commands? Or more interesting, which response types do
these commands expect?
I don't think this is a sunxi specific issue, I have seen similar
issues for other host controllers.


Indeed. A similar fix was needed for dw_mmc host controller.
bit 10 in STATUS register of sysnopsys dw_mmc should be issued each time 
you start a new cmd. It's hard to say whetehr a local hack or not, 
because it's a mandatory requirement from IP databook(refer to 
"Sysnopsys DesignWare cores Mobile Storage Host Databook" Chapter 7- 
Programming the DWC_mobile_storage).


Bit 10: indicate state-machine is ready, controller MUST guarantee all
I/O used in "free state", actually high.

If dw_mmc's state-machine isn't ready, NO cmd can be issued, which means 
even we configure cmd and cmdarg, start bit cannot be auto-clean by 
controller that leads to no cmd_done interrupt generated which dw_mmc's 
tasklet state-machine need.





I am thinking that perhaps this should be managed by the mmc core
instead of local hacks to sunxi. Potentially we could make the core to
invoke the already existing host_ops->card_busy() callback when
needed...


The problem here is that there are a number of host controllers out
there not implementing that callback. That may be because the hardware
is dealing properly with busy signalling, but I would not bet on that.

Regards,
Arend


Within this context, could I ask whether you controller supports IRQ
based HW-busy detection? Or you need polling of the status register?



This commit fixes this, thereby fixing the wifi reliability issues on
the Cubietruck and other sunxi boards using sdio wifi.

Reported-by: Eugene K 
Suggested-by: Eugene K 
Cc: Eugene K 
Cc: Arend van Spriel 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Properly accredit Eugene K for coming up with the fix for this
---
  drivers/mmc/host/sunxi-mmc.c | 32 
  1 file changed, 32 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 4d3e1ff..daa90b7 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -289,6 +289,24 @@ static int sunxi_mmc_init_host(struct mmc_host
*mmc)
 return 0;
  }

+/* Wait for card to report ready before starting a new cmd */
+static int sunxi_mmc_wait_card_ready(struct sunxi_mmc_host *host)
+{
+   unsigned long expire = jiffies + msecs_to_jiffies(500);
+   u32 rval;
+
+   do {
+   rval = mmc_readl(host, REG_STAS);
+   } while (time_before(jiffies, expire) && (rval &
SDXC_CARD_DATA_BUSY));
+
+   if (rval & SDXC_CARD_DATA_BUSY) {
+   dev_err(mmc_dev(host->mmc), "Error R1 ready timeout\n");
+   return -EIO;
+   }
+
+   return 0;
+}
+
  static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 struct mmc_data *data)
  {
@@ -383,6 +401,8 @@ static void sunxi_mmc_send_manual_stop(struct
sunxi_mmc_host *host,
 u32 arg, cmd_val, ri;
 unsigned long expire = jiffies + msecs_to_jiffies(1000);

+   sunxi_mmc_wait_card_ready(host);
+
 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
   SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;

@@ -597,6 +617,11 @@ static int sunxi_mmc_oclk_onoff(struct
sunxi_mmc_host *host, u32 oclk_en)
  {
 unsigned long expire = jiffies + msecs_to_jiffies(250);
 u32 rval;
+   int ret;
+
+   ret = sunxi_mmc_wait_card_ready(host);
+   if (ret)
+   return ret;

 rval = mmc_readl(host, REG_CLKCR);
 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
@@ -785,6 +810,13 @@ static void sunxi_mmc_request(struct mmc_host
*mmc, struct mmc_request *mrq)
 return;
 }

+   ret = sunxi_mmc_wait_card_ready(host);
+   if (ret) {
+   mrq->cmd->error = ret;
+   mmc_request_done(mmc, mrq);
+   return;
+   }
+
 if (data) {
 ret = sunxi_mmc_map_dma(host, data);
 if (ret < 0) {
--
2.4.3



Kind regards
Uffe



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Shawn Lin

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