Re: [PATCH v7 06/14] drm/mediatek: Add HDMI support
On Mon, 2015-11-30 at 22:07 +0100, Philipp Zabel wrote:
> From: Jie Qiu
>
> This patch adds drivers for the HDMI bridge connected to the DPI0
> display subsystem function block, for the HDMI DDC block, and for
> the HDMI PHY to support HDMI output.
>
> Signed-off-by: Jie Qiu
> Signed-off-by: Philipp Zabel
> ---
<...>
> +static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
> + struct drm_display_mode *mode)
> +{
> + struct hdmi_avi_infoframe frame;
> + u8 buffer[17];
> + ssize_t err;
> +
> + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
> + if (err < 0) {
> + dev_err(hdmi->dev,
> + "Failed to get AVI infoframe from mode: %ld\n", err);
Please use %zd instead for ssize_t, otherwise you'll see warning message
when compile this on 32bits platform.
Joe.C
> + return err;
> + }
> +
> + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
> + if (err < 0) {
> + dev_err(hdmi->dev, "Failed to pack AVI infoframe: %ld\n", err);
> + return err;
> + }
> +
> + mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
> + return 0;
> +}
> +
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Re: [PATCH v3 4/5] pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for mt2701
On Mon, 2015-12-28 at 15:09 +0800, Biao Huang wrote:
> Add mt2701 support using mediatek common pinctrl driver.
> MT2701 have some special pins need an extra setting register
> than other ICs, so adding this support to common code.
>
> Signed-off-by: Biao Huang
> Acked-by: Yingjoe Chen
<...>
> +
> +static struct platform_driver mtk_pinctrl_driver = {
> + .probe = mt2701_pinctrl_probe,
> + .driver = {
> + .name = "mediatek-mt2701-pinctrl",
> + .owner = THIS_MODULE,
> + .of_match_table = mt2701_pctrl_match,
> + },
> +};
> +
> +static int __init mtk_pinctrl_init(void)
> +{
> + return platform_driver_register(&mtk_pinctrl_driver);
> +}
> +
> +arch_initcall(mtk_pinctrl_init);
As discussed in
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003350.html
we should use subsys_initcall() instead.
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> index f307f1d..76279f0 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
<...>
> @@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev
> *pctldev,
> ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
> break;
> case PIN_CONFIG_INPUT_ENABLE:
> + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
> ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
> break;
> case PIN_CONFIG_OUTPUT:
> @@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev
> *pctldev,
> ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
> break;
> case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
> ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
> break;
> case PIN_CONFIG_DRIVE_STRENGTH:
This change is not directly related to adding mt2710 support and change
behavior for all MTK pinctrl drivers, please create a separate patch for
this.
Joe.C
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Re: [PATCH v2 4/5] pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for mt2701
On Fri, 2015-12-11 at 17:07 +0800, Biao Huang wrote:
> Add mt2701 support using mediatek common pinctrl driver.
> MT2701 have some special pins need an extra setting register
> than other ICs, so adding this support to common code.
>
> Signed-off-by: Biao Huang
> ---
> drivers/pinctrl/mediatek/Kconfig |6 +
> drivers/pinctrl/mediatek/Makefile |1 +
> drivers/pinctrl/mediatek/pinctrl-mt2701.c | 590 +++
> drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 +
> drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +-
> drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h | 2323
> +
> 6 files changed, 2945 insertions(+), 1 deletion(-)
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
This patch looks good to me.
Thanks
Acked-by: Yingjoe Chen
Joe.C
>
> diff --git a/drivers/pinctrl/mediatek/Kconfig
> b/drivers/pinctrl/mediatek/Kconfig
> index 02f6f92..13e9939 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
> select OF_GPIO
>
> # For ARMv7 SoCs
> +config PINCTRL_MT2701
> + bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
> + depends on OF
> + default MACH_MT2701
> + select PINCTRL_MTK_COMMON
> +
> config PINCTRL_MT8135
> bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
> depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile
> b/drivers/pinctrl/mediatek/Makefile
> index eb923d6..da30314 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
>
> # SoC Drivers
> +obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
> obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
> obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
> obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> new file mode 100644
> index 000..5eb1b52
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> @@ -0,0 +1,590 @@
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + * Author: Biao Huang
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-mtk-common.h"
> +#include "pinctrl-mtk-mt2701.h"
> +
> +/**
> + * struct mtk_spec_pinmux_set
> + * - For special pins' mode setting
> + * @pin: The pin number.
> + * @offset: The offset of extra setting register.
> + * @bit: The bit of extra setting register.
> + */
> +struct mtk_spec_pinmux_set {
> + unsigned short pin;
> + unsigned short offset;
> + unsigned char bit;
> +};
> +
> +#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
> + { \
> + .pin = _pin,\
> + .offset = _offset, \
> + .bit = _bit,\
> + }
> +
> +static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
> + /* 0E4E8SR 4/8/12/16 */
> + MTK_DRV_GRP(4, 16, 1, 2, 4),
> + /* 0E2E4SR 2/4/6/8 */
> + MTK_DRV_GRP(2, 8, 1, 2, 2),
> + /* E8E4E2 2/4/6/8/10/12/14/16 */
> + MTK_DRV_GRP(2, 16, 0, 2, 2)
> +};
> +
> +static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
> + MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
> + MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
> + MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
> + MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
> + MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
> + MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
> + MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
> + MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
> + MTK_
Re: [PATCH v8 2/2] arm64: dts: mt8173: Add nor flash node
On Wed, 2015-11-25 at 11:50 +0100, Matthias Brugger wrote:
>
> On 18/11/15 04:30, Bayi Cheng wrote:
> > Add Mediatek nor flash node
> >
> > Signed-off-by: Bayi Cheng
> > Acked-by: Brian Norris
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +-
> > 1 file changed, 17 insertions(+), 1 deletion(-)
> >
>
> Applied to v4.5-next/dts
>
> Thanks.
> Matthias
>
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 4dd5f93..7988656 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -387,7 +387,23 @@
> > status = "disabled";
> > };
> >
> > - i2c3: i2c@1101 {
> > + nor_flash: spi@1100d000 {
> > + compatible = "mediatek,mt8173-nor";
> > + reg = <0 0x1100d000 0 0xe0>;
> > + clocks = <&pericfg CLK_PERI_SPI>,
> > +<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> > + clock-names = "spi", "sf";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > +
> > + flash@0 {
> > + compatible = "jedec,spi-nor";
> > + reg = <0>;
> > + };
> > + };
> > +
> > + i2c3: i2c3@1101 {
Hi Matthias,
Just notice this one. Please make sure this line should be
i2c3: i2c@1101 {
instead of
i2c3: i2c3@1101 {
Joe.C
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Re: [PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Mon, 2015-10-26 at 09:56 +0900, Kevin Hilman wrote: > Hello, > > On Sat, Oct 3, 2015 at 12:19 AM, Yingjoe Chen > wrote: > > Add arch timer node to enable arch-timer support. MT8135 firmware > > doesn't correctly setup arch-timer frequency and CNTVOFF, add > > properties to workaround this. > > > > This also set cpu enable-method to enable SMP. > > > > Signed-off-by: Yingjoe Chen > > kernelci.org started detecting new boot failures for the mt8135-evb in > the arm-soc tree[1], and the boot failures were bisected down to this > patch, which landed upstream in the form of commit d186a394bb98 (ARM: > dts: mt8135: enable basic SMP bringup for mt8135) > > Maybe this new SMP support requires updating the firmware on the board > as well? If so, the changelog should've been a bit more explicit > about firmware dependencies. Kevin, Thanks for testing. No, it doesn't need new firmware. Will test to see what's going wrong. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/5] Add SMP bringup support for mt65xx socs
This series add SMP brinup support for MediaTek SoCs. This is v5 and is based on v4.3-rc1. There are similar but different SMP bringup up methods on MediaTek mt65xx and mt81xx. On MT8135 & MT8127, system boots with a trustzone firmware. Others, like MT6589, doesn't have trustzone, and run kernel directly in secure world. Patch 1 enable arch timer support. Patch 2,3 add support for cpu enable-method "mediatek,mt6589-smp" and "mediatek,mt81xx-tz-smp", which support Mediatek SMP bringup for non-TZ and TZ platform. Patch 4,5 finally enable SMP bringup for mt8135 and mt8127. Changes in v5: - Fix dts error - Add Rob's Ack tag. Changes in v4[3]: - rebase to v4.3-rc1 - Reserve trustzone bootinfo memory area in device tree. Changes in v3: - v3 in [1] - The first 2 patches in v2 are merged in v4.2-rc1. - Patch 3~4 in v2 are moved to another series [2] - platsmp.c changes based on Stephen's suggestion - Change cpu enable-method name to "mediatek,mt6589-smp" Changes in v2: - Fix boot issue for THUMB2 kernel. - Not enable GPT_CLK_EVT when setup to fix GPT spurious interrupt issue - Change platsmp.c according to Matthias' suggestion http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000714.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000528.html [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001570.html [2] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001544.html [3] http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002377.html Matthias Brugger (1): ARM: mediatek: enable gpt6 on boot up to make arch timer working Yingjoe Chen (4): devicetree: bindings: add new SMP enable method Mediatek SoC ARM: mediatek: add smp bringup code ARM: dts: mt8135: enable basic SMP bringup for mt8135 ARM: dts: mt8127: enable basic SMP bringup for mt8127 Documentation/devicetree/bindings/arm/cpus.txt | 2 + arch/arm/boot/dts/mt8127.dtsi | 27 + arch/arm/boot/dts/mt8135.dtsi | 27 + arch/arm/mach-mediatek/Makefile| 3 + arch/arm/mach-mediatek/mediatek.c | 27 + arch/arm/mach-mediatek/platsmp.c | 141 + 6 files changed, 227 insertions(+) create mode 100644 arch/arm/mach-mediatek/platsmp.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
Add arch timer node to enable arch-timer support. MT8135 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8135.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 08371db..cb99b02 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -46,6 +46,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu0: cpu@0 {
device_type = "cpu";
@@ -72,6 +73,17 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ trustzone-bootinfo@80002000 {
+ compatible = "mediatek,trustzone-bootinfo";
+ reg = <0 0x80002000 0 0x1000>;
+ };
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -97,6 +109,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.9.1
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[PATCH v5 1/5] ARM: mediatek: enable gpt6 on boot up to make arch timer working
From: Matthias Brugger
We enable GTP6 which ungates the arch timer clock.
In the future this should be done in the bootloader.
Signed-off-by: Matthias Brugger
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/mediatek.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/mach-mediatek/mediatek.c
b/arch/arm/mach-mediatek/mediatek.c
index a954900..19dc738 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -16,6 +16,32 @@
*/
#include
#include
+#include
+#include
+#include
+
+
+#define GPT6_CON_MT65xx 0x10008060
+#define GPT_ENABLE 0x31
+
+static void __init mediatek_timer_init(void)
+{
+ void __iomem *gpt_base;
+
+ if (of_machine_is_compatible("mediatek,mt6589") ||
+ of_machine_is_compatible("mediatek,mt8135") ||
+ of_machine_is_compatible("mediatek,mt8127")) {
+ /* turn on GPT6 which ungates arch timer clocks */
+ gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
+
+ /* enable clock and set to free-run */
+ writel(GPT_ENABLE, gpt_base);
+ iounmap(gpt_base);
+ }
+
+ of_clk_init(NULL);
+ clocksource_of_init();
+};
static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
@@ -27,4 +53,5 @@ static const char * const mediatek_board_dt_compat[] = {
DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
.dt_compat = mediatek_board_dt_compat,
+ .init_time = mediatek_timer_init,
MACHINE_END
--
1.9.1
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[PATCH v5 2/5] devicetree: bindings: add new SMP enable method Mediatek SoC
This commit add new cpu enable method "mediatek,mt65xx-smp" and "mediatek,mt81xx-tz-smp". Acked-by: Rob Herring Signed-off-by: Yingjoe Chen --- Documentation/devicetree/bindings/arm/cpus.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91e6e5c..3a07a87 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -195,6 +195,8 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6589-smp" + "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/5] ARM: mediatek: add smp bringup code
Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/Makefile | 3 +
arch/arm/mach-mediatek/platsmp.c | 141 +++
2 files changed, 144 insertions(+)
create mode 100644 arch/arm/mach-mediatek/platsmp.c
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 43e619f..2116460 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1 +1,4 @@
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
+endif
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
new file mode 100644
index 000..8141f3f
--- /dev/null
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -0,0 +1,141 @@
+/*
+ * arch/arm/mach-mediatek/platsmp.c
+ *
+ * Copyright (c) 2014 Mediatek Inc.
+ * Author: Shunli Wang
+ * Yingjoe Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_MAX_CPU8
+#define MTK_SMP_REG_SIZE 0x1000
+
+struct mtk_smp_boot_info {
+ unsigned long smp_base;
+ unsigned int jump_reg;
+ unsigned int core_keys[MTK_MAX_CPU - 1];
+ unsigned int core_regs[MTK_MAX_CPU - 1];
+};
+
+static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {
+ 0x80002000, 0x3fc,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x3f8, 0x3f8, 0x3f8 },
+};
+
+static const struct mtk_smp_boot_info mtk_mt6589_boot = {
+ 0x10002000, 0x34,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x38, 0x3c, 0x40 },
+};
+
+static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
+ { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
+};
+
+static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
+};
+
+static void __iomem *mtk_smp_base;
+static const struct mtk_smp_boot_info *mtk_smp_info;
+
+static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ if (!mtk_smp_base)
+ return -EINVAL;
+
+ if (!mtk_smp_info->core_keys[cpu-1])
+ return -EINVAL;
+
+ writel_relaxed(mtk_smp_info->core_keys[cpu-1],
+ mtk_smp_base + mtk_smp_info->core_regs[cpu-1]);
+
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ return 0;
+}
+
+static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
+{
+ int i, num;
+ const struct of_device_id *infos;
+
+ if (trustzone) {
+ num = ARRAY_SIZE(mtk_tz_smp_boot_infos);
+ infos = mtk_tz_smp_boot_infos;
+ } else {
+ num = ARRAY_SIZE(mtk_smp_boot_infos);
+ infos = mtk_smp_boot_infos;
+ }
+
+ /* Find smp boot info for this SoC */
+ for (i = 0; i < num; i++) {
+ if (of_machine_is_compatible(infos[i].compatible)) {
+ mtk_smp_info = infos[i].data;
+ break;
+ }
+ }
+
+ if (!mtk_smp_info) {
+ pr_err("%s: Device is not supported\n", __func__);
+ return;
+ }
+
+ if (trustzone) {
+ /* smp_base(trustzone-bootinfo) is reserved by device tree */
+ mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);
+ } else {
+ mtk_smp_base = ioremap(mtk_smp_info->smp_base,
MTK_SMP_REG_SIZE);
+ if (!mtk_smp_base) {
+ pr_err("%s: Can't remap %lx\n", __func__,
+ mtk_smp_info->smp_base);
+ return;
+ }
+ }
+
+ /*
+* write the address of slave startup address into the system-wide
+* jump register
+*/
+ writel_relaxed(virt_to_phys(secondary_startup_arm),
+ mtk_smp_base + mtk_smp_info->jump_reg);
+}
+
+static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpus(max_cpus, 1);
+}
+
+static void __init mtk_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpus(max_cpus, 0);
+}
+
+static struct smp_operations mt81xx_tz_smp_ops __initdata = {
+ .smp_prepare_cpus = mtk_tz_smp_prepare_cpus,
+ .smp_boot
[PATCH v5 5/5] ARM: dts: mt8127: enable basic SMP bringup for mt8127
Add arch timer node to enable arch-timer support. MT8127 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8127.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index ca3402e..52086c8 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu@0 {
device_type = "cpu";
@@ -47,6 +48,17 @@
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ trustzone-bootinfo@80002000 {
+ compatible = "mediatek,trustzone-bootinfo";
+ reg = <0 0x80002000 0 0x1000>;
+ };
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -72,6 +84,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.9.1
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[PATCH v4 1/3] dt-bindings: add more MediaTek SoC to mtk-timer binding
Add compatible string for mt8127, mt8135 and mt8173 and sort the list. Signed-off-by: Yingjoe Chen --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 53a3029..64083bc 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -3,10 +3,12 @@ Mediatek MT6577, MT6572 and MT6589 Timers Required properties: - compatible should contain: - * "mediatek,mt6589-timer" for MT6589 compatible timers * "mediatek,mt6580-timer" for MT6580 compatible timers - * "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580, - MT6577) + * "mediatek,mt6589-timer" for MT6589 compatible timers + * "mediatek,mt8127-timer" for MT8127 compatible timers + * "mediatek,mt8135-timer" for MT8135 compatible timers + * "mediatek,mt8173-timer" for MT8173 compatible timers + * "mediatek,mt6577-timer" for MT6577 and all above compatible timers - reg: Should contain location and length for timers register. - clocks: Clocks driving the timer hardware. This list should include two clocks. The order is system clock and as second clock the RTC clock. -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/3] arm64: dts: mt8173: add timer node
From: Daniel Kurtz
Add device node to enable GPT timer.
Signed-off-by: Daniel Kurtz
Signed-off-by: Eddie Huang
Signed-off-by: Yingjoe Chen
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..d763803 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -238,6 +238,15 @@
reg = <0 0x10007000 0 0x100>;
};
+ timer: timer@10008000 {
+ compatible = "mediatek,mt8173-timer",
+"mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CLK_13M>,
+<&topckgen CLK_TOP_RTC_SEL>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8173-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
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[PATCH v4 2/3] arm64: mediatek: enable MTK_TIMER
Enable MTK_TIMER for MediaTek plaform, which will be used as tick broadcast device and schedule clock. Signed-off-by: Yingjoe Chen --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 23800a1..8176455 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -42,6 +42,7 @@ config ARCH_MEDIATEK bool "Mediatek MT65xx & MT81xx ARMv8 SoC" select ARM_GIC select PINCTRL + select MTK_TIMER help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] add GPT timer support for mt8173
On Fri, 2015-10-02 at 23:05 +0800, Yingjoe Chen wrote: > This is based on v4.3-rc1 + clockevents-4.4[1] and James's mediatek-clk > tree[2]. > > Changes compare to previous version[3]: > - Add more MediaTek SoC to mtk-timer binding > - Update commit message to better describe the purpose. > > Changes compare to v2[4]: > - the first two mtk_timer related changes are removed because they are > replaced/accepted in clockevents tree. > - Remove 'add 13mhz clock for MT8173' because it is accepted in > mediatek-clk tree. > - Kconfig.platforms path change. Hi Sudeep, Mark, I just post a new version of this patch. Sorry I forgot to CC you. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/3] add GPT timer support for mt8173
This is based on v4.3-rc1 + clockevents-4.4[1] and James's mediatek-clk tree[2]. Changes compare to previous version[3]: - Add more MediaTek SoC to mtk-timer binding - Update commit message to better describe the purpose. Changes compare to v2[4]: - the first two mtk_timer related changes are removed because they are replaced/accepted in clockevents tree. - Remove 'add 13mhz clock for MT8173' because it is accepted in mediatek-clk tree. - Kconfig.platforms path change. [1] https://git.linaro.org/people/daniel.lezcano/linux.git clockevents/4.4 [2] http://lists.infradead.org/pipermail/linux-mediatek/2015-August/002069.html [3] http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002301.html [4] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001544.html Daniel Kurtz (1): arm64: dts: mt8173: add timer node Yingjoe Chen (2): dt-bindings: add more MediaTek SoC to mtk-timer binding arm64: mediatek: enable MTK_TIMER Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 8 +--- arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 + 3 files changed, 15 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm64: dts: mt8173: add timer node
On Thu, 2015-10-01 at 16:32 +0100, Sudeep Holla wrote: > > On 01/10/15 15:33, Yingjoe Chen wrote: > > On Thu, 2015-09-17 at 17:13 +0100, Sudeep Holla wrote: > >> > > [...] > > >> > >> I think your are confusing the system counter with arch timers. System > >> counter is always-on, but the arch timers(logic implementing timers > >> comparators) might not be off when the processor is powered down. > >> > >> I think you need this timer and are using it for low power idle states > >> in which case you will use this as a clock event and not clock source. > >> It will be used as a hardware broadcast event source. > >> > >> There's no call to sched_clock_register in mtk_timer.c, so it can't be > >> the sched clock, so you need to fix the commit log. > > > > Hi Sudeep, > > > > Sorry for late reply. > > > > For sched_clock_register, please see > > http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001547.html > > which was accepted in > > https://git.linaro.org/people/daniel.lezcano/linux.git/shortlog/refs/heads/clockevents/4.4 > > > > The commit message makes no sense to me. The counters should continue to > work as long as they are in always-on domain. Only timers are lost > when you enter deeper idle states. So I agree with using MTK timer as > broadcast timer/eventsource. You still didn't answer what's the need > to use MTK timer as sched clocksource ? Hi, Sudeep, ARM ARM said the counter should be in always-on domain, but unfortunately that not true for mt8173. The last CPU enter idle can choose to enter deep idle mode and the counter value would be lost. Our firmware backup/recover the counter so it looks like it is stopped. That's why I thought we need to use it as sched clocksource. On mt8173, we will fix the firmware to add missing counts, so it will looks like the counter keep counting. But other mediatek platform have similar issue, and the 2 counter have same resolution, so I still want to keep using GPT as sched clocksource. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm64: dts: mt8173: add timer node
On Thu, 2015-09-17 at 17:41 +0100, Mark Rutland wrote: > On Thu, Sep 17, 2015 at 03:56:56PM +0100, Yingjoe Chen wrote: > > On Thu, 2015-09-17 at 14:51 +0100, Sudeep Holla wrote: > > > > > > On 16/09/15 03:04, Yingjoe Chen wrote: > > > > From: Daniel Kurtz > > > > > > > > Add device node to enable GPT timer. This timer will be > > > > used as sched clock source. > > > > > > > > > > Interesting any known issues with or advantage over the arch timers > > > to prefer it as sched clock source. I see even arch timers are present > > > in DT, hence the question. Or is it just a incorrect commit log ? > > > > > > How does this get selected as sched clock source ? I don't see > > > sched_clock_register in mtk_timer.c > > > > > > To be clear, I am not against adding this timer support, but just want > > > to know is it preferred for sched clock source ? if yes why ? better > > > resolution ? > > > > Hi Sudeep, > > > > Thanks for your review. > > > > I hit the send too soon and missed cover letter, please see: > > http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002303.html > > > > The main reason to use GPT as sched clock is it won't stop during idle. > > You don't mean sched clock, you just mean a clock_event_device. > > A sched_clock is a high-precision clocksource that is read from (which > by definition requires the CPUs to be non-idle). It doesn't have > anything to do with interrupts and therefore cannot wake devices from > idle. > > While the clock_event_device for the generic timer can't necessarily > wake CPUs from idle. The generic timer system counter counts even if > CPUs are idle, so the generic timer is fine as a sched_clock. Hi, Mark, Thanks for your info and sorry for late reply. I notice ARM ARM said the arch timer shouldn't stop when idle, but unfortunately that not true for mt8173. The last CPU enter idle can choose to enter deep idle mode and the counter value would be lost. Our firmware backup/recover the counter so it looks like it is stopped. We will change the firmware to add missing count when back from deep idle to make it looks like the counter never stop. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm64: dts: mt8173: add timer node
On Thu, 2015-09-17 at 17:13 +0100, Sudeep Holla wrote:
>
> On 17/09/15 15:56, Yingjoe Chen wrote:
> > On Thu, 2015-09-17 at 14:51 +0100, Sudeep Holla wrote:
> >>
> >> On 16/09/15 03:04, Yingjoe Chen wrote:
> >>> From: Daniel Kurtz
> >>>
> >>> Add device node to enable GPT timer. This timer will be
> >>> used as sched clock source.
> >>>
> >>
> >> Interesting any known issues with or advantage over the arch timers
> >> to prefer it as sched clock source. I see even arch timers are present
> >> in DT, hence the question. Or is it just a incorrect commit log ?
> >>
> >> How does this get selected as sched clock source ? I don't see
> >> sched_clock_register in mtk_timer.c
> >>
> >> To be clear, I am not against adding this timer support, but just want
> >> to know is it preferred for sched clock source ? if yes why ? better
> >> resolution ?
> >
> > Hi Sudeep,
> >
> > Thanks for your review.
> >
> > I hit the send too soon and missed cover letter, please see:
> > http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002303.html
> >
>
> OK
>
> > The main reason to use GPT as sched clock is it won't stop during idle.
> >
> >
>
> I think your are confusing the system counter with arch timers. System
> counter is always-on, but the arch timers(logic implementing timers
> comparators) might not be off when the processor is powered down.
>
> I think you need this timer and are using it for low power idle states
> in which case you will use this as a clock event and not clock source.
> It will be used as a hardware broadcast event source.
>
> There's no call to sched_clock_register in mtk_timer.c, so it can't be
> the sched clock, so you need to fix the commit log.
Hi Sudeep,
Sorry for late reply.
For sched_clock_register, please see
http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001547.html
which was accepted in
https://git.linaro.org/people/daniel.lezcano/linux.git/shortlog/refs/heads/clockevents/4.4
You are right it is also used as clock event. I think we don't need to
mention those detail in commit message, so I'll change to just:
"Add device node to enable GPT timer."
>
> [...]
>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> index d18ee42..d763803 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> @@ -238,6 +238,15 @@
> >>> reg = <0 0x10007000 0 0x100>;
> >>> };
> >>>
> >>> + timer: timer@10008000 {
> >>> + compatible = "mediatek,mt8173-timer",
> >>
> >> Missing documentation ? I am referring upstream and it might be in some
> >> patches already queued perhaps ?
> >
> > This is documented in
> > Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt.
> > Do you mean I should add "mediatek,mt8173-timer" to that file?
> >
>
> Yes
Will do in next round.
Thanks
Joe.C
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Re: [PATCH v4 3/5] ARM: mediatek: add smp bringup code
On Sat, 2015-09-26 at 10:38 +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 24, 2015 at 11:38:58PM +0800, Yingjoe Chen wrote:
> > +struct mtk_smp_boot_info {
> > + unsigned long smp_base;
> ...
> > +static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {
> > + 0x80002000, 0x3fc,
> ...
> > +static const struct mtk_smp_boot_info mtk_mt6589_boot = {
> > + 0x10002000, 0x34,
> ...
> > + if (trustzone) {
> > + /* smp_base(trustzone-bootinfo) is reserved by device tree */
> > + mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);
>
> I can't say whether this is correct or not, as we've got rid of most of
> the information that would allow me to make that decision.
>
> The address passed to phys_to_virt() _must_ be one which is mapped by
> the kernel as lowmem. I've no idea if the above would fall into that
> category though.
>
Currently only mt8127/mt8135 trustzone firmware use this reserve
location. The reserved memory is before kernel code, so it will
definitely in lowmem.
Joe.C
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Re: [PATCH v4 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Thu, 2015-09-24 at 23:38 +0800, Yingjoe Chen wrote:
> Add arch timer node to enable arch-timer support. MT8135 firmware
> doesn't correctly setup arch-timer frequency and CNTVOFF, add
> properties to workaround this.
>
> This also set cpu enable-method to enable SMP.
>
> Signed-off-by: Yingjoe Chen
> ---
> arch/arm/boot/dts/mt8135.dtsi | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
> index 08371db..c3c90f2 100644
> --- a/arch/arm/boot/dts/mt8135.dtsi
> +++ b/arch/arm/boot/dts/mt8135.dtsi
> @@ -46,6 +46,7 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> + enable-method = "mediatek,mt81xx-tz-smp";
>
> cpu0: cpu@0 {
> device_type = "cpu";
> @@ -72,6 +73,17 @@
> };
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + trustzone-bootinfo: trustzone-bootinfo@80002000 {
Sorry, this should be
+ trustzone-bootinfo@80002000 {
I'll fix this in next version.
Joe.C
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Re: [PATCH v3 0/5] Add SMP bringup support for mt65xx socs
On Fri, 2015-08-07 at 18:50 +0800, Yingjoe Chen wrote: > On Wed, 2015-08-05 at 23:31 +0100, Russell King - ARM Linux wrote: > > The problem is that this patch series uses memblock_reserve() way after > > the memory has been transitioned out of memblock's control, so actually > > this has no effect. > > > > I've seen a number of patches doing this. I'm not sure what's soo friggin > > hard for people to understand: memblock is about the EARLY stages of > > getting the system up and running. Once the memory has been handed > > over to the kernel's memory management, memblock MUST NOT BE USED to > > reserve memory. > > > > There is one place, and one place only in the ARM kernel where > > memblock_reserve() is possible, and that's in the ->reserve machine > > callback. NOWHERE ELSE is permissible. > > > It seems we can write memory-reserve node in device tree to do this as > well. Do you prefer us to reserve memblock in reserve callback or using > device tree? After consideration, I decide to reserve this memory in device tree. The memory is already used by trustzone, we should reserved them even when we don't run SMP. I just sent out a new series, please help to review them. Thanks Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/5] ARM: mediatek: add smp bringup code
Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/Makefile | 3 +
arch/arm/mach-mediatek/platsmp.c | 141 +++
2 files changed, 144 insertions(+)
create mode 100644 arch/arm/mach-mediatek/platsmp.c
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 43e619f..2116460 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1 +1,4 @@
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
+endif
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
new file mode 100644
index 000..8141f3f
--- /dev/null
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -0,0 +1,141 @@
+/*
+ * arch/arm/mach-mediatek/platsmp.c
+ *
+ * Copyright (c) 2014 Mediatek Inc.
+ * Author: Shunli Wang
+ * Yingjoe Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_MAX_CPU8
+#define MTK_SMP_REG_SIZE 0x1000
+
+struct mtk_smp_boot_info {
+ unsigned long smp_base;
+ unsigned int jump_reg;
+ unsigned int core_keys[MTK_MAX_CPU - 1];
+ unsigned int core_regs[MTK_MAX_CPU - 1];
+};
+
+static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {
+ 0x80002000, 0x3fc,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x3f8, 0x3f8, 0x3f8 },
+};
+
+static const struct mtk_smp_boot_info mtk_mt6589_boot = {
+ 0x10002000, 0x34,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x38, 0x3c, 0x40 },
+};
+
+static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
+ { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
+};
+
+static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
+};
+
+static void __iomem *mtk_smp_base;
+static const struct mtk_smp_boot_info *mtk_smp_info;
+
+static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ if (!mtk_smp_base)
+ return -EINVAL;
+
+ if (!mtk_smp_info->core_keys[cpu-1])
+ return -EINVAL;
+
+ writel_relaxed(mtk_smp_info->core_keys[cpu-1],
+ mtk_smp_base + mtk_smp_info->core_regs[cpu-1]);
+
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ return 0;
+}
+
+static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
+{
+ int i, num;
+ const struct of_device_id *infos;
+
+ if (trustzone) {
+ num = ARRAY_SIZE(mtk_tz_smp_boot_infos);
+ infos = mtk_tz_smp_boot_infos;
+ } else {
+ num = ARRAY_SIZE(mtk_smp_boot_infos);
+ infos = mtk_smp_boot_infos;
+ }
+
+ /* Find smp boot info for this SoC */
+ for (i = 0; i < num; i++) {
+ if (of_machine_is_compatible(infos[i].compatible)) {
+ mtk_smp_info = infos[i].data;
+ break;
+ }
+ }
+
+ if (!mtk_smp_info) {
+ pr_err("%s: Device is not supported\n", __func__);
+ return;
+ }
+
+ if (trustzone) {
+ /* smp_base(trustzone-bootinfo) is reserved by device tree */
+ mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);
+ } else {
+ mtk_smp_base = ioremap(mtk_smp_info->smp_base,
MTK_SMP_REG_SIZE);
+ if (!mtk_smp_base) {
+ pr_err("%s: Can't remap %lx\n", __func__,
+ mtk_smp_info->smp_base);
+ return;
+ }
+ }
+
+ /*
+* write the address of slave startup address into the system-wide
+* jump register
+*/
+ writel_relaxed(virt_to_phys(secondary_startup_arm),
+ mtk_smp_base + mtk_smp_info->jump_reg);
+}
+
+static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpus(max_cpus, 1);
+}
+
+static void __init mtk_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpus(max_cpus, 0);
+}
+
+static struct smp_operations mt81xx_tz_smp_ops __initdata = {
+ .smp_prepare_cpus = mtk_tz_smp_prepare_cpus,
+ .smp_boot
[PATCH v4 2/5] devicetree: bindings: add new SMP enable method Mediatek SoC
This commit add new cpu enable method "mediatek,mt65xx-smp" and "mediatek,mt81xx-tz-smp". Signed-off-by: Yingjoe Chen --- Documentation/devicetree/bindings/arm/cpus.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91e6e5c..3a07a87 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -195,6 +195,8 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6589-smp" + "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 5/5] ARM: dts: mt8127: enable basic SMP bringup for mt8127
Add arch timer node to enable arch-timer support. MT8127 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8127.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index ca3402e..50652fd 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu@0 {
device_type = "cpu";
@@ -47,6 +48,17 @@
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ trustzone-bootinfo: trustzone-bootinfo@80002000 {
+ compatible = "mediatek,trustzone-bootinfo";
+ reg = <0 0x80002000 0 0x1000>;
+ };
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -72,6 +84,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.9.1
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[PATCH v4 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
Add arch timer node to enable arch-timer support. MT8135 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8135.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 08371db..c3c90f2 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -46,6 +46,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu0: cpu@0 {
device_type = "cpu";
@@ -72,6 +73,17 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ trustzone-bootinfo: trustzone-bootinfo@80002000 {
+ compatible = "mediatek,trustzone-bootinfo";
+ reg = <0 0x80002000 0 0x1000>;
+ };
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -97,6 +109,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.9.1
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[PATCH v4 1/5] ARM: mediatek: enable gpt6 on boot up to make arch timer working
From: Matthias Brugger
We enable GTP6 which ungates the arch timer clock.
In the future this should be done in the bootloader.
Signed-off-by: Matthias Brugger
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/mediatek.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/mach-mediatek/mediatek.c
b/arch/arm/mach-mediatek/mediatek.c
index a954900..19dc738 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -16,6 +16,32 @@
*/
#include
#include
+#include
+#include
+#include
+
+
+#define GPT6_CON_MT65xx 0x10008060
+#define GPT_ENABLE 0x31
+
+static void __init mediatek_timer_init(void)
+{
+ void __iomem *gpt_base;
+
+ if (of_machine_is_compatible("mediatek,mt6589") ||
+ of_machine_is_compatible("mediatek,mt8135") ||
+ of_machine_is_compatible("mediatek,mt8127")) {
+ /* turn on GPT6 which ungates arch timer clocks */
+ gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
+
+ /* enable clock and set to free-run */
+ writel(GPT_ENABLE, gpt_base);
+ iounmap(gpt_base);
+ }
+
+ of_clk_init(NULL);
+ clocksource_of_init();
+};
static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
@@ -27,4 +53,5 @@ static const char * const mediatek_board_dt_compat[] = {
DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
.dt_compat = mediatek_board_dt_compat,
+ .init_time = mediatek_timer_init,
MACHINE_END
--
1.9.1
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[PATCH v4 0/5] Add SMP bringup support for mt65xx socs
This series add SMP brinup support for MediaTek SoCs. This is v4 and is based on v4.3-rc1. There are similar but different SMP bringup up methods on MediaTek mt65xx and mt81xx. On MT8135 & MT8127, system boots with a trustzone firmware. Others, like MT6589, doesn't have trustzone, and run kernel directly in secure world. Patch 1 enable arch timer support. Patch 2,3 add support for cpu enable-method "mediatek,mt6589-smp" and "mediatek,mt81xx-tz-smp", which support Mediatek SMP bringup for non-TZ and TZ platform. Patch 4,5 finally enable SMP bringup for mt8135 and mt8127. Changes in v4: - rebase to v4.3-rc1 - Reserve trustzone bootinfo memory area in device tree. Changes in v3: - v3 in [1] - The first 2 patches in v2 are merged in v4.2-rc1. - Patch 3~4 in v2 are moved to another series [2] - platsmp.c changes based on Stephen's suggestion - Change cpu enable-method name to "mediatek,mt6589-smp" Changes in v2: - Fix boot issue for THUMB2 kernel. - Not enable GPT_CLK_EVT when setup to fix GPT spurious interrupt issue - Change platsmp.c according to Matthias' suggestion http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000714.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000528.html [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001570.html [2] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001544.html Matthias Brugger (1): ARM: mediatek: enable gpt6 on boot up to make arch timer working Yingjoe Chen (4): devicetree: bindings: add new SMP enable method Mediatek SoC ARM: mediatek: add smp bringup code ARM: dts: mt8135: enable basic SMP bringup for mt8135 ARM: dts: mt8127: enable basic SMP bringup for mt8127 Documentation/devicetree/bindings/arm/cpus.txt | 2 + arch/arm/boot/dts/mt8127.dtsi | 27 + arch/arm/boot/dts/mt8135.dtsi | 27 + arch/arm/mach-mediatek/Makefile| 3 + arch/arm/mach-mediatek/mediatek.c | 27 + arch/arm/mach-mediatek/platsmp.c | 141 + 6 files changed, 227 insertions(+) create mode 100644 arch/arm/mach-mediatek/platsmp.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm64: dts: mt8173: add timer node
On Thu, 2015-09-17 at 14:51 +0100, Sudeep Holla wrote:
>
> On 16/09/15 03:04, Yingjoe Chen wrote:
> > From: Daniel Kurtz
> >
> > Add device node to enable GPT timer. This timer will be
> > used as sched clock source.
> >
>
> Interesting any known issues with or advantage over the arch timers
> to prefer it as sched clock source. I see even arch timers are present
> in DT, hence the question. Or is it just a incorrect commit log ?
>
> How does this get selected as sched clock source ? I don't see
> sched_clock_register in mtk_timer.c
>
> To be clear, I am not against adding this timer support, but just want
> to know is it preferred for sched clock source ? if yes why ? better
> resolution ?
Hi Sudeep,
Thanks for your review.
I hit the send too soon and missed cover letter, please see:
http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002303.html
The main reason to use GPT as sched clock is it won't stop during idle.
> > Change-Id: Idc4e3f0ee80b5c36cae6f0f2328f94aafcca1253
>
> ^ Should be dropped
>
> > Signed-off-by: Daniel Kurtz
> > Signed-off-by: Eddie Huang
> > Signed-off-by: Yingjoe Chen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index d18ee42..d763803 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -238,6 +238,15 @@
> > reg = <0 0x10007000 0 0x100>;
> > };
> >
> > + timer: timer@10008000 {
> > + compatible = "mediatek,mt8173-timer",
>
> Missing documentation ? I am referring upstream and it might be in some
> patches already queued perhaps ?
This is documented in
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt.
Do you mean I should add "mediatek,mt8173-timer" to that file?
Joe.C
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Re: [PATCH 1/2] arm64: mediatek: enable MTK_TIMER
On Wed, 2015-09-16 at 10:04 +0800, Yingjoe Chen wrote: > Enable MTK_TIMER for MediaTek plaform, which will be used as > schedule clock. Sorry, sending this series too early without cover letter and removing Change-Id. Here's the cover letter: This is actually v3 of "add GPT timer support for mt8173" series. This is based on v4.3-rc1 + clockevents-4.4[1] and James's mediatek-clk tree[2]. Changes compare to previous version[3]: - the first two mtk_timer related changes are removed because they are replaced/accepted in clockevents tree. - Remove 'add 13mhz clock for MT8173' because it is accepted in mediatek-clk tree. - Kconfig.platforms path change. So we only have 2 patches left here. Matthias, can you take these and help to remove the Change-Id? Daniel Kurtz (1): arm64: dts: mt8173: add timer node Yingjoe Chen (1): arm64: mediatek: enable MTK_TIMER [1] https://git.linaro.org/people/daniel.lezcano/linux.git clockevents/4.4 [2] http://lists.infradead.org/pipermail/linux-mediatek/2015-August/002069.html [3] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001544.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] arm64: dts: mt8173: add timer node
From: Daniel Kurtz
Add device node to enable GPT timer. This timer will be
used as sched clock source.
Change-Id: Idc4e3f0ee80b5c36cae6f0f2328f94aafcca1253
Signed-off-by: Daniel Kurtz
Signed-off-by: Eddie Huang
Signed-off-by: Yingjoe Chen
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..d763803 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -238,6 +238,15 @@
reg = <0 0x10007000 0 0x100>;
};
+ timer: timer@10008000 {
+ compatible = "mediatek,mt8173-timer",
+"mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CLK_13M>,
+<&topckgen CLK_TOP_RTC_SEL>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8173-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
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[PATCH 1/2] arm64: mediatek: enable MTK_TIMER
Enable MTK_TIMER for MediaTek plaform, which will be used as schedule clock. Change-Id: Ib77a0bf01193102c755077b6e72e73e477b18e5f Signed-off-by: Yingjoe Chen --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 23800a1..8176455 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -42,6 +42,7 @@ config ARCH_MEDIATEK bool "Mediatek MT65xx & MT81xx ARMv8 SoC" select ARM_GIC select PINCTRL + select MTK_TIMER help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] arm64: mt8173.dtsi: correct i2c node names
Node name in device tree should describe general class of the
device. Correct incorrect i2c node names.
Signed-off-by: Yingjoe Chen
---
This is based on v4.3-rc1.
All the other i2c node names are correct.
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..7f360b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -365,7 +365,7 @@
status = "disabled";
};
- i2c3: i2c3@1101 {
+ i2c3: i2c@1101 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x1101 0 0x70>,
<0 0x11000280 0 0x80>;
@@ -381,7 +381,7 @@
status = "disabled";
};
- i2c4: i2c4@11011000 {
+ i2c4: i2c@11011000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11011000 0 0x70>,
<0 0x11000300 0 0x80>;
@@ -397,7 +397,7 @@
status = "disabled";
};
- i2c6: i2c6@11013000 {
+ i2c6: i2c@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
<0 0x1180 0 0x80>;
--
1.9.1
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Re: [PATCH 0/5] add GPT timer support for mt8173
On Wed, 2015-08-26 at 09:37 +0200, Daniel Lezcano wrote: > On 07/13/2015 11:32 AM, Yingjoe Chen wrote: > > This series add GPT timer support for mt8173. This is based on v4.2-rc1 > > and Matthias' next branch (for dts parts). > > > > The first 2 patches comes from 'Add SMP bringup support for mt65xx socs' > > series [1]. I decide to move these 2 patches to this series, since it > > is more relevent here. They are changed based on Matthias' and Daniel's > > comments. > > > > [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000714.html > > > > Daniel Kurtz (1): > >arm64: dts: mt8173: add timer node > > > > Yingjoe Chen (4): > >clocksource: mediatek: do not enable GPT_CLK_EVT when setup > >clocksource: mediatek: Use GPT as sched clock source > >arm64: mediatek: enable MTK_TIMER > >clk: mediatek: add 13mhz clock for MT8173 > > > > arch/arm64/Kconfig | 1 + > > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 + > > drivers/clk/mediatek/clk-mt8173.c| 5 + > > drivers/clocksource/mtk_timer.c | 26 -- > > include/dt-bindings/clock/mt8173-clk.h | 3 ++- > > 5 files changed, 37 insertions(+), 7 deletions(-) > > Who will take this patchset ? I can take the patch 2 if needed. > > Hi Daniel, Please take patch 2 with your fix. Thanks. I think patch 3(enable MTK_TIMER in Kconfig) and 5 (add timer node) should go through Matthias' tree to arm-soc and patch 4(add 13mhz clock) should go through James' mtk-clk tree to clk maintainer. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
On Mon, 2015-08-24 at 09:51 +0200, Daniel Lezcano wrote: > On 08/21/2015 04:39 PM, Yingjoe Chen wrote: > > [ ... ] > > >>- Does the spurious interrupt occurs *every* time ? at each boot ? > > > > Yes. If you applied this series to enable mtk timer without this fix on > > mt8173 or mt8135 you can reproduce it. It occurs for every boot. > > > > It crash before uart driver is ready, so you'll have to use earlycon to > > see the crash log. > > Can you give me the earlycon params ? Hi Daniel, You probably already figure this out. anyway I'm using this to enable earlycon: Add 'earlycon' in bootargs, and in device tree chosen part, add "linux,stdout-path=&uart0;" Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
On Thu, 2015-08-20 at 16:28 +0200, Daniel Lezcano wrote:
> On 08/17/2015 04:10 PM, Yingjoe Chen wrote:
> > On Thu, 2015-08-13 at 10:35 +0200, Daniel Lezcano wrote:
> >> On 07/22/2015 10:14 AM, Yingjoe Chen wrote:
> >>> Spurious mtk timer interrupt is noticed at boot and cause kernel
> >>> crash. It seems if GPT is enabled, it will latch irq status even
> >>> when its IRQ is disabled.
>
> It "seems" ?
Hi,
Datasheet doesn't mention detail. So I did some experiments, playing
around with registers. Based on my observation, I think this is what
happens:
For each GPT timer, it has ENABLE, IRQ_EN, IRQ status, IRQ_ACK, counter
& compare.
When mtk_timer_init calls mtk_timer_setup to setup GPT_CLK_EVT, it
enable the timer but didn't set counter or compare. Both counter &
compare is zero on reset, so GPT immediately raise IRQ status. IRQ_EN is
still disabled now, so it didn't trigger interrupt right away.
At end of mtk_timer_init, it calls mtk_timer_enable_irq to enable irq.
Since IRQ status is 1 now, GPT trigger interrupt immediately. The
interrupt is serviced by mtk_timer_interrupt. Since this is not an
expected event, evt->dev.event_handler will be NULL and system crashed
in the handler.
> >>> When irq is enabled afterward, we see
> >>> spurious interrupt.
>
> Doesn't have the firmware something to do with that ?
We have 6 GPT on mt8173, mtk timer use 2 of them. The spurious interrupt
only happens on GPT_CLK_EVT (GPT1). Our firmware didn't touch that one,
so it is in reset default when mtk timer driver try to enable it.
> I have a mtk 8173 board I can use next week. How do you reproduce the
> issue ?
>
> >>> Change init flow to only enable GPT_CLK_SRC at mtk_timer_init.
> >>>
> >>> Acked-by: Matthias Brugger
> >>> Reviewed-by: Daniel Kurtz
> >>> Signed-off-by: Yingjoe Chen
> >>> ---
> >>>
> >>> Update to my patch [1], added __init as Daniel suggest. This is the
> >>> only patch that need to change in that series, so I only sent this one.
> >>>
> >>> http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001545.html
> >>>
> >>>drivers/clocksource/mtk_timer.c | 16 ++--
> >>>1 file changed, 10 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/drivers/clocksource/mtk_timer.c
> >>> b/drivers/clocksource/mtk_timer.c
> >>> index 68ab423..2ba5b66 100644
> >>> --- a/drivers/clocksource/mtk_timer.c
> >>> +++ b/drivers/clocksource/mtk_timer.c
> >>> @@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct
> >>> mtk_clock_event_device *evt)
> >>> writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
> >>>}
> >>>
> >>> -static void
> >>> -mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
> >>> +static void __init mtk_timer_setup(struct mtk_clock_event_device *evt,
> >>> +u8 timer, u8 option, bool enable)
> >>>{
> >>> + u32 val;
> >>> +
> >>> writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
> >>> evt->gpt_base + TIMER_CTRL_REG(timer));
> >>>
> >>> @@ -167,8 +169,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt,
> >>> u8 timer, u8 option)
> >>>
> >>> writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
> >>>
> >>> - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
> >>> - evt->gpt_base + TIMER_CTRL_REG(timer));
> >>> + val = TIMER_CTRL_OP(option);
> >>> + if (enable)
> >>> + val |= TIMER_CTRL_ENABLE;
> >>> + writel(val, evt->gpt_base + TIMER_CTRL_REG(timer));
> >>
> >> Instead of the 'enable' new option, I prefer a test with 'timer' with a
> >> comment:
> >>
> >>/*
> >> * the timer hw is broken in that way ... bla bla, so we only
> >> * enable the clocksource ...
> >> */
> >>if (timer == GPT_CLK_SRC)
> >>val |= TIMER_CTRL_ENABLE;
> >
> > Hi Daniel,
> >
> > Thanks for your review.
> > Since this bug happens to anyone using interrupt,
>
> Can you elaborate ? I don't get the point.
>
> > I'm not sure checking
> > timer and only enable it for GPT_CLK_SRC is easier to read. Anyway, I'll
> > change to this in next version.
> >> That sai
Re: [PATCH v2 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
On Thu, 2015-08-13 at 10:35 +0200, Daniel Lezcano wrote:
> On 07/22/2015 10:14 AM, Yingjoe Chen wrote:
> > Spurious mtk timer interrupt is noticed at boot and cause kernel
> > crash. It seems if GPT is enabled, it will latch irq status even
> > when its IRQ is disabled. When irq is enabled afterward, we see
> > spurious interrupt.
> > Change init flow to only enable GPT_CLK_SRC at mtk_timer_init.
> >
> > Acked-by: Matthias Brugger
> > Reviewed-by: Daniel Kurtz
> > Signed-off-by: Yingjoe Chen
> > ---
> >
> > Update to my patch [1], added __init as Daniel suggest. This is the
> > only patch that need to change in that series, so I only sent this one.
> >
> > http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001545.html
> >
> > drivers/clocksource/mtk_timer.c | 16 ++--
> > 1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/clocksource/mtk_timer.c
> > b/drivers/clocksource/mtk_timer.c
> > index 68ab423..2ba5b66 100644
> > --- a/drivers/clocksource/mtk_timer.c
> > +++ b/drivers/clocksource/mtk_timer.c
> > @@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct
> > mtk_clock_event_device *evt)
> > writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
> > }
> >
> > -static void
> > -mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
> > +static void __init mtk_timer_setup(struct mtk_clock_event_device *evt,
> > + u8 timer, u8 option, bool enable)
> > {
> > + u32 val;
> > +
> > writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
> > evt->gpt_base + TIMER_CTRL_REG(timer));
> >
> > @@ -167,8 +169,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt, u8
> > timer, u8 option)
> >
> > writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
> >
> > - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
> > - evt->gpt_base + TIMER_CTRL_REG(timer));
> > + val = TIMER_CTRL_OP(option);
> > + if (enable)
> > + val |= TIMER_CTRL_ENABLE;
> > + writel(val, evt->gpt_base + TIMER_CTRL_REG(timer));
>
> Instead of the 'enable' new option, I prefer a test with 'timer' with a
> comment:
>
> /*
>* the timer hw is broken in that way ... bla bla, so we only
>* enable the clocksource ...
>*/
> if (timer == GPT_CLK_SRC)
> val |= TIMER_CTRL_ENABLE;
Hi Daniel,
Thanks for your review.
Since this bug happens to anyone using interrupt, I'm not sure checking
timer and only enable it for GPT_CLK_SRC is easier to read. Anyway, I'll
change to this in next version.
> That said, can you have a look at commit 1096be08 ?
> "clockevents: sun5i: Fix setup_irq init sequence"
>
> first and check if moving the interrupt request after the
> clockevents_config_and_register could fix your issue.
I've tested this before, see:
http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000539.html
http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000551.html
Joe.C
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Re: [PATCH v3 0/5] Add SMP bringup support for mt65xx socs
On Wed, 2015-08-05 at 23:31 +0100, Russell King - ARM Linux wrote: > On Wed, Aug 05, 2015 at 08:44:11PM +0200, Matthias Brugger wrote: > > On Tuesday, July 14, 2015 01:18:26 PM Yingjoe Chen wrote: > > > This series add SMP brinup support for MediaTek SoCs. This is based > > > on v4.2-rc1 and Matthias' next branch (for dts parts). <...> > > Applied to v4.2-next/soc-2 and v4.2-next/dts-2 > > I've just NAK'd one of the patches in this set; I don't tend to even see > mediatek patches normally, as they all head into my junk mailfolder > because mediatek's mail server setup is truely abysmal (it has broken > reverse DNS - the DNS positively says that the mail server is not a > legit owner of the name it claims to be.) Hi Russell, Hope you see this. Thanks for your review. I already pass this information to our IT, hope they can resolve this soon. > The problem is that this patch series uses memblock_reserve() way after > the memory has been transitioned out of memblock's control, so actually > this has no effect. > > I've seen a number of patches doing this. I'm not sure what's soo friggin > hard for people to understand: memblock is about the EARLY stages of > getting the system up and running. Once the memory has been handed > over to the kernel's memory management, memblock MUST NOT BE USED to > reserve memory. > > There is one place, and one place only in the ARM kernel where > memblock_reserve() is possible, and that's in the ->reserve machine > callback. NOWHERE ELSE is permissible. It seems we can write memory-reserve node in device tree to do this as well. Do you prefer us to reserve memblock in reserve callback or using device tree? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
On Wed, 2015-07-22 at 16:14 +0800, Yingjoe Chen wrote: > Spurious mtk timer interrupt is noticed at boot and cause kernel > crash. It seems if GPT is enabled, it will latch irq status even > when its IRQ is disabled. When irq is enabled afterward, we see > spurious interrupt. > Change init flow to only enable GPT_CLK_SRC at mtk_timer_init. > > Acked-by: Matthias Brugger > Reviewed-by: Daniel Kurtz > Signed-off-by: Yingjoe Chen > --- > Update to my patch [1], added __init as Daniel suggest. This is the > only patch that need to change in that series, so I only sent this one. > > http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001545.html Hi Daniel, Thomas, Any suggestions for mtk_timer fixes in this series? Should I resend and add tags from the reviewers? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
On Tue, 2015-07-14 at 15:39 +0800, Daniel Kurtz wrote: > Hi Yingjoe, > > On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen > wrote: > > Spurious mtk timer interrupt is noticed at boot and cause kernel > > crash. It seems if GPT is enabled, it will latch irq status even > > when its IRQ is disabled. When irq is enabled afterward, we see > > spurious interrupt. > > Change init flow to only enable GPT_CLK_SRC at mtk_timer_init. > > > > Signed-off-by: Yingjoe Chen > > --- > > drivers/clocksource/mtk_timer.c | 16 ++-- > > 1 file changed, 10 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/clocksource/mtk_timer.c > > b/drivers/clocksource/mtk_timer.c > > index 68ab423..237c20b 100644 > > --- a/drivers/clocksource/mtk_timer.c > > +++ b/drivers/clocksource/mtk_timer.c > > @@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct > > mtk_clock_event_device *evt) > > writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); > > } > > > > -static void > > -mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) > > +static void mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, > > + u8 option, bool enable) > > This function can be: __init > > Other than this tiny nit, and the small potential conflict in patch 4, > this whole series is: > > Reviewed-by: Daniel Kurtz > > (I do think it is a bit strange that the mediatek,mt6577-timer binding > does not use "clock-names", but that is independent of this patch > set). > Hi Daniel, Thanks for your review. I added __init as you suggested, and Pi-Cheng already sent an updated version of his patch to resolve the conflict[1]. Joe.C [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001592.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
Spurious mtk timer interrupt is noticed at boot and cause kernel
crash. It seems if GPT is enabled, it will latch irq status even
when its IRQ is disabled. When irq is enabled afterward, we see
spurious interrupt.
Change init flow to only enable GPT_CLK_SRC at mtk_timer_init.
Acked-by: Matthias Brugger
Reviewed-by: Daniel Kurtz
Signed-off-by: Yingjoe Chen
---
Update to my patch [1], added __init as Daniel suggest. This is the
only patch that need to change in that series, so I only sent this one.
http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001545.html
drivers/clocksource/mtk_timer.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
index 68ab423..2ba5b66 100644
--- a/drivers/clocksource/mtk_timer.c
+++ b/drivers/clocksource/mtk_timer.c
@@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct
mtk_clock_event_device *evt)
writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
}
-static void
-mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
+static void __init mtk_timer_setup(struct mtk_clock_event_device *evt,
+ u8 timer, u8 option, bool enable)
{
+ u32 val;
+
writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
evt->gpt_base + TIMER_CTRL_REG(timer));
@@ -167,8 +169,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt, u8
timer, u8 option)
writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
- writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
+ val = TIMER_CTRL_OP(option);
+ if (enable)
+ val |= TIMER_CTRL_ENABLE;
+ writel(val, evt->gpt_base + TIMER_CTRL_REG(timer));
}
static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
@@ -235,12 +239,12 @@ static void __init mtk_timer_init(struct device_node
*node)
evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
/* Configure clock source */
- mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
+ mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, true);
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
node->name, rate, 300, 32, clocksource_mmio_readl_up);
/* Configure clock event */
- mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT, false);
clockevents_config_and_register(&evt->dev, rate, 0x3,
0x);
--
1.8.1.1.dirty
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Re: [PATCH v2 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173
Hi Daniel, Chunfeng,
On Mon, 2015-07-20 at 22:39 +0800, chunfeng yun wrote:
> Hi,
>
> On Tue, 2015-07-14 at 18:12 +0800, Daniel Kurtz wrote:
<...>
> > > +
> > > + usb_p1_vbus: fixedregulator@0 {
> >
> > Why @0 ?
> It is the first fixed regulator, so set it to 0 as a index.
> I will remove it later
Since this name should be unique, I think we should use gpio number as
address for fixedregulator in case we need other fixedregulators. So
this could be:
usb_p1_vbus: fixedregulator@130 {
Also, we should sort according to the address(gpio number) for these
nodes. Does this make sense?
Joe.C
> >
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "usb_vbus";
> > > + regulator-min-microvolt = <500>;
> > > + regulator-max-microvolt = <500>;
> > > + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
> > > + enable-active-high;
> > > + };
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Re: [PATCH v3 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Tue, 2015-07-14 at 09:19 -0500, Nathan Lynch wrote:
> On 07/14/2015 12:18 AM, Yingjoe Chen wrote:
> > Add arch timer node to enable arch-timer support. MT8135 firmware
> > doesn't correctly setup arch-timer frequency and CNTVOFF, add
> > properties to workaround this.
>
> [...]
>
> >
> > + timer {
> > + compatible = "arm,armv7-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = > + IRQ_TYPE_LEVEL_LOW)>,
> > + > + IRQ_TYPE_LEVEL_LOW)>,
> > + > + IRQ_TYPE_LEVEL_LOW)>,
> > + > + IRQ_TYPE_LEVEL_LOW)>;
> > + clock-frequency = <1300>;
> > + arm,cpu-registers-not-fw-configured;
>
> It's disappointing to see this property in new DTS submissions. It
> prevents taking advantage of the VDSO for gettimeofday/clock_gettime.
>
Hi,
I know. But unfortunately this is a more then 1 year SoC, so I can't do
anything to change this :(
Joe.C
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[PATCH v3 2/5] devicetree: bindings: add new SMP enable method Mediatek SoC
This commit add new cpu enable method "mediatek,mt65xx-smp" and "mediatek,mt81xx-tz-smp". Signed-off-by: Yingjoe Chen --- Documentation/devicetree/bindings/arm/cpus.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index d6b794c..d58eb45 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -195,6 +195,8 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6589-smp" + "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 5/5] ARM: dts: mt8127: enable basic SMP bringup for mt8127
Add arch timer node to enable arch-timer support. MT8127 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8127.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index ca3402e..fae84ee 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu@0 {
device_type = "cpu";
@@ -72,6 +73,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.8.1.1.dirty
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[PATCH v3 0/5] Add SMP bringup support for mt65xx socs
This series add SMP brinup support for MediaTek SoCs. This is based on v4.2-rc1 and Matthias' next branch (for dts parts). There are similar but different SMP bringup up methods on MediaTek mt65xx and mt81xx. On MT8135 & MT8127, system boots with a trustzone firmware. Others, like MT6589, doesn't have trustzone, and run kernel directly in secure world. Patch 1 enable arch timer support. Patch 2,3 add support for cpu enable-method "mediatek,mt6589-smp" and "mediatek,mt81xx-tz-smp", which support Mediatek SMP bringup for non-TZ and TZ platform. Patch 4,5 finally enable SMP bringup for mt8135 and mt8127. Changes in v3: - The first 2 patches in v2 are merged in v4.2-rc1. - Patch 3~4 in v2 are moved to another series [1] - platsmp.c changes based on Stephen's suggestion - Change cpu enable-method name to "mediatek,mt6589-smp" Changes in v2: - Fix boot issue for THUMB2 kernel. - Not enable GPT_CLK_EVT when setup to fix GPT spurious interrupt issue - Change platsmp.c according to Matthias' suggestion http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000714.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000528.html [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001544.html Matthias Brugger (1): ARM: mediatek: enable gpt6 on boot up to make arch timer working Yingjoe Chen (4): devicetree: bindings: add new SMP enable method Mediatek SoC ARM: mediatek: add smp bringup code ARM: dts: mt8135: enable basic SMP bringup for mt8135 ARM: dts: mt8127: enable basic SMP bringup for mt8127 Documentation/devicetree/bindings/arm/cpus.txt | 2 + arch/arm/boot/dts/mt8127.dtsi | 16 +++ arch/arm/boot/dts/mt8135.dtsi | 16 +++ arch/arm/mach-mediatek/Makefile| 3 + arch/arm/mach-mediatek/mediatek.c | 27 + arch/arm/mach-mediatek/platsmp.c | 144 + 6 files changed, 208 insertions(+) create mode 100644 arch/arm/mach-mediatek/platsmp.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/5] ARM: mediatek: add smp bringup code
Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/Makefile | 3 +
arch/arm/mach-mediatek/platsmp.c | 144 +++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm/mach-mediatek/platsmp.c
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 43e619f..2116460 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1 +1,4 @@
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
+endif
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
new file mode 100644
index 000..a5bc108
--- /dev/null
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-mediatek/platsmp.c
+ *
+ * Copyright (c) 2014 Mediatek Inc.
+ * Author: Shunli Wang
+ * Yingjoe Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_MAX_CPU8
+#define MTK_SMP_REG_SIZE 0x1000
+
+struct mtk_smp_boot_info {
+ unsigned long smp_base;
+ unsigned int jump_reg;
+ unsigned int core_keys[MTK_MAX_CPU - 1];
+ unsigned int core_regs[MTK_MAX_CPU - 1];
+};
+
+static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {
+ 0x80002000, 0x3fc,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x3f8, 0x3f8, 0x3f8 },
+};
+
+static const struct mtk_smp_boot_info mtk_mt6589_boot = {
+ 0x10002000, 0x34,
+ { 0x534c4131, 0x4c415332, 0x41534c33 },
+ { 0x38, 0x3c, 0x40 },
+};
+
+static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
+ { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
+};
+
+static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+ { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
+};
+
+static void __iomem *mtk_smp_base;
+static const struct mtk_smp_boot_info *mtk_smp_info;
+
+static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ if (!mtk_smp_base)
+ return -EINVAL;
+
+ if (!mtk_smp_info->core_keys[cpu-1])
+ return -EINVAL;
+
+ writel_relaxed(mtk_smp_info->core_keys[cpu-1],
+ mtk_smp_base + mtk_smp_info->core_regs[cpu-1]);
+
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ return 0;
+}
+
+static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
+{
+ int i, num;
+ const struct of_device_id *infos;
+
+ if (trustzone) {
+ num = ARRAY_SIZE(mtk_tz_smp_boot_infos);
+ infos = mtk_tz_smp_boot_infos;
+ } else {
+ num = ARRAY_SIZE(mtk_smp_boot_infos);
+ infos = mtk_smp_boot_infos;
+ }
+
+ /* Find smp boot info for this SoC */
+ for (i = 0; i < num; i++) {
+ if (of_machine_is_compatible(infos[i].compatible)) {
+ mtk_smp_info = infos[i].data;
+ break;
+ }
+ }
+
+ if (!mtk_smp_info) {
+ pr_err("%s: Device is not supported\n", __func__);
+ return;
+ }
+
+ if (trustzone) {
+ if (memblock_reserve(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE))
{
+ pr_err("%s: Can't reserve smp memory\n", __func__);
+ return;
+ }
+ mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);
+ } else {
+ mtk_smp_base = ioremap(mtk_smp_info->smp_base,
MTK_SMP_REG_SIZE);
+ if (!mtk_smp_base) {
+ pr_err("%s: Can't remap %lx\n", __func__,
+ mtk_smp_info->smp_base);
+ return;
+ }
+ }
+
+ /*
+* write the address of slave startup address into the system-wide
+* jump register
+*/
+ writel_relaxed(virt_to_phys(secondary_startup_arm),
+ mtk_smp_base + mtk_smp_info->jump_reg);
+}
+
+static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpus(max_cpus, 1);
+}
+
+static void __init mtk_smp_prepare_cpus(unsigned int max_cpus)
+{
+ __mtk_smp_prepare_cpu
[PATCH v3 1/5] ARM: mediatek: enable gpt6 on boot up to make arch timer working
From: Matthias Brugger
We enable GTP6 which ungates the arch timer clock.
In the future this should be done in the bootloader.
Signed-off-by: Matthias Brugger
Signed-off-by: Yingjoe Chen
---
arch/arm/mach-mediatek/mediatek.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/mach-mediatek/mediatek.c
b/arch/arm/mach-mediatek/mediatek.c
index a954900..19dc738 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -16,6 +16,32 @@
*/
#include
#include
+#include
+#include
+#include
+
+
+#define GPT6_CON_MT65xx 0x10008060
+#define GPT_ENABLE 0x31
+
+static void __init mediatek_timer_init(void)
+{
+ void __iomem *gpt_base;
+
+ if (of_machine_is_compatible("mediatek,mt6589") ||
+ of_machine_is_compatible("mediatek,mt8135") ||
+ of_machine_is_compatible("mediatek,mt8127")) {
+ /* turn on GPT6 which ungates arch timer clocks */
+ gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
+
+ /* enable clock and set to free-run */
+ writel(GPT_ENABLE, gpt_base);
+ iounmap(gpt_base);
+ }
+
+ of_clk_init(NULL);
+ clocksource_of_init();
+};
static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
@@ -27,4 +53,5 @@ static const char * const mediatek_board_dt_compat[] = {
DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
.dt_compat = mediatek_board_dt_compat,
+ .init_time = mediatek_timer_init,
MACHINE_END
--
1.8.1.1.dirty
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[PATCH v3 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
Add arch timer node to enable arch-timer support. MT8135 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt8135.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 0aba9eb..0264d2e 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -44,6 +44,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu0: cpu@0 {
device_type = "cpu";
@@ -96,6 +97,21 @@
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.8.1.1.dirty
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[PATCH 0/5] add GPT timer support for mt8173
This series add GPT timer support for mt8173. This is based on v4.2-rc1 and Matthias' next branch (for dts parts). The first 2 patches comes from 'Add SMP bringup support for mt65xx socs' series [1]. I decide to move these 2 patches to this series, since it is more relevent here. They are changed based on Matthias' and Daniel's comments. [1] http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000714.html Daniel Kurtz (1): arm64: dts: mt8173: add timer node Yingjoe Chen (4): clocksource: mediatek: do not enable GPT_CLK_EVT when setup clocksource: mediatek: Use GPT as sched clock source arm64: mediatek: enable MTK_TIMER clk: mediatek: add 13mhz clock for MT8173 arch/arm64/Kconfig | 1 + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 + drivers/clk/mediatek/clk-mt8173.c| 5 + drivers/clocksource/mtk_timer.c | 26 -- include/dt-bindings/clock/mt8173-clk.h | 3 ++- 5 files changed, 37 insertions(+), 7 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] clocksource: mediatek: do not enable GPT_CLK_EVT when setup
Spurious mtk timer interrupt is noticed at boot and cause kernel
crash. It seems if GPT is enabled, it will latch irq status even
when its IRQ is disabled. When irq is enabled afterward, we see
spurious interrupt.
Change init flow to only enable GPT_CLK_SRC at mtk_timer_init.
Signed-off-by: Yingjoe Chen
---
drivers/clocksource/mtk_timer.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
index 68ab423..237c20b 100644
--- a/drivers/clocksource/mtk_timer.c
+++ b/drivers/clocksource/mtk_timer.c
@@ -156,9 +156,11 @@ static void mtk_timer_global_reset(struct
mtk_clock_event_device *evt)
writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
}
-static void
-mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
+static void mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer,
+ u8 option, bool enable)
{
+ u32 val;
+
writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
evt->gpt_base + TIMER_CTRL_REG(timer));
@@ -167,8 +169,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt, u8
timer, u8 option)
writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
- writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
+ val = TIMER_CTRL_OP(option);
+ if (enable)
+ val |= TIMER_CTRL_ENABLE;
+ writel(val, evt->gpt_base + TIMER_CTRL_REG(timer));
}
static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
@@ -235,12 +239,12 @@ static void __init mtk_timer_init(struct device_node
*node)
evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
/* Configure clock source */
- mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
+ mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, true);
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
node->name, rate, 300, 32, clocksource_mmio_readl_up);
/* Configure clock event */
- mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT, false);
clockevents_config_and_register(&evt->dev, rate, 0x3,
0x);
--
1.8.1.1.dirty
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[PATCH 4/5] clk: mediatek: add 13mhz clock for MT8173
Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
index 4b9e04c..540c5c3 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -618,6 +618,10 @@ static const struct mtk_gate infra_clks[] __initconst = {
GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
};
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+ FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
+};
+
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
@@ -737,6 +741,7 @@ static void __init mtk_infrasys_init(struct device_node
*node)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
diff --git a/include/dt-bindings/clock/mt8173-clk.h
b/include/dt-bindings/clock/mt8173-clk.h
index 4ad76ed..fa2a2bb 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -187,7 +187,8 @@
#define CLK_INFRA_CEC 9
#define CLK_INFRA_PMICSPI 10
#define CLK_INFRA_PMICWRAP 11
-#define CLK_INFRA_NR_CLK 12
+#define CLK_INFRA_CLK_13M 12
+#define CLK_INFRA_NR_CLK 13
/* PERI_SYS */
--
1.8.1.1.dirty
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[PATCH 3/5] arm64: mediatek: enable MTK_TIMER
Enable MTK_TIMER for MediaTek plaform, which will be used as schedule clock. Signed-off-by: Yingjoe Chen --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0f6edb1..5934f51 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -193,6 +193,7 @@ config ARCH_MEDIATEK bool "Mediatek MT65xx & MT81xx ARMv8 SoC" select ARM_GIC select PINCTRL + select MTK_TIMER help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] clocksource: mediatek: Use GPT as sched clock source
When cpu is in deep idle, arch timer will stop counting. Setup GPT as
sched clock source so it can keep counting in idle.
Signed-off-by: Yingjoe Chen
---
drivers/clocksource/mtk_timer.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
index 237c20b..ae95b29 100644
--- a/drivers/clocksource/mtk_timer.c
+++ b/drivers/clocksource/mtk_timer.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#define GPT_IRQ_EN_REG 0x00
@@ -59,6 +60,13 @@ struct mtk_clock_event_device {
struct clock_event_device dev;
};
+static void __iomem *gpt_sched_reg __read_mostly;
+
+static u64 notrace mtk_read_sched_clock(void)
+{
+ return readl_relaxed(gpt_sched_reg);
+}
+
static inline struct mtk_clock_event_device *to_mtk_clk(
struct clock_event_device *c)
{
@@ -242,6 +250,8 @@ static void __init mtk_timer_init(struct device_node *node)
mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, true);
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
node->name, rate, 300, 32, clocksource_mmio_readl_up);
+ gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
+ sched_clock_register(mtk_read_sched_clock, 32, rate);
/* Configure clock event */
mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT, false);
--
1.8.1.1.dirty
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[PATCH 5/5] arm64: dts: mt8173: add timer node
From: Daniel Kurtz
Add device node to enable GPT timer. This timer will be
used as sched clock source.
Signed-off-by: Daniel Kurtz
Signed-off-by: Eddie Huang
Signed-off-by: Yingjoe Chen
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 0696f8f..04bdd8f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -219,6 +219,15 @@
reg = <0 0x10007000 0 0x100>;
};
+ timer: timer@10008000 {
+ compatible = "mediatek,mt8173-timer",
+"mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = ;
+ clocks = <&infracfg CLK_INFRA_CLK_13M>,
+<&topckgen CLK_TOP_RTC_SEL>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8173-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.8.1.1.dirty
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Re: [PATCH v2 4/9] clocksource: mediatek: Use GPT as sched clock source
On Fri, 2015-07-03 at 17:51 +0200, Matthias Brugger wrote: > On Friday, July 03, 2015 09:48:42 PM Daniel Kurtz wrote: <...> > > >> @@ -243,6 +251,8 @@ static void __init mtk_timer_init(struct device_node > > >> *node)>> > > >> mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, 1); > > >> clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), > > >> > > >> node->name, rate, 300, 32, > > >> clocksource_mmio_readl_up); > > >> > > >> + gpt_base = evt->gpt_base; > > > > > > This is really hacky. We should clean up the code and provide > > > mtk_clock_event_device globally. > > > Please add the patch below, which does exactly this. > > > > I don't think this is so hacky. > > In light of Stephen's comment about the benefit of using > > container_of() to extract gpt_base from the passed in struct > > clock_event_device in the other routines, what is the benefit of > > making more of mtk_clock_event_device global? > > I think what Yingjoe has implemented is short and sweet. > > > > Huh, this patch got somehow forgotten. > Ok, just one comment. I would prefer to rename the global gpt_base to > gpt_sched_base or something similar and set the pointer + offset directly > mtk_timer_init. In next version, I will it change to: static void __iomem *gpt_sched_reg __read_mostly; and in mtk_timer_init: + gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC); Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] pwm: add MediaTek display PWM driver support
On Thu, 2015-06-18 at 18:19 +0800, YH Huang wrote: > On Fri, 2015-06-12 at 12:20 +0200, Thierry Reding wrote: > > > +/* Shift log2(PWM_PERIOD_MAX + 1) as divisor */ > > > +#define PWM_PERIOD_BIT_SHIFT 12 > > > > I wasn't very clear about this in my earlier review, so let me try to > > explain why I think this is confusing. You use this as a divisor, but > > you encode it as a shift. It's also PWM_PERIOD_MAX + 1, so I think it > > would make more sense to drop this, keep PWM_PERIOD_MAX as above and > > then replace the > > > > >> PWM_PERIOD_BIT_SHIFT > > > > below by > > > > / (PWM_PERIOD_MAX + 1) > > > > Maybe I can change in this way: > Remove this: #define PWM_PERIOD_MAX 0x0fff > Using ">> PWM_PERIOD_BIT_SHIFT" is faster than "/ (PWM_PERIOD_MAX + 1)" > Is this right? The place which use this shift is: clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> PWM_PERIOD_BIT_SHIFT; div_u64 return u64. If we change >> to /, and somehow compiler didn't optimize that div into shift, it will cause build error. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/6] xhci: probe phy before add usb_hcd
On Wed, 2015-05-27 at 07:18 -0500, Felipe Balbi wrote: > On Wed, May 27, 2015 at 07:48:00PM +0800, chunfeng@mediatek.com wrote: > > From: Chunfeng Yun > > > > find the phy driver before add primary usb_hcd to avoid acessing > > xHCI register which may hangup the system when the phy is not loaded > > yet and the related powers or clocks put in phy driver are not > > enabled. > > it seems like the same clock is needed by PHY and XHCI. This patch looks > incorrect. Hi, I agree that the driver should enable clock it used by itself and not depends on init order. This should be fixed. But in general, I think it make sense to only add hcd after all required resource are ready. At least it remove unnecessary calls to usb_add_hcd/usb_remove_hcd. Is it better if the commit message is changed to something like the below? Currently xhci_plat_probe() call usb_add_hcd before trying to init the phy. However if the phy is not ready at the moment, it have to remove the hcd and probe again later Change the init order so we only add hcd when all required resource are ready. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] pwm: add Mediatek display PWM driver support
On Tue, 2015-05-26 at 08:05 +0200, Sascha Hauer wrote:
> On Thu, May 21, 2015 at 04:22:31PM +0800, YH Huang wrote:
> > On Mon, 2015-05-18 at 11:42 +0800, Daniel Kurtz wrote:
<...>
> > > On Mon, May 11, 2015 at 5:26 PM, YH Huang wrote:
> > > > +
> > > > +static const struct of_device_id mtk_disp_pwm_of_match[] = {
> > > > + { .compatible = "mediatek,mt6595-disp-pwm" },
> > >
> > > Does this driver support the PWM in mt8173?
> > > If so, don't you need this, too:
> > >
> > > { .compatible = "mediatek,mt8173-disp-pwm" },
> >
> > Yes, it supports mt8173.
> > I will add it.
>
> If both yre compatible you don't need to add it since you have a
> "mediatek,mt6595-disp-pwm" in the mt8173 device tree.
Hi Sascha,
We got a similar discussion about this with Mark Brown for spi driver,
please see:
http://lists.infradead.org/pipermail/linux-mediatek/2015-May/000673.html
Joe.C
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Re: [PATCH v2 0/2] Add MediaTek display PWM driver
On Thu, 2015-05-21 at 21:29 +0800, YH Huang wrote: > YH Huang (2): > dt-bindings: pwm: add MediaTek display PWM bindings > pwm: add MediaTek display PWM driver support > > .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 25 +++ > drivers/pwm/Kconfig| 10 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-mtk-disp.c | 228 > + > 4 files changed, 264 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt > create mode 100644 drivers/pwm/pwm-mtk-disp.c Hi YH, It would be easier for reviewer if you have a summary here on what you have changed compare to last version. Also, please add patch series summary even for v2, it remind reviewer what this series is about. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/9] clocksource: mediatek: Use GPT as sched clock source
On Wed, 2015-05-20 at 13:02 +0200, Matthias Brugger wrote:
> 2015-05-16 9:58 GMT+02:00 Yingjoe Chen :
> > When cpu is in deep idle, arch timer will stop counting. Setup GPT as
> > sched clock source so it can keep counting in idle.
> >
> > Signed-off-by: Yingjoe Chen
> > ---
> > drivers/clocksource/mtk_timer.c | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/clocksource/mtk_timer.c
> > b/drivers/clocksource/mtk_timer.c
> > index 91206f9..fe7cf72 100644
> > --- a/drivers/clocksource/mtk_timer.c
> > +++ b/drivers/clocksource/mtk_timer.c
> > @@ -24,6 +24,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > #define GPT_IRQ_EN_REG 0x00
> > @@ -59,6 +60,13 @@ struct mtk_clock_event_device {
> > struct clock_event_device dev;
> > };
> >
> > +static void __iomem *gpt_base __read_mostly;
> > +
> > +static u64 notrace mtk_read_sched_clock(void)
> > +{
> > + return readl_relaxed(gpt_base + TIMER_CNT_REG(GPT_CLK_SRC));
> > +}
> > +
> > static inline struct mtk_clock_event_device *to_mtk_clk(
> > struct clock_event_device *c)
> > {
> > @@ -243,6 +251,8 @@ static void __init mtk_timer_init(struct device_node
> > *node)
> > mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, 1);
> > clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
> > node->name, rate, 300, 32,
> > clocksource_mmio_readl_up);
> > + gpt_base = evt->gpt_base;
>
> This is really hacky. We should clean up the code and provide
> mtk_clock_event_device globally.
> Please add the patch below, which does exactly this.
> 8< >8 --
> From 631e7bf4e5d9456d0bb4a29b2dee4b84e8c052bd Mon Sep 17 00:00:00 2001
> From: Matthias Brugger
> Date: Wed, 20 May 2015 12:43:16 +0200
> Subject: [PATCH] clocksource: mediatek: Define mtk_clock_event_device globally
>
> Sched clock code, especially sched_clock_register does not allow to pass a
> pointer to actual_read_sched_clock. So if in the driver the register base
> address is not globally defined, we are not able to read the scheduler
> clock register. This patch sets the mtk_clock_event_device struct globally
> for the driver, to be able to read the register.
Hi,
I'm not sure using a global device pointer is any better.
Actually, almost every user of sched_clock_register need to keep a
global register base address. Does it make sense to fix this in
sched_clock_register?
> Signed-off-by: Matthias Brugger
> ---
> drivers/clocksource/mtk_timer.c | 50
> +++--
> 1 file changed, 18 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
> index 68ab423..c5f5b40 100644
> --- a/drivers/clocksource/mtk_timer.c
> +++ b/drivers/clocksource/mtk_timer.c
> @@ -59,13 +59,9 @@ struct mtk_clock_event_device {
> struct clock_event_device dev;
> };
>
> -static inline struct mtk_clock_event_device *to_mtk_clk(
> -struct clock_event_device *c)
> -{
> -return container_of(c, struct mtk_clock_event_device, dev);
> -}
> +struct mtk_clock_event_device *evt;
The name is too short even if we make it static:
static struct mtk_clock_event_device *evt __read_mostly;
Joe.C
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[PATCH 2/2] arm64: dts: mt8173: Fixup pinctrl nodes
The 8173 pinctrl node doesn't follow dts convention. Fix them.
Also add a comment to explain pinctrl register usage to make it
more clear.
Signed-off-by: Yingjoe Chen
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 8346c0f..e4a30cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -128,6 +128,7 @@
compatible = "simple-bus";
ranges;
+ /* Provide regmap for pinctrl driver */
syscfg_pctl_a: syscfg_pctl_a@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
@@ -159,9 +160,13 @@
#reset-cells = <1>;
};
- pio: pinctrl@0x10005000 {
+ /*
+* Pinctrl access register at 0x10005000 through regmap.
+* Register 0x1000b000 is used by EINT.
+*/
+ pio: pinctrl@10005000 {
compatible = "mediatek,mt8173-pinctrl";
- reg = <0 0x1000B000 0 0x1000>;
+ reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
pins-are-numbered;
gpio-controller;
@@ -169,8 +174,8 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = ,
- ,
- ;
+,
+;
};
sysirq: intpol-controller@10200620 {
--
1.8.1.1.dirty
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[PATCH 1/2] ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135.
From: Hongzhou Yang Matthias, Since mt8135 pinctrl node patch is not in v4.1-rc1, I'd like to make some minor change to follow dts convention. Let me know what you think. Thanks. Joe.C ---8< Add pinctrl,GPIO and EINT node to mt8135.dtsi. Signed-off-by: Yingjoe Chen Signed-off-by: Hongzhou Yang Acked-by: Linus Walleij --- arch/arm/boot/dts/mt8135-pinfunc.h | 1302 arch/arm/boot/dts/mt8135.dtsi | 31 + 2 files changed, 1333 insertions(+) create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h new file mode 100644 index 000..5a60987 --- /dev/null +++ b/arch/arm/boot/dts/mt8135-pinfunc.h @@ -0,0 +1,1302 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_MT8135_PINFUNC_H +#define __DTS_MT8135_PINFUNC_H + +#include + +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) + +#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) + +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) + +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_
Re: [PATCH 1/5] soc: mediatek: Add SMI driver
On Mon, 2015-03-09 at 22:56 +0100, Arnd Bergmann wrote: > On Monday 09 March 2015 11:26:52 Yingjoe Chen wrote: > > On Fri, 2015-03-06 at 18:48 +0800, yong...@mediatek.com wrote: > > > From: Yong Wu > > > > > > This patch add SMI(Smart Multimedia Interface) driver. This driver is > > > responsible to enable/disable iommu and control the clocks of each > > > local arbiter. > > > > > > Signed-off-by: Yong Wu > > > --- > > > drivers/soc/mediatek/Kconfig | 7 ++ > > > drivers/soc/mediatek/Makefile | 1 + > > > drivers/soc/mediatek/mt8173-smi.c | 143 > > > ++ > > > include/linux/mtk-smi.h | 40 +++ > > > 4 files changed, 191 insertions(+) > > > create mode 100644 drivers/soc/mediatek/mt8173-smi.c > > > create mode 100644 include/linux/mtk-smi.h > > > > > > > Hi Arnd, Matthias, > > > > For the SMI driver, we can't find a better place, so we put it in > > drivers/soc/mediatek now. Please let us know if you have any suggestion > > or concern. Thanks > > From what I understand from your description, I think it would better > fit in drivers/iommu. Another option is drivers/memory, which I think > is where the respective Tegra driver ended up. Hi Arnd, The description above only describe what is implemented now. Besides that, SMI HW also does: - Prioritize/arbitrate memory requests between different ports & larbs. - Bandwidth limiter - Performance monitor I think drivers/memory make more sense. I can't find info about drivers/memory in MAINTAINERS. Can this go through ARM SoC tree if we put SMI driver there? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] soc: mediatek: Add SMI driver
On Mon, 2015-03-09 at 18:59 +0100, Paul Bolle wrote: > Hi Yong, > > Yong Wu schreef op ma 09-03-2015 om 19:57 [+0800]: > > On Fri, 2015-03-06 at 12:30 +0100, Paul Bolle wrote: > > > On Fri, 2015-03-06 at 18:48 +0800, yong...@mediatek.com wrote: > > > > --- a/drivers/soc/mediatek/Kconfig > > > > +++ b/drivers/soc/mediatek/Kconfig > > > > @@ -20,3 +20,10 @@ config MT8173_PMIC_WRAP > > > > PMIC wrapper is a proprietary hardware in MT8173 to make > > > > communication protocols to access PMIC device. > > > > This driver implement access protocols for MT8173. > > > > + > > > > +config MTK_SMI > > > > +bool > > > > > > Nit: make this one tab instead of 8 spaces, please. > > > > > > > + help > > > > + Smi help enable/disable iommu in mt8173 and control the > > > > + clock of each local arbiter. > > > > + It should be true while MTK_IOMMU enable. > > > > > > I don't think anyone using the *config tools will ever see this text, as > > > there's no prompt. So you might as well make this a comment or drop it > > > altogether. > > > > > We could search it in the tool even though we don't see it. In next > > version, I will try to make it a comment. > > > Is this selected by more than just MTK_IOMMU (see 2/5)? If not, I think > > > MTK_SMI will be set and unset in lockstep with MTK_IOMMU. In other > > > words, you could as well use one Kconfig symbol. > > > > > if we disable MTK_IOMMU, the MTK_SMI also should be selected.That is > > because > > if the multimedia h/w want to work, the clock of the local arbiters always > > should be opened. > > This is a bit confusing, I'm afraid. Do you mean to say that it ought to > be possible for MTK_SMI to be 'y' even if MTK_IOMMU would be 'n'? The SMI can be configured to bypass IOMMU and send traffic directly to memory interface. It is possible to not use IOMMU and have display/MM to use continuous memory only. Besides MTK_IOMMU, we expect DRM, VDEC driver to select MTK_SMI as well. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] iommu/mediatek: Add mt8173 IOMMU driver
On Tue, 2015-03-10 at 02:00 +0900, Tomasz Figa wrote: > On Mon, Mar 9, 2015 at 11:46 PM, Yingjoe Chen > wrote: > > On Mon, 2015-03-09 at 20:11 +0900, Tomasz Figa wrote: > > <...> > >> > +/* > >> > + * pimudev is a global var for dma_alloc_coherent. > >> > + * It is not accepatable, we will delete it if "domain_alloc" is enabled > >> > + */ > >> > +static struct device *pimudev; > >> > >> This is indeed not acceptable. Could you replace dma_alloc_coherent() > >> with something that doesn't require device pointer, e.g. > >> alloc_pages()? (Although that would require you to handle cache > >> maintenance in the driver, due to cached memory allocated.) I need to > >> think about a better solution for this. > > > > Hi, > > > > For 2nd level page table, we use cached memory now. Currently we are > > using __dma_flush_range to flush the cache, which is also unacceptable. > > > > For proper cache management, we'll need to use dma_map_single or > > dma_sync_*, which still need a deivce*. > > Looking at how already mainlined drivers do this, they either use > dmac_flush_range() > (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/msm_iommu.c?id=refs/tags/v4.0-rc3#n80) > or directly __cpuc_flush_dcache_area() and outer_flush_range() > (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/rockchip-iommu.c?id=refs/tags/v4.0-rc3#n93). Hi, These only exist in arch/arm, not arm64. I think we should avoid using API start with __ in drivers. This driver might be used in both arm/arm64, I think the only option for us is DMA APIs. Actually, I'm thinking that we should change to use coherent memory for 2nd level page table as well and totally skip the cache flush. It seems dma_pool_create is suitable to replace kmem_cache we are using right now. However it still need a device*, which we have to fix anyway. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] iommu/mediatek: Add mt8173 IOMMU driver
On Mon, 2015-03-09 at 20:11 +0900, Tomasz Figa wrote: <...> > > +/* > > + * pimudev is a global var for dma_alloc_coherent. > > + * It is not accepatable, we will delete it if "domain_alloc" is enabled > > + */ > > +static struct device *pimudev; > > This is indeed not acceptable. Could you replace dma_alloc_coherent() > with something that doesn't require device pointer, e.g. > alloc_pages()? (Although that would require you to handle cache > maintenance in the driver, due to cached memory allocated.) I need to > think about a better solution for this. Hi, For 2nd level page table, we use cached memory now. Currently we are using __dma_flush_range to flush the cache, which is also unacceptable. For proper cache management, we'll need to use dma_map_single or dma_sync_*, which still need a deivce*. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] soc: mediatek: Add SMI driver
On Fri, 2015-03-06 at 18:48 +0800, yong...@mediatek.com wrote: > From: Yong Wu > > This patch add SMI(Smart Multimedia Interface) driver. This driver is > responsible to enable/disable iommu and control the clocks of each > local arbiter. > > Signed-off-by: Yong Wu > --- > drivers/soc/mediatek/Kconfig | 7 ++ > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mt8173-smi.c | 143 > ++ > include/linux/mtk-smi.h | 40 +++ > 4 files changed, 191 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8173-smi.c > create mode 100644 include/linux/mtk-smi.h > Hi Arnd, Matthias, For the SMI driver, we can't find a better place, so we put it in drivers/soc/mediatek now. Please let us know if you have any suggestion or concern. Thanks You can find more description about SMI and how we use it in the cover letter: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/328451.html Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] arm64: mediatek: Add config option for mt8173.
On Wed, 2015-03-04 at 10:53 +0100, Arnd Bergmann wrote: > On Wednesday 04 March 2015 10:31:07 Yingjoe Chen wrote: > > Hi, > > > > Since we support devicetree, we don't need MACH_* to build a working > > kernel. This is true even for our v7 soc. We intend to use it to reduce > > numbers of drivers in product kernel binary. > > Most drivers are shared among the same SoCs family, but some are not. > > Currently for pinctrl driver, we are doing this so user don't need to > > select them one by one: > > > > config PINCTRL_MT8173 > > def_bool MACH_MT8173 > > select PINCTRL_MTK_COMMON > > > > Alternatively, we could add these MACH_* to some other places, eg, > > drivers/soc/mediatek. Or we don't add MACH_* at all, and have all > > drivers export their own Kconfig option. User will need to select each > > of them one-by-one. > > > > What do you think? > > I would rather see these as user-selectable options, which has the > other benefit of giving compile-time coverage. For your example, > I'd suggest doing > > config PINCTRL_MT8173 > bool "Mediatek MT8173 pin control" > depends on ARCH_MEDIATEK || COMPILE_TEST > select PINCTRL_MTK_COMMON > help > ... a useful description ... > OK, I'll send a new patch to do this. Thanks. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] arm64: mediatek: Add config option for mt8173.
On Wed, 2015-02-25 at 11:11 +, Catalin Marinas wrote: > On Wed, Feb 25, 2015 at 11:51:57AM +0100, Arnd Bergmann wrote: > > On Wednesday 25 February 2015 17:07:22 Yingjoe Chen wrote: > > > On Tue, 2015-01-27 at 15:13 +0800, Hongzhou Yang wrote: > > > > From: Hongzhou Yang > > > > > > > > The upcoming MTK pinctrl driver have a big pin table for each SoC, > > > > and we don't want to bloat the kernel binary if we don't need it. > > > > Add config options so we can build for one SoC only. > > > > > > > > Signed-off-by: Hongzhou Yang > > > > --- > > > > arch/arm64/Kconfig | 6 ++ > > > > 1 file changed, 6 insertions(+) > > > > > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > > > > index e627ead..6213dac 100644 > > > > --- a/arch/arm64/Kconfig > > > > +++ b/arch/arm64/Kconfig > > > > @@ -151,9 +151,15 @@ menu "Platform selection" > > > > config ARCH_MEDIATEK > > > > bool "Mediatek MT65xx & MT81xx ARMv8 SoC" > > > > select ARM_GIC > > > > + select PINCTRL > > > > help > > > > Support for Mediatek MT65xx & MT81xx ARMv8 SoCs > > > > > > > > +config MACH_MT8173 > > > > + bool "Mediatek 8173 Soc Supprt" > > > > + depends on ARCH_MEDIATEK > > > > + default y > > > > + > > > > config ARCH_SEATTLE > > > > bool "AMD Seattle SoC Family" > > > > help > > > > > > Hi Arnd/Matthias, > > > > > > Any comments on this patch? > > > > Hi Joe, > > > > Actually I just commented on a similar patch from Samsung the other > > day, and I think we should make a more general decision about these: > > > > I would rather see only one Kconfig option per SoC family and use > > ARCH_MEDIATEK without any MACH_* options. We can have other options > > for e.g. networking chips from Mediatek that are not closely related > > but I would group all the phone and tablet chips under one option > > here. Same for the other vendors of course. > > I agree. > Hi, Since we support devicetree, we don't need MACH_* to build a working kernel. This is true even for our v7 soc. We intend to use it to reduce numbers of drivers in product kernel binary. Most drivers are shared among the same SoCs family, but some are not. Currently for pinctrl driver, we are doing this so user don't need to select them one by one: config PINCTRL_MT8173 def_bool MACH_MT8173 select PINCTRL_MTK_COMMON Alternatively, we could add these MACH_* to some other places, eg, drivers/soc/mediatek. Or we don't add MACH_* at all, and have all drivers export their own Kconfig option. User will need to select each of them one-by-one. What do you think? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] arm64: mediatek: Add config option for mt8173.
On Tue, 2015-01-27 at 15:13 +0800, Hongzhou Yang wrote: > From: Hongzhou Yang > > The upcoming MTK pinctrl driver have a big pin table for each SoC, > and we don't want to bloat the kernel binary if we don't need it. > Add config options so we can build for one SoC only. > > Signed-off-by: Hongzhou Yang > --- > arch/arm64/Kconfig | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index e627ead..6213dac 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -151,9 +151,15 @@ menu "Platform selection" > config ARCH_MEDIATEK > bool "Mediatek MT65xx & MT81xx ARMv8 SoC" > select ARM_GIC > + select PINCTRL > help > Support for Mediatek MT65xx & MT81xx ARMv8 SoCs > > +config MACH_MT8173 > + bool "Mediatek 8173 Soc Supprt" > + depends on ARCH_MEDIATEK > + default y > + > config ARCH_SEATTLE > bool "AMD Seattle SoC Family" > help Hi Arnd/Matthias, Any comments on this patch? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/7] pinctrl: mediatek: emulate GPIO interrupt on both-edges
On Tue, 2015-02-10 at 09:40 +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Jan 27, 2015 at 02:15:26PM +0800, Chaotian Jing wrote:
> > From: Yingjoe Chen
> >
> > MTK EINT does not support generating interrupt on both edges.
> > Emulate this by changing edge polarity while enable irq,
> > set types and interrupt handling. This follows an example of
> > drivers/gpio/gpio-mxc.c.
<...>
> > +static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
> > +{
> > + int start_level, curr_level;
> > + unsigned int reg_offset;
> > + const struct mtk_eint_offsets *eint_offsets =
> > &(pctl->devdata->eint_offsets);
> > + u32 mask = 1 << (hwirq & 0x1f);
> > + u32 port = (hwirq >> 5) & eint_offsets->port_mask;
> > + void __iomem *reg = pctl->eint_reg_base + (port << 2);
> > + const struct mtk_desc_pin *pin;
> > +
> > + pin = mtk_find_pin_by_eint_num(pctl, hwirq);
> > + curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
> > + do {
> > + start_level = curr_level;
> > + if (start_level)
> > + reg_offset = eint_offsets->pol_clr;
> > + else
> > + reg_offset = eint_offsets->pol_set;
> > + writel(mask, reg + reg_offset);
> > +
> > + curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
> > + } while (start_level != curr_level);
> > +
> > + return start_level;
> > +}
> > +
> > static void mtk_eint_mask(struct irq_data *d)
> > {
> > struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
> > @@ -814,6 +840,9 @@ static void mtk_eint_unmask(struct irq_data *d)
> > eint_offsets->mask_clr);
> >
> > writel(mask, reg);
> > +
> > + if (pctl->eint_dual_edges[d->hwirq])
> > + mtk_eint_flip_edge(pctl, d->hwirq);
> > }
> From looking at the code it seems to me that there is a bug. Consider
> the following to happen:
>
> pin changes level, say high to low, triggers irq
>
> irq is masked by writel(mask, reg) in mtk_eint_mask
>
> mtk_eint_flip_edge gets curr_level = low
>
> pin goes up
>
> writel(mask, reg + eint_offsets->pol_set);
>
> oh, pin is high, so: writel(mask, reg + eint_offsets->pol_clr
>
> So now you trigger the irq the next time when the pin goes down again.
> But that means to missed to trigger on the "pin goes up" in the above
> list, right?
Hi Uwe,
Yes, this could be a problem when irq happen. So I fix/workaround this
in mtk_eint_irq_handler() using soft-irq. When this bit is set, eint
will trigger the same interrupt again.
+ if (dual_edges) {
+ curr_level = mtk_eint_flip_edge(pctl, index);
+
+ /* If level changed, we might lost one edge
+ interrupt, raised it through soft-irq */
+ if (start_level != curr_level)
+ writel(BIT(offset), reg -
+ eint_offsets->stat +
+ eint_offsets->soft_set);
+ }
Joe.C
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Re: [PATCH v5 1/5] ARM: mediatek: Add config options for mediatek SoCs.
Hi,
On Tue, 2015-01-27 at 11:16 +0100, Paul Bolle wrote:
> Joe,
>
> On Thu, 2015-01-22 at 13:54 +0100, Matthias Brugger wrote:
> > 2015-01-21 6:28 GMT+01:00 Hongzhou Yang :
> > > From: Yingjoe Chen
> > >
> > > The upcoming MTK pinctrl driver have a big pin table for each SoC
> > > and we don't want to bloat the kernel binary if we don't need it.
> > > Add config options so we can build for one SoC only.
> > >
> > > Acked-by: Linus Walleij
> > > Signed-off-by: Yingjoe Chen
> > > Signed-off-by: Hongzhou Yang
> >
> > Applied to v3.20-next/soc
>
> This became commit ad8a221e1f49 ("ARM: mediatek: Add config options for
> mediatek SoCs.") in today's linux-next (ie, next-20150127). I noticed
> because a script I use to check linux-next spotted a problem with it.
>
> > > ---
> > > arch/arm/mach-mediatek/Kconfig | 22 +-
> > > 1 file changed, 21 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/mach-mediatek/Kconfig
> > > b/arch/arm/mach-mediatek/Kconfig
> > > index f73f588..f7e463c 100644
> > > --- a/arch/arm/mach-mediatek/Kconfig
> > > +++ b/arch/arm/mach-mediatek/Kconfig
> > > @@ -1,6 +1,26 @@
> > > -config ARCH_MEDIATEK
> > > +menuconfig ARCH_MEDIATEK
> > > bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> > > select ARM_GIC
> > > select MTK_TIMER
> > > help
> > > Support for Mediatek MT65xx & MT81xx SoCs
> > > +
> > > +if ARCH_MEDIATEK
> > > +
> > > +config MACH_MT6589
> > > + bool "MediaTek MT6589 SoCs support"
> > > + default ARCH_MEDIATEK
> > > +
> > > +config MACH_MT6592
> > > + bool "MediaTek MT6592 SoCs support"
> > > + default ARCH_MEDIATEK
> > > +
> > > +config MACH_MT8127
> > > + bool "MediaTek MT8127 SoCs support"
> > > + default ARCH_MEDIATEK
> > > +
> > > +config MACH_MT8135
> > > + bool "MediaTek MT8135 SoCs support"
> > > + default ARCH_MEDIATEK
> > > +
> > > +endif
>
> None of these four new MACH_MT* Kconfig symbols are currently used in
> linux-next. I assume that patches that actually use them (either as a
> Kconfig symbol or as a CONFIG_* macro) are still pending. Is that
> correct?
Yes, it is used in patch 3 in this series[1], and is discussed in [2].
Joe.C
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/318453.html
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315616.html
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Re: [PATCH v4 2/2] I2C: mediatek: Add driver for MediaTek I2C controller
Hi,
On Wed, 2015-01-21 at 16:31 +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Wed, Jan 21, 2015 at 08:49:40PM +0800, Yingjoe Chen wrote:
> > On Wed, 2015-01-21 at 09:15 +0100, Uwe Kleine-König wrote:
<...>
> > > > > > > +static int mtk_i2c_remove(struct platform_device *pdev)
> > > > > > > +{
> > > > > > > + struct mtk_i2c *i2c = platform_get_drvdata(pdev);
> > > > > > > +
> > > > > > > + i2c_del_adapter(&i2c->adap);
> > > > > > > + free_i2c_dma_bufs(i2c);
> > > > > > > + platform_set_drvdata(pdev, NULL);
> > > > > > > +
> > > > > > Here you need to make sure that no irq is running when
> > > > > > i2c_del_adapter
> > > > > > is called.
> > > > > OK, add check here
> > > >
> > > > I thought after i2c_del_adapter() is complete, all i2c_transfer for this
> > > > adapter is completed. If this is true, then i2c clock is already off and
> > > > we won't have any on-going transfer/pending irq.
> > > Consider that there is an ongoing transaction and before it completes
> > > the adapter-device is unbound from the driver. Then i2c_del_adapter is
> > > called which frees the resources managed by the core, then the device's
> > > completion irq triggers and the freed adapter is used which probably
> > > results in an oops.
> >
> > Not sure if I missed anything. i2c_transfer() is a synchronize call. If
> > we fixed timeout issue you mentioned in mtk_i2c_transfer(), it will turn
> > off clock before it return, which disable any transaction and clear all
> > pending irq.
> There is no synchronization to prevent unbinding the i2c-bus device
> while there is a i2c transfer on the wire. i2c_del_adapter only takes
> i2c-core.c's &core_lock while i2c_transfer takes &adapter->bus_lock.
> If you want to test for it: do something like that:
>
> while true; do dd if=/sys/bus/i2c/.../eeprom of=/dev/null; done
>
> and while this is running do:
>
> cd /sys/bus/platform/drivers/mt-i2c
> while true; do
> echo 1100d000.i2c > unbind;
> sleep 1;
> echo 1100d000.i2c > bind;
> sleep 1;
> done
>
> > Your scenario can only happens when one thread is still running in
> > i2c_transfer/algo->master_xfer and the other thread is trying to remove
> > the device. If that happened, then every device data access in
> > mtk_i2c_transfer might cause oops. I looked at some i2c drivers and
> > can't find any checking for this case, I can't find anything prevent i2c
> > device removal before pending i2c_transfer complete either. Would you
> > give me an example?
> I just noticed that even "my" driver is affected. If the above recipe
> makes your driver barf there is something to fix, if not ... hmm, then
> maybe there is more synchronization than I'm aware of or my recipe is
> wrong.
>
> At least another driver author believed me:
> http://thread.gmane.org/gmane.linux.drivers.i2c/21531/focus=21662
If there is no synchronization mechanism then every driver is affected.
We should add the check in the core instead of fixing it in every
driver. We could take the bus_lock in i2c_del_adapter() and check if the
adapter is removed in __i2c_transfer(), this should fix the problem.
Wolfram, what do you think about this? Is there anything we are missing?
Joe.C
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Re: [PATCH v4 2/2] I2C: mediatek: Add driver for MediaTek I2C controller
On Wed, 2015-01-21 at 09:15 +0100, Uwe Kleine-König wrote:
> Hello,
>
> On Wed, Jan 21, 2015 at 02:30:09PM +0800, Yingjoe Chen wrote:
> > On Wed, 2015-01-21 at 11:13 +0800, Eddie Huang wrote:
> > <...>
> > > > > + ret = -EINVAL;
> > > > > + goto err_exit;
> > > > > + }
> > > > > +
> > > > > + if (msgs->buf == NULL) {
> > > > > + dev_dbg(i2c->dev, " data buffer is NULL.\n");
> > > > > + ret = -EINVAL;
> > > > > + goto err_exit;
> > > > > + }
> > > > > +
> > > > > + i2c->addr = msgs->addr;
> > > > > + i2c->msg_len = msgs->len;
> > > > > + i2c->msg_buf = msgs->buf;
> > > > > +
> > > > > + if (msgs->flags & I2C_M_RD)
> > > > > + i2c->op = I2C_MASTER_RD;
> > > > > + else
> > > > > + i2c->op = I2C_MASTER_WR;
> > > > > +
> > > > > + /* combined two messages into one transaction */
> > > > > + if (num > 1) {
> > > > > + i2c->msg_aux_len = (msgs + 1)->len;
> > > > > + i2c->op = I2C_MASTER_WRRD;
> > > > > + }
> > > > This means "write then read", right? You should check here that the
> > > > first message is really a write and the 2nd a read then.
> > > > Can this happen at all with the quirks defined below (.max_num_msgs =
> > > > 1)?
> > > Yes, mean write then read. Indeed, add check is better.
> > > If msg number is 1, means normal write or read, not "write then read".
> >
> > The quirks will increase the message count and check 'write then read'
> > for us. We don't have to add check here.
> I have to admit I don't know that quirks stuff, so it's well possible
> that I'm wrong here.
>
> > > > > +static int mtk_i2c_remove(struct platform_device *pdev)
> > > > > +{
> > > > > + struct mtk_i2c *i2c = platform_get_drvdata(pdev);
> > > > > +
> > > > > + i2c_del_adapter(&i2c->adap);
> > > > > + free_i2c_dma_bufs(i2c);
> > > > > + platform_set_drvdata(pdev, NULL);
> > > > > +
> > > > Here you need to make sure that no irq is running when i2c_del_adapter
> > > > is called.
> > > OK, add check here
> >
> > I thought after i2c_del_adapter() is complete, all i2c_transfer for this
> > adapter is completed. If this is true, then i2c clock is already off and
> > we won't have any on-going transfer/pending irq.
> Consider that there is an ongoing transaction and before it completes
> the adapter-device is unbound from the driver. Then i2c_del_adapter is
> called which frees the resources managed by the core, then the device's
> completion irq triggers and the freed adapter is used which probably
> results in an oops.
Not sure if I missed anything. i2c_transfer() is a synchronize call. If
we fixed timeout issue you mentioned in mtk_i2c_transfer(), it will turn
off clock before it return, which disable any transaction and clear all
pending irq.
Your scenario can only happens when one thread is still running in
i2c_transfer/algo->master_xfer and the other thread is trying to remove
the device. If that happened, then every device data access in
mtk_i2c_transfer might cause oops. I looked at some i2c drivers and
can't find any checking for this case, I can't find anything prevent i2c
device removal before pending i2c_transfer complete either. Would you
give me an example?
Joe.C
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Re: [PATCH v4 2/2] I2C: mediatek: Add driver for MediaTek I2C controller
Hi Uwe,
Thanks for your review,
On Wed, 2015-01-21 at 11:13 +0800, Eddie Huang wrote:
<...>
> > > + ret = -EINVAL;
> > > + goto err_exit;
> > > + }
> > > +
> > > + if (msgs->buf == NULL) {
> > > + dev_dbg(i2c->dev, " data buffer is NULL.\n");
> > > + ret = -EINVAL;
> > > + goto err_exit;
> > > + }
> > > +
> > > + i2c->addr = msgs->addr;
> > > + i2c->msg_len = msgs->len;
> > > + i2c->msg_buf = msgs->buf;
> > > +
> > > + if (msgs->flags & I2C_M_RD)
> > > + i2c->op = I2C_MASTER_RD;
> > > + else
> > > + i2c->op = I2C_MASTER_WR;
> > > +
> > > + /* combined two messages into one transaction */
> > > + if (num > 1) {
> > > + i2c->msg_aux_len = (msgs + 1)->len;
> > > + i2c->op = I2C_MASTER_WRRD;
> > > + }
> > This means "write then read", right? You should check here that the
> > first message is really a write and the 2nd a read then.
> > Can this happen at all with the quirks defined below (.max_num_msgs =
> > 1)?
> Yes, mean write then read. Indeed, add check is better.
> If msg number is 1, means normal write or read, not "write then read".
The quirks will increase the message count and check 'write then read'
for us. We don't have to add check here.
<...>
> > > +static int mtk_i2c_remove(struct platform_device *pdev)
> > > +{
> > > + struct mtk_i2c *i2c = platform_get_drvdata(pdev);
> > > +
> > > + i2c_del_adapter(&i2c->adap);
> > > + free_i2c_dma_bufs(i2c);
> > > + platform_set_drvdata(pdev, NULL);
> > > +
> > Here you need to make sure that no irq is running when i2c_del_adapter
> > is called.
> OK, add check here
I thought after i2c_del_adapter() is complete, all i2c_transfer for this
adapter is completed. If this is true, then i2c clock is already off and
we won't have any on-going transfer/pending irq.
Joe.C
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Re: [PATCH v5 0/5] Add Mediatek SoC Pinctrl/GPIO/EINT driver for MT8135.
On Wed, 2015-01-21 at 13:28 +0800, Hongzhou Yang wrote: > This is v5 of add Mediatek SoC Pinctrl/GPIO/EINT driver for MT8135. > It is based on Joe.C' basic device tree support. > See > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296093.html Hi, A little correction. I just talked to Hongzhou, this series is based on 3.19-rc1 instead of my old patch. Sorry for the confusion. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer wrote:
> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>
> >> > You often talk about ambiguities. Could you give an example what
> >> > ambiguities you mean?
> >>
> >> What happened was this pins = ; arguments were sometimes
> >> strings and sometimes integers, that becomes strange to handle
> >> in code, ambiguous.
> >
> > I see. I like naming it 'pinmux' because that's what it is: pins and
> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> > without mux setting. How about 'pin-no-mux'? We also could add an
> > explicit "pins-are-numbered" property instead of distinguishing this
> > by property names.
>
> I kind of like this "pins-are-numbered" thing.
>
> The other property for the pin, whether pinmux or pin-no-mux or
> pin-num-and-mux etc is no such big deal, as long as it's
> consistent and documented with the generic bindings.
Hi Linus,
To make sure I understand it correct, you think something like this is
OK?
pinctrl@01c20800 {
compatible = "mediatek,mt8135-pinctrl";
[...]
pins-are-numbered;
i2c0_pins_a: i2c0@0 {
pins1 {
pins = ,
;
bias-disable;
};
};
[]
}
Joe.C
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Re: [PATCH v4 4/5] ARM: mediatek: Add EINT support to MTK pinctrl driver.
On Thu, 2015-01-15 at 18:30 +0100, Linus Walleij wrote: > On Wed, Jan 14, 2015 at 3:32 AM, Yingjoe Chen > wrote: > > > Let's me describe my problem more clearly. On our SoC, if a pin support > > interrupt it will have 2 different numbers for it. For examples, here's > > a partial list for the gpio and EINT number mappings on mt8135: > > > >gpio EINT > > 0 49 > > 1 48 > > ... > > 36 97 > > 37 19 > > ... > > > > To control interrupt related function, we'll need EINT number to locate > > corresponding register bits. When interrupt occurs, the interrupt > > handler will know which EINT interrupt occurs. In irq_chip functions, > > only .irq_request_resources and .irq_release_resources use gpio number > > to set pinmux to EINT mode and all the others need EINT number. > > > > Because EINT number is used more frequently in interrupt related > > functions, it make sense to use EINT number as hwirq instead of gpio > > number. That means irq_domain will translate EINT number to virq. > > So what mtk_gpio_to_irq actually do is translate gpio number to EINT > > number and use irq domain to translate it to virq. > > But the EINT is not a hardware number is it? It is a hardware number. eg, to mask irq for the gpio 0 above, we have to set bit49 in EINT mask_set register. When this irq triggered, it is reported using EINT status register bit49. We can find out EINT number for a GPIO using mtk_desc_pin tables. In drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h, for GPIO0, we can see its EINT is 49 and must set to function 2 for EINT. I believe this is similar to sunxi. MTK_PIN( PINCTRL_PIN(0, "MSDC0_DAT7"), "D21", "mt8135", MTK_EINT_FUNCTION(2, 49), MTK_FUNCTION(0, "GPIO0"), MTK_FUNCTION(1, "MSDC0_DAT7"), MTK_FUNCTION(2, "EINT49"), MTK_FUNCTION(3, "I2SOUT_DAT"), MTK_FUNCTION(4, "DAC_DAT_OUT"), MTK_FUNCTION(5, "PCM1_DO"), MTK_FUNCTION(6, "SPI1_MO"), MTK_FUNCTION(7, "NALE") ), Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/5] ARM: mediatek: Add config options for mediatek SoCs.
On Tue, 2015-01-13 at 10:43 +0100, Linus Walleij wrote: > On Wed, Dec 17, 2014 at 12:34 AM, Hongzhou Yang > wrote: > > > From: Yingjoe Chen > > > > The upcoming MTK pinctrl driver have a big pin table for each SoC > > and we don't want to bloat the kernel binary if we don't need it. > > Add config options so we can build for one SoC only. > > > > Signed-off-by: Yingjoe Chen > > Signed-off-by: Hongzhou Yang > > Acked-by: Linus Walleij > > I guess this goes directly to the ARM SoC tree. As it is only > Kconfig symbols it should be OK to merge out-of-order. > Hi Matthias, Since this one is in arch/arm/mach-mediatek, can you take it? Links for original post in case you can't find it. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/311181.html Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/5] ARM: mediatek: Add EINT support to MTK pinctrl driver.
On Tue, 2015-01-13 at 14:24 +0100, Linus Walleij wrote:
> On Tue, Jan 6, 2015 at 10:16 AM, Yingjoe Chen
> wrote:
> > On Wed, 2014-12-17 at 17:09 +0800, Yingjoe Chen wrote:
> >> On Wed, 2014-12-17 at 07:34 +0800, Hongzhou Yang wrote:
> >> > From: Maoguang Meng
> >> >
> >> > MTK SoC support external interrupt(EINT) from most SoC pins.
> >> > Add EINT support to pinctrl driver.
> >> >
> >> > Signed-off-by: Maoguang Meng
> >> > Signed-off-by: Hongzhou Yang
> >>
> >> Hi Linus,
> >>
> >> This patch add EINT support to the pinctrl driver. We've surveyed
> >> GPIOLIB_IRQCHIP, but we didn't use it because:
> >>
> >> - Not every GPIO pin support interrupt.
> >> - EINT use a different numbering to GPIO. eg, from the mt8135 table,
> >> GPIO29 is EINT158. It is more nature & efficient to use EINT number as
> >> hwirq.
> >>
> >> + MTK_EINT_FUNCTION(2, 158),
> >> + MTK_FUNCTION(0, "GPIO29"),
> >
> > After further looking into this, we could use GPIOLIB_IRQCHIP if we add
> > an extension gpiochip_irqchip_add() to accept interrupt numbers and
> > custom .to_irq function for our SoC. We could still reuse other code
> > GPIOLIB_IRQCHIP provide.
>
> I see, and I still want to see all possibilities to centralize code
> surveyed.
>
> If I understand correctly what you actually need is a linear
> irqdomain with "holes" (invalid offsets) in it.
> So this is what we should design for.
>
> The .to_irq() function should not really perform anything but a
> simple lookup in the domain.
>
> What you do here:
>
> +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> +{
> + const struct mtk_desc_pin *pin;
> + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> + int irq;
> +
> + pin = pctl->devdata->pins + offset;
> + if (pin->eint.eintnum == NO_EINT_SUPPORT)
> + return -EINVAL;
> +
> + irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
> + if (!irq)
> + return -EINVAL;
> +
> + return irq;
> +}
>
> Is *avoiding* to translate some IRQs from a certain offset using
> the domain, I think that is the wrong way to go.
Hi Linus,
Yes, it have holes and avoiding translate some gpio to irq, but it also
using a different hwirq number to do the translate.
Let's me describe my problem more clearly. On our SoC, if a pin support
interrupt it will have 2 different numbers for it. For examples, here's
a partial list for the gpio and EINT number mappings on mt8135:
gpio EINT
0 49
1 48
...
36 97
37 19
...
To control interrupt related function, we'll need EINT number to locate
corresponding register bits. When interrupt occurs, the interrupt
handler will know which EINT interrupt occurs. In irq_chip functions,
only .irq_request_resources and .irq_release_resources use gpio number
to set pinmux to EINT mode and all the others need EINT number.
Because EINT number is used more frequently in interrupt related
functions, it make sense to use EINT number as hwirq instead of gpio
number. That means irq_domain will translate EINT number to virq.
So what mtk_gpio_to_irq actually do is translate gpio number to EINT
number and use irq domain to translate it to virq.
Below is a draft of what I have in mind. For SoC that can use gpio
number to control irq they still use gpiochip_irqchip_add(). For SoC
that need to use another number to control irq, like us, can use
gpiochip_irqchip_add_with_map. We can't reuse gpiochip_to_irq or
gpiochip_irq_reqres/relres in GPIOLIB_IRQCHIP, but we can still reuse
others code.
Let me know if this is the direction you want.
Thanks
Joe.C
===
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -567,11 +567,14 @@ static void gpiochip_irqchip_remove(struct
gpio_chip *gpiochip)
* the pins on the gpiochip can generate a unique IRQ. Everything else
* need to be open coded.
*/
-int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
-struct irq_chip *irqchip,
-unsigned int first_irq,
-irq_flow_handler_t handler,
-unsigned int type)
+int gpiochip_irqchip_add_with_map(struct gpio_chip *gpiochip,
+ struct irq_chip *irqchip,
+ unsigned int first_irq,
+ irq_flow_handler_t handler,
+ unsigned int type,
+ unsigned int
Re: [PATCH v3 0/2] ARM: mediatek: Add driver for Mediatek I2C controller
On Tue, 2015-01-13 at 10:57 +0100, Wolfram Sang wrote: > On Tue, Jan 06, 2015 at 02:37:53PM +0100, Wolfram Sang wrote: > > > > > We've started upstream work for MT8173[1]. > > > > > > We've fixed these issues for new SoC, and we believe it is fully I2C > > > compatible now. We'll add mt8173 support to this driver, so this driver > > > will support both fully I2C compatible SoC and the current one. > > > > From what you tell, I'd rather add the MT8173 support incrementally. > > Let's get first the limited support properly implemented, then add > > another controller. > > > > I'll send out my draft for describing the quirks later today. > > What do you think about my two proposals? I think the quirks can describe our HW limitation without issue. We are porting our i2c driver base on that. Will let you know the test result. Thanks Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/5] ARM: mediatek: Add EINT support to MTK pinctrl driver.
On Wed, 2014-12-17 at 17:09 +0800, Yingjoe Chen wrote: > On Wed, 2014-12-17 at 07:34 +0800, Hongzhou Yang wrote: > > From: Maoguang Meng > > > > MTK SoC support external interrupt(EINT) from most SoC pins. > > Add EINT support to pinctrl driver. > > > > Signed-off-by: Maoguang Meng > > Signed-off-by: Hongzhou Yang > > Hi Linus, > > This patch add EINT support to the pinctrl driver. We've surveyed > GPIOLIB_IRQCHIP, but we didn't use it because: > > - Not every GPIO pin support interrupt. > - EINT use a different numbering to GPIO. eg, from the mt8135 table, > GPIO29 is EINT158. It is more nature & efficient to use EINT number as > hwirq. > > + MTK_EINT_FUNCTION(2, 158), > + MTK_FUNCTION(0, "GPIO29"), Hi Linus, After further looking into this, we could use GPIOLIB_IRQCHIP if we add an extension gpiochip_irqchip_add() to accept interrupt numbers and custom .to_irq function for our SoC. We could still reuse other code GPIOLIB_IRQCHIP provide. Please let me know what you think about this idea. Thanks. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 3/4] ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
Hi Matthias, On Tue, 2014-11-25 at 16:04 +0800, Yingjoe Chen wrote: > Add sysirq settings for mt6589/mt8135/mt8127 > This also correct timer interrupt flag. The old setting works > because boot loader already set polarity for timer interrupt. > Without intpol support, the setting was not changed so gic > can get the irq correctly. > > Signed-off-by: Yingjoe Chen > --- > arch/arm/boot/dts/mt6589.dtsi | 14 -- > arch/arm/boot/dts/mt8127.dtsi | 14 -- > arch/arm/boot/dts/mt8135.dtsi | 14 -- > 3 files changed, 36 insertions(+), 6 deletions(-) It seems this patch is not merged in 3.19-rc1. This do have dependency on other patches, and all the other patches in this series are merged. Is this planed to merge later or do we need to send additional pull request for it? Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/5] ARM: mediatek: Add EINT support to MTK pinctrl driver.
On Wed, 2014-12-17 at 07:34 +0800, Hongzhou Yang wrote: > From: Maoguang Meng > > MTK SoC support external interrupt(EINT) from most SoC pins. > Add EINT support to pinctrl driver. > > Signed-off-by: Maoguang Meng > Signed-off-by: Hongzhou Yang Hi Linus, This patch add EINT support to the pinctrl driver. We've surveyed GPIOLIB_IRQCHIP, but we didn't use it because: - Not every GPIO pin support interrupt. - EINT use a different numbering to GPIO. eg, from the mt8135 table, GPIO29 is EINT158. It is more nature & efficient to use EINT number as hwirq. + MTK_EINT_FUNCTION(2, 158), + MTK_FUNCTION(0, "GPIO29"), Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/2] ARM: mediatek: Add driver for Mediatek I2C controller
On Thu, 2014-11-27 at 17:45 +0100, Wolfram Sang wrote: > > > I think there are now 3 drivers in my queue which are not fully I2C > > > compatible but more supporting the very minimum to, say, read an eeprom. > > > I am not feeling well to allow them to use I2C_FUNC_I2C. So, I want to > > > think about ways how to communicate deficiencies like "only 255 byte" or > > > "only WRRD messages" to users of that I2C controller. This is most > > > likely not happening before 3.19. But assistance is very welcome. Hi Wolfram, We've started upstream work for MT8173[1]. We've fixed these issues for new SoC, and we believe it is fully I2C compatible now. We'll add mt8173 support to this driver, so this driver will support both fully I2C compatible SoC and the current one. Joe.C [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/309847.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] irqchip: mediatek: Add support for mt8173
Hi Arnd,
On Wed, 2014-12-10 at 12:00 +0100, Arnd Bergmann wrote:
> On Wednesday 10 December 2014 18:50:00 Eddie Huang wrote:
> > From: Yingjoe Chen
> >
> > MT8173 intpol have 32 more irq pins, add support to it.
> >
> > Signed-off-by: Yingjoe Chen
> > Signed-off-by: Eddie Huang
> >
>
> How about adding a property for the number of irq pins and leave the
> old compatible string in place? I don't think it would be good if
> we have to update this driver for each new SoC that uses this
> irqchip just to change one number.
>
> Arnd
OK, I'll change to something like this in next version:
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
@@ -17,12 +17,17 @@ Required properties:
use the same interrupt-cells format as GIC.
- reg: Physical base address of the intpol registers and length of memory
mapped region.
+Optional properties:
+- mediatek,intpol-number: The number of interrupts supported by intpol,
+ default 224 if omitted.
+
Example:
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200100 0 0x1c>;
+ mediatek,intpol-number = <224>;
};
Joe.C
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Re: [PATCH 3/4] arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile
Hi,
On Wed, 2014-12-10 at 18:50 +0800, Eddie Huang wrote:
<...>
> diff --git a/arch/arm64/boot/dts/mt8173-evb.dts
> b/arch/arm64/boot/dts/mt8173-evb.dts
> new file mode 100644
> index 000..adf26dd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mt8173-evb.dts
<...>
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <1 13 0x8>,
> + <1 14 0x8>,
> + <1 11 0x8>,
> + <1 10 0x8>;
> + clock-frequency = <1300>;
I believe our firmware doesn't need this line. Please remove it.
Joe.C
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Re: [PATCH v8 2/4] ARM: mediatek: Add sysirq interrupt polarity support
On Sat, 2014-11-29 at 18:40 +0100, Beniamino Galvani wrote:
> On Tue, Nov 25, 2014 at 04:04:20PM +0800, Yingjoe Chen wrote:
> > Mediatek SoCs have interrupt polarity support in sysirq which
> > allows to invert polarity for given interrupt. Add this support
> > using hierarchy irq domain.
> >
> > [...]
> >
> > +static int __init mtk_sysirq_of_init(struct device_node *node,
> > +struct device_node *parent)
> > +{
> > + struct irq_domain *domain, *domain_parent;
> > + struct mtk_sysirq_chip_data *chip_data;
> > + int ret = 0;
> > +
> > + domain_parent = irq_find_host(parent);
> > + if (!domain_parent) {
> > + pr_err("mtk_sysirq: interrupt-parent not found\n");
> > + return -EINVAL;
> > + }
> > +
> > + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> > + if (!chip_data)
> > + return -ENOMEM;
> > +
> > + chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
> > + if (!chip_data->intpol_base) {
>
> Hi,
>
> you should use IS_ERR() to check the return value here.
Thanks for catching this. I think this is merged, so I'll prepare a new
patch to fix this.
Joe.C
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Re: [PATCH v3 0/2] ARM: mediatek: Add driver for Mediatek I2C controller
Hi, On Mon, 2014-11-24 at 13:15 +0100, Wolfram Sang wrote: > Hi, > > some very high level remarks: > > On Mon, Nov 24, 2014 at 05:38:46PM +0800, Xudong Chen wrote: > > This series is the third version of Mediatek SoCs I2C controller common > > bus driver. > > Compared to the second version, > > 1. Add comments for clock in dt-bindings file i2c-mt6577.txt. > > 2. Remove mt8135.dtsi because of the dependency on pinctrl and clock. > > 3. Encode the feature have-dcm in i2c-mt65xx.c by checking the compatible. > > > > This driver is based on 3.18-rc1. > > > > MTK I2C HW has some limitation. > > 1. If the i2c_msg number is more than one, STOP will be issued instead of > > RS(Repeat Start) between each message. > > Such as: "START + ADDR + DATA_n + STOP + START + ADDR + DATA_n + STOP ..." > > > > 2. Mediatek I2C controller support WRRD(write then read) mode, in WRRD > > mode the Repeat Start will be issued between 2 messages. > > In this driver if 2 messages is first write then read, the driver will > > combine 2 messages using Write-Read mode so the RS will be issued between > > the 2 messages. > > Ex: W/R/R, driver will combine first W/R and then R. > > The data series will be: > > "START + WriteADDR + DATA + RS + ReadADDR + DATA + STOP + START + ReadADDR + > > DATA + STOP". > > I think there are now 3 drivers in my queue which are not fully I2C > compatible but more supporting the very minimum to, say, read an eeprom. > I am not feeling well to allow them to use I2C_FUNC_I2C. So, I want to > think about ways how to communicate deficiencies like "only 255 byte" or > "only WRRD messages" to users of that I2C controller. This is most > likely not happening before 3.19. But assistance is very welcome. Let's us know what we could help :) > > 3. Due to HW limitation, in this version the max transfer data length is 255 > > in one message. If want to transfer more than 255 bytes, HW needs the SW > > driver to split the data. Take 600 bytes for example, the data need to be > > divided into 3 parts 255 + 255 + 90. The data series will be: > > "START + ADDR + DATA_255 + RS + ADDR + DATA_255 + RS + ADDR + DATA_90 + > > STOP" > > instead of "START + ADDR + DATA_900 + STOP". > > We haven't implement this yet, we will do this in the separate patch. > > I don't like this idea. If somebody wants to send 1 message with 600 > bytes and we can't do this, we should simply say so. Sending 3 messages > is not the same. Agreed. I think this should only happen when we know the device can support that. However, from our experience, many i2c devices do support it. Do you think it is OK to add a flag in i2c_msg(eg, I2C_M_ALLOW_SPLIT) and only do message split when this flag is on? > > MT8135 and MT6589 can control I2C pins on PMIC(MT6397) by setting the i2c > > registers in MT8135 side. In this case, driver should set OFFSET_PATH_DIR > > bit first, the operation on other registers are still the same. > > For now MT6589/MT8135 support this, MT6577/MT6595/MT8127 do not support. > > For example, If want to use I2C4/5/6 pins on MT8135 just need to enable > > the pinmux, else if want to use I2C pins on PMIC(MT6397) need to add > > "mediatek,have-pmic" property in the .dts file of each platform. > > What about Sascha's idea of using a pinctrl driver? We are working on mt6397 pmic pinctrl driver. It depends on mt8135 pinctrl driver [1] and pmic pwrap driver [2]. There are some discussion about pinctrl bindings, we'll send pmic pinctrl driver when that is settled. Just to make it clear, the pinctrl driver only handle pin mux, we still need to set mediatek,have-pmic to send i2c data through pmic. Joe.C [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/301417.html [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 3/4] ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
On Tue, 2014-11-25 at 16:04 +0800, Yingjoe Chen wrote: > Add sysirq settings for mt6589/mt8135/mt8127 > This also correct timer interrupt flag. The old setting works > because boot loader already set polarity for timer interrupt. > Without intpol support, the setting was not changed so gic > can get the irq correctly. Hi Matthias, I think this patch should go through you. Would you take a look at this patch? Also, mt8135/mt8127 uart support[1] depends on this, should we send it again? Thanks. Joe.C [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296147.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4] clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
Hi,
On Wed, 2014-11-26 at 08:14 -0800, Doug Anderson wrote:
> Yingjoe,
>
> On Wed, Nov 26, 2014 at 6:41 AM, Yingjoe Chen
> wrote:
> > Sorry for the (very) late reply.
> > I just realize today MT8135 need this and the other patch [1] to boot
> > SMP correctly. I've applied both patches and they works fine. Thanks :)
>
> Excellent. It's helpful to include a Tested-by: tag in your email.
> You'd have a line with just "Tested-by: Yingjoe Chen
> "
sure, here's my tested-by for the 2 patches
Tested-by: Yingjoe Chen
I'll remember to add it next time :)
> > However, I'm not sure if we really need to add new property.
> > arm_arch_timer driver will only use virtual timer when virtual PPI
> > interrupt is provided, so the following patch to timer dtsi will also
> > works. I think if the firmware doesn't support virtual timer, it make
> > sense to not supply virtual interrupt.
> >
> > timer {
> > compatible = "arm,armv7-timer";
> > interrupts = ,
> > -,
> > -,
> > -;
> > +;
> > clock-frequency = <1300>;
> > };
>
> Once you have Sonny's patch then I believe that the above would work.
> However we rejected something like this because device tree is
> supposed to describe the hardware. The hardware really does provide
> the virtual timer interrupts and they really are at PPI 11 and PPI 10.
> It's just that firmware doesn't handle things properly so they can't
> be used.
>
> NOTE: If we add the "arm,cpu-registers-not-fw-configured" to the
> device tree and firmware actually works out how to configure things
> (like if somehow has firmware that has a hypervisor) then it can
> easily remove this device tree property before calling through to the
> kernel. It would be much harder for the firmware to add back in the
> "PPI 11" and "PPI 10" entries to the timer.
>
> -Doug
I see your point, that's good for me then.
Thanks.
Joe.C
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Re: [PATCH v4] clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
On Wed, 2014-10-08 at 15:33 +0800, Sonny Rao wrote:
> From: Doug Anderson
>
> Some 32-bit (ARMv7) systems are architected like this:
>
> * The firmware doesn't know and doesn't care about hypervisor mode and
> we don't want to add the complexity of hypervisor there.
>
> * The firmware isn't involved in SMP bringup or resume.
>
> * The ARCH timer come up with an uninitialized offset (CNTVOFF)
> between the virtual and physical counters. Each core gets a
> different random offset.
>
> * The device boots in "Secure SVC" mode.
>
> * Nothing has touched the reset value of CNTHCTL.PL1PCEN or
> CNTHCTL.PL1PCTEN (both default to 1 at reset)
>
> On systems like the above, it doesn't make sense to use the virtual
> counter. There's nobody managing the offset and each time a core goes
> down and comes back up it will get reinitialized to some other random
> value.
>
> This adds an optional property which can inform the kernel of this
> situation, and firmware is free to remove the property if it is going
> to initialize the CNTVOFF registers when each CPU comes out of reset.
>
> Currently, the best course of action in this case is to use the
> physical timer, which is why it is important that CNTHCTL hasn't been
> changed from its reset value and it's a reasonable assumption given
> that the firmware has never entered HYP mode.
>
> Note that it's been said that on ARMv8 systems the firmware and
> kernel really can't be architected as described above. That means
> using the physical timer like this really only makes sense for ARMv7
> systems.
>
> Signed-off-by: Doug Anderson
> Signed-off-by: Sonny Rao
> Reviewed-by: Mark Rutland
> ---
> Changes in v2:
> - Add "#ifdef CONFIG_ARM" as per Will Deacon
>
> Changes in v3:
> - change property name to arm,cntvoff-not-fw-configured and specify
> that the value of CNTHCTL.PL1PC(T)EN must still be the reset value
> of 1 as per Mark Rutland
>
> Changes in v4:
> - change property name to arm,cpu-registers-not-fw-configured and
> specify that all cpu registers must have architected reset values
> per Mark Rutland
> - change from "#ifdef CONFIG_ARM" to "if (IS_ENABLED(CONFIG_ARM))" per
> Arnd Bergmann
> ---
> Documentation/devicetree/bindings/arm/arch_timer.txt | 8
> drivers/clocksource/arm_arch_timer.c | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt
> b/Documentation/devicetree/bindings/arm/arch_timer.txt
> index 37b2caf..256b4d8 100644
> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
> @@ -22,6 +22,14 @@ to deliver its interrupts via SPIs.
> - always-on : a boolean property. If present, the timer is powered through an
>always-on power domain, therefore it never loses context.
>
> +** Optional properties:
> +
> +- arm,cpu-registers-not-fw-configured : Firmware does not initialize
> + any of the generic timer CPU registers, which contain their
> + architecturally-defined reset values. Only supported for 32-bit
> + systems which follow the ARMv7 architected reset values.
> +
> +
Hi,
Sorry for the (very) late reply.
I just realize today MT8135 need this and the other patch [1] to boot
SMP correctly. I've applied both patches and they works fine. Thanks :)
However, I'm not sure if we really need to add new property.
arm_arch_timer driver will only use virtual timer when virtual PPI
interrupt is provided, so the following patch to timer dtsi will also
works. I think if the firmware doesn't support virtual timer, it make
sense to not supply virtual interrupt.
timer {
compatible = "arm,armv7-timer";
interrupts = ,
-,
-,
-;
+;
clock-frequency = <1300>;
};
Joe.C
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/305436.html
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[PATCH v8 4/4] dt-bindings: add bindings for mediatek sysirq
Add binding documentation for Mediatek SoC SYSIRQ.
Signed-off-by: Yingjoe Chen
---
.../bindings/arm/mediatek/mediatek,sysirq.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
new file mode 100644
index 000..d680b07
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
@@ -0,0 +1,28 @@
+Mediatek 65xx/81xx sysirq
+
+Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
+interrupt.
+
+Required properties:
+- compatible: should be one of:
+ "mediatek,mt8135-sysirq"
+ "mediatek,mt8127-sysirq"
+ "mediatek,mt6589-sysirq"
+ "mediatek,mt6582-sysirq"
+ "mediatek,mt6577-sysirq"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Use the same format as specified by GIC in
+ Documentation/devicetree/bindings/arm/gic.txt
+- interrupt-parent: phandle of irq parent for sysirq. The parent must
+ use the same interrupt-cells format as GIC.
+- reg: Physical base address of the intpol registers and length of memory
+ mapped region.
+
+Example:
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200100 0 0x1c>;
+ };
--
1.8.1.1.dirty
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[PATCH v8 1/4] irqchip: gic: Support hierarchy irq domain.
Add support to use gic as a parent for stacked irq domain.
Signed-off-by: Yingjoe Chen
---
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-gic.c | 77 ---
2 files changed, 54 insertions(+), 24 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b21f12f..7f34138 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -5,6 +5,7 @@ config IRQCHIP
config ARM_GIC
bool
select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
select MULTI_IRQ_HANDLER
config GIC_NON_BANKED
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 38493ff..ab6069b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -788,17 +788,16 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
{
if (hw < 32) {
irq_set_percpu_devid(irq);
- irq_set_chip_and_handler(irq, &gic_chip,
-handle_percpu_devid_irq);
+ irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
+ handle_percpu_devid_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
} else {
- irq_set_chip_and_handler(irq, &gic_chip,
-handle_fasteoi_irq);
+ irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
+ handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
gic_routable_irq_domain_ops->map(d, irq, hw);
}
- irq_set_chip_data(irq, d->host_data);
return 0;
}
@@ -858,6 +857,31 @@ static struct notifier_block gic_cpu_notifier = {
};
#endif
+static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct of_phandle_args *irq_data = arg;
+
+ ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
+ irq_data->args_count, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++)
+ gic_irq_domain_map(domain, virq + i, hwirq + i);
+
+ return 0;
+}
+
+static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
+ .xlate = gic_irq_domain_xlate,
+ .alloc = gic_irq_domain_alloc,
+ .free = irq_domain_free_irqs_top,
+};
+
static const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
.unmap = gic_irq_domain_unmap,
@@ -948,18 +972,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic_cpu_map[i] = 0xff;
/*
-* For primary GICs, skip over SGIs.
-* For secondary GICs, skip over PPIs, too.
-*/
- if (gic_nr == 0 && (irq_start & 31) > 0) {
- hwirq_base = 16;
- if (irq_start != -1)
- irq_start = (irq_start & ~31) + 16;
- } else {
- hwirq_base = 32;
- }
-
- /*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
@@ -969,10 +981,31 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic_irqs = 1020;
gic->gic_irqs = gic_irqs;
- gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+ if (node) { /* DT case */
+ const struct irq_domain_ops *ops =
&gic_irq_domain_hierarchy_ops;
+
+ if (!of_property_read_u32(node, "arm,routable-irqs",
+ &nr_routable_irqs)) {
+ ops = &gic_irq_domain_ops;
+ gic_irqs = nr_routable_irqs;
+ }
+
+ gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ } else {/* Non-DT case */
+ /*
+* For primary GICs, skip over SGIs.
+* For secondary GICs, skip over PPIs, too.
+*/
+ if (gic_nr == 0 && (irq_start & 31) > 0) {
+ hwirq_base = 16;
+ if (irq_start != -1)
+ irq_start = (irq_start & ~31) + 16;
+ } else {
+ hwirq_base = 32;
+ }
+
+ gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
- if (of_property_read_u32(node, "arm,routable-irqs",
-&nr_routable_irqs)) {
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
[PATCH v8 3/4] ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
Add sysirq settings for mt6589/mt8135/mt8127
This also correct timer interrupt flag. The old setting works
because boot loader already set polarity for timer interrupt.
Without intpol support, the setting was not changed so gic
can get the irq correctly.
Signed-off-by: Yingjoe Chen
---
arch/arm/boot/dts/mt6589.dtsi | 14 --
arch/arm/boot/dts/mt8127.dtsi | 14 --
arch/arm/boot/dts/mt8135.dtsi | 14 --
3 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index e3c7600..c91b2a9 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -19,7 +19,7 @@
/ {
compatible = "mediatek,mt6589";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
@@ -76,15 +76,25 @@
timer: timer@10008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
- interrupts = ;
+ interrupts = ;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt6589-sysirq",
+"mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200100 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
<0x10212000 0x1000>,
<0x10214000 0x2000>,
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index c3ee060..49f5976 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -18,7 +18,7 @@
/ {
compatible = "mediatek,mt8127";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
@@ -82,15 +82,25 @@
compatible = "mediatek,mt8127-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
- interrupts = ;
+ interrupts = ;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt8127-sysirq",
+"mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200100 0 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x1000>,
<0 0x10214000 0 0x2000>,
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 5faae6e..60338d9 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -18,7 +18,7 @@
/ {
compatible = "mediatek,mt8135";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpu-map {
cluster0 {
@@ -105,15 +105,25 @@
compatible = "mediatek,mt8135-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
- interrupts = ;
+ interrupts = ;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@102
[PATCH v8 2/4] ARM: mediatek: Add sysirq interrupt polarity support
Mediatek SoCs have interrupt polarity support in sysirq which
allows to invert polarity for given interrupt. Add this support
using hierarchy irq domain.
Signed-off-by: Yingjoe Chen
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mtk-sysirq.c | 163 +++
2 files changed, 164 insertions(+)
create mode 100644 drivers/irqchip/irq-mtk-sysirq.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 173bb5f..4e0f254 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_IRQ_CROSSBAR)+= irq-crossbar.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
irq-bcm7120-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
+obj-$(CONFIG_ARCH_MEDIATEK)+= irq-mtk-sysirq.o
diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
new file mode 100644
index 000..7e342df
--- /dev/null
+++ b/drivers/irqchip/irq-mtk-sysirq.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "irqchip.h"
+
+#define MT6577_SYS_INTPOL_NUM (224)
+
+struct mtk_sysirq_chip_data {
+ spinlock_t lock;
+ void __iomem *intpol_base;
+};
+
+static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct mtk_sysirq_chip_data *chip_data = data->chip_data;
+ u32 offset, reg_index, value;
+ unsigned long flags;
+ int ret;
+
+ offset = hwirq & 0x1f;
+ reg_index = hwirq >> 5;
+
+ spin_lock_irqsave(&chip_data->lock, flags);
+ value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
+ if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
+ if (type == IRQ_TYPE_LEVEL_LOW)
+ type = IRQ_TYPE_LEVEL_HIGH;
+ else
+ type = IRQ_TYPE_EDGE_RISING;
+ value |= (1 << offset);
+ } else {
+ value &= ~(1 << offset);
+ }
+ writel(value, chip_data->intpol_base + reg_index * 4);
+
+ data = data->parent_data;
+ ret = data->chip->irq_set_type(data, type);
+ spin_unlock_irqrestore(&chip_data->lock, flags);
+ return ret;
+}
+
+static struct irq_chip mtk_sysirq_chip = {
+ .name = "MT_SYSIRQ",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi= irq_chip_eoi_parent,
+ .irq_set_type = mtk_sysirq_set_type,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int mtk_sysirq_domain_xlate(struct irq_domain *d,
+ struct device_node *controller,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ if (intsize != 3)
+ return -EINVAL;
+
+ /* sysirq doesn't support PPI */
+ if (intspec[0])
+ return -EINVAL;
+
+ *out_hwirq = intspec[1];
+ *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+}
+
+static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int
virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct of_phandle_args *irq_data = arg;
+ struct of_phandle_args gic_data = *irq_data;
+
+ if (irq_data->args_count != 3)
+ return -EINVAL;
+
+ /* sysirq doesn't support PPI */
+ if (irq_data->args[0])
+ return -EINVAL;
+
+ hwirq = irq_data->args[1];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &mtk_sysirq_chip,
+ domain->host_data);
+
+ gic_data.np = domain->parent->of_node;
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
+}
+
+static struct irq_domain
[PATCH v8 0/4] ARM: mediatek: Add support for interrupt polarity
This series is 8th version of interrupt polarity support for MediaTek SoCs. I rebased previous version to latest tip/irq/irqdomain, and fix issues raised by Marc & Mark. The interrupt & irq free work fine on mt8135 board. Simplified block diagram for interrupt on my system: +---+ +---+ ---| SYSIRQ|--|ARM GIC| ---| |--| | ---| |--| | ---| |--| | ---| |--| | +---+ +---+ In device tree, interrupt-parent for other devices is sysirq, child of gic. This describe HW better and allow device to specify polarity as it is sent by the device. When using hierarchy irq domain, gic will use irq_domain_add_linear to create irqdomain and all interrupt numbers must come from device tree. My /proc/interrupts looks like this now: # cat /proc/interrupts CPU0 16: 149578 MT_SYSIRQ 113 mtk_timer 20: 1082 MT_SYSIRQ 54 serial Changes in v8: - Rebased to new tip/irq/irqdomain - Update mediatek,sysirq.txt bindinds to document interrupt-cells format and interrupt-parents - Change interrupt-cells format check in mtk_sysirq. - Minor coding style fix Changes in v7: - Discussed in [1] - Rebased to tip/irq/irqdomain - In mtk_sysirq_domain_alloc, use copy of irq_data to workaound of_node check in gic_irq_domain_xlate. Changes in v6: - Discussed in [2] - Rebased to tip/irq/irqdomain Changes in v5: - Discussed in [3] - Fix bug on mt6589 reported by Matthias - Fix bug for irq_find_mapping in irq_create_of_mapping - Merge Marc's change to proper handle non-DT case in gic_init_bases Changes in v4: - Discussed in [4] - Remove arm,hierarchy-irq-domain. When GIC is probed by DT, it will support hierarchy irqdomain. Changes in v3: - Discussed in [5] - First implementation using hierarchy irqdomain [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/304119.html [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302221.html [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/298161.html [4] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296911.html [5] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/293766.html Yingjoe Chen (4): irqchip: gic: Support hierarchy irq domain. ARM: mediatek: Add sysirq interrupt polarity support ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi dt-bindings: add bindings for mediatek sysirq .../bindings/arm/mediatek/mediatek,sysirq.txt | 28 arch/arm/boot/dts/mt6589.dtsi | 14 +- arch/arm/boot/dts/mt8127.dtsi | 14 +- arch/arm/boot/dts/mt8135.dtsi | 14 +- drivers/irqchip/Kconfig| 1 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic.c | 77 +++--- drivers/irqchip/irq-mtk-sysirq.c | 163 + 8 files changed, 282 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt create mode 100644 drivers/irqchip/irq-mtk-sysirq.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 4/4] dt-bindings: add bindings for mediatek sysirq
Hi Mark, On Wed, 2014-11-19 at 18:07 +, Mark Rutland wrote: > On Wed, Nov 19, 2014 at 02:14:11PM +0000, Yingjoe Chen wrote: > > Add binding documentation for Mediatek SoC SYSIRQ. > > > > Signed-off-by: Yingjoe Chen > > --- > > .../bindings/arm/mediatek/mediatek,sysirq.txt | 26 > > ++ > > 1 file changed, 26 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt > > new file mode 100644 > > index 000..8669536 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt > > @@ -0,0 +1,26 @@ > > +Mediatek 65xx/81xx sysirq > > + > > +Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI > > +interrupt. > > + > > +Required properties: > > +- compatible: should be one of: > > + "mediatek,mt8135-sysirq" > > + "mediatek,mt8127-sysirq" > > + "mediatek,mt6589-sysirq" > > + "mediatek,mt6582-sysirq" > > + "mediatek,mt6577-sysirq" > > +- interrupt-controller : Identifies the node as an interrupt controller > > +- #interrupt-cells : Must use the same cells/format as parent controller. > > +- interrupt-parent: phandle of irq domain parent for sysirq. > > I'm concerned that this sounds very general while the binding assumes > the GICv2 interrupt-specifier format. Either the driver needs to become > more general, or this needs to be tightened up. > > It's also odd to say "irq domain parent", as that's purely a Linux > construct and has nothing to do with the HW. The implementation expect the parent to use the same interrupt-cells format as GIC. Based on the block diagram in the cover-letter, we could say GIC is the irq parent of sysirq. So I'm planning to change to this, hope this is OK. - #interrupt-cells : Use the same format as specified by GIC in Documentation/devicetree/bindings/arm/gic.txt - interrupt-parent: phandle of irq parent for sysirq. The parent must use the same interrupt-cells format as GIC. Joe.C -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 1/4] irqchip: gic: Support hierarchy irq domain.
Hi,
On Thu, 2014-11-20 at 10:07 +, Marc Zyngier wrote:
> On Thu, Nov 20 2014 at 4:26:10 am GMT, Jiang Liu
> wrote:
>
> Hi Jiang,
>
> > On 2014/11/20 1:18, Marc Zyngier wrote:
> >> Hi Yingjoe,
> >>
> >> On Wed, Nov 19 2014 at 2:14:08 pm GMT, Yingjoe Chen
> >> wrote:
> >>> +
> >>> +static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
> >>> + .xlate = gic_irq_domain_xlate,
> >>> + .alloc = gic_irq_domain_alloc,
> >>> + .free = irq_domain_free_irqs_top,
> >>
> >> I'm convinced that irq_domain_free_irqs_top is the wrong function to
> >> call here, because you're calling it from the bottom, not the top-level
> >> (it has no parent).
> >>
> >> I cannot verify this with your code as I don't a working platform with
> >> GICv2m, but if I enable something similar on GICv3, it dies a very
> >> painful way:
> >>
> >> Unable to handle kernel NULL pointer dereference at virtual address
> >> 0018
> >> pgd = ffc03d059000
> >> [0018] *pgd=81356003, *pud=81356003,
> >> *pmd=
> >> Internal error: Oops: 9606 [#1] SMP
> >> Modules linked in:
> >> CPU: 4 PID: 1052 Comm: sh Not tainted 3.18.0-rc4+ #3311
> >> task: ffc03e32 ti: ffc00139 task.ti: ffc00139
> >> PC is at irq_domain_free_irqs_recursive+0x1c/0x80
> >> LR is at irq_domain_free_irqs_common+0x88/0x9c
> >> pc : [] lr : [] pstate: 6145
> >> [...]
> >> [] irq_domain_free_irqs_recursive+0x1c/0x80
> >> [] irq_domain_free_irqs_common+0x84/0x9c
> >> [] irq_domain_free_irqs_top+0x64/0x7c <--
> >> gic_domain.free()
> >> [] irq_domain_free_irqs_recursive+0x24/0x80
> >> [] irq_domain_free_irqs_parent+0x14/0x20
> >> [] its_irq_domain_free+0xc8/0x250
> >> [] irq_domain_free_irqs_recursive+0x24/0x80
> >> [] irq_domain_free_irqs_common+0x84/0x9c
> >> [] irq_domain_free_irqs_top+0x64/0x7c
> >> [] msi_domain_free+0x70/0x88
> >> [] irq_domain_free_irqs_recursive+0x24/0x80
> >> [] irq_domain_free_irqs+0x108/0x17c
> >> [] msi_domain_free_irqs+0x28/0x4c
> >> [] free_msi_irqs+0xb4/0x1c0
> >> [] pci_disable_msix+0x3c/0x4c
> >> [...]
> >>
> >> and I cannot see how this could work on the standard GIC either.
> >>
> >> Thomas, Jiang: could you please confirm or infirm my suspicions? My
> >> understanding is that irq_domain_free_irqs_top can only be called from
> >> the top-level domain.
> > Hi Marc,
> > It indicates that irq_domain_free_irqs_top() is not a good name.
> > We have:
> > 1) irq_domain_set_hwirq_and_chip() to set irq_chip and chip_data
> > 2) irq_domain_set_info() to set irq_chip, chip_data, flow_handler and
> >handler_data;
> > 3) irq_domain_reset_irq_data() resets irq_chip and chip_data.
> > 4) irq_domain_free_irqs_common() resets irq_chip, chip_data and calls
> >parent domain's domain_ops.free() callback.
> > 5) irq_domain_free_irqs_top() resets irq_chip, chip_data, flow handler,
> >handler_data and call parent domain's domain_ops.free() callback.
>
> Yes, and this "call parent domain's free callback" is where the problem
> lies. Here, it is called from the innermost domain, with no parent.
>
> > So there two possible improvements here:
> > 1) Rename irq_domain_free_irqs_top() with better name, any suggestions?
> >It's named as is because it's always called by the outer-most
> >irqdomains on x86.
> > 2) Change irq_domain_free_irqs_common() and irq_domain_free_irqs_top()
> >to call parent domain's domain_ops.free() callback only if parent
> >exists. By this way, they could be used for inner-most irqdomains.
> > If OK, I will respin a version 4 patch set based on tip/irq/irqdomain.
> > Thoughts?
>
> Checking the parent is probably a safe solution (this is not a hot path
> anyway). I don't care much about the name though, and I the only thing I
> can think of is irq_domain_free_irqs_reset_flow, which looks so bad it's
> not even funny. I'll let the matter rest in your capable hands! ;-)
I've applied Jiang's "irqdomain: Enhance irq_domain_free_irqs_common()
to support parentless irqdomain" patch and it did fix the crash.
Thanks Jiang, Marc
Joe.C
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