Re: [PATCH v2 4/9] ARM: dts: add dts files for hi3519-demb board

[zhangfei]

On 12/07/2015 02:37 PM, xuejiancheng wrote:


As this seems to be a standard part, we can also think about making a
high-level driver for in in drivers/soc rather than relying on the syscon
driver which we tend to use more for one-off devices with random register
layouts.


Sorry. I didn't understand your meaning well and maybe I gave you a wrong 
description.
Please allow me to clarify it again.
The "sysctrl" nodes here is just used for the "reboot" function. It is 
corresponding to
the driver "drivers/power/reset/hisi-reboot.c". The compatible string in the 
driver is
"hisilicon,sysctrl".



Pls try use drivers/power/reset/syscon-reboot.c

Thanks
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[PATCH] arm64: dts: add hi6220 usb node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao <zhangfei@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 33 +++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 0f11e2a..abb2ea0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -209,6 +209,39 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+   fixed_5v_hub: regulator@0 {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed_5v_hub";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-boot-on;
+   gpio = < 7 0>;
+   regulator-always-on;
+   };
+
+   usb_phy: usbphy {
+   compatible = "hisilicon,hi6220-usb-phy";
+   #phy-cells = <0>;
+   phy-supply = <_5v_hub>;
+   hisilicon,peripheral-syscon = <_ctrl>;
+   };
+
+   usb: usb@f72c {
+   compatible = "hisilicon,hi6220-usb";
+   reg = <0x0 0xf72c 0x0 0x4>;
+   phys = <_phy>;
+   phy-names = "usb2-phy";
+   clocks = <_ctrl HI6220_USBOTG_HCLK>;
+   clock-names = "otg";
+   dr_mode = "otg";
+   g-use-dma;
+   g-rx-fifo-size = <512>;
+   g-np-tx-fifo-size = <128>;
+   g-tx-fifo-size = <128 128 128 128 128 128>;
+   interrupts = <0 77 0x4>;
+   };
+
gpio0: gpio@f8011000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8011000 0x0 0x1000>;
-- 
1.9.1

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Re: [PATCH] usb: dwc2: add support of hi6220

[zhangfei]

On 11/20/2015 11:34 PM, Felipe Balbi wrote:


John Youn  writes:



That's weird. I just sync'd to your testing/next and it seems to
apply fine.

Same with the series from Gregory Herrero.

Any chance it's something to do with your local repo?


odd. Seems like it works if I apply manually with git am, but fails if I
pipe message from emacs to git am. Oh well, let me try again.



Thanks Felipe & John, have verified hi6220 usb on testing/next.

Thanks
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[PATCH v2] phy: add phy-hi6220-usb

[Zhangfei Gao]

Support hi6220 use phy for HiKey board

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Zhangfei Gao <zhangfei@linaro.org>
---
Rebase to  Linux 4.4-rc1
 
 .../devicetree/bindings/phy/phy-hi6220-usb.txt |  16 ++
 drivers/phy/Kconfig|   9 ++
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-hi6220-usb.c   | 168 +
 4 files changed, 194 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
 create mode 100644 drivers/phy/phy-hi6220-usb.c

diff --git a/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
new file mode 100644
index ..f17a56e2152f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
@@ -0,0 +1,16 @@
+Hisilicon hi6220 usb PHY
+---
+
+Required properties:
+- compatible: should be "hisilicon,hi6220-usb-phy"
+- #phy-cells: must be 0
+- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+   usb_phy: usbphy {
+   compatible = "hisilicon,hi6220-usb-phy";
+   #phy-cells = <0>;
+   phy-supply = <_5v_hub>;
+   hisilicon,peripheral-syscon = <_ctrl>;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..e1090507f2cd 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -215,6 +215,15 @@ config PHY_MT65XX_USB3
  for mt65xx SoCs. it supports two usb2.0 ports and
  one usb3.0 port.
 
+config PHY_HI6220_USB
+   tristate "hi6220 USB PHY support"
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver"
depends on ARCH_SUNXI && HAS_IOMEM && OF
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..faccda1f237f 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3)+= 
phy-ti-pipe3.o
 obj-$(CONFIG_TWL4030_USB)  += phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)  += phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
+obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
 obj-$(CONFIG_PHY_MT65XX_USB3)  += phy-mt65xx-usb3.o
 obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
diff --git a/drivers/phy/phy-hi6220-usb.c b/drivers/phy/phy-hi6220-usb.c
new file mode 100644
index ..b2141cbd4cf6
--- /dev/null
+++ b/drivers/phy/phy-hi6220-usb.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct regmap *reg;
+   struct device *dev;
+};
+
+static void hi6220_phy_init(struct hi6220_priv *priv)
+{
+   struct regmap *reg = priv->reg;
+   u32 val, mask;
+
+   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
+ RST0_USBOTG | RST0_USBOTG_32K;
+   mask = val;
+   regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val);
+   regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val

[PATCH] usb: dwc2: add support of hi6220

[Zhangfei Gao]

Support hisilicon,hi6220-usb for HiKey board

Signed-off-by: Zhangfei Gao <zhangfei@linaro.org>
---
 Documentation/devicetree/bindings/usb/dwc2.txt |  1 +
 drivers/usb/dwc2/platform.c| 32 ++
 2 files changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
   - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 5859b0f..a5cb1bf 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -54,6 +54,37 @@
 
 static const char dwc2_driver_name[] = "dwc2";
 
+static const struct dwc2_core_params params_hi6220 = {
+   .otg_cap= 2,/* No HNP/SRP capable */
+   .otg_ver= 0,/* 1.3 */
+   .dma_enable = 1,
+   .dma_desc_enable= 0,
+   .speed  = 0,/* High Speed */
+   .enable_dynamic_fifo= 1,
+   .en_multiple_tx_fifo= 1,
+   .host_rx_fifo_size  = 512,
+   .host_nperio_tx_fifo_size   = 512,
+   .host_perio_tx_fifo_size= 512,
+   .max_transfer_size  = 65535,
+   .max_packet_count   = 511,
+   .host_channels  = 16,
+   .phy_type   = 1,/* UTMI */
+   .phy_utmi_width = 8,
+   .phy_ulpi_ddr   = 0,/* Single */
+   .phy_ulpi_ext_vbus  = 0,
+   .i2c_enable = 0,
+   .ulpi_fs_ls = 0,
+   .host_support_fs_ls_low_power   = 0,
+   .host_ls_low_power_phy_clk  = 0,/* 48 MHz */
+   .ts_dline   = 0,
+   .reload_ctl = 0,
+   .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ GAHBCFG_HBSTLEN_SHIFT,
+   .uframe_sched   = 0,
+   .external_id_pin_ctl= -1,
+   .hibernation= -1,
+};
+
 static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -282,6 +313,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = _bcm2835 },
+   { .compatible = "hisilicon,hi6220-usb", .data = _hi6220 },
{ .compatible = "rockchip,rk3066-usb", .data = _rk3066 },
{ .compatible = "snps,dwc2", .data = NULL },
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
-- 
1.9.1

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[PATCH] phy: add phy-hi6220-usb

[Zhangfei Gao]

Support hi6220 use phy for HiKey board

Signed-off-by: Zhangfei Gao <zhangfei@linaro.org>
---
 .../devicetree/bindings/phy/phy-hi6220-usb.txt |  16 ++
 drivers/phy/Kconfig|   9 ++
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-hi6220-usb.c   | 168 +
 4 files changed, 194 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
 create mode 100644 drivers/phy/phy-hi6220-usb.c

diff --git a/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
new file mode 100644
index 000..f17a56e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
@@ -0,0 +1,16 @@
+Hisilicon hi6220 usb PHY
+---
+
+Required properties:
+- compatible: should be "hisilicon,hi6220-usb-phy"
+- #phy-cells: must be 0
+- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+   usb_phy: usbphy {
+   compatible = "hisilicon,hi6220-usb-phy";
+   #phy-cells = <0>;
+   phy-supply = <_5v_hub>;
+   hisilicon,peripheral-syscon = <_ctrl>;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..c91a612 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA
help
  Support for SATA PHY on Hisilicon hix5hd2 Soc.
 
+config PHY_HI6220_USB
+   tristate "hi6220 USB PHY support"
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver"
depends on ARCH_SUNXI && HAS_IOMEM && OF
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..0c5ccc9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3)+= 
phy-ti-pipe3.o
 obj-$(CONFIG_TWL4030_USB)  += phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)  += phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
+obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
 obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
diff --git a/drivers/phy/phy-hi6220-usb.c b/drivers/phy/phy-hi6220-usb.c
new file mode 100644
index 000..b2141cb
--- /dev/null
+++ b/drivers/phy/phy-hi6220-usb.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct regmap *reg;
+   struct device *dev;
+};
+
+static void hi6220_phy_init(struct hi6220_priv *priv)
+{
+   struct regmap *reg = priv->reg;
+   u32 val, mask;
+
+   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
+ RST0_USBOTG | RST0_USBOTG_32K;
+   mask = val;
+   regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val);
+   regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val);
+}
+
+static int hi6220_phy_setup(struct hi6220_priv *priv, bool on)
+{
+   struct regmap *reg = priv->reg;
+   u32 val,

Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS

[zhangfei]

On 10/27/2015 10:39 PM, Mark Rutland wrote:

On Tue, Oct 27, 2015 at 01:09:15PM +, John Garry wrote:

On 26/10/2015 14:45, Mark Rutland wrote:

On Mon, Oct 26, 2015 at 10:14:33PM +0800, John Garry wrote:

Add devicetree bindings for HiSilicon SAS driver.

Signed-off-by: John Garry 
---
  .../devicetree/bindings/scsi/hisilicon-sas.txt | 70 ++
  1 file changed, 70 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt

diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt 
b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
new file mode 100644
index 000..d1e7b2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -0,0 +1,70 @@
+* HiSilicon SAS controller
+
+The HiSilicon SAS controller supports SAS/SATA.
+
+Main node required properties:
+  - compatible : value should be as follows:
+   (a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
+  - reg : Address and length of the SAS register
+  - hisilicon,sas-syscon: phandle of syscon used for sas control
+  - ctrl-reg : offset to the following SAS control registers (in order):
+   - reset assert
+   - clock disable
+   - reset status
+   - reset de-assert
+   - clock enable


This needs a better name, and it should probably be split up into
several properties.

However, it sounds like the syscon is actually a clock+reset
controller, and should be modelled as such. It's not actually a part of
the SAS controller as such.


The syscon block is a general subsystem control block, and it is not
specifically only for controlling reset and enabling clocks (other
functions include serdes control, for example). It is also shared
with other peripherals.

So we can remove the ctrl-reg property (since it is not part of the
SAS controller), and add the relevant syscon register offsets to the
"hisilicon,sas-syscon" property, like this:
hisilicon,sas-syscon = <_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;

Ok?


It would be better to have each offset in a separate property.


These register are not used for different purpose.
Instead, they are all used for one purpose, reset the sas controller;
Though a bit complicated, the silicon has special requirement here.

So still prefer using the original method,
ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
Since we can simply use of_property_read_u32_array.

Thanks

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Re: [PATCH 02/25] devicetree: bindings: scsi: HiSi SAS

[zhangfei]

On 10/19/2015 06:48 PM, John Garry wrote:

On 16/10/2015 14:47, Rob Herring wrote:



+  - reg : Address and length of the register sets for the device
+   - SAS controller registers
+   - SAS controller control registers
+
+  - reset-reg : offset to reset, status, and clock registers in
control registers


Within the above register range? If so and if this varies, then that
implies there is more than 1 version of IP. In that case you should
have a more specific compatible string.


The registers in the second region are for syscon register offsets. See
last note, below.


How long is this property I count 3 cells here, but the example has 5.
Define what each cell corresponds to specifically.


We will add all the cells to the decription, which are:
Reset assert, clock disable, reset status, reset de-assert, and clock
enable.

+


We have switch to using syscon,
The dts has been changed to

sas_ctrl0: sas_ctrl@c000 {
compatible = "hisilicon,sas-ctrl", "syscon";
reg = <0x0 0xc000 0x0 0x1>;
};

sas0: sas@c100 {
compatible = "hisilicon,sas-controller-v1";
reg = <0x0 0xc100 0x0 0x1>;
hisilicon,sas-syscon = <_ctrl0>;
ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;

ctrl-reg contains several regs in sas-ctrl, which need to be accessed 
since some complicated requirement of the silicon.


Have considered using
hisilicon,sas-syscon = <_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;
But of_property_read_u32_array cat not get array from index 1.
Then we have to use of_property_read_u32_index one by one.

So instead we add additional ctrl-reg, and get the array one time via 
of_property_read_u32_array.


Thanks


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Re: [PATCH 03/25] scsi: hisi_sas: add initial bare driver

[zhangfei]

On 10/15/2015 05:23 PM, John Garry wrote:

On 15/10/2015 09:49, Xinwei Kong wrote:






+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.



+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");

V2

Can add. We do say in the header that it is v2.


No, should use MODULE_LICENSE("GPL");

include/linux/module.h

/*
 * The following license idents are currently accepted as indicating free
 * software modules
 *
 *  "GPL"   [GNU Public License v2 or later]
 *  "GPL v2"[GNU Public License v2]

Thanks
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Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[zhangfei]

On 10/14/2015 11:18 PM, Arnd Bergmann wrote:

On Wednesday 14 October 2015 16:05:21 John Garry wrote:


OK, we can look at adding the ability to read the SAS HBA address from a
FW image or EFI variables.



The easiest way is usually to have a DT property that gets updated
by the firmware.



Yes
In net subsystem, there is mac-address.

In dts, we set default mac-address, which will be modified by 
boot-loader, if all 0 random address will be used.

mac-address = [00 00 00 00 00 00];

In driver, mac-address can be get via of_get_mac_address.

Can we use the similar method here?

Thanks
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Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[zhangfei]

Hi, Arnd

On 10/12/2015 11:15 PM, Arnd Bergmann wrote:

On Monday 12 October 2015 23:20:17 John Garry wrote:

+   interrupt_count = of_property_count_u32_elems(np, "interrupts");
+   if (interrupt_count < 0)
+   goto err_out;
+
+   if (of_property_read_u32(np, "#interrupt-cells", _cells))
+   goto err_out;
+
+   hisi_hba->int_names = devm_kcalloc(>dev,
+  interrupt_count / interrupt_cells,
+  HISI_SAS_NAME_LEN,
+  GFP_KERNEL);



This computation looks wrong: the "interrupts" property refers to interrupts
that are referenced by this node and provided by an interrupt-controller,
while the "#interrupt-cells" property refers to interrupts provided by
this node. They don't need to have any relation.


We will use of_irq_count instead.

Thanks
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Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[zhangfei]

On 10/12/2015 11:21 PM, Arnd Bergmann wrote:

On Monday 12 October 2015 23:20:19 John Garry wrote:

+int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
+{
+   struct platform_device *pdev = hisi_hba->pdev;
+   struct device *dev = >dev;
+   struct resource *res;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   hisi_hba->regs = devm_ioremap(dev,
+ res->start,
+ resource_size(res));
+   if (!hisi_hba->regs)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+   hisi_hba->ctrl_regs = devm_ioremap(dev,
+  res->start,
+  resource_size(res));
+   if (!hisi_hba->ctrl_regs)
+   return -ENOMEM;
+
+   return 0;
+}

  static const struct of_device_id sas_of_match[] = {



Better use devm_ioremap_resource() here, which registers the resource so they
are checked for conflicts and listed in /proc/iomem.



Yes, hisi_hba->regs can use devm_ioremap_resource.

However ctrl_regs have to use devm_ioremap, since the address are 
sharing among different nodes, unfortunately, and devm_ioremap_resource 
will fail.


Thanks
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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Roger

On 02/24/2015 06:13 PM, Roger Quadros wrote:

On Sat, Feb 21, 2015 at 11:03:05PM +0800, zhangfei wrote:

+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+struct usb_otg *otg = priv-phy.otg;
+
+if (!otg-gadget)
+return;
+
+if (on)
+usb_gadget_connect(otg-gadget);
+else
+usb_gadget_disconnect(otg-gadget);


why is the PHY fiddling with pullups ?


We use this to enable/disable otg gadget mode.


I got that, but the pullups don't belong to the PHY, they belong to the
gadget.


The gpio_id  gpio_vbus are used to distinguish otg gadget mode or
host mode.
When micro usb or otg device attached to otg, gpio_vbus falling down.
And gpio_id = 1 is micro usb, gpio_id = 0 is otg device.


all of that I understood clearly :-)


So when micro usb attached, we enable gadget mode; while micro usb
detached, we disable gadget mode, and dwc2 will automatically set to
host mode.


that's all fine, I'm concerned about letting the PHY fiddle with
something it doesn't own. If I am to change pullups rules in udc-core,
this is likely to break down miserably and I don't want to have to go
through that.


Thanks for the clarifying.


no problem.


How about using usb_gadget_vbus_connect/disconnect, which are used in many
files under drivers/usb/phy.
There is no vbus_session in dwc2/gadget.c, I thought it would be same as
pullup.

However, usb_gadget_vbus_connect still need para gadget, where should we put
this file, drivers/usb/phy or drivers/phy


drivers/phy, if the framework misses anything you need, it's a great
opportunity to give back to the community by extending the framework.


Sorry, I am a little confused.
I need some concrete suggestion for the next step of this patch, which is 
required for the community board, hikey board.

Do you mean in the future we need use hsotg-phy instead of hsotg-uphy.
 struct phy *phy;
 struct usb_phy *uphy;
usb_phy has many members that struct phy does not have, including otg.
struct usb_otg  *otg;
Is that mean we need port such member from usb_phy to phy.


In my opinion otg structure should belong to the USB core part that takes care
of the OTG/DRD state machine. We still don't have a clear solution here and
I'm currently investigating this.
My current work is to get Dual role functionality working with DWC3 controller 
and TI
platforms.

Currently phy drivers take care of OTG operation themselves but there is an 
opportunity
to share code and centralize USB role switching.
The USB core should be the owner of the Host controller, Gadget controller and 
the OTG phy
and should take care of the that.


Good idea.
If you have any patch, I will be very happy to verify.

How about adding these things in drivers/phy/phy-core.c, it is also 
sharable, though not in usb core.


Just tried adding one member struct usb_otg otg to struct phy, since not 
find any good member can hold usb_otg.
In drivers/phy/phy-core.c, adding extcon_register_interest, 
phy_vbus_notifier, phy_set_peripheral, it works for me, dwc2 on hikey board.






Besides, are you ok with using usb_gadget_vbus_connect/disconnect.


I don't think PHY is the right place for this even though older drivers seem to 
be doing so.
But at the same time there is nowhere else to add this at the moment.
The right place should be the USB core that is aware of host/gadget, phy and 
the state of the bus.


Understand.


Scratching one's own itch kinda thing...


+static void hi6220_detect_work(struct work_struct *work)
+{
+struct hi6220_priv *priv =
+container_of(work, struct hi6220_priv, work.work);
+int gpio_id, gpio_vbus;
+enum usb_otg_state state;
+
+if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+return;
+
+gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);


looks like this should be using extcon

Not used extcon before.
However, we need gpio_vbus interrupt.
Checked phy-tahvo.c and phy-omap-otg.c, not find extcon related with
interrupt.
Will investigate tomorrow.


drivers/extcon/extcon-gpio.c

I think there is no need to use extcon, gpio is clear enough.
extcon-gpio.c even do not support dt.


well, add DT. The whole idea of free software is that we improve on
things we already have. EXTCON is *the* API to handle such things.




I wrote the extcon-gpio-usb.c driver for exactly your use case. It is
queued for v4.1
https://lkml.org/lkml/2015/2/2/187


That's great, thanks.


It takes care of debouncing for you. Although currently it supports only ID 
gpio,
it should be very easy to extend to VBUS sense GPIO.


I think I am still not understanding extcon-gpio, not sure why need use this 
API here.


several reasons. Let me list a few.
1) Code reuse. Every PHY driver doesn't need to implement GPIO/interrupt 
handling and debouncing.
It just registers what cable events it wants to hear and gets a notification.
2) The events (ID/VBUS

Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

On 02/23/2015 11:36 PM, Felipe Balbi wrote:

Hi,

On Sun, Feb 22, 2015 at 11:10:36AM +0800, zhangfei wrote:

+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);


why is the PHY fiddling with pullups ?


We use this to enable/disable otg gadget mode.


I got that, but the pullups don't belong to the PHY, they belong to the
gadget.


The gpio_id  gpio_vbus are used to distinguish otg gadget mode or
host mode.
When micro usb or otg device attached to otg, gpio_vbus falling down.
And gpio_id = 1 is micro usb, gpio_id = 0 is otg device.


all of that I understood clearly :-)


So when micro usb attached, we enable gadget mode; while micro usb
detached, we disable gadget mode, and dwc2 will automatically set to
host mode.


that's all fine, I'm concerned about letting the PHY fiddle with
something it doesn't own. If I am to change pullups rules in udc-core,
this is likely to break down miserably and I don't want to have to go
through that.


Thanks for the clarifying.


no problem.


How about using usb_gadget_vbus_connect/disconnect, which are used in many
files under drivers/usb/phy.
There is no vbus_session in dwc2/gadget.c, I thought it would be same as
pullup.

However, usb_gadget_vbus_connect still need para gadget, where should we put
this file, drivers/usb/phy or drivers/phy


drivers/phy, if the framework misses anything you need, it's a great
opportunity to give back to the community by extending the framework.


Sorry, I am a little confused.
I need some concrete suggestion for the next step of this patch, which is
required for the community board, hikey board.

Do you mean in the future we need use hsotg-phy instead of hsotg-uphy.
 struct phy *phy;
 struct usb_phy *uphy;


yes, we need to move everybody to use struct phy, instead of struct
usb_phy.


usb_phy has many members that struct phy does not have, including otg.
struct usb_otg  *otg;
Is that mean we need port such member from usb_phy to phy.


This means we have a little ground work to do before we can add your phy
driver to that framework, right ? As I said, if the framework is missing
anything, work with Kishon (generic phy maintainer) to add those missing
pieces generically.


OK, got it.



Besides, are you ok with using usb_gadget_vbus_connect/disconnect.



Scratching one's own itch kinda thing...


+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);


looks like this should be using extcon

Not used extcon before.
However, we need gpio_vbus interrupt.
Checked phy-tahvo.c and phy-omap-otg.c, not find extcon related with
interrupt.
Will investigate tomorrow.


drivers/extcon/extcon-gpio.c

I think there is no need to use extcon, gpio is clear enough.
extcon-gpio.c even do not support dt.


well, add DT. The whole idea of free software is that we improve on
things we already have. EXTCON is *the* API to handle such things.


I think I am still not understanding extcon-gpio, not sure why need
use this API here.


because extcon is the API to use for external connectors. The same way
you use regulator framework to control that single GPIO tied to an
enable signal of a fixed regulator, you use extcon when you need to read
that gpio signal tied to id pin of the USB connector.


Here two gpio requires, one gpio as interrupt, in the interrupt
handler, we detect the gpio status judging the otg status.
extcon-gpio.c use the interrupt, then can we also use the gpio
interrupt.  Using extcon-gpio is used for saving gpio_request?


extcon is used to hide gpio_request from dwc2. dwc2 only knows about
extcon, not gpios. extcon will request the gpio and use it as interrupt
source. When an IRQ fires, it will read the gpio state and decide if it
should broadcast a message to tell dwc2 to become host or peripheral.


Thanks for the kind education, understand now.





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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Balbi

On 02/22/2015 12:21 AM, Felipe Balbi wrote:

Hi,

On Sat, Feb 21, 2015 at 11:03:05PM +0800, zhangfei wrote:

+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);


why is the PHY fiddling with pullups ?


We use this to enable/disable otg gadget mode.


I got that, but the pullups don't belong to the PHY, they belong to the
gadget.


The gpio_id  gpio_vbus are used to distinguish otg gadget mode or
host mode.
When micro usb or otg device attached to otg, gpio_vbus falling down.
And gpio_id = 1 is micro usb, gpio_id = 0 is otg device.


all of that I understood clearly :-)


So when micro usb attached, we enable gadget mode; while micro usb
detached, we disable gadget mode, and dwc2 will automatically set to
host mode.


that's all fine, I'm concerned about letting the PHY fiddle with
something it doesn't own. If I am to change pullups rules in udc-core,
this is likely to break down miserably and I don't want to have to go
through that.


Thanks for the clarifying.


no problem.


How about using usb_gadget_vbus_connect/disconnect, which are used in many
files under drivers/usb/phy.
There is no vbus_session in dwc2/gadget.c, I thought it would be same as
pullup.

However, usb_gadget_vbus_connect still need para gadget, where should we put
this file, drivers/usb/phy or drivers/phy


drivers/phy, if the framework misses anything you need, it's a great
opportunity to give back to the community by extending the framework.


Sorry, I am a little confused.
I need some concrete suggestion for the next step of this patch, which 
is required for the community board, hikey board.


Do you mean in the future we need use hsotg-phy instead of hsotg-uphy.
struct phy *phy;
struct usb_phy *uphy;
usb_phy has many members that struct phy does not have, including otg.
struct usb_otg  *otg;
Is that mean we need port such member from usb_phy to phy.

Besides, are you ok with using usb_gadget_vbus_connect/disconnect.



Scratching one's own itch kinda thing...


+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);


looks like this should be using extcon

Not used extcon before.
However, we need gpio_vbus interrupt.
Checked phy-tahvo.c and phy-omap-otg.c, not find extcon related with
interrupt.
Will investigate tomorrow.


drivers/extcon/extcon-gpio.c

I think there is no need to use extcon, gpio is clear enough.
extcon-gpio.c even do not support dt.


well, add DT. The whole idea of free software is that we improve on
things we already have. EXTCON is *the* API to handle such things.


I think I am still not understanding extcon-gpio, not sure why need use 
this API here.


Here two gpio requires, one gpio as interrupt, in the interrupt handler, 
we detect the gpio status judging the otg status.

extcon-gpio.c use the interrupt, then can we also use the gpio interrupt.
Using extcon-gpio is used for saving gpio_request?



Quite frankly, though, Roger Quadros (now in Cc) has been working to get
DT support on extcon-gpio, so perhaps wait for that and base your
patches on top of his.

Now your statement that GPIO is clear enough is completely bogus to me.

Why do we have fixed regulators with GPIO enable signals, right ? Might
as well just fiddle with the GPIO directly, right ? Wrong, the idea of
using these frameworks is to encapsulate implementation details and make
sure that if things change from one board to another, we can still use
our SW without major modifications.


+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_peripheral(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state;
+   }
+}
+
+static irqreturn_t hiusb_gpio_intr(int irq, void *data)
+{
+   struct hi6220_priv *priv = (struct hi6220_priv *)data;
+
+   /* add debounce time */
+   schedule_delayed_work(priv-work, msecs_to_jiffies(100));


this is really bad. We have threaded interrupt support, right ?


Since we use two gpio to distinguish gadget mode or host mode.
Debounce time can introduce more accuracy.


gpio_set_debounce() ?

Not all gpio.c support set_debounce, including gpio

Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Balbi

On 02/21/2015 12:06 AM, Felipe Balbi wrote:

Hi,

On Fri, Feb 20, 2015 at 11:44:37PM +0800, zhangfei wrote:

Hi, Balbi

On 02/20/2015 10:41 PM, Felipe Balbi wrote:


+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);


why is the PHY fiddling with pullups ?


We use this to enable/disable otg gadget mode.


I got that, but the pullups don't belong to the PHY, they belong to the
gadget.


The gpio_id  gpio_vbus are used to distinguish otg gadget mode or
host mode.
When micro usb or otg device attached to otg, gpio_vbus falling down.
And gpio_id = 1 is micro usb, gpio_id = 0 is otg device.


all of that I understood clearly :-)


So when micro usb attached, we enable gadget mode; while micro usb
detached, we disable gadget mode, and dwc2 will automatically set to
host mode.


that's all fine, I'm concerned about letting the PHY fiddle with
something it doesn't own. If I am to change pullups rules in udc-core,
this is likely to break down miserably and I don't want to have to go
through that.


Thanks for the clarifying.

How about using usb_gadget_vbus_connect/disconnect, which are used in 
many files under drivers/usb/phy.
There is no vbus_session in dwc2/gadget.c, I thought it would be same as 
pullup.


However, usb_gadget_vbus_connect still need para gadget, where should we 
put this file, drivers/usb/phy or drivers/phy





+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);


looks like this should be using extcon

Not used extcon before.
However, we need gpio_vbus interrupt.
Checked phy-tahvo.c and phy-omap-otg.c, not find extcon related with
interrupt.
Will investigate tomorrow.


drivers/extcon/extcon-gpio.c

I think there is no need to use extcon, gpio is clear enough.
extcon-gpio.c even do not support dt.




+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_peripheral(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state;
+   }
+}
+
+static irqreturn_t hiusb_gpio_intr(int irq, void *data)
+{
+   struct hi6220_priv *priv = (struct hi6220_priv *)data;
+
+   /* add debounce time */
+   schedule_delayed_work(priv-work, msecs_to_jiffies(100));


this is really bad. We have threaded interrupt support, right ?


Since we use two gpio to distinguish gadget mode or host mode.
Debounce time can introduce more accuracy.


gpio_set_debounce() ?

Not all gpio.c support set_debounce, including gpio-pl061.c.




I think threaded interrupt can not be used for adding debounce time.
Here add debounce is just for safety.


add the debounce to the gpio itself.


Here the debounce added only for safety.
gpio_id may mis-report when unplug usb, but it is correct for plug usb  
otg device.

So debounce can be omitted.
If you think using delayed work for debounce is ugly, it is fine switch 
to threaded_irq.


Thanks

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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

On 02/20/2015 12:38 PM, Felipe Balbi wrote:

On Fri, Feb 20, 2015 at 11:07:21AM +0800, zhangfei wrote:

Hi, Balbi

On 02/18/2015 10:35 PM, Felipe Balbi wrote:

On Wed, Feb 18, 2015 at 01:44:21PM +0800, zhangfei wrote:

Hi, Kishon

On 02/18/2015 01:35 PM, Kishon Vijay Abraham I wrote:

Hi,

On Thursday 12 February 2015 01:07 PM, Zhangfei Gao wrote:

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  drivers/phy/Kconfig  |   9 ++
  drivers/phy/Makefile |   1 +
  drivers/phy/phy-hi6220-usb.c | 306
+++
  3 files changed, 316 insertions(+)
  create mode 100644 drivers/phy/phy-hi6220-usb.c


why is this driver in drivers/phy when it doesn't use the generic PHY
framework at all?



Balbi recommended new drivers only on drivers/phy/, including usb
phy.


but it should use the API too. It's not only about a directory, you need
to use the new API.


So Move drivers/usb/phy/phy-hi6220-usb.c to
drivers/phy/phy-hi6220-usb.c, required by Balbi.


you're reading what I stated the way you like.


Sorry for my bad understanding.

Still not clear about the otg_set_peripheral, which is required in
phy-hi6220-usb.c

1. drivers/usb/dwc2/gadget.c use
otg_set_peripheral(hsotg-uphy-otg, hsotg-gadget);

2. include/linux/phy/phy.h
struct phy do not have member otg, while struct usb_phy has.

Could you give more hints?


your set_peripheral doesn't do anything, just holds a pointer. Might as
well not implement it. I'll review your driver more fully tomorrow.

There a few things which must be changed.



Thanks in advance.

We need this call back set_peripheral setting otg-gadget, which used in 
usb_gadget_connect/disconnect(otg-gadget).


The workable method test here is not provide phy-names = usb2-phy;
Then dwc2 will still use hsotg-uphy instead of hsotg-phy.
Though devm_phy_create is used in phy-hi6220-usb.c, phy_ops is not used 
in fact.


Thanks

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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Balbi

On 02/20/2015 10:41 PM, Felipe Balbi wrote:


+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);


why is the PHY fiddling with pullups ?


We use this to enable/disable otg gadget mode.

The gpio_id  gpio_vbus are used to distinguish otg gadget mode or host 
mode.

When micro usb or otg device attached to otg, gpio_vbus falling down.
And gpio_id = 1 is micro usb, gpio_id = 0 is otg device.

So when micro usb attached, we enable gadget mode; while micro usb 
detached, we disable gadget mode, and dwc2 will automatically set to 
host mode.





+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);


looks like this should be using extcon

Not used extcon before.
However, we need gpio_vbus interrupt.
Checked phy-tahvo.c and phy-omap-otg.c, not find extcon related with 
interrupt.

Will investigate tomorrow.




+
+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_peripheral(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state;
+   }
+}
+
+static irqreturn_t hiusb_gpio_intr(int irq, void *data)
+{
+   struct hi6220_priv *priv = (struct hi6220_priv *)data;
+
+   /* add debounce time */
+   schedule_delayed_work(priv-work, msecs_to_jiffies(100));


this is really bad. We have threaded interrupt support, right ?


Since we use two gpio to distinguish gadget mode or host mode.
Debounce time can introduce more accuracy.
I think threaded interrupt can not be used for adding debounce time.
Here add debounce is just for safety.

Thanks

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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Balbi

On 02/18/2015 10:35 PM, Felipe Balbi wrote:

On Wed, Feb 18, 2015 at 01:44:21PM +0800, zhangfei wrote:

Hi, Kishon

On 02/18/2015 01:35 PM, Kishon Vijay Abraham I wrote:

Hi,

On Thursday 12 February 2015 01:07 PM, Zhangfei Gao wrote:

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  drivers/phy/Kconfig  |   9 ++
  drivers/phy/Makefile |   1 +
  drivers/phy/phy-hi6220-usb.c | 306
+++
  3 files changed, 316 insertions(+)
  create mode 100644 drivers/phy/phy-hi6220-usb.c


why is this driver in drivers/phy when it doesn't use the generic PHY
framework at all?



Balbi recommended new drivers only on drivers/phy/, including usb
phy.


but it should use the API too. It's not only about a directory, you need
to use the new API.


So Move drivers/usb/phy/phy-hi6220-usb.c to
drivers/phy/phy-hi6220-usb.c, required by Balbi.


you're reading what I stated the way you like.


Sorry for my bad understanding.

Still not clear about the otg_set_peripheral, which is required in 
phy-hi6220-usb.c


1. drivers/usb/dwc2/gadget.c use
otg_set_peripheral(hsotg-uphy-otg, hsotg-gadget);

2. include/linux/phy/phy.h
struct phy do not have member otg, while struct usb_phy has.

Could you give more hints?

Thanks
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Re: [PATCH v4 4/4] phy: add phy-hi6220-usb

[zhangfei]

Hi, Kishon

On 02/18/2015 01:35 PM, Kishon Vijay Abraham I wrote:

Hi,

On Thursday 12 February 2015 01:07 PM, Zhangfei Gao wrote:

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  drivers/phy/Kconfig  |   9 ++
  drivers/phy/Makefile |   1 +
  drivers/phy/phy-hi6220-usb.c | 306
+++
  3 files changed, 316 insertions(+)
  create mode 100644 drivers/phy/phy-hi6220-usb.c


why is this driver in drivers/phy when it doesn't use the generic PHY
framework at all?



Balbi recommended new drivers only on drivers/phy/, including usb phy.
So Move drivers/usb/phy/phy-hi6220-usb.c to 
drivers/phy/phy-hi6220-usb.c, required by Balbi.


Thanks
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Re: [resend PATCH v3 4/4] usb: phy: add phy-hi6220-usb

[zhangfei]

On 02/10/2015 10:48 PM, Felipe Balbi wrote:


diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY

  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.

+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
  config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..00172d3 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
  obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
  obj-$(CONFIG_USB_EHCI_TEGRA)  += phy-tegra-usb.o
  obj-$(CONFIG_USB_GPIO_VBUS)   += phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220-usb.o


new drivers only on drivers/phy/, sorry.


One more quesiton.
Should I also move Documentation/devicetree/bindings/usb/hi6220-usb.txt 
to Documentation/devicetree/bindings/phy/?


I describing both usb controller and phy here, is it still should be put 
under Documentation/devicetree/bindings/usb/?


Hisilicon hi6220 SoC USB controller
-

usb controller is inherited from dwc2, refer dwc2.txt
-

Required properties:
- compatible: hisilicon,hi6220-usb
Refer to dwc2.txt for dwc2 usb properties


PHY:
-

Required properties:
- compatible: hisilicon,hi6220-usb-phy
- vcc-supply: phandle to the regulator that provides power to the PHY.
- clocks: phandle and clock specifier of the PHY clock.
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
- hisilicon,vbus-gpios: gpio of detecting vbus.
- hisilicon,id-gpios: gpio of detecting id.

Example:

sys_ctrl: syscon@f703 {
compatible = hisilicon,sysctrl, syscon;
reg = 0x0 0xf703 0x0 0x1000;
};

usb_phy: usb-phy {
compatible = hisilicon,hi6220-usb-phy;
vcc-supply = fixed_5v_hub;
hisilicon,vbus-gpios = gpio2 6 0;
hisilicon,id-gpios = gpio2 5 0;
hisilicon,peripheral-syscon = sys_ctrl;
clocks = clock_sys HI6220_USBOTG_HCLK;
};

usb: usb@f72c {
compatible = hisilicon,hi6220-usb;
reg = 0x0 0xf72c 0x0 0x4;
phys = usb_phy;
dr_mode = otg;
g-use-dma;
g-rx-fifo-size = 512;
g-np-tx-fifo-size = 128;
g-tx-fifo-size = 128;
interrupts = 0 77 0x4;
};




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[PATCH v4 2/4] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/usb/hi6220-usb.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt 
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..b3a7b5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,49 @@
+Hisilicon hi6220 SoC USB controller
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb
+Refer to dwc2.txt for dwc2 usb properties
+
+
+PHY:
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle and clock specifier of the PHY clock.
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,vbus-gpios: gpio of detecting vbus.
+- hisilicon,id-gpios: gpio of detecting id.
+
+Example:
+
+   sys_ctrl: syscon@f703 {
+   compatible = hisilicon,sysctrl, syscon;
+   reg = 0x0 0xf703 0x0 0x1000;
+   };
+
+   usb_phy: usb-phy {
+   compatible = hisilicon,hi6220-usb-phy;
+   vcc-supply = fixed_5v_hub;
+   hisilicon,vbus-gpios = gpio2 6 0;
+   hisilicon,id-gpios = gpio2 5 0;
+   hisilicon,peripheral-syscon = sys_ctrl;
+   clocks = clock_sys HI6220_USBOTG_HCLK;
+   };
+
+   usb: usb@f72c {
+   compatible = hisilicon,hi6220-usb;
+   reg = 0x0 0xf72c 0x0 0x4;
+   phys = usb_phy;
+   dr_mode = otg;
+   g-use-dma;
+   g-rx-fifo-size = 512;
+   g-np-tx-fifo-size = 128;
+   g-tx-fifo-size = 128;
+   interrupts = 0 77 0x4;
+   };
-- 
1.9.1

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[PATCH v4 3/4] usb: dwc2: platform: add hi6220 support

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/dwc2/platform.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index ae095f0..f7c67db 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -50,6 +50,35 @@
 
 static const char dwc2_driver_name[] = dwc2;
 
+static const struct dwc2_core_params params_hi6220 = {
+   .otg_cap= 2,/* No HNP/SRP capable */
+   .otg_ver= 0,/* 1.3 */
+   .dma_enable = 1,
+   .dma_desc_enable= 0,
+   .speed  = 0,/* High Speed */
+   .enable_dynamic_fifo= 1,
+   .en_multiple_tx_fifo= 1,
+   .host_rx_fifo_size  = 512,
+   .host_nperio_tx_fifo_size   = 512,
+   .host_perio_tx_fifo_size= 512,
+   .max_transfer_size  = 65535,
+   .max_packet_count   = 511,
+   .host_channels  = 16,
+   .phy_type   = 1,/* UTMI */
+   .phy_utmi_width = 8,
+   .phy_ulpi_ddr   = 0,/* Single */
+   .phy_ulpi_ext_vbus  = 0,
+   .i2c_enable = 0,
+   .ulpi_fs_ls = 0,
+   .host_support_fs_ls_low_power   = 0,
+   .host_ls_low_power_phy_clk  = 0,/* 48 MHz */
+   .ts_dline   = 0,
+   .reload_ctl = 0,
+   .ahbcfg = GAHBCFG_HBSTLEN_INCR16 
+ GAHBCFG_HBSTLEN_SHIFT,
+   .uframe_sched   = 0,
+};
+
 static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -129,6 +158,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = brcm,bcm2835-usb, .data = params_bcm2835 },
+   { .compatible = hisilicon,hi6220-usb, .data = params_hi6220 },
{ .compatible = rockchip,rk3066-usb, .data = params_rk3066 },
{ .compatible = snps,dwc2, .data = NULL },
{ .compatible = samsung,s3c6400-hsotg, .data = NULL},
-- 
1.9.1

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[PATCH v4 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

[Zhangfei Gao]

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - rockchip,rk3188-usb, rockchip,rk3066-usb, snps,dwc2: for rk3188 Soc;
   - rockchip,rk3288-usb, rockchip,rk3066-usb, snps,dwc2: for rk3288 Soc;
-- 
1.9.1

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[PATCH v4 4/4] phy: add phy-hi6220-usb

[Zhangfei Gao]

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/phy/Kconfig  |   9 ++
 drivers/phy/Makefile |   1 +
 drivers/phy/phy-hi6220-usb.c | 306 +++
 3 files changed, 316 insertions(+)
 create mode 100644 drivers/phy/phy-hi6220-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..40a1ef1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -162,6 +162,15 @@ config PHY_HIX5HD2_SATA
help
  Support for SATA PHY on Hisilicon hix5hd2 Soc.
 
+config PHY_HI6220_USB
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config PHY_SUN4I_USB
tristate Allwinner sunxi SoC USB PHY driver
depends on ARCH_SUNXI  HAS_IOMEM  OF
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..ec43c2d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_TI_PIPE3)+= 
phy-ti-pipe3.o
 obj-$(CONFIG_TWL4030_USB)  += phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)  += phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
+obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
 obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
 phy-exynos-usb2-y  += phy-samsung-usb2.o
diff --git a/drivers/phy/phy-hi6220-usb.c b/drivers/phy/phy-hi6220-usb.c
new file mode 100644
index 000..0d9f5ac
--- /dev/null
+++ b/drivers/phy/phy-hi6220-usb.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/regulator/consumer.h
+#include linux/usb/gadget.h
+#include linux/usb/otg.h
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct usb_phy phy;
+   struct delayed_work work;
+   struct regmap *reg;
+   struct clk *clk;
+   struct regulator *vcc;
+   struct device *dev;
+   int gpio_vbus;
+   int gpio_id;
+   enum usb_otg_state state;
+};
+
+static void hi6220_start_peripheral(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);
+
+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_peripheral(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state;
+   }
+}
+
+static

[PATCH v4 0/4] add usb support for hi6220

[Zhangfei Gao]

v4:
Move drivers/usb/phy/phy-hi6220-usb.c to drivers/phy/phy-hi6220-usb.c, required 
by Balbi.
Modify dt bindings per comments from Mark and Sergei

v3:
fix typo and add -EPROBE_DEFER of regulator, pointed by Peter

v2:
address comments from Sergei and Peter
add hi6220_phy_setup(false) code

v1:
hi6220 usb controller is inherited from dwc2
add phy accordingly
support otg gadget/host

Zhangfei Gao (4):
  Documentation: dt-bindings: add dt binding info for hi6220 dwc2
  Documentation: dt-bindings: add dt binding info for hi6220
  usb: dwc2: platform: add hi6220 support
  phy: add phy-hi6220-usb

 Documentation/devicetree/bindings/usb/dwc2.txt |   1 +
 .../devicetree/bindings/usb/hi6220-usb.txt |  49 
 drivers/phy/Kconfig|   9 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-hi6220-usb.c   | 306 +
 drivers/usb/dwc2/platform.c|  30 ++
 6 files changed, 396 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
 create mode 100644 drivers/phy/phy-hi6220-usb.c

-- 
1.9.1

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Re: [PATCH v3 4/5] usb: phy: load usb phy earlier

[zhangfei]

On 02/10/2015 10:49 PM, Felipe Balbi wrote:

On Tue, Feb 10, 2015 at 03:04:28PM +0800, Peter Chen wrote:

This patch does not belong to phy, so, doesn't need to
add phy in subject, meanwhile, please add GregKH as TO list,
he is the right one to queue this patch.

Reply-To:
In-Reply-To: 1423554627-694-5-git-send-email-zhangfei@linaro.org

On Tue, Feb 10, 2015 at 03:50:26PM +0800, Zhangfei Gao wrote:

Since phy is definitely used in usb controller, load the phy
earlier to make boot time shorter.

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Acked-by: Peter Chen peter.c...@freescale.com


NAK, make sure there are no such dependencies with your controller
driver. They should know how to defer probing if their resources aren't
available yet.


Sorry for the confusion,
There is no dependencies at all, just for optimization.
Peter already told me this patch should not be put here, causing confusion.
And I resend in another thread.

The controller is dwc2, which use defer probe. And dwc2 controller defer 
probe every time even the phy driver in the same folder.
Since we know the calling sequence, we can simply change the sequence to 
load the phy earlier.



However, as you said the new driver will be put in drivers/phy, there 
should be no such issue in the future.

It is OK not using this patch.

Thanks

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Re: [resend PATCH v3 4/4] usb: phy: add phy-hi6220-usb

[zhangfei]

On 02/10/2015 10:48 PM, Felipe Balbi wrote:

On Tue, Feb 10, 2015 at 05:10:04PM +0800, Zhangfei Gao wrote:

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  drivers/usb/phy/Kconfig  |   9 ++
  drivers/usb/phy/Makefile |   1 +
  drivers/usb/phy/phy-hi6220-usb.c | 306 +++
  3 files changed, 316 insertions(+)
  create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY

  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.

+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
  config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..00172d3 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
  obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
  obj-$(CONFIG_USB_EHCI_TEGRA)  += phy-tegra-usb.o
  obj-$(CONFIG_USB_GPIO_VBUS)   += phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220-usb.o


new drivers only on drivers/phy/, sorry.


OK, thanks for the info, I don't know this at all.
So even usb phy should be put under drivers/phy/.

Will change that.

Thanks Felipe
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Re: [PATCH v3 4/5] usb: phy: load usb phy earlier

[zhangfei]

On 02/10/2015 03:04 PM, Peter Chen wrote:

This patch does not belong to phy, so, doesn't need to
add phy in subject, meanwhile, please add GregKH as TO list,
he is the right one to queue this patch.

Reply-To:
In-Reply-To: 1423554627-694-5-git-send-email-zhangfei@linaro.org


OK, thanks Peter.
Will resend this patchset and drop this one.

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[resend PATCH v3 3/4] usb: dwc2: platform: add hi6220 support

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/dwc2/platform.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index ae095f0..f7c67db 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -50,6 +50,35 @@
 
 static const char dwc2_driver_name[] = dwc2;
 
+static const struct dwc2_core_params params_hi6220 = {
+   .otg_cap= 2,/* No HNP/SRP capable */
+   .otg_ver= 0,/* 1.3 */
+   .dma_enable = 1,
+   .dma_desc_enable= 0,
+   .speed  = 0,/* High Speed */
+   .enable_dynamic_fifo= 1,
+   .en_multiple_tx_fifo= 1,
+   .host_rx_fifo_size  = 512,
+   .host_nperio_tx_fifo_size   = 512,
+   .host_perio_tx_fifo_size= 512,
+   .max_transfer_size  = 65535,
+   .max_packet_count   = 511,
+   .host_channels  = 16,
+   .phy_type   = 1,/* UTMI */
+   .phy_utmi_width = 8,
+   .phy_ulpi_ddr   = 0,/* Single */
+   .phy_ulpi_ext_vbus  = 0,
+   .i2c_enable = 0,
+   .ulpi_fs_ls = 0,
+   .host_support_fs_ls_low_power   = 0,
+   .host_ls_low_power_phy_clk  = 0,/* 48 MHz */
+   .ts_dline   = 0,
+   .reload_ctl = 0,
+   .ahbcfg = GAHBCFG_HBSTLEN_INCR16 
+ GAHBCFG_HBSTLEN_SHIFT,
+   .uframe_sched   = 0,
+};
+
 static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -129,6 +158,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = brcm,bcm2835-usb, .data = params_bcm2835 },
+   { .compatible = hisilicon,hi6220-usb, .data = params_hi6220 },
{ .compatible = rockchip,rk3066-usb, .data = params_rk3066 },
{ .compatible = snps,dwc2, .data = NULL },
{ .compatible = samsung,s3c6400-hsotg, .data = NULL},
-- 
1.9.1

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[resend PATCH v3 2/4] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/usb/hi6220-usb.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt 
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..b8278de
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,49 @@
+Hisilicon hi6220 SoC USB controller
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb
+Refer to dwc2.txt for dwc2 usb properties
+
+
+PHY:
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle and clock specifier of the PHY clock.
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,gpio-vbus: gpio of detecting vbus.
+- hisilicon,gpio-id: gpio of detecting id.
+
+Example:
+
+   peripheral_ctrl: syscon@f703 {
+   compatible = syscon;
+   reg = 0x0 0xf703 0x0 0x1000;
+   };
+
+   usb2_phy: usbphy {
+   compatible = hisilicon,hi6220-usb-phy;
+   vcc-supply = fixed_5v_hub;
+   hisilicon,gpio-vbus = gpio2 6 0;
+   hisilicon,gpio-id = gpio2 5 0;
+   hisilicon,peripheral-syscon = peripheral_ctrl;
+   clocks = clock_sys HI6220_USBOTG_HCLK;
+   };
+
+   usb: usb@f72c {
+   compatible = hisilicon,hi6220-usb;
+   reg = 0x0 0xf72c 0x0 0x4;
+   phys = usb2_phy;
+   dr_mode = otg;
+   g-use-dma;
+   g-rx-fifo-size = 512;
+   g-np-tx-fifo-size = 128;
+   g-tx-fifo-size = 128;
+   interrupts = 0 77 0x4;
+   };
-- 
1.9.1

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[resend PATCH v3 4/4] usb: phy: add phy-hi6220-usb

[Zhangfei Gao]

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/phy/Kconfig  |   9 ++
 drivers/usb/phy/Makefile |   1 +
 drivers/usb/phy/phy-hi6220-usb.c | 306 +++
 3 files changed, 316 insertions(+)
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY
 
  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..00172d3 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
 obj-$(CONFIG_TWL6030_USB)  += phy-twl6030-usb.o
 obj-$(CONFIG_USB_EHCI_TEGRA)   += phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220-usb.o
 obj-$(CONFIG_USB_ISP1301)  += phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)  += phy-msm-usb.o
 obj-$(CONFIG_USB_MV_OTG)   += phy-mv-usb.o
diff --git a/drivers/usb/phy/phy-hi6220-usb.c b/drivers/usb/phy/phy-hi6220-usb.c
new file mode 100644
index 000..efb4bbb
--- /dev/null
+++ b/drivers/usb/phy/phy-hi6220-usb.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/regulator/consumer.h
+#include linux/usb/gadget.h
+#include linux/usb/otg.h
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct usb_phy phy;
+   struct delayed_work work;
+   struct regmap *reg;
+   struct clk *clk;
+   struct regulator *vcc;
+   struct device *dev;
+   int gpio_vbus;
+   int gpio_id;
+   enum usb_otg_state state;
+};
+
+static void hi6220_start_periphrals(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);
+
+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_periphrals(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state

[resend PATCH v3 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

[Zhangfei Gao]

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - rockchip,rk3188-usb, rockchip,rk3066-usb, snps,dwc2: for rk3188 Soc;
   - rockchip,rk3288-usb, rockchip,rk3066-usb, snps,dwc2: for rk3288 Soc;
-- 
1.9.1

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[resend PATCH v3 0/4] add usb support for hi6220

[Zhangfei Gao]

v3:
fix typo and add -EPROBE_DEFER of regulator, pointed by Peter

v2:
address comments from Sergei and Peter
add hi6220_phy_setup(false) code

v1:
hi6220 usb controller is inherited from dwc2
add phy accordingly
support otg gadget/host

Zhangfei Gao (4):
  Documentation: dt-bindings: add dt binding info for hi6220 dwc2
  Documentation: dt-bindings: add dt binding info for hi6220
  usb: dwc2: platform: add hi6220 support
  usb: phy: add phy-hi6220-usb

 Documentation/devicetree/bindings/usb/dwc2.txt |   1 +
 .../devicetree/bindings/usb/hi6220-usb.txt |  49 
 drivers/usb/dwc2/platform.c|  30 ++
 drivers/usb/phy/Kconfig|   9 +
 drivers/usb/phy/Makefile   |   1 +
 drivers/usb/phy/phy-hi6220-usb.c   | 306 +
 6 files changed, 396 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

-- 
1.9.1

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Re: [PATCH v2 4/4] usb: phy: add phy-hi6220-usb

[Zhangfei Gao]

On 9 February 2015 at 22:26, zhangfei zhangfei@linaro.org wrote:


 On 02/09/2015 10:11 AM, Peter Chen wrote:

 +static void hi6220_detect_work(struct work_struct *work)
 +{
 +   struct hi6220_priv *priv =
 +   container_of(work, struct hi6220_priv, work.work);
 +   int gpio_id, gpio_vubs;


 %s/gpio_vubs/gpio_vbus


 Yes, typo


 +static void hi6220_phy_setup(struct hi6220_priv *priv, bool on)
 +{
 +   struct regmap *reg = priv-reg;
 +   u32 val, mask;
 +   int ret;
 +
 +   if (priv-reg == NULL)
 +   return;
 +
 +   if (on) {
 +   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
 + RST0_USBOTG | RST0_USBOTG_32K;
 +   mask = val;
 +   ret = regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask,
 val);
 +   if (ret)
 +   return;
 +
 +   ret = regmap_read(reg, SC_PERIPH_CTRL5, val);
 +   val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB;
 +   mask = val | CTRL5_PICOPHY_BC_MODE;
 +   ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask,
 val);
 +   if (ret)
 +   return;
 +
 +   val =  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL |
 +  CTRL4_OTG_PHY_SEL;
 +   mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE;
 +   ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask,
 val);
 +   if (ret)
 +   return;
 +
 +   ret = regmap_write(reg, SC_PERIPH_CTRL8,
 EYE_PATTERN_PARA);
 +   if (ret)
 +   return;
 +   } else {
 +   val = CTRL4_PICO_SIDDQ;
 +   mask = val;
 +   ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask,
 val);
 +   if (ret)
 +   return;
 +
 +   ret = regmap_read(reg, SC_PERIPH_CTRL4, val);
 +
 +   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
 + RST0_USBOTG | RST0_USBOTG_32K;
 +   mask = val;
 +   ret = regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask,
 val);
 +   if (ret)
 +   return;
 +   }


 You have return value check for regmap API, but no error message or
 return value for hi6220_phy_setup, it looks strange.


 There was dev_err(priv-dev, failed to setup phy\n);
 Then I found priv-dev is the only one place to use, so I remove this for
 simple.



 +}
 +
 +static int hi6220_phy_probe(struct platform_device *pdev)
 +{
 +   struct hi6220_priv *priv;
 +   struct usb_otg *otg;
 +   struct device_node *np = pdev-dev.of_node;
 +   int ret, irq;
 +
 +   priv = devm_kzalloc(pdev-dev, sizeof(*priv), GFP_KERNEL);
 +   if (!priv)
 +   return -ENOMEM;
 +
 +   otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
 +   if (!otg)
 +   return -ENOMEM;
 +
 +   priv-phy.dev = pdev-dev;
 +   priv-phy.otg = otg;
 +   priv-phy.label = hi6220;
 +   priv-phy.type = USB_PHY_TYPE_USB2;
 +   otg-set_peripheral = hi6220_set_peripheral;
 +   platform_set_drvdata(pdev, priv);
 +
 +   priv-gpio_vbus = of_get_named_gpio(np, hisilicon,gpio-vbus,
 0);
 +   if (priv-gpio_vbus == -EPROBE_DEFER)
 +   return -EPROBE_DEFER;
 +   if (!gpio_is_valid(priv-gpio_vbus)) {
 +   dev_err(pdev-dev, invalid gpio %d\n,
 priv-gpio_vbus);
 +   return -ENODEV;
 +   }
 +
 +   priv-gpio_id = of_get_named_gpio(np, hisilicon,gpio-id, 0);
 +   if (priv-gpio_id == -EPROBE_DEFER)
 +   return -EPROBE_DEFER;
 +   if (!gpio_is_valid(priv-gpio_id)) {
 +   dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_id);
 +   return -ENODEV;
 +   }
 +
 +   priv-reg = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
 +   hisilicon,peripheral-syscon);
 +   if (IS_ERR(priv-reg))
 +   priv-reg = NULL;
 +


 see my comments at your v1.

 As replied in v1, EPROBE_DEFER does not needed.
 syscon is register far earlier.


 +   INIT_DELAYED_WORK(priv-work, hi6220_detect_work);
 +
 +   ret = devm_gpio_request_one(pdev-dev, priv-gpio_vbus,
 +   GPIOF_IN, gpio_vbus);
 +   if (ret  0) {
 +   dev_err(pdev-dev, gpio request failed for
 gpio_vbus\n);
 +   return ret;
 +   }
 +
 +   ret = devm_gpio_request_one(pdev-dev, priv-gpio_id,
 +   GPIOF_IN, gpio_id);
 +   if (ret  0) {
 +   dev_err(pdev-dev, gpio request failed for gpio_id\n);
 +   return ret;
 +   }
 +
 +   priv-vcc = devm_regulator_get(pdev-dev, vcc);
 +   if (!IS_ERR(priv-vcc)) {


 EPROBE_DEFER?

 No, this is not needed, since regulator is registered earlier than device.

 drivers/Makefile
 # regulators early, since some subsystems

[PATCH v3 2/5] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/usb/hi6220-usb.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt 
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..b8278de
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,49 @@
+Hisilicon hi6220 SoC USB controller
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb
+Refer to dwc2.txt for dwc2 usb properties
+
+
+PHY:
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle and clock specifier of the PHY clock.
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,gpio-vbus: gpio of detecting vbus.
+- hisilicon,gpio-id: gpio of detecting id.
+
+Example:
+
+   peripheral_ctrl: syscon@f703 {
+   compatible = syscon;
+   reg = 0x0 0xf703 0x0 0x1000;
+   };
+
+   usb2_phy: usbphy {
+   compatible = hisilicon,hi6220-usb-phy;
+   vcc-supply = fixed_5v_hub;
+   hisilicon,gpio-vbus = gpio2 6 0;
+   hisilicon,gpio-id = gpio2 5 0;
+   hisilicon,peripheral-syscon = peripheral_ctrl;
+   clocks = clock_sys HI6220_USBOTG_HCLK;
+   };
+
+   usb: usb@f72c {
+   compatible = hisilicon,hi6220-usb;
+   reg = 0x0 0xf72c 0x0 0x4;
+   phys = usb2_phy;
+   dr_mode = otg;
+   g-use-dma;
+   g-rx-fifo-size = 512;
+   g-np-tx-fifo-size = 128;
+   g-tx-fifo-size = 128;
+   interrupts = 0 77 0x4;
+   };
-- 
1.9.1

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[PATCH v3 1/5] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

[Zhangfei Gao]

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - rockchip,rk3188-usb, rockchip,rk3066-usb, snps,dwc2: for rk3188 Soc;
   - rockchip,rk3288-usb, rockchip,rk3066-usb, snps,dwc2: for rk3288 Soc;
-- 
1.9.1

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[PATCH v3 0/5] add usb support for hi6220

[Zhangfei Gao]

v3:
fix typo and add -EPROBE_DEFER of regulator, pointed by Peter

v2:
address comments from Sergei and Peter
add hi6220_phy_setup(false) code

v1:
hi6220 usb controller is inherited from dwc2
add phy accordingly
support otg gadget/host


Zhangfei Gao (5):
  Documentation: dt-bindings: add dt binding info for hi6220 dwc2
  Documentation: dt-bindings: add dt binding info for hi6220
  usb: dwc2: platform: add hi6220 support
  usb: phy: load usb phy earlier
  usb: phy: add phy-hi6220-usb

 Documentation/devicetree/bindings/usb/dwc2.txt |   1 +
 .../devicetree/bindings/usb/hi6220-usb.txt |  49 
 drivers/usb/Makefile   |   2 +-
 drivers/usb/dwc2/platform.c|  30 ++
 drivers/usb/phy/Kconfig|   9 +
 drivers/usb/phy/Makefile   |   1 +
 drivers/usb/phy/phy-hi6220-usb.c   | 308 +
 7 files changed, 399 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

-- 
1.9.1

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[PATCH v3 5/5] usb: phy: add phy-hi6220-usb

[Zhangfei Gao]

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/phy/Kconfig  |   9 ++
 drivers/usb/phy/Makefile |   1 +
 drivers/usb/phy/phy-hi6220-usb.c | 308 +++
 3 files changed, 318 insertions(+)
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY
 
  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..00172d3 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
 obj-$(CONFIG_TWL6030_USB)  += phy-twl6030-usb.o
 obj-$(CONFIG_USB_EHCI_TEGRA)   += phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220-usb.o
 obj-$(CONFIG_USB_ISP1301)  += phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)  += phy-msm-usb.o
 obj-$(CONFIG_USB_MV_OTG)   += phy-mv-usb.o
diff --git a/drivers/usb/phy/phy-hi6220-usb.c b/drivers/usb/phy/phy-hi6220-usb.c
new file mode 100644
index 000..b251e85
--- /dev/null
+++ b/drivers/usb/phy/phy-hi6220-usb.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/regulator/consumer.h
+#include linux/usb/gadget.h
+#include linux/usb/otg.h
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct usb_phy phy;
+   struct delayed_work work;
+   struct regmap *reg;
+   struct clk *clk;
+   struct regulator *vcc;
+   struct device *dev;
+   int gpio_vbus;
+   int gpio_id;
+   enum usb_otg_state state;
+};
+
+static void hi6220_start_periphrals(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vbus;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vbus = gpio_get_value_cansleep(priv-gpio_vbus);
+
+   if (gpio_vbus == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_periphrals(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state

[PATCH v3 4/5] usb: phy: load usb phy earlier

[Zhangfei Gao]

Since phy is definitely used in usb controller, load the phy
earlier to make boot time shorter.

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Acked-by: Peter Chen peter.c...@freescale.com
---
 drivers/usb/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 2f1e2aa..d8926c6 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -5,6 +5,7 @@
 # Object files in subdirectories
 
 obj-$(CONFIG_USB)  += core/
+obj-$(CONFIG_USB_SUPPORT)  += phy/
 
 obj-$(CONFIG_USB_DWC3) += dwc3/
 obj-$(CONFIG_USB_DWC2) += dwc2/
@@ -48,7 +49,6 @@ obj-$(CONFIG_USB_MICROTEK)+= image/
 obj-$(CONFIG_USB_SERIAL)   += serial/
 
 obj-$(CONFIG_USB)  += misc/
-obj-$(CONFIG_USB_SUPPORT)  += phy/
 obj-$(CONFIG_EARLY_PRINTK_DBGP)+= early/
 
 obj-$(CONFIG_USB_ATM)  += atm/
-- 
1.9.1

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Re: [PATCH v2 4/4] usb: phy: add phy-hi6220-usb

[zhangfei]

On 02/09/2015 10:11 AM, Peter Chen wrote:


+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vubs;


%s/gpio_vubs/gpio_vbus


Yes, typo


+static void hi6220_phy_setup(struct hi6220_priv *priv, bool on)
+{
+   struct regmap *reg = priv-reg;
+   u32 val, mask;
+   int ret;
+
+   if (priv-reg == NULL)
+   return;
+
+   if (on) {
+   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
+ RST0_USBOTG | RST0_USBOTG_32K;
+   mask = val;
+   ret = regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val);
+   if (ret)
+   return;
+
+   ret = regmap_read(reg, SC_PERIPH_CTRL5, val);
+   val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB;
+   mask = val | CTRL5_PICOPHY_BC_MODE;
+   ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val);
+   if (ret)
+   return;
+
+   val =  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL |
+  CTRL4_OTG_PHY_SEL;
+   mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE;
+   ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
+   if (ret)
+   return;
+
+   ret = regmap_write(reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA);
+   if (ret)
+   return;
+   } else {
+   val = CTRL4_PICO_SIDDQ;
+   mask = val;
+   ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
+   if (ret)
+   return;
+
+   ret = regmap_read(reg, SC_PERIPH_CTRL4, val);
+
+   val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
+ RST0_USBOTG | RST0_USBOTG_32K;
+   mask = val;
+   ret = regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val);
+   if (ret)
+   return;
+   }


You have return value check for regmap API, but no error message or
return value for hi6220_phy_setup, it looks strange.


There was dev_err(priv-dev, failed to setup phy\n);
Then I found priv-dev is the only one place to use, so I remove this 
for simple.





+}
+
+static int hi6220_phy_probe(struct platform_device *pdev)
+{
+   struct hi6220_priv *priv;
+   struct usb_otg *otg;
+   struct device_node *np = pdev-dev.of_node;
+   int ret, irq;
+
+   priv = devm_kzalloc(pdev-dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv)
+   return -ENOMEM;
+
+   otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
+   if (!otg)
+   return -ENOMEM;
+
+   priv-phy.dev = pdev-dev;
+   priv-phy.otg = otg;
+   priv-phy.label = hi6220;
+   priv-phy.type = USB_PHY_TYPE_USB2;
+   otg-set_peripheral = hi6220_set_peripheral;
+   platform_set_drvdata(pdev, priv);
+
+   priv-gpio_vbus = of_get_named_gpio(np, hisilicon,gpio-vbus, 0);
+   if (priv-gpio_vbus == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   if (!gpio_is_valid(priv-gpio_vbus)) {
+   dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_vbus);
+   return -ENODEV;
+   }
+
+   priv-gpio_id = of_get_named_gpio(np, hisilicon,gpio-id, 0);
+   if (priv-gpio_id == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   if (!gpio_is_valid(priv-gpio_id)) {
+   dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_id);
+   return -ENODEV;
+   }
+
+   priv-reg = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
+   hisilicon,peripheral-syscon);
+   if (IS_ERR(priv-reg))
+   priv-reg = NULL;
+


see my comments at your v1.

As replied in v1, EPROBE_DEFER does not needed.
syscon is register far earlier.




+   INIT_DELAYED_WORK(priv-work, hi6220_detect_work);
+
+   ret = devm_gpio_request_one(pdev-dev, priv-gpio_vbus,
+   GPIOF_IN, gpio_vbus);
+   if (ret  0) {
+   dev_err(pdev-dev, gpio request failed for gpio_vbus\n);
+   return ret;
+   }
+
+   ret = devm_gpio_request_one(pdev-dev, priv-gpio_id,
+   GPIOF_IN, gpio_id);
+   if (ret  0) {
+   dev_err(pdev-dev, gpio request failed for gpio_id\n);
+   return ret;
+   }
+
+   priv-vcc = devm_regulator_get(pdev-dev, vcc);
+   if (!IS_ERR(priv-vcc)) {


EPROBE_DEFER?

No, this is not needed, since regulator is registered earlier than device.

drivers/Makefile
# regulators early, since some subsystems rely on them to initialize
obj-$(CONFIG_REGULATOR) += regulator/

EPROBE_DEFER should be the last option we rely on.


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Re: [PATCH 4/4] usb: phy: add phy-hi6220

[Zhangfei Gao]

On 9 February 2015 at 09:57, Peter Chen peter.c...@freescale.com wrote:
  +static int hi6220_phy_probe(struct platform_device *pdev)
  +{
  + struct hi6220_priv *priv;
  + struct usb_otg *otg;
  + struct device_node *np = pdev-dev.of_node;
  + int ret, irq;
  +
  + priv = devm_kzalloc(pdev-dev, sizeof(*priv), GFP_KERNEL);
  + if (!priv)
  + return -ENOMEM;
  +
  + otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
  + if (!otg)
  + return -ENOMEM;
  +
  + priv-phy.dev = pdev-dev;
  + priv-phy.otg = otg;
  + priv-phy.label = hi6220;
  + platform_set_drvdata(pdev, priv);
  + otg-set_peripheral = mv_otg_set_peripheral;
  +
  + priv-gpio_vbus_det = of_get_named_gpio(np, 
  hisilicon,gpio_vbus_det, 0);
  + if (priv-gpio_vbus_det == -EPROBE_DEFER)
  + return -EPROBE_DEFER;
  + if (!gpio_is_valid(priv-gpio_vbus_det)) {
  + dev_err(pdev-dev, invalid gpio %d\n, 
  priv-gpio_vbus_det);
  + return -ENODEV;
  + }
  +
  + priv-gpio_id_det = of_get_named_gpio(np, hisilicon,gpio_id_det, 
  0);
  + if (priv-gpio_id_det == -EPROBE_DEFER)
  + return -EPROBE_DEFER;
  + if (!gpio_is_valid(priv-gpio_id_det)) {
  + dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_id_det);
  + return -ENODEV;
  + }
  +
  + priv-reg = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
  + hisilicon,peripheral-syscon);
  + if (IS_ERR(priv-reg))
  + priv-reg = NULL;
 
  You may differentiate -ENODEV and other errors, for other errors, you
  can show an error, and return directly.

 Here I want to set this property as optional, in case other platform
 do not need this property.
 So phy_setup also add protection if (priv-reg == NULL) return;


 If syscon_regmap_lookup_by_phandle returns -EPROBE_DEFER, you may want
 to try later.

It should not.
syscon is postcore_initcall(syscon_init);

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[PATCH v2 4/4] usb: phy: add phy-hi6220-usb

[Zhangfei Gao]

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/phy/Kconfig  |   9 ++
 drivers/usb/phy/Makefile |   1 +
 drivers/usb/phy/phy-hi6220-usb.c | 297 +++
 3 files changed, 307 insertions(+)
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY
 
  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..00172d3 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
 obj-$(CONFIG_TWL6030_USB)  += phy-twl6030-usb.o
 obj-$(CONFIG_USB_EHCI_TEGRA)   += phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220-usb.o
 obj-$(CONFIG_USB_ISP1301)  += phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)  += phy-msm-usb.o
 obj-$(CONFIG_USB_MV_OTG)   += phy-mv-usb.o
diff --git a/drivers/usb/phy/phy-hi6220-usb.c b/drivers/usb/phy/phy-hi6220-usb.c
new file mode 100644
index 000..8092bca
--- /dev/null
+++ b/drivers/usb/phy/phy-hi6220-usb.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/regulator/consumer.h
+#include linux/usb/gadget.h
+#include linux/usb/otg.h
+
+#define SC_PERIPH_CTRL40x00c
+
+#define CTRL4_PICO_SIDDQ   BIT(6)
+#define CTRL4_PICO_OGDISABLE   BIT(8)
+#define CTRL4_PICO_VBUSVLDEXT  BIT(10)
+#define CTRL4_PICO_VBUSVLDEXTSEL   BIT(11)
+#define CTRL4_OTG_PHY_SEL  BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define CTRL5_USBOTG_RES_SEL   BIT(3)
+#define CTRL5_PICOPHY_ACAENB   BIT(4)
+#define CTRL5_PICOPHY_BC_MODE  BIT(5)
+#define CTRL5_PICOPHY_CHRGSEL  BIT(6)
+#define CTRL5_PICOPHY_VDATSRCEND   BIT(7)
+#define CTRL5_PICOPHY_VDATDETENB   BIT(8)
+#define CTRL5_PICOPHY_DCDENB   BIT(9)
+#define CTRL5_PICOPHY_IDDIGBIT(10)
+
+#define SC_PERIPH_CTRL80x018
+#define SC_PERIPH_RSTEN0   0x300
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define RST0_USBOTG_BUSBIT(4)
+#define RST0_POR_PICOPHY   BIT(5)
+#define RST0_USBOTGBIT(6)
+#define RST0_USBOTG_32KBIT(7)
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+struct hi6220_priv {
+   struct usb_phy phy;
+   struct delayed_work work;
+   struct regmap *reg;
+   struct clk *clk;
+   struct regulator *vcc;
+   int gpio_vbus;
+   int gpio_id;
+   enum usb_otg_state state;
+};
+
+static void hi6220_start_periphrals(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int gpio_id, gpio_vubs;
+   enum usb_otg_state state;
+
+   if (!gpio_is_valid(priv-gpio_id) || !gpio_is_valid(priv-gpio_vbus))
+   return;
+
+   gpio_id = gpio_get_value_cansleep(priv-gpio_id);
+   gpio_vubs = gpio_get_value_cansleep(priv-gpio_vbus);
+
+   if (gpio_vubs == 0) {
+   if (gpio_id == 1)
+   state = OTG_STATE_B_PERIPHERAL;
+   else
+   state = OTG_STATE_A_HOST;
+   } else {
+   state = OTG_STATE_A_HOST;
+   }
+
+   if (priv-state != state) {
+   hi6220_start_periphrals(priv, state == OTG_STATE_B_PERIPHERAL);
+   priv-state = state;
+   }
+}
+
+static

[PATCH v2 2/4] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/usb/hi6220-usb.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt 
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..b8278de
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,49 @@
+Hisilicon hi6220 SoC USB controller
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb
+Refer to dwc2.txt for dwc2 usb properties
+
+
+PHY:
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle and clock specifier of the PHY clock.
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,gpio-vbus: gpio of detecting vbus.
+- hisilicon,gpio-id: gpio of detecting id.
+
+Example:
+
+   peripheral_ctrl: syscon@f703 {
+   compatible = syscon;
+   reg = 0x0 0xf703 0x0 0x1000;
+   };
+
+   usb2_phy: usbphy {
+   compatible = hisilicon,hi6220-usb-phy;
+   vcc-supply = fixed_5v_hub;
+   hisilicon,gpio-vbus = gpio2 6 0;
+   hisilicon,gpio-id = gpio2 5 0;
+   hisilicon,peripheral-syscon = peripheral_ctrl;
+   clocks = clock_sys HI6220_USBOTG_HCLK;
+   };
+
+   usb: usb@f72c {
+   compatible = hisilicon,hi6220-usb;
+   reg = 0x0 0xf72c 0x0 0x4;
+   phys = usb2_phy;
+   dr_mode = otg;
+   g-use-dma;
+   g-rx-fifo-size = 512;
+   g-np-tx-fifo-size = 128;
+   g-tx-fifo-size = 128;
+   interrupts = 0 77 0x4;
+   };
-- 
1.9.1

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[PATCH v2 3/4] usb: dwc2: platform: add hi6220 support

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/dwc2/platform.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index ae095f0..f7c67db 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -50,6 +50,35 @@
 
 static const char dwc2_driver_name[] = dwc2;
 
+static const struct dwc2_core_params params_hi6220 = {
+   .otg_cap= 2,/* No HNP/SRP capable */
+   .otg_ver= 0,/* 1.3 */
+   .dma_enable = 1,
+   .dma_desc_enable= 0,
+   .speed  = 0,/* High Speed */
+   .enable_dynamic_fifo= 1,
+   .en_multiple_tx_fifo= 1,
+   .host_rx_fifo_size  = 512,
+   .host_nperio_tx_fifo_size   = 512,
+   .host_perio_tx_fifo_size= 512,
+   .max_transfer_size  = 65535,
+   .max_packet_count   = 511,
+   .host_channels  = 16,
+   .phy_type   = 1,/* UTMI */
+   .phy_utmi_width = 8,
+   .phy_ulpi_ddr   = 0,/* Single */
+   .phy_ulpi_ext_vbus  = 0,
+   .i2c_enable = 0,
+   .ulpi_fs_ls = 0,
+   .host_support_fs_ls_low_power   = 0,
+   .host_ls_low_power_phy_clk  = 0,/* 48 MHz */
+   .ts_dline   = 0,
+   .reload_ctl = 0,
+   .ahbcfg = GAHBCFG_HBSTLEN_INCR16 
+ GAHBCFG_HBSTLEN_SHIFT,
+   .uframe_sched   = 0,
+};
+
 static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -129,6 +158,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = brcm,bcm2835-usb, .data = params_bcm2835 },
+   { .compatible = hisilicon,hi6220-usb, .data = params_hi6220 },
{ .compatible = rockchip,rk3066-usb, .data = params_rk3066 },
{ .compatible = snps,dwc2, .data = NULL },
{ .compatible = samsung,s3c6400-hsotg, .data = NULL},
-- 
1.9.1

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[PATCH v2 0/4] add usb support for hi6220

[Zhangfei Gao]

v2:
address comments from Sergei and Peter
add hi6220_phy_setup(false) code

v1:
hi6220 usb controller is inherited from dwc2
add phy accordingly
support otg gadget/host

Zhangfei Gao (4):
  Documentation: dt-bindings: add dt binding info for hi6220 dwc2
  Documentation: dt-bindings: add dt binding info for hi6220
  usb: dwc2: platform: add hi6220 support
  usb: phy: add phy-hi6220-usb

 Documentation/devicetree/bindings/usb/dwc2.txt |   1 +
 .../devicetree/bindings/usb/hi6220-usb.txt |  49 
 drivers/usb/dwc2/platform.c|  30 +++
 drivers/usb/phy/Kconfig|   9 +
 drivers/usb/phy/Makefile   |   1 +
 drivers/usb/phy/phy-hi6220-usb.c   | 297 +
 6 files changed, 387 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
 create mode 100644 drivers/usb/phy/phy-hi6220-usb.c

-- 
1.9.1

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[PATCH v2 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

[Zhangfei Gao]

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - rockchip,rk3188-usb, rockchip,rk3066-usb, snps,dwc2: for rk3188 Soc;
   - rockchip,rk3288-usb, rockchip,rk3066-usb, snps,dwc2: for rk3288 Soc;
-- 
1.9.1

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Re: [PATCH 4/4] usb: phy: add phy-hi6220

[Zhangfei Gao]

On 6 February 2015 at 16:41, Peter Chen peter.c...@freescale.com wrote:
 On Thu, Feb 05, 2015 at 10:47:00PM +0800, Zhangfei Gao wrote:

 @@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)+= 
 phy-samsung-usb.o
  obj-$(CONFIG_TWL6030_USB)+= phy-twl6030-usb.o
  obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
  obj-$(CONFIG_USB_GPIO_VBUS)  += phy-gpio-vbus-usb.o
 +obj-$(CONFIG_USB_HI6220_PHY) += phy-hi6220.o

 To align the naming method, phy-hi6220-usb is better.
Sure,


 +enum usb_mode {
 + USB_EMPTY,
 + GADGET_DEVICE,
 + OTG_HOST,
 +};

 This usb_mode is a little strange, what state you would like to
 use?

it is internal state machine, to distinguish otg gadget mode and host mode.
There are two gpio, we use gpio_vbus interrupt as well as gpio_id
status to distinguish gadget or host.

 +static irqreturn_t hiusb_gpio_intr(int irq, void *data)
 +{
 + struct hi6220_priv *priv = (struct hi6220_priv *)data;
 +
 + /* add debounce time */
 + schedule_delayed_work(priv-work, msecs_to_jiffies(100));
 + return IRQ_HANDLED;
 +}
 +
 +static int mv_otg_set_peripheral(struct usb_otg *otg,

 mv? You may want to use hi
Yes, my bad.


 +static void hi6220_phy_setup(struct hi6220_priv *priv)
 +{
 + u32 val, mask;
 + int ret;
 +
 + if (priv-reg == NULL)
 + return;
 +
 + val = PERIPH_RSTDIS0_USBOTG_BUS | PERIPH_RSTDIS0_POR_PICOPHY |
 +   PERIPH_RSTDIS0_USBOTG | PERIPH_RSTDIS0_USBOTG_32K;
 + mask = val;
 + ret = regmap_update_bits(priv-reg, SC_PERIPH_RSTDIS0, mask, val);
 + if (ret)
 + return;
 +
 + ret = regmap_read(priv-reg, SC_PERIPH_CTRL5, val);
 + val = PERIPH_CTRL5_USBOTG_RES_SEL | PERIPH_CTRL5_PICOPHY_ACAENB;
 + mask = val | PERIPH_CTRL5_PICOPHY_BC_MODE;
 + ret = regmap_update_bits(priv-reg, SC_PERIPH_CTRL5, mask, val);
 + if (ret)
 + return;
 +
 + val =  PERIPH_CTRL4_PICO_VBUSVLDEXT | PERIPH_CTRL4_PICO_VBUSVLDEXTSEL |
 +PERIPH_CTRL4_OTG_PHY_SEL;
 + mask = val | PERIPH_CTRL4_PICO_SIDDQ | PERIPH_CTRL4_PICO_OGDISABLE;
 + ret = regmap_update_bits(priv-reg, SC_PERIPH_CTRL4, mask, val);
 + if (ret)
 + return;
 +
 + ret = regmap_write(priv-reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA);
 + if (ret)
 + return;
 +}
 +
 +static int hi6220_phy_probe(struct platform_device *pdev)
 +{
 + struct hi6220_priv *priv;
 + struct usb_otg *otg;
 + struct device_node *np = pdev-dev.of_node;
 + int ret, irq;
 +
 + priv = devm_kzalloc(pdev-dev, sizeof(*priv), GFP_KERNEL);
 + if (!priv)
 + return -ENOMEM;
 +
 + otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL);
 + if (!otg)
 + return -ENOMEM;
 +
 + priv-phy.dev = pdev-dev;
 + priv-phy.otg = otg;
 + priv-phy.label = hi6220;
 + platform_set_drvdata(pdev, priv);
 + otg-set_peripheral = mv_otg_set_peripheral;
 +
 + priv-gpio_vbus_det = of_get_named_gpio(np, hisilicon,gpio_vbus_det, 
 0);
 + if (priv-gpio_vbus_det == -EPROBE_DEFER)
 + return -EPROBE_DEFER;
 + if (!gpio_is_valid(priv-gpio_vbus_det)) {
 + dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_vbus_det);
 + return -ENODEV;
 + }
 +
 + priv-gpio_id_det = of_get_named_gpio(np, hisilicon,gpio_id_det, 0);
 + if (priv-gpio_id_det == -EPROBE_DEFER)
 + return -EPROBE_DEFER;
 + if (!gpio_is_valid(priv-gpio_id_det)) {
 + dev_err(pdev-dev, invalid gpio %d\n, priv-gpio_id_det);
 + return -ENODEV;
 + }
 +
 + priv-reg = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
 + hisilicon,peripheral-syscon);
 + if (IS_ERR(priv-reg))
 + priv-reg = NULL;

 You may differentiate -ENODEV and other errors, for other errors, you
 can show an error, and return directly.

Here I want to set this property as optional, in case other platform
do not need this property.
So phy_setup also add protection if (priv-reg == NULL) return;


 +
 + INIT_DELAYED_WORK(priv-work, hi6220_detect_work);
 +
 + ret = devm_gpio_request_one(pdev-dev, priv-gpio_vbus_det,
 + GPIOF_IN, gpio_vbus_det);
 + if (ret  0) {
 + dev_err(pdev-dev, gpio request failed for gpio_vbus_det\n);
 + return ret;
 + }
 +
 + ret = devm_gpio_request_one(pdev-dev, priv-gpio_id_det,
 + GPIOF_IN, gpio_id_det);
 + if (ret  0) {
 + dev_err(pdev-dev, gpio request failed for gpio_id_det\n);
 + return ret;
 + }
 +
 + priv-vcc = devm_regulator_get(pdev-dev, vcc);
 + if (!IS_ERR(priv-vcc)) {
 + ret = regulator_enable(priv-vcc);
 + if (ret) {
 + dev_err(pdev-dev, Failed to enable regulator\n);
 + return -ENODEV;
 + }
 + }
 +
 + priv-clk

Re: [PATCH 2/4] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

On 6 February 2015 at 02:24, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
 diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt
 b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
 new file mode 100644
 index 000..e926364
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
 @@ -0,0 +1,50 @@
 +Hisilicon hi6220  SoC USB controlle


Controller.
Yes, my mistake.
To prevent spelling error next time, will paste to google doc first
for the auto spelling check.


 +-
 +
 +usb controller is inherited from dwc2, refer dwc2.txt
 +-
 +
 +Required properties:
 +- compatible: hisilicon,hi6220-usb-phy


PHY? I thought you were describing the USB controller.
my bad
should be compatible: hisilicon,hi6220-usb


 +Refer to dwc2.txt for dwc2 usb properties
 +
 +
 +phy:
change to PHY:
 +-
 +
 +Required properties:
 +- compatible: hisilicon,hi6220-usb-phy
 +- vcc-supply: phandle to the regulator that provides power to the PHY.
 +- clocks: phandle to the PHY clock. Use as per Documentation/devicetree


Actually, it's phandle and clock specifier.
Change to
 - clocks: phandle and clock specifier of the PHY clock.


 +  /bindings/clock/clock-bindings.txt
 +- hisilicon,peripheral-syscon: phandle of syscon used to control
 peripheral.
 +- hisilicon,gpio_vbus_det: gpio of detecting vbus.
 +- hisilicon,gpio_id_det: gpio of detecting id.


Hyphens are preferred over underscores in the prop names.
Change to
- hisilicon,gpio-vbus-det: gpio of detecting vbus.
- hisilicon,gpio-id-det: gpio of detecting id.

Thanks Sergei
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[PATCH 3/4] usb: dwc2: platform: add hi6220 support

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/dwc2/platform.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index ae095f0..ceee385 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -50,6 +50,34 @@
 
 static const char dwc2_driver_name[] = dwc2;
 
+static const struct dwc2_core_params params_hi6220 = {
+   .otg_cap= 2,/* No HNP/SRP capable */
+   .otg_ver= 0,/* 1.3 */
+   .dma_enable = 1,
+   .dma_desc_enable= 0,
+   .speed  = 0,/* High Speed */
+   .enable_dynamic_fifo= 1,
+   .en_multiple_tx_fifo= 1,
+   .host_rx_fifo_size  = 512,
+   .host_nperio_tx_fifo_size   = 512,
+   .host_perio_tx_fifo_size= 512,
+   .max_transfer_size  = 65535,
+   .max_packet_count   = 511,
+   .host_channels  = 16,
+   .phy_type   = 1,/* UTMI */
+   .phy_utmi_width = 8,
+   .phy_ulpi_ddr   = 0,/* Single */
+   .phy_ulpi_ext_vbus  = 0,
+   .i2c_enable = 0,
+   .ulpi_fs_ls = 0,
+   .host_support_fs_ls_low_power   = 0,
+   .host_ls_low_power_phy_clk  = 0,/* 48 MHz */
+   .ts_dline   = 0,
+   .reload_ctl = 0,
+   .ahbcfg = 0x7  GAHBCFG_HBSTLEN_SHIFT, /* 
INCR16 */
+   .uframe_sched   = 0,
+};
+
 static const struct dwc2_core_params params_bcm2835 = {
.otg_cap= 0,/* HNP/SRP capable */
.otg_ver= 0,/* 1.3 */
@@ -129,6 +157,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = brcm,bcm2835-usb, .data = params_bcm2835 },
+   { .compatible = hisilicon,hi6220-usb, .data = params_hi6220 },
{ .compatible = rockchip,rk3066-usb, .data = params_rk3066 },
{ .compatible = snps,dwc2, .data = NULL },
{ .compatible = samsung,s3c6400-hsotg, .data = NULL},
-- 
1.9.1

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[PATCH 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

[Zhangfei Gao]

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index fd132cb..2213682 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
   - rockchip,rk3188-usb, rockchip,rk3066-usb, snps,dwc2: for rk3188 Soc;
   - rockchip,rk3288-usb, rockchip,rk3066-usb, snps,dwc2: for rk3288 Soc;
-- 
1.9.1

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[PATCH 2/4] Documentation: dt-bindings: add dt binding info for hi6220

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/usb/hi6220-usb.txt | 50 ++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt 
b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
new file mode 100644
index 000..e926364
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hi6220-usb.txt
@@ -0,0 +1,50 @@
+Hisilicon hi6220  SoC USB controlle
+-
+
+usb controller is inherited from dwc2, refer dwc2.txt
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+Refer to dwc2.txt for dwc2 usb properties
+
+
+phy:
+-
+
+Required properties:
+- compatible: hisilicon,hi6220-usb-phy
+- vcc-supply: phandle to the regulator that provides power to the PHY.
+- clocks: phandle to the PHY clock. Use as per Documentation/devicetree
+  /bindings/clock/clock-bindings.txt
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,gpio_vbus_det: gpio of detecting vbus.
+- hisilicon,gpio_id_det: gpio of detecting id.
+
+Example:
+
+   peripheral_ctrl: syscon@f703 {
+   compatible = syscon;
+   reg = 0x0 0xf703 0x0 0x1000;
+   };
+
+   usb2_phy: usbphy {
+   compatible = hisilicon,hi6220-usb-phy;
+   vcc-supply = fixed_5v_hub;
+   hisilicon,gpio_vbus_det = gpio2 6 0;
+   hisilicon,gpio_id_det = gpio2 5 0;
+   hisilicon,peripheral-syscon = peripheral_ctrl;
+   clocks = clock_sys HI6220_USBOTG_HCLK;
+   };
+
+   usb: usb@f72c {
+   compatible = hisilicon,hi6220-usb;
+   reg = 0x0 0xf72c 0x0 0x4;
+   phys = usb2_phy;
+   dr_mode = otg;
+   g-use-dma;
+   g-rx-fifo-size = 512;
+   g-np-tx-fifo-size = 128;
+   g-tx-fifo-size = 128;
+   interrupts = 0 77 0x4;
+   };
-- 
1.9.1

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[PATCH 4/4] usb: phy: add phy-hi6220

[Zhangfei Gao]

Add usb phy controller for hi6220 platform

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/usb/phy/Kconfig  |   9 ++
 drivers/usb/phy/Makefile |   1 +
 drivers/usb/phy/phy-hi6220.c | 290 +++
 3 files changed, 300 insertions(+)
 create mode 100644 drivers/usb/phy/phy-hi6220.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c6d0c8e..405a3d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -173,6 +173,15 @@ config USB_MXS_PHY
 
  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
+config USB_HI6220_PHY
+   tristate hi6220 USB PHY support
+   select USB_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI6220 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config USB_RCAR_PHY
tristate Renesas R-Car USB PHY support
depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 75f2bba..819283c 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SAMSUNG_USBPHY)  += phy-samsung-usb.o
 obj-$(CONFIG_TWL6030_USB)  += phy-twl6030-usb.o
 obj-$(CONFIG_USB_EHCI_TEGRA)   += phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
+obj-$(CONFIG_USB_HI6220_PHY)   += phy-hi6220.o
 obj-$(CONFIG_USB_ISP1301)  += phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)  += phy-msm-usb.o
 obj-$(CONFIG_USB_MV_OTG)   += phy-mv-usb.o
diff --git a/drivers/usb/phy/phy-hi6220.c b/drivers/usb/phy/phy-hi6220.c
new file mode 100644
index 000..87b1f0e
--- /dev/null
+++ b/drivers/usb/phy/phy-hi6220.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/regulator/consumer.h
+#include linux/usb/gadget.h
+#include linux/usb/otg.h
+
+#define SC_PERIPH_CTRL40x00c
+
+#define PERIPH_CTRL4_PICO_SIDDQBIT(6)
+#define PERIPH_CTRL4_PICO_OGDISABLEBIT(8)
+#define PERIPH_CTRL4_PICO_VBUSVLDEXT   BIT(10)
+#define PERIPH_CTRL4_PICO_VBUSVLDEXTSELBIT(11)
+#define PERIPH_CTRL4_OTG_PHY_SEL   BIT(21)
+
+#define SC_PERIPH_CTRL50x010
+
+#define PERIPH_CTRL5_USBOTG_RES_SELBIT(3)
+#define PERIPH_CTRL5_PICOPHY_ACAENBBIT(4)
+#define PERIPH_CTRL5_PICOPHY_BC_MODE   BIT(5)
+#define PERIPH_CTRL5_PICOPHY_CHRGSEL   BIT(6)
+#define PERIPH_CTRL5_PICOPHY_VDATSRCENDBIT(7)
+#define PERIPH_CTRL5_PICOPHY_VDATDETENBBIT(8)
+#define PERIPH_CTRL5_PICOPHY_DCDENBBIT(9)
+#define PERIPH_CTRL5_PICOPHY_IDDIG BIT(10)
+
+#define SC_PERIPH_CTRL80x018
+
+#define EYE_PATTERN_PARA   0x7053348c
+
+#define SC_PERIPH_RSTDIS0  0x304
+
+#define PERIPH_RSTDIS0_USBOTG_BUS  BIT(4)
+#define PERIPH_RSTDIS0_POR_PICOPHY BIT(5)
+#define PERIPH_RSTDIS0_USBOTG  BIT(6)
+#define PERIPH_RSTDIS0_USBOTG_32K  BIT(7)
+
+enum usb_mode {
+   USB_EMPTY,
+   GADGET_DEVICE,
+   OTG_HOST,
+};
+
+struct hi6220_priv {
+   struct usb_phy phy;
+   struct delayed_work work;
+   struct regmap *reg;
+   struct clk *clk;
+   struct regulator *vcc;
+   int gpio_vbus_det;
+   int gpio_id_det;
+   enum usb_mode mode;
+};
+
+static void hi6220_start_periphrals(struct hi6220_priv *priv, bool on)
+{
+   struct usb_otg *otg = priv-phy.otg;
+
+   if (!otg-gadget)
+   return;
+
+   if (on)
+   usb_gadget_connect(otg-gadget);
+   else
+   usb_gadget_disconnect(otg-gadget);
+}
+
+static void hi6220_detect_work(struct work_struct *work)
+{
+   struct hi6220_priv *priv =
+   container_of(work, struct hi6220_priv, work.work);
+   int id_det, vbus_det;
+   enum usb_mode mode;
+
+   if (!gpio_is_valid(priv-gpio_id_det) ||
+   !gpio_is_valid(priv-gpio_vbus_det))
+   return;
+
+   id_det = gpio_get_value_cansleep(priv-gpio_id_det);
+   vbus_det = gpio_get_value_cansleep(priv-gpio_vbus_det);
+
+   if (vbus_det == 0) {
+   if (id_det == 1)
+   mode = GADGET_DEVICE;
+   else
+   mode = OTG_HOST;
+   } else {
+   mode = USB_EMPTY;
+   }
+
+   if (mode == GADGET_DEVICE  priv-mode == USB_EMPTY)
+   hi6220_start_periphrals(priv, true);
+   if (mode == USB_EMPTY  priv-mode

[PATCH 0/4] add usb support for hi6220

[Zhangfei Gao]

hi6220 usb controller is inherited from dwc2
add phy accordingly
support otg gadget/host

Zhangfei Gao (4):
  Documentation: dt-bindings: add dt binding info for hi6220 dwc2
  Documentation: dt-bindings: add dt binding info for hi6220
  usb: dwc2: platform: add hi6220 support
  usb: phy: add phy-hi6220

 Documentation/devicetree/bindings/usb/dwc2.txt |   1 +
 .../devicetree/bindings/usb/hi6220-usb.txt |  50 
 drivers/usb/dwc2/platform.c|  29 +++
 drivers/usb/phy/Kconfig|   8 +
 drivers/usb/phy/Makefile   |   1 +
 drivers/usb/phy/phy-hi6220.c   | 290 +
 6 files changed, 379 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt
 create mode 100644 drivers/usb/phy/phy-hi6220.c

-- 
1.9.1

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[PATCH v4 01/10] ARM: dts: hix5hd2: add gmac node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2-dkb.dts |   28 
 arch/arm/boot/dts/hisi-x5hd2.dtsi|   16 
 2 files changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts 
b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 05b44c2..0da3f3b 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,3 +51,31 @@
 uart0 {
status = okay;
 };
+
+gmac0 {
+   #address-cells = 1;
+   #size-cells = 0;
+   phy-handle = phy2;
+   phy-mode = mii;
+   /* Placeholder, overwritten by bootloader */
+   mac-address = [00 00 00 00 00 00];
+   status = okay;
+
+   phy2: ethernet-phy@2 {
+   reg = 2;
+   };
+};
+
+gmac1 {
+   #address-cells = 1;
+   #size-cells = 0;
+   phy-handle = phy1;
+   phy-mode = rgmii;
+   /* Placeholder, overwritten by bootloader */
+   mac-address = [00 00 00 00 00 00];
+   status = okay;
+
+   phy1: ethernet-phy@1 {
+   reg = 1;
+   };
+};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index f85ba29..012525c 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -166,5 +166,21 @@
#clock-cells = 1;
};
};
+
+   gmac0: ethernet@184 {
+   compatible = hisilicon,hix5hd2-gmac;
+   reg = 0x184 0x1000,0x184300c 0x4;
+   interrupts = 0 71 4;
+   clocks = clock HIX5HD2_MAC0_CLK;
+   status = disabled;
+   };
+
+   gmac1: ethernet@1841000 {
+   compatible = hisilicon,hix5hd2-gmac;
+   reg = 0x1841000 0x1000,0x1843010 0x4;
+   interrupts = 0 72 4;
+   clocks = clock HIX5HD2_MAC1_CLK;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v4 07/10] ARM: dts: hix5hd2: add ir node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d07589b..576d8c2 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -391,7 +391,7 @@
};
 
sysctrl: system-controller@ {
-   compatible = hisilicon,sysctrl;
+   compatible = hisilicon,sysctrl, syscon;
reg = 0x 0x1000;
reboot-offset = 0x4;
};
@@ -478,5 +478,13 @@
interrupts = 0 70 4;
clocks = clock HIX5HD2_SATA_CLK;
};
+
+   ir: ir@001000 {
+   compatible = hisilicon,hix5hd2-ir;
+   reg = 0x001000 0x1000;
+   interrupts = 0 47 4;
+   clocks = clock HIX5HD2_FIXED_24M;
+   hisilicon,power-syscon = sysctrl;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v4 05/10] ARM: dts: hix5hd2: add gpio node

[Zhangfei Gao]

Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |  234 +
 1 file changed, 234 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d5b3a8f..7f1a3e0 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,6 +131,240 @@
clock-names = apb_pclk;
status = disabled;
};
+
+   gpio0: gpio@b2 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb2 0x1000;
+   interrupts = 0 108 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio1: gpio@b21000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb21000 0x1000;
+   interrupts = 0 109 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio2: gpio@b22000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb22000 0x1000;
+   interrupts = 0 110 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio3: gpio@b23000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb23000 0x1000;
+   interrupts = 0 111 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio4: gpio@b24000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb24000 0x1000;
+   interrupts = 0 112 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio5: gpio@004000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0x004000 0x1000;
+   interrupts = 0 113 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled;
+   };
+
+   gpio6: gpio@b26000 {
+   compatible = arm,pl061, arm,primecell;
+   reg = 0xb26000 0x1000;
+   interrupts = 0 114 0x4;
+   gpio-controller;
+   #gpio-cells = 2;
+   clocks = clock HIX5HD2_FIXED_100M;
+   clock-names = apb_pclk;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   status = disabled

[PATCH v4 00/10] hix5hd2 add some nodes

[Zhangfei Gao]

v4:
Rebase on 3.18-rc1
Update hisi_defconfig, adding some drivers for hix5hd2
Reuse syscon-reboot for reboot, drivers/power/reset/syscon-reboot.c

Test hisi_defconfig on hix5hd2, d01 and k3v2

v3: 
Change node wdt for a watchdog timer as comment from Dinh

v2:
Add comments of mac-address, suggested by Mark

Zhangfei Gao (10):
  ARM: dts: hix5hd2: add gmac node
  ARM: dts: hix5hd2: add mmc node
  ARM: dts: hix5hd2: add usb node
  ARM: dts: hix5hd2: add sata node
  ARM: dts: hix5hd2: add gpio node
  ARM: dts: hix5hd2: add wdg node
  ARM: dts: hix5hd2: add ir node
  ARM: dts: hix5hd2: add i2c node
  ARM: dts: hix5hd2: add reboot node
  ARM: hisi_defconfig: add driver support for hix5hd2

 arch/arm/boot/dts/hisi-x5hd2-dkb.dts |   33 +++
 arch/arm/boot/dts/hisi-x5hd2.dtsi|  390 +-
 arch/arm/configs/hisi_defconfig  |   19 ++
 3 files changed, 440 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v4 08/10] ARM: dts: hix5hd2: add i2c node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 576d8c2..b8deb6c 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -486,5 +486,65 @@
clocks = clock HIX5HD2_FIXED_24M;
hisilicon,power-syscon = sysctrl;
};
+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c1: i2c@b11000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb11000 0x1000;
+   interrupts = 0 39 4;
+   clocks = clock HIX5HD2_I2C1_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c2: i2c@b12000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb12000 0x1000;
+   interrupts = 0 40 4;
+   clocks = clock HIX5HD2_I2C2_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c3: i2c@b13000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb13000 0x1000;
+   interrupts = 0 41 4;
+   clocks = clock HIX5HD2_I2C3_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c4: i2c@b16000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb16000 0x1000;
+   interrupts = 0 43 4;
+   clocks = clock HIX5HD2_I2C4_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c5: i2c@b17000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb17000 0x1000;
+   interrupts = 0 44 4;
+   clocks = clock HIX5HD2_I2C5_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v4 03/10] ARM: dts: hix5hd2: add usb node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index fea5d5c..4f9e8a3 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -201,5 +201,19 @@
clocks = clock HIX5HD2_MAC1_CLK;
status = disabled;
};
+
+   usb0: ehci@189 {
+   compatible = generic-ehci;
+   reg = 0x189 0x1000;
+   interrupts = 0 66 4;
+   clocks = clock HIX5HD2_USB_CLK;
+   };
+
+   usb1: ohci@188 {
+   compatible = generic-ohci;
+   reg = 0x188 0x1000;
+   interrupts = 0 67 4;
+   clocks = clock HIX5HD2_USB_CLK;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v4 04/10] ARM: dts: hix5hd2: add sata node

[Zhangfei Gao]

Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2-dkb.dts |5 +
 arch/arm/boot/dts/hisi-x5hd2.dtsi|   20 
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts 
b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 0da3f3b..721b092 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -79,3 +79,8 @@
reg = 1;
};
 };
+
+ahci {
+   phys = sata_phy;
+   phy-names = sata-phy;
+};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 4f9e8a3..d5b3a8f 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -215,5 +215,25 @@
interrupts = 0 67 4;
clocks = clock HIX5HD2_USB_CLK;
};
+
+   peripheral_ctrl: syscon@a2 {
+   compatible = syscon;
+   reg = 0xa2 0x1000;
+   };
+
+   sata_phy: phy@190 {
+   compatible = hisilicon,hix5hd2-sata-phy;
+   reg = 0x190 0x1;
+   #phy-cells = 0;
+   hisilicon,peripheral-syscon = peripheral_ctrl;
+   hisilicon,power-reg = 0x8 10;
+   };
+
+   ahci: sata@190 {
+   compatible = hisilicon,hisi-ahci;
+   reg = 0x190 0x1;
+   interrupts = 0 70 4;
+   clocks = clock HIX5HD2_SATA_CLK;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v4 02/10] ARM: dts: hix5hd2: add mmc node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 012525c..fea5d5c 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -167,6 +167,25 @@
};
};
 
+   /* unremovable emmc as mmcblk0 */
+   mmc: mmc@183 {
+   compatible = snps,dw-mshc;
+   reg = 0x183 0x1000;
+   interrupts = 0 35 4;
+   clocks = clock HIX5HD2_MMC_CIU_RST,
+clock HIX5HD2_MMC_BIU_CLK;
+   clock-names = ciu, biu;
+   };
+
+   sd: mmc@182 {
+   compatible = snps,dw-mshc;
+   reg = 0x182 0x1000;
+   interrupts = 0 34 4;
+   clocks = clock HIX5HD2_SD_CIU_RST,
+clock HIX5HD2_SD_BIU_CLK;
+   clock-names = ciu,biu;
+   };
+
gmac0: ethernet@184 {
compatible = hisilicon,hix5hd2-gmac;
reg = 0x184 0x1000,0x184300c 0x4;
-- 
1.7.9.5

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[PATCH v4 06/10] ARM: dts: hix5hd2: add wdg node

[Zhangfei Gao]

Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 7f1a3e0..d07589b 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -365,6 +365,15 @@
#interrupt-cells = 2;
status = disabled;
};
+
+   wdt0: watchdog@a2c000 {
+   compatible = arm,sp805, arm,primecell;
+   arm,primecell-periphid = 0x00141805;
+   reg = 0xa2c000 0x1000;
+   interrupts = 0 29 4;
+   clocks = clock HIX5HD2_WDG0_RST;
+   clock-names = apb_pclk;
+   };
};
 
local_timer@00a00600 {
-- 
1.7.9.5

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[PATCH v4 10/10] ARM: hisi_defconfig: add driver support for hix5hd2

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/configs/hisi_defconfig |   19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 1772505..1fe3621f 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -5,6 +5,8 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_RD_LZMA=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_HIP04=y
 CONFIG_SMP=y
@@ -14,8 +16,11 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_NEON=y
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
@@ -26,6 +31,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -39,8 +45,13 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_PINCTRL_SINGLE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIOLIB=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MFD_SYSCON=y
+CONFIG_POWER_RESET_SYSCON=y
 CONFIG_DRM=y
 CONFIG_FB_SIMPLE=y
 CONFIG_USB=y
@@ -48,15 +59,21 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_IDMAC=y
+CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_PL330_DMA=y
 CONFIG_PWM=y
+CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_EXT4_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
@@ -65,6 +82,8 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_VFP=y
-- 
1.7.9.5

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[PATCH v4 09/10] ARM: dts: hix5hd2: add reboot node

[Zhangfei Gao]

Reuse syscon-reboot, drivers/power/reset/syscon-reboot.c

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index b8deb6c..c52722b 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -393,7 +393,13 @@
sysctrl: system-controller@ {
compatible = hisilicon,sysctrl, syscon;
reg = 0x 0x1000;
-   reboot-offset = 0x4;
+   };
+
+   reboot {
+   compatible = syscon-reboot;
+   regmap = sysctrl;
+   offset = 0x4;
+   mask = 0xdeadbeef;
};
 
cpuctrl@00a22000 {
-- 
1.7.9.5

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Re: [PATCH v5 3/3] ARM: dts: hix5hd2: add i2c node

[zhangfei]

On 10/08/2014 01:14 AM, Wolfram Sang wrote:

On Tue, Oct 07, 2014 at 09:04:13AM +0800, Zhangfei Gao wrote:

Signed-off-by: Zhangfei Gao zhangfei@linaro.org


This one should go via arm-soc.



Thanks Wolfram for the help.
Will send the dts serious after rc1 come out with clock define.

Thanks
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Re: [PATCH v4 2/3] i2c: hix5hd2: add i2c controller driver

[zhangfei]

On 10/07/2014 01:56 AM, Wolfram Sang wrote:

On Fri, Oct 03, 2014 at 11:35:48PM +0800, Zhangfei Gao wrote:

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org


Sorry, one more thing, then we are ready to go:


+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.


Here you say GPL v2 or later...


+MODULE_LICENSE(GPL v2);


... here GPL v2 only. That should be consistent!


Thanks for the notifying this, not notice before.
Should change to MODULE_LICENSE(GPL).

include/linux/module.h

/*
 * The following license idents are currently accepted as indicating free
 * software modules
 *
 *  GPL   [GNU Public License v2 or later]
 *  GPL v2[GNU Public License v2]
 *  GPL and additional rights [GNU Public License v2 rights 
and more]

 *  Dual BSD/GPL  [GNU Public License v2
 *   or BSD license choice]
 *  Dual MIT/GPL  [GNU Public License v2
 *   or MIT license choice]
 *  Dual MPL/GPL  [GNU Public License v2
 *   or Mozilla license choice]
 *

Thanks
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[PATCH v5 0/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

v5:
Mentioned by Wolfram
To make license consistent, using GPL [GNU Public License v2 or later] 

v4:
Suggested by Wolfram
Put runtime pm calls before i2c_add_adapter, in case i2c operation during probe.

Also remove COMPILE_TEST, since compile test fail with linux-next next-20141003
Will add back later when readl/writel_relaxed is defined.

v3:
Add COMPILE_TEST as dependence to enable compile test
Remove specific mach info in dts binding to solve the confusion.

v2: 
Modify according to Wolfram's comments 
including change vector name, coding style, return value etc.

Wei Yan (2):
  i2c: hix5hd2: add devicetree documentation
  i2c: hix5hd2: add i2c controller driver

Zhangfei Gao (1):
  ARM: dts: hix5hd2: add i2c node

 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   24 +
 arch/arm/boot/dts/hisi-x5hd2.dtsi  |   60 +++
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-hix5hd2.c   |  557 
 5 files changed, 652 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

-- 
1.7.9.5

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[PATCH v5 1/3] i2c: hix5hd2: add devicetree documentation

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   24 
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt 
b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 000..f98b374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,24 @@
+I2C for Hisilicon hix5hd2 chipset platform
+
+Required properties:
+- compatible: Must be hisilicon,hix5hd2-i2c
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = 1;
+- #size-cells = 0;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 
10
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0@f8b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xf8b1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+}
-- 
1.7.9.5

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[PATCH v5 3/3] ARM: dts: hix5hd2: add i2c node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d3d99fb..17d0637 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -476,5 +476,65 @@
 interrupts = 0 70 4;
 clocks = clock HIX5HD2_SATA_CLK;
};
+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c1: i2c@b11000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb11000 0x1000;
+   interrupts = 0 39 4;
+   clocks = clock HIX5HD2_I2C1_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c2: i2c@b12000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb12000 0x1000;
+   interrupts = 0 40 4;
+   clocks = clock HIX5HD2_I2C2_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c3: i2c@b13000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb13000 0x1000;
+   interrupts = 0 41 4;
+   clocks = clock HIX5HD2_I2C3_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c4: i2c@b16000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb16000 0x1000;
+   interrupts = 0 43 4;
+   clocks = clock HIX5HD2_I2C4_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c5: i2c@b17000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb17000 0x1000;
+   interrupts = 0 44 4;
+   clocks = clock HIX5HD2_I2C5_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v5 2/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/i2c/busses/Kconfig   |   10 +
 drivers/i2c/busses/Makefile  |1 +
 drivers/i2c/busses/i2c-hix5hd2.c |  557 ++
 3 files changed, 568 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..ba0f43c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
  This driver can also be built as a module.  If so, the module
  will be called i2c-amd8111.
 
+config I2C_HIX5HD2
+   tristate Hix5hd2 high-speed I2C driver
+   depends on ARCH_HIX5HD2
+   help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs.
+
+ This driver can also be built as a module.  If so, the module
+ will be called i2c-hix5hd2.
+
 config I2C_I801
tristate Intel 82801 (ICH/PCH)
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T)   += i2c-eg20t.o
 obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2)  += i2c-hix5hd2.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 000..9490d0f
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/i2c.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+
+/* Register Map */
+#define HIX5I2C_CTRL   0x00
+#define HIX5I2C_COM0x04
+#define HIX5I2C_ICR0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H  0x10
+#define HIX5I2C_SCL_L  0x14
+#define HIX5I2C_TXR0x18
+#define HIX5I2C_RXR0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL   BIT(7)
+#define I2C_UNMASK_START   BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SENDBIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE   BIT(1)
+#define I2C_UNMASK_OVERBIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START  BIT(3)
+#define I2C_READ   BIT(2)
+#define I2C_WRITE  BIT(1)
+#define I2C_STOP   BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_STARTBIT(6)
+#define I2C_CLEAR_END  BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE  BIT(3)
+#define I2C_CLEAR_ACK  BIT(2)
+#define I2C_CLEAR_ARBITRATEBIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL  (I2C_CLEAR_START | I2C_CLEAR_END | \
+   I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+   I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+   I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY   BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR   BIT(5)
+#define I2C_SEND_INTR  BIT(4)
+#define I2C_RECEIVE_INTR   BIT(3)
+#define I2C_ACK_INTR   BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR  BIT(0)
+
+#define HIX5I2C_MAX_FREQ   40  /* 400k */
+#define HIX5I2C_READ_OPERATION 0x01
+
+enum hix5hd2_i2c_state {
+   HIX5I2C_STAT_RW_ERR = -1,
+   HIX5I2C_STAT_INIT,
+   HIX5I2C_STAT_RW,
+   HIX5I2C_STAT_SND_STOP,
+   HIX5I2C_STAT_RW_SUCCESS,
+};
+
+struct hix5hd2_i2c_priv {
+   struct i2c_adapter adap;
+   struct i2c_msg *msg;
+   struct completion msg_complete;
+   unsigned int msg_idx;
+   unsigned

Re: [PATCH v3 2/3] i2c: hix5hd2: add i2c controller driver

[zhangfei]

On 10/03/2014 08:09 PM, Wolfram Sang wrote:

Hi,

On Tue, Sep 30, 2014 at 08:20:27PM +0800, Zhangfei Gao wrote:

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org


Looks good to me. You probably want to have a look at this patch
http://patchwork.ozlabs.org/patch/394648/

an do something similar here, I guess.

BTW what tests have you performed?



Thanks Wolfram for the info, will update accordingly.

Currently Wei help do the test via I2C device interface, on a specific 
board with i2c device.

We do the test after the board is up, also no i2c activity during probe.

Thanks
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[PATCH v4 0/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

v4:
Suggested by Wolfram
Put runtime pm calls before i2c_add_adapter, in case i2c operation during probe.

Also remove COMPILE_TEST, since compile test fail with linux-next next-20141003
Will add back later when readl/writel_relaxed is defined.

v3:
Add COMPILE_TEST as dependence to enable compile test
Remove specific mach info in dts binding to solve the confusion.

v2: 
Modify according to Wolfram's comments 
including change vector name, coding style, return value etc.

Wei Yan (2):
  i2c: hix5hd2: add devicetree documentation
  i2c: hix5hd2: add i2c controller driver

Zhangfei Gao (1):
  ARM: dts: hix5hd2: add i2c node

 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   25 +
 arch/arm/boot/dts/hisi-x5hd2.dtsi  |   60 +++
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-hix5hd2.c   |  557 
 5 files changed, 653 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

-- 
1.7.9.5

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[PATCH v4 1/3] i2c: hix5hd2: add devicetree documentation

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   25 
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt 
b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 000..660b7ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,25 @@
+I2C for Hisilicon hix5hd2 chipset platform
+
+Required properties:
+- compatible: Must be hisilicon,hix5hd2-i2c
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = 1;
+- #size-cells = 0;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 
10
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0@f8b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xf8b1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+}
-- 
1.7.9.5

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[PATCH v4 2/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/i2c/busses/Kconfig   |   10 +
 drivers/i2c/busses/Makefile  |1 +
 drivers/i2c/busses/i2c-hix5hd2.c |  557 ++
 3 files changed, 568 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..ba0f43c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
  This driver can also be built as a module.  If so, the module
  will be called i2c-amd8111.
 
+config I2C_HIX5HD2
+   tristate Hix5hd2 high-speed I2C driver
+   depends on ARCH_HIX5HD2
+   help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs.
+
+ This driver can also be built as a module.  If so, the module
+ will be called i2c-hix5hd2.
+
 config I2C_I801
tristate Intel 82801 (ICH/PCH)
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T)   += i2c-eg20t.o
 obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2)  += i2c-hix5hd2.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 000..650b371
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/i2c.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+
+/* Register Map */
+#define HIX5I2C_CTRL   0x00
+#define HIX5I2C_COM0x04
+#define HIX5I2C_ICR0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H  0x10
+#define HIX5I2C_SCL_L  0x14
+#define HIX5I2C_TXR0x18
+#define HIX5I2C_RXR0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL   BIT(7)
+#define I2C_UNMASK_START   BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SENDBIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE   BIT(1)
+#define I2C_UNMASK_OVERBIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START  BIT(3)
+#define I2C_READ   BIT(2)
+#define I2C_WRITE  BIT(1)
+#define I2C_STOP   BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_STARTBIT(6)
+#define I2C_CLEAR_END  BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE  BIT(3)
+#define I2C_CLEAR_ACK  BIT(2)
+#define I2C_CLEAR_ARBITRATEBIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL  (I2C_CLEAR_START | I2C_CLEAR_END | \
+   I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+   I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+   I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY   BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR   BIT(5)
+#define I2C_SEND_INTR  BIT(4)
+#define I2C_RECEIVE_INTR   BIT(3)
+#define I2C_ACK_INTR   BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR  BIT(0)
+
+#define HIX5I2C_MAX_FREQ   40  /* 400k */
+#define HIX5I2C_READ_OPERATION 0x01
+
+enum hix5hd2_i2c_state {
+   HIX5I2C_STAT_RW_ERR = -1,
+   HIX5I2C_STAT_INIT,
+   HIX5I2C_STAT_RW,
+   HIX5I2C_STAT_SND_STOP,
+   HIX5I2C_STAT_RW_SUCCESS,
+};
+
+struct hix5hd2_i2c_priv {
+   struct i2c_adapter adap;
+   struct i2c_msg *msg;
+   struct completion msg_complete;
+   unsigned int msg_idx;
+   unsigned

[PATCH v4 3/3] ARM: dts: hix5hd2: add i2c node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d3d99fb..17d0637 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -476,5 +476,65 @@
 interrupts = 0 70 4;
 clocks = clock HIX5HD2_SATA_CLK;
};
+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c1: i2c@b11000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb11000 0x1000;
+   interrupts = 0 39 4;
+   clocks = clock HIX5HD2_I2C1_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c2: i2c@b12000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb12000 0x1000;
+   interrupts = 0 40 4;
+   clocks = clock HIX5HD2_I2C2_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c3: i2c@b13000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb13000 0x1000;
+   interrupts = 0 41 4;
+   clocks = clock HIX5HD2_I2C3_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c4: i2c@b16000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb16000 0x1000;
+   interrupts = 0 43 4;
+   clocks = clock HIX5HD2_I2C4_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c5: i2c@b17000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb17000 0x1000;
+   interrupts = 0 44 4;
+   clocks = clock HIX5HD2_I2C5_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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Re: [PATCH v3 2/3] i2c: hix5hd2: add i2c controller driver

[zhangfei]

On 10/04/2014 12:48 AM, Wolfram Sang wrote:

Currently Wei help do the test via I2C device interface, on a specific board
with i2c device.
We do the test after the board is up, also no i2c activity during probe.


Huh, so the driver has not been tested with a real i2c slave so far? Or
am I misunderstanding something?


Sorry for the confusion

It is tested via e2prom,
Write group of data then read back to check whether they are same or not.
We use I2C device interface, and only run the test application when 
board is up.


Thanks


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Re: [PATCH v2 3/3] ARM: dts: hix5hd2: add i2c node

[zhangfei]

On 09/30/2014 05:02 PM, Arnd Bergmann wrote:

On Sunday 28 September 2014 12:22:09 Zhangfei Gao wrote:

+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };



HIX5HD2_I2C0_RST is not defined anywhere, so this will result in the
same build error that has required reverting a lot of patches for the
3.18 merge window.

How do you plan to deal with the dependency in the future?



HIX5HD2_I2C0_RST in clock patch and already been merged through clock 
tree in 09/29, should be in 3.18-rc1 (not sure).

When clock patch are combined in the same rc, will send the dts patch.
Sorry for the build issue.

Thanks
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Re: [PATCH v2 1/3] i2c: hix5hd2: add devicetree documentation

[zhangfei]

On 09/30/2014 05:01 PM, Arnd Bergmann wrote:

On Sunday 28 September 2014 12:22:07 Zhangfei Gao wrote:

+
+Required properties:
+- compatible: Must be hisilicon,hix5hd2-i2c
+  Specifically, the following versions of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)



How do you detect the specific model? Is there a hardware register that
lets you know the type?
If you have a device specific compatible string, you should list all
the known strings.

In fact, no need to distinguish these hardware, the only difference is 
i2c module number.

The same compatible is used.
These info can be removed to remove the confusion.

Thanks
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[PATCH v3 3/3] ARM: dts: hix5hd2: add i2c node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d3d99fb..17d0637 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -476,5 +476,65 @@
 interrupts = 0 70 4;
 clocks = clock HIX5HD2_SATA_CLK;
};
+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c1: i2c@b11000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb11000 0x1000;
+   interrupts = 0 39 4;
+   clocks = clock HIX5HD2_I2C1_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c2: i2c@b12000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb12000 0x1000;
+   interrupts = 0 40 4;
+   clocks = clock HIX5HD2_I2C2_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c3: i2c@b13000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb13000 0x1000;
+   interrupts = 0 41 4;
+   clocks = clock HIX5HD2_I2C3_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c4: i2c@b16000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb16000 0x1000;
+   interrupts = 0 43 4;
+   clocks = clock HIX5HD2_I2C4_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c5: i2c@b17000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb17000 0x1000;
+   interrupts = 0 44 4;
+   clocks = clock HIX5HD2_I2C5_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v3 2/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/i2c/busses/Kconfig   |   10 +
 drivers/i2c/busses/Makefile  |1 +
 drivers/i2c/busses/i2c-hix5hd2.c |  554 ++
 3 files changed, 565 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..2ef671f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
  This driver can also be built as a module.  If so, the module
  will be called i2c-amd8111.
 
+config I2C_HIX5HD2
+   tristate Hix5hd2 high-speed I2C driver
+   depends on ARCH_HIX5HD2 || COMPILE_TEST
+   help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs.
+
+ This driver can also be built as a module.  If so, the module
+ will be called i2c-hix5hd2.
+
 config I2C_I801
tristate Intel 82801 (ICH/PCH)
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T)   += i2c-eg20t.o
 obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2)  += i2c-hix5hd2.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 000..4b18bde
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/i2c.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+
+/* Register Map */
+#define HIX5I2C_CTRL   0x00
+#define HIX5I2C_COM0x04
+#define HIX5I2C_ICR0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H  0x10
+#define HIX5I2C_SCL_L  0x14
+#define HIX5I2C_TXR0x18
+#define HIX5I2C_RXR0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL   BIT(7)
+#define I2C_UNMASK_START   BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SENDBIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE   BIT(1)
+#define I2C_UNMASK_OVERBIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START  BIT(3)
+#define I2C_READ   BIT(2)
+#define I2C_WRITE  BIT(1)
+#define I2C_STOP   BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_STARTBIT(6)
+#define I2C_CLEAR_END  BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE  BIT(3)
+#define I2C_CLEAR_ACK  BIT(2)
+#define I2C_CLEAR_ARBITRATEBIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL  (I2C_CLEAR_START | I2C_CLEAR_END | \
+   I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+   I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+   I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY   BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR   BIT(5)
+#define I2C_SEND_INTR  BIT(4)
+#define I2C_RECEIVE_INTR   BIT(3)
+#define I2C_ACK_INTR   BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR  BIT(0)
+
+#define HIX5I2C_MAX_FREQ   40  /* 400k */
+#define HIX5I2C_READ_OPERATION 0x01
+
+enum hix5hd2_i2c_state {
+   HIX5I2C_STAT_RW_ERR = -1,
+   HIX5I2C_STAT_INIT,
+   HIX5I2C_STAT_RW,
+   HIX5I2C_STAT_SND_STOP,
+   HIX5I2C_STAT_RW_SUCCESS,
+};
+
+struct hix5hd2_i2c_priv {
+   struct i2c_adapter adap;
+   struct i2c_msg *msg;
+   struct completion msg_complete;
+   unsigned int msg_idx

[PATCH v3 0/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

v3:
Add COMPILE_TEST as dependence to enable compile test
Remove specific mach info in dts binding to solve the confusion.

v2: 
Modify according to Wolfram's comments 
including change vector name, coding style, return value etc.

Wei Yan (2):
  i2c: hix5hd2: add devicetree documentation
  i2c: hix5hd2: add i2c controller driver

Zhangfei Gao (1):
  ARM: dts: hix5hd2: add i2c node

 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   25 +
 arch/arm/boot/dts/hisi-x5hd2.dtsi  |   60 +++
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-hix5hd2.c   |  554 
 5 files changed, 650 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

-- 
1.7.9.5

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Re: [PATCH v2 2/3] i2c: hix5hd2: add i2c controller driver

[zhangfei]

On 09/28/2014 12:22 PM, Zhangfei Gao wrote:

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  drivers/i2c/busses/Kconfig   |   10 +
  drivers/i2c/busses/Makefile  |1 +
  drivers/i2c/busses/i2c-hix5hd2.c |  554 ++
  3 files changed, 565 insertions(+)
  create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..ba0f43c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
  This driver can also be built as a module.  If so, the module
  will be called i2c-amd8111.

+config I2C_HIX5HD2
+   tristate Hix5hd2 high-speed I2C driver
+   depends on ARCH_HIX5HD2


Would like to remove the dependence in next version to enable compile-test.
The commit 4c255791ffd6410f (asm-generic: io: implement relaxed 
accessor macros as conditional wrappers) adds wrappers to asm-generic 
of {read,write}{b,w,l,q}_relaxed.


Thanks
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[PATCH v2 1/3] i2c: hix5hd2: add devicetree documentation

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   31 
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt

diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt 
b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 000..981a069
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,31 @@
+I2C for Hisilicon hix5hd2 chipset platforms (3716,3719,3798...)
+
+Required properties:
+- compatible: Must be hisilicon,hix5hd2-i2c
+  Specifically, the following versions of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = 1;
+- #size-cells = 0;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 
10
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0@f8b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xf8b1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+}
-- 
1.7.9.5

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[PATCH v2 0/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

v2: 
Modify according to Wolfram's comments 
including change vector name, coding style, return value etc.

Wei Yan (2):
  i2c: hix5hd2: add devicetree documentation
  i2c: hix5hd2: add i2c controller driver

Zhangfei Gao (1):
  ARM: dts: hix5hd2: add i2c node

 .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   31 ++
 arch/arm/boot/dts/hisi-x5hd2.dtsi  |   60 +++
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-hix5hd2.c   |  555 
 5 files changed, 657 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

-- 
1.7.9.5

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[PATCH v2 3/3] ARM: dts: hix5hd2: add i2c node

[Zhangfei Gao]

Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi 
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d3d99fb..17d0637 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -476,5 +476,65 @@
 interrupts = 0 70 4;
 clocks = clock HIX5HD2_SATA_CLK;
};
+
+   i2c0: i2c@b1 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb1 0x1000;
+   interrupts = 0 38 4;
+   clocks = clock HIX5HD2_I2C0_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c1: i2c@b11000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb11000 0x1000;
+   interrupts = 0 39 4;
+   clocks = clock HIX5HD2_I2C1_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c2: i2c@b12000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb12000 0x1000;
+   interrupts = 0 40 4;
+   clocks = clock HIX5HD2_I2C2_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c3: i2c@b13000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb13000 0x1000;
+   interrupts = 0 41 4;
+   clocks = clock HIX5HD2_I2C3_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c4: i2c@b16000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb16000 0x1000;
+   interrupts = 0 43 4;
+   clocks = clock HIX5HD2_I2C4_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
+
+   i2c5: i2c@b17000 {
+   compatible = hisilicon,hix5hd2-i2c;
+   reg = 0xb17000 0x1000;
+   interrupts = 0 44 4;
+   clocks = clock HIX5HD2_I2C5_RST;
+   #address-cells = 1;
+   #size-cells = 0;
+   status = disabled;
+   };
};
 };
-- 
1.7.9.5

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[PATCH v2 2/3] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/i2c/busses/Kconfig   |   10 +
 drivers/i2c/busses/Makefile  |1 +
 drivers/i2c/busses/i2c-hix5hd2.c |  554 ++
 3 files changed, 565 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..ba0f43c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
  This driver can also be built as a module.  If so, the module
  will be called i2c-amd8111.
 
+config I2C_HIX5HD2
+   tristate Hix5hd2 high-speed I2C driver
+   depends on ARCH_HIX5HD2
+   help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs.
+
+ This driver can also be built as a module.  If so, the module
+ will be called i2c-hix5hd2.
+
 config I2C_I801
tristate Intel 82801 (ICH/PCH)
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T)   += i2c-eg20t.o
 obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2)  += i2c-hix5hd2.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)  += i2c-imx.o
 obj-$(CONFIG_I2C_IOP3XX)   += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 000..4b18bde
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/i2c.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+
+/* Register Map */
+#define HIX5I2C_CTRL   0x00
+#define HIX5I2C_COM0x04
+#define HIX5I2C_ICR0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H  0x10
+#define HIX5I2C_SCL_L  0x14
+#define HIX5I2C_TXR0x18
+#define HIX5I2C_RXR0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL   BIT(7)
+#define I2C_UNMASK_START   BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SENDBIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE   BIT(1)
+#define I2C_UNMASK_OVERBIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START  BIT(3)
+#define I2C_READ   BIT(2)
+#define I2C_WRITE  BIT(1)
+#define I2C_STOP   BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_STARTBIT(6)
+#define I2C_CLEAR_END  BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE  BIT(3)
+#define I2C_CLEAR_ACK  BIT(2)
+#define I2C_CLEAR_ARBITRATEBIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL  (I2C_CLEAR_START | I2C_CLEAR_END | \
+   I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+   I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+   I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY   BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR   BIT(5)
+#define I2C_SEND_INTR  BIT(4)
+#define I2C_RECEIVE_INTR   BIT(3)
+#define I2C_ACK_INTR   BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR  BIT(0)
+
+#define HIX5I2C_MAX_FREQ   40  /* 400k */
+#define HIX5I2C_READ_OPERATION 0x01
+
+enum hix5hd2_i2c_state {
+   HIX5I2C_STAT_RW_ERR = -1,
+   HIX5I2C_STAT_INIT,
+   HIX5I2C_STAT_RW,
+   HIX5I2C_STAT_SND_STOP,
+   HIX5I2C_STAT_RW_SUCCESS,
+};
+
+struct hix5hd2_i2c_priv {
+   struct i2c_adapter adap;
+   struct i2c_msg *msg;
+   struct completion msg_complete;
+   unsigned int msg_idx;
+   unsigned

[PATCH v5 0/4] clk: hix5hd2: clocks update

[Zhangfei Gao]

v5:
0001:
Suggested by Mike, change to clk_ether_prepare since delay required inside

v4:
Drop ir clock, whose register is not in the same region

v3: 
Add patches 3, 4, 5 for clocks of watchdog, ir, and i2c
Patches 1, 2 are same as v2

Guoxiong Yan (1):
  clk: hix5hd2: add watchdog0 clocks

Jiancheng Xue (1):
  clk: hix5hd2: add sd clk

Wei Yan (1):
  clk: hix5hd2: add I2C clocks

Zhangfei Gao (1):
  clk: hix5hd2: add complex clk

 drivers/clk/hisilicon/clk-hix5hd2.c   |  236 -
 include/dt-bindings/clock/hix5hd2-clock.h |   27 
 2 files changed, 257 insertions(+), 6 deletions(-)

-- 
1.7.9.5

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[PATCH v5 2/4] clk: hix5hd2: add sd clk

[Zhangfei Gao]

From: Jiancheng Xue xuejianch...@huawei.com

Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/clk/hisilicon/clk-hix5hd2.c   |   21 +++--
 include/dt-bindings/clock/hix5hd2-clock.h |4 
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c 
b/drivers/clk/hisilicon/clk-hix5hd2.c
index da9ca05..13d6ec2 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -50,9 +50,9 @@ static const char *sfc_mux_p[] __initconst = {
24m, 150m, 200m, 100m, 75m, };
 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
 
-static const char *sdio1_mux_p[] __initconst = {
+static const char *sdio_mux_p[] __initconst = {
75m, 100m, 50m, 15m, };
-static u32 sdio1_mux_table[] = {0, 1, 2, 3};
+static u32 sdio_mux_table[] = {0, 1, 2, 3};
 
 static const char *fephy_mux_p[] __initconst = { 25m, 125m};
 static u32 fephy_mux_table[] = {0, 1};
@@ -61,20 +61,29 @@ static u32 fephy_mux_table[] = {0, 1};
 static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
{ HIX5HD2_SFC_MUX, sfc_mux, sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
-   { HIX5HD2_MMC_MUX, mmc_mux, sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p),
-   CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio1_mux_table, },
+   { HIX5HD2_MMC_MUX, mmc_mux, sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
+   CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
+   { HIX5HD2_SD_MUX, sd_mux, sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
+   CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
{ HIX5HD2_FEPHY_MUX, fephy_mux,
fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
 };
 
 static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
-   /*sfc*/
+   /* sfc */
{ HIX5HD2_SFC_CLK, clk_sfc, sfc_mux,
CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
{ HIX5HD2_SFC_RST, rst_sfc, clk_sfc,
CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
-   /*sdio1*/
+   /* sdio0 */
+   { HIX5HD2_SD_BIU_CLK, clk_sd_biu, 200m,
+   CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
+   { HIX5HD2_SD_CIU_CLK, clk_sd_ciu, sd_mux,
+   CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
+   { HIX5HD2_SD_CIU_RST, rst_sd_ciu, clk_sd_ciu,
+   CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
+   /* sdio1 */
{ HIX5HD2_MMC_BIU_CLK, clk_mmc_biu, 200m,
CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
{ HIX5HD2_MMC_CIU_CLK, clk_mmc_ciu, mmc_mux,
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h 
b/include/dt-bindings/clock/hix5hd2-clock.h
index e328669..5bd4135 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -46,6 +46,7 @@
 #define HIX5HD2_SFC_MUX64
 #define HIX5HD2_MMC_MUX65
 #define HIX5HD2_FEPHY_MUX  66
+#define HIX5HD2_SD_MUX 67
 
 /* gate clocks */
 #define HIX5HD2_SFC_RST128
@@ -56,6 +57,9 @@
 #define HIX5HD2_FWD_BUS_CLK133
 #define HIX5HD2_FWD_SYS_CLK134
 #define HIX5HD2_MAC0_PHY_CLK   135
+#define HIX5HD2_SD_CIU_CLK 136
+#define HIX5HD2_SD_BIU_CLK 137
+#define HIX5HD2_SD_CIU_RST 138
 
 /* complex */
 #define HIX5HD2_MAC0_CLK   192
-- 
1.7.9.5

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[PATCH v5 4/4] clk: hix5hd2: add I2C clocks

[Zhangfei Gao]

From: Wei Yan sledge.yan...@huawei.com

hix5hd2 add I2C clocks (I2C0~i2C5)

Signed-off-by: Wei Yan sledge.yan...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/clk/hisilicon/clk-hix5hd2.c   |   25 +
 include/dt-bindings/clock/hix5hd2-clock.h |   12 
 2 files changed, 37 insertions(+)

diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c 
b/drivers/clk/hisilicon/clk-hix5hd2.c
index 6e97e54..3f369c6 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -100,6 +100,31 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] 
__initdata = {
CLK_SET_RATE_PARENT, 0x178, 0, 0, },
{ HIX5HD2_WDG0_RST, rst_wdg0, clk_wdg0,
CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
+   /* I2C */
+   {HIX5HD2_I2C0_CLK, clk_i2c0, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
+   {HIX5HD2_I2C0_RST, rst_i2c0, clk_i2c0,
+CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, },
+   {HIX5HD2_I2C1_CLK, clk_i2c1, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
+   {HIX5HD2_I2C1_RST, rst_i2c1, clk_i2c1,
+CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, },
+   {HIX5HD2_I2C2_CLK, clk_i2c2, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
+   {HIX5HD2_I2C2_RST, rst_i2c2, clk_i2c2,
+CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, },
+   {HIX5HD2_I2C3_CLK, clk_i2c3, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 16, 0, },
+   {HIX5HD2_I2C3_RST, rst_i2c3, clk_i2c3,
+CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, },
+   {HIX5HD2_I2C4_CLK, clk_i2c4, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 20, 0, },
+   {HIX5HD2_I2C4_RST, rst_i2c4, clk_i2c4,
+CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, },
+   {HIX5HD2_I2C5_CLK, clk_i2c5, 100m,
+CLK_SET_RATE_PARENT, 0x06c, 0, 0, },
+   {HIX5HD2_I2C5_RST, rst_i2c5, clk_i2c5,
+CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, },
 };
 
 enum hix5hd2_clk_type {
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h 
b/include/dt-bindings/clock/hix5hd2-clock.h
index b8e3c9d..fd29c17 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -62,6 +62,18 @@
 #define HIX5HD2_SD_CIU_RST 138
 #define HIX5HD2_WDG0_CLK   139
 #define HIX5HD2_WDG0_RST   140
+#define HIX5HD2_I2C0_CLK   141
+#define HIX5HD2_I2C0_RST   142
+#define HIX5HD2_I2C1_CLK   143
+#define HIX5HD2_I2C1_RST   144
+#define HIX5HD2_I2C2_CLK   145
+#define HIX5HD2_I2C2_RST   146
+#define HIX5HD2_I2C3_CLK   147
+#define HIX5HD2_I2C3_RST   148
+#define HIX5HD2_I2C4_CLK   149
+#define HIX5HD2_I2C4_RST   150
+#define HIX5HD2_I2C5_CLK   151
+#define HIX5HD2_I2C5_RST   152
 
 /* complex */
 #define HIX5HD2_MAC0_CLK   192
-- 
1.7.9.5

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[PATCH v5 1/4] clk: hix5hd2: add complex clk

[Zhangfei Gao]

Support clk of sata, usb and ethernet

Signed-off-by: Jiancheng Xue xuejianch...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/clk/hisilicon/clk-hix5hd2.c   |  181 +
 include/dt-bindings/clock/hix5hd2-clock.h |9 ++
 2 files changed, 190 insertions(+)

diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c 
b/drivers/clk/hisilicon/clk-hix5hd2.c
index e5fcfb4..da9ca05 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -9,6 +9,8 @@
 
 #include linux/of_address.h
 #include dt-bindings/clock/hix5hd2-clock.h
+#include linux/slab.h
+#include linux/delay.h
 #include clk.h
 
 static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
@@ -79,8 +81,184 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] 
__initdata = {
CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
{ HIX5HD2_MMC_CIU_RST, rst_mmc_ciu, clk_mmc_ciu,
CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
+   /* gsf */
+   { HIX5HD2_FWD_BUS_CLK, clk_fwd_bus, NULL, 0, 0xcc, 0, 0, },
+   { HIX5HD2_FWD_SYS_CLK, clk_fwd_sys, clk_fwd_bus, 0, 0xcc, 5, 0, },
+   { HIX5HD2_MAC0_PHY_CLK, clk_fephy, clk_fwd_sys,
+CLK_SET_RATE_PARENT, 0x120, 0, 0, },
 };
 
+enum hix5hd2_clk_type {
+   TYPE_COMPLEX,
+   TYPE_ETHER,
+};
+
+struct hix5hd2_complex_clock {
+   const char  *name;
+   const char  *parent_name;
+   u32 id;
+   u32 ctrl_reg;
+   u32 ctrl_clk_mask;
+   u32 ctrl_rst_mask;
+   u32 phy_reg;
+   u32 phy_clk_mask;
+   u32 phy_rst_mask;
+   enum hix5hd2_clk_type type;
+};
+
+struct hix5hd2_clk_complex {
+   struct clk_hw   hw;
+   u32 id;
+   void __iomem*ctrl_reg;
+   u32 ctrl_clk_mask;
+   u32 ctrl_rst_mask;
+   void __iomem*phy_reg;
+   u32 phy_clk_mask;
+   u32 phy_rst_mask;
+};
+
+static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
+   {clk_mac0, clk_fephy, HIX5HD2_MAC0_CLK,
+   0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
+   {clk_mac1, clk_fwd_sys, HIX5HD2_MAC1_CLK,
+   0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER},
+   {clk_sata, NULL, HIX5HD2_SATA_CLK,
+   0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX},
+   {clk_usb, NULL, HIX5HD2_USB_CLK,
+   0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX},
+};
+
+#define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw)
+
+static int clk_ether_prepare(struct clk_hw *hw)
+{
+   struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
+   u32 val;
+
+   val = readl_relaxed(clk-ctrl_reg);
+   val |= clk-ctrl_clk_mask | clk-ctrl_rst_mask;
+   writel_relaxed(val, clk-ctrl_reg);
+   val = ~(clk-ctrl_rst_mask);
+   writel_relaxed(val, clk-ctrl_reg);
+
+   val = readl_relaxed(clk-phy_reg);
+   val |= clk-phy_clk_mask;
+   val = ~(clk-phy_rst_mask);
+   writel_relaxed(val, clk-phy_reg);
+   mdelay(10);
+
+   val = ~(clk-phy_clk_mask);
+   val |= clk-phy_rst_mask;
+   writel_relaxed(val, clk-phy_reg);
+   mdelay(10);
+
+   val |= clk-phy_clk_mask;
+   val = ~(clk-phy_rst_mask);
+   writel_relaxed(val, clk-phy_reg);
+   mdelay(30);
+   return 0;
+}
+
+static void clk_ether_unprepare(struct clk_hw *hw)
+{
+   struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
+   u32 val;
+
+   val = readl_relaxed(clk-ctrl_reg);
+   val = ~(clk-ctrl_clk_mask);
+   writel_relaxed(val, clk-ctrl_reg);
+}
+
+static struct clk_ops clk_ether_ops = {
+   .prepare = clk_ether_prepare,
+   .unprepare = clk_ether_unprepare,
+};
+
+static int clk_complex_enable(struct clk_hw *hw)
+{
+   struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
+   u32 val;
+
+   val = readl_relaxed(clk-ctrl_reg);
+   val |= clk-ctrl_clk_mask;
+   val = ~(clk-ctrl_rst_mask);
+   writel_relaxed(val, clk-ctrl_reg);
+
+   val = readl_relaxed(clk-phy_reg);
+   val |= clk-phy_clk_mask;
+   val = ~(clk-phy_rst_mask);
+   writel_relaxed(val, clk-phy_reg);
+
+   return 0;
+}
+
+static void clk_complex_disable(struct clk_hw *hw)
+{
+   struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
+   u32 val;
+
+   val = readl_relaxed(clk-ctrl_reg);
+   val |= clk-ctrl_rst_mask;
+   val = ~(clk-ctrl_clk_mask);
+   writel_relaxed(val, clk-ctrl_reg);
+
+   val = readl_relaxed(clk-phy_reg);
+   val |= clk-phy_rst_mask;
+   val = ~(clk-phy_clk_mask);
+   writel_relaxed(val, clk-phy_reg);
+}
+
+static struct clk_ops clk_complex_ops = {
+   .enable = clk_complex_enable,
+   .disable = clk_complex_disable,
+};
+
+void __init hix5hd2_clk_register_complex(struct

[PATCH v5 3/4] clk: hix5hd2: add watchdog0 clocks

[Zhangfei Gao]

From: Guoxiong Yan yanguoxi...@huawei.com

hix5hd2 add watchdog0 clocks

Signed-off-by: Guoxiong Yan yanguoxi...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/clk/hisilicon/clk-hix5hd2.c   |5 +
 include/dt-bindings/clock/hix5hd2-clock.h |2 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c 
b/drivers/clk/hisilicon/clk-hix5hd2.c
index 13d6ec2..6e97e54 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -95,6 +95,11 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata 
= {
{ HIX5HD2_FWD_SYS_CLK, clk_fwd_sys, clk_fwd_bus, 0, 0xcc, 5, 0, },
{ HIX5HD2_MAC0_PHY_CLK, clk_fephy, clk_fwd_sys,
 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
+   /* wdg0 */
+   { HIX5HD2_WDG0_CLK, clk_wdg0, 24m,
+   CLK_SET_RATE_PARENT, 0x178, 0, 0, },
+   { HIX5HD2_WDG0_RST, rst_wdg0, clk_wdg0,
+   CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
 };
 
 enum hix5hd2_clk_type {
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h 
b/include/dt-bindings/clock/hix5hd2-clock.h
index 5bd4135..b8e3c9d 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -60,6 +60,8 @@
 #define HIX5HD2_SD_CIU_CLK 136
 #define HIX5HD2_SD_BIU_CLK 137
 #define HIX5HD2_SD_CIU_RST 138
+#define HIX5HD2_WDG0_CLK   139
+#define HIX5HD2_WDG0_RST   140
 
 /* complex */
 #define HIX5HD2_MAC0_CLK   192
-- 
1.7.9.5

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Re: [PATCH resend 1/4] clk: hix5hd2: add complex clk

[Zhangfei Gao]

Hi, Mike

Thanks for the comments.
Sorry for the delay, since the trip.

On 11 September 2014 00:52, Mike Turquette mturque...@linaro.org wrote:
  +static int clk_ether_enable(struct clk_hw *hw)
  +{
  +   struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
  +   u32 val;
  +
  +   val = readl_relaxed(clk-ctrl_reg);
  +   val |= clk-ctrl_clk_mask | clk-ctrl_rst_mask;
  +   writel_relaxed(val, clk-ctrl_reg);
  +   val = ~(clk-ctrl_rst_mask);
  +   writel_relaxed(val, clk-ctrl_reg);
  +
  +   val = readl_relaxed(clk-phy_reg);
  +   val |= clk-phy_clk_mask;
  +   val = ~(clk-phy_rst_mask);
  +   writel_relaxed(val, clk-phy_reg);
  +   mdelay(10);
  +
  +   val = ~(clk-phy_clk_mask);
  +   val |= clk-phy_rst_mask;
  +   writel_relaxed(val, clk-phy_reg);
  +   mdelay(10);
  +
  +   val |= clk-phy_clk_mask;
  +   val = ~(clk-phy_rst_mask);
  +   writel_relaxed(val, clk-phy_reg);
  +   mdelay(30);

 With all of these mdelays, I wonder if you should use .prepare and
 .unprepare instead? Does the Ethernet driver call clk_{en|dis}able from
 interrupt context?


 Thank you for the advise.

 In hix5hd2 soc, these mdelays are necessary for resetting the Ethernet  phy
 device. The hardware need some time to be stable.It's difficult to use 
 .prepare
 and .unprepare instead, because they are embeded in several places among the
 whole sequence. Even though some code segment could be put into  the .prepare
 callback, mdelays should still be reserved. So we hope to keep this manner if
 it's ok.

 OK. I wonder if you should be using the reset controller framework to control 
 the
 reset of your phy? Some clock drivers are also reset drivers since bits
 for controlling that stuff are often combined in the same register
 space. As an example, take a look at:

 drivers/clk/qcom/gcc-apq8084.c

Have considered the reset before, and decided simply to encapsulate to clock.
1, The reset and delay is rather a silicon limitation, and will be
optimized later, so only switch on / off are required later.
2, There is dependence, like first reset, then delay, then switch on,
it would be complicated to add this to the net driver itself.
3, Some driver use standard driver, like usb / mmc, which already have
clock interface inside, it would be easier to use them directly
without touching the driver itself.



 The Ethernet driver won't call clk_enable and clk_disable from interrupt
 context.

 Good to know. clk_enable and clk_disable are designed to be called
 safely from interrupt context. clk_prepare and clk_unprepare often
 enable/disable a clock, but are designed for use in a regular process
 context (e.g. we might sleep or schedule). So depending on how long it
 takes you to enable/disable your Ethernet clock you might want to
 migrate to those callbacks instead.


Thanks for the info.
Could we directly move .clk_enable to .clk_preare, and move
.clk_disable to clk_unprepare.
Then the delay should not be a problem any more.
What the dirver using is clk_prepare_enable  clk_disable_unprepare,
which are called in open/close  probe.

Thanks
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Re: [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver

[Zhangfei Gao]

On 26 August 2014 13:25, Zhangfei Gao zhangfei@linaro.org wrote:
 Resend: verified on 3.17-rc1

 Wei Yan (2):
   i2c: hix5hd2: add devicetree documentation
   i2c: hix5hd2: add i2c controller driver

  .../devicetree/bindings/i2c/i2c-hix5hd2.txt|   31 ++
  drivers/i2c/busses/Kconfig |   16 +
  drivers/i2c/busses/Makefile|1 +
  drivers/i2c/busses/i2c-hix5hd2.c   |  576 
 
  4 files changed, 624 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
  create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c


Any comments, thanks a lot.
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Re: [PATCH v4 1/2] rc: Add DT bindings for hix5hd2

[zhangfei]

On 09/01/2014 11:49 AM, Varka Bhadram wrote:

On 08/31/2014 08:09 AM, Zhangfei Gao wrote:

From: Guoxiong Yan yanguoxi...@huawei.com

Signed-off-by: Guoxiong Yan yanguoxi...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
  .../devicetree/bindings/media/hix5hd2-ir.txt   |   25

  1 file changed, 25 insertions(+)
  create mode 100644
Documentation/devicetree/bindings/media/hix5hd2-ir.txt

diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
new file mode 100644
index 000..fb5e760
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
@@ -0,0 +1,25 @@
+Device-Tree bindings for hix5hd2 ir IP
+
+Required properties:
+- compatible: Should contain hisilicon,hix5hd2-ir.
+- reg: Base physical address of the controller and length of memory
+  mapped region.
+- interrupts: interrupt-specifier for the sole interrupt
generated by
+  the device. The interrupt specifier format depends on the
interrupt
+  controller parent.
+- clocks: clock phandle and specifier pair.
+- hisilicon,power-syscon: phandle of syscon used to control power.
+


No need of tab space before -compatible Give tab spaces after
properties...

ex:

Required properties:
- compatible: Should contain hisilicon,hix5hd2-ir.
- reg: Base physical address of the controller and length of
memory
   mapped region.

...

Its not standard, but in my view it is understandable. Now every one
following this
one.


Really, I still prefer the original one.
Have checked several bindings under media, so add tab ahead
like st-rc.txt, gpio-ir-receiver.txt

Thanks
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Re: [PATCH v3 2/3] rc: Introduce hix5hd2 IR transmitter driver

[zhangfei]

Hi, Sean

On 08/29/2014 12:22 AM, Sean Young wrote:

On Thu, Aug 28, 2014 at 11:16:16PM +0800, Zhangfei Gao wrote:

From: Guoxiong Yan yanguoxi...@huawei.com

IR transmitter driver for Hisilicon hix5hd2 soc

By default all protocols are disabled.
For example nec decoder can be enabled by either
1. ir-keytable -p nec
2. echo nec  /sys/class/rc/rc0/protocols
See see Documentation/ABI/testing/sysfs-class-rc


I'm not sure that's true any more. All protocols are enabled, right?

By default, all protocols are disabled

#cat /sys/class/rc/rc0/protocols
other [unknown] rc-5 nec rc-6 jvc sony rc-5-sz sanyo sharp mce_kbd lirc xmp


+config IR_HIX5HD2
+   tristate Hisilicon hix5hd2 IR remote control
+   depends on RC_CORE
+   help
+Say Y here if you want to use hisilicon remote control.
+The driver passes raw pulse and space information to the LIRC decoder.
+To compile this driver as a module, choose M here: the module will be
+called hisi_ir.


The module won't be called that.

Yes, change to ir-hix5hd2r.


+struct hix5hd2_ir_priv {
+   int irq;
+   void*base;
+   struct device   *dev;
+   struct rc_dev   *rdev;
+   struct regmap   *regmap;
+   struct clk  *clock;
+   const char  *map_name;


map_name member is only assigned, it's unused.

OK


+static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
+{
+   u32 symb_num, symb_val, symb_time;
+   u32 data_l, data_h;
+   u32 irq_sr, i;
+   struct hix5hd2_ir_priv *priv = data;
+
+   irq_sr = readl_relaxed(priv-base + IR_INTS);
+   if (irq_sr  INTMS_OVERFLOW) {
+   /*
+* we must read IR_DATAL first, then we can clean up
+* IR_INTS availably since logic would not clear
+* fifo when overflow, drv do the job
+*/
+   ir_raw_event_reset(priv-rdev);
+   symb_num = readl_relaxed(priv-base + IR_DATAH);
+   for (i = 0; i  symb_num; i++)
+   readl_relaxed(priv-base + IR_DATAL);
+
+   writel_relaxed(INT_CLR_OVERFLOW, priv-base + IR_INTC);
+   dev_info(priv-dev, overflow, level=%d\n,
+IR_CFG_INT_THRESHOLD);
+   }
+
+   if ((irq_sr  INTMS_SYMBRCV) || (irq_sr  INTMS_TIMEOUT)) {
+   DEFINE_IR_RAW_EVENT(ev);
+
+   symb_num = readl_relaxed(priv-base + IR_DATAH);
+   for (i = 0; i  symb_num; i++) {
+   symb_val = readl_relaxed(priv-base + IR_DATAL);
+   data_l = ((symb_val  0x) * 10);
+   data_h =  ((symb_val  16)  0x) * 10;
+   symb_time = (data_l + data_h) / 10;
+
+   ev.duration = US_TO_NS(data_l);
+   ev.pulse = true;
+   ir_raw_event_store(priv-rdev, ev);
+
+   if (symb_time  IR_CFG_SYMBOL_MAXWIDTH) {
+   ev.duration = US_TO_NS(data_h);
+   ev.pulse = false;
+   ir_raw_event_store(priv-rdev, ev);
+   } else {
+   hix5hd2_ir_send_lirc_timeout(priv-rdev);


Surely this is when IR goes idle.

ir_raw_event_set_idle(priv-rdev, true);

This will set up idle processing and send the timeout IR event.


Yes, ir_raw_event_set_idle is simpler.


+static int hix5hd2_ir_open(struct rc_dev *rdev)
+{
+   struct hix5hd2_ir_priv *priv = rdev-priv;
+
+   hix5hd2_ir_enable(priv, true);
+   hix5hd2_ir_config(priv);


hix5hd2_ir_config can fail, the error can be returned to userspace rather
than silently failing.


Change to return hix5hd2_ir_config(priv);


+   if (devm_request_irq(dev, priv-irq, hix5hd2_ir_rx_interrupt,
+IRQF_NO_SUSPEND, pdev-name, priv)  0) {
+   dev_err(dev, IRQ %d register failed\n, priv-irq);
+   return -EINVAL;
+   }


You've requested the interrupts too early, if an interrupts arrives before
you've set up all the members in priv it'll go bang in the interrupt handler.


Will move request_irq after rc_register_device
However, ir controller only be enabled in open.


+
+   /**
+* for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW
+* lircd expects a long space first before a signal train to sync.
+*/
+   hix5hd2_ir_send_lirc_timeout(rdev);


I don't know why this is needed, sounds like a lircd oddity.

To be honst, I don't know either.
This is refer to st_rc.c
Currently I only test with nec decoder.
Will remove this until it is required.


+static struct platform_driver hix5hd2_ir_driver = {
+   .driver = {
+   .name = IR_HIX5HD2_NAME,
+   .of_match_table = hix5hd2_ir_table,
+   .pm

Re: [PATCH v3 2/3] rc: Introduce hix5hd2 IR transmitter driver

[zhangfei]

On 08/29/2014 11:41 AM, Varka Bhadram wrote:

On 08/28/2014 08:46 PM, Zhangfei Gao wrote:

From: Guoxiong Yan yanguoxi...@huawei.com

IR transmitter driver for Hisilicon hix5hd2 soc

By default all protocols are disabled.
For example nec decoder can be enabled by either
1. ir-keytable -p nec
2. echo nec  /sys/class/rc/rc0/protocols
See see Documentation/ABI/testing/sysfs-class-rc


(...)


+static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
+{
+u32 symb_num, symb_val, symb_time;
+u32 data_l, data_h;
+u32 irq_sr, i;
+struct hix5hd2_ir_priv *priv = data;
+
+irq_sr = readl_relaxed(priv-base + IR_INTS);
+if (irq_sr  INTMS_OVERFLOW) {
+/*
+ * we must read IR_DATAL first, then we can clean up
+ * IR_INTS availably since logic would not clear
+ * fifo when overflow, drv do the job
+ */
+ir_raw_event_reset(priv-rdev);
+symb_num = readl_relaxed(priv-base + IR_DATAH);
+for (i = 0; i  symb_num; i++)
+readl_relaxed(priv-base + IR_DATAL);
+
+writel_relaxed(INT_CLR_OVERFLOW, priv-base + IR_INTC);
+dev_info(priv-dev, overflow, level=%d\n,
+ IR_CFG_INT_THRESHOLD);
+}
+
+if ((irq_sr  INTMS_SYMBRCV) || (irq_sr  INTMS_TIMEOUT)) {
+DEFINE_IR_RAW_EVENT(ev);
+
+symb_num = readl_relaxed(priv-base + IR_DATAH);
+for (i = 0; i  symb_num; i++) {
+symb_val = readl_relaxed(priv-base + IR_DATAL);
+data_l = ((symb_val  0x) * 10);
+data_h =  ((symb_val  16)  0x) * 10;
+symb_time = (data_l + data_h) / 10;
+
+ev.duration = US_TO_NS(data_l);
+ev.pulse = true;
+ir_raw_event_store(priv-rdev, ev);
+
+if (symb_time  IR_CFG_SYMBOL_MAXWIDTH) {
+ev.duration = US_TO_NS(data_h);
+ev.pulse = false;
+ir_raw_event_store(priv-rdev, ev);
+} else {
+hix5hd2_ir_send_lirc_timeout(priv-rdev);
+}
+}
+
+if (irq_sr  INTMS_SYMBRCV)
+writel_relaxed(INT_CLR_RCV, priv-base + IR_INTC);
+if (irq_sr  INTMS_TIMEOUT)
+writel_relaxed(INT_CLR_TIMEOUT, priv-base + IR_INTC);
+}
+
+/* Empty software fifo */
+ir_raw_event_handle(priv-rdev);
+return IRQ_HANDLED;
+}
+


It looks good if the entire ISR() above the probe()/remove()
functionalities
of the driver. Maximum of the developers follows this structure.

(...)


+static struct of_device_id hix5hd2_ir_table[] = {
+{ .compatible = hisilicon,hix5hd2-ir, },
+{},
+};
+MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
+


Every driver put these device ids above *struct platform_driver*
definition.
So that we can see the of_match_table


+static int hix5hd2_ir_probe(struct platform_device *pdev)
+{
+int ret;
+struct rc_dev *rdev;
+struct device *dev = pdev-dev;
+struct resource *res;
+struct hix5hd2_ir_priv *priv;
+struct device_node *node = pdev-dev.of_node;
+
+priv = devm_kzalloc(dev, sizeof(struct hix5hd2_ir_priv),
GFP_KERNEL);


sizeof(*priv)...?


+if (!priv)
+return -ENOMEM;
+


(...)


+#endif
+
+static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
+ hix5hd2_ir_resume);
+


We can move the device ids here


Thanks Varka, will change sequence accordingly.

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[PATCH v4 1/2] rc: Add DT bindings for hix5hd2

[Zhangfei Gao]

From: Guoxiong Yan yanguoxi...@huawei.com

Signed-off-by: Guoxiong Yan yanguoxi...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 .../devicetree/bindings/media/hix5hd2-ir.txt   |   25 
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/hix5hd2-ir.txt

diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt 
b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
new file mode 100644
index 000..fb5e760
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
@@ -0,0 +1,25 @@
+Device-Tree bindings for hix5hd2 ir IP
+
+Required properties:
+   - compatible: Should contain hisilicon,hix5hd2-ir.
+   - reg: Base physical address of the controller and length of memory
+ mapped region.
+   - interrupts: interrupt-specifier for the sole interrupt generated by
+ the device. The interrupt specifier format depends on the interrupt
+ controller parent.
+   - clocks: clock phandle and specifier pair.
+   - hisilicon,power-syscon: phandle of syscon used to control power.
+
+Optional properties:
+   - linux,rc-map-name : Remote control map name.
+
+Example node:
+
+   ir: ir@f8001000 {
+   compatible = hisilicon,hix5hd2-ir;
+   reg = 0xf8001000 0x1000;
+   interrupts = 0 47 4;
+   clocks = clock HIX5HD2_FIXED_24M;
+   hisilicon,power-syscon = sysctrl;
+   linux,rc-map-name = rc-tivo;
+   };
-- 
1.7.9.5

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[PATCH v4 0/3] Introduce hix5hd2 IR transmitter driver

[Zhangfei Gao]

v4:
Change sequence and some comments from Sean and Varka

v3:
Got info from Mauro, 3.17 disable all protocol by default, specific protocol
can be selected via ir-keytable and /sys/class/rc/rc0/protocols

Got suggestion from Sean, add rdev specific info, like timeout, resoluton.
Add optional property linux,rc-map-name, if kernel keymap is used
otherwise user space keymap will be used.

v2:
Rebase to 3.17-rc1, solve two issues:
a) rc_set_allowed_protocols is deprecated
b) rc-ir-raw.c add empty change_protocol, which block using all protocol
For example, when rdev-map_name = RC_MAP_LIRC, ir-nec-decoder can not be used.

Guoxiong Yan (2):
  rc: Add DT bindings for hix5hd2
  rc: Introduce hix5hd2 IR transmitter driver

Zhangfei Gao (1):
  ARM: dts: hix5hd2: add ir node

 .../devicetree/bindings/media/hix5hd2-ir.txt   |   25 ++
 arch/arm/boot/dts/hisi-x5hd2.dtsi  |   10 +-
 drivers/media/rc/Kconfig   |   11 +
 drivers/media/rc/Makefile  |1 +
 drivers/media/rc/ir-hix5hd2.c  |  343 
 5 files changed, 389 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/media/hix5hd2-ir.txt
 create mode 100644 drivers/media/rc/ir-hix5hd2.c

-- 
1.7.9.5

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[PATCH v4 2/2] rc: Introduce hix5hd2 IR transmitter driver

[Zhangfei Gao]

From: Guoxiong Yan yanguoxi...@huawei.com

IR transmitter driver for Hisilicon hix5hd2 soc

By default all protocols are disabled.
For example nec decoder can be enabled by either
1. ir-keytable -p nec
2. echo nec  /sys/class/rc/rc0/protocols
See see Documentation/ABI/testing/sysfs-class-rc

Signed-off-by: Guoxiong Yan yanguoxi...@huawei.com
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
 drivers/media/rc/Kconfig  |   10 ++
 drivers/media/rc/Makefile |1 +
 drivers/media/rc/ir-hix5hd2.c |  343 +
 3 files changed, 354 insertions(+)
 create mode 100644 drivers/media/rc/ir-hix5hd2.c

diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 5e626af..01e5f7a 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -164,6 +164,16 @@ config IR_ENE
   To compile this driver as a module, choose M here: the
   module will be called ene_ir.
 
+config IR_HIX5HD2
+   tristate Hisilicon hix5hd2 IR remote control
+   depends on RC_CORE
+   help
+Say Y here if you want to use hisilicon hix5hd2 remote control.
+To compile this driver as a module, choose M here: the module will be
+called ir-hix5hd2.
+
+If you're not sure, select N here
+
 config IR_IMON
tristate SoundGraph iMON Receiver and Display
depends on USB_ARCH_HAS_HCD
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 9f9843a1..0989f94 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_IR_XMP_DECODER) += ir-xmp-decoder.o
 
 # stand-alone IR receivers/transmitters
 obj-$(CONFIG_RC_ATI_REMOTE) += ati_remote.o
+obj-$(CONFIG_IR_HIX5HD2) += ir-hix5hd2.o
 obj-$(CONFIG_IR_IMON) += imon.o
 obj-$(CONFIG_IR_ITE_CIR) += ite-cir.o
 obj-$(CONFIG_IR_MCEUSB) += mceusb.o
diff --git a/drivers/media/rc/ir-hix5hd2.c b/drivers/media/rc/ir-hix5hd2.c
new file mode 100644
index 000..64f8257
--- /dev/null
+++ b/drivers/media/rc/ir-hix5hd2.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/regmap.h
+#include media/rc-core.h
+
+#define IR_ENABLE  0x00
+#define IR_CONFIG  0x04
+#define CNT_LEADS  0x08
+#define CNT_LEADE  0x0c
+#define CNT_SLEADE 0x10
+#define CNT0_B 0x14
+#define CNT1_B 0x18
+#define IR_BUSY0x1c
+#define IR_DATAH   0x20
+#define IR_DATAL   0x24
+#define IR_INTM0x28
+#define IR_INTS0x2c
+#define IR_INTC0x30
+#define IR_START   0x34
+
+/* interrupt mask */
+#define INTMS_SYMBRCV  (BIT(24) | BIT(8))
+#define INTMS_TIMEOUT  (BIT(25) | BIT(9))
+#define INTMS_OVERFLOW (BIT(26) | BIT(10))
+#define INT_CLR_OVERFLOW   BIT(18)
+#define INT_CLR_TIMEOUTBIT(17)
+#define INT_CLR_RCVBIT(16)
+#define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17))
+
+#define IR_CLK 0x48
+#define IR_CLK_ENABLE  BIT(4)
+#define IR_CLK_RESET   BIT(5)
+
+#define IR_CFG_WIDTH_MASK  0x
+#define IR_CFG_WIDTH_SHIFT 16
+#define IR_CFG_FORMAT_MASK 0x3
+#define IR_CFG_FORMAT_SHIFT14
+#define IR_CFG_INT_LEVEL_MASK  0x3f
+#define IR_CFG_INT_LEVEL_SHIFT 8
+/* only support raw mode */
+#define IR_CFG_MODE_RAWBIT(7)
+#define IR_CFG_FREQ_MASK   0x7f
+#define IR_CFG_FREQ_SHIFT  0
+#define IR_CFG_INT_THRESHOLD   1
+/* symbol start from low to high, symbol stream end at high*/
+#define IR_CFG_SYMBOL_FMT  0
+#define IR_CFG_SYMBOL_MAXWIDTH 0x3e80
+
+#define IR_HIX5HD2_NAMEhix5hd2-ir
+
+struct hix5hd2_ir_priv {
+   int irq;
+   void*base;
+   struct device   *dev;
+   struct rc_dev   *rdev;
+   struct regmap   *regmap;
+   struct clk  *clock;
+   unsigned long   rate;
+};
+
+static void hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
+{
+   u32 val;
+
+   regmap_read(dev-regmap, IR_CLK, val);
+   if (on) {
+   val = ~IR_CLK_RESET;
+   val |= IR_CLK_ENABLE;
+   } else {
+   val = ~IR_CLK_ENABLE;
+   val |= IR_CLK_RESET;
+   }
+   regmap_write(dev-regmap, IR_CLK, val);
+}
+
+static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
+{
+   int timeout = 1;
+   u32 val, rate