Re: [PATCH 1/3] clk: samsung: exynos4: Add SSS gate clock
On 20.10.2015 04:59, Stephen Boyd wrote: > On 10/19, Krzysztof Kozlowski wrote: >> Add a gate clock for controlling all clocks of Security Sub System >> (SSS). >> >> Signed-off-by: Krzysztof Kozlowski >> --- > > The To: list is huge, so I have no idea if you want me to apply > this patch or not, and given that it's part of a series that has > dts changes I guess that means it should go through arm-soc: > > Acked-by: Stephen Boyd If you are OK with that I would like to push it through arm-soc. Thanks for the ack! Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: samsung: exynos4: Add SSS gate clock
On 10/19, Krzysztof Kozlowski wrote: > Add a gate clock for controlling all clocks of Security Sub System > (SSS). > > Signed-off-by: Krzysztof Kozlowski > --- The To: list is huge, so I have no idea if you want me to apply this patch or not, and given that it's part of a series that has dts changes I guess that means it should go through arm-soc: Acked-by: Stephen Boyd -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] clk: samsung: exynos4: Add SSS gate clock
Add a gate clock for controlling all clocks of Security Sub System
(SSS).
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/samsung/clk-exynos4.c | 1 +
include/dt-bindings/clock/exynos4.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 7f370d3e0983..ac03e4fe2871 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1024,6 +1024,7 @@ static struct samsung_gate_clock exynos4_gate_clks[]
__initdata = {
0, 0),
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
0, 0),
+ GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
diff --git a/include/dt-bindings/clock/exynos4.h
b/include/dt-bindings/clock/exynos4.h
index c4b1676ea674..c40111f36d5e 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -93,6 +93,7 @@
#define CLK_SCLK_FIMG2D177
/* gate clocks */
+#define CLK_SSS255
#define CLK_FIMC0 256
#define CLK_FIMC1 257
#define CLK_FIMC2 258
--
1.9.1
--
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