Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 02/12/15 04:49, Mark Rutland wrote:
> Hi,
>
> I haven't given this a thorough review, but I spotted a couple of items
> below.
>
> On Wed, Feb 11, 2015 at 01:05:24AM +, Stephen Boyd wrote:
>> Scorpion supports a set of local performance monitor event
>> selection registers (LPM) sitting behind a cp15 based interface
>> that extend the architected PMU events to include Scorpion CPU
>> and Venum VFP specific events. To use these events the user is
>> expected to program the lpm register with the event code shifted
>> into the group they care about and then point the PMNx event at
>> that region+group combo by writing a LPMn_GROUPx event. Add
>> support for this hardware.
>>
>> Note: the raw event number is a pure software construct that
>> allows us to map the multi-dimensional number space of regions,
>> groups, and event codes into a flat event number space suitable
>> for use by the perf framework.
>>
>> This is based on code originally written by Ashwin Chaugule and
>> Neil Leeder [1] massed to become similar to the Krait PMU support
>> code.
>>
>> [1]
>> https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
>>
>> Cc: Neil Leeder
>> Cc: Ashwin Chaugule
>> Cc:
>> Signed-off-by: Stephen Boyd
>> ---
>> Documentation/devicetree/bindings/arm/pmu.txt | 2 +
>> arch/arm/kernel/perf_event_cpu.c | 2 +
>> arch/arm/kernel/perf_event_v7.c | 395
>> ++
>> 3 files changed, 399 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
>> b/Documentation/devicetree/bindings/arm/pmu.txt
>> index 75ef91d08f3b..6e54a9d88b7a 100644
>> --- a/Documentation/devicetree/bindings/arm/pmu.txt
>> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
>> @@ -18,6 +18,8 @@ Required properties:
>> "arm,arm11mpcore-pmu"
>> "arm,arm1176-pmu"
>> "arm,arm1136-pmu"
>> + "qcom,scorpion-pmu"
>> + "qcom,scorpion-mp-pmu"
> Is the PMU any different in the MP and !MP variants? The code doesn't
> seem to handle the two any differently and will pass either to userspace
> as "armv7_scorpion".
>
> If there is some difference that we don't handle right now, that's fine,
> it just looks a little odd.
It seems that on MP there are two event encodings on MP that aren't
there on !MP and vice versa[1]. So I made two compatibles to reflect
that. I'll make two names that go to userspace to clarify this.
>> +static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
>> + [PERF_COUNT_HW_CACHE_OP_MAX]
>> + [PERF_COUNT_HW_CACHE_RESULT_MAX]
>> = {
>> + PERF_CACHE_MAP_ALL_UNSUPPORTED,
>> + /*
>> +* The performance counters don't differentiate between read and
>> write
>> +* accesses/misses so this isn't strictly correct, but it's the best
>> we
>> +* can do. Writes and reads get combined.
>> +*/
>> + [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] =
>> ARMV7_PERFCTR_L1_DCACHE_ACCESS,
>> + [C(L1D)][C(OP_READ)][C(RESULT_MISS)] =
>> ARMV7_PERFCTR_L1_DCACHE_REFILL,
>> + [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] =
>> ARMV7_PERFCTR_L1_DCACHE_ACCESS,
>> + [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] =
>> ARMV7_PERFCTR_L1_DCACHE_REFILL,
>> + [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
>> + [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
>> + [C(L1I)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
>> + [C(L1I)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
> These last two entries go against the policy we set in commit
> 40c390c768f89849: "ARM: perf: don't pretend to support counting of L1I
> writes", so I think they should be dropped.
Fair enough. Thanks for the pointer.
>
>> + /*
>> +* Only ITLB misses and DTLB refills are supported. If users want
>> the
>> +* DTLB refills misses a raw counter must be used.
>> +*/
>> + [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
>> + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
>> + [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
>> + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
>> + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
>> + [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
>> + [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] =
>> ARMV7_PERFCTR_PC_BRANCH_PRED,
>> + [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
>> + [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] =
>> ARMV7_PERFCTR_PC_BRANCH_PRED,
>> + [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
>> +};
> Not ARMV7_PERFCTR_PC_BRANCH_MIS_PRED for the RESULT_MISS cases as with
> all other ARMv7 instances (Krait included)?
I was just copying the stuff from downstream. I th
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
Hi,
I haven't given this a thorough review, but I spotted a couple of items
below.
On Wed, Feb 11, 2015 at 01:05:24AM +, Stephen Boyd wrote:
> Scorpion supports a set of local performance monitor event
> selection registers (LPM) sitting behind a cp15 based interface
> that extend the architected PMU events to include Scorpion CPU
> and Venum VFP specific events. To use these events the user is
> expected to program the lpm register with the event code shifted
> into the group they care about and then point the PMNx event at
> that region+group combo by writing a LPMn_GROUPx event. Add
> support for this hardware.
>
> Note: the raw event number is a pure software construct that
> allows us to map the multi-dimensional number space of regions,
> groups, and event codes into a flat event number space suitable
> for use by the perf framework.
>
> This is based on code originally written by Ashwin Chaugule and
> Neil Leeder [1] massed to become similar to the Krait PMU support
> code.
>
> [1]
> https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
>
> Cc: Neil Leeder
> Cc: Ashwin Chaugule
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/pmu.txt | 2 +
> arch/arm/kernel/perf_event_cpu.c | 2 +
> arch/arm/kernel/perf_event_v7.c | 395
> ++
> 3 files changed, 399 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
> b/Documentation/devicetree/bindings/arm/pmu.txt
> index 75ef91d08f3b..6e54a9d88b7a 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.txt
> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
> @@ -18,6 +18,8 @@ Required properties:
> "arm,arm11mpcore-pmu"
> "arm,arm1176-pmu"
> "arm,arm1136-pmu"
> + "qcom,scorpion-pmu"
> + "qcom,scorpion-mp-pmu"
Is the PMU any different in the MP and !MP variants? The code doesn't
seem to handle the two any differently and will pass either to userspace
as "armv7_scorpion".
If there is some difference that we don't handle right now, that's fine,
it just looks a little odd.
[...]
> +static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> + [PERF_COUNT_HW_CACHE_OP_MAX]
> + [PERF_COUNT_HW_CACHE_RESULT_MAX]
> = {
> + PERF_CACHE_MAP_ALL_UNSUPPORTED,
> + /*
> +* The performance counters don't differentiate between read and write
> +* accesses/misses so this isn't strictly correct, but it's the best
> we
> +* can do. Writes and reads get combined.
> +*/
> + [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] =
> ARMV7_PERFCTR_L1_DCACHE_ACCESS,
> + [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
> + [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] =
> ARMV7_PERFCTR_L1_DCACHE_ACCESS,
> + [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] =
> ARMV7_PERFCTR_L1_DCACHE_REFILL,
> + [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
> + [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
> + [C(L1I)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
> + [C(L1I)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
These last two entries go against the policy we set in commit
40c390c768f89849: "ARM: perf: don't pretend to support counting of L1I
writes", so I think they should be dropped.
> + /*
> +* Only ITLB misses and DTLB refills are supported. If users want the
> +* DTLB refills misses a raw counter must be used.
> +*/
> + [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
> + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
> + [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
> + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
> + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
> + [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
> + [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
> + [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
> + [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] =
> ARMV7_PERFCTR_PC_BRANCH_PRED,
> + [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
> +};
Not ARMV7_PERFCTR_PC_BRANCH_MIS_PRED for the RESULT_MISS cases as with
all other ARMv7 instances (Krait included)?
Thanks,
Mark.
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Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 11 February 2015 at 13:27, Stephen Boyd wrote: > On 02/10, Ashwin Chaugule wrote: >> Hi Stephen, >> >> On 10 February 2015 at 20:05, Stephen Boyd wrote: >> > Scorpion supports a set of local performance monitor event >> > selection registers (LPM) sitting behind a cp15 based interface >> > that extend the architected PMU events to include Scorpion CPU >> > and Venum VFP specific events. To use these events the user is >> > expected to program the lpm register with the event code shifted >> > into the group they care about and then point the PMNx event at >> > that region+group combo by writing a LPMn_GROUPx event. Add >> > support for this hardware. >> > >> > Note: the raw event number is a pure software construct that >> > allows us to map the multi-dimensional number space of regions, >> > groups, and event codes into a flat event number space suitable >> > for use by the perf framework. >> > >> > This is based on code originally written by Ashwin Chaugule and >> > Neil Leeder [1] massed to become similar to the Krait PMU support >> > code. >> >> Thanks for taking this up! >> Overall this series looks good to me, but from what I faintly >> recollect, doesn't this (and the Krait pmu code) get affected by >> powercollapse issues anymore? >> e.g. >> https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/arch/arm/kernel/perf_event_msm.c?h=msm-3.4&id=b5ca687960f0fea2f4735e83ca5c9543474c19de >> > > Right now there isn't any power collapse support in mainline so > there's no immediate problem. Once we add power collapse support > (i.e. cpuidle) to the Scorpion and Krait platforms we'll need to > do something in the perf event code to properly maintain the > counts across idle. I imagine it would be done by registering for > cpu_pm notifications and then doing the save/restore on > CPU_PM_ENTER and CPU_PM_EXIT. At least, that's what you started > doing in this patch[1]. And then it seems the patch you mention > came after that and actually did the save/restore of the counts. > > [1] > https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/?h=msm-3.4&id=464983a7e991a484cac0bc0885cee4fee318d659 Right. Thats essential whenever the power collapse stuff goes in. Thanks, Ashwin. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 02/10, Stephen Boyd wrote:
> Scorpion supports a set of local performance monitor event
> selection registers (LPM) sitting behind a cp15 based interface
> that extend the architected PMU events to include Scorpion CPU
> and Venum VFP specific events. To use these events the user is
> expected to program the lpm register with the event code shifted
> into the group they care about and then point the PMNx event at
> that region+group combo by writing a LPMn_GROUPx event. Add
> support for this hardware.
>
> Note: the raw event number is a pure software construct that
> allows us to map the multi-dimensional number space of regions,
> groups, and event codes into a flat event number space suitable
> for use by the perf framework.
>
> This is based on code originally written by Ashwin Chaugule and
> Neil Leeder [1] massed to become similar to the Krait PMU support
> code.
>
> [1]
> https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
>
> Cc: Neil Leeder
> Cc: Ashwin Chaugule
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/pmu.txt | 2 +
> arch/arm/kernel/perf_event_cpu.c | 2 +
> arch/arm/kernel/perf_event_v7.c | 395
> ++
> 3 files changed, 399 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
> b/Documentation/devicetree/bindings/arm/pmu.txt
> index 75ef91d08f3b..6e54a9d88b7a 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.txt
> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
> @@ -18,6 +18,8 @@ Required properties:
> "arm,arm11mpcore-pmu"
> "arm,arm1176-pmu"
> "arm,arm1136-pmu"
> + "qcom,scorpion-pmu"
> + "qcom,scorpion-mp-pmu"
> "qcom,krait-pmu"
> - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a
> per-cpu
> interrupt (PPI) then 1 interrupt should be specified.
> diff --git a/arch/arm/kernel/perf_event_cpu.c
> b/arch/arm/kernel/perf_event_cpu.c
> index dd9acc95ebc0..010ffd241434 100644
> --- a/arch/arm/kernel/perf_event_cpu.c
> +++ b/arch/arm/kernel/perf_event_cpu.c
> @@ -242,6 +242,8 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
> {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
> {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
> {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
> + {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
> + {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_pmu_init},
> {.compatible = "qcom,krait-pmu",.data = krait_pmu_init},
> {},
> };
> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index 84a3ec3bc592..14bc8726f554 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -140,6 +140,23 @@ enum krait_perf_types {
> KRAIT_PERFCTR_L1_DTLB_ACCESS= 0x12210,
> };
>
> +/* ARMv7 Scorpion specific event types */
> +enum scorpion_perf_types {
> + SCORPION_LPM0_GROUP0= 0x4c,
> + SCORPION_LPM1_GROUP0= 0x50,
> + SCORPION_LPM2_GROUP0= 0x54,
> + SCORPION_L2LPM_GROUP0 = 0x58,
> + SCORPION_VLPM_GROUP0= 0x5c,
> +
> + SCORPION_ICACHE_ACCESS = 0x10053,
> + SCORPION_ICACHE_MISS= 0x10052,
> +
> + SCORPION_DTLB_ACCESS= 0x12013,
> + SCORPION_DTLB_MISS = 0x12012,
> +
> + SCORPION_ITLB_MISS = 0x12021,
> +};
> +
> /*
> * Cortex-A8 HW events mapping
> *
> @@ -482,6 +499,51 @@ static const unsigned
> krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> };
>
> /*
> + * Scorpion HW events mapping
> + */
> +static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
> + PERF_MAP_ALL_UNSUPPORTED,
> + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
> + [PERF_COUNT_HW_INSTRUCTIONS]= ARMV7_PERFCTR_INSTR_EXECUTED,
> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
> + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
> + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
> +};
> +
> +static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> + [PERF_COUNT_HW_CACHE_OP_MAX]
> + [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
> + PERF_CACHE_MAP_ALL_UNSUPPORTED,
> + /*
> + * The performance counters don't differentiate between read and write
> + * accesses/misses so this isn't strictly correct, but it's the best we
> + * can do. Writes and reads get combined.
> + */
> + [C(L1D)][C(OP_
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
On 02/10, Ashwin Chaugule wrote: > Hi Stephen, > > On 10 February 2015 at 20:05, Stephen Boyd wrote: > > Scorpion supports a set of local performance monitor event > > selection registers (LPM) sitting behind a cp15 based interface > > that extend the architected PMU events to include Scorpion CPU > > and Venum VFP specific events. To use these events the user is > > expected to program the lpm register with the event code shifted > > into the group they care about and then point the PMNx event at > > that region+group combo by writing a LPMn_GROUPx event. Add > > support for this hardware. > > > > Note: the raw event number is a pure software construct that > > allows us to map the multi-dimensional number space of regions, > > groups, and event codes into a flat event number space suitable > > for use by the perf framework. > > > > This is based on code originally written by Ashwin Chaugule and > > Neil Leeder [1] massed to become similar to the Krait PMU support > > code. > > Thanks for taking this up! > Overall this series looks good to me, but from what I faintly > recollect, doesn't this (and the Krait pmu code) get affected by > powercollapse issues anymore? > e.g. > https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/arch/arm/kernel/perf_event_msm.c?h=msm-3.4&id=b5ca687960f0fea2f4735e83ca5c9543474c19de > Right now there isn't any power collapse support in mainline so there's no immediate problem. Once we add power collapse support (i.e. cpuidle) to the Scorpion and Krait platforms we'll need to do something in the perf event code to properly maintain the counts across idle. I imagine it would be done by registering for cpu_pm notifications and then doing the save/restore on CPU_PM_ENTER and CPU_PM_EXIT. At least, that's what you started doing in this patch[1]. And then it seems the patch you mention came after that and actually did the save/restore of the counts. [1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/?h=msm-3.4&id=464983a7e991a484cac0bc0885cee4fee318d659 -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
Hi Stephen,
On 10 February 2015 at 20:05, Stephen Boyd wrote:
> Scorpion supports a set of local performance monitor event
> selection registers (LPM) sitting behind a cp15 based interface
> that extend the architected PMU events to include Scorpion CPU
> and Venum VFP specific events. To use these events the user is
> expected to program the lpm register with the event code shifted
> into the group they care about and then point the PMNx event at
> that region+group combo by writing a LPMn_GROUPx event. Add
> support for this hardware.
>
> Note: the raw event number is a pure software construct that
> allows us to map the multi-dimensional number space of regions,
> groups, and event codes into a flat event number space suitable
> for use by the perf framework.
>
> This is based on code originally written by Ashwin Chaugule and
> Neil Leeder [1] massed to become similar to the Krait PMU support
> code.
Thanks for taking this up!
Overall this series looks good to me, but from what I faintly
recollect, doesn't this (and the Krait pmu code) get affected by
powercollapse issues anymore?
e.g.
https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/arch/arm/kernel/perf_event_msm.c?h=msm-3.4&id=b5ca687960f0fea2f4735e83ca5c9543474c19de
Thanks,
Ashwin.
>
> [1]
> https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
>
> Cc: Neil Leeder
> Cc: Ashwin Chaugule
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/pmu.txt | 2 +
> arch/arm/kernel/perf_event_cpu.c | 2 +
> arch/arm/kernel/perf_event_v7.c | 395
> ++
> 3 files changed, 399 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
> b/Documentation/devicetree/bindings/arm/pmu.txt
> index 75ef91d08f3b..6e54a9d88b7a 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.txt
> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
> @@ -18,6 +18,8 @@ Required properties:
> "arm,arm11mpcore-pmu"
> "arm,arm1176-pmu"
> "arm,arm1136-pmu"
> + "qcom,scorpion-pmu"
> + "qcom,scorpion-mp-pmu"
> "qcom,krait-pmu"
> - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a
> per-cpu
> interrupt (PPI) then 1 interrupt should be specified.
> diff --git a/arch/arm/kernel/perf_event_cpu.c
> b/arch/arm/kernel/perf_event_cpu.c
> index dd9acc95ebc0..010ffd241434 100644
> --- a/arch/arm/kernel/perf_event_cpu.c
> +++ b/arch/arm/kernel/perf_event_cpu.c
> @@ -242,6 +242,8 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
> {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
> {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
> {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
> + {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
> + {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_pmu_init},
> {.compatible = "qcom,krait-pmu",.data = krait_pmu_init},
> {},
> };
> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index 84a3ec3bc592..14bc8726f554 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -140,6 +140,23 @@ enum krait_perf_types {
> KRAIT_PERFCTR_L1_DTLB_ACCESS= 0x12210,
> };
>
> +/* ARMv7 Scorpion specific event types */
> +enum scorpion_perf_types {
> + SCORPION_LPM0_GROUP0= 0x4c,
> + SCORPION_LPM1_GROUP0= 0x50,
> + SCORPION_LPM2_GROUP0= 0x54,
> + SCORPION_L2LPM_GROUP0 = 0x58,
> + SCORPION_VLPM_GROUP0= 0x5c,
> +
> + SCORPION_ICACHE_ACCESS = 0x10053,
> + SCORPION_ICACHE_MISS= 0x10052,
> +
> + SCORPION_DTLB_ACCESS= 0x12013,
> + SCORPION_DTLB_MISS = 0x12012,
> +
> + SCORPION_ITLB_MISS = 0x12021,
> +};
> +
> /*
> * Cortex-A8 HW events mapping
> *
> @@ -482,6 +499,51 @@ static const unsigned
> krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> };
>
> /*
> + * Scorpion HW events mapping
> + */
> +static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
> + PERF_MAP_ALL_UNSUPPORTED,
> + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
> + [PERF_COUNT_HW_INSTRUCTIONS]= ARMV7_PERFCTR_INSTR_EXECUTED,
> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
> + [PERF_COUNT_HW_BRANCH_MISSES] =
> ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
> + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
> +};
> +
> +static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> +
[PATCH 2/2] ARM: perf: Add support for Scorpion PMUs
Scorpion supports a set of local performance monitor event
selection registers (LPM) sitting behind a cp15 based interface
that extend the architected PMU events to include Scorpion CPU
and Venum VFP specific events. To use these events the user is
expected to program the lpm register with the event code shifted
into the group they care about and then point the PMNx event at
that region+group combo by writing a LPMn_GROUPx event. Add
support for this hardware.
Note: the raw event number is a pure software construct that
allows us to map the multi-dimensional number space of regions,
groups, and event codes into a flat event number space suitable
for use by the perf framework.
This is based on code originally written by Ashwin Chaugule and
Neil Leeder [1] massed to become similar to the Krait PMU support
code.
[1]
https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm.c?h=msm-3.4
Cc: Neil Leeder
Cc: Ashwin Chaugule
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/pmu.txt | 2 +
arch/arm/kernel/perf_event_cpu.c | 2 +
arch/arm/kernel/perf_event_v7.c | 395 ++
3 files changed, 399 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
b/Documentation/devicetree/bindings/arm/pmu.txt
index 75ef91d08f3b..6e54a9d88b7a 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -18,6 +18,8 @@ Required properties:
"arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
+ "qcom,scorpion-pmu"
+ "qcom,scorpion-mp-pmu"
"qcom,krait-pmu"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a
per-cpu
interrupt (PPI) then 1 interrupt should be specified.
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index dd9acc95ebc0..010ffd241434 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -242,6 +242,8 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
+ {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
+ {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_pmu_init},
{.compatible = "qcom,krait-pmu",.data = krait_pmu_init},
{},
};
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 84a3ec3bc592..14bc8726f554 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -140,6 +140,23 @@ enum krait_perf_types {
KRAIT_PERFCTR_L1_DTLB_ACCESS= 0x12210,
};
+/* ARMv7 Scorpion specific event types */
+enum scorpion_perf_types {
+ SCORPION_LPM0_GROUP0= 0x4c,
+ SCORPION_LPM1_GROUP0= 0x50,
+ SCORPION_LPM2_GROUP0= 0x54,
+ SCORPION_L2LPM_GROUP0 = 0x58,
+ SCORPION_VLPM_GROUP0= 0x5c,
+
+ SCORPION_ICACHE_ACCESS = 0x10053,
+ SCORPION_ICACHE_MISS= 0x10052,
+
+ SCORPION_DTLB_ACCESS= 0x12013,
+ SCORPION_DTLB_MISS = 0x12012,
+
+ SCORPION_ITLB_MISS = 0x12021,
+};
+
/*
* Cortex-A8 HW events mapping
*
@@ -482,6 +499,51 @@ static const unsigned
krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
};
/*
+ * Scorpion HW events mapping
+ */
+static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
+ PERF_MAP_ALL_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS]= ARMV7_PERFCTR_INSTR_EXECUTED,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ PERF_CACHE_MAP_ALL_UNSUPPORTED,
+ /*
+* The performance counters don't differentiate between read and write
+* accesses/misses so this isn't strictly correct, but it's the best we
+* can do. Writes and reads get combined.
+*/
+ [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)
