Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register
On Fri, Nov 20, 2015 at 09:06:33AM -0600, Felipe Balbi wrote:
>
> Hi,
>
> Andy Gross writes:
> > This patch adds automatic configuration of the TCSR phy mux register based
> > on
> > the syscon-tcsr devicetree entry. This configuration is optional, as some
> > platforms may not require the mux selection.
> >
> > Signed-off-by: Andy Gross
>
> just when I find a way to make a generic dwc3-of-simple.c glue layer :-p
>
> I can, certainly drop my patches but I need more details on the syscon
> usage below.
>
> > ---
> > drivers/usb/dwc3/dwc3-qcom.c | 25 +
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> > index 0880260..fcf264c 100644
> > --- a/drivers/usb/dwc3/dwc3-qcom.c
> > +++ b/drivers/usb/dwc3/dwc3-qcom.c
> > @@ -17,6 +17,8 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> >
> > struct dwc3_qcom {
> > struct device *dev;
> > @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> > {
> > struct device_node *node = pdev->dev.of_node;
> > struct dwc3_qcom *qdwc;
> > + struct regmap *regmap;
> > + u32 mux_offset;
> > + u32 mux_bit;
> > int ret;
> >
> > qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> > @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> > qdwc->sleep_clk = NULL;
> > }
> >
> > + /* look for tcsr and if present, provision it */
> > + regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
> > + if (!IS_ERR(regmap)) {
> > + if (of_property_read_u32_index(node, "syscon-tcsr", 1,
> > + &mux_offset)) {
> > + dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
> > + return -EINVAL;
> > + }
> > + if (of_property_read_u32_index(node, "syscon-tcsr", 2,
> > + &mux_bit)) {
> > + dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
> > + BIT(mux_bit));
>
> what is tcsr and what does it ? It also seems to be optional, why's that ?
>
> --
> balbi
The syscon is to set the mux selection for the phys. Our hardware has a
steering mux between hsic and dwc3 and setting this to 1 steers the phys to the
right controller.
It is optional because not all platforms appear to have this stupidity.
--
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a Linux Foundation Collaborative Project
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Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register
Hi,
Andy Gross writes:
> This patch adds automatic configuration of the TCSR phy mux register based on
> the syscon-tcsr devicetree entry. This configuration is optional, as some
> platforms may not require the mux selection.
>
> Signed-off-by: Andy Gross
just when I find a way to make a generic dwc3-of-simple.c glue layer :-p
I can, certainly drop my patches but I need more details on the syscon
usage below.
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 0880260..fcf264c 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -17,6 +17,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> struct dwc3_qcom {
> struct device *dev;
> @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> {
> struct device_node *node = pdev->dev.of_node;
> struct dwc3_qcom *qdwc;
> + struct regmap *regmap;
> + u32 mux_offset;
> + u32 mux_bit;
> int ret;
>
> qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> qdwc->sleep_clk = NULL;
> }
>
> + /* look for tcsr and if present, provision it */
> + regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
> + if (!IS_ERR(regmap)) {
> + if (of_property_read_u32_index(node, "syscon-tcsr", 1,
> +&mux_offset)) {
> + dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
> + return -EINVAL;
> + }
> + if (of_property_read_u32_index(node, "syscon-tcsr", 2,
> +&mux_bit)) {
> + dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
> + return -EINVAL;
> + }
> +
> + regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
> +BIT(mux_bit));
what is tcsr and what does it ? It also seems to be optional, why's that ?
--
balbi
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Description: PGP signature
[PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register
This patch adds automatic configuration of the TCSR phy mux register based on
the syscon-tcsr devicetree entry. This configuration is optional, as some
platforms may not require the mux selection.
Signed-off-by: Andy Gross
---
drivers/usb/dwc3/dwc3-qcom.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 0880260..fcf264c 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
struct dwc3_qcom {
struct device *dev;
@@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct dwc3_qcom *qdwc;
+ struct regmap *regmap;
+ u32 mux_offset;
+ u32 mux_bit;
int ret;
qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
@@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
qdwc->sleep_clk = NULL;
}
+ /* look for tcsr and if present, provision it */
+ regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+ if (!IS_ERR(regmap)) {
+ if (of_property_read_u32_index(node, "syscon-tcsr", 1,
+ &mux_offset)) {
+ dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
+ return -EINVAL;
+ }
+ if (of_property_read_u32_index(node, "syscon-tcsr", 2,
+ &mux_bit)) {
+ dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
+ BIT(mux_bit));
+ } else {
+ dev_info(qdwc->dev, "missing syscon tcsr entry\n");
+ }
+
ret = clk_prepare_enable(qdwc->core_clk);
if (ret) {
dev_err(qdwc->dev, "failed to enable core clock\n");
--
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hosted by The Linux Foundation
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