Re: [PATCH 3/4][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
On Tue, Jul 7, 2015 at 2:17 PM, Adrian Alonso aalo...@freescale.com wrote:
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
Acked-by: frank...@freescale.com
- Change from v1 to v2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
- Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr
base register address.
---
drivers/pinctrl/freescale/pinctrl-imx.c | 72
++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..aef4ca3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -38,7 +38,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base +
pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC
general
* purpose register, not regular select input
register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at
offset
* 0, and we only print register value for regular
case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with
normal iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct
pinctrl_dev *pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct
pinctrl_dev *pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+
[PATCH 3/4][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides
low power state rentetion capabilities on gpios that are part of
iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to
properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by: Adrian Alonso aalo...@freescale.com
- Change from v1 to v2:
- Add suggested comment for input select register shared between
iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to
16 bit representation.
- Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr
base register address.
---
drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++---
drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++-
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba..aef4ca3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,7 +1,7 @@
/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng dong.aish...@linaro.org
@@ -38,7 +38,6 @@
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- void __iomem *base;
const struct imx_pinctrl_soc_info *info;
};
@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
if (info-flags SHARE_MUX_CONF_REG) {
u32 reg;
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= (pin-mux_mode 20);
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
} else {
- writel(pin-mux_mode, ipctl-base + pin_reg-mux_reg);
+ writel(pin-mux_mode, pin_reg-base + pin_reg-mux_reg);
}
dev_dbg(ipctl-dev, write: offset 0x%x val 0x%x\n,
pin_reg-mux_reg, pin-mux_mode);
@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl-base + pin-input_reg);
+ val = readl(pin_reg-base + pin-input_reg);
val = ~mask;
val |= select shift;
- writel(val, ipctl-base + pin-input_reg);
+ writel(val, pin_reg-base + pin-input_reg);
} else if (pin-input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin-input_val, ipctl-base + pin-input_reg);
+ if (info-flags IOMUXC_LPSR_SUPPORT
+ IOMUXC_LPSR_MASK(pin-input_val))
+ /* iomuxc-lpsr select input register shared with normal
iomuxc */
+ writel(pin-input_val, info-base +
pin-input_reg);
+ else
+ writel(pin-input_val, pin_reg-base +
pin-input_reg);
+
dev_dbg(ipctl-dev,
==select_input: offset 0x%x val 0x%x\n,
pin-input_reg, pin-input_val);
@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev,
return -EINVAL;
mux_pin:
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
reg = ~(0x7 20);
reg |= imx_pin-config;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base + pin_reg-mux_reg);
return 0;
}
@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
return -EINVAL;
/* IBE always enabled allows us to read the value on the wire */
- reg = readl(ipctl-base + pin_reg-mux_reg);
+ reg = readl(pin_reg-base + pin_reg-mux_reg);
if (input)
reg = ~0x2;
else
reg |= 0x2;
- writel(reg, ipctl-base + pin_reg-mux_reg);
+ writel(reg, pin_reg-base +
