Re: [PATCH v2 4/6] clk: mediatek: Add MT2701 clock support
Hi Philipp,
On Tue, 2016-01-05 at 10:30 +0100, Philipp Zabel wrote:
> Hi James,
>
> Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao:
> > From: Shunli Wang
> >
> > Add MT2701 clock support, include topckgen, apmixedsys,
> > infracfg, pericfg and subsystem clocks.
> >
> > Signed-off-by: Shunli Wang
> > Signed-off-by: James Liao
> > ---
> > drivers/clk/mediatek/Kconfig |8 +
> > drivers/clk/mediatek/Makefile |1 +
> > drivers/clk/mediatek/clk-gate.c | 56 ++
> > drivers/clk/mediatek/clk-gate.h |2 +
> > drivers/clk/mediatek/clk-mt2701.c | 1210
> > +
> > drivers/clk/mediatek/clk-mtk.c| 25 +
> > drivers/clk/mediatek/clk-mtk.h| 35 +-
> > 7 files changed, 1334 insertions(+), 3 deletions(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt2701.c
> >
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index dc224e6..6c7cdc0 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
> > ---help---
> > Mediatek SoCs' clock support.
> >
> > +config COMMON_CLK_MT2701
> > + bool "Clock driver for Mediatek MT2701 and MT7623"
> > + depends on COMMON_CLK
> > + select COMMON_CLK_MEDIATEK
> > + default ARCH_MEDIATEK
> > + ---help---
> > + This driver supports Mediatek MT2701 and MT7623 clocks.
> > +
> > config COMMON_CLK_MT8135
> > bool "Clock driver for Mediatek MT8135"
> > depends on COMMON_CLK
> > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> > index 32e7222..5b2b91b 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -1,4 +1,5 @@
> > obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o
> > clk-apmixed.o
> > obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> > +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
> > obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
> > obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
> > diff --git a/drivers/clk/mediatek/clk-gate.c
> > b/drivers/clk/mediatek/clk-gate.c
> > index 576bdb7..38badb4 100644
> > --- a/drivers/clk/mediatek/clk-gate.c
> > +++ b/drivers/clk/mediatek/clk-gate.c
> > @@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
> > regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
> > }
> >
> > +static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_gate *cg = to_clk_gate(hw);
> > + u32 val;
> > +
> > + regmap_read(cg->regmap, cg->sta_ofs, &val);
> > + val |= BIT(cg->bit);
> > + regmap_write(cg->regmap, cg->sta_ofs, val);
>
> You can use regmap_update_bits here:
>
> u32 bit = BIT(cg->bit);
> regmap_update_bits(cg->regmap, cg->sta_ofs, bit, bit);
>
> > +}
> > +
> > +static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_gate *cg = to_clk_gate(hw);
> > + u32 val;
> > +
> > + regmap_read(cg->regmap, cg->sta_ofs, &val);
> > + val &= ~(BIT(cg->bit));
> > + regmap_write(cg->regmap, cg->sta_ofs, val);
>
> and here:
>
> u32 bit = BIT(cg->bit);
> regmap_update_bits(cg->regmap, cg->sta_ofs, bit, 0);
OK. I'll change it in next patch. Thanks.
Best regards,
James
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] clk: mediatek: Add MT2701 clock support
Hi James,
Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao:
> From: Shunli Wang
>
> Add MT2701 clock support, include topckgen, apmixedsys,
> infracfg, pericfg and subsystem clocks.
>
> Signed-off-by: Shunli Wang
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/Kconfig |8 +
> drivers/clk/mediatek/Makefile |1 +
> drivers/clk/mediatek/clk-gate.c | 56 ++
> drivers/clk/mediatek/clk-gate.h |2 +
> drivers/clk/mediatek/clk-mt2701.c | 1210
> +
> drivers/clk/mediatek/clk-mtk.c| 25 +
> drivers/clk/mediatek/clk-mtk.h| 35 +-
> 7 files changed, 1334 insertions(+), 3 deletions(-)
> create mode 100644 drivers/clk/mediatek/clk-mt2701.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index dc224e6..6c7cdc0 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
> ---help---
> Mediatek SoCs' clock support.
>
> +config COMMON_CLK_MT2701
> + bool "Clock driver for Mediatek MT2701 and MT7623"
> + depends on COMMON_CLK
> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK
> + ---help---
> + This driver supports Mediatek MT2701 and MT7623 clocks.
> +
> config COMMON_CLK_MT8135
> bool "Clock driver for Mediatek MT8135"
> depends on COMMON_CLK
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 32e7222..5b2b91b 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,4 +1,5 @@
> obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o
> clk-apmixed.o
> obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
> obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 576bdb7..38badb4 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
> regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
> }
>
> +static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_gate *cg = to_clk_gate(hw);
> + u32 val;
> +
> + regmap_read(cg->regmap, cg->sta_ofs, &val);
> + val |= BIT(cg->bit);
> + regmap_write(cg->regmap, cg->sta_ofs, val);
You can use regmap_update_bits here:
u32 bit = BIT(cg->bit);
regmap_update_bits(cg->regmap, cg->sta_ofs, bit, bit);
> +}
> +
> +static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_gate *cg = to_clk_gate(hw);
> + u32 val;
> +
> + regmap_read(cg->regmap, cg->sta_ofs, &val);
> + val &= ~(BIT(cg->bit));
> + regmap_write(cg->regmap, cg->sta_ofs, val);
and here:
u32 bit = BIT(cg->bit);
regmap_update_bits(cg->regmap, cg->sta_ofs, bit, 0);
best regards
Philipp
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/6] clk: mediatek: Add MT2701 clock support
From: Shunli Wang
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
---
drivers/clk/mediatek/Kconfig |8 +
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-gate.c | 56 ++
drivers/clk/mediatek/clk-gate.h |2 +
drivers/clk/mediatek/clk-mt2701.c | 1210 +
drivers/clk/mediatek/clk-mtk.c| 25 +
drivers/clk/mediatek/clk-mtk.h| 35 +-
7 files changed, 1334 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/mediatek/clk-mt2701.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..6c7cdc0 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
---help---
Mediatek SoCs' clock support.
+config COMMON_CLK_MT2701
+ bool "Clock driver for Mediatek MT2701 and MT7623"
+ depends on COMMON_CLK
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ ---help---
+ This driver supports Mediatek MT2701 and MT7623 clocks.
+
config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..5b2b91b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o
clk-apmixed.o
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 576bdb7..38badb4 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
}
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_clk_gate(hw);
+ u32 val;
+
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ val |= BIT(cg->bit);
+ regmap_write(cg->regmap, cg->sta_ofs, val);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_clk_gate(hw);
+ u32 val;
+
+ regmap_read(cg->regmap, cg->sta_ofs, &val);
+ val &= ~(BIT(cg->bit));
+ regmap_write(cg->regmap, cg->sta_ofs, val);
+}
+
static int mtk_cg_enable(struct clk_hw *hw)
{
mtk_cg_clr_bit(hw);
@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
mtk_cg_clr_bit(hw);
}
+static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+
+ return 0;
+}
+
+static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+}
+
+static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+
+ return 0;
+}
+
+static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+}
+
const struct clk_ops mtk_clk_gate_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable,
@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.disable= mtk_cg_disable_inv,
};
+const struct clk_ops mtk_clk_gate_ops_no_setclr = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_enable_no_setclr,
+ .disable= mtk_cg_disable_no_setclr,
+};
+
+const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
+ .is_enabled = mtk_cg_bit_is_set,
+ .enable = mtk_cg_enable_inv_no_setclr,
+ .disable= mtk_cg_disable_inv_no_setclr,
+};
+
struct clk * __init mtk_clk_register_gate(
const char *name,
const char *parent_name,
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 11e25c9..7f7ef34 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw
*hw)
extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
struct clk *mtk_clk_register_gate(
const char *name,
diff --git a/drivers/clk/mediatek/clk-mt2701.c
b/drivers/clk/mediatek/clk-mt2701.c
new file mode 100644
index 000..2f521f4
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -0,0 +1,1210 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the G
