Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support
On Wed, Sep 30, 2015 at 06:32:01PM +0100, Mark Rutland wrote: > On Wed, Sep 30, 2015 at 02:51:26PM +0100, Ivan T. Ivanov wrote: > > > > On Wed, 2015-09-30 at 14:29 +0100, Mark Rutland wrote: > > > On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote: > > > > Add transmit DMA support for UARTDM type of controllers. > > > > > > > > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine > > > > and APQ8016, which have UARTDM v1.4 and BAM DMA engine. > > > > > > > > Signed-off-by: Ivan T. Ivanov iva...@linaro.org> > > > > --- > > > > .../devicetree/bindings/serial/qcom,msm-uartdm.txt | 3 + > > > > drivers/tty/serial/msm_serial.c| 312 > > > > +++-- > > > > drivers/tty/serial/msm_serial.h| 3 + > > > > 3 files changed, 294 insertions(+), 24 deletions(-) > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > > index a2114c217376..a600023d9ec1 100644 > > > > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > > @@ -26,6 +26,9 @@ Required properties: > > > > Optional properties: > > > > - dmas: Should contain dma specifiers for transmit and receive channels > > > > - dma-names: Should contain "tx" for transmit and "rx" for receive > > > > channels > > > > +- qcom,tx-crci: Identificator for Client Rate Control Interface > > > > to be > > > > + used with TX DMA channel. Required when using DMA for > > > > transmission > > > > + with UARTDM v1.3 and bellow. > > > > > > This sounds like it belongs in the dma-specifier, and dealt with by the > > > DMA controller driver. > > > > > > Why does the UART driver need to know about this? > > > > CRCI information was part of the first version of ADM DMA engine driver > > bindings, but Andy remove it because some client devices are requiring > > more that one CRCI number. See here[1] and here [2]. > > > > Regards, > > Ivan > > > > [1] > > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314190.html > > [2] https://lkml.org/lkml/2015/8/19/19 > > This leaves me more confused. If different writes from the same agent > are being distinguished then it sounds like you actually have two > logical DMA channels. > > Could you elaborate on the qcom,ebi2-nand binding? From a brief read I'd > expect you to have "txrx" and "cmd" dmas, rather than describing the > CRCI information on the side. The ADM does have physical channels, but when you utilize those channels you may also need to describe the flow control used for specific transactions. And this flow control has to be configured for that specific transaction, if you are interleaving different flow control origination/end points. In the case of nand, they actually use different flow controls on the same physical channel. For UART/I2C/SPI, they use just one flow control identifier. I see your point at specifying these as logical channels. That is certainly a possibility. Then the ADM driver would just have to handle the logical channel allocation. That would remove the need for the slave_config being sent. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support
On Wed, Sep 30, 2015 at 02:51:26PM +0100, Ivan T. Ivanov wrote: > > On Wed, 2015-09-30 at 14:29 +0100, Mark Rutland wrote: > > On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote: > > > Add transmit DMA support for UARTDM type of controllers. > > > > > > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine > > > and APQ8016, which have UARTDM v1.4 and BAM DMA engine. > > > > > > Signed-off-by: Ivan T. Ivanov iva...@linaro.org> > > > --- > > > .../devicetree/bindings/serial/qcom,msm-uartdm.txt | 3 + > > > drivers/tty/serial/msm_serial.c| 312 > > > +++-- > > > drivers/tty/serial/msm_serial.h| 3 + > > > 3 files changed, 294 insertions(+), 24 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > index a2114c217376..a600023d9ec1 100644 > > > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > > @@ -26,6 +26,9 @@ Required properties: > > > Optional properties: > > > - dmas: Should contain dma specifiers for transmit and receive channels > > > - dma-names: Should contain "tx" for transmit and "rx" for receive > > > channels > > > +- qcom,tx-crci: Identificator for Client Rate Control Interface to > > > be > > > + used with TX DMA channel. Required when using DMA for > > > transmission > > > + with UARTDM v1.3 and bellow. > > > > This sounds like it belongs in the dma-specifier, and dealt with by the > > DMA controller driver. > > > > Why does the UART driver need to know about this? > > CRCI information was part of the first version of ADM DMA engine driver > bindings, but Andy remove it because some client devices are requiring > more that one CRCI number. See here[1] and here [2]. > > Regards, > Ivan > > [1] > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314190.html > [2] https://lkml.org/lkml/2015/8/19/19 This leaves me more confused. If different writes from the same agent are being distinguished then it sounds like you actually have two logical DMA channels. Could you elaborate on the qcom,ebi2-nand binding? From a brief read I'd expect you to have "txrx" and "cmd" dmas, rather than describing the CRCI information on the side. Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support
On Wed, 2015-09-30 at 14:29 +0100, Mark Rutland wrote: > On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote: > > Add transmit DMA support for UARTDM type of controllers. > > > > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine > > and APQ8016, which have UARTDM v1.4 and BAM DMA engine. > > > > Signed-off-by: Ivan T. Ivanov iva...@linaro.org> > > --- > > .../devicetree/bindings/serial/qcom,msm-uartdm.txt | 3 + > > drivers/tty/serial/msm_serial.c| 312 > > +++-- > > drivers/tty/serial/msm_serial.h| 3 + > > 3 files changed, 294 insertions(+), 24 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > index a2114c217376..a600023d9ec1 100644 > > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > > @@ -26,6 +26,9 @@ Required properties: > > Optional properties: > > - dmas: Should contain dma specifiers for transmit and receive channels > > - dma-names: Should contain "tx" for transmit and "rx" for receive channels > > +- qcom,tx-crci: Identificator for Client Rate Control Interface to be > > + used with TX DMA channel. Required when using DMA for > > transmission > > + with UARTDM v1.3 and bellow. > > This sounds like it belongs in the dma-specifier, and dealt with by the > DMA controller driver. > > Why does the UART driver need to know about this? CRCI information was part of the first version of ADM DMA engine driver bindings, but Andy remove it because some client devices are requiring more that one CRCI number. See here[1] and here [2]. Regards, Ivan [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314190.html [2] https://lkml.org/lkml/2015/8/19/19 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support
On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote: > Add transmit DMA support for UARTDM type of controllers. > > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine > and APQ8016, which have UARTDM v1.4 and BAM DMA engine. > > Signed-off-by: Ivan T. Ivanov > --- > .../devicetree/bindings/serial/qcom,msm-uartdm.txt | 3 + > drivers/tty/serial/msm_serial.c| 312 > +++-- > drivers/tty/serial/msm_serial.h| 3 + > 3 files changed, 294 insertions(+), 24 deletions(-) > > diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > index a2114c217376..a600023d9ec1 100644 > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt > @@ -26,6 +26,9 @@ Required properties: > Optional properties: > - dmas: Should contain dma specifiers for transmit and receive channels > - dma-names: Should contain "tx" for transmit and "rx" for receive channels > +- qcom,tx-crci: Identificator for Client Rate Control Interface to be > + used with TX DMA channel. Required when using DMA for transmission > + with UARTDM v1.3 and bellow. This sounds like it belongs in the dma-specifier, and dealt with by the DMA controller driver. Why does the UART driver need to know about this? Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/6] tty: serial: msm: Add TX DMA support
Add transmit DMA support for UARTDM type of controllers.
Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
and APQ8016, which have UARTDM v1.4 and BAM DMA engine.
Signed-off-by: Ivan T. Ivanov
---
.../devicetree/bindings/serial/qcom,msm-uartdm.txt | 3 +
drivers/tty/serial/msm_serial.c| 312 +++--
drivers/tty/serial/msm_serial.h| 3 +
3 files changed, 294 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a2114c217376..a600023d9ec1 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,9 @@ Required properties:
Optional properties:
- dmas: Should contain dma specifiers for transmit and receive channels
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator for Client Rate Control Interface to be
+ used with TX DMA channel. Required when using DMA for transmission
+ with UARTDM v1.3 and bellow.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index e33966280606..2f395f5d78d0 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -20,6 +20,8 @@
#endif
#include
+#include
+#include
#include
#include
#include
@@ -39,6 +41,10 @@
#include "msm_serial.h"
+#define UARTDM_BURST_SIZE 16 /* in bytes */
+#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
+#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
+
enum {
UARTDM_1P1 = 1,
UARTDM_1P2,
@@ -46,6 +52,17 @@ enum {
UARTDM_1P4,
};
+struct msm_dma {
+ struct dma_chan *chan;
+ enum dma_data_direction dir;
+ dma_addr_t phys;
+ unsigned char *virt;
+ dma_cookie_tcookie;
+ u32 enable_bit;
+ unsigned intcount;
+ struct dma_async_tx_descriptor *desc;
+};
+
struct msm_port {
struct uart_portuart;
charname[16];
@@ -55,8 +72,93 @@ struct msm_port {
int is_uartdm;
unsigned intold_snap_state;
boolbreak_detected;
+ struct msm_dma tx_dma;
};
+static void msm_handle_tx(struct uart_port *port);
+
+void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
+{
+ struct device *dev = port->dev;
+ unsigned int mapped;
+ u32 val;
+
+ mapped = dma->count;
+ dma->count = 0;
+
+ dmaengine_terminate_all(dma->chan);
+
+ /*
+* DMA Stall happens if enqueue and flush command happens concurrently.
+* For example before changing the baud rate/protocol configuration and
+* sending flush command to ADM, disable the channel of UARTDM.
+* Note: should not reset the receiver here immediately as it is not
+* suggested to do disable/reset or reset/disable at the same time.
+*/
+ val = msm_read(port, UARTDM_DMEN);
+ val &= ~dma->enable_bit;
+ msm_write(port, val, UARTDM_DMEN);
+
+ if (mapped)
+ dma_unmap_single(dev, dma->phys, mapped, dma->dir);
+}
+
+static void msm_release_dma(struct msm_port *msm_port)
+{
+ struct msm_dma *dma;
+
+ dma = &msm_port->tx_dma;
+ if (dma->chan) {
+ msm_stop_dma(&msm_port->uart, dma);
+ dma_release_channel(dma->chan);
+ }
+
+ memset(dma, 0, sizeof(*dma));
+}
+
+static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
+{
+ struct device *dev = msm_port->uart.dev;
+ struct dma_slave_config conf;
+ struct msm_dma *dma;
+ u32 crci = 0;
+ int ret;
+
+ dma = &msm_port->tx_dma;
+
+ /* allocate DMA resources, if available */
+ dma->chan = dma_request_slave_channel_reason(dev, "tx");
+ if (IS_ERR(dma->chan))
+ goto no_tx;
+
+ of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
+
+ memset(&conf, 0, sizeof(conf));
+ conf.direction = DMA_MEM_TO_DEV;
+ conf.device_fc = true;
+ conf.dst_addr = base + UARTDM_TF;
+ conf.dst_maxburst = UARTDM_BURST_SIZE;
+ conf.slave_id = crci;
+
+ ret = dmaengine_slave_config(dma->chan, &conf);
+ if (ret)
+ goto rel_tx;
+
+ dma->dir = DMA_TO_DEVICE;
+
+ if (msm_port->is_uartdm < UARTDM_1P4)
+ dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
+ else
+ dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
+
+ return;
+
+rel_tx:
+ dma_release_channel(dma->c
