Re: [PATCH v3 02/10] clk: cygnus: Convert all macros to all caps

[Stephen Boyd]

On 10/15, Jon Mason wrote:
> The macros that are being used to initialize the values of the clk
> structures should be all caps.  Find and replace all of them with their
> relevant counterparts.
> 
> Signed-off-by: Jon Mason 
> ---

Applied to clk-next

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[PATCH v3 02/10] clk: cygnus: Convert all macros to all caps

[Jon Mason]

The macros that are being used to initialize the values of the clk
structures should be all caps.  Find and replace all of them with their
relevant counterparts.

Signed-off-by: Jon Mason 
---
 drivers/clk/bcm/clk-cygnus.c | 146 +--
 1 file changed, 73 insertions(+), 73 deletions(-)

diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index 316c603..aac82c6 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -23,28 +23,28 @@
 #include 
 #include "clk-iproc.h"
 
-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
 
-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
.pwr_shift = ps, .iso_shift = is }
 
-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
 
-#define asiu_div_val(o, es, hs, hw, ls, lw) \
+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
{ .offset = o, .en_shift = es, .high_shift = hs, \
.high_width = hw, .low_shift = ls, .low_width = lw }
 
-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
.reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
.ka_width = kaw }
 
-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
 
-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
 
-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
 
 static void __init cygnus_armpll_init(struct device_node *node)
 {
@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", 
cygnus_armpll_init);
 static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
-   .aon = aon_val(0x0, 2, 1, 0),
-   .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
-   .sw_ctrl = sw_ctrl_val(0x10, 31),
-   .ndiv_int = reg_val(0x10, 20, 10),
-   .ndiv_frac = reg_val(0x10, 0, 20),
-   .pdiv = reg_val(0x14, 0, 4),
-   .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
-   .status = reg_val(0x28, 12, 1),
+   .aon = AON_VAL(0x0, 2, 1, 0),
+   .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+   .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+   .ndiv_int = REG_VAL(0x10, 20, 10),
+   .ndiv_frac = REG_VAL(0x10, 0, 20),
+   .pdiv = REG_VAL(0x14, 0, 4),
+   .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
+   .status = REG_VAL(0x28, 12, 1),
 };
 
 static const struct iproc_clk_ctrl genpll_clk[] = {
[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
.flags = IPROC_CLK_AON,
-   .enable = enable_val(0x4, 6, 0, 12),
-   .mdiv = reg_val(0x20, 0, 8),
+   .enable = ENABLE_VAL(0x4, 6, 0, 12),
+   .mdiv = REG_VAL(0x20, 0, 8),
},
[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
.flags = IPROC_CLK_AON,
-   .enable = enable_val(0x4, 7, 1, 13),
-   .mdiv = reg_val(0x20, 10, 8),
+   .enable = ENABLE_VAL(0x4, 7, 1, 13),
+   .mdiv = REG_VAL(0x20, 10, 8),
},
[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
.flags = IPROC_CLK_AON,
-   .enable = enable_val(0x4, 8, 2, 14),
-   .mdiv = reg_val(0x20, 20, 8),
+   .enable = ENABLE_VAL(0x4, 8, 2, 14),
+   .mdiv = REG_VAL(0x20, 20, 8),
},
[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
.flags = IPROC_CLK_AON,
-   .enable = enable_val(0x4, 9, 3, 15),
-   .mdiv = reg_val(0x24, 0, 8),
+   .enable = ENABLE_VAL(0x4, 9, 3, 15),
+   .mdiv = REG_VAL(0x24, 0, 8),
},
[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
.flags = IPROC_CLK_AON,
-   .enable = enable_val(0x4, 10, 4, 16),
-   .mdiv = reg_val(0x24, 10, 8),
+   .enable = ENABLE_VAL(0x4, 10, 4, 16),
+   .mdiv = REG_VAL(0x24, 10, 8),
},
[BCM_CYGNUS_GENPLL_CAN_CLK] = {
.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
.flags = IPROC_CLK_AON,
-