Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

2015-08-04 Thread Archit Taneja 



On 8/4/2015 1:05 AM, Andy Gross wrote:

On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:

Enable the NAND controller node on the AP148 platform. Provide pinmux
information.

Cc: devicetree@vger.kernel.org

Signed-off-by: Archit Taneja 
---
  arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 
  1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..2e88eff 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio34", "gpio35", "gpio36",
+  "gpio37", "gpio38", "gpio39",
+  "gpio40", "gpio41", "gpio42",
+  "gpio43", "gpio44", "gpio45",
+  "gpio46", "gpio47";
+   function = "nand";
+   drive-strength = <10>;
+   bias-disable;
+   };
+   pullups {
+   pins = "gpio39";
+   bias-pull-up;
+   };
+   hold {
+   pins = "gpio40", "gpio41", "gpio42",
+  "gpio43", "gpio44", "gpio45",
+  "gpio46", "gpio47";
+   bias-bus-hold;


Maybe split out the bias-disable into a separate set and remove that property
from the mux.


I'll fix this.

Thanks,
Archit

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Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

2015-08-04 Thread Archit Taneja 



On 8/4/2015 2:28 AM, Stephen Boyd wrote:

On 08/03, Archit Taneja wrote:

@@ -93,5 +115,19 @@
sata@2900 {
status = "ok";
};
+
+   nand@1ac0 {
+   status = "ok";
+
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+
+   nand-ecc-strength = <4>;
+   nand-bus-width = <8>;
+   };
};
  };
+
+&adm_dma {
+   status = "ok";
+};


I think the preference is to put the full path to the device in
the dts file and then have status = "ok". So please move this
into the soc node and give the correct offset, etc. like we've
done for other nodes.


I'll do that.

Archit

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Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

2015-08-03 Thread Stephen Boyd 
On 08/03, Archit Taneja wrote:
> @@ -93,5 +115,19 @@
>   sata@2900 {
>   status = "ok";
>   };
> +
> + nand@1ac0 {
> + status = "ok";
> +
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> +
> + nand-ecc-strength = <4>;
> + nand-bus-width = <8>;
> + };
>   };
>  };
> +
> +&adm_dma {
> + status = "ok";
> +};

I think the preference is to put the full path to the device in
the dts file and then have status = "ok". So please move this
into the soc node and give the correct offset, etc. like we've
done for other nodes.

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Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

2015-08-03 Thread Andy Gross 
On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
> 
> Cc: devicetree@vger.kernel.org
> 
> Signed-off-by: Archit Taneja 
> ---
>  arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 
> 
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
> b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> index 7f9ea50..2e88eff 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> @@ -30,6 +30,28 @@
>   bias-none;
>   };
>   };
> + nand_pins: nand_pins {
> + mux {
> + pins = "gpio34", "gpio35", "gpio36",
> +"gpio37", "gpio38", "gpio39",
> +"gpio40", "gpio41", "gpio42",
> +"gpio43", "gpio44", "gpio45",
> +"gpio46", "gpio47";
> + function = "nand";
> + drive-strength = <10>;
> + bias-disable;
> + };
> + pullups {
> + pins = "gpio39";
> + bias-pull-up;
> + };
> + hold {
> + pins = "gpio40", "gpio41", "gpio42",
> +"gpio43", "gpio44", "gpio45",
> +"gpio46", "gpio47";
> + bias-bus-hold;

Maybe split out the bias-disable into a separate set and remove that property
from the mux.

> + };
> + };
>   };
>  
>   gsbi@1630 {
> @@ -93,5 +115,19 @@
>   sata@2900 {
>   status = "ok";
>   };
> +
> + nand@1ac0 {
> + status = "ok";
> +
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> +
> + nand-ecc-strength = <4>;
> + nand-bus-width = <8>;
> + };
>   };
>  };
> +
> +&adm_dma {
> + status = "ok";
> +};
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 

-- 
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

2015-08-02 Thread Archit Taneja 
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.

Cc: devicetree@vger.kernel.org

Signed-off-by: Archit Taneja 
---
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..2e88eff 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio34", "gpio35", "gpio36",
+  "gpio37", "gpio38", "gpio39",
+  "gpio40", "gpio41", "gpio42",
+  "gpio43", "gpio44", "gpio45",
+  "gpio46", "gpio47";
+   function = "nand";
+   drive-strength = <10>;
+   bias-disable;
+   };
+   pullups {
+   pins = "gpio39";
+   bias-pull-up;
+   };
+   hold {
+   pins = "gpio40", "gpio41", "gpio42",
+  "gpio43", "gpio44", "gpio45",
+  "gpio46", "gpio47";
+   bias-bus-hold;
+   };
+   };
};
 
gsbi@1630 {
@@ -93,5 +115,19 @@
sata@2900 {
status = "ok";
};
+
+   nand@1ac0 {
+   status = "ok";
+
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+
+   nand-ecc-strength = <4>;
+   nand-bus-width = <8>;
+   };
};
 };
+
+&adm_dma {
+   status = "ok";
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

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