Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
Hi Mikeļ¼
I am sorry. I have to correct my answer about using CLK_OF_DECLARE.
On 2016/1/5 15:21, xuejiancheng wrote:
> Hi Mike,
>Happy new year to you!
>Thank you for taking time to reply.
>
> On 2015/12/31 8:23, Michael Turquette wrote:
>> Hello Jiancheng Xue,
>>
>> Quoting Jiancheng Xue (2015-12-29 17:43:47)
>>> The CRG(Clock and Reset Generator) block provides clock
>>> and reset signals for other modules in hi3519 soc.
>>>
>>> Signed-off-by: Jiancheng Xue
>>> ---
>>> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
>>> drivers/clk/hisilicon/Kconfig | 7 +
>>> drivers/clk/hisilicon/Makefile | 2 +
>>> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
>>> drivers/clk/hisilicon/reset.c | 149
>>> +
>>> drivers/clk/hisilicon/reset.h | 32 +
>>> include/dt-bindings/clock/hi3519-clock.h | 43 ++
>>> 7 files changed, 382 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
>>> create mode 100644 drivers/clk/hisilicon/reset.c
>>> create mode 100644 drivers/clk/hisilicon/reset.h
>>> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>>
>> Please keep Philipp Zabel Cc'd for reset-related patches. I've added
>> him to Cc.
>>
> OK.
>
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>> new file mode 100644
>>> index 000..2d23950
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>> @@ -0,0 +1,46 @@
>>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>>> +
>>> +The Hi3519 CRG module provides clock and reset signals to various
>>> +controllers within the SoC.
>>> +
>>> +This binding uses the following bindings:
>>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>>> +Documentation/devicetree/bindings/reset/reset.txt
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: should be one of the following.
>>> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>>> +
>>> +- reg: physical base address of the controller and length of memory mapped
>>> + region.
>>> +
>>> +- #clock-cells: should be 1.
>>> +
>>> +Each clock is assigned an identifier and client nodes use this identifier
>>> +to specify the clock which they consume.
>>> +
>>> +All these identifier could be found in .
>>> +
>>> +- #reset-cells: should be 2.
>>> +
>>> +A reset signal can be controlled by writing a bit register in the CRG
>>> module.
>>> +The reset specifier consists of two cells. The first cell represents the
>>> +register offset relative to the base address. The second cell represents
>>> the
>>> +bit index in the register.
>>> +
>>> +Example: CRG nodes
>>> +CRG: clock-reset-controller@1201 {
>>> + compatible = "hisilicon,hi3519-crg";
>>> +reg = <0x1201 0x1>;
>>> +#clock-cells = <1>;
>>> +#reset-cells = <2>;
>>> +};
>>> +
>>> +Example: consumer nodes
>>> +i2c0: i2c@1211 {
>>> + compatible = "hisilicon,hi3519-i2c";
>>> +reg = <0x1211 0x1000>;
>>> +clocks = <&CRG HI3519_I2C0_RST>;*/
>>> +resets = <&CRG 0xe4 0>;
>>> +};
>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>> index e434854..b6baebf 100644
>>> --- a/drivers/clk/hisilicon/Kconfig
>>> +++ b/drivers/clk/hisilicon/Kconfig
>>> @@ -1,3 +1,10 @@
>>> +config COMMON_CLK_HI3519
>>> + tristate "Clock Driver for Hi3519"
>>> + depends on ARCH_HISI
>>> + default y
>>> + help
>>> + Build the clock driver for hi3519.
>>> +
>>> config COMMON_CLK_HI6220
>>> bool "Hi6220 Clock Driver"
>>> depends on ARCH_HISI || COMPILE_TEST
>>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>>> index 74dba31..3f57b09 100644
>>> --- a/drivers/clk/hisilicon/Makefile
>>> +++ b/drivers/clk/hisilicon/Makefile
>>> @@ -4,8 +4,10 @@
>>>
>>> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>>>
>>> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
>>> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
>>> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
>>> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
>>> obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
>>> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
>>> +obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
>>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
>>> b/drivers/clk/hisilicon/clk-hi3519.c
>>> new file mode 100644
>>> index 000..e220234
>>> --- /dev/null
>>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>>> @@ -0,0 +1,103 @@
>>> +/*
>>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the te
Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
Hi Philipp,
Thank you very much for your quick reply.
On 2016/1/5 18:12, Philipp Zabel wrote:
> H Jiancheng,
>
> Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
>> The CRG(Clock and Reset Generator) block provides clock
>> and reset signals for other modules in hi3519 soc.
>>
>> Signed-off-by: Jiancheng Xue
>> ---
>> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
>> drivers/clk/hisilicon/Kconfig | 7 +
>> drivers/clk/hisilicon/Makefile | 2 +
>> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
>> drivers/clk/hisilicon/reset.c | 149
>> +
>> drivers/clk/hisilicon/reset.h | 32 +
>> include/dt-bindings/clock/hi3519-clock.h | 43 ++
>> 7 files changed, 382 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
>> create mode 100644 drivers/clk/hisilicon/reset.c
>> create mode 100644 drivers/clk/hisilicon/reset.h
>> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> new file mode 100644
>> index 000..2d23950
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>> +
>> +The Hi3519 CRG module provides clock and reset signals to various
>> +controllers within the SoC.
>> +
>> +This binding uses the following bindings:
>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +Documentation/devicetree/bindings/reset/reset.txt
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes use this identifier
>> +to specify the clock which they consume.
>> +
>> +All these identifier could be found in .
>> +
>> +- #reset-cells: should be 2.
>> +
>> +A reset signal can be controlled by writing a bit register in the CRG
>> module.
>> +The reset specifier consists of two cells. The first cell represents the
>> +register offset relative to the base address. The second cell represents the
>> +bit index in the register.
>
> Are the resets controlled by single bits spread around the register
> space? If so, I'm fine with this binding.
>
Yes, you are right.
>> +Example: CRG nodes
>> +CRG: clock-reset-controller@1201 {
>> +compatible = "hisilicon,hi3519-crg";
>> +reg = <0x1201 0x1>;
>> +#clock-cells = <1>;
>> +#reset-cells = <2>;
>> +};
>> +
>> +Example: consumer nodes
>> +i2c0: i2c@1211 {
>> +compatible = "hisilicon,hi3519-i2c";
>> +reg = <0x1211 0x1000>;
>> +clocks = <&CRG HI3519_I2C0_RST>;*/
>> +resets = <&CRG 0xe4 0>;
>> +};
>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>> index e434854..b6baebf 100644
>> --- a/drivers/clk/hisilicon/Kconfig
>> +++ b/drivers/clk/hisilicon/Kconfig
>> @@ -1,3 +1,10 @@
>> +config COMMON_CLK_HI3519
>> +tristate "Clock Driver for Hi3519"
>> +depends on ARCH_HISI
>> +default y
>> +help
>> + Build the clock driver for hi3519.
>> +
>> config COMMON_CLK_HI6220
>> bool "Hi6220 Clock Driver"
>> depends on ARCH_HISI || COMPILE_TEST
>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>> index 74dba31..3f57b09 100644
>> --- a/drivers/clk/hisilicon/Makefile
>> +++ b/drivers/clk/hisilicon/Makefile
>> @@ -4,8 +4,10 @@
>>
>> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>>
>> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
>> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
>> obj-$(CONFIG_ARCH_HIP04)+= clk-hip04.o
>> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
>> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
>> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
>> +obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
>> b/drivers/clk/hisilicon/clk-hi3519.c
>> new file mode 100644
>> index 000..e220234
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>> @@ -0,0 +1,103 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHO
Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
H Jiancheng,
Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
> The CRG(Clock and Reset Generator) block provides clock
> and reset signals for other modules in hi3519 soc.
>
> Signed-off-by: Jiancheng Xue
> ---
> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
> drivers/clk/hisilicon/Kconfig | 7 +
> drivers/clk/hisilicon/Makefile | 2 +
> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
> drivers/clk/hisilicon/reset.c | 149
> +
> drivers/clk/hisilicon/reset.h | 32 +
> include/dt-bindings/clock/hi3519-clock.h | 43 ++
> 7 files changed, 382 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
> create mode 100644 drivers/clk/hisilicon/reset.c
> create mode 100644 drivers/clk/hisilicon/reset.h
> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> new file mode 100644
> index 000..2d23950
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> @@ -0,0 +1,46 @@
> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
> +
> +The Hi3519 CRG module provides clock and reset signals to various
> +controllers within the SoC.
> +
> +This binding uses the following bindings:
> +Documentation/devicetree/bindings/clock/clock-bindings.txt
> +Documentation/devicetree/bindings/reset/reset.txt
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes use this identifier
> +to specify the clock which they consume.
> +
> +All these identifier could be found in .
> +
> +- #reset-cells: should be 2.
> +
> +A reset signal can be controlled by writing a bit register in the CRG module.
> +The reset specifier consists of two cells. The first cell represents the
> +register offset relative to the base address. The second cell represents the
> +bit index in the register.
Are the resets controlled by single bits spread around the register
space? If so, I'm fine with this binding.
> +Example: CRG nodes
> +CRG: clock-reset-controller@1201 {
> + compatible = "hisilicon,hi3519-crg";
> +reg = <0x1201 0x1>;
> +#clock-cells = <1>;
> +#reset-cells = <2>;
> +};
> +
> +Example: consumer nodes
> +i2c0: i2c@1211 {
> + compatible = "hisilicon,hi3519-i2c";
> +reg = <0x1211 0x1000>;
> +clocks = <&CRG HI3519_I2C0_RST>;*/
> +resets = <&CRG 0xe4 0>;
> +};
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> index e434854..b6baebf 100644
> --- a/drivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -1,3 +1,10 @@
> +config COMMON_CLK_HI3519
> + tristate "Clock Driver for Hi3519"
> + depends on ARCH_HISI
> + default y
> + help
> + Build the clock driver for hi3519.
> +
> config COMMON_CLK_HI6220
> bool "Hi6220 Clock Driver"
> depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 74dba31..3f57b09 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -4,8 +4,10 @@
>
> obj-y+= clk.o clkgate-separated.o clkdivider-hi6220.o
>
> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> obj-$(CONFIG_ARCH_HI3xxx)+= clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
> obj-$(CONFIG_STUB_CLK_HI6220)+= clk-hi6220-stub.o
> +obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
> b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 000..e220234
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Pu
Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
Hi Mike,
Happy new year to you!
Thank you for taking time to reply.
On 2015/12/31 8:23, Michael Turquette wrote:
> Hello Jiancheng Xue,
>
> Quoting Jiancheng Xue (2015-12-29 17:43:47)
>> The CRG(Clock and Reset Generator) block provides clock
>> and reset signals for other modules in hi3519 soc.
>>
>> Signed-off-by: Jiancheng Xue
>> ---
>> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
>> drivers/clk/hisilicon/Kconfig | 7 +
>> drivers/clk/hisilicon/Makefile | 2 +
>> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
>> drivers/clk/hisilicon/reset.c | 149
>> +
>> drivers/clk/hisilicon/reset.h | 32 +
>> include/dt-bindings/clock/hi3519-clock.h | 43 ++
>> 7 files changed, 382 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
>> create mode 100644 drivers/clk/hisilicon/reset.c
>> create mode 100644 drivers/clk/hisilicon/reset.h
>> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
>
> Please keep Philipp Zabel Cc'd for reset-related patches. I've added
> him to Cc.
>
OK.
>>
>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> new file mode 100644
>> index 000..2d23950
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>> +
>> +The Hi3519 CRG module provides clock and reset signals to various
>> +controllers within the SoC.
>> +
>> +This binding uses the following bindings:
>> +Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +Documentation/devicetree/bindings/reset/reset.txt
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes use this identifier
>> +to specify the clock which they consume.
>> +
>> +All these identifier could be found in .
>> +
>> +- #reset-cells: should be 2.
>> +
>> +A reset signal can be controlled by writing a bit register in the CRG
>> module.
>> +The reset specifier consists of two cells. The first cell represents the
>> +register offset relative to the base address. The second cell represents the
>> +bit index in the register.
>> +
>> +Example: CRG nodes
>> +CRG: clock-reset-controller@1201 {
>> + compatible = "hisilicon,hi3519-crg";
>> +reg = <0x1201 0x1>;
>> +#clock-cells = <1>;
>> +#reset-cells = <2>;
>> +};
>> +
>> +Example: consumer nodes
>> +i2c0: i2c@1211 {
>> + compatible = "hisilicon,hi3519-i2c";
>> +reg = <0x1211 0x1000>;
>> +clocks = <&CRG HI3519_I2C0_RST>;*/
>> +resets = <&CRG 0xe4 0>;
>> +};
>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>> index e434854..b6baebf 100644
>> --- a/drivers/clk/hisilicon/Kconfig
>> +++ b/drivers/clk/hisilicon/Kconfig
>> @@ -1,3 +1,10 @@
>> +config COMMON_CLK_HI3519
>> + tristate "Clock Driver for Hi3519"
>> + depends on ARCH_HISI
>> + default y
>> + help
>> + Build the clock driver for hi3519.
>> +
>> config COMMON_CLK_HI6220
>> bool "Hi6220 Clock Driver"
>> depends on ARCH_HISI || COMPILE_TEST
>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>> index 74dba31..3f57b09 100644
>> --- a/drivers/clk/hisilicon/Makefile
>> +++ b/drivers/clk/hisilicon/Makefile
>> @@ -4,8 +4,10 @@
>>
>> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>>
>> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
>> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
>> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
>> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
>> obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
>> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
>> +obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
>> b/drivers/clk/hisilicon/clk-hi3519.c
>> new file mode 100644
>> index 000..e220234
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>> @@ -0,0 +1,103 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT AN
Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
On Wed, Dec 30, 2015 at 09:43:47AM +0800, Jiancheng Xue wrote: > The CRG(Clock and Reset Generator) block provides clock > and reset signals for other modules in hi3519 soc. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++ For the binding: Acked-by: Rob Herring -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
Hello Jiancheng Xue,
Quoting Jiancheng Xue (2015-12-29 17:43:47)
> The CRG(Clock and Reset Generator) block provides clock
> and reset signals for other modules in hi3519 soc.
>
> Signed-off-by: Jiancheng Xue
> ---
> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
> drivers/clk/hisilicon/Kconfig | 7 +
> drivers/clk/hisilicon/Makefile | 2 +
> drivers/clk/hisilicon/clk-hi3519.c | 103 ++
> drivers/clk/hisilicon/reset.c | 149
> +
> drivers/clk/hisilicon/reset.h | 32 +
> include/dt-bindings/clock/hi3519-clock.h | 43 ++
> 7 files changed, 382 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
> create mode 100644 drivers/clk/hisilicon/reset.c
> create mode 100644 drivers/clk/hisilicon/reset.h
> create mode 100644 include/dt-bindings/clock/hi3519-clock.h
Please keep Philipp Zabel Cc'd for reset-related patches. I've added
him to Cc.
>
> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> new file mode 100644
> index 000..2d23950
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> @@ -0,0 +1,46 @@
> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
> +
> +The Hi3519 CRG module provides clock and reset signals to various
> +controllers within the SoC.
> +
> +This binding uses the following bindings:
> +Documentation/devicetree/bindings/clock/clock-bindings.txt
> +Documentation/devicetree/bindings/reset/reset.txt
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> + - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes use this identifier
> +to specify the clock which they consume.
> +
> +All these identifier could be found in .
> +
> +- #reset-cells: should be 2.
> +
> +A reset signal can be controlled by writing a bit register in the CRG module.
> +The reset specifier consists of two cells. The first cell represents the
> +register offset relative to the base address. The second cell represents the
> +bit index in the register.
> +
> +Example: CRG nodes
> +CRG: clock-reset-controller@1201 {
> + compatible = "hisilicon,hi3519-crg";
> +reg = <0x1201 0x1>;
> +#clock-cells = <1>;
> +#reset-cells = <2>;
> +};
> +
> +Example: consumer nodes
> +i2c0: i2c@1211 {
> + compatible = "hisilicon,hi3519-i2c";
> +reg = <0x1211 0x1000>;
> +clocks = <&CRG HI3519_I2C0_RST>;*/
> +resets = <&CRG 0xe4 0>;
> +};
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> index e434854..b6baebf 100644
> --- a/drivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -1,3 +1,10 @@
> +config COMMON_CLK_HI3519
> + tristate "Clock Driver for Hi3519"
> + depends on ARCH_HISI
> + default y
> + help
> + Build the clock driver for hi3519.
> +
> config COMMON_CLK_HI6220
> bool "Hi6220 Clock Driver"
> depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 74dba31..3f57b09 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -4,8 +4,10 @@
>
> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>
> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
> +obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c
> b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 000..e220234
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along wit
[PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue
---
.../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 2 +
drivers/clk/hisilicon/clk-hi3519.c | 103 ++
drivers/clk/hisilicon/reset.c | 149 +
drivers/clk/hisilicon/reset.h | 32 +
include/dt-bindings/clock/hi3519-clock.h | 43 ++
7 files changed, 382 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
create mode 100644 drivers/clk/hisilicon/reset.c
create mode 100644 drivers/clk/hisilicon/reset.h
create mode 100644 include/dt-bindings/clock/hi3519-clock.h
diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 000..2d23950
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in .
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@1201 {
+ compatible = "hisilicon,hi3519-crg";
+reg = <0x1201 0x1>;
+#clock-cells = <1>;
+#reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@1211 {
+ compatible = "hisilicon,hi3519-i2c";
+reg = <0x1211 0x1000>;
+clocks = <&CRG HI3519_I2C0_RST>;*/
+resets = <&CRG 0xe4 0>;
+};
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..b6baebf 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_CLK_HI3519
+ tristate "Clock Driver for Hi3519"
+ depends on ARCH_HISI
+ default y
+ help
+ Build the clock driver for hi3519.
+
config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@
obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
+obj-$(CONFIG_RESET_CONTROLLER) += reset.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c
b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 000..e220234
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see
