Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-13 Thread Stefan Agner 
On 2015-03-13 05:48, Shawn Guo wrote:
 On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
 On 2015-03-11 01:48, Shawn Guo wrote:
  On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
  Add the Miscellaneous System Control Module (MSCM) to the base
  device tree for Vybrid SoC's. This module contains registers
  to get information of the individual and current (accessing)
  CPU. In a second block, there is an interrupt router, which
  handles the routing of the interrupts between the two CPU cores
  on VF6xx variants of the SoC. However, also on single core
  variants the interrupt router needs to be configured in order
  to receive interrupts on the CPU's interrupt controller. Almost
  all peripheral interrupts are routed through the router, hence
  the MSCM module is the default interrupt parent for this SoC.
 
  In a earlier commit the interrupt nodes were moved out of the
  peripheral nodes and specified in the CPU specific vf500.dtsi
  device tree. This allowed to use the base device tree vfxxx.dtsi
  also for a Cortex-M4 specific device tree, which uses different
  interrupt nodes due to the NVIC interrupt controller. However,
  since the interrupt parent for peripherals is the MSCM module
  independently which CPU the device tree is used for, we can move
  the interrupt nodes into the base device tree vfxxx.dtsi again.
  Depending on which CPU this base device tree will be used with,
  the correct parent interrupt controller has to be assigned to
  the MSCM-IR node (GIC or NVIC). The driver takes care of the
  parent interrupt controller specific needs (interrupt-cells).
 
  Acked-by: Marc Zyngier marc.zyng...@arm.com
  Signed-off-by: Stefan Agner ste...@agner.ch
 
  Stefan,
 
  I guess this patch has a run-time dependency on the first two in the
  series, right?  Or put it another way, if I apply this single patch on
  my branch, the dtb and kernel built from the same branch do not work
  together, right?  If so, we will need to either wait for the first two
  hit mainline or pull Jason's irqchip/vybrid branch into my tree as
  prerequisite (irqchip/vybrid needs to be stable).
 
  Shawn

 Yes, that is true. The driver need to be in place in order to
 successfully boot with the new device tree.
 
 Okay.  Pulled Jason's irqchip/vybrid branch in, and applied the patch.
 
 Stefan,
 
 There was a conflict on device dspi1 when applying the patch to my
 imx/dt branch.  Please take a look to see if I solved it correctly.
 

Hi Shawn,

Your updated patch looks good to me. Also quickly boot tested the
branch, worked fine.

Thx!

--
Stefan


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Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-12 Thread Stefan Agner 
On 2015-03-11 01:48, Shawn Guo wrote:
 On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
 Add the Miscellaneous System Control Module (MSCM) to the base
 device tree for Vybrid SoC's. This module contains registers
 to get information of the individual and current (accessing)
 CPU. In a second block, there is an interrupt router, which
 handles the routing of the interrupts between the two CPU cores
 on VF6xx variants of the SoC. However, also on single core
 variants the interrupt router needs to be configured in order
 to receive interrupts on the CPU's interrupt controller. Almost
 all peripheral interrupts are routed through the router, hence
 the MSCM module is the default interrupt parent for this SoC.

 In a earlier commit the interrupt nodes were moved out of the
 peripheral nodes and specified in the CPU specific vf500.dtsi
 device tree. This allowed to use the base device tree vfxxx.dtsi
 also for a Cortex-M4 specific device tree, which uses different
 interrupt nodes due to the NVIC interrupt controller. However,
 since the interrupt parent for peripherals is the MSCM module
 independently which CPU the device tree is used for, we can move
 the interrupt nodes into the base device tree vfxxx.dtsi again.
 Depending on which CPU this base device tree will be used with,
 the correct parent interrupt controller has to be assigned to
 the MSCM-IR node (GIC or NVIC). The driver takes care of the
 parent interrupt controller specific needs (interrupt-cells).

 Acked-by: Marc Zyngier marc.zyng...@arm.com
 Signed-off-by: Stefan Agner ste...@agner.ch
 
 Stefan,
 
 I guess this patch has a run-time dependency on the first two in the
 series, right?  Or put it another way, if I apply this single patch on
 my branch, the dtb and kernel built from the same branch do not work
 together, right?  If so, we will need to either wait for the first two
 hit mainline or pull Jason's irqchip/vybrid branch into my tree as
 prerequisite (irqchip/vybrid needs to be stable).
 
 Shawn

Yes, that is true. The driver need to be in place in order to
successfully boot with the new device tree.

--
Stefan

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Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-12 Thread Shawn Guo 
On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
 On 2015-03-11 01:48, Shawn Guo wrote:
  On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
  Add the Miscellaneous System Control Module (MSCM) to the base
  device tree for Vybrid SoC's. This module contains registers
  to get information of the individual and current (accessing)
  CPU. In a second block, there is an interrupt router, which
  handles the routing of the interrupts between the two CPU cores
  on VF6xx variants of the SoC. However, also on single core
  variants the interrupt router needs to be configured in order
  to receive interrupts on the CPU's interrupt controller. Almost
  all peripheral interrupts are routed through the router, hence
  the MSCM module is the default interrupt parent for this SoC.
 
  In a earlier commit the interrupt nodes were moved out of the
  peripheral nodes and specified in the CPU specific vf500.dtsi
  device tree. This allowed to use the base device tree vfxxx.dtsi
  also for a Cortex-M4 specific device tree, which uses different
  interrupt nodes due to the NVIC interrupt controller. However,
  since the interrupt parent for peripherals is the MSCM module
  independently which CPU the device tree is used for, we can move
  the interrupt nodes into the base device tree vfxxx.dtsi again.
  Depending on which CPU this base device tree will be used with,
  the correct parent interrupt controller has to be assigned to
  the MSCM-IR node (GIC or NVIC). The driver takes care of the
  parent interrupt controller specific needs (interrupt-cells).
 
  Acked-by: Marc Zyngier marc.zyng...@arm.com
  Signed-off-by: Stefan Agner ste...@agner.ch
  
  Stefan,
  
  I guess this patch has a run-time dependency on the first two in the
  series, right?  Or put it another way, if I apply this single patch on
  my branch, the dtb and kernel built from the same branch do not work
  together, right?  If so, we will need to either wait for the first two
  hit mainline or pull Jason's irqchip/vybrid branch into my tree as
  prerequisite (irqchip/vybrid needs to be stable).
  
  Shawn
 
 Yes, that is true. The driver need to be in place in order to
 successfully boot with the new device tree.

Okay.  Pulled Jason's irqchip/vybrid branch in, and applied the patch.

Stefan,

There was a conflict on device dspi1 when applying the patch to my
imx/dt branch.  Please take a look to see if I solved it correctly.

Shawn
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Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-10 Thread Jason Cooper 
On Wed, Mar 11, 2015 at 08:48:15AM +0800, Shawn Guo wrote:
 On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
  Add the Miscellaneous System Control Module (MSCM) to the base
  device tree for Vybrid SoC's. This module contains registers
  to get information of the individual and current (accessing)
  CPU. In a second block, there is an interrupt router, which
  handles the routing of the interrupts between the two CPU cores
  on VF6xx variants of the SoC. However, also on single core
  variants the interrupt router needs to be configured in order
  to receive interrupts on the CPU's interrupt controller. Almost
  all peripheral interrupts are routed through the router, hence
  the MSCM module is the default interrupt parent for this SoC.
  
  In a earlier commit the interrupt nodes were moved out of the
  peripheral nodes and specified in the CPU specific vf500.dtsi
  device tree. This allowed to use the base device tree vfxxx.dtsi
  also for a Cortex-M4 specific device tree, which uses different
  interrupt nodes due to the NVIC interrupt controller. However,
  since the interrupt parent for peripherals is the MSCM module
  independently which CPU the device tree is used for, we can move
  the interrupt nodes into the base device tree vfxxx.dtsi again.
  Depending on which CPU this base device tree will be used with,
  the correct parent interrupt controller has to be assigned to
  the MSCM-IR node (GIC or NVIC). The driver takes care of the
  parent interrupt controller specific needs (interrupt-cells).
  
  Acked-by: Marc Zyngier marc.zyng...@arm.com
  Signed-off-by: Stefan Agner ste...@agner.ch
 
 Stefan,
 
 I guess this patch has a run-time dependency on the first two in the
 series, right?  Or put it another way, if I apply this single patch on
 my branch, the dtb and kernel built from the same branch do not work
 together, right?  If so, we will need to either wait for the first two
 hit mainline or pull Jason's irqchip/vybrid branch into my tree as
 prerequisite (irqchip/vybrid needs to be stable).

No problem, I'll only add patches on top of this if needed.  no rebasing.

thx,

Jason.
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Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-10 Thread Shawn Guo 
On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
 Add the Miscellaneous System Control Module (MSCM) to the base
 device tree for Vybrid SoC's. This module contains registers
 to get information of the individual and current (accessing)
 CPU. In a second block, there is an interrupt router, which
 handles the routing of the interrupts between the two CPU cores
 on VF6xx variants of the SoC. However, also on single core
 variants the interrupt router needs to be configured in order
 to receive interrupts on the CPU's interrupt controller. Almost
 all peripheral interrupts are routed through the router, hence
 the MSCM module is the default interrupt parent for this SoC.
 
 In a earlier commit the interrupt nodes were moved out of the
 peripheral nodes and specified in the CPU specific vf500.dtsi
 device tree. This allowed to use the base device tree vfxxx.dtsi
 also for a Cortex-M4 specific device tree, which uses different
 interrupt nodes due to the NVIC interrupt controller. However,
 since the interrupt parent for peripherals is the MSCM module
 independently which CPU the device tree is used for, we can move
 the interrupt nodes into the base device tree vfxxx.dtsi again.
 Depending on which CPU this base device tree will be used with,
 the correct parent interrupt controller has to be assigned to
 the MSCM-IR node (GIC or NVIC). The driver takes care of the
 parent interrupt controller specific needs (interrupt-cells).
 
 Acked-by: Marc Zyngier marc.zyng...@arm.com
 Signed-off-by: Stefan Agner ste...@agner.ch

Stefan,

I guess this patch has a run-time dependency on the first two in the
series, right?  Or put it another way, if I apply this single patch on
my branch, the dtb and kernel built from the same branch do not work
together, right?  If so, we will need to either wait for the first two
hit mainline or pull Jason's irqchip/vybrid branch into my tree as
prerequisite (irqchip/vybrid needs to be stable).

Shawn

 ---
  arch/arm/boot/dts/vf500.dtsi | 137 
 ++-
  arch/arm/boot/dts/vfxxx.dtsi |  49 
  2 files changed, 53 insertions(+), 133 deletions(-)
 
 diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
 index 1dbf8d2..e976d2f 100644
 --- a/arch/arm/boot/dts/vf500.dtsi
 +++ b/arch/arm/boot/dts/vf500.dtsi
 @@ -24,14 +24,13 @@
   };
  
   soc {
 - interrupt-parent = intc;
 -
   aips-bus@4000 {
  
   intc: interrupt-controller@40002000 {
   compatible = arm,cortex-a9-gic;
   #interrupt-cells = 3;
   interrupt-controller;
 + interrupt-parent = intc;
   reg = 0x40003000 0x1000,
 0x40002100 0x100;
   };
 @@ -40,145 +39,17 @@
   compatible = arm,cortex-a9-global-timer;
   reg = 0x40002200 0x20;
   interrupts = GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH;
 + interrupt-parent = intc;
   clocks = clks VF610_CLK_PLATFORM_BUS;
   };
   };
   };
  };
  
 -adc0 {
 - interrupts = GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -adc1 {
 - interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -can0 {
 - interrupts = GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -can1 {
 - interrupts = GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -dspi0 {
 - interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -edma0 {
 - interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
 - GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH;
 - interrupt-names = edma-tx, edma-err;
 -};
 -
 -edma1 {
 - interrupts = GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH,
 - GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
 - interrupt-names = edma-tx, edma-err;
 -};
 -
 -esdhc1 {
 - interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -fec0 {
 - interrupts = GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -fec1 {
 - interrupts = GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -ftm {
 - interrupts = GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -gpio0 {
 - interrupts = GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -gpio1 {
 - interrupts = GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -gpio2 {
 - interrupts = GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -gpio3 {
 - interrupts = GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -gpio4 {
 - interrupts = GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -i2c0 {
 - interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -pit {
 - interrupts = GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -qspi0 {
 - interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -sai2 {
 - interrupts = GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -snvsrtc {
 - interrupts = GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH;
 -};
 -
 -src {
 - interrupts =

[PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)

2015-03-01 Thread Stefan Agner 
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.

In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).

Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Stefan Agner ste...@agner.ch
---
 arch/arm/boot/dts/vf500.dtsi | 137 ++-
 arch/arm/boot/dts/vfxxx.dtsi |  49 
 2 files changed, 53 insertions(+), 133 deletions(-)

diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2..e976d2f 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
 
soc {
-   interrupt-parent = intc;
-
aips-bus@4000 {
 
intc: interrupt-controller@40002000 {
compatible = arm,cortex-a9-gic;
#interrupt-cells = 3;
interrupt-controller;
+   interrupt-parent = intc;
reg = 0x40003000 0x1000,
  0x40002100 0x100;
};
@@ -40,145 +39,17 @@
compatible = arm,cortex-a9-global-timer;
reg = 0x40002200 0x20;
interrupts = GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH;
+   interrupt-parent = intc;
clocks = clks VF610_CLK_PLATFORM_BUS;
};
};
};
 };
 
-adc0 {
-   interrupts = GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH;
-};
-
-adc1 {
-   interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
-};
-
-can0 {
-   interrupts = GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH;
-};
-
-can1 {
-   interrupts = GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH;
-};
-
-dspi0 {
-   interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
-};
-
-edma0 {
-   interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
-   GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH;
-   interrupt-names = edma-tx, edma-err;
-};
-
-edma1 {
-   interrupts = GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH,
-   GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
-   interrupt-names = edma-tx, edma-err;
-};
-
-esdhc1 {
-   interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
-};
-
-fec0 {
-   interrupts = GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH;
-};
-
-fec1 {
-   interrupts = GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH;
-};
-
-ftm {
-   interrupts = GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio0 {
-   interrupts = GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio1 {
-   interrupts = GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio2 {
-   interrupts = GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio3 {
-   interrupts = GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio4 {
-   interrupts = GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH;
-};
-
-i2c0 {
-   interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
-};
-
-pit {
-   interrupts = GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH;
-};
-
-qspi0 {
-   interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
-};
-
-sai2 {
-   interrupts = GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH;
-};
-
-snvsrtc {
-   interrupts = GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH;
-};
-
-src {
-   interrupts = GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart0 {
-   interrupts = GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart1 {
-   interrupts = GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart2 {
-   interrupts = GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart3 {
-   interrupts = GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart4 {
-   interrupts = GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart5 {
-   interrupts = GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbdev0 {
-   interrupts = GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbh1 {
-