Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
On 2015/9/7 20:17, Lian M.H. wrote:
> Hi Zhou,
>
> You can aslo add my Tested-by: Minghuan Lian
>
> I submitted my patch based on your patchset. It works well on our SoC
> ls1021(arm32) ls1043(arm64) and ls2085(arm64)
>
> Best Regards.
> Minghuan
Hi Minghuan,
Many thanks for your testing. Will add your Tested-by in next version :)
Best Regards,
Zhou
>
>> -Original Message-
>> From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
>> On Behalf Of Gabriel Fernandez
>> Sent: Thursday, August 27, 2015 8:57 PM
>> To: Zhou Wang
>> Cc: thomas.petazz...@free-electrons.com; r...@kernel.org;
>> lorenzo.pieral...@arm.com; Russell King ;
>> gabriele.paol...@huawei.com; Arnd Bergmann ;
>> devicetree@vger.kernel.org; jingooh...@gmail.com;
>> pratyush.an...@gmail.com; Liviu Dudau ;
>> xuw...@hisilicon.com; james.mo...@arm.com; qiuzhe...@hisilicon.com;
>> liudongdo...@huawei.com; linux-...@vger.kernel.org; Bjorn Helgaas
>> ; zhangju...@huawei.com; liguo...@hisilicon.com;
>> qiuji...@huawei.com; linux-arm-ker...@lists.infradead.org;
>> ja...@lakedaemon.net
>> Subject: Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
>>
>> Hi Zhou,
>>
>> You can add my Tested-by: Gabriel Fernandez
>>
>> I tested your patchset with a STMicroelectronics PCIe controller.
>> This controller is based on designware PCIe driver and works on ARM32.
>>
>> Please find my patchset here:
>> http://www.spinics.net/lists/kernel/msg2064266.html
>>
>> Best Regards.
>>
>> Gabriel.
>>
>> On 25 August 2015 at 11:58, Zhou Wang wrote:
>>> This patch tries to unify ARM32 and ARM64 PCIe in designware driver.
>>> Delete function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and
>>> struct hw_pci, move related operations to dw_pcie_host_init.
>>>
>>> This patch also try to use of_pci_get_host_bridge_resources for ARM32
>>> and ARM64 according to the suggestion for Gabriele[1]
>>>
>>> Finally this patch reverts commit f4c55c5a3f7f "PCI: designware:
>>> Program ATU with untranslated address" based on 1/6 in this series. we
>>> delete *_mod_base in pcie-designware. This was discussed in [2]
>>>
>>> I have compiled the driver with multi_v7_defconfig. However, I don't
>>> have
>>> ARM32 PCIe related board to do test. It will be appreciated if someone
>>> could help to test it.
>>>
>>> Signed-off-by: Zhou Wang
>>> Signed-off-by: Gabriele Paoloni
>>> Signed-off-by: Arnd Bergmann
>>> Tested-By: James Morse
>>>
>>> [1] http://www.spinics.net/lists/linux-pci/msg42194.html
>>> [2] http://www.spinics.net/lists/arm-kernel/msg436779.html
>>> ---
>>> drivers/pci/host/pci-dra7xx.c | 14 +--
>>> drivers/pci/host/pci-keystone-dw.c | 2 +-
>>> drivers/pci/host/pcie-designware.c | 230
>>> +
>>> drivers/pci/host/pcie-designware.h | 14 +--
>>> 4 files changed, 90 insertions(+), 170 deletions(-)
>>>
>>> diff --git a/drivers/pci/host/pci-dra7xx.c
>>> b/drivers/pci/host/pci-dra7xx.c index 18ae7ff..ac401be 100644
>>> --- a/drivers/pci/host/pci-dra7xx.c
>>> +++ b/drivers/pci/host/pci-dra7xx.c
>>> @@ -141,15 +141,15 @@ static void dra7xx_pcie_host_init(struct
>>> pcie_port *pp) {
>>> dw_pcie_setup_rc(pp);
>>>
>>> - if (pp->io_mod_base)
>>> - pp->io_mod_base &= CPU_TO_BUS_ADDR;
>>> + if (pp->io_base)
>>> + pp->io_base &= CPU_TO_BUS_ADDR;
>>>
>>> - if (pp->mem_mod_base)
>>> - pp->mem_mod_base &= CPU_TO_BUS_ADDR;
>>> + if (pp->mem_base)
>>> + pp->mem_base &= CPU_TO_BUS_ADDR;
>>>
>>> - if (pp->cfg0_mod_base) {
>>> - pp->cfg0_mod_base &= CPU_TO_BUS_ADDR;
>>> - pp->cfg1_mod_base &= CPU_TO_BUS_ADDR;
>>> + if (pp->cfg0_base) {
>>> + pp->cfg0_base &= CPU_TO_BUS_ADDR;
>>> + pp->cfg1_base &= CPU_TO_BUS_ADDR;
>>> }
>>>
>>> dra7xx_pcie_establish_link(pp); diff --git
>>> a/drivers/pci/host/pci-keystone-dw.c
>>> b/drivers/pci/host/pci-keystone-dw.c
>>> index f34892e..b1e4135 100644
>>> --- a/drivers/pci/host/pci-keystone-dw.c
>>> +++ b/drivers/pci/host/pci-keystone-dw.c
Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
On 2015/8/27 20:56, Gabriel Fernandez wrote:
> Hi Zhou,
>
> You can add my Tested-by: Gabriel Fernandez
>
> I tested your patchset with a STMicroelectronics PCIe controller.
> This controller is based on designware PCIe driver and works on ARM32.
>
> Please find my patchset here:
> http://www.spinics.net/lists/kernel/msg2064266.html
>
> Best Regards.
>
> Gabriel.
>
Hi Gabriel,
It is very helpful to test this patch. Many thanks!
Best Regards,
Zhou
> On 25 August 2015 at 11:58, Zhou Wang wrote:
>> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
>> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
>> move related operations to dw_pcie_host_init.
>>
>> This patch also try to use of_pci_get_host_bridge_resources for ARM32 and
>> ARM64
>> according to the suggestion for Gabriele[1]
>>
>> Finally this patch reverts commit f4c55c5a3f7f "PCI: designware: Program ATU
>> with untranslated address" based on 1/6 in this series. we delete *_mod_base
>> in
>> pcie-designware. This was discussed in [2]
>>
>> I have compiled the driver with multi_v7_defconfig. However, I don't have
>> ARM32 PCIe related board to do test. It will be appreciated if someone could
>> help to test it.
>>
>> Signed-off-by: Zhou Wang
>> Signed-off-by: Gabriele Paoloni
>> Signed-off-by: Arnd Bergmann
>> Tested-By: James Morse
>>
>> [1] http://www.spinics.net/lists/linux-pci/msg42194.html
>> [2] http://www.spinics.net/lists/arm-kernel/msg436779.html
>> ---
>> drivers/pci/host/pci-dra7xx.c | 14 +--
>> drivers/pci/host/pci-keystone-dw.c | 2 +-
>> drivers/pci/host/pcie-designware.c | 230
>> +
>> drivers/pci/host/pcie-designware.h | 14 +--
>> 4 files changed, 90 insertions(+), 170 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
>> index 18ae7ff..ac401be 100644
>> --- a/drivers/pci/host/pci-dra7xx.c
>> +++ b/drivers/pci/host/pci-dra7xx.c
>> @@ -141,15 +141,15 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
>> {
>> dw_pcie_setup_rc(pp);
>>
>> - if (pp->io_mod_base)
>> - pp->io_mod_base &= CPU_TO_BUS_ADDR;
>> + if (pp->io_base)
>> + pp->io_base &= CPU_TO_BUS_ADDR;
>>
>> - if (pp->mem_mod_base)
>> - pp->mem_mod_base &= CPU_TO_BUS_ADDR;
>> + if (pp->mem_base)
>> + pp->mem_base &= CPU_TO_BUS_ADDR;
>>
>> - if (pp->cfg0_mod_base) {
>> - pp->cfg0_mod_base &= CPU_TO_BUS_ADDR;
>> - pp->cfg1_mod_base &= CPU_TO_BUS_ADDR;
>> + if (pp->cfg0_base) {
>> + pp->cfg0_base &= CPU_TO_BUS_ADDR;
>> + pp->cfg1_base &= CPU_TO_BUS_ADDR;
>> }
>>
>> dra7xx_pcie_establish_link(pp);
>> diff --git a/drivers/pci/host/pci-keystone-dw.c
>> b/drivers/pci/host/pci-keystone-dw.c
>> index f34892e..b1e4135 100644
>> --- a/drivers/pci/host/pci-keystone-dw.c
>> +++ b/drivers/pci/host/pci-keystone-dw.c
>> @@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem
>> *reg_virt)
>> void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>> {
>> struct pcie_port *pp = &ks_pcie->pp;
>> - u32 start = pp->mem.start, end = pp->mem.end;
>> + u32 start = pp->mem->start, end = pp->mem->end;
>> int i, tr_size;
>>
>> /* Disable BARs for inbound access */
>> diff --git a/drivers/pci/host/pcie-designware.c
>> b/drivers/pci/host/pcie-designware.c
>> index c5d407c..e2d1898 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -11,6 +11,7 @@
>> * published by the Free Software Foundation.
>> */
>>
>> +#include
>> #include
>> #include
>> #include
>> @@ -69,16 +70,7 @@
>> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
>> #define PCIE_ATU_UPPER_TARGET 0x91C
>>
>> -static struct hw_pci dw_pci;
>> -
>> -static unsigned long global_io_offset;
>> -
>> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>> -{
>> - BUG_ON(!sys->private_data);
>> -
>> - return sys->private_data;
>> -}
>> +static struct pci_ops dw_pcie_ops;
>>
>> int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>> {
>> @@ -255,7 +247,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp,
>> int irq)
>> static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
>> {
>> int irq, pos0, i;
>> - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
>> + struct pcie_port *pp = desc->dev->bus->sysdata;
>>
>> pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
>>order_base_2(no_irqs));
>> @@ -298,7 +290,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip,
>> struct pci_dev *pdev,
>> {
>> int irq, pos;
>> struct msi_msg msg;
>> - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
>>
RE: [PATCH v8 3/6] PCI: designware: Add ARM64 support
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-ow...@vger.kernel.org]
> On Behalf Of Gabriel Fernandez
> Sent: 27 August 2015 13:57
> To: Wangzhou (B)
> Cc: Bjorn Helgaas; jingooh...@gmail.com; pratyush.an...@gmail.com; Arnd
> Bergmann; Russell King; thomas.petazz...@free-electrons.com; Gabriele Paoloni;
> lorenzo.pieral...@arm.com; james.mo...@arm.com; Liviu Dudau;
> ja...@lakedaemon.net; r...@kernel.org; devicetree@vger.kernel.org; linux-
> p...@vger.kernel.org; xuwei (O); qiuzhenfa; liudongdong (C); zhangjukuo;
> Liguozhu (Kenneth); qiujiang; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
>
> Hi Zhou,
>
> You can add my Tested-by: Gabriel Fernandez
>
> I tested your patchset with a STMicroelectronics PCIe controller.
> This controller is based on designware PCIe driver and works on ARM32.
>
> Please find my patchset here:
> http://www.spinics.net/lists/kernel/msg2064266.html
>
> Best Regards.
>
> Gabriel.
Many Thanks for this Gabriel
Cheers
Gab
>
> On 25 August 2015 at 11:58, Zhou Wang wrote:
> > This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
> > function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
> > move related operations to dw_pcie_host_init.
> >
> > This patch also try to use of_pci_get_host_bridge_resources for ARM32 and
> ARM64
> > according to the suggestion for Gabriele[1]
> >
> > Finally this patch reverts commit f4c55c5a3f7f "PCI: designware: Program ATU
> > with untranslated address" based on 1/6 in this series. we delete *_mod_base
> in
> > pcie-designware. This was discussed in [2]
> >
> > I have compiled the driver with multi_v7_defconfig. However, I don't have
> > ARM32 PCIe related board to do test. It will be appreciated if someone could
> > help to test it.
> >
> > Signed-off-by: Zhou Wang
> > Signed-off-by: Gabriele Paoloni
> > Signed-off-by: Arnd Bergmann
> > Tested-By: James Morse
> >
> > [1] http://www.spinics.net/lists/linux-pci/msg42194.html
> > [2] http://www.spinics.net/lists/arm-kernel/msg436779.html
> > ---
> > drivers/pci/host/pci-dra7xx.c | 14 +--
> > drivers/pci/host/pci-keystone-dw.c | 2 +-
> > drivers/pci/host/pcie-designware.c | 230 +-
> ---
> > drivers/pci/host/pcie-designware.h | 14 +--
> > 4 files changed, 90 insertions(+), 170 deletions(-)
> >
> > diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> > index 18ae7ff..ac401be 100644
> > --- a/drivers/pci/host/pci-dra7xx.c
> > +++ b/drivers/pci/host/pci-dra7xx.c
> > @@ -141,15 +141,15 @@ static void dra7xx_pcie_host_init(struct pcie_port
> > *pp)
> > {
> > dw_pcie_setup_rc(pp);
> >
> > - if (pp->io_mod_base)
> > - pp->io_mod_base &= CPU_TO_BUS_ADDR;
> > + if (pp->io_base)
> > + pp->io_base &= CPU_TO_BUS_ADDR;
> >
> > - if (pp->mem_mod_base)
> > - pp->mem_mod_base &= CPU_TO_BUS_ADDR;
> > + if (pp->mem_base)
> > + pp->mem_base &= CPU_TO_BUS_ADDR;
> >
> > - if (pp->cfg0_mod_base) {
> > - pp->cfg0_mod_base &= CPU_TO_BUS_ADDR;
> > - pp->cfg1_mod_base &= CPU_TO_BUS_ADDR;
> > + if (pp->cfg0_base) {
> > + pp->cfg0_base &= CPU_TO_BUS_ADDR;
> > + pp->cfg1_base &= CPU_TO_BUS_ADDR;
> > }
> >
> > dra7xx_pcie_establish_link(pp);
> > diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-
> keystone-dw.c
> > index f34892e..b1e4135 100644
> > --- a/drivers/pci/host/pci-keystone-dw.c
> > +++ b/drivers/pci/host/pci-keystone-dw.c
> > @@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem
> *reg_virt)
> > void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> > {
> > struct pcie_port *pp = &ks_pcie->pp;
> > - u32 start = pp->mem.start, end = pp->mem.end;
> > + u32 start = pp->mem->start, end = pp->mem->end;
> > int i, tr_size;
> >
> > /* Disable BARs for inbound access */
> > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
> designware.c
> > index c5d407c..e2d1898 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> >
Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support
Hi Zhou,
You can add my Tested-by: Gabriel Fernandez
I tested your patchset with a STMicroelectronics PCIe controller.
This controller is based on designware PCIe driver and works on ARM32.
Please find my patchset here:
http://www.spinics.net/lists/kernel/msg2064266.html
Best Regards.
Gabriel.
On 25 August 2015 at 11:58, Zhou Wang wrote:
> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
> move related operations to dw_pcie_host_init.
>
> This patch also try to use of_pci_get_host_bridge_resources for ARM32 and
> ARM64
> according to the suggestion for Gabriele[1]
>
> Finally this patch reverts commit f4c55c5a3f7f "PCI: designware: Program ATU
> with untranslated address" based on 1/6 in this series. we delete *_mod_base
> in
> pcie-designware. This was discussed in [2]
>
> I have compiled the driver with multi_v7_defconfig. However, I don't have
> ARM32 PCIe related board to do test. It will be appreciated if someone could
> help to test it.
>
> Signed-off-by: Zhou Wang
> Signed-off-by: Gabriele Paoloni
> Signed-off-by: Arnd Bergmann
> Tested-By: James Morse
>
> [1] http://www.spinics.net/lists/linux-pci/msg42194.html
> [2] http://www.spinics.net/lists/arm-kernel/msg436779.html
> ---
> drivers/pci/host/pci-dra7xx.c | 14 +--
> drivers/pci/host/pci-keystone-dw.c | 2 +-
> drivers/pci/host/pcie-designware.c | 230
> +
> drivers/pci/host/pcie-designware.h | 14 +--
> 4 files changed, 90 insertions(+), 170 deletions(-)
>
> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> index 18ae7ff..ac401be 100644
> --- a/drivers/pci/host/pci-dra7xx.c
> +++ b/drivers/pci/host/pci-dra7xx.c
> @@ -141,15 +141,15 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
> {
> dw_pcie_setup_rc(pp);
>
> - if (pp->io_mod_base)
> - pp->io_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->io_base)
> + pp->io_base &= CPU_TO_BUS_ADDR;
>
> - if (pp->mem_mod_base)
> - pp->mem_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->mem_base)
> + pp->mem_base &= CPU_TO_BUS_ADDR;
>
> - if (pp->cfg0_mod_base) {
> - pp->cfg0_mod_base &= CPU_TO_BUS_ADDR;
> - pp->cfg1_mod_base &= CPU_TO_BUS_ADDR;
> + if (pp->cfg0_base) {
> + pp->cfg0_base &= CPU_TO_BUS_ADDR;
> + pp->cfg1_base &= CPU_TO_BUS_ADDR;
> }
>
> dra7xx_pcie_establish_link(pp);
> diff --git a/drivers/pci/host/pci-keystone-dw.c
> b/drivers/pci/host/pci-keystone-dw.c
> index f34892e..b1e4135 100644
> --- a/drivers/pci/host/pci-keystone-dw.c
> +++ b/drivers/pci/host/pci-keystone-dw.c
> @@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem
> *reg_virt)
> void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> {
> struct pcie_port *pp = &ks_pcie->pp;
> - u32 start = pp->mem.start, end = pp->mem.end;
> + u32 start = pp->mem->start, end = pp->mem->end;
> int i, tr_size;
>
> /* Disable BARs for inbound access */
> diff --git a/drivers/pci/host/pcie-designware.c
> b/drivers/pci/host/pcie-designware.c
> index c5d407c..e2d1898 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -11,6 +11,7 @@
> * published by the Free Software Foundation.
> */
>
> +#include
> #include
> #include
> #include
> @@ -69,16 +70,7 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> -static struct hw_pci dw_pci;
> -
> -static unsigned long global_io_offset;
> -
> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
> -{
> - BUG_ON(!sys->private_data);
> -
> - return sys->private_data;
> -}
> +static struct pci_ops dw_pcie_ops;
>
> int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
> {
> @@ -255,7 +247,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int
> irq)
> static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
> {
> int irq, pos0, i;
> - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
> + struct pcie_port *pp = desc->dev->bus->sysdata;
>
> pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
>order_base_2(no_irqs));
> @@ -298,7 +290,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip,
> struct pci_dev *pdev,
> {
> int irq, pos;
> struct msi_msg msg;
> - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
> + struct pcie_port *pp = pdev->bus->sysdata;
>
> if (desc->msi_attrib.is_msix)
> return -EINVAL;
> @@ -327,7 +319,7 @@ static void dw_msi_teardown_irq(struct msi_controller
> *chip, unsigned int irq)
> {
> struct irq_data *data = irq_get_irq_d
