Re: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller devices to device tree

[Guennadi Liakhovetski]

Hi Laurent

On Sat, 18 May 2013, Laurent Pinchart wrote:

> Hi Guennadi,
> 
> On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> > Hi Laurent
> > 
> > On Wed, 15 May 2013, Laurent Pinchart wrote:
> > > Add GPIO controller nodes to the r8a7790 core device tree.
> > > 
> > > Signed-off-by: Laurent Pinchart
> > > 
> > > ---
> > > 
> > >  arch/arm/boot/dts/r8a7790.dtsi | 54 +
> > >  1 file changed, 54 insertions(+)
> > 
> > Also here a couple of things are missing (presumably, for other SoCs you
> > need the same):
> 
> Thank you for testing the patch set. I'll integrate the modification in the 
> next version for r8a7778, r8a7779 and r8a7790.
> 
> As the gpio-ranges property specifies the number of GPIOs handled by the 
> controller, what's your opinion on dropping the #gpio-lines property from the 
> bindings ?

Well, gpio-ranges can contain several ranges, so, in a generic case you 
would have to sum them up to get a total count. But if you're ok with that 
or if your platforms only have 1 gpio gange per controller, of course, 
that property seems redundant. OTOH it is already used in r8a7779.dtsi, 
and thus already belongs to the ABI... Not sure whether removing it would 
be accepted.

Thanks
Guennadi

> > diff --git a/arch/arm/boot/dts/r8a7790.dtsi
> > b/arch/arm/boot/dts/r8a7790.dtsi
> > index 674ee39..cd1a04f 100644
> > --- a/arch/arm/boot/dts/r8a7790.dtsi
> > +++ b/arch/arm/boot/dts/r8a7790.dtsi
> > @@ -51,6 +51,7 @@
> > interrupts = <0 4 0x4>;
> > #gpio-cells = <2>;
> > gpio-controller;
> > +   gpio-ranges = <&pfc 0 0 32>;
> > };
> > 
> > gpio1: gpio@ffc41000 {

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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Re: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller devices to device tree

[Laurent Pinchart]

Hi Guennadi,

On Friday 17 May 2013 14:26:48 Guennadi Liakhovetski wrote:
> Hi Laurent
> 
> On Wed, 15 May 2013, Laurent Pinchart wrote:
> > Add GPIO controller nodes to the r8a7790 core device tree.
> > 
> > Signed-off-by: Laurent Pinchart
> > 
> > ---
> > 
> >  arch/arm/boot/dts/r8a7790.dtsi | 54 +
> >  1 file changed, 54 insertions(+)
> 
> Also here a couple of things are missing (presumably, for other SoCs you
> need the same):

Thank you for testing the patch set. I'll integrate the modification in the 
next version for r8a7778, r8a7779 and r8a7790.

As the gpio-ranges property specifies the number of GPIOs handled by the 
controller, what's your opinion on dropping the #gpio-lines property from the 
bindings ?

> diff --git a/arch/arm/boot/dts/r8a7790.dtsi
> b/arch/arm/boot/dts/r8a7790.dtsi
> index 674ee39..cd1a04f 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -51,6 +51,7 @@
>   interrupts = <0 4 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 0 32>;
>   };
> 
>   gpio1: gpio@ffc41000 {
> @@ -60,6 +61,7 @@
>   interrupts = <0 5 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 32 32>;
>   };
> 
>   gpio2: gpio@ffc42000 {
> @@ -69,6 +71,7 @@
>   interrupts = <0 6 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 64 32>;
>   };
> 
>   gpio3: gpio@ffc43000 {
> @@ -78,6 +81,7 @@
>   interrupts = <0 7 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 96 32>;
>   };
> 
>   gpio4: gpio@ffc44000 {
> @@ -87,6 +91,7 @@
>   interrupts = <0 8 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 128 32>;
>   };
> 
>   gpio5: gpio@ffc45000 {
> @@ -96,6 +101,7 @@
>   interrupts = <0 9 0x4>;
>   #gpio-cells = <2>;
>   gpio-controller;
> + gpio-ranges = <&pfc 0 160 32>;
>   };
> 
>   timer {
> @@ -118,6 +124,7 @@
>   pfc: pfc@e606 {
>   compatible = "renesas,pfc-r8a7790";
>   reg = <0 0xe606 0 0x250>;
> + #gpio-range-cells = <3>;
>   };
> 
>   /* No MMC_CAP_UHS_DDR50 (dual data rate) capability on r8a7790! */

-- 
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Laurent Pinchart

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Re: [RFC/PATCH 2/2] gpio-rcar: Add DT support

[Laurent Pinchart]

Hi Guennadi,

On Friday 17 May 2013 14:22:22 Guennadi Liakhovetski wrote:
> On Fri, 10 May 2013, Laurent Pinchart wrote:
> > Add DT bindings for the gpio-rcar driver and read the device
> > configuration from the DT node at probe time if available.
> > 
> > Cc: devicetree-discuss@lists.ozlabs.org
> > Signed-off-by: Laurent Pinchart 
> > ---
> > 
> >  .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 48 +
> >  drivers/gpio/gpio-rcar.c   | 63 +
> >  2 files changed, 101 insertions(+), 10 deletions(-)
> >  create mode 100644
> >  Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
> Testing this patch reveals, that (at least) one thing is missing here:
> 
> diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> index a499ea6..e233778 100644
> --- a/drivers/gpio/gpio-rcar.c
> +++ b/drivers/gpio/gpio-rcar.c
> @@ -342,6 +342,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
> gpio_chip->owner = THIS_MODULE;
>   gpio_chip->base = p->config.gpio_base;
>   gpio_chip->ngpio = p->config.number_of_pins;
> + gpio_chip->dev = &pdev->dev;
> 
>   irq_chip = &p->irq_chip;
>   irq_chip->name = name;

Indeed, thank you. I wonder how I managed not to notice this. I'll integrate 
the modification for v2.

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Re: [PATCH] gianfar: add missing iounmap() on error in gianfar_ptp_probe()

[David Miller]

From: Wei Yongjun 
Date: Fri, 17 May 2013 16:25:34 +0800

> From: Wei Yongjun 
> 
> Add the missing iounmap() before return from gianfar_ptp_probe()
> in the error handling case.
> 
> Signed-off-by: Wei Yongjun 

Applied, thanks.
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Re: Pulls and drive strengths in the pinctrl world

[Tomasz Figa]

Hi Jean-Christophe,

On Friday 17 of May 2013 14:26:25 Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:22 Wed 15 May , Stephen Warren wrote:
> > On 05/15/2013 06:13 PM, Tomasz Figa wrote:
> > > On Wednesday 15 of May 2013 16:55:37 Doug Anderson wrote:
> > >> Tomasz / Linus,
> > >> 
> > >> On Wed, May 15, 2013 at 3:06 PM, Tomasz Figa
> > >> 
> > > 
> > > wrote:
> > >>> Yes. I don't like the current way too much either, duplication
> > >>> being
> > >>> one of the reasons.
> > >> 
> > >> Do you have any other ideas?  It sounds like Linus didn't like my
> > >> suggestion and makes some good points...
> > > 
> > > I don't have anything interesting at the moment. It's a bit late now
> > > here (2 AM), so I'm going to get some sleep first.
> > > 
> > > Also after reading Stephen's reply, I'm wondering if hogging
> > > wouldn't
> > > solve the problem indeed. (It might have to be fixed on
> > > pinctrl-samsung
> > > first, as last time I tried to use it, it caused some errors from
> > > pinctrl core, but haven't time to track them down, as it wasn't
> > > anything important at that time).
> > 
> > One issue I noticed with the DT fragments earlier in this thread. It
> > looks like hogs in the Samsung pinctrl bingings end up looking like:
> > 
> > pinctrl {
> > 
> > pina {
> > 
> > samsung,pins = ;
> > samsung,pin-function = <0xf>;
> > samsung,pin-pud = <0>;
> > ...
> 
> I have a huge issue here that we had on at91 too
> 
> we are going to have a huge numbet of node
> 
> and on at91 we handle the pin the same way as samsung
> and ST have also a similiar IP
> 
> so I'll prefer to reuse the AT91 DT bindings
> 
> as said by Linus I just push a cleanup of the magic by using Macro
> which make it really readable now
> 
> some extract of the sama5 pinctrl
> 
>   mmc0 {
>   pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
>   atmel,pins =
>*/ AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A
> MCI0_CDA with pullup */ AT91_PIOD 1 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;/* PD1 periph A MCI0_DA0 with pullup */ };
>   pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
>   atmel,pins =
>MCI0_DA1 with pullup */ AT91_PIOD 3 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP  /* PD3 periph A MCI0_DA2 with pullup */ AT91_PIOD
> 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;/* PD4 periph A MCI0_DA3 
with
> pullup */ };
>   pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
>   atmel,pins =
>MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ AT91_PIOD 6
> AT91_PERIPH_A AT91_PINCTRL_PULL_UP/* PD6 periph A MCI0_DA5 with
> pullup, conflicts with TIOB0, PWML2 */ AT91_PIOD 7 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP  /* PD7 periph A MCI0_DA6 with pullup, conlicts
> with TCLK0, PWMH3 */ AT91_PIOD 8 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;/* PD8 periph A MCI0_DA7 with pullup, 
conflicts
> with PWML3 */ };
>   };
> 
> of sam9g45
> 
>   i2c_gpio2 {
>   pinctrl_i2c_gpio2: i2c_gpio2-0 {
>   atmel,pins =
>multidrive I2C2 data */ AT91_PIOB 5 AT91_PERIPH_GPIO
> AT91_PINCTRL_MULTI_DRIVE>;/* PB5 gpio multidrive I2C2 clock */ };
>   };
> 
> so we could share the c code too

I'd have a question with regard to AT91 bindings.

Using Samsung bindings we don't need to specify all configuration options 
for a pin, only those that are relevant for the platform. Do your bindings 
allow this?

Apparently AT91 has less configurable things and those available are 
usually always configured together so it's not a problem. But on our SoCs 
we have a bit more of them:
- function (input, output, special functions)
- pull-down/-up
- driver strength
- power down mode function (input, output low, output high, retention)
- power down mode pull-down/-up
- one could argue that default output value could be set this way as well, 
by adding samsung,pin-value property.

Best regards,
Tomasz

> Best Regards,
> J,
> 
> > };
> > pinp {
> > 
> > samsung,pins = ;
> > samsung,pin-function = <0xe>;
> > samsung,pin-pud = <1>;
> > ...
> > 
> > };
> > pinx {
> > 
> > samsung,pins = ;
> > samsung,pin-function = <0xd>;
> > samsung,pin-pud = <2>;
> > ...
> > 
> > };
> > 
> > pinctrl-names = "default";
> > pinctrl-0 = <&pina &pinp &pinx>;
> > 
> > };
> > 
> > That pinctrl-0 property could get rather large (hard to
> > write/maintain,
> > unwieldy) if it needs to set up lots of different configurations.
> > That's why I made the equivalent Tegra bindings be:
> > 
> > pinctrl {
> > 
> > pins_default {
> > 
> > pina {
> > 
> > samsung,pins = ;
> > samsung,pin-function = <0xf>;
> > samsung,pin-pud = <0>;
> > ...
>

[GIT PULL] DT changes for v3.10

[Grant Likely]

Hi Linus,

Here are a few DT bug fixes and documentation updates. Sorry this pull
request came after -rc1. I hope it is still okay to pull in. All has
been in linux-next well before the merge window.

g.

The following changes since commit 31880c37c11e28cb81c70757e38392b42e695dc6:

  Linux 3.9-rc6 (2013-04-07 20:49:54 -0700)

are available in the git repository at:

  git://git.secretlab.ca/git/linux tags/devicetree-for-linus

for you to fetch changes up to 3132f623386e9ac87077bd839e726f7b940fbc94:

  Merge branch 'for-next' of git://sources.calxeda.com/kernel/linux
into HEAD (2013-05-07 12:03:42 +0100)



Device tree bug fixes and documentation updates for v3.10

Nothing earth shattering here. A build failure fix, and fix for
releasing nodes and some documenation updates.


Grant Likely (1):
  Merge branch 'for-next' of
git://sources.calxeda.com/kernel/linux into HEAD

Rahul Sharma (1):
  of/documentation: move video device bindings to a common place

Rob Herring (1):
  Merge tag 'tegra-for-3.10-dtc-cpp-chroot-std-headers' of
git://git.kernel.org/.../swarren/linux-tegra into for-next

Sergei Shtylyov (1):
  : fix compilation warnings with DT disabled

Tang Yuantian (1):
  of/base: release the node correctly in of_parse_phandle_with_args()

Uwe Kleine-König (1):
  Documentation/devicetree: make semantic of initrd-end more explicit

 .../{drm/exynos/hdmi.txt => video/exynos_hdmi.txt} |  0
 .../hdmiddc.txt => video/exynos_hdmiddc.txt}   |  0
 .../hdmiphy.txt => video/exynos_hdmiphy.txt}   |  0
 .../exynos/mixer.txt => video/exynos_mixer.txt}|  0
 Documentation/devicetree/usage-model.txt   |  8 +-
 arch/arm/boot/dts/include/dt-bindings  |  1 +
 drivers/of/base.c  |  4 +-
 include/dt-bindings/gpio/gpio.h| 15 
 include/dt-bindings/interrupt-controller/arm-gic.h | 22 +
 include/dt-bindings/interrupt-controller/irq.h | 19 +
 include/linux/of_platform.h|  5 +-
 scripts/Makefile.lib   | 17 ++--
 scripts/basic/fixdep.c | 93 ++
 13 files changed, 135 insertions(+), 49 deletions(-)
 rename Documentation/devicetree/bindings/{drm/exynos/hdmi.txt =>
video/exynos_hdmi.txt} (100%)
 rename Documentation/devicetree/bindings/{drm/exynos/hdmiddc.txt =>
video/exynos_hdmiddc.txt} (100%)
 rename Documentation/devicetree/bindings/{drm/exynos/hdmiphy.txt =>
video/exynos_hdmiphy.txt} (100%)
 rename Documentation/devicetree/bindings/{drm/exynos/mixer.txt =>
video/exynos_mixer.txt} (100%)
 create mode 12 arch/arm/boot/dts/include/dt-bindings
 create mode 100644 include/dt-bindings/gpio/gpio.h
 create mode 100644 include/dt-bindings/interrupt-controller/arm-gic.h
 create mode 100644 include/dt-bindings/interrupt-controller/irq.h


--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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Re: [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates

[Gregory CLEMENT]

On 05/17/2013 05:20 PM, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
> 
> Signed-off-by: Lorenzo Pieralisi 
> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi 
> b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 272bbc6..2407903 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -23,8 +23,12 @@
>   compatible = "marvell,armada-370-xp";
>  
>   cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
>   cpu@0 {
>   compatible = "marvell,sheeva-v7";
> + device_type = "cpu";
> + reg = <0>;
>   };
>   };
>  
> 

Acked-by: Gregory CLEMENT 

-- 
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes

[Lorenzo Pieralisi]

On Fri, May 17, 2013 at 05:31:18PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
>  wrote:
> > The introduction of the cpu-map topology node in the cpus node implies
> > that cpus node might have children that are not cpu nodes. The DT
> > parsing code needs updating otherwise it would check for cpu nodes
> > properties in nodes that are not required to contain them, resulting
> > in warnings that have no bearing on bindings defined in the dts source file.
> 
> Great, so a new DT with cpu-map entries may not work with old kernels.
> Please check the behavior. This should go to stable kernels.

You are right, and I do not see any other solution if we want the
cpu-map node to live in the cpus node; at the time we added the cpus/cpu
bindings we thought that the cpus node's children would be restricted to cpu
nodes, and well, we are changing that, this is one of the consequences.

Yes, this patch should go to stable kernels, I will do that.

Lorenzo

> Rob
> 
> >
> > Signed-off-by: Lorenzo Pieralisi 
> > ---
> >  arch/arm/kernel/devtree.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> > index 5af04f6..904cad5 100644
> > --- a/arch/arm/kernel/devtree.c
> > +++ b/arch/arm/kernel/devtree.c
> > @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> > for_each_child_of_node(cpus, cpu) {
> > u32 hwid;
> >
> > +   if (of_node_cmp(cpu->type, "cpu"))
> > +   continue;
> > +
> > pr_debug(" * %s...\n", cpu->full_name);
> > /*
> >  * A device tree containing CPU nodes with missing "reg"
> > --
> > 1.8.2.2
> >
> >
> > ___
> > devicetree-discuss mailing list
> > devicetree-discuss@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
> 

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Re: [PATCH] : fix compilation warnings with DT disabled

[Grant Likely]

On Thu, May 16, 2013 at 11:44 PM, Rob Herring  wrote:
>> I hoped to see this fix in 3.10-rc1. Is there any hope to see it in
>> 3.10-rc's?
>> The code it fixes the warnings in is already in Linus tree.
>
> So I had this queued up, but Grant did not send DT update to Linus for
> 3.10. The main thing we had was the preprocessor support and that went
> thru arm-soc tree. I plan to send this and other fixes to Linus for
> 3.10.

I got gun shy from the gpio stuff and fixated on better testing of my
tree. Everything in my tree is bug fixes so I'll be sending the pull
request today

g.
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Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes

[Rob Herring]

On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
 wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.

Great, so a new DT with cpu-map entries may not work with old kernels.
Please check the behavior. This should go to stable kernels.

Rob

>
> Signed-off-by: Lorenzo Pieralisi 
> ---
>  arch/arm/kernel/devtree.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> for_each_child_of_node(cpus, cpu) {
> u32 hwid;
>
> +   if (of_node_cmp(cpu->type, "cpu"))
> +   continue;
> +
> pr_debug(" * %s...\n", cpu->full_name);
> /*
>  * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
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Re: [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update

[Nicolas Pitre]

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> DT cpu map parsing code must be made compliant with the latest cpus/cpu
> nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
> function with checks and additional parsing rules.
> 
> Uniprocessor systems predating v7 do not parse the cpus node at all
> since the reg property is meaningless on those systems.
> 
> Device trees for 64-bit systems can be taken as device tree input also
> for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
> are zeroed as required in the respective fields and detects automatically
> the cpus node #address-cells value so that device tree written for
> 64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
> be taken as input. The correct device tree entries are to be set up by the
> boot loader, kernel code just checks that device tree entries in the cpus
> node are as expected for a 32-bit CPU (reg[63:24] == 0).
> 
> cpu node entries with invalid reg property or containing duplicates are
> ignored and the device tree parsing is not stopped anymore when such
> entries are encountered, the device tree cpu node entry is just skipped.
> 
> A device tree with cpu nodes missing the boot CPU MPIDR is considered
> an error and the kernel flags this up as such to trigger firmware updates.
> 
> Signed-off-by: Lorenzo Pieralisi 

Acked-by: Nicolas Pitre 


> ---
>  arch/arm/kernel/devtree.c | 146 
> --
>  1 file changed, 88 insertions(+), 58 deletions(-)
> 
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 0905502..80d6cf24 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -23,6 +23,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
>   */
>  void __init arm_dt_init_cpu_maps(void)
>  {
> - /*
> -  * Temp logical map is initialized with UINT_MAX values that are
> -  * considered invalid logical map entries since the logical map must
> -  * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
> -  * read as 0.
> -  */
>   struct device_node *cpu, *cpus;
> - u32 i, j, cpuidx = 1;
> + u32 i, ac, cpuidx = 1;
> + int len;
>   u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>  
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>   bool bootcpu_valid = false;
>   cpus = of_find_node_by_path("/cpus");
>  
> - if (!cpus)
> + if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
>   return;
>  
> + if (of_property_read_u32(cpus, "#address-cells", &ac)) {
> + pr_warn("%s invalid #address-cells\n", cpus->full_name);
> + ac = of_n_addr_cells(cpus);
> + }
> + /*
> +  * The boot CPU knows its MPIDR and initialize it
> +  * to allow DT boot CPU detection.
> +  */
> + cpu_logical_map(0) = mpidr;
> +
>   for_each_child_of_node(cpus, cpu) {
> - u32 hwid;
> + u64 hwid64;
> + u32 hwid32;
> + const __be32 *prop;
>  
>   if (of_node_cmp(cpu->type, "cpu"))
>   continue;
>  
>   pr_debug(" * %s...\n", cpu->full_name);
>   /*
> -  * A device tree containing CPU nodes with missing "reg"
> -  * properties is considered invalid to build the
> -  * cpu_logical_map.
> +  * A CPU node with missing or wrong "reg" property is
> +  * considered invalid to build a cpu_logical_map entry.
>*/
> - if (of_property_read_u32(cpu, "reg", &hwid)) {
> - pr_debug(" * %s missing reg property\n",
> -  cpu->full_name);
> - return;
> + prop = of_get_property(cpu, "reg", &len);
> + if (!prop || len < (ac * sizeof(*prop))) {
> + pr_warn(" * %s node missing/wrong reg property, 
> skipped\n",
> + cpu->full_name);
> + goto next;
>   }
>  
>   /*
> -  * 8 MSBs must be set to 0 in the DT since the reg property
> -  * defines the MPIDR[23:0].
> +  * Always read reg as u64 value.
> +  * For dts with #address-cells == 1 hwid64[63:32]
> +  * will be set to 0 by of_read_number.
> +  * Toss away the top 32 bits and store value in hwid32.
>*/
> - if (hwid & ~MPIDR_HWID_BITMASK)
> - return;
> -
> + hwid32 = hwid64 = of_read_number(prop, ac);
> + /*
> +  * hwid64[63:24] must be always be 0 since the reg
> +  * property defines the MPIDR[23:0] bits regardless
> +  * of the cpus node #address-cel

Re: [PATCH v6] ARM:dts:omap4-panda: Update the LED support for the panda DTS

[Nishanth Menon]

On 11:02-20130517, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
> 
> A1-A3 = gpio_wk7
> ES = gpio_110
> 
> There is no change to LED D2
> 
> Abstract away the pinmux and the LED definitions for the two boards into
> the respective DTS files.
> 
> Signed-off-by: Dan Murphy 
> ---
> Changes in this version:
>   - review comments incorporated.
> Previous version of this patch was discussed in:
>   https://patchwork.kernel.org/patch/2582771/
one minor nit,
$subject could do with space after the ':'
otherwise, it looks fine to me. Will suggest waiting for further
reviewers if they have an opinion prior to a new rev.

> 
>  arch/arm/boot/dts/omap4-panda-common.dtsi |   16 +++-
>  arch/arm/boot/dts/omap4-panda-es.dts  |   28 
>  2 files changed, 43 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi 
> b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 03bd60d..5fd59b3 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -16,8 +16,13 @@
>   reg = <0x8000 0x4000>; /* 1 GB */
>   };
>  
> - leds {
> + leds: leds {
>   compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + &led_wkgpio_pins
> + >;
> +
>   heartbeat {
>   label = "pandaboard::status1";
>   gpios = <&gpio1 7 0>;
> @@ -137,6 +142,15 @@
>   };
>  };
>  
> +&omap4_pmx_wkup {
> + led_wkgpio_pins: pinmux_leds_wkpins {
> + pinctrl-single,pins = <
> + 0x1a 0x3/* gpio_wk7 OUTPUT | MODE 3 */
> + 0x1c 0x3/* gpio_wk8 OUTPUT | MODE 3 */
> + >;
> + };
> +};
> +
>  &i2c1 {
>   pinctrl-names = "default";
>   pinctrl-0 = <&i2c1_pins>;
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts 
> b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..c968a3b 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,31 @@
>   0x5e 0x100  /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>   >;
>  };
> +
> +&omap4_pmx_core {
> + led_gpio_pins: gpio_led_pmx {
> + pinctrl-single,pins = <
> + 0xb6 0x3/* gpio_110 OUTPUT | MODE 3 */
> + >;
> + };
> +};
> +
> +&led_wkgpio_pins {
> + pinctrl-single,pins = <
> + 0x1c 0x3/* gpio_wk8 OUTPUT | MODE 3 */
> + >;
> +};
> +
> +&leds {
> + pinctrl-0 = <
> + &led_gpio_pins
> + &led_wkgpio_pins
> + >;
> +
> + heartbeat {
> + gpios = <&gpio4 14 0>;
> + };
> + mmc {
> + gpios = <&gpio1 8 0>;
> + };
> +};

-- 
Regards,
Nishanth Menon
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[GIT PULL] ARM DT topology bindings

[Lorenzo Pieralisi]

Hi Grant, Rob,

since it looks like we reached agreement on DT topology bindings for ARM
please pull the bindings documentation so that code relying on the
topology to be published and set in stone can be released and can stabilize.

The topology documentation relies on updates to the cpus/cpu nodes bindings
that I have just posted:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/169083.html

I do not know if you prefer to merge both documents at once or we can merge
this document first waiting for the other patchset to get merged, please
let me know.

Thank you very much indeed,
Lorenzo

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

  Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

  git://linux-arm.org/linux-2.6-lp.git dt-topology

for you to fetch changes up to 9cb1b6c8d59f09e51c87ac812b83d0350151ed3b:

  Documentation: DT: arm: define CPU topology bindings (2013-05-17 16:40:12 
+0100)


Lorenzo Pieralisi (1):
  Documentation: DT: arm: define CPU topology bindings

 Documentation/devicetree/bindings/arm/topology.txt | 492 +
 1 file changed, 492 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/topology.txt

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Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Nicolas Pitre]

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
> 
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - define 32/64 dts compatibility settings
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
> 
> Signed-off-by: Lorenzo Pieralisi 

Acked-by: Nicolas Pitre 


> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 459 
> ++---
>  1 file changed, 412 insertions(+), 47 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
> b/Documentation/devicetree/bindings/arm/cpus.txt
> index f32494d..3fc0c11 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -1,77 +1,442 @@
> -* ARM CPUs binding description
> +=
> +ARM CPUs bindings
> +=
>  
>  The device tree allows to describe the layout of CPUs in a system through
>  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>  defining properties for every cpu.
>  
> -Bindings for CPU nodes follow the ePAPR standard, available from:
> -
> -http://devicetree.org
> -
> -For the ARM architecture every CPU node must contain the following 
> properties:
> -
> -- device_type:   must be "cpu"
> -- reg:   property matching the CPU MPIDR[23:0] register bits
> - reg[31:24] bits must be set to 0
> -- compatible:should be one of:
> - "arm,arm1020"
> - "arm,arm1020e"
> - "arm,arm1022"
> - "arm,arm1026"
> - "arm,arm720"
> - "arm,arm740"
> - "arm,arm7tdmi"
> - "arm,arm920"
> - "arm,arm922"
> - "arm,arm925"
> - "arm,arm926"
> - "arm,arm940"
> - "arm,arm946"
> - "arm,arm9tdmi"
> - "arm,cortex-a5"
> - "arm,cortex-a7"
> - "arm,cortex-a8"
> - "arm,cortex-a9"
> - "arm,cortex-a15"
> - "arm,arm1136"
> - "arm,arm1156"
> - "arm,arm1176"
> - "arm,arm11mpcore"
> - "faraday,fa526"
> - "intel,sa110"
> - "intel,sa1100"
> - "marvell,feroceon"
> - "marvell,mohawk"
> - "marvell,xsc3"
> - "marvell,xscale"
> -
> -Example:
> +Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
> +
> +https://www.power.org/documentation/epapr-version-1-1/
> +
> +with updates for 32-bit and 64-bit ARM systems provided in this document.
> +
> +
> +Convention used in this document
> +
> +
> +This document follows the conventions described in the ePAPR v1.1, with
> +the addition:
> +
> +- square brackets define bitfields, eg reg[7:0] value of the bitfield in
> +  the reg property contained in bits 7 down to 0
> +
> +=
> +cpus and cpu node bindings definition
> +=
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> + Description: Container of cpu nodes
> +
> + The node name must be "cpus".
> +
> + A cpus node must define the following properties:
> +
> + - #address-cells
> + Usage: required
> + Value type: 
> +
> + Definition depends on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> +   value must be 0.
> + # On 32-bit ARM 11 MPcore, ARM v7 or later systems
> +   value must be 1.
> + # On ARM v8 64-bit systems value must be set to 1
> +   or 2. Refer to the cpu node's reg property
> +   description for allowed configurations.
> +
> + - #size-cells
> + Usage: required
> + Value type: 
> + Definition: must be set to 0
> +
> +- cpu node
> +
> + Description: Describes a CPU in an ARM based system
> +
> + PROPERTIES
> +
> + - device_type
> + Usage: required
> + Value type: 
> + Definition: must be "cpu"
> + - reg
> + Usage and definition depend on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> +   this property is optional since they do not define
> +   any register that provides a CPU identifier.
>

Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes

[Nicolas Pitre]

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
> 
> Signed-off-by: Lorenzo Pieralisi 

Acked-by: Nicolas Pitre 



> ---
>  arch/arm/kernel/devtree.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
>   for_each_child_of_node(cpus, cpu) {
>   u32 hwid;
>  
> + if (of_node_cmp(cpu->type, "cpu"))
> + continue;
> +
>   pr_debug(" * %s...\n", cpu->full_name);
>   /*
>* A device tree containing CPU nodes with missing "reg"
> -- 
> 1.8.2.2
> 
> 
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Re: [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization

[Nicolas Pitre]

On Fri, 17 May 2013, Lorenzo Pieralisi wrote:

> The __cpu_logical_map array is statically initialized to 0, which is a valid
> MPIDR value. To prevent issues with the current implementation, this patch
> defines an MPIDR_INVALID value, and statically initializes the
> __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
> tmp_map array used to stash DT reg properties while parsing DT are initialized
> with the MPIDR_INVALID value as well for consistency.
> 
> Signed-off-by: Lorenzo Pieralisi 
> CC: Will Deacon 

Acked-by: Nicolas Pitre 


> ---
>  arch/arm/include/asm/cputype.h  | 2 ++
>  arch/arm/include/asm/smp_plat.h | 2 +-
>  arch/arm/kernel/devtree.c   | 2 +-
>  arch/arm/kernel/setup.c | 2 +-
>  4 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 7652712..dba62cb 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -32,6 +32,8 @@
>  
>  #define MPIDR_HWID_BITMASK 0xFF
>  
> +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> +
>  #define MPIDR_LEVEL_BITS 8
>  #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
>  
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index aaa61b6..e789832 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
>  /*
>   * Logical CPU mapping.
>   */
> -extern int __cpu_logical_map[];
> +extern u32 __cpu_logical_map[];
>  #define cpu_logical_map(cpu) __cpu_logical_map[cpu]
>  /*
>   * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 904cad5..0905502 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
>   u32 i, j, cpuidx = 1;
>   u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>  
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
> + u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>   bool bootcpu_valid = false;
>   cpus = of_find_node_by_path("/cpus");
>  
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 6ae71b7..eeac924 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -457,7 +457,7 @@ void notrace cpu_init(void)
>   : "r14");
>  }
>  
> -int __cpu_logical_map[NR_CPUS];
> +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>  
>  void __init smp_setup_processor_id(void)
>  {
> -- 
> 1.8.2.2
> 
> 
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[RFC PATCH v4 10/18] ARM: dts: omap: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/omap2.dtsi | 6 +-
 arch/arm/boot/dts/omap3.dtsi | 5 +
 arch/arm/boot/dts/omap4.dtsi | 7 +++
 arch/arm/boot/dts/omap5.dtsi | 7 +++
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..4aac404 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
};
 
cpus {
-   cpu@0 {
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
compatible = "arm,arm1136jf-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..ba05d7f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
};
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a8";
+   device_type = "cpu";
+   reg = <0x0>;
};
};
 
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..33a9450 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
};
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
next-level-cache = <&L2>;
+   reg = <0x0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
next-level-cache = <&L2>;
+   reg = <0x1>;
};
};
 
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..35a6536 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
};
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
cpu@0 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
+   reg = <0x0>;
};
cpu@1 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
+   reg = <0x1>;
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 08/18] ARM: dts: imx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Shawn Guo 
---
 arch/arm/boot/dts/imx23.dtsi  | 8 ++--
 arch/arm/boot/dts/imx28.dtsi  | 8 ++--
 arch/arm/boot/dts/imx6dl.dtsi | 2 ++
 arch/arm/boot/dts/imx6q.dtsi  | 4 
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0..587ceef 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
};
 
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb..4c10a19 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
};
 
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a..62dc781 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
 
cpu@0 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
 
cpu@1 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e6758..dc54a72 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
 
cpu@0 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
@@ -39,18 +40,21 @@
 
cpu@1 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
 
cpu@2 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
 
cpu@3 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
-- 
1.8.2.2


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[RFC PATCH v4 16/18] ARM: dts: spear: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Viresh Kumar 
---
 arch/arm/boot/dts/spear13xx.dtsi | 2 ++
 arch/arm/boot/dts/spear3xx.dtsi  | 8 ++--
 arch/arm/boot/dts/spear600.dtsi  | 8 ++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd..4382547 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
 
cpu@0 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
 
cpu@1 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d..f0e3fcf 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
interrupt-parent = <&vic>;
 
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc..9f60a7b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
compatible = "st,spear600";
 
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/armada-370-xp.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi 
b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..2407903 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
compatible = "marvell,armada-370-xp";
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
cpu@0 {
compatible = "marvell,sheeva-v7";
+   device_type = "cpu";
+   reg = <0>;
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates

[Lorenzo Pieralisi]

In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.

Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition

Signed-off-by: Lorenzo Pieralisi 
---
 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++---
 1 file changed, 412 insertions(+), 47 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..3fc0c11 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,442 @@
-* ARM CPUs binding description
+=
+ARM CPUs bindings
+=
 
 The device tree allows to describe the layout of CPUs in a system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type: must be "cpu"
-- reg: property matching the CPU MPIDR[23:0] register bits
-   reg[31:24] bits must be set to 0
-- compatible:  should be one of:
-   "arm,arm1020"
-   "arm,arm1020e"
-   "arm,arm1022"
-   "arm,arm1026"
-   "arm,arm720"
-   "arm,arm740"
-   "arm,arm7tdmi"
-   "arm,arm920"
-   "arm,arm922"
-   "arm,arm925"
-   "arm,arm926"
-   "arm,arm940"
-   "arm,arm946"
-   "arm,arm9tdmi"
-   "arm,cortex-a5"
-   "arm,cortex-a7"
-   "arm,cortex-a8"
-   "arm,cortex-a9"
-   "arm,cortex-a15"
-   "arm,arm1136"
-   "arm,arm1156"
-   "arm,arm1176"
-   "arm,arm11mpcore"
-   "faraday,fa526"
-   "intel,sa110"
-   "intel,sa1100"
-   "marvell,feroceon"
-   "marvell,mohawk"
-   "marvell,xsc3"
-   "marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+
+Convention used in this document
+
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+  the reg property contained in bits 7 down to 0
+
+=
+cpus and cpu node bindings definition
+=
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+   Description: Container of cpu nodes
+
+   The node name must be "cpus".
+
+   A cpus node must define the following properties:
+
+   - #address-cells
+   Usage: required
+   Value type: 
+
+   Definition depends on ARM architecture version and
+   configuration:
+
+   # On uniprocessor ARM architectures previous to v7
+ value must be 0.
+   # On 32-bit ARM 11 MPcore, ARM v7 or later systems
+ value must be 1.
+   # On ARM v8 64-bit systems value must be set to 1
+ or 2. Refer to the cpu node's reg property
+ description for allowed configurations.
+
+   - #size-cells
+   Usage: required
+   Value type: 
+   Definition: must be set to 0
+
+- cpu node
+
+   Description: Describes a CPU in an ARM based system
+
+   PROPERTIES
+
+   - device_type
+   Usage: required
+   Value type: 
+   Definition: must be "cpu"
+   - reg
+   Usage and definition depend on ARM architecture version and
+   configuration:
+
+   # On uniprocessor ARM architectures previous to v7
+ this property is optional since they do not define
+ any register that provides a CPU identifier.
+ Any value set in the reg property for these CPUs
+ should be ignored.
+
+   # On ARM 11 MPcore based systems this property is
+ required and matches the CPUID[11:0]

[RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/am33xx.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..6827853 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -26,8 +26,12 @@
};
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
+   device_type = "cpu";
+   reg = <0>;
 
/*
 * To consider voltage drop between PMIC and SoC,
-- 
1.8.2.2


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[RFC PATCH v4 09/18] ARM: dts: lpc32xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/lpc32xx.dtsi | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f48..3abebb7 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
interrupt-parent = <&mic>;
 
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 06/18] ARM: dts: at91: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Nicolas Ferre 
---
 arch/arm/boot/dts/at91rm9200.dtsi  | 6 +-
 arch/arm/boot/dts/at91sam9260.dtsi | 8 ++--
 arch/arm/boot/dts/at91sam9263.dtsi | 8 ++--
 arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++--
 arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++--
 arch/arm/boot/dts/at91sam9x5.dtsi  | 8 ++--
 arch/arm/boot/dts/sama5d3.dtsi | 2 ++
 7 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi 
b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..0af879a 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -35,8 +35,12 @@
ssc2 = &ssc2;
};
cpus {
-   cpu@0 {
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
compatible = "arm,arm920t";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi 
b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..e1ba7ea 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -32,8 +32,12 @@
ssc0 = &ssc0;
};
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi 
b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..fcd38f8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -29,8 +29,12 @@
ssc1 = &ssc1;
};
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi 
b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..479a062 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -35,8 +35,12 @@
ssc1 = &ssc1;
};
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi 
b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..01df681 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -31,8 +31,12 @@
ssc0 = &ssc0;
};
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi 
b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..6d8bd671 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -33,8 +33,12 @@
ssc0 = &ssc0;
};
cpus {
-   cpu@0 {
-   compatible = "arm,arm926ejs";
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
};
};
 
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..5325371 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -36,7 +36,9 @@
};
cpus {
cpu@0 {
+   device_type = "cpu";
compatible = "arm,cortex-a5";
+   reg = <0x0>;
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/pxa2xx.dtsi | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad3..a5e90f0 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
};
 
cpus {
-   cpu@0 {
-   compatible = "arm,xscale";
+   #address-cells = <0>;
+   #size-cells = <0>;
+   cpu {
+   compatible = "marvell,xscale";
+   device_type = "cpu";
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Barry Song 
---
 arch/arm/boot/dts/prima2.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..02edd89 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
#size-cells = <0>;
 
cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
-- 
1.8.2.2


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[RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update

[Lorenzo Pieralisi]

DT cpu map parsing code must be made compliant with the latest cpus/cpu
nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
function with checks and additional parsing rules.

Uniprocessor systems predating v7 do not parse the cpus node at all
since the reg property is meaningless on those systems.

Device trees for 64-bit systems can be taken as device tree input also
for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
are zeroed as required in the respective fields and detects automatically
the cpus node #address-cells value so that device tree written for
64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
be taken as input. The correct device tree entries are to be set up by the
boot loader, kernel code just checks that device tree entries in the cpus
node are as expected for a 32-bit CPU (reg[63:24] == 0).

cpu node entries with invalid reg property or containing duplicates are
ignored and the device tree parsing is not stopped anymore when such
entries are encountered, the device tree cpu node entry is just skipped.

A device tree with cpu nodes missing the boot CPU MPIDR is considered
an error and the kernel flags this up as such to trigger firmware updates.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/kernel/devtree.c | 146 --
 1 file changed, 88 insertions(+), 58 deletions(-)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 0905502..80d6cf24 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
  */
 void __init arm_dt_init_cpu_maps(void)
 {
-   /*
-* Temp logical map is initialized with UINT_MAX values that are
-* considered invalid logical map entries since the logical map must
-* contain a list of MPIDR[23:0] values where MPIDR[31:24] must
-* read as 0.
-*/
struct device_node *cpu, *cpus;
-   u32 i, j, cpuidx = 1;
+   u32 i, ac, cpuidx = 1;
+   int len;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-   u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
 
-   if (!cpus)
+   if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
return;
 
+   if (of_property_read_u32(cpus, "#address-cells", &ac)) {
+   pr_warn("%s invalid #address-cells\n", cpus->full_name);
+   ac = of_n_addr_cells(cpus);
+   }
+   /*
+* The boot CPU knows its MPIDR and initialize it
+* to allow DT boot CPU detection.
+*/
+   cpu_logical_map(0) = mpidr;
+
for_each_child_of_node(cpus, cpu) {
-   u32 hwid;
+   u64 hwid64;
+   u32 hwid32;
+   const __be32 *prop;
 
if (of_node_cmp(cpu->type, "cpu"))
continue;
 
pr_debug(" * %s...\n", cpu->full_name);
/*
-* A device tree containing CPU nodes with missing "reg"
-* properties is considered invalid to build the
-* cpu_logical_map.
+* A CPU node with missing or wrong "reg" property is
+* considered invalid to build a cpu_logical_map entry.
 */
-   if (of_property_read_u32(cpu, "reg", &hwid)) {
-   pr_debug(" * %s missing reg property\n",
-cpu->full_name);
-   return;
+   prop = of_get_property(cpu, "reg", &len);
+   if (!prop || len < (ac * sizeof(*prop))) {
+   pr_warn(" * %s node missing/wrong reg property, 
skipped\n",
+   cpu->full_name);
+   goto next;
}
 
/*
-* 8 MSBs must be set to 0 in the DT since the reg property
-* defines the MPIDR[23:0].
+* Always read reg as u64 value.
+* For dts with #address-cells == 1 hwid64[63:32]
+* will be set to 0 by of_read_number.
+* Toss away the top 32 bits and store value in hwid32.
 */
-   if (hwid & ~MPIDR_HWID_BITMASK)
-   return;
-
+   hwid32 = hwid64 = of_read_number(prop, ac);
+   /*
+* hwid64[63:24] must be always be 0 since the reg
+* property defines the MPIDR[23:0] bits regardless
+* of the cpus node #address-cells value.
+*/
+   if (hwid64 & ~MPIDR_HWID_BITMASK) {
+   pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, 
got %#016llx, skipped

[RFC PATCH v4 11/18] ARM: dts: picoxcell: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi 
b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c20..533919e 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
 
cpus {
-   #address-cells = <1>;
+   #address-cells = <0>;
#size-cells = <0>;
 
-   cpu@0 {
-   compatible = "arm,1176jz-s";
+   cpu {
+   compatible = "arm,arm1176jz-s";
+   device_type = "cpu";
clock-frequency = <4>;
-   reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi 
b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d..ab3e800 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
 
cpus {
-   #address-cells = <1>;
+   #address-cells = <0>;
#size-cells = <0>;
 
-   cpu@0 {
-   compatible = "arm,1176jz-s";
+   cpu {
+   compatible = "arm,arm1176jz-s";
+   device_type = "cpu";
cpu-clock = <&arm_clk>, "cpu";
-   reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
-- 
1.8.2.2


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[RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization

[Lorenzo Pieralisi]

The __cpu_logical_map array is statically initialized to 0, which is a valid
MPIDR value. To prevent issues with the current implementation, this patch
defines an MPIDR_INVALID value, and statically initializes the
__cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
tmp_map array used to stash DT reg properties while parsing DT are initialized
with the MPIDR_INVALID value as well for consistency.

Signed-off-by: Lorenzo Pieralisi 
CC: Will Deacon 
---
 arch/arm/include/asm/cputype.h  | 2 ++
 arch/arm/include/asm/smp_plat.h | 2 +-
 arch/arm/kernel/devtree.c   | 2 +-
 arch/arm/kernel/setup.c | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..dba62cb 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -32,6 +32,8 @@
 
 #define MPIDR_HWID_BITMASK 0xFF
 
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..e789832 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
 #define cpu_logical_map(cpu)   __cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 904cad5..0905502 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
u32 i, j, cpuidx = 1;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-   u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+   u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6ae71b7..eeac924 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
: "r14");
 }
 
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 
 void __init smp_setup_processor_id(void)
 {
-- 
1.8.2.2


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[RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/boot/dts/exynos5440.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi 
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..646677e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -38,18 +38,22 @@
#size-cells = <0>;
 
cpu@0 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
cpu@1 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
cpu@2 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
cpu@3 {
+   device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
-- 
1.8.2.2


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[RFC PATCH v4 00/18] ARM: DT cpu bindings updates

[Lorenzo Pieralisi]

This patchset is an update of a previous posting:

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165219.html

v4 changes:

- Replaced WARN* with pr_warn
- Removed tmp_map in arm_dt_init_cpu_maps()
- Rebased against 3.10-rc1
- Patched additional atmel and sunxi dts files
- Removed BUG_ON on !bootcpu_valid, now flagged up as an error
- Added code to reset invalid entries in cpu_logical_map after DT parsing

v3 changes:

- More dts fixes of in-kernel dts
- Defined ARM v8 behaviour with different cpus node #address-cells
- Added pre ARM11 processors suffixes in the cpu node compatible list
- Reordered series
- Reworded #address-cells definition
- Added ARM v8 - cores running on AArch32 bindings example
- Moved WARN* calls on one line to prevent grepping issues

v2 changes:

- Reworded DT cpu bindings
- Split the set, with per-mach specific dts updates
- Updated cpu node compatible string list
- Defined behaviour of OS running on v8 in AArch32

The introduction of DT cpus/cpu bindings for ARM requires well established
rules to enforce the reg property definition for 32-bit and 64-bit ARM
processors, inclusive of legacy and current uniprocessor/SMP systems.

ARM 64 bit architecture also requires dtb compiled for 64-bit configurations
to be reused for kernels running in 32 bit mode, so the cpus/cpu bindings
specification must be made compliant to cope with this configuration.

Patch #1-#2 of this series are fixes and are included to have a clean patch
series and should get reviewed and merged separately.

Patch #3-18, along with some kernel fixes related to DT parsing function,
update the cpu node bindings and in kernel dts files to cope with legacy,
current and upcoming ARM systems.

In-kernel device tree source files are updated to comply with the latest
specification, so thorough testing is required in order to validate all
changes on all affected ARM systems, in particular systems with exotic
MPIDR configurations that are likely to break with the changes provided.

Code relying on the reg property size to be 4-bytes must be updated so that
dtbs compiled for 64-bit kernels can also be used to boot a 32-bit system.

Lorenzo Pieralisi (18):
  ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
  ARM: kernel: fix __cpu_logical_map default initialization
  Documentation: devicetree: arm: cpus/cpu nodes bindings updates
  ARM: dts: am33xx: cpus/cpu nodes dts updates
  ARM: dts: armada-370-xp: cpus/cpu node dts updates
  ARM: dts: at91: cpus/cpu node dts updates
  ARM: dts: exynos5440: cpus/cpu nodes dts updates
  ARM: dts: imx: cpus/cpu nodes dts updates
  ARM: dts: lpc32xx: cpus/cpu nodes dts updates
  ARM: dts: omap: cpus/cpu nodes dts updates
  ARM: dts: picoxcell: cpus/cpu nodes dts updates
  ARM: dts: prima2: cpus/cpu node dts updates
  ARM: dts: pxa2xx: cpus/cpu nodes dts updates
  ARM: dts: r8a7740: cpus/cpu nodes dts updates
  ARM: dts: sh7372: cpus/cpu nodes dts updates
  ARM: dts: spear: cpus/cpu nodes dts updates
  ARM: dts: sunxi: cpus/cpu nodes dts updates
  ARM: DT: kernel: DT cpus/cpu node bindings update

 Documentation/devicetree/bindings/arm/cpus.txt | 459 ++---
 arch/arm/boot/dts/am33xx.dtsi  |   4 +
 arch/arm/boot/dts/armada-370-xp.dtsi   |   4 +
 arch/arm/boot/dts/at91rm9200.dtsi  |   6 +-
 arch/arm/boot/dts/at91sam9260.dtsi |   8 +-
 arch/arm/boot/dts/at91sam9263.dtsi |   8 +-
 arch/arm/boot/dts/at91sam9g45.dtsi |   8 +-
 arch/arm/boot/dts/at91sam9n12.dtsi |   8 +-
 arch/arm/boot/dts/at91sam9x5.dtsi  |   8 +-
 arch/arm/boot/dts/exynos5440.dtsi  |   4 +
 arch/arm/boot/dts/imx23.dtsi   |   8 +-
 arch/arm/boot/dts/imx28.dtsi   |   8 +-
 arch/arm/boot/dts/imx6dl.dtsi  |   2 +
 arch/arm/boot/dts/imx6q.dtsi   |   4 +
 arch/arm/boot/dts/lpc32xx.dtsi |   8 +-
 arch/arm/boot/dts/omap2.dtsi   |   6 +-
 arch/arm/boot/dts/omap3.dtsi   |   5 +
 arch/arm/boot/dts/omap4.dtsi   |   7 +
 arch/arm/boot/dts/omap5.dtsi   |   7 +
 arch/arm/boot/dts/picoxcell-pc3x2.dtsi |   8 +-
 arch/arm/boot/dts/picoxcell-pc3x3.dtsi |   8 +-
 arch/arm/boot/dts/prima2.dtsi  |   2 +
 arch/arm/boot/dts/pxa2xx.dtsi  |   7 +-
 arch/arm/boot/dts/r8a7740.dtsi |   4 +
 arch/arm/boot/dts/sama5d3.dtsi |   2 +
 arch/arm/boot/dts/sh7372.dtsi  |   5 +
 arch/arm/boot/dts/spear13xx.dtsi   |   2 +
 arch/arm/boot/dts/spear3xx.dtsi|   8 +-
 arch/arm/boot/dts/spear600.dtsi|   8 +-
 arch/arm/boot/dts/sun4i-a10.dtsi   |   2 +
 arch/arm/boot/dts/sun5i-a13.dtsi   |   2 +
 arch/arm/include/asm/cputype.h |   2 +
 arch/arm/include/asm/smp_plat.h|   2 +-
 arch/arm/kern

[RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes

[Lorenzo Pieralisi]

The introduction of the cpu-map topology node in the cpus node implies
that cpus node might have children that are not cpu nodes. The DT
parsing code needs updating otherwise it would check for cpu nodes
properties in nodes that are not required to contain them, resulting
in warnings that have no bearing on bindings defined in the dts source file.

Signed-off-by: Lorenzo Pieralisi 
---
 arch/arm/kernel/devtree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..904cad5 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
for_each_child_of_node(cpus, cpu) {
u32 hwid;
 
+   if (of_node_cmp(cpu->type, "cpu"))
+   continue;
+
pr_debug(" * %s...\n", cpu->full_name);
/*
 * A device tree containing CPU nodes with missing "reg"
-- 
1.8.2.2


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[RFC PATCH v4 17/18] ARM: dts: sunxi: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
 arch/arm/boot/dts/sun5i-a13.dtsi | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..39a8f61 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,7 +17,9 @@
 
cpus {
cpu@0 {
+   device_type = "cpu";
compatible = "arm,cortex-a8";
+   reg = <0x0>;
};
};
 
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..00a2637 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -18,7 +18,9 @@
 
cpus {
cpu@0 {
+   device_type = "cpu";
compatible = "arm,cortex-a8";
+   reg = <0x0>;
};
};
 
-- 
1.8.2.2


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[RFC PATCH v4 15/18] ARM: dts: sh7372: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Simon Horman 
---
 arch/arm/boot/dts/sh7372.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..7bf020e 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
compatible = "renesas,sh7372";
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a8";
+   device_type = "cpu";
+   reg = <0x0>;
};
};
 };
-- 
1.8.2.2


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[RFC PATCH v4 14/18] ARM: dts: r8a7740: cpus/cpu nodes dts updates

[Lorenzo Pieralisi]

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.

Signed-off-by: Lorenzo Pieralisi 
Acked-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7740.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..8a831e9 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
compatible = "renesas,r8a7740";
 
cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0x0>;
};
};
 };
-- 
1.8.2.2


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[PATCH 3/5] ARM: at91: sam9x5ek add udc DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Cc: Nicolas Ferre 
---
 arch/arm/boot/dts/at91sam9x5ek.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi 
b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 19c8ebb..5e10027 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -52,6 +52,11 @@
status = "okay";
};
 
+   usb2: gadget@f803c000 {
+   atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+   };
+
i2c0: i2c@f801 {
status = "okay";
};
-- 
1.7.10.4

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[PATCH 4/5] ARM: at91: sam9g45 add udc DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Cc: Nicolas Ferre 
---
 arch/arm/boot/dts/at91sam9g45.dtsi |   62 
 arch/arm/mach-at91/at91sam9g45.c   |2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi 
b/arch/arm/boot/dts/at91sam9g45.dtsi
index f0091af..fccc488 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -582,6 +582,68 @@
pinctrl-0 = <&pinctrl_spi1>;
status = "disabled";
};
+
+   usb2: gadget@fff78000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "atmel,at91sam9rl-udc";
+   reg = <0x0060 0x8
+  0xfff78000 0x400>;
+   interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+   status = "disabled";
+
+   ep0 {
+   reg = <0>;
+   atmel,fifo-size = <64>;
+   atmel,nb-banks = <1>;
+   };
+
+   ep1 {
+   reg = <1>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep2 {
+   reg = <2>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep3 {
+   reg = <3>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep4 {
+   reg = <4>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep5 {
+   reg = <5>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep6 {
+   reg = <6>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+   };
};
 
nand0: nand@4000 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..95a418a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+   CLKDEV_CON_DEV_ID("hclk", "60.gadget", &utmi_clk),
+   CLKDEV_CON_DEV_ID("pclk", "60.gadget", &udphs_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID(NULL, "f200.gpio", &pioA_clk),
-- 
1.7.10.4

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[PATCH 5/5] ARM: at91: sam9m10g45ek add udc DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Cc: Nicolas Ferre 
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts 
b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 89c50d1..17665ef 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -112,6 +112,11 @@
reg = <0>;
};
};
+
+   usb2: gadget@fff78000 {
+   atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+   };
};
 
nand0: nand@4000 {
-- 
1.7.10.4

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[PATCH 2/5] ARM: at91: sam9x5 add udc DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Cc: Nicolas Ferre 
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   62 +
 arch/arm/mach-at91/at91sam9x5.c   |2 ++
 2 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi 
b/arch/arm/boot/dts/at91sam9x5.dtsi
index af91599..01a815d 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -645,6 +645,68 @@
status = "disabled";
};
 
+   usb2: gadget@f803c000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "atmel,at91sam9rl-udc";
+   reg = <0x0050 0x8
+  0xf803c000 0x400>;
+   interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+   status = "disabled";
+
+   ep0 {
+   reg = <0>;
+   atmel,fifo-size = <64>;
+   atmel,nb-banks = <1>;
+   };
+
+   ep1 {
+   reg = <1>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep2 {
+   reg = <2>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep3 {
+   reg = <3>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep4 {
+   reg = <4>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep5 {
+   reg = <5>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep6 {
+   reg = <6>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+   };
+
rtc@feb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfeb0 0x40>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec..2abee66 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("hclk", "60.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ohci_clk", "60.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "70.ehci", &uhphs_clk),
+   CLKDEV_CON_DEV_ID("hclk", "50.gadget", &utmi_clk),
+   CLKDEV_CON_DEV_ID("pclk", "50.gadget", &udphs_clk),
 };
 
 /*
-- 
1.7.10.4

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[PATCH 1/5] usb: add Atmel USBA UDC DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Allow to compile the driver all the time if AT91 enabled.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Cc: Nicolas Ferre 
Cc: linux-...@vger.kernel.org
---
 .../devicetree/bindings/usb/atmel-usb.txt  |   82 
 drivers/usb/gadget/Kconfig |2 +-
 drivers/usb/gadget/atmel_usba_udc.c|  214 +++-
 drivers/usb/gadget/atmel_usba_udc.h|1 +
 4 files changed, 244 insertions(+), 55 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt 
b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd215..878556b2 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,85 @@ usb1: gadget@fffa4000 {
interrupts = <10 4>;
atmel,vbus-gpio = <&pioC 5 0>;
 };
+
+Atmel High-Speed USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain macb interrupt
+ - ep childnode: To specifiy the number of endpoints and their properties.
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+
+usb2: gadget at fff78000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "atmel,at91sam9rl-udc";
+   reg = <0x0060 0x8
+  0xfff78000 0x400>;
+   interrupts = <27 4>;
+   atmel,vbus-gpio = <&pioB 19 0>;
+
+   ep0 {
+   reg = <0>;
+   atmel,fifo-size = <64>;
+   atmel,nb-banks = <1>;
+   };
+
+   ep1 {
+   reg = <1>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep2 {
+   reg = <2>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <2>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep3 {
+   reg = <3>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep4 {
+   reg = <4>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   };
+
+   ep5 {
+   reg = <5>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+
+   ep6 {
+   reg = <6>;
+   atmel,fifo-size = <1024>;
+   atmel,nb-banks = <3>;
+   atmel,can-dma;
+   atmel,can-isoc;
+   };
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 83300d9..5e47d50 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_LPC32XX
 
 config USB_ATMEL_USBA
tristate "Atmel USBA"
-   depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+   depends on AVR32 || ARCH_AT91
help
  USBA is the integrated high-speed USB Device controller on
  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c 
b/drivers/usb/gadget/atmel_usba_udc.c
index f2a970f..b3084b9 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -22,6 +22,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 
@@ -1835,9 +1837,143 @@ static int atmel_usba_stop(struct usb_gadget *gadget,
return 0;
 }
 
-static int __init usba_udc_probe(struct platform_device *pdev)
+#ifdef CONFIG_OF
+static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
+   struct usba_udc *udc)
+{
+   u32 val;
+   const char *name;
+   enum of_gpio_flags flags;
+   struct device_node *np = pdev->dev.of_node;
+   struct device_node *pp;
+   int i, ret;
+   struct usba_ep *eps, *ep;
+
+   udc->num_ep = 0;
+
+   udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+   &flags);
+   udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+   pp = NULL;
+   while ((pp = of_get_next_child(np, pp)))
+   udc->num_ep++;
+
+   eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
+  GFP_KERNEL);
+   if (!eps)
+   return ERR_PTR(-ENOMEM);

Re: [RFC 3/8] mfd:syscon: Introduce claim/read/write/release APIs

[Arnd Bergmann]

On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
> On 08/05/13 20:48, Arnd Bergmann wrote:
> I agree, my initial approach was having a dedicated driver specific to
> ST syscon, however syscon seems to do things very much similar to what
> we want, so I have integrated those 3 functions in syscon.
> Am happy to go back with my first approach of adding ST specific syscon
> driver if no one is actually going to benefit with such a change to
> syscon driver.

That would at least be less controversial.

> > Can you describe how your syscon registers are laid out?
> On STiH416 SOC we have 9 SYSCONF(aka System Configuration
> Registers)named banks/groups, each bank has its own memory map.
> Each sysconf bank has number of 32 bit registers which vary from bank to
> bank, like sysconf bank "sbc" has range from SYSTEM_CONFIG0 to
> SYSTEM_CONFIG999 where as  sysconf bank "front" has range of
> SYSTEM_CONFIG1000 to SYSTEM_CONFIG1999 and so on.
> 
> Each register is assigned with a unique SYCONF number, example:
> SYSTEM_CONFIG100, SYSTEM_CONFIG101 , .. and so on.
> Each sysconf contains bits of the IP configurations wired-up to the
> sysconf register bits.

Ok.

> As example:
> 
> - Each pinctrl entry for set of 8 pins uses around 8-10 sysconfig
> register to control pinconf and pin functions.
> - IPs like Ethernet have few bit like Ethernet-Mode selection external
> or internal phyclk wired up to bits in sysconf registers,
> - Few clocks are controlled by sysconf registers.
> - Reset to IPs are wired up to bits of sysconf same registers.
> - ARM core soft reset is wired up to the sysconf registers...
> And most of the IPs have similar requirements ..
> 
> Total layout of the sysconf changes per SOC, and the bit arrangements
> aswell, however the core IP(pinctrl, etherenet ...) and logic to drive
> those bits remains exactly same.

It sounds like you really need a driver with high-level interfaces
for the bits that change by each core and are needed by otherwise
identical drivers, like the Ethernet driver you mention.

I would not go as far as you did describing the individual bits in
the device node using these however. That driver can be layered on
top of the existing syscon driver, but hardcode the bits for each
SoC it knows of.

For drivers that are essentially just wrappers around sysconf,
I would make them one driver per SoC and use a low-level interface
but still hardcode the offsets in the driver instead of using DT
to find the registers.

The pinctrl and reset drivers are examples of this.

> In general the requirements of the sysconf support to the SOC/driver
> support is.
> 1> It should be able to read/write a sysconf register bits without
> having to "if" each SOC in the code. So that code is totally abstracted.
> Which is currently achieved by passing the information from the device
> trees and the driver just uses the property to get it.

The goal sounds fine, just the method is a bit more complex than necessary
here I think.

> 2> The infrastructure should protect the claimed registers from
> over-writing by other drivers. We do this by claim-read/write-release
> style API.

I don't understand this part. Is it about atomicity of accesses to
32-bit registers when you only want to change a bit? That is something
the regmap interface handles already.

If this is about drivers touching registers they should not touch
in the first place, I think it should not be needed at all, because
that would be a driver bug, and you can't really protect yourself
from broken drivers anyway.

> 3> The driver should be able to set a group of sysconf registers bits to
> a particular values before initialises the IP. I was thinking of doing
> this in a same way as pinctrl state.

That does not fit well with the model we use for other subsystems. If possible,
try to use the existing abstractions for clock, regulator, pinctrl, reset,
etc. and call generic interfaces from the driver. When that does not work,
create a high-level function call from your sysconf driver to do a particular
thing (e.g. stih_sysconf_ethernet_set_phy_mode()) rather than set up random
bits from the driver.

Arnd
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[PATCH 0/5 v3] ARM: at91: dt: add USBA support

[Jean-Christophe PLAGNIOL-VILLARD]

HI,

v3:
rebase againt 3.10-rc1 + dt macro cleanup

This patch serie finish to add the usb device support to dt for at91
with the usba support present on the last at91 generation since sam9g45

The following changes since commit b3f442b0eedbc20b5ce3f4a96530588d14901199:

  ARM: at91: udpate defconfigs (2013-05-17 15:05:08 +0200)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/for-3.11-usba

for you to fetch changes up to f24c9792c29803420a7bf7204223ef028191d449:

  ARM: at91: sam9m10g45ek add udc DT support (2013-05-17 22:05:46 +0800)


Jean-Christophe PLAGNIOL-VILLARD (5):
  usb: add Atmel USBA UDC DT support
  ARM: at91: sam9x5 add udc DT support
  ARM: at91: sam9x5ek add udc DT support
  ARM: at91: sam9g45 add udc DT support
  ARM: at91: sam9m10g45ek add udc DT support

 Documentation/devicetree/bindings/usb/atmel-usb.txt |   82 
+++
 arch/arm/boot/dts/at91sam9g45.dtsi  |   62 

 arch/arm/boot/dts/at91sam9m10g45ek.dts  |5 +
 arch/arm/boot/dts/at91sam9x5.dtsi   |   62 

 arch/arm/boot/dts/at91sam9x5ek.dtsi |5 +
 arch/arm/mach-at91/at91sam9g45.c|2 ++
 arch/arm/mach-at91/at91sam9x5.c |2 ++
 drivers/usb/gadget/Kconfig  |2 +-
 drivers/usb/gadget/atmel_usba_udc.c |  214 
++
 drivers/usb/gadget/atmel_usba_udc.h |1 +
 10 files changed, 382 insertions(+), 55 deletions(-)

Best Regards,
J.
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Re: [PATCH v5] ARM:dts:omap4-panda: Update the LED support for the panda DTS

[Nishanth Menon]

On 08:21-20130517, Dan Murphy wrote:
[...]
May be others with better DT experience can help here..
but here is a trick to reduce dts file changes:
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts 
> b/arch/arm/boot/dts/omap4-panda-es.dts
> index f1d8c21..08d2e38 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -34,3 +34,37 @@
>   0x5e 0x100  /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
>   >;
>  };
> +
> +&omap4_pmx_core {
> + led_gpio_pins: gpio_led_pmx {
> + pinctrl-single,pins = <
> + 0xb6 0x3/* gpio_110 OUTPUT | MODE 3 */
> + >;
> + };
> +};
> +
> +&led_wkgpio_pins {
> + pinctrl-single,pins = <
> + 0x1c 0x3/* gpio_wk8 OUTPUT | MODE 3 */
> + >;
> +};
> +
> +&leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
Normally, override  will either add (if new param) OR replace (if same param)
So the above two are superfluous.
> + pinctrl-0 = <
> + &led_gpio_pins
> + &led_wkgpio_pins
> + >;
These are needed
> +
> + heartbeat {
> + label = "pandaboard::status1";
can drop this
> + gpios = <&gpio4 14 0>;
needed
> + linux,default-trigger = "heartbeat";
can be dropped
> + };
> + mmc {
> + label = "pandaboard::status2";
could be dropped
> + gpios = <&gpio1 8 0>;
needed
> + linux,default-trigger = "mmc0";
could be dropped.

-- 
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Nishanth Menon
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Re: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370

[Jason Cooper]

On Fri, May 17, 2013 at 12:08:26AM -0700, Mike Turquette wrote:
> Quoting Jason Cooper (2013-05-16 08:06:16)
> > Mike, Sebastian,
> > 
> > On Thu, May 16, 2013 at 10:26:24AM +0200, Sebastian Hesselbarth wrote:
> > > On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> > > >Dear Mike Turquette,
> > > >
> > > >On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> > > >>Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > > >>>The Armada 370 has two gatable clocks for each PCIe interface, and we
> > > >>>want both of them to be enabled. We therefore make one of the two
> > > >>>clocks a child of the other, as we did for the sataX and sataXlnk
> > > >>>clocks on Armada XP.
> > > >>
> > > >>Ack for patches #5 and #6.  Do you want me to take them?
> > 
> > Thanks for the Ack!
> > 
> > > >I don't know, I guess with your Ack, it would be easier to carry them
> > > >through the Marvell maintainers and then the arm-soc tree, so that we
> > > >can test arm-soc and have all the pieces needed in here.
> > > >
> > > >That said, Sebastian Hesselbarth has submitted a big rework of the
> > > >mvebu clock drivers, which would conflict with this patch, and
> > > >Sebastian's rework would most likely go through your tree. If that's
> > > >the case, I guess it would be better to let you take #5 and #6 in this
> > > >patch series.
> > > 
> > > I also requested to take the restructure patches through ARM tree. They
> > > are only touching files in drivers/clk/mvebu and by taking them through
> > > ARM, we can update PCIe clock patches easily. The dependency between
> > > Thomas' and my patches basically is that I renamed files that Thomas
> > > now commits to. (I switched clk/mvebu from per-function files to per-soc
> > > files).
> > 
> > I agree.  My heart jumped into my throat a little there :)  Mike, if
> > it's ok with you, I'd prefer to take these through arm-soc.  Any merge
> > conflicts should be minimal.  And at any rate, resolving the conflicts
> > are *much* easier to handle than having arm-soc depend on an outside
> > tree (then Linus has to take care in the order he merges them, no
> > rebasing for clk tree, dogs and cats living together, etc ;-) )
> > 
> 
> Yeah that all sounds good to me.  I'll review the restructure patches
> shortly.

Awesome, thanks.

Jason.
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Re: [PATCH 0/5 v2] ARM: at91: dt: switch to pre-processor

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:28 Fri 17 May , Nicolas Ferre wrote:
> On 15/05/2013 16:19, Jean-Christophe PLAGNIOL-VILLARD :
> >HI,
> >
> > v2:
> >  use common IRQ define
> >  split patch
> >  rebase on 3.10-rc1
> >
> > The follow patch series switch the at91 to DT pre-processor
> >
> > So we can use macro for AIC and Pinctrl instead of magic
> 
> Hi, this is very good for me: nice to use the common GPIO and IRQ
> defines. It increases readability a lot!
and avoid typo when adding pinctrl
> 
> So, it seems natural to push this series through arm-soc. It would
> be integrated early in a "cleanup" branch for 3.11.
> We also would like to make it a prerequisite for all AT91 material
> that are touching the changed files, targeted for 3.11.

agreed
> 
> Acked-by: Nicolas Ferre 

Best Regards,
J.
> 
> Thanks, best regards.
> 
> >The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:
> >
> >   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)
> >
> >are available in the git repository at:
> >
> >   git://github.com/at91linux/linux-at91.git j/for-3.11-dt
> >
> >for you to fetch changes up to 3668ac6a70bc5af71a947ad7b531c57b8a787ea0:
> >
> >   ARM: at91: dt: switch to standard IRQ flag defines (2013-05-15 21:56:18 
> > +0800)
> >
> >
> >Jean-Christophe PLAGNIOL-VILLARD (5):
> >   ARM: at91: dt: use #include for all device trees
> >   ARM: at91: dt: switch to standard GPIO flag defines.
> >   ARM: at91: dt: add pinctrl pre-processor define
> >   ARM: at91: dt: switch to pinctrl to pre-processor
> >   ARM: at91: dt: switch to standard IRQ flag defines
> >
> >  arch/arm/boot/dts/aks-cdu.dts   |   12 +--
> >  arch/arm/boot/dts/animeo_ip.dts |   18 ++---
> >  arch/arm/boot/dts/at91-ariag25.dts  |6 +-
> >  arch/arm/boot/dts/at91rm9200.dtsi   |  207 
> > +
> >  arch/arm/boot/dts/at91rm9200ek.dts  |   10 +--
> >  arch/arm/boot/dts/at91sam9260.dtsi  |  215 
> > ++-
> >  arch/arm/boot/dts/at91sam9263.dtsi  |  203 
> > 
> >  arch/arm/boot/dts/at91sam9263ek.dts |   24 +++---
> >  arch/arm/boot/dts/at91sam9g15.dtsi  |2 +-
> >  arch/arm/boot/dts/at91sam9g15ek.dts |4 +-
> >  arch/arm/boot/dts/at91sam9g20.dtsi  |2 +-
> >  arch/arm/boot/dts/at91sam9g20ek.dts |6 +-
> >  arch/arm/boot/dts/at91sam9g20ek_2mmc.dts|   10 +--
> >  arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   28 ---
> >  arch/arm/boot/dts/at91sam9g25.dtsi  |2 +-
> >  arch/arm/boot/dts/at91sam9g25ek.dts |4 +-
> >  arch/arm/boot/dts/at91sam9g35.dtsi  |2 +-
> >  arch/arm/boot/dts/at91sam9g35ek.dts |4 +-
> >  arch/arm/boot/dts/at91sam9g45.dtsi  |  213 
> > +-
> >  arch/arm/boot/dts/at91sam9m10g45ek.dts  |   38 -
> >  arch/arm/boot/dts/at91sam9n12.dtsi  |  141 
> > +-
> >  arch/arm/boot/dts/at91sam9n12ek.dts |   14 ++--
> >  arch/arm/boot/dts/at91sam9x25.dtsi  |   22 +++---
> >  arch/arm/boot/dts/at91sam9x25ek.dts |4 +-
> >  arch/arm/boot/dts/at91sam9x35.dtsi  |2 +-
> >  arch/arm/boot/dts/at91sam9x35ek.dts |4 +-
> >  arch/arm/boot/dts/at91sam9x5.dtsi   |  279 
> > +-
> >  arch/arm/boot/dts/at91sam9x5cm.dtsi |8 +-
> >  arch/arm/boot/dts/at91sam9x5ek.dtsi |   14 ++--
> >  arch/arm/boot/dts/ethernut5.dts |6 +-
> >  arch/arm/boot/dts/evk-pro3.dts  |6 +-
> >  arch/arm/boot/dts/ge863-pro3.dtsi   |2 +-
> >  arch/arm/boot/dts/kizbox.dts|   16 ++--
> >  arch/arm/boot/dts/mpa1600.dts   |4 +-
> >  arch/arm/boot/dts/pm9g45.dts|   22 +++---
> >  arch/arm/boot/dts/sama5d3.dtsi  |  520 
> > ++-
> >  arch/arm/boot/dts/sama5d31ek.dts|6 +-
> >  arch/arm/boot/dts/sama5d33ek.dts|4 +-
> >  arch/arm/boot/dts/sama5d34ek.dts|6 +-
> >  arch/arm/boot/dts/sama5d35ek.dts|4 +-
> >  arch/arm/boot/dts/sama5d3xcm.dtsi   |4 +-
> >  arch/arm/boot/dts/sama5d3xdm.dtsi   |2 +-
> >  arch/arm/boot/dts/sama5d3xmb.dtsi   |   26 +++
> >  arch/arm/boot/dts/tny_a9260.dts |4 +-
> >  arch/arm/boot/dts/tny_a9263.dts |4 +-
> >  arch/arm/boot/dts/tny_a9g20.dts |4 +-
> >  arch/arm/boot/dts/usb_a9260.dts |4 +-
> >  arch/arm/boot/dts/usb_a9260_common.dtsi |6 +-
>

Re: Pulls and drive strengths in the pinctrl world

[Tomasz Figa]

Hi Linus,

On Friday 17 of May 2013 13:59:54 Linus Walleij wrote:
> On Fri, May 17, 2013 at 11:09 AM, Tomasz Figa  wrote:
> >> Just add another state, pctldev->hog_shutdown to this, and
> >> add an operation pinctrl_force_poweroff() in the same spirit as
> >> pinctrl_force_sleep() that we already have.
> >> 
> >> Add a new state to include/linux/pinctrl/pinctrl-state.h:
> >> #define PINCTRL_STATE_POWEROFF "poweroff"
> >> 
> >> And define you pin table to hog these pins with the mentioned
> >> default and poweroff states.
> >> 
> >> Result: pinctrl core keeps track of your offstate too.
> > 
> > Power down mode settings on our pin controller are completely unrelated to
> > normal mode settings. You can set them once in appropriate registers and
> > pins are switched to them automatically when the SoC enters sleep mode.
> 
> Aha so it's actually automatic sleep modes, not power down
> (as in, disconnect the power and then push the "on" button to
> get it back up).
> 
> Please remember to document it per above in the code and the
> device tree, so everybody understands what it is.

Sure.

> > So IMHO in our case power mode settings are just additional pin
> > configuration options, next to pull-up/-down and driver strength.
> 
> I see. Yes that is different.
> 
> You might want to have a debugfs file in your driver for inspecting
> them though, that sounds like it could be helpful. I'd recommend
> augmenting your .pin_config_dbg_show() callback in the
> struct pinconf_ops to display this for each pin, in addition to the
> current configuration.

Seems reasonable.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics

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Re: Pulls and drive strengths in the pinctrl world

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:22 Wed 15 May , Stephen Warren wrote:
> On 05/15/2013 06:13 PM, Tomasz Figa wrote:
> > On Wednesday 15 of May 2013 16:55:37 Doug Anderson wrote:
> >> Tomasz / Linus,
> >>
> >> On Wed, May 15, 2013 at 3:06 PM, Tomasz Figa  
> > wrote:
> >>> Yes. I don't like the current way too much either, duplication being
> >>> one of the reasons.
> >>
> >> Do you have any other ideas?  It sounds like Linus didn't like my
> >> suggestion and makes some good points...
> > 
> > I don't have anything interesting at the moment. It's a bit late now here 
> > (2 AM), so I'm going to get some sleep first.
> > 
> > Also after reading Stephen's reply, I'm wondering if hogging wouldn't 
> > solve the problem indeed. (It might have to be fixed on pinctrl-samsung 
> > first, as last time I tried to use it, it caused some errors from pinctrl 
> > core, but haven't time to track them down, as it wasn't anything important 
> > at that time).
> 
> One issue I noticed with the DT fragments earlier in this thread. It
> looks like hogs in the Samsung pinctrl bingings end up looking like:
> 
> pinctrl {
> pina {
> samsung,pins = ;
> samsung,pin-function = <0xf>;
> samsung,pin-pud = <0>;
> ...

I have a huge issue here that we had on at91 too

we are going to have a huge numbet of node

and on at91 we handle the pin the same way as samsung
and ST have also a similiar IP

so I'll prefer to reuse the AT91 DT bindings

as said by Linus I just push a cleanup of the magic by using Macro
which make it really readable now

some extract of the sama5 pinctrl

mmc0 {
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
atmel,pins =
;   /* PD1 periph A MCI0_DA0 with pullup */
};
pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
atmel,pins =
;   /* PD4 periph A MCI0_DA3 with pullup */
};
pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
atmel,pins =
;   /* PD8 periph A MCI0_DA7 with pullup, conflicts 
with PWML3 */
};
};

of sam9g45

i2c_gpio2 {
pinctrl_i2c_gpio2: i2c_gpio2-0 {
atmel,pins =
;/* PB5 gpio multidrive I2C2 clock */
};
};

so we could share the c code too

Best Regards,
J,
> };
> pinp {
> samsung,pins = ;
> samsung,pin-function = <0xe>;
> samsung,pin-pud = <1>;
> ...
> };
> pinx {
> samsung,pins = ;
> samsung,pin-function = <0xd>;
> samsung,pin-pud = <2>;
> ...
> };
> 
> pinctrl-names = "default";
> pinctrl-0 = <&pina &pinp &pinx>;
> };
> 
> That pinctrl-0 property could get rather large (hard to write/maintain,
> unwieldy) if it needs to set up lots of different configurations. That's
> why I made the equivalent Tegra bindings be:
> 
> pinctrl {
> pins_default {
> pina {
> samsung,pins = ;
> samsung,pin-function = <0xf>;
> samsung,pin-pud = <0>;
> ...
> };
> pinp {
> samsung,pins = ;
> samsung,pin-function = <0xe>;
> samsung,pin-pud = <1>;
> ...
> };
> pinx {
> samsung,pins = ;
> samsung,pin-function = <0xd>;
> samsung,pin-pud = <2>;
> ...
> };
> };
> 
> pinctrl-names = "default";
> pinctrl-0 = <&pins_default>;
> };
> 
> The extra level within the "pinctrl configuration node" ("pins_default"
> here) makes the pinctrl-0 property a lot easier to write, and the
> advantage happens at every use-site that needs to configure different
> subsets of the relevant pins in different ways.
> 
> If you're changing all the bindings anyway, introducing this extra level
> might be something to think about.
> 
> I did try to explain my philosophy here when we all got together to
> design the pinctrl bindings, but I obviously didn't explain it well
> enough, or people didn't like it anyway.
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Re: [PATCH 1/2] video: exynos_dp: Add parsing of gpios pins to exynos-dp driver

[Tomasz Figa]

Hi Jingoo,

On Thursday 16 of May 2013 02:03:59 한진구 wrote:
> Tuesday, May 14, 2013 11:17 PM, Vikas Sajjan wrote:
> 
> > 
> > Hi Vikas,
> > 
> > On Tuesday 14 of May 2013 18:25:51 Vikas Sajjan wrote:
> > 
> > >  Adds GPIO parsing functionality for "LCD backlight" and "LCD enable"
> > >  GPIO pins of exynos dp controller.
> > >
> > >
> > >
> > > Signed-off-by: Vikas Sajjan 
> > > ---
> > > 
> > >  drivers/video/exynos/exynos_dp_core.c |   45
> > > 
> > > + 1 file changed, 45 insertions(+)
> > >
> > >
> > 
> > 
> > I don't think that Exynos DP driver is right place for such code.
> > Backlight
 and LCD drivers are responsible for backlight and LCD power
> > control using backlight and LCD subsystems.
> > 
> > IMHO the correct solution would be to either extend existing
> > backlight/lcd
> > drivers found in drivers/video/backlight to support direct GPIO control
> > and
 parse GPIO pins from device tree or create new gpio_bl and gpio_lcd
> > drivers.
> 
> Hi Vikas Sajian,
> 
> I agree with Tomasz Figa's opinion.
> Backlight/LCD framework should be used.
> eDP panel backlight on SMDK5210 board can be controlled by PWM;
> thus, pwm-backlight driver should be used.
> Also, eDP panel reset pin should be controlled by using
> platform-lcd driver.
> 
> 
> > 
> > CCing Richard, Florian and linux-fbdev.
> 
> 
> Also, I have been doing backlight reviews instead of Richard,
> please do CC'ing me.

OK. I used get_maintainers script, but it seems like the result was a bit off 
in this case. Will remember for future.

Best regards,
-- 
Tomasz Figa
Linux Kernel Developer
Samsung R&D Institute Poland
Samsung Electronics

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Re: [PATCH v3 09/20] ARM: shmobile: r8a7790: Add GPIO controller devices to device tree

[Guennadi Liakhovetski]

Hi Laurent

On Wed, 15 May 2013, Laurent Pinchart wrote:

> Add GPIO controller nodes to the r8a7790 core device tree.
> 
> Signed-off-by: Laurent Pinchart 
> ---
>  arch/arm/boot/dts/r8a7790.dtsi | 54 
> ++
>  1 file changed, 54 insertions(+)

Also here a couple of things are missing (presumably, for other SoCs you 
need the same):

diff --git a/arch/arm/boot/dts/r8a7790.dtsi 
b/arch/arm/boot/dts/r8a7790.dtsi
index 674ee39..cd1a04f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -51,6 +51,7 @@
interrupts = <0 4 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 0 32>;
};
 
gpio1: gpio@ffc41000 {
@@ -60,6 +61,7 @@
interrupts = <0 5 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 32 32>;
};
 
gpio2: gpio@ffc42000 {
@@ -69,6 +71,7 @@
interrupts = <0 6 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 64 32>;
};
 
gpio3: gpio@ffc43000 {
@@ -78,6 +81,7 @@
interrupts = <0 7 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 96 32>;
};
 
gpio4: gpio@ffc44000 {
@@ -87,6 +91,7 @@
interrupts = <0 8 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 128 32>;
};
 
gpio5: gpio@ffc45000 {
@@ -96,6 +101,7 @@
interrupts = <0 9 0x4>;
#gpio-cells = <2>;
gpio-controller;
+   gpio-ranges = <&pfc 0 160 32>;
};
 
timer {
@@ -118,6 +124,7 @@
pfc: pfc@e606 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe606 0 0x250>;
+   #gpio-range-cells = <3>;
};
 
/* No MMC_CAP_UHS_DDR50 (dual data rate) capability on r8a7790! */

Thanks
Guennadi
---
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Freelance Open-Source Software Developer
http://www.open-technology.de/
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Re: [RFC/PATCH 2/2] gpio-rcar: Add DT support

[Guennadi Liakhovetski]

Hi Laurent

On Fri, 10 May 2013, Laurent Pinchart wrote:

> Add DT bindings for the gpio-rcar driver and read the device
> configuration from the DT node at probe time if available.
> 
> Cc: devicetree-discuss@lists.ozlabs.org
> Signed-off-by: Laurent Pinchart 
> ---
>  .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 48 +
>  drivers/gpio/gpio-rcar.c   | 63 
> ++
>  2 files changed, 101 insertions(+), 10 deletions(-)
>  create mode 100644 
> Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt

Testing this patch reveals, that (at least) one thing is missing here:

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index a499ea6..e233778 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -342,6 +342,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
gpio_chip->owner = THIS_MODULE;
gpio_chip->base = p->config.gpio_base;
gpio_chip->ngpio = p->config.number_of_pins;
+   gpio_chip->dev = &pdev->dev;
 
irq_chip = &p->irq_chip;
irq_chip->name = name;

Thanks
Guennadi
---
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Freelance Open-Source Software Developer
http://www.open-technology.de/
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Re: Pulls and drive strengths in the pinctrl world

[Linus Walleij]

On Fri, May 17, 2013 at 11:09 AM, Tomasz Figa  wrote:

>> Just add another state, pctldev->hog_shutdown to this, and
>> add an operation pinctrl_force_poweroff() in the same spirit as
>> pinctrl_force_sleep() that we already have.
>>
>> Add a new state to include/linux/pinctrl/pinctrl-state.h:
>> #define PINCTRL_STATE_POWEROFF "poweroff"
>>
>> And define you pin table to hog these pins with the mentioned
>> default and poweroff states.
>>
>> Result: pinctrl core keeps track of your offstate too.
>
> Power down mode settings on our pin controller are completely unrelated to
> normal mode settings. You can set them once in appropriate registers and
> pins are switched to them automatically when the SoC enters sleep mode.

Aha so it's actually automatic sleep modes, not power down
(as in, disconnect the power and then push the "on" button to
get it back up).

Please remember to document it per above in the code and the
device tree, so everybody understands what it is.

> So IMHO in our case power mode settings are just additional pin
> configuration options, next to pull-up/-down and driver strength.

I see. Yes that is different.

You might want to have a debugfs file in your driver for inspecting
them though, that sounds like it could be helpful. I'd recommend
augmenting your .pin_config_dbg_show() callback in the
struct pinconf_ops to display this for each pin, in addition to the
current configuration.

Yours,
Linus Walleij
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[PATCH v9] i2c: exynos5: add High Speed I2C controller driver

[Naveen Krishna Chatradhi]

Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.

Driver only supports Device Tree method.

Changes since v1:
1. Added FIFO functionality
2. Added High speed mode functionality
3. Remove SMBUS_QUICK
4. Remove the debugfs functionality
5. Use devm_* functions where ever possible
6. Driver is free from GPIO configs (only supports pinctrl method)
7. Use OF data string "clock-frequency" to get the bus operating frequencies
8. Split the clock divisor calculation function
9. Add resets for the failed transacton cases
10. few other bug fixes and cosmetic changes

Signed-off-by: Taekgyun Ko 
Signed-off-by: Naveen Krishna Chatradhi 
Reviewed-by: Simon Glass 
Tested-by: Andrew Bresticker 
Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Andrew Bresticker 
---

Changes since v8
1. improved the device tree bindings description page for i2c-exynos5
2. fixed the return value check for devm_ioremap_resource

 .../devicetree/bindings/i2c/i2c-exynos5.txt|   45 +
 drivers/i2c/busses/Kconfig |7 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-exynos5.c   |  888 
 4 files changed, 941 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
 create mode 100644 drivers/i2c/busses/i2c-exynos5.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt 
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
new file mode 100644
index 000..29c01c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -0,0 +1,45 @@
+* Samsung's High Speed I2C controller
+
+The Samsung's High Speed I2C controller is used to interface with I2C devices
+at various speeds ranging from 100khz to 3.4Mhz.
+
+Required properties:
+  - compatible: value should be.
+  -> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.
+  - reg: physical base address of the controller and length of memory mapped
+region.
+  - interrupts: interrupt number to the cpu.
+  - #address-cells: always 1 (for i2c addresses)
+  - #size-cells: always 0
+
+  - Pinctrl:
+- pinctrl-0: Pin control group to be used for this controller.
+- pinctrl-names: Should contain only one value - "default".
+
+Optional properties:
+  - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not
+specified, default value is 0.
+  - clock-frequency: Desired operating frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+
+Example:
+
+hsi2c@12ca {
+   compatible = "samsung,exynos5-hsi2c";
+   reg = <0x12ca 0x100>;
+   interrupts = <56>;
+   clock-frequency = <10>;
+
+   /* Pinctrl variant begins here */
+   pinctrl-0 = <&i2c4_bus>;
+   pinctrl-names = "default";
+   /* Pinctrl variant ends here */
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   s2mps11_pmic@66 {
+   compatible = "samsung,s2mps11-pmic";
+   reg = <0x66>;
+   };
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..49a665f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -434,6 +434,13 @@ config I2C_EG20T
  ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
  ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
 
+config I2C_EXYNOS5
+   tristate "Exynos5 high-speed I2C driver"
+   depends on ARCH_EXYNOS5 && OF
+   help
+ Say Y here to include support for high-speed I2C controller in the
+ Exynos5 based Samsung SoCs.
+
 config I2C_GPIO
tristate "GPIO-based bitbanging I2C"
depends on GENERIC_GPIO
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..b19366c 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
 obj-$(CONFIG_I2C_DESIGNWARE_PCI)   += i2c-designware-pci.o
 i2c-designware-pci-objs := i2c-designware-pcidrv.o
 obj-$(CONFIG_I2C_EG20T)+= i2c-eg20t.o
+obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
new file mode 100644
index 000..33c481d
--- /dev/null
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -0,0 +1,888 @@
+/**
+ * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 

Re: Pulls and drive strengths in the pinctrl world

[Tomasz Figa]

Hi Linus,

On Friday 17 of May 2013 10:38:53 Linus Walleij wrote:
> On Thu, May 16, 2013 at 2:03 AM, Doug Anderson  
wrote:
> >> I prefer to put all the static pinctrl configuration in the pinctrl
> >> hog, and only the dynamic stuff in the individual device nodes.
> >> 
> >> I know LinusW won't like this suggestion much though:-)
> 
> (It's not that bad actually...)
> 
> > Ah right!  I forgot about hogs in this case.  That's also reasonable
> > as a solution and is similar to what we've got in the tree for
> > powerdown configuration of pins (I'll try to post this patch soon too,
> > WIP at  and
> > .
> 
> I don't like these Gerrit patches really, it's better to move
> this to the pinctrl core using hogs.
> 
> If you look in drivers/pinctr/core.c you can find this:
> 
> pinctrl_register()
> {
> (...)
> if (!IS_ERR(pctldev->p)) {
> pctldev->hog_default =
> pinctrl_lookup_state(pctldev->p,
> PINCTRL_STATE_DEFAULT); if (IS_ERR(pctldev->hog_default)) {
> dev_dbg(dev, "failed to lookup the default
> state\n"); } else {
> if (pinctrl_select_state(pctldev->p,
> pctldev->hog_default))
> dev_err(dev,
> "failed to select default
> state\n"); }
> 
> pctldev->hog_sleep =
> pinctrl_lookup_state(pctldev->p,
>
> PINCTRL_STATE_SLEEP); if (IS_ERR(pctldev->hog_sleep))
> dev_dbg(dev, "failed to lookup the sleep
> state\n"); }
> 
> Just add another state, pctldev->hog_shutdown to this, and
> add an operation pinctrl_force_poweroff() in the same spirit as
> pinctrl_force_sleep() that we already have.
> 
> Add a new state to include/linux/pinctrl/pinctrl-state.h:
> #define PINCTRL_STATE_POWEROFF "poweroff"
> 
> And define you pin table to hog these pins with the mentioned
> default and poweroff states.
> 
> Result: pinctrl core keeps track of your offstate too.

Power down mode settings on our pin controller are completely unrelated to 
normal mode settings. You can set them once in appropriate registers and 
pins are switched to them automatically when the SoC enters sleep mode.

So IMHO in our case power mode settings are just additional pin 
configuration options, next to pull-up/-down and driver strength.

Best regards,
Tomasz

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Re: Pulls and drive strengths in the pinctrl world

[Linus Walleij]

On Thu, May 16, 2013 at 2:03 AM, Doug Anderson  wrote:

>> I prefer to put all the static pinctrl configuration in the pinctrl hog,
>> and only the dynamic stuff in the individual device nodes.
>>
>> I know LinusW won't like this suggestion much though:-)

(It's not that bad actually...)

> Ah right!  I forgot about hogs in this case.  That's also reasonable
> as a solution and is similar to what we've got in the tree for
> powerdown configuration of pins (I'll try to post this patch soon too,
> WIP at  and
> .

I don't like these Gerrit patches really, it's better to move
this to the pinctrl core using hogs.

If you look in drivers/pinctr/core.c you can find this:

pinctrl_register()
{
(...)
if (!IS_ERR(pctldev->p)) {
pctldev->hog_default =
pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT);
if (IS_ERR(pctldev->hog_default)) {
dev_dbg(dev, "failed to lookup the default state\n");
} else {
if (pinctrl_select_state(pctldev->p,
pctldev->hog_default))
dev_err(dev,
"failed to select default state\n");
}

pctldev->hog_sleep =
pinctrl_lookup_state(pctldev->p,
PINCTRL_STATE_SLEEP);
if (IS_ERR(pctldev->hog_sleep))
dev_dbg(dev, "failed to lookup the sleep state\n");
}

Just add another state, pctldev->hog_shutdown to this, and
add an operation pinctrl_force_poweroff() in the same spirit as
pinctrl_force_sleep() that we already have.

Add a new state to include/linux/pinctrl/pinctrl-state.h:
#define PINCTRL_STATE_POWEROFF "poweroff"

And define you pin table to hog these pins with the mentioned
default and poweroff states.

Result: pinctrl core keeps track of your offstate too.

Yours,
Linus Walleij
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Re: [PATCH 0/5 v2] ARM: at91: dt: switch to pre-processor

[Nicolas Ferre]

On 15/05/2013 16:19, Jean-Christophe PLAGNIOL-VILLARD :

HI,

v2:
 use common IRQ define
 split patch
 rebase on 3.10-rc1

 The follow patch series switch the at91 to DT pre-processor

 So we can use macro for AIC and Pinctrl instead of magic


Hi, this is very good for me: nice to use the common GPIO and IRQ 
defines. It increases readability a lot!


So, it seems natural to push this series through arm-soc. It would be 
integrated early in a "cleanup" branch for 3.11.
We also would like to make it a prerequisite for all AT91 material that 
are touching the changed files, targeted for 3.11.


Acked-by: Nicolas Ferre 

Thanks, best regards.


The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://github.com/at91linux/linux-at91.git j/for-3.11-dt

for you to fetch changes up to 3668ac6a70bc5af71a947ad7b531c57b8a787ea0:

   ARM: at91: dt: switch to standard IRQ flag defines (2013-05-15 21:56:18 
+0800)


Jean-Christophe PLAGNIOL-VILLARD (5):
   ARM: at91: dt: use #include for all device trees
   ARM: at91: dt: switch to standard GPIO flag defines.
   ARM: at91: dt: add pinctrl pre-processor define
   ARM: at91: dt: switch to pinctrl to pre-processor
   ARM: at91: dt: switch to standard IRQ flag defines

  arch/arm/boot/dts/aks-cdu.dts   |   12 +--
  arch/arm/boot/dts/animeo_ip.dts |   18 ++---
  arch/arm/boot/dts/at91-ariag25.dts  |6 +-
  arch/arm/boot/dts/at91rm9200.dtsi   |  207 
+
  arch/arm/boot/dts/at91rm9200ek.dts  |   10 +--
  arch/arm/boot/dts/at91sam9260.dtsi  |  215 
++-
  arch/arm/boot/dts/at91sam9263.dtsi  |  203 

  arch/arm/boot/dts/at91sam9263ek.dts |   24 +++---
  arch/arm/boot/dts/at91sam9g15.dtsi  |2 +-
  arch/arm/boot/dts/at91sam9g15ek.dts |4 +-
  arch/arm/boot/dts/at91sam9g20.dtsi  |2 +-
  arch/arm/boot/dts/at91sam9g20ek.dts |6 +-
  arch/arm/boot/dts/at91sam9g20ek_2mmc.dts|   10 +--
  arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   28 ---
  arch/arm/boot/dts/at91sam9g25.dtsi  |2 +-
  arch/arm/boot/dts/at91sam9g25ek.dts |4 +-
  arch/arm/boot/dts/at91sam9g35.dtsi  |2 +-
  arch/arm/boot/dts/at91sam9g35ek.dts |4 +-
  arch/arm/boot/dts/at91sam9g45.dtsi  |  213 
+-
  arch/arm/boot/dts/at91sam9m10g45ek.dts  |   38 -
  arch/arm/boot/dts/at91sam9n12.dtsi  |  141 
+-
  arch/arm/boot/dts/at91sam9n12ek.dts |   14 ++--
  arch/arm/boot/dts/at91sam9x25.dtsi  |   22 +++---
  arch/arm/boot/dts/at91sam9x25ek.dts |4 +-
  arch/arm/boot/dts/at91sam9x35.dtsi  |2 +-
  arch/arm/boot/dts/at91sam9x35ek.dts |4 +-
  arch/arm/boot/dts/at91sam9x5.dtsi   |  279 
+-
  arch/arm/boot/dts/at91sam9x5cm.dtsi |8 +-
  arch/arm/boot/dts/at91sam9x5ek.dtsi |   14 ++--
  arch/arm/boot/dts/ethernut5.dts |6 +-
  arch/arm/boot/dts/evk-pro3.dts  |6 +-
  arch/arm/boot/dts/ge863-pro3.dtsi   |2 +-
  arch/arm/boot/dts/kizbox.dts|   16 ++--
  arch/arm/boot/dts/mpa1600.dts   |4 +-
  arch/arm/boot/dts/pm9g45.dts|   22 +++---
  arch/arm/boot/dts/sama5d3.dtsi  |  520 
++-
  arch/arm/boot/dts/sama5d31ek.dts|6 +-
  arch/arm/boot/dts/sama5d33ek.dts|4 +-
  arch/arm/boot/dts/sama5d34ek.dts|6 +-
  arch/arm/boot/dts/sama5d35ek.dts|4 +-
  arch/arm/boot/dts/sama5d3xcm.dtsi   |4 +-
  arch/arm/boot/dts/sama5d3xdm.dtsi   |2 +-
  arch/arm/boot/dts/sama5d3xmb.dtsi   |   26 +++
  arch/arm/boot/dts/tny_a9260.dts |4 +-
  arch/arm/boot/dts/tny_a9263.dts |4 +-
  arch/arm/boot/dts/tny_a9g20.dts |4 +-
  arch/arm/boot/dts/usb_a9260.dts |4 +-
  arch/arm/boot/dts/usb_a9260_common.dtsi |6 +-
  arch/arm/boot/dts/usb_a9263.dts |8 +-
  arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi|   22 +++---
  arch/arm/boot/dts/usb_a9g20.dts |4 +-
  include/dt-bindings/pinctrl/at91.h  |   35 +
  52 files changed, 1139 insertions(+), 1078 deletions(-)
  create mode 100644 include/dt-bindings/pinctrl/at91.h

Best Regards,
J.





--
Nicolas

[PATCH] gianfar: add missing iounmap() on error in gianfar_ptp_probe()

[Wei Yongjun]

From: Wei Yongjun 

Add the missing iounmap() before return from gianfar_ptp_probe()
in the error handling case.

Signed-off-by: Wei Yongjun 
---
 drivers/net/ethernet/freescale/gianfar_ptp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/freescale/gianfar_ptp.c 
b/drivers/net/ethernet/freescale/gianfar_ptp.c
index 576e4b8..083ea2b 100644
--- a/drivers/net/ethernet/freescale/gianfar_ptp.c
+++ b/drivers/net/ethernet/freescale/gianfar_ptp.c
@@ -524,6 +524,7 @@ static int gianfar_ptp_probe(struct platform_device *dev)
return 0;
 
 no_clock:
+   iounmap(etsects->regs);
 no_ioremap:
release_resource(etsects->rsrc);
 no_resource:

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[PATCH] ipmi: add missing platform_device_put() on error in try_smi_init()

[Wei Yongjun]

From: Wei Yongjun 

Add the missing platform_device_put() before return from
try_smi_init() in the platform_device_add() fail case.

Signed-off-by: Wei Yongjun 
---
 drivers/char/ipmi/ipmi_si_intf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index af4b23f..3f6c390 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -3299,6 +3299,7 @@ static int try_smi_init(struct smi_info *new_smi)
   "Unable to register system interface device:"
   " %d\n",
   rv);
+   platform_device_put(new_smi->pdev);
goto out_err;
}
new_smi->dev_registered = 1;

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Re: [PATCH RFC 0/2] clk: add metag specific gate/mux clocks

[James Hogan]

On 16/05/13 23:22, Stephen Boyd wrote:
> On 05/16/13 02:56, James Hogan wrote:
>> On 15/05/13 23:31, Stephen Boyd wrote:
>>> Can you please Cc the devicetree mailing list when proposing new bindings?
>> Erm, I think it was on Cc (devicetree-discuss@lists.ozlabs.org yeh?)
> 
> I added them in my reply.

Ah yes, sorry, my mistake.

Cheers
James

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Re: [PATCHv9 5/9] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370

[Mike Turquette]

Quoting Jason Cooper (2013-05-16 08:06:16)
> Mike, Sebastian,
> 
> On Thu, May 16, 2013 at 10:26:24AM +0200, Sebastian Hesselbarth wrote:
> > On 05/16/2013 09:44 AM, Thomas Petazzoni wrote:
> > >Dear Mike Turquette,
> > >
> > >On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> > >>Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > >>>The Armada 370 has two gatable clocks for each PCIe interface, and we
> > >>>want both of them to be enabled. We therefore make one of the two
> > >>>clocks a child of the other, as we did for the sataX and sataXlnk
> > >>>clocks on Armada XP.
> > >>
> > >>Ack for patches #5 and #6.  Do you want me to take them?
> 
> Thanks for the Ack!
> 
> > >I don't know, I guess with your Ack, it would be easier to carry them
> > >through the Marvell maintainers and then the arm-soc tree, so that we
> > >can test arm-soc and have all the pieces needed in here.
> > >
> > >That said, Sebastian Hesselbarth has submitted a big rework of the
> > >mvebu clock drivers, which would conflict with this patch, and
> > >Sebastian's rework would most likely go through your tree. If that's
> > >the case, I guess it would be better to let you take #5 and #6 in this
> > >patch series.
> > 
> > I also requested to take the restructure patches through ARM tree. They
> > are only touching files in drivers/clk/mvebu and by taking them through
> > ARM, we can update PCIe clock patches easily. The dependency between
> > Thomas' and my patches basically is that I renamed files that Thomas
> > now commits to. (I switched clk/mvebu from per-function files to per-soc
> > files).
> 
> I agree.  My heart jumped into my throat a little there :)  Mike, if
> it's ok with you, I'd prefer to take these through arm-soc.  Any merge
> conflicts should be minimal.  And at any rate, resolving the conflicts
> are *much* easier to handle than having arm-soc depend on an outside
> tree (then Linus has to take care in the order he merges them, no
> rebasing for clk tree, dogs and cats living together, etc ;-) )
> 

Yeah that all sounds good to me.  I'll review the restructure patches
shortly.

Regards,
Mike

> thx,
> 
> Jason.
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