Re: [PATCH] usb: phy: samsung: adding usbphy for Exynos4X12
Hi Dongjin,
On Mon, May 13, 2013 at 11:55 PM, Dongjin Kim wrote:
> This patch adds usb host phy (USB 2.0 PHY) support for Samsung Exynos4X12 SoC.
> New functions, samsung_exynos4x12_usb2phy_enable/_disable and selecting
> reference clock, for Exynos4X12 are added. Since it has different register
> set up with Exynos4210 or Exynos5250, "samsung,exynos4x12-usb2phy" is added.
A patch-set for 4x12 from Tomasz too.
[PATCH 0/6] Samsung USB PHY SoC support cleanup
@ http://www.mail-archive.com/linux-usb@vger.kernel.org/msg18177.html
Hi Tomasz,
Planning to re-spin that series ?
>
> Signed-off-by: Dongjin Kim
> ---
> .../devicetree/bindings/usb/samsung-usbphy.txt |5 ++
> drivers/usb/phy/phy-samsung-usb.c | 30 ++-
> drivers/usb/phy/phy-samsung-usb.h | 18
> drivers/usb/phy/phy-samsung-usb2.c | 90
>
> 4 files changed, 140 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> index 33fd354..f805878 100644
> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -18,6 +18,11 @@ Exynos4210:
> - clock-names: names of clock correseponding IDs clock property as requested
>by the controller driver.
>
> +Exynos4x12:
> +- compatible : should be "samsung,exynos4x12-usb2phy"
> +- reg : base physical address of the phy registers and length of memory
> mapped
> + region.
> +
> Exynos5250:
> - compatible : should be "samsung,exynos5250-usb2phy"
> - reg : base physical address of the phy registers and length of memory
> mapped
> diff --git a/drivers/usb/phy/phy-samsung-usb.c
> b/drivers/usb/phy/phy-samsung-usb.c
> index 7b118ee5..efb26de 100644
> --- a/drivers/usb/phy/phy-samsung-usb.c
> +++ b/drivers/usb/phy/phy-samsung-usb.c
> @@ -91,10 +91,11 @@ void samsung_usbphy_set_isolation(struct samsung_usbphy
> *sphy, bool on)
> */
> break;
> case TYPE_EXYNOS4210:
> + case TYPE_EXYNOS4X12:
> /*
> -* Fall through since exynos4210 and exynos5250 have similar
> -* register architecture: two separate registers for host and
> -* device phy control with enable bit at position 0.
> +* Fall through since exynos4210/4x12 and exynos5250 have
> +* similar register architecture: two separateregistersfor
> +* host and device phy control with enable bit at position 0.
> */
> case TYPE_EXYNOS5250:
> if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
> @@ -210,6 +211,29 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy
> *sphy)
> refclk_freq = FSEL_CLKSEL_24M;
> break;
> }
> + } else if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
> + switch (clk_get_rate(ref_clk)) {
> + case 9600 * KHZ:
> + refclk_freq = FSEL_CLKSEL_9600K;
> + break;
> + case 10 * MHZ:
> + refclk_freq = FSEL_CLKSEL_10M;
> + break;
> + case 12 * MHZ:
> + refclk_freq = FSEL_CLKSEL_12M;
> + break;
> + case 19200 * KHZ:
> + refclk_freq = FSEL_CLKSEL_19200K;
> + break;
> + case 20 * MHZ:
> + refclk_freq = FSEL_CLKSEL_20M;
> + break;
> + case 24 * MHZ:
> + default:
> + /* default reference clock */
> + refclk_freq = FSEL_CLKSEL_24M;
> + break;
> + }
> } else {
> switch (clk_get_rate(ref_clk)) {
> case 12 * MHZ:
> diff --git a/drivers/usb/phy/phy-samsung-usb.h
> b/drivers/usb/phy/phy-samsung-usb.h
> index 70a9cae..ad86bce 100644
> --- a/drivers/usb/phy/phy-samsung-usb.h
> +++ b/drivers/usb/phy/phy-samsung-usb.h
> @@ -47,6 +47,23 @@
> #define RSTCON_HLINK_SWRST (0x1 << 1)
> #define RSTCON_SWRST (0x1 << 0)
>
> +/* For Exynos4x12 */
> +#define PHYCLK_COMMON_ON_N_PHY0(0x1 << 4)
> +#define PHYCLK_COMMON_ON_N_PHY1(0x1 << 7)
> +
> +#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
> +#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
> +#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
> +
> +#define PHYPWR_ANALOG_POWERDOWN_PHY1 (0x1 << 7)
> +
> +#define RSTCON_HLINK_SWRST_MASK(0xf << 7)
> +#define RSTCON_PHY1_SWRST_MASK (0xf << 3)
> +#define RSTCON_PHY0_SWRST_MASK (0x
Re: [PATCH v5 0/3] ARM: Exynos5250: Enabling dwc3-exynos driver
Hi Kukjin, On Fri, Mar 15, 2013 at 1:32 PM, Vivek Gautam wrote: > This patch-set is in continuation with patch-series: > [PATCH v4 0/4] Enable ehci, ohci and dwc3 devices on exynos5250 > out of which follwowing patches have been picked up: > ARM: Exynos5250: Enabling ehci-s5p driver > ARM: Exynos5250: Enabling ohci-exynos driver > > Based on following patch-set for Samsung's usb PHY enablement: > [PATCH v4 0/2] ARM: Exynos5250: Enabling samsung usb phy > > and further depends on dwc3-exynos driver patch-set: > [PATCH 0/2] dwc3: exynos: Device tree fixes > > Changes from v4: > - Aligning with the recently merged common clock framework, thereby >no place for clock file changes. ;-) > - Adding proper binding documentation as per latest bindings changes in >dwc3 driver (dwc3/core.c as well as for dwc3-exynos.c change reflected >by above patch-set. > - Bifurcating the patch to separate our Documentation, arch and dts changes. > > Vivek Gautam (3): > usb: Add device tree bindings for dwc3-exynos > ARM: exynos5250: dts: Enabling dwc3-exynos driver > ARM: exynos5: Enable XHCI support on exynos5 > > .../devicetree/bindings/usb/exynos-usb.txt | 34 > > arch/arm/boot/dts/exynos5250.dtsi | 20 ++- > arch/arm/mach-exynos/Kconfig |1 + > 3 files changed, 53 insertions(+), 2 deletions(-) Waiting for your review on this patch-set. :-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v4 0/2] ARM: Exynos5250: Enabling samsung usb phy
Hi Kukjin, On Fri, Mar 15, 2013 at 1:26 PM, Vivek Gautam wrote: > Based on 'for-next' of linux-samsung tree with following patches > from Doug on top: > usb: Document clocks in samsung, exynos4210-ehci/ohci bindings > ARM: dts: add usb 2.0 clock references to exynos5250 device tree > > Also depending upon following patch-series for Samsung-usb-phy driver: > [PATCH v7 0/2] Adding USB 3.0 DRD-phy support for exynos5250 > > Changes from v3: > Added 'clocks' and 'clock-names' entry also in device nodes, aligning > with common clock framework for Samsung's SoCs. > > Vivek Gautam (2): > ARM: Exynos5250: Enabling samsung-usb2phy driver > ARM: Exynos5250: Enabling samsung-usb3phy driver > > arch/arm/boot/dts/exynos5250.dtsi | 29 + > 1 files changed, 29 insertions(+), 0 deletions(-) Waiting for your review on this patch-set. :-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 3/3] ARM: exynos5: Enable XHCI support on exynos5
This patch enables support for XHCI on exynos5 series of SOCs, to support host side USB 3.0 support. Signed-off-by: Vivek Gautam --- arch/arm/mach-exynos/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ef3b69a..1c582cf 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -420,6 +420,7 @@ config MACH_EXYNOS5_DT depends on ARCH_EXYNOS5 select ARM_AMBA select CLKSRC_OF + select USB_ARCH_HAS_XHCI select USE_OF help Machine support for Samsung EXYNOS5 machine with device tree enabled. -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 2/3] ARM: exynos5250: dts: Enabling dwc3-exynos driver
Adding DWC3 device tree node for Exynos5250 needed to
parse device tree data.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5b6f8c8..e0feedb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -398,7 +398,23 @@
dma-names = "tx", "rx";
};
- usbphy@1210 {
+ usb@1200 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&clock 286>;
+ clock-names = "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x1200 0x1>;
+ interrupts = <0 72 0>;
+ usb-phy = <&usb2_phy &usb3_phy>;
+ };
+ };
+
+ usb3_phy: usbphy@1210 {
compatible = "samsung,exynos5250-usb3phy";
reg = <0x1210 0x100>;
clocks = <&clock 1>, <&clock 286>;
@@ -430,7 +446,7 @@
clock-names = "usbhost";
};
- usbphy@1213 {
+ usb2_phy: usbphy@1213 {
compatible = "samsung,exynos5250-usb2phy";
reg = <0x1213 0x100>;
clocks = <&clock 1>, <&clock 285>;
--
1.7.6.5
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[PATCH v5 1/3] usb: Add device tree bindings for dwc3-exynos
Document device tree binding information as required by the
Samsung' USB 3.0 controller.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/usb/exynos-usb.txt | 34
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index b3abde7..d967ba1 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -48,3 +48,37 @@ Example:
clocks = <&clock 285>;
clock-names = "usbhost";
};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
+ controller.
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+with 'reg' property.
+ - ranges: allows valid 1:1 translation between child's address space and
+ parent's address space
+ - clocks: Clock IDs array as required by the controller.
+ - clock-names: names of clocks correseponding to IDs in the clock property
+
+Sub-nodes:
+The dwc3 core should be added as subnode to Exynos dwc3 glue.
+- dwc3 :
+ The binding details of dwc3 can be found in:
+ Documentation/devicetree/bindings/usb/dwc3.txt
+
+Example:
+ usb@1200 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&clock 286>;
+ clock-names = "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x1200 0x1>;
+ interrupts = <0 72 0>;
+ usb-phy = <&usb2_phy &usb3_phy>;
+ };
+ };
--
1.7.6.5
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[PATCH v5 0/3] ARM: Exynos5250: Enabling dwc3-exynos driver
This patch-set is in continuation with patch-series: [PATCH v4 0/4] Enable ehci, ohci and dwc3 devices on exynos5250 out of which follwowing patches have been picked up: ARM: Exynos5250: Enabling ehci-s5p driver ARM: Exynos5250: Enabling ohci-exynos driver Based on following patch-set for Samsung's usb PHY enablement: [PATCH v4 0/2] ARM: Exynos5250: Enabling samsung usb phy and further depends on dwc3-exynos driver patch-set: [PATCH 0/2] dwc3: exynos: Device tree fixes Changes from v4: - Aligning with the recently merged common clock framework, thereby no place for clock file changes. ;-) - Adding proper binding documentation as per latest bindings changes in dwc3 driver (dwc3/core.c as well as for dwc3-exynos.c change reflected by above patch-set. - Bifurcating the patch to separate our Documentation, arch and dts changes. Vivek Gautam (3): usb: Add device tree bindings for dwc3-exynos ARM: exynos5250: dts: Enabling dwc3-exynos driver ARM: exynos5: Enable XHCI support on exynos5 .../devicetree/bindings/usb/exynos-usb.txt | 34 arch/arm/boot/dts/exynos5250.dtsi | 20 ++- arch/arm/mach-exynos/Kconfig |1 + 3 files changed, 53 insertions(+), 2 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v4 2/2] ARM: Exynos5250: Enabling samsung-usb3phy driver
Adding usb3.0 phy node for Exynos5250 along with the
necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5ef9c1e..5b6f8c8 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -398,6 +398,20 @@
dma-names = "tx", "rx";
};
+ usbphy@1210 {
+ compatible = "samsung,exynos5250-usb3phy";
+ reg = <0x1210 0x100>;
+ clocks = <&clock 1>, <&clock 286>;
+ clock-names = "ext_xtal", "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ reg = <0x10040704 0x8>;
+ };
+ };
+
usb@1211 {
compatible = "samsung,exynos4210-ehci";
reg = <0x1211 0x100>;
--
1.7.6.5
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[PATCH v4 1/2] ARM: Exynos5250: Enabling samsung-usb2phy driver
Adding usbphy node for Exynos5250 along with the
necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 59be603..5ef9c1e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -416,6 +416,21 @@
clock-names = "usbhost";
};
+ usbphy@1213 {
+ compatible = "samsung,exynos5250-usb2phy";
+ reg = <0x1213 0x100>;
+ clocks = <&clock 1>, <&clock 285>;
+ clock-names = "ext_xtal", "usbhost";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ reg = <0x10040704 0x8>,
+ <0x10050230 0x4>;
+ };
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.7.6.5
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[PATCH v4 0/2] ARM: Exynos5250: Enabling samsung usb phy
Based on 'for-next' of linux-samsung tree with following patches from Doug on top: usb: Document clocks in samsung, exynos4210-ehci/ohci bindings ARM: dts: add usb 2.0 clock references to exynos5250 device tree Also depending upon following patch-series for Samsung-usb-phy driver: [PATCH v7 0/2] Adding USB 3.0 DRD-phy support for exynos5250 Changes from v3: Added 'clocks' and 'clock-names' entry also in device nodes, aligning with common clock framework for Samsung's SoCs. Vivek Gautam (2): ARM: Exynos5250: Enabling samsung-usb2phy driver ARM: Exynos5250: Enabling samsung-usb3phy driver arch/arm/boot/dts/exynos5250.dtsi | 29 + 1 files changed, 29 insertions(+), 0 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 2/2] usb: dwc3: exynos: use clk_prepare_enable and clk_disable_unprepare
Hi, On Thu, Mar 14, 2013 at 4:23 PM, Felipe Balbi wrote: > Hi, > > On Thu, Mar 14, 2013 at 04:14:58PM +0530, Vivek Gautam wrote: >> Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare >> calls as required by common clock framework. >> >> Signed-off-by: Vivek Gautam >> CC: Felipe Balbi >> CC: Kukjin Kim >> --- >> drivers/usb/dwc3/dwc3-exynos.c |6 +++--- >> 1 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c >> index 66ca9ac..b03f609 100644 >> --- a/drivers/usb/dwc3/dwc3-exynos.c >> +++ b/drivers/usb/dwc3/dwc3-exynos.c >> @@ -129,7 +129,7 @@ static int dwc3_exynos_probe(struct platform_device >> *pdev) >> exynos->dev = dev; >> exynos->clk = clk; >> >> - clk_enable(exynos->clk); >> + clk_prepare_enable(exynos->clk); > > eventually we need to pass this clock handling to dwc3/core.c. Just make > sure it's optional since not all platforms need it. > True, as of now i could see only exynos platform getting a device clock for dwc3-glue. So, if not all platforms need to do this, why should we plan to move this to dwc3/core.c ? > I guess the best way would be to handle clocks via > ->runtime_suspend()/->runtime_resume() ?? Right, but there was a doubt actually if you can please clear that. In device probe, after enabling runtime_pm we would need to 'pm_runtime_get_sync' the device. Thereby, in runtime_resume the clocks will be enabled. Now as soon as the device probe finishes, the device will go in suspend state, calling runtime_suspend and the clocks would be disabled. Now would it be possible for the controller to detect any connect/disconnect. Pardon me if there is something very silly i am missing out. > > -- > balbi -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v2 1/2] usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev
Used of_platform_populate() to create dwc3 core platform_device
from device tree data. Additionally some cleanup is also done.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
Changes from v1:
- Added method to unregister dwc3 core from dwc3_exynos_remove()
using device_for_each_child() API, which we missed to do.
drivers/usb/dwc3/dwc3-exynos.c | 56 ++--
1 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index e12e452..f77ec75 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -22,9 +22,9 @@
#include
#include
#include
+#include
struct dwc3_exynos {
- struct platform_device *dwc3;
struct platform_device *usb2_phy;
struct platform_device *usb3_phy;
struct device *dev;
@@ -86,21 +86,30 @@ err1:
return ret;
}
+static int dwc3_exynos_remove_child(struct device *dev, void *unused)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+
+ platform_device_unregister(pdev);
+
+ return 0;
+}
+
static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
static int dwc3_exynos_probe(struct platform_device *pdev)
{
- struct platform_device *dwc3;
struct dwc3_exynos *exynos;
struct clk *clk;
struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
int ret = -ENOMEM;
exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
if (!exynos) {
dev_err(dev, "not enough memory\n");
- return -ENOMEM;
+ goto err1;
}
/*
@@ -108,21 +117,15 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
* Since shared usb code relies on it, set it here for now.
* Once we move to full device tree support this will vanish off.
*/
- if (!pdev->dev.dma_mask)
- pdev->dev.dma_mask = &dwc3_exynos_dma_mask;
+ if (!dev->dma_mask)
+ dev->dma_mask = &dwc3_exynos_dma_mask;
platform_set_drvdata(pdev, exynos);
ret = dwc3_exynos_register_phys(exynos);
if (ret) {
dev_err(dev, "couldn't register PHYs\n");
- return ret;
- }
-
- dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
- if (!dwc3) {
- dev_err(dev, "couldn't allocate dwc3 device\n");
- return -ENOMEM;
+ goto err1;
}
clk = devm_clk_get(dev, "usbdrd30");
@@ -132,27 +135,20 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
goto err1;
}
- dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
-
- dwc3->dev.parent = dev;
- dwc3->dev.dma_mask = dev->dma_mask;
- dwc3->dev.dma_parms = dev->dma_parms;
- exynos->dwc3= dwc3;
exynos->dev = dev;
exynos->clk = clk;
clk_enable(exynos->clk);
- ret = platform_device_add_resources(dwc3, pdev->resource,
- pdev->num_resources);
- if (ret) {
- dev_err(dev, "couldn't add resources to dwc3 device\n");
- goto err2;
- }
-
- ret = platform_device_add(dwc3);
- if (ret) {
- dev_err(dev, "failed to register dwc3 device\n");
+ if (node) {
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwc3 core\n");
+ goto err2;
+ }
+ } else {
+ dev_err(dev, "no device node, failed to add dwc3 core\n");
+ ret = -ENODEV;
goto err2;
}
@@ -161,8 +157,6 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
err2:
clk_disable(clk);
err1:
- platform_device_put(dwc3);
-
return ret;
}
@@ -170,9 +164,9 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
{
struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
- platform_device_unregister(exynos->dwc3);
platform_device_unregister(exynos->usb2_phy);
platform_device_unregister(exynos->usb3_phy);
+ device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
clk_disable(exynos->clk);
--
1.7.6.5
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Re: [PATCH 1/2] usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev
On Thu, Mar 14, 2013 at 4:21 PM, Felipe Balbi wrote:
> Hi,
>
> On Thu, Mar 14, 2013 at 04:14:57PM +0530, Vivek Gautam wrote:
>> @@ -170,7 +155,6 @@ static int dwc3_exynos_remove(struct platform_device
>> *pdev)
>> {
>> struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
>>
>> - platform_device_unregister(exynos->dwc3);
>
> don't you want to do what Kishon did here and have:
>
> static int dwc3_exynos_remove_child(struct device *dev, void *unused)
> {
> struct platform_device *pdev = to_platform_device(dev);
>
> platform_device_unregister(pdev);
>
> return 0;
> }
>
> device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
>
> ???
Hmm, right. We need to do that. :-)
>
> --
> balbi
--
Thanks & Regards
Vivek
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[PATCH 2/2] usb: dwc3: exynos: use clk_prepare_enable and clk_disable_unprepare
Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
calls as required by common clock framework.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
drivers/usb/dwc3/dwc3-exynos.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 66ca9ac..b03f609 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -129,7 +129,7 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
exynos->dev = dev;
exynos->clk = clk;
- clk_enable(exynos->clk);
+ clk_prepare_enable(exynos->clk);
if (node) {
ret = of_platform_populate(node, NULL, NULL, dev);
@@ -146,7 +146,7 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
return 0;
err2:
- clk_disable(clk);
+ clk_disable_unprepare(clk);
err1:
return ret;
}
@@ -158,7 +158,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
platform_device_unregister(exynos->usb2_phy);
platform_device_unregister(exynos->usb3_phy);
- clk_disable(exynos->clk);
+ clk_disable_unprepare(exynos->clk);
return 0;
}
--
1.7.6.5
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[PATCH 1/2] usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev
Used of_platform_populate() to create dwc3 core platform_device
from device tree data. Additionally some cleanup is also done.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
drivers/usb/dwc3/dwc3-exynos.c | 46 +---
1 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index e12e452..66ca9ac 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -22,9 +22,9 @@
#include
#include
#include
+#include
struct dwc3_exynos {
- struct platform_device *dwc3;
struct platform_device *usb2_phy;
struct platform_device *usb3_phy;
struct device *dev;
@@ -90,17 +90,17 @@ static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
static int dwc3_exynos_probe(struct platform_device *pdev)
{
- struct platform_device *dwc3;
struct dwc3_exynos *exynos;
struct clk *clk;
struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
int ret = -ENOMEM;
exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
if (!exynos) {
dev_err(dev, "not enough memory\n");
- return -ENOMEM;
+ goto err1;
}
/*
@@ -108,21 +108,15 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
* Since shared usb code relies on it, set it here for now.
* Once we move to full device tree support this will vanish off.
*/
- if (!pdev->dev.dma_mask)
- pdev->dev.dma_mask = &dwc3_exynos_dma_mask;
+ if (!dev->dma_mask)
+ dev->dma_mask = &dwc3_exynos_dma_mask;
platform_set_drvdata(pdev, exynos);
ret = dwc3_exynos_register_phys(exynos);
if (ret) {
dev_err(dev, "couldn't register PHYs\n");
- return ret;
- }
-
- dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
- if (!dwc3) {
- dev_err(dev, "couldn't allocate dwc3 device\n");
- return -ENOMEM;
+ goto err1;
}
clk = devm_clk_get(dev, "usbdrd30");
@@ -132,27 +126,20 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
goto err1;
}
- dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
-
- dwc3->dev.parent = dev;
- dwc3->dev.dma_mask = dev->dma_mask;
- dwc3->dev.dma_parms = dev->dma_parms;
- exynos->dwc3= dwc3;
exynos->dev = dev;
exynos->clk = clk;
clk_enable(exynos->clk);
- ret = platform_device_add_resources(dwc3, pdev->resource,
- pdev->num_resources);
- if (ret) {
- dev_err(dev, "couldn't add resources to dwc3 device\n");
- goto err2;
- }
-
- ret = platform_device_add(dwc3);
- if (ret) {
- dev_err(dev, "failed to register dwc3 device\n");
+ if (node) {
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwc3 core\n");
+ goto err2;
+ }
+ } else {
+ dev_err(dev, "no device node, failed to add dwc3 core\n");
+ ret = -ENODEV;
goto err2;
}
@@ -161,8 +148,6 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
err2:
clk_disable(clk);
err1:
- platform_device_put(dwc3);
-
return ret;
}
@@ -170,7 +155,6 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
{
struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
- platform_device_unregister(exynos->dwc3);
platform_device_unregister(exynos->usb2_phy);
platform_device_unregister(exynos->usb3_phy);
--
1.7.6.5
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[PATCH 0/2] dwc3: exynos: Device tree fixes
This patch-set modifies dwc3-exynos as per latest bindings available for dwc3. Now the dwc3 core also has device support, there's no need to add platform device for core in glue layers. This change has come as a result of discussion happened in: [PATCH RFC] usb: dwc3: Get PHY from platform specific dwc3 dt node. Additionally, now that Samsung exynos series has moved to common clock framework, we use clock_prepare_enable() and clock_disable_unprepare() APIs. Some cleanup is also done here. Based on 'usb-next' plus Felipe's 'testing' branch patches; (some 194 patches in fact ;-), on top of 3.9rc2 tag). Also based on: "usb: dwc3: set dma_mask for dwc3_omap device" by Kishon in which DMA mask for dwc3-core is being set from its parent. Vivek Gautam (2): usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev usb: dwc3: exynos: use clk_prepare_enable and clk_disable_unprepare drivers/usb/dwc3/dwc3-exynos.c | 54 ++-- 1 files changed, 19 insertions(+), 35 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v7 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.
Signed-off-by: Vivek Gautam
Signed-off-by: Felipe Balbi
Acked-by: Kukjin Kim
---
.../devicetree/bindings/usb/samsung-usbphy.txt | 54 +++
drivers/usb/phy/Kconfig|7 +
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/phy-samsung-usb.h | 80 +
drivers/usb/phy/phy-samsung-usb3.c | 349
5 files changed, 491 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/phy/phy-samsung-usb3.c
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 96940ab..f575302 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -61,3 +61,57 @@ Example:
reg = <0x10020704 0x8>;
};
};
+
+
+** Samsung's usb 3.0 phy transceiver
+
+Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
+which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
+controllers across Samsung SOCs.
+
+Required properties:
+
+Exynos5250:
+- compatible : should be "samsung,exynos5250-usb3phy"
+- reg : base physical address of the phy registers and length of memory mapped
+ region.
+- clocks: Clock IDs array as required by the controller.
+- clock-names: names of clocks correseponding to IDs in the clock property
+ as requested by the controller driver.
+
+Optional properties:
+- #address-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- #size-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- ranges: allows valid translation between child's address space and parent's
+ address space.
+
+- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
+ interface for usb-phy. It should provide the following information required
by
+ usb-phy controller to control phy.
+ - reg : base physical address of PHY_CONTROL registers.
+ The size of this register is the total sum of size of all PHY_CONTROL
+ registers that the SoC has. For example, the size will be
+ '0x4' in case we have only one PHY_CONTROL register (e.g.
+ OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
+ and, '0x8' in case we have two PHY_CONTROL registers (e.g.
+ USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
+ and so on.
+
+Example:
+ usbphy@1210 {
+ compatible = "samsung,exynos5250-usb3phy";
+ reg = <0x1210 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&clock 1>, <&clock 286>;
+ clock-names = "ext_xtal", "usbdrd30";
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = <0x10040704 0x8>;
+ };
+ };
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e8cd52a..7e8fe0f 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -99,6 +99,13 @@ config SAMSUNG_USB2PHY
Enable this to support Samsung USB 2.0 (High Speed) PHY controller
driver for Samsung SoCs.
+config SAMSUNG_USB3PHY
+ tristate "Samsung USB 3.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
+ help
+ Enable this to support Samsung USB 3.0 (Super Speed) phy controller
+ for samsung SoCs.
+
config TWL4030_USB
tristate "TWL4030 USB Transceiver Driver"
depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 8cd355f..33863c0 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_OMAP_USB2) +=
phy-omap-usb2.o
obj-$(CONFIG_OMAP_USB3)+= phy-omap-usb3.o
obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
+obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
diff --git a/drivers/usb/phy/phy-samsung-usb.h
b/drivers/usb/phy/phy-samsung-usb.h
index 481737d7..70a9cae 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -145,6 +145,86 @@
#define EXYNOS5_PHY_OTG_TUNE
[PATCH v7 1/2] usb: phy: samsung: Common out the generic stuff
Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common phy helper driver under SAMSUNG_USBPHY,
and moving USB 2.0 PHY driver under SAMSUNG_USB2PHY.
Also allowing samsung PHY drivers be built as modules.
Signed-off-by: Vivek Gautam
Signed-off-by: Felipe Balbi
Acked-by: Kukjin Kim
---
.../devicetree/bindings/usb/samsung-usbphy.txt | 22 +-
drivers/usb/phy/Kconfig| 15 +-
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/phy-samsung-usb.c | 726 +---
drivers/usb/phy/phy-samsung-usb.h | 247 +++
drivers/usb/phy/phy-samsung-usb2.c | 509 ++
6 files changed, 800 insertions(+), 720 deletions(-)
create mode 100644 drivers/usb/phy/phy-samsung-usb.h
create mode 100644 drivers/usb/phy/phy-samsung-usb2.c
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 0331949..96940ab 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -1,20 +1,25 @@
-* Samsung's usb phy transceiver
+SAMSUNG USB-PHY controllers
-The Samsung's phy transceiver is used for controlling usb phy for
-s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
-across Samsung SOCs.
+** Samsung's usb 2.0 phy transceiver
+
+The Samsung's usb 2.0 phy transceiver is used for controlling
+usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
+usb controllers across Samsung SOCs.
TODO: Adding the PHY binding with controller(s) according to the under
developement generic PHY driver.
Required properties:
Exynos4210:
-- compatible : should be "samsung,exynos4210-usbphy"
+- compatible : should be "samsung,exynos4210-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
+- clocks: Clock IDs array as required by the controller.
+- clock-names: names of clock correseponding IDs clock property as requested
+ by the controller driver.
Exynos5250:
-- compatible : should be "samsung,exynos5250-usbphy"
+- compatible : should be "samsung,exynos5250-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
@@ -44,10 +49,13 @@ Example:
usbphy@125B {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "samsung,exynos4210-usbphy";
+ compatible = "samsung,exynos4210-usb2phy";
reg = <0x125B 0x100>;
ranges;
+ clocks = <&clock 2>, <&clock 305>;
+ clock-names = "xusbxti", "otg";
+
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = <0x10020704 0x8>;
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 97de6de..e8cd52a 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -86,11 +86,18 @@ config OMAP_USB3
on/off the PHY.
config SAMSUNG_USBPHY
- bool "Samsung USB PHY controller Driver"
- depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+ tristate "Samsung USB PHY Driver"
help
- Enable this to support Samsung USB phy controller for samsung
- SoCs.
+ Enable this to support Samsung USB phy helper driver for Samsung SoCs.
+ This driver provides common interface to interact, for Samsung USB
2.0 PHY
+ driver and later for Samsung USB 3.0 PHY driver.
+
+config SAMSUNG_USB2PHY
+ tristate "Samsung USB 2.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
+ help
+ Enable this to support Samsung USB 2.0 (High Speed) PHY controller
+ driver for Samsung SoCs.
config TWL4030_USB
tristate "TWL4030 USB Transceiver Driver"
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 5fb4a5d..8cd355f 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_CONTROL_USB)+=
phy-omap-control.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_OMAP_USB3)+= phy-omap-usb3.o
obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
+obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
diff --git a/drivers/usb/phy/phy-samsung-usb.c
b/drivers/usb/phy/phy-samsung-usb.c
index 967101e..7b118ee5 100644
[PATCH v7 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Changes from v6: - Changing the file names accordingly as per [PATCH] usb: phy: rename all phy drivers to phy-$name.c - Using devm_clk_get for PHY ref clocks "ext_xtal" and "xusbxti" - Adding the bindings documentation for separate USB 2.0 phy and USB 3.0 phy. Based on 'usb-next' plus Felipe's 'testing' branch patches; (some 194 patches in fact ;-), on top of 3.9rc2 tag). Tested after merging linux-samsung's 'for-next' into 'usb-next' to verify things with recently merged common clock framework for samsung's SoCs. Vivek Gautam (2): usb: phy: samsung: Common out the generic stuff usb: phy: samsung: Add PHY support for USB 3.0 controller .../devicetree/bindings/usb/samsung-usbphy.txt | 76 ++- drivers/usb/phy/Kconfig| 22 +- drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-samsung-usb.c | 726 +--- drivers/usb/phy/phy-samsung-usb.h | 327 + drivers/usb/phy/phy-samsung-usb2.c | 509 ++ drivers/usb/phy/phy-samsung-usb3.c | 349 ++ 7 files changed, 1291 insertions(+), 720 deletions(-) create mode 100644 drivers/usb/phy/phy-samsung-usb.h create mode 100644 drivers/usb/phy/phy-samsung-usb2.c create mode 100644 drivers/usb/phy/phy-samsung-usb3.c -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Hi Felipe, On Wed, Feb 27, 2013 at 8:13 PM, Vivek Gautam wrote: > Based on 'usb-next' > > Changes from v5: > - Squashed the following change from Felipe in this patch-set: >[PATCH] usb: phy: samsung: let it be built as a module > - Using EXPORT_SYMBOL_GPL() to export symbols in "samsung-usbphy.c" >to allow module builds of these samsung PHY drivers. > > Vivek Gautam (2): > usb: phy: samsung: Common out the generic stuff > usb: phy: samsung: Add PHY support for USB 3.0 controller > I am rebasing this pach-set on top of your PHY driver changes in 'testing' branch of your tree. I took first 194 patches ;) from top of testing branch (i could find these on top of 3.9 rc2 merge), and applied the same on 'usb-next' branch in my development tree in order to test further. I shall be posting these rebased patch-set, so that it will be easier for you to merge the changes in. Is there something you want to point out to me while i do this ? > drivers/usb/phy/Kconfig | 25 +- > drivers/usb/phy/Makefile |2 + > drivers/usb/phy/samsung-usb2phy.c | 511 ++ > drivers/usb/phy/samsung-usb3phy.c | 349 ++ > drivers/usb/phy/samsung-usbphy.c | 722 > + > drivers/usb/phy/samsung-usbphy.h | 328 + > 6 files changed, 1224 insertions(+), 713 deletions(-) > create mode 100644 drivers/usb/phy/samsung-usb2phy.c > create mode 100644 drivers/usb/phy/samsung-usb3phy.c > create mode 100644 drivers/usb/phy/samsung-usbphy.h > > -- > 1.7.6.5 > > ___ > devicetree-discuss mailing list > devicetree-discuss@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/devicetree-discuss -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH RFC] usb: dwc3: Get PHY from platform specific dwc3 dt node.
Hi, On Thu, Jan 31, 2013 at 9:08 PM, Felipe Balbi wrote: > On Thu, Jan 31, 2013 at 09:00:37PM +0530, Vivek Gautam wrote: >> Hi Felipe, >> >> >> On Thu, Jan 31, 2013 at 8:55 PM, Felipe Balbi wrote: >> > Hi, >> > >> > On Thu, Jan 31, 2013 at 08:53:27PM +0530, Vivek Gautam wrote: >> >> >> Moreover, SoCs having multiple dwc3 controllers will have multiple >> >> >> PHYs, which eventually be added using usb_add_phy_dev(), and not >> >> >> using usb_add_phy(). So each dwc3 controller won't be able to >> >> >> get PHYs by simply calling devm_usb_get_phy() also. >> >> > >> >> > No. We have added usb_get_phy_dev() for that purpose in the case of >> >> > non-dt. >> >> > I think, instead you can have a patch to use devm_usb_get_phy_dev() >> >> > here and >> >> > in exynos platform specific code use usb_bind_phy() to bind the phy and >> >> > controller till you change it to dt. >> >> > >> >> >> >> We have dt support for dwc3-exynos, in such case we should go ahead with >> >> of_platform_populate(), right ? >> >> But if when i use of_platform_populate() i will not be able to set >> >> dma_mask to dwc3->dev. :-( >> > >> > do you have a special need for dma_mask because OF already sets it. >> > >> If i am not wrong of_platform_device_create_pdata() will set >> "dev->dev.coherent_dma_mask = DMA_BIT_MASK(32)" >> and not dma_mask. >> I fact we had some discussion sometime back when we needed the same >> for dwc3-exynos in the thread: >> [PATCH v2 1/2] USB: dwc3-exynos: Add support for device tree >> >> But couldn't get final node on it. >> So suggestions here please. :-) > > hmm.. you're right there. Grant, Rob ? Any hints ? > Any suggestions on this ? > -- > balbi -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v6 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.
Signed-off-by: Vivek Gautam
Signed-off-by: Felipe Balbi
Acked-by: Kukjin Kim
---
drivers/usb/phy/Kconfig |8 +
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb3phy.c | 349 +
drivers/usb/phy/samsung-usbphy.h | 81 +
4 files changed, 439 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb3phy.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 4d72962..4f696d0 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -74,6 +74,14 @@ config SAMSUNG_USB2PHY
Enable this to support Samsung USB 2.0 (High Speed) PHY controller
driver for Samsung SoCs.
+config SAMSUNG_USB3PHY
+ tristate "Samsung USB 3.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
+ select USB_OTG_UTILS
+ help
+ Enable this to support Samsung USB 3.0 (Super Speed) phy controller
+ for samsung SoCs.
+
config SAMSUNG_USBPHY
tristate "Samsung USB PHY Driver"
help
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 1efa174..77f0b2e 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2phy.o
+obj-$(CONFIG_SAMSUNG_USB3PHY) += samsung-usb3phy.o
diff --git a/drivers/usb/phy/samsung-usb3phy.c
b/drivers/usb/phy/samsung-usb3phy.c
new file mode 100644
index 000..70e2c7b
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb3phy.c
@@ -0,0 +1,349 @@
+/* linux/drivers/usb/phy/samsung-usb3phy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Vivek Gautam
+ *
+ * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+/*
+ * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock
core.
+ */
+static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
+{
+ u32 reg;
+ u32 refclk;
+
+ refclk = sphy->ref_clk_freq;
+
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case FSEL_CLKSEL_50M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_20M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_19200K:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ case FSEL_CLKSEL_24M:
+ default:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
+static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyparam0;
+ u32 phyparam1;
+ u32 linksystem;
+ u32 phybatchg;
+ u32 phytest;
+ u32 phyclkrst;
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
+
+ phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
+ /* Select PHY CLK source */
+ phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+ /* Set Loss-of-Signal Detector sensitivity */
+ phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+ phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
+ writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
+
+ writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
+
+ /*
+* Setting the Frame length Adj value[6:1] to default 0x20
+* See xHCI 1.0 spec, 5.2.4
+*/
+ linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20);
+ writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
+
+ phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
+ /* Set Tx De-Emphasis level */
+ phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
+ phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
+
[PATCH v6 1/2] usb: phy: samsung: Common out the generic stuff
Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common phy helper driver under SAMSUNG_USBPHY,
and moving USB 2.0 PHY driver under SAMSUNG_USB2PHY.
Also allowing samsung PHY drivers be built as modules.
Signed-off-by: Vivek Gautam
Signed-off-by: Felipe Balbi
Acked-by: Kukjin Kim
---
drivers/usb/phy/Kconfig | 17 +-
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb2phy.c | 511 ++
drivers/usb/phy/samsung-usbphy.c | 722 +
drivers/usb/phy/samsung-usbphy.h | 247 +
5 files changed, 785 insertions(+), 713 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb2phy.c
create mode 100644 drivers/usb/phy/samsung-usbphy.h
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 65217a5..4d72962 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -66,10 +66,17 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called rcar-phy.
-config SAMSUNG_USBPHY
- bool "Samsung USB PHY controller Driver"
- depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+config SAMSUNG_USB2PHY
+ tristate "Samsung USB 2.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
select USB_OTG_UTILS
help
- Enable this to support Samsung USB phy controller for samsung
- SoCs.
+ Enable this to support Samsung USB 2.0 (High Speed) PHY controller
+ driver for Samsung SoCs.
+
+config SAMSUNG_USBPHY
+ tristate "Samsung USB PHY Driver"
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung SoCs.
+ This driver provides common interface to interact, for Samsung USB
2.0 PHY
+ driver and later for Samsung USB 3.0 PHY driver.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index b13faa1..1efa174 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
+obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2phy.o
diff --git a/drivers/usb/phy/samsung-usb2phy.c
b/drivers/usb/phy/samsung-usb2phy.c
new file mode 100644
index 000..55ac3a8
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb2phy.c
@@ -0,0 +1,511 @@
+/* linux/drivers/usb/phy/samsung-usb2phy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Praveen Paneri
+ *
+ * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
+ * OHCI-EXYNOS controllers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+int samsung_usb2phy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ if (!otg)
+ return -ENODEV;
+
+ if (!otg->host)
+ otg->host = host;
+
+ return 0;
+}
+
+static bool exynos5_phyhost_is_on(void *regs)
+{
+ u32 reg;
+
+ reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ return !(reg & HOST_CTRL0_SIDDQ);
+}
+
+static void samsung_exynos5_usb2phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyclk = sphy->ref_clk_freq;
+ u32 phyhost;
+ u32 phyotg;
+ u32 phyhsic;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+ atomic_inc(&sphy->phy_usage);
+
+ if (exynos5_phyhost_is_on(regs)) {
+ dev_info(sphy->dev, "Already power on PHY\n");
+ return;
+ }
+
+ /* Host configuration */
+ phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ /* phy reference clock configuration */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= HOST_CTRL0_FSEL(phyclk);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHYSWRST |
+ HOST_CTRL0_PHYSWRSTALL |
+ HOST_CTRL0_SIDDQ |
+ /
[PATCH v6 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Based on 'usb-next' Changes from v5: - Squashed the following change from Felipe in this patch-set: [PATCH] usb: phy: samsung: let it be built as a module - Using EXPORT_SYMBOL_GPL() to export symbols in "samsung-usbphy.c" to allow module builds of these samsung PHY drivers. Vivek Gautam (2): usb: phy: samsung: Common out the generic stuff usb: phy: samsung: Add PHY support for USB 3.0 controller drivers/usb/phy/Kconfig | 25 +- drivers/usb/phy/Makefile |2 + drivers/usb/phy/samsung-usb2phy.c | 511 ++ drivers/usb/phy/samsung-usb3phy.c | 349 ++ drivers/usb/phy/samsung-usbphy.c | 722 + drivers/usb/phy/samsung-usbphy.h | 328 + 6 files changed, 1224 insertions(+), 713 deletions(-) create mode 100644 drivers/usb/phy/samsung-usb2phy.c create mode 100644 drivers/usb/phy/samsung-usb3phy.c create mode 100644 drivers/usb/phy/samsung-usbphy.h -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RESEND PATCH v9 0/2] usb: phy: samsung: Introducing usb phy driver for samsung SoCs
Hi Balbi, On Wed, Feb 27, 2013 at 1:45 PM, Felipe Balbi wrote: > Hi, > > On Fri, Jan 18, 2013 at 02:30:21PM +0530, Praveen Paneri wrote: >> Changes from v8: >> Resending this patch series after rebasing to the latest usb-next branch. >> Rewording inline comments for better readability. >> Removed IS_ENABLED(CONFIG_OF) as pdev->dev.of_node is enough to check for dt >> support. >> Using of_match_ptr to add of_match_table to platform_driver structure. >> Removed unnecessary variables. > > trying applying these but it doesn't apply unfortunately. > Already present in 3.8.0 ? ;-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v5 1/4] ARM: Exynos5250: Enabling ehci-s5p driver
On Sat, Feb 9, 2013 at 4:05 AM, Kukjin Kim wrote:
> Vivek Gautam wrote:
>>
>> Adding EHCI device tree node for Exynos5250 along with
>> the device base adress and gpio line for vbus.
>>
>> Signed-off-by: Vivek Gautam
>> Acked-by: Jingoo Han
>> Acked-by: Grant Likely
>> ---
>>
>> Changes from v4:
>> - Added gpio line for VBUS of USB2.0 on snow board.
>>
>> .../devicetree/bindings/usb/exynos-usb.txt | 25
>>
>> arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
>> arch/arm/boot/dts/exynos5250-snow.dts |4 +++
>> arch/arm/boot/dts/exynos5250.dtsi |6
>> 4 files changed, 39 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/usb/exynos-
>> usb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> b/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> new file mode 100644
>> index 000..e8bbb47
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> @@ -0,0 +1,25 @@
>> +Samsung Exynos SoC USB controller
>> +
>> +The USB devices interface with USB controllers on Exynos SOCs.
>> +The device node has following properties.
>> +
>> +EHCI
>> +Required properties:
>> + - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
>> + EHCI controller in host mode.
>> + - reg: physical base address of the controller and length of memory
>> mapped
>> + region.
>> + - interrupts: interrupt number to the cpu.
>> +
>> +Optional properties:
>> + - samsung,vbus-gpio: if present, specifies the GPIO that
>> + needs to be pulled up for the bus to be powered.
>> +
>> +Example:
>> +
>> + usb@1211 {
>> + compatible = "samsung,exynos4210-ehci";
>> + reg = <0x1211 0x100>;
>> + interrupts = <0 71 0>;
>> + samsung,vbus-gpio = <&gpx2 6 1 3 3>;
>> + };
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 942d576..7363e14 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -204,4 +204,8 @@
>> samsung,mfc-r = <0x4300 0x80>;
>> samsung,mfc-l = <0x5100 0x80>;
>> };
>> +
>> + usb@1211 {
>> + samsung,vbus-gpio = <&gpx2 6 1 3 3>;
>> + };
>> };
>> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
>> b/arch/arm/boot/dts/exynos5250-snow.dts
>> index 17dd951..47b6b84 100644
>> --- a/arch/arm/boot/dts/exynos5250-snow.dts
>> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
>> @@ -40,4 +40,8 @@
>> <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
>> };
>> };
>> +
>> + usb@1211 {
>> + samsung,vbus-gpio = <&gpx1 1 1 3 3>;
>> + };
>> };
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index 30485de..2cbe53e 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -275,6 +275,12 @@
>> #size-cells = <0>;
>> };
>>
>> + usb@1211 {
>> + compatible = "samsung,exynos4210-ehci";
>> + reg = <0x1211 0x100>;
>> + interrupts = <0 71 0>;
>> + };
>> +
>> amba {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> --
>> 1.7.6.5
>
> Looks good to me and applied this and "[PATCH v3 2/4] ARM: Exynos5250:
> Enabling ohci-exynos driver" in Samsung tree.
>
> Note, I think, you need to implement to use pinctrl for this instead of old
> gpio bindings next time, probably after release v3.9-rc1.
>
Sure, will add the necessary pinctrl support replacing the old gpio bindings,
and post the same asap. :-)
> Ah, one more, please use subject lines appropriate like others, "ARM: dts:
> ".
>
Sorry, for misleading subject line, will keep commit titles
aligned-with in future,
> Thanks.
>
> - Kukjin
>
--
Thanks & Regards
Vivek
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Re: [PATCH v5 0/2] Adding USB 3.0 DRD-phy support for exynos5250
On Wed, Feb 13, 2013 at 2:02 PM, Felipe Balbi wrote: > On Tue, Feb 12, 2013 at 10:31:00PM -0800, kg...@kernel.org wrote: >> Vivek Gautam wrote: >> > >> > Based on 'usb-next' >> > >> > Changes from v4: >> > - Modifying function names and driver names to follow a common >> >naming convention. >> > "usb2phy" for samsung-usb2phy driver >> > "usb3phy" for samsung-usb3phy driver >> > - Changing file names "samsung-usb2.c" to "samsung-usb2phy.c" and, >> >"samsung-usb3.c" to "samsung-usb3phy.c" >> > - Removing dependencies for SAMSUNG_USB2PHY and >> > SAMSUNG_USB3PHY. >> > - Arranging SAMSUNG_USB2PHY and SAMSUNG_USB3PHY to select >> > SAMSUNG_USBPHY, >> >which is the usb-phy helper driver. >> > >> > Vivek Gautam (2): >> > usb: phy: samsung: Common out the generic stuff >> > usb: phy: samsung: Add PHY support for USB 3.0 controller >> > >> > drivers/usb/phy/Kconfig | 25 +- >> > drivers/usb/phy/Makefile |2 + >> > drivers/usb/phy/samsung-usb2phy.c | 511 >> > ++ >> > drivers/usb/phy/samsung-usb3phy.c | 349 ++ >> > drivers/usb/phy/samsung-usbphy.c | 717 >> + >> > drivers/usb/phy/samsung-usbphy.h | 328 + >> > 6 files changed, 1219 insertions(+), 713 deletions(-) >> > create mode 100644 drivers/usb/phy/samsung-usb2phy.c >> > create mode 100644 drivers/usb/phy/samsung-usb3phy.c >> > create mode 100644 drivers/usb/phy/samsung-usbphy.h >> > >> > -- >> > 1.7.6.5 >> >> For now, looks good to me, and if any enhancement is required, it can be >> done next time. >> >> Felipe, please go ahead with my ack :-) >> Acked-by: Kukjin Kim > > Thank you, but it's too late for v3.9, this will have to wait until > v3.10. You will get an email once I apply these to my branch. > Sure, thanks :) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v3 2/2] ARM: Exynos5250: Enabling samsung-usb3phy driver
Adding device node for Samsung USB 3.0 PHY controller driver
on Exynos5250 along with the necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index d1865a8..451dcdb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -99,6 +99,18 @@
interrupts = <0 65 0>;
};
+ usbphy@1210 {
+ compatible = "samsung,exynos5250-usb3phy";
+ reg = <0x1210 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ reg = <0x10040704 0x8>;
+ };
+ };
+
usbphy@1213 {
compatible = "samsung,exynos5250-usb2phy";
reg = <0x1213 0x100>;
--
1.7.6.5
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[PATCH v3 1/2] ARM: Exynos5250: Enabling samsung-usb2phy driver
Adding device node for Samsung USB 2.0 PHY controller driver
on Exynos5250 along with the necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..d1865a8 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -99,6 +99,19 @@
interrupts = <0 65 0>;
};
+ usbphy@1213 {
+ compatible = "samsung,exynos5250-usb2phy";
+ reg = <0x1213 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ reg = <0x10040704 0x8>,
+ <0x10050230 0x4>;
+ };
+ };
+
serial@12C0 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C0 0x100>;
--
1.7.6.5
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[PATCH v3 0/2] ARM: Exynos5250: Enabling samsung usb phy
Based on for-next of 'linux-samsung' tree. Aligned with following patches for separate PHY drivers for USB 2.0 and USB 3.0 for Samsung SoCs. [PATCH v5 1/2] usb: phy: samsung: Common out the generic stuff [PATCH v5 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller Changes from v2: - Putting device nodes in order of device addresses. Changes from v1: - Putting separate device nodes for usb 2.0 phy and usb 3.0 phy based on separate driver for samsung usb 3.0 phy and samsung usb 2.0 phy: [PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250 [PATCH v8 0/4] Adding usb2.0 host-phy support for exynos5250 - Aligning as per the patch: usb: phy: samsung: Add support to set pmu isolation - Replaced phy-handle approach for PHY CONTROL registers to child nodes. - Removing AUX data entry from exynos5250 dt file. Vivek Gautam (2): ARM: Exynos5250: Enabling samsung-usb2phy driver ARM: Exynos5250: Enabling samsung-usb3phy driver arch/arm/boot/dts/exynos5250.dtsi | 25 + 1 files changed, 25 insertions(+), 0 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/Kconfig |8 +
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb3phy.c | 349 +
drivers/usb/phy/samsung-usbphy.h | 81 +
4 files changed, 439 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb3phy.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index b28878d..723d7b1 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -74,6 +74,14 @@ config SAMSUNG_USB2PHY
Enable this to support Samsung USB 2.0 (High Speed) PHY controller
driver for Samsung SoCs.
+config SAMSUNG_USB3PHY
+ bool "Samsung USB 3.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
+ select USB_OTG_UTILS
+ help
+ Enable this to support Samsung USB 3.0 (Super Speed) phy controller
+ for samsung SoCs.
+
config SAMSUNG_USBPHY
bool "Samsung USB PHY Driver"
help
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 1efa174..77f0b2e 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2phy.o
+obj-$(CONFIG_SAMSUNG_USB3PHY) += samsung-usb3phy.o
diff --git a/drivers/usb/phy/samsung-usb3phy.c
b/drivers/usb/phy/samsung-usb3phy.c
new file mode 100644
index 000..70e2c7b
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb3phy.c
@@ -0,0 +1,349 @@
+/* linux/drivers/usb/phy/samsung-usb3phy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Vivek Gautam
+ *
+ * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+/*
+ * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock
core.
+ */
+static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
+{
+ u32 reg;
+ u32 refclk;
+
+ refclk = sphy->ref_clk_freq;
+
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case FSEL_CLKSEL_50M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_20M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_19200K:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ case FSEL_CLKSEL_24M:
+ default:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
+static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyparam0;
+ u32 phyparam1;
+ u32 linksystem;
+ u32 phybatchg;
+ u32 phytest;
+ u32 phyclkrst;
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
+
+ phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
+ /* Select PHY CLK source */
+ phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+ /* Set Loss-of-Signal Detector sensitivity */
+ phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+ phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
+ writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
+
+ writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
+
+ /*
+* Setting the Frame length Adj value[6:1] to default 0x20
+* See xHCI 1.0 spec, 5.2.4
+*/
+ linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20);
+ writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
+
+ phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
+ /* Set Tx De-Emphasis level */
+ phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
+ phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
+ writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1);
+
+
[PATCH v5 1/2] usb: phy: samsung: Common out the generic stuff
Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common phy helper driver under SAMSUNG_USBPHY,
and moving USB 2.0 PHY driver under SAMSUNG_USB2PHY.
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/Kconfig | 17 +-
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb2phy.c | 511 ++
drivers/usb/phy/samsung-usbphy.c | 717 +
drivers/usb/phy/samsung-usbphy.h | 247 +
5 files changed, 780 insertions(+), 713 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb2phy.c
create mode 100644 drivers/usb/phy/samsung-usbphy.h
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 65217a5..b28878d 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -66,10 +66,17 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called rcar-phy.
-config SAMSUNG_USBPHY
- bool "Samsung USB PHY controller Driver"
- depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+config SAMSUNG_USB2PHY
+ bool "Samsung USB 2.0 PHY controller Driver"
+ select SAMSUNG_USBPHY
select USB_OTG_UTILS
help
- Enable this to support Samsung USB phy controller for samsung
- SoCs.
+ Enable this to support Samsung USB 2.0 (High Speed) PHY controller
+ driver for Samsung SoCs.
+
+config SAMSUNG_USBPHY
+ bool "Samsung USB PHY Driver"
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung SoCs.
+ This driver provides common interface to interact, for Samsung USB
2.0 PHY
+ driver and later for Samsung USB 3.0 PHY driver.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index b13faa1..1efa174 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
+obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2phy.o
diff --git a/drivers/usb/phy/samsung-usb2phy.c
b/drivers/usb/phy/samsung-usb2phy.c
new file mode 100644
index 000..55ac3a8
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb2phy.c
@@ -0,0 +1,511 @@
+/* linux/drivers/usb/phy/samsung-usb2phy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Praveen Paneri
+ *
+ * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
+ * OHCI-EXYNOS controllers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+int samsung_usb2phy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ if (!otg)
+ return -ENODEV;
+
+ if (!otg->host)
+ otg->host = host;
+
+ return 0;
+}
+
+static bool exynos5_phyhost_is_on(void *regs)
+{
+ u32 reg;
+
+ reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ return !(reg & HOST_CTRL0_SIDDQ);
+}
+
+static void samsung_exynos5_usb2phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyclk = sphy->ref_clk_freq;
+ u32 phyhost;
+ u32 phyotg;
+ u32 phyhsic;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+ atomic_inc(&sphy->phy_usage);
+
+ if (exynos5_phyhost_is_on(regs)) {
+ dev_info(sphy->dev, "Already power on PHY\n");
+ return;
+ }
+
+ /* Host configuration */
+ phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ /* phy reference clock configuration */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= HOST_CTRL0_FSEL(phyclk);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHYSWRST |
+ HOST_CTRL0_PHYSWRSTALL |
+ HOST_CTRL0_SIDDQ |
+ /* Enable normal mode of operation */
+ HOST_CTRL0_FORCESUSPEND |
+ HOST_CT
[PATCH v5 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Based on 'usb-next' Changes from v4: - Modifying function names and driver names to follow a common naming convention. "usb2phy" for samsung-usb2phy driver "usb3phy" for samsung-usb3phy driver - Changing file names "samsung-usb2.c" to "samsung-usb2phy.c" and, "samsung-usb3.c" to "samsung-usb3phy.c" - Removing dependencies for SAMSUNG_USB2PHY and SAMSUNG_USB3PHY. - Arranging SAMSUNG_USB2PHY and SAMSUNG_USB3PHY to select SAMSUNG_USBPHY, which is the usb-phy helper driver. Vivek Gautam (2): usb: phy: samsung: Common out the generic stuff usb: phy: samsung: Add PHY support for USB 3.0 controller drivers/usb/phy/Kconfig | 25 +- drivers/usb/phy/Makefile |2 + drivers/usb/phy/samsung-usb2phy.c | 511 ++ drivers/usb/phy/samsung-usb3phy.c | 349 ++ drivers/usb/phy/samsung-usbphy.c | 717 + drivers/usb/phy/samsung-usbphy.h | 328 + 6 files changed, 1219 insertions(+), 713 deletions(-) create mode 100644 drivers/usb/phy/samsung-usb2phy.c create mode 100644 drivers/usb/phy/samsung-usb3phy.c create mode 100644 drivers/usb/phy/samsung-usbphy.h -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Hi Kukjin,
On Wed, Jan 30, 2013 at 11:31 AM, Kukjin Kim wrote:
> Vivek Gautam wrote:
>>
>> Adding PHY driver support for USB 3.0 controller for Samsung's
>> SoCs.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>>
>> Changes from v3:
>> - Making SAMSUNG_USB3PHY dependent on SAMSUNG_USBPHY.
>> - Adding USB_DWC3 to dependencies of SAMSUNG_USB2PHY since
>>dwc3 controller also looks for USB2 type PHY.
>>
>> drivers/usb/phy/Kconfig | 11 +-
>> drivers/usb/phy/Makefile |1 +
>> drivers/usb/phy/samsung-usb3.c | 349
>> ++
>> drivers/usb/phy/samsung-usbphy.h | 81 +
>> 4 files changed, 441 insertions(+), 1 deletions(-)
>> create mode 100644 drivers/usb/phy/samsung-usb3.c
>>
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index cc0d230..9325a95 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -52,14 +52,23 @@ config SAMSUNG_USBPHY
>> help
>> Enable this to support Samsung USB phy controllers for Samsung
>> SoCs.
>> + Further enable USB 2.0 type PHY or USB 3.0 type PHY as required
>> + for USB controllers in use.
>>
>> if SAMSUNG_USBPHY
>>
>> config SAMSUNG_USB2PHY
>> bool "Samsung USB 2.0 PHY controller Driver"
>> - depends on USB_S3C_HSOTG || USB_EHCI_S5P ||
>> USB_OHCI_EXYNOS
>> + depends on USB_S3C_HSOTG || USB_EHCI_S5P ||
>> USB_OHCI_EXYNOS || USB_DWC3
>> help
>> Enable this to support Samsung USB 2.0 (High Speed) phy controller
>> for Samsung SoCs.
>>
>> +config SAMSUNG_USB3PHY
>> + bool "Samsung USB 3.0 PHY controller Driver"
>> + depends on USB_DWC3
>> + help
>> + Enable this to support Samsung USB 3.0 (Super Speed) phy
>> controller
>> + for samsung SoCs.
>> +
>> endif
>
> It mean, when USB_DWC3 is selected, we can select only one USB2PHY or
> USB3PHY?
>
Actually, DWC3 expects both USB2PHY and USB3PHY, so went this way.
But this seems bad :-(
Will remove these dependencies as suggested by Felipe also.
> [...]
>
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id samsung_usbphy_dt_match[] = {
>> + {
>> + .compatible = "samsung,exynos5250-usb3-phy",
>> + .data = &usb3_phy_exynos5
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
>> +#endif
>> +
>> +static struct platform_device_id samsung_usbphy_driver_ids[] = {
>> + {
>> + .name = "exynos5250-usb3-phy",
>
> According to the name of file, exynos5250-usb3phy? Just it is imho...
>
Ok, sure will amend this.
>> + .driver_data= (unsigned long)&usb3_phy_exynos5,
>> + },
>> + {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
>> +
>> +static struct platform_driver samsung_usb3_phy_driver = {
>> + .probe = samsung_usb3_phy_probe,
>> + .remove = samsung_usb3_phy_remove,
>> + .id_table = samsung_usbphy_driver_ids,
>> + .driver = {
>> + .name = "samsung-usb3-phy",
>> + .owner = THIS_MODULE,
>> + .of_match_table =
>> of_match_ptr(samsung_usbphy_dt_match),
>> + },
>> +};
>> +
>> +module_platform_driver(samsung_usb3_phy_driver);
>> +
>> +MODULE_DESCRIPTION("Samsung USB 3.0 phy controller");
>> +MODULE_AUTHOR("Vivek Gautam ");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:samsung-usb3-phy");
>
> I want you to use same naming rule.
>
Sure.
--
Thanks & Regards
Vivek
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Re: [PATCH v4 1/2] usb: phy: samsung: Common out the generic stuff
Hi Kukjin, On Wed, Jan 30, 2013 at 11:26 AM, Kukjin Kim wrote: > Vivek Gautam wrote: >> >> Moving register and structure definitions to header file, >> and keeping the generic functions to be used across >> multiple PHYs in common file "samsung-usbphy.c". >> Also renaming the usb 2.0 phy driver to "samsung-usb2.c" > > Just in my opinion, Samsung-usb2phy is more clear?...In addition, I looked > at using SAMSUNG_USB2PHY as a statement. > Sure will change the file names as suggested samsung-usbphy.c : common PHY controller driver samsung-usb2phy.c : USB 2.0 PHY controller driver Will change the names for CONFIG_XX also accordingly. >> >> Signed-off-by: Vivek Gautam >> --- >> >> Changes from v3: >> - Using separate config SAMSUNG_USB2PHY dependent on >>SAMSUNG_USBPHY for samsung-usb2 type PHY controller. >> >> drivers/usb/phy/Kconfig | 14 +- >> drivers/usb/phy/Makefile |1 + >> drivers/usb/phy/samsung-usb2.c | 511 +++ >> drivers/usb/phy/samsung-usbphy.c | 714 > +- >> drivers/usb/phy/samsung-usbphy.h | 247 + >> 5 files changed, 778 insertions(+), 709 deletions(-) >> create mode 100644 drivers/usb/phy/samsung-usb2.c >> create mode 100644 drivers/usb/phy/samsung-usbphy.h >> >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> index fae4d08..cc0d230 100644 >> --- a/drivers/usb/phy/Kconfig >> +++ b/drivers/usb/phy/Kconfig >> @@ -48,8 +48,18 @@ config USB_RCAR_PHY >> >> config SAMSUNG_USBPHY >> bool "Samsung USB PHY controller Driver" >> - depends on USB_S3C_HSOTG || USB_EHCI_S5P || >> USB_OHCI_EXYNOS > > So this can be selected without any dependency? > The idea was SAMSUNG_USBPHY is selected for usb2 type PHY as well as usb 3 type PHY. But this seems to be bad :-( Better we do something like this ? config SAMSUNG_USB2 bool "Samsung USB 2.0 PHY controller Driver" select SAMSUNG_USBPHY select USB_OTG_UTILS help Enable this to support Samsung USB 2.0 (High Speed) PHY controller driver for Samsung SoCs. config SAMSUNG_USBPHY bool "Samsung USB PHY controller Driver" help Enable this to support Samsung USB phy helper driver for Samsung SoCs. This driver provides common interface for Samsung USB 2.0 PHY driver and later for Samsung USB 3.0 PHY driver. >> select USB_OTG_UTILS >> help >> - Enable this to support Samsung USB phy controller for samsung >> + Enable this to support Samsung USB phy controllers for Samsung >> SoCs. > > Hmm, according to above comments, this should be enabled under Samsung SoC? > May we just add these configs under USB as mentioned above ? >> + >> +if SAMSUNG_USBPHY > > Why is this needed here? > We will not need this if we change to something like mentioned above. >> + >> +config SAMSUNG_USB2PHY >> + bool "Samsung USB 2.0 PHY controller Driver" >> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || >> USB_OHCI_EXYNOS >> + help >> + Enable this to support Samsung USB 2.0 (High Speed) phy controller >> + for Samsung SoCs. >> + >> +endif >> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile >> index ec304f6..7ba9862 100644 >> --- a/drivers/usb/phy/Makefile >> +++ b/drivers/usb/phy/Makefile >> @@ -10,3 +10,4 @@ obj-$(CONFIG_MV_U3D_PHY)+= >> mv_u3d_phy.o >> obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o >> obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o >> obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o >> +obj-$(CONFIG_SAMSUNG_USB2PHY)+= samsung-usb2.o >> diff --git a/drivers/usb/phy/samsung-usb2.c b/drivers/usb/phy/samsung- >> usb2.c >> new file mode 100644 >> index 000..9a9d1d0 >> --- /dev/null >> +++ b/drivers/usb/phy/samsung-usb2.c >> @@ -0,0 +1,511 @@ >> +/* linux/drivers/usb/phy/samsung-usb2.c >> + * >> + * Copyright (c) 2012 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * Author: Praveen Paneri >> + * >> + * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, > EHCI-S5P >> and >> + * OHCI-EXYNOS controllers. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundat
Re: [PATCH v4 2/4] ARM: Exynos5250: Enabling ohci-exynos driver
Hi Kukjin,
On Fri, Feb 1, 2013 at 3:56 AM, Kukjin Kim wrote:
> Tomasz Figa wrote:
>>
>> Hi Vivek,
>
> [...]
>
>> > + usb@1212 {
>> > + compatible = "samsung,exynos4210-ohci";
>> > + reg = <0x1212 0x100>;
>> > + interrupts = <0 71 0>;
>>
>> For Samsung platforms we decided per board enabling of nodes and so this
>> node should also contain:
>>
>> status = "disabled";
>>
>> while in dts file of board using ohci there would be an overriding entry:
>>
>> usb@1212 {
>> status = "okay";
>> };
>>
>> I know that Exynos5250 has not been yet converted into this convention,
>> but using it when adding new devices will simplify the process.
>>
> Well, I have another opinion on this...
>
> Let's see, yeah, we are using following method in EXYNOS4 DT...
> - disabling IPs in SoC DT source and enabling IPs in board DT source
>
> But as I said, in EXYNOS5440 DT, I want to use following, because most of
> them should be enabled/used.
> - enabling IPs in SoC DT source and no need enabling in board DT source.
>
> I mean, it depends on each SoC's situation.
>
So, since USB 2.0 (EHCI/OHCI) shall be always enabled on almost all the boards,
so we shall keep it enabled in SOC DT source.
In that case following patches can be picked for a merge:
[PATCH v5 1/4] ARM: Exynos5250: Enabling ehci-s5p driver
http://www.mail-archive.com/linux-usb@vger.kernel.org/msg12330.html
[PATCH v4 2/4] ARM: Exynos5250: Enabling ohci-exynos driver
http://www.mail-archive.com/linux-usb@vger.kernel.org/msg12266.html
These will enable EHCI and OHCI support on exynos5250.
Please let me know if you want me to resend them. ;-)
--
Thanks & Regards
Vivek
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Re: [PATCH RFC] usb: dwc3: Get PHY from platform specific dwc3 dt node.
On Fri, Feb 1, 2013 at 2:20 PM, Felipe Balbi wrote:
> On Fri, Feb 01, 2013 at 11:54:01AM +0530, Vivek Gautam wrote:
>> Hi Balbi,
>>
>>
>> On Fri, Feb 1, 2013 at 11:52 AM, Vivek Gautam
>> wrote:
>> > Hi Kishon,
>> >
>> >
>> > On Fri, Feb 1, 2013 at 10:51 AM, kishon wrote:
>> >> Hi,
>> >>
>> >>
>> >> On Thursday 31 January 2013 09:08 PM, Felipe Balbi wrote:
>> >>>
>> >>> On Thu, Jan 31, 2013 at 09:00:37PM +0530, Vivek Gautam wrote:
>> >>>>
>> >>>> Hi Felipe,
>> >>>>
>> >>>>
>> >>>> On Thu, Jan 31, 2013 at 8:55 PM, Felipe Balbi wrote:
>> >>>>>
>> >>>>> Hi,
>> >>>>>
>> >>>>> On Thu, Jan 31, 2013 at 08:53:27PM +0530, Vivek Gautam wrote:
>> >>>>>>>>
>> >>>>>>>> Moreover, SoCs having multiple dwc3 controllers will have multiple
>> >>>>>>>> PHYs, which eventually be added using usb_add_phy_dev(), and not
>> >>>>>>>> using usb_add_phy(). So each dwc3 controller won't be able to
>> >>>>>>>> get PHYs by simply calling devm_usb_get_phy() also.
>> >>>>>>>
>> >>>>>>>
>> >>>>>>> No. We have added usb_get_phy_dev() for that purpose in the case of
>> >>>>>>> non-dt.
>> >>>>>>> I think, instead you can have a patch to use devm_usb_get_phy_dev()
>> >>>>>>> here and
>> >>>>>>> in exynos platform specific code use usb_bind_phy() to bind the phy
>> >>>>>>> and
>> >>>>>>> controller till you change it to dt.
>> >>>>>>>
>> >>>>>>
>> >>>>>> We have dt support for dwc3-exynos, in such case we should go ahead
>> >>>>>> with
>> >>>>>> of_platform_populate(), right ?
>> >>>>>> But if when i use of_platform_populate() i will not be able to set
>> >>>>>> dma_mask to dwc3->dev. :-(
>> >>
>> >>
>> >> You can do something like this
>> >>
>> >> static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
>> >>
>> >> static int dwc3_exynos_set_dmamask(struct device *dev, void *c)
>> >> {
>> >> dev->dma_mask = &dwc3_exynos_dma_mask;
>> >>
>> >> return 0;
>> >> }
>> >>
>> >> And in your probe after of_platform_populate, you can add
>> >>
>> >> device_for_each_child(&pdev->dev, NULL, dwc3_exynos_set_dmamask);
>> >>
>> >> Here pdev is the platform device of dwc3-exynos. By this way all the
>> >> children of dwc3-exynos will have dma_mask set to the required value.
>> >>
>> >
>> > Nice idea, thanks :-)
>> > hmm.. so i can patch this now, and get things working ;-)
>> >
>>
>> If this is fine with you shall i go ahead and post a patch for the same ? ;-)
>
> should be fine, but we can wait a bit to see if DeviceTree folks reply,
> your patch will only go on v3.10 anyway.
>
Yeah, sure. No problem at all.
For the time being i will continue to use this change for my other
development work too. :-)
--
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Re: [PATCH RFC] usb: dwc3: Get PHY from platform specific dwc3 dt node.
Hi Balbi,
On Fri, Feb 1, 2013 at 11:52 AM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Fri, Feb 1, 2013 at 10:51 AM, kishon wrote:
>> Hi,
>>
>>
>> On Thursday 31 January 2013 09:08 PM, Felipe Balbi wrote:
>>>
>>> On Thu, Jan 31, 2013 at 09:00:37PM +0530, Vivek Gautam wrote:
>>>>
>>>> Hi Felipe,
>>>>
>>>>
>>>> On Thu, Jan 31, 2013 at 8:55 PM, Felipe Balbi wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>> On Thu, Jan 31, 2013 at 08:53:27PM +0530, Vivek Gautam wrote:
>>>>>>>>
>>>>>>>> Moreover, SoCs having multiple dwc3 controllers will have multiple
>>>>>>>> PHYs, which eventually be added using usb_add_phy_dev(), and not
>>>>>>>> using usb_add_phy(). So each dwc3 controller won't be able to
>>>>>>>> get PHYs by simply calling devm_usb_get_phy() also.
>>>>>>>
>>>>>>>
>>>>>>> No. We have added usb_get_phy_dev() for that purpose in the case of
>>>>>>> non-dt.
>>>>>>> I think, instead you can have a patch to use devm_usb_get_phy_dev()
>>>>>>> here and
>>>>>>> in exynos platform specific code use usb_bind_phy() to bind the phy
>>>>>>> and
>>>>>>> controller till you change it to dt.
>>>>>>>
>>>>>>
>>>>>> We have dt support for dwc3-exynos, in such case we should go ahead
>>>>>> with
>>>>>> of_platform_populate(), right ?
>>>>>> But if when i use of_platform_populate() i will not be able to set
>>>>>> dma_mask to dwc3->dev. :-(
>>
>>
>> You can do something like this
>>
>> static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
>>
>> static int dwc3_exynos_set_dmamask(struct device *dev, void *c)
>> {
>> dev->dma_mask = &dwc3_exynos_dma_mask;
>>
>> return 0;
>> }
>>
>> And in your probe after of_platform_populate, you can add
>>
>> device_for_each_child(&pdev->dev, NULL, dwc3_exynos_set_dmamask);
>>
>> Here pdev is the platform device of dwc3-exynos. By this way all the
>> children of dwc3-exynos will have dma_mask set to the required value.
>>
>
> Nice idea, thanks :-)
> hmm.. so i can patch this now, and get things working ;-)
>
If this is fine with you shall i go ahead and post a patch for the same ? ;-)
>> I'm not sure if there is any other better way to achieve the same (without
>> patching of.c ;-))
>>
>
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Re: [PATCH RFC] usb: dwc3: Get PHY from platform specific dwc3 dt node.
Hi Kishon,
On Fri, Feb 1, 2013 at 10:51 AM, kishon wrote:
> Hi,
>
>
> On Thursday 31 January 2013 09:08 PM, Felipe Balbi wrote:
>>
>> On Thu, Jan 31, 2013 at 09:00:37PM +0530, Vivek Gautam wrote:
>>>
>>> Hi Felipe,
>>>
>>>
>>> On Thu, Jan 31, 2013 at 8:55 PM, Felipe Balbi wrote:
>>>>
>>>> Hi,
>>>>
>>>> On Thu, Jan 31, 2013 at 08:53:27PM +0530, Vivek Gautam wrote:
>>>>>>>
>>>>>>> Moreover, SoCs having multiple dwc3 controllers will have multiple
>>>>>>> PHYs, which eventually be added using usb_add_phy_dev(), and not
>>>>>>> using usb_add_phy(). So each dwc3 controller won't be able to
>>>>>>> get PHYs by simply calling devm_usb_get_phy() also.
>>>>>>
>>>>>>
>>>>>> No. We have added usb_get_phy_dev() for that purpose in the case of
>>>>>> non-dt.
>>>>>> I think, instead you can have a patch to use devm_usb_get_phy_dev()
>>>>>> here and
>>>>>> in exynos platform specific code use usb_bind_phy() to bind the phy
>>>>>> and
>>>>>> controller till you change it to dt.
>>>>>>
>>>>>
>>>>> We have dt support for dwc3-exynos, in such case we should go ahead
>>>>> with
>>>>> of_platform_populate(), right ?
>>>>> But if when i use of_platform_populate() i will not be able to set
>>>>> dma_mask to dwc3->dev. :-(
>
>
> You can do something like this
>
> static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
>
> static int dwc3_exynos_set_dmamask(struct device *dev, void *c)
> {
> dev->dma_mask = &dwc3_exynos_dma_mask;
>
> return 0;
> }
>
> And in your probe after of_platform_populate, you can add
>
> device_for_each_child(&pdev->dev, NULL, dwc3_exynos_set_dmamask);
>
> Here pdev is the platform device of dwc3-exynos. By this way all the
> children of dwc3-exynos will have dma_mask set to the required value.
>
Nice idea, thanks :-)
hmm.. so i can patch this now, and get things working ;-)
> I'm not sure if there is any other better way to achieve the same (without
> patching of.c ;-))
>
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Re: [PATCH v2 1/2] ARM: Exynos5250: Enabling samsung-usbphy driver
Hi Kukjin,
On Wed, Jan 30, 2013 at 10:36 AM, Kukjin Kim wrote:
> Vivek Gautam wrote:
>>
>> Adding usbphy node for Exynos5250 along with the
>> necessary device data to be parsed.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>> arch/arm/boot/dts/exynos5250.dtsi | 15 +++
>> 1 files changed, 15 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index 30485de..610e338 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -275,6 +275,21 @@
>> #size-cells = <0>;
>> };
>>
>> + usbphy@1213 {
>
> Please put above node by order of address.
>
Sure will do that. Actually thought the listing was as per IPs.
>> + compatible = "samsung,exynos5250-usbphy";
>> + reg = <0x1213 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + usbphy-sys {
>> + /* USB device and host PHY_CONTROL registers
> */
>
> Please add the binding documentation instead of comment here.
>
Bindings documentation already added at
"Documentation/devicetree/bindings/usb/samsung-usbphy.txt"
merged in 'usb-next'.
>> + reg = <0x10040704 0x8>,
>> + /* USB2.0 PHY configuration register */
>> + <0x10050230 0x4>;
>> + };
>> + };
>> +
>> amba {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> --
>> 1.7.6.5
>
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Re: [PATCH v2 0/2] ARM: Exynos5250: Enabling samsung usb phy
On Tue, Jan 22, 2013 at 9:01 PM, Vivek Gautam wrote: > Changes from v1: > - Putting separate device nodes for usb 2.0 phy and usb 3.0 phy >based on separate driver for samsung usb 3.0 phy and >samsung usb 2.0 phy: >[PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250 >[PATCH v8 0/4] Adding usb2.0 host-phy support for exynos5250 > - Aligning as per the patch: >usb: phy: samsung: Add support to set pmu isolation > - Replaced phy-handle approach for PHY CONTROL registers >to child nodes. > - Removing AUX data entry from exynos5250 dt file. > > Vivek Gautam (2): > ARM: Exynos5250: Enabling samsung-usbphy driver > ARM: Exynos5250: Enabling samsung-usb3-phy driver > any comments on this patch-series please ? > arch/arm/boot/dts/exynos5250.dtsi | 28 > 1 files changed, 28 insertions(+), 0 deletions(-) > > -- > 1.7.6.5 > -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos
Hi Tomasz,
On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam wrote:
> Hi Tomasz,
>
>
> On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa wrote:
>> Hi Vivek,
>>
>> Don't you need also some clkdev lookup entry to make the clock available
>> in the driver?
>>
>
> This clock source we added with a motive of completion, however it's
> not being used as of now.
> As far as i could see the lookup structure contains clocks for devices
> having multiple instances.
> Do you feel that i should be adding an entry in clk_lookup structure ?
> May be i am missing here something. Can you please elaborate on the
> use-case of clk_lookup
> entries.
>
As indicated above "sclk_usbdrd30" is added with a motive of
completion, however it's
not being used as of now.
And "usbdrd30" is the actual device clock used, where 'drd30' is just
an indicative of
'dual role device and usb 3.0'. So the clock name 'usbdrd30' is the
usb 3.0 clock for drd.
Am i missing something that you wanted to convey here ?
>>
>> On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
>>> Adding necessary device clock to exynos5 needed for
>>> the DWC3 controller.
>>>
>>> Signed-off-by: Vivek Gautam
>>> ---
>>> arch/arm/mach-exynos/clock-exynos5.c | 24
>>> 1 files changed, 24 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>> b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>> @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>> .enable = exynos5_clk_ip_fsys_ctrl ,
>>> .ctrlbit= (1 << 18),
>>> }, {
>>> + .name = "usbdrd30",
>>> + .parent = &exynos5_clk_aclk_200.clk,
>>> + .enable = exynos5_clk_ip_fsys_ctrl,
>>> + .ctrlbit= (1 << 19),
>>> + }, {
>>> .name = "usbotg",
>>> .enable = exynos5_clk_ip_fsys_ctrl,
>>> .ctrlbit= (1 << 7),
>>> @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
>>> = { .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
>>> };
>>>
>>> +struct clk *exynos5_clkset_usbdrd30_list[] = {
>>> + [0] = &exynos5_clk_mout_mpll.clk,
>>> + [1] = &exynos5_clk_mout_cpll.clk,
>>> +};
>>> +
>>> +struct clksrc_sources exynos5_clkset_usbdrd30 = {
>>> + .sources= exynos5_clkset_usbdrd30_list,
>>> + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
>>> +};
>>> +
>>> /* Possible clock sources for aclk_266_gscl_sub Mux */
>>> static struct clk *clk_src_gscl_266_list[] = {
>>> [0] = &clk_ext_xtal_mux,
>>> @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>>> .parent = &exynos5_clk_mout_cpll.clk,
>>> },
>>> .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
>> },
>>> + }, {
>>> + .clk= {
>>> + .name = "sclk_usbdrd30",
>>> + .enable = exynos5_clksrc_mask_fsys_ctrl,
>>> + .ctrlbit= (1 << 28),
>>> + },
>>> + .sources = &exynos5_clkset_usbdrd30,
>>> + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
>> 1 },
>>> + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
>> 4 },
>>> },
>>> };
>
>
--
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Re: [PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
CC: Doug Anderson
On Mon, Jan 28, 2013 at 3:56 PM, Vivek Gautam wrote:
> Adding PHY driver support for USB 3.0 controller for Samsung's
> SoCs.
>
> Signed-off-by: Vivek Gautam
> ---
>
> Changes from v3:
> - Making SAMSUNG_USB3PHY dependent on SAMSUNG_USBPHY.
> - Adding USB_DWC3 to dependencies of SAMSUNG_USB2PHY since
>dwc3 controller also looks for USB2 type PHY.
>
> drivers/usb/phy/Kconfig | 11 +-
> drivers/usb/phy/Makefile |1 +
> drivers/usb/phy/samsung-usb3.c | 349
> ++
> drivers/usb/phy/samsung-usbphy.h | 81 +
> 4 files changed, 441 insertions(+), 1 deletions(-)
> create mode 100644 drivers/usb/phy/samsung-usb3.c
>
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index cc0d230..9325a95 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -52,14 +52,23 @@ config SAMSUNG_USBPHY
> help
> Enable this to support Samsung USB phy controllers for Samsung
> SoCs.
> + Further enable USB 2.0 type PHY or USB 3.0 type PHY as required
> + for USB controllers in use.
>
> if SAMSUNG_USBPHY
>
> config SAMSUNG_USB2PHY
> bool "Samsung USB 2.0 PHY controller Driver"
> - depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS ||
> USB_DWC3
> help
> Enable this to support Samsung USB 2.0 (High Speed) phy controller
> for Samsung SoCs.
>
> +config SAMSUNG_USB3PHY
> + bool "Samsung USB 3.0 PHY controller Driver"
> + depends on USB_DWC3
> + help
> + Enable this to support Samsung USB 3.0 (Super Speed) phy controller
> + for samsung SoCs.
> +
> endif
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index 7ba9862..b8505ac 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
> obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
> obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
> obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2.o
> +obj-$(CONFIG_SAMSUNG_USB3PHY) += samsung-usb3.o
> diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
> new file mode 100644
> index 000..29e1321
> --- /dev/null
> +++ b/drivers/usb/phy/samsung-usb3.c
> @@ -0,0 +1,349 @@
> +/* linux/drivers/usb/phy/samsung-usb3.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * Author: Vivek Gautam
> + *
> + * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "samsung-usbphy.h"
> +
> +/*
> + * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock
> core.
> + */
> +static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
> +{
> + u32 reg;
> + u32 refclk;
> +
> + refclk = sphy->ref_clk_freq;
> +
> + reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
> + PHYCLKRST_FSEL(refclk);
> +
> + switch (refclk) {
> + case FSEL_CLKSEL_50M:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x00));
> + break;
> + case FSEL_CLKSEL_20M:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x00));
> + break;
> + case FSEL_CLKSEL_19200K:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x88));
> + break;
> + case FSEL_CLKSEL_24M:
> + default:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x88));
> + break;
> + }
> +
> + return reg;
> +}
> +
> +static int samsung_exynos5_usb3_phy_enabl
[PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.
Signed-off-by: Vivek Gautam
---
Changes from v3:
- Making SAMSUNG_USB3PHY dependent on SAMSUNG_USBPHY.
- Adding USB_DWC3 to dependencies of SAMSUNG_USB2PHY since
dwc3 controller also looks for USB2 type PHY.
drivers/usb/phy/Kconfig | 11 +-
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb3.c | 349 ++
drivers/usb/phy/samsung-usbphy.h | 81 +
4 files changed, 441 insertions(+), 1 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb3.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index cc0d230..9325a95 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -52,14 +52,23 @@ config SAMSUNG_USBPHY
help
Enable this to support Samsung USB phy controllers for Samsung
SoCs.
+ Further enable USB 2.0 type PHY or USB 3.0 type PHY as required
+ for USB controllers in use.
if SAMSUNG_USBPHY
config SAMSUNG_USB2PHY
bool "Samsung USB 2.0 PHY controller Driver"
- depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+ depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS || USB_DWC3
help
Enable this to support Samsung USB 2.0 (High Speed) phy controller
for Samsung SoCs.
+config SAMSUNG_USB3PHY
+ bool "Samsung USB 3.0 PHY controller Driver"
+ depends on USB_DWC3
+ help
+ Enable this to support Samsung USB 3.0 (Super Speed) phy controller
+ for samsung SoCs.
+
endif
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 7ba9862..b8505ac 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2.o
+obj-$(CONFIG_SAMSUNG_USB3PHY) += samsung-usb3.o
diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
new file mode 100644
index 000..29e1321
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb3.c
@@ -0,0 +1,349 @@
+/* linux/drivers/usb/phy/samsung-usb3.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Vivek Gautam
+ *
+ * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+/*
+ * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock
core.
+ */
+static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
+{
+ u32 reg;
+ u32 refclk;
+
+ refclk = sphy->ref_clk_freq;
+
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case FSEL_CLKSEL_50M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_20M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_19200K:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ case FSEL_CLKSEL_24M:
+ default:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
+static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyparam0;
+ u32 phyparam1;
+ u32 linksystem;
+ u32 phybatchg;
+ u32 phytest;
+ u32 phyclkrst;
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
+
+ phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
+ /* Select PHY CLK source */
+ phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+ /* Set Loss-of-Signal Detector sensitivity */
+ phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+ phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
+ writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
+
+ writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
+
+ /*
+* S
[PATCH v4 1/2] usb: phy: samsung: Common out the generic stuff
Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common file "samsung-usbphy.c".
Also renaming the usb 2.0 phy driver to "samsung-usb2.c"
Signed-off-by: Vivek Gautam
---
Changes from v3:
- Using separate config SAMSUNG_USB2PHY dependent on
SAMSUNG_USBPHY for samsung-usb2 type PHY controller.
drivers/usb/phy/Kconfig | 14 +-
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb2.c | 511 +++
drivers/usb/phy/samsung-usbphy.c | 714 +-
drivers/usb/phy/samsung-usbphy.h | 247 +
5 files changed, 778 insertions(+), 709 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb2.c
create mode 100644 drivers/usb/phy/samsung-usbphy.h
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index fae4d08..cc0d230 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -48,8 +48,18 @@ config USB_RCAR_PHY
config SAMSUNG_USBPHY
bool "Samsung USB PHY controller Driver"
- depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
select USB_OTG_UTILS
help
- Enable this to support Samsung USB phy controller for samsung
+ Enable this to support Samsung USB phy controllers for Samsung
SoCs.
+
+if SAMSUNG_USBPHY
+
+config SAMSUNG_USB2PHY
+ bool "Samsung USB 2.0 PHY controller Driver"
+ depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+ help
+ Enable this to support Samsung USB 2.0 (High Speed) phy controller
+ for Samsung SoCs.
+
+endif
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index ec304f6..7ba9862 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
+obj-$(CONFIG_SAMSUNG_USB2PHY) += samsung-usb2.o
diff --git a/drivers/usb/phy/samsung-usb2.c b/drivers/usb/phy/samsung-usb2.c
new file mode 100644
index 000..9a9d1d0
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb2.c
@@ -0,0 +1,511 @@
+/* linux/drivers/usb/phy/samsung-usb2.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Praveen Paneri
+ *
+ * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
+ * OHCI-EXYNOS controllers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ if (!otg)
+ return -ENODEV;
+
+ if (!otg->host)
+ otg->host = host;
+
+ return 0;
+}
+
+static bool exynos5_phyhost_is_on(void *regs)
+{
+ u32 reg;
+
+ reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ return !(reg & HOST_CTRL0_SIDDQ);
+}
+
+static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyclk = sphy->ref_clk_freq;
+ u32 phyhost;
+ u32 phyotg;
+ u32 phyhsic;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+ atomic_inc(&sphy->phy_usage);
+
+ if (exynos5_phyhost_is_on(regs)) {
+ dev_info(sphy->dev, "Already power on PHY\n");
+ return;
+ }
+
+ /* Host configuration */
+ phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ /* phy reference clock configuration */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= HOST_CTRL0_FSEL(phyclk);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHYSWRST |
+ HOST_CTRL0_PHYSWRSTALL |
+ HOST_CTRL0_SIDDQ |
+ /* Enable normal mode of operation */
+ HOST_CTRL0_FORCESUSPEND |
+ HOST_CTRL0_FORCESLEEP);
+
+ /* Link reset */
+ phyhost |= (HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST |
+
Re: [PATCH v2 0/2] usb: exynos: Fix compatible strings used for device
On Thu, Jan 24, 2013 at 7:15 PM, Vivek Gautam wrote: > Using chip specific compatible string as it should be. > So fixing this for ehci-s5p, ohci-exynos and dwc3-exynos > which till now used a generic 'exynos' in their compatible strings. > > Changes from v1: > - Changing compatible string from "samsung,exynos5250-dwc3" to > "samsung,exynos5250-dwusb3" as per discussion happened in thread: > [PATCH 0/2] usb: exynos: Fix compatible strings used for device. > Based on 'usb-next' branch. > Vivek Gautam (2): > usb: ehci-s5p/ohci-exynos: Fix compatible strings for the device > usb: dwc3-exynos: Fix compatible strings for the device > > drivers/usb/dwc3/dwc3-exynos.c |2 +- > drivers/usb/host/ehci-s5p.c|2 +- > drivers/usb/host/ohci-exynos.c |2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > -- > 1.7.6.5 > -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v2 2/2] usb: dwc3-exynos: Fix compatible strings for the device
Using specific chip in compatible strings. Newer SOCs can claim
device by using older string in the compatible list.
Signed-off-by: Vivek Gautam
Acked-by: Grant Likely
Reviewed-by: Doug Anderson
---
drivers/usb/dwc3/dwc3-exynos.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index aae5328..e2207a6 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -188,7 +188,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id exynos_dwc3_match[] = {
- { .compatible = "samsung,exynos-dwc3" },
+ { .compatible = "samsung,exynos5250-dwusb3" },
{},
};
MODULE_DEVICE_TABLE(of, exynos_dwc3_match);
--
1.7.6.5
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[PATCH v2 1/2] usb: ehci-s5p/ohci-exynos: Fix compatible strings for the device
Using specific chip in compatible strings. Newer SOCs can claim
device by using older string in the compatible list.
Signed-off-by: Vivek Gautam
Acked-by: Grant Likely
Reviewed-by: Doug Anderson
---
drivers/usb/host/ehci-s5p.c|2 +-
drivers/usb/host/ohci-exynos.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 319dcfa..f18e6ac 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -266,7 +266,7 @@ static const struct dev_pm_ops s5p_ehci_pm_ops = {
#ifdef CONFIG_OF
static const struct of_device_id exynos_ehci_match[] = {
- { .compatible = "samsung,exynos-ehci" },
+ { .compatible = "samsung,exynos4210-ehci" },
{},
};
MODULE_DEVICE_TABLE(of, exynos_ehci_match);
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index aa3b884..77f2017 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -267,7 +267,7 @@ static const struct dev_pm_ops exynos_ohci_pm_ops = {
#ifdef CONFIG_OF
static const struct of_device_id exynos_ohci_match[] = {
- { .compatible = "samsung,exynos-ohci" },
+ { .compatible = "samsung,exynos4210-ohci" },
{},
};
MODULE_DEVICE_TABLE(of, exynos_ohci_match);
--
1.7.6.5
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[PATCH v2 0/2] usb: exynos: Fix compatible strings used for device
Using chip specific compatible string as it should be. So fixing this for ehci-s5p, ohci-exynos and dwc3-exynos which till now used a generic 'exynos' in their compatible strings. Changes from v1: - Changing compatible string from "samsung,exynos5250-dwc3" to "samsung,exynos5250-dwusb3" as per discussion happened in thread: [PATCH 0/2] usb: exynos: Fix compatible strings used for device. Vivek Gautam (2): usb: ehci-s5p/ohci-exynos: Fix compatible strings for the device usb: dwc3-exynos: Fix compatible strings for the device drivers/usb/dwc3/dwc3-exynos.c |2 +- drivers/usb/host/ehci-s5p.c|2 +- drivers/usb/host/ohci-exynos.c |2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 0/2] usb: exynos: Fix compatible strings used for device
Hi Sylwester,
On Wed, Jan 23, 2013 at 6:10 PM, Sylwester Nawrocki
wrote:
> Hi,
>
> On 01/23/2013 01:20 PM, Vivek Gautam wrote:
>>>>>> - { .compatible = "samsung,exynos-dwc3" },
>>>>>> + { .compatible = "samsung,synopsis-dwc3" }
>>>>>
>>>>> You're both missing a point here. The synopsys IP driver is called
>>>>> dwc3.ko and that's compatible with synopsys,dwc3. Your glue layer driver
>>>>> (dwc3-exynos.ko) is compatible with your platform, so
>>>>> samsung,exynos-dwc3 sounds correct to me.
>>>>>
>>>> Hmm...yeah, you're right and agreed.
>>>>
>>>> However, we need to use more clear name there like "samsung,exynos-dwusb3"
>>>> in compatible, because you know there are lots of other IPs in Synopsis
>>>> Design Ware brand. So we have to include usb in compatible for that.
>>>
>>> fair enough.
>>>
>>
>> Thanks for your suggestions. This definitely make things clear.
>> I shall then keep "samsung,exynos-dwusb3" as the compatible string or,
>> should i be including '5250' string as well, something like
>> "samsung,exynos5250-dwusb3"
>> as pointed out by Grant earlier ? :-O
>
> IMHO this needs to be "samsung,exynos5250-dwusb3", rather than
> "samsung,exynos-dwusb3". :)
>
Alright, thanks.
I shall update this patch. :)
--
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Vivek
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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos
Hi Tomasz,
On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam wrote:
> Hi Tomasz,
>
>
> On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa wrote:
>> Hi Vivek,
>>
>> Don't you need also some clkdev lookup entry to make the clock available
>> in the driver?
>>
>
> This clock source we added with a motive of completion, however it's
> not being used as of now.
> As far as i could see the lookup structure contains clocks for devices
> having multiple instances.
> Do you feel that i should be adding an entry in clk_lookup structure ?
> May be i am missing here something. Can you please elaborate on the
> use-case of clk_lookup
> entries.
>
Any suggestions on this please ?
>>
>> On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
>>> Adding necessary device clock to exynos5 needed for
>>> the DWC3 controller.
>>>
>>> Signed-off-by: Vivek Gautam
>>> ---
>>> arch/arm/mach-exynos/clock-exynos5.c | 24
>>> 1 files changed, 24 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>> b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>> @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>> .enable = exynos5_clk_ip_fsys_ctrl ,
>>> .ctrlbit= (1 << 18),
>>> }, {
>>> + .name = "usbdrd30",
>>> + .parent = &exynos5_clk_aclk_200.clk,
>>> + .enable = exynos5_clk_ip_fsys_ctrl,
>>> + .ctrlbit= (1 << 19),
>>> + }, {
>>> .name = "usbotg",
>>> .enable = exynos5_clk_ip_fsys_ctrl,
>>> .ctrlbit= (1 << 7),
>>> @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
>>> = { .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
>>> };
>>>
>>> +struct clk *exynos5_clkset_usbdrd30_list[] = {
>>> + [0] = &exynos5_clk_mout_mpll.clk,
>>> + [1] = &exynos5_clk_mout_cpll.clk,
>>> +};
>>> +
>>> +struct clksrc_sources exynos5_clkset_usbdrd30 = {
>>> + .sources= exynos5_clkset_usbdrd30_list,
>>> + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
>>> +};
>>> +
>>> /* Possible clock sources for aclk_266_gscl_sub Mux */
>>> static struct clk *clk_src_gscl_266_list[] = {
>>> [0] = &clk_ext_xtal_mux,
>>> @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>>> .parent = &exynos5_clk_mout_cpll.clk,
>>> },
>>> .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
>> },
>>> + }, {
>>> + .clk= {
>>> + .name = "sclk_usbdrd30",
>>> + .enable = exynos5_clksrc_mask_fsys_ctrl,
>>> + .ctrlbit= (1 << 28),
>>> + },
>>> + .sources = &exynos5_clkset_usbdrd30,
>>> + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
>> 1 },
>>> + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
>> 4 },
>>> },
>>> };
>
>
--
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Re: [PATCH 0/2] usb: exynos: Fix compatible strings used for device
Hi all,
On Wed, Jan 23, 2013 at 3:20 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Jan 22, 2013 at 02:04:56PM -0800, Kukjin Kim wrote:
>> Felipe Balbi wrote:
>> > Hi,
>> >
>> Hi Felipe,
>>
>> [...]
>>
>> > > Right, DWC has version number, but that being the kind of USB controller
>> > > (USB 2.0 and USB 3.0)
>> > >
>> > > DWC2: USB High Speed controller (as also indicated in the patch from
>> > > Paul: [RFC PATCH 0/6] DWC2 DesignWare HS OTG driver)
>> > > DWC3: USB Super Speed controller
>> > >
>> > > Is it fine if we use something like shown below, as suggested by you
>> earlier ?
>> > >
>> > > - { .compatible = "samsung,exynos-dwc3" },
>> > > + { .compatible = "samsung,synopsis-dwc3" }
>> >
>> > You're both missing a point here. The synopsys IP driver is called
>> > dwc3.ko and that's compatible with synopsys,dwc3. Your glue layer driver
>> > (dwc3-exynos.ko) is compatible with your platform, so
>> > samsung,exynos-dwc3 sounds correct to me.
>> >
>> Hmm...yeah, you're right and agreed.
>>
>> However, we need to use more clear name there like "samsung,exynos-dwusb3"
>> in compatible, because you know there are lots of other IPs in Synopsis
>> Design Ware brand. So we have to include usb in compatible for that.
>
> fair enough.
>
Thanks for your suggestions. This definitely make things clear.
I shall then keep "samsung,exynos-dwusb3" as the compatible string or,
should i be including '5250' string as well, something like
"samsung,exynos5250-dwusb3"
as pointed out by Grant earlier ? :-O
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[PATCH v2 2/2] ARM: Exynos5250: Enabling samsung-usb3-phy driver
Adding usb3.0 phy node for Exynos5250 along with the
necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 610e338..018a70d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -275,6 +275,19 @@
#size-cells = <0>;
};
+ usbphy@1210 {
+ compatible = "samsung,exynos5250-usb3-phy";
+ reg = <0x1210 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = <0x10040704 0x8>;
+ };
+ };
+
usbphy@1213 {
compatible = "samsung,exynos5250-usbphy";
reg = <0x1213 0x100>;
--
1.7.6.5
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[PATCH v2 1/2] ARM: Exynos5250: Enabling samsung-usbphy driver
Adding usbphy node for Exynos5250 along with the
necessary device data to be parsed.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..610e338 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -275,6 +275,21 @@
#size-cells = <0>;
};
+ usbphy@1213 {
+ compatible = "samsung,exynos5250-usbphy";
+ reg = <0x1213 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = <0x10040704 0x8>,
+ /* USB2.0 PHY configuration register */
+ <0x10050230 0x4>;
+ };
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.7.6.5
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[PATCH v2 0/2] ARM: Exynos5250: Enabling samsung usb phy
Changes from v1: - Putting separate device nodes for usb 2.0 phy and usb 3.0 phy based on separate driver for samsung usb 3.0 phy and samsung usb 2.0 phy: [PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250 [PATCH v8 0/4] Adding usb2.0 host-phy support for exynos5250 - Aligning as per the patch: usb: phy: samsung: Add support to set pmu isolation - Replaced phy-handle approach for PHY CONTROL registers to child nodes. - Removing AUX data entry from exynos5250 dt file. Vivek Gautam (2): ARM: Exynos5250: Enabling samsung-usbphy driver ARM: Exynos5250: Enabling samsung-usb3-phy driver arch/arm/boot/dts/exynos5250.dtsi | 28 1 files changed, 28 insertions(+), 0 deletions(-) -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v8 4/4] USB: ohci-exynos: Add phy driver support
Adding the phy-driver to ohci-exynos. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Alan Stern
Acked-by: Kukjin Kim
---
drivers/usb/host/ohci-exynos.c | 84 ++--
1 files changed, 63 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 804fb62..1b38409 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
@@ -22,8 +23,31 @@ struct exynos_ohci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct usb_otg *otg;
+ struct exynos4_ohci_platdata *pdata;
};
+static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+ if (exynos_ohci->phy)
+ usb_phy_init(exynos_ohci->phy);
+ else if (exynos_ohci->pdata->phy_init)
+ exynos_ohci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+}
+
+static void exynos_ohci_phy_disable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+ if (exynos_ohci->phy)
+ usb_phy_shutdown(exynos_ohci->phy);
+ else if (exynos_ohci->pdata->phy_exit)
+ exynos_ohci->pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+}
+
static int ohci_exynos_reset(struct usb_hcd *hcd)
{
return ohci_init(hcd_to_ohci(hcd));
@@ -79,20 +103,15 @@ static u64 ohci_exynos_dma_mask = DMA_BIT_MASK(32);
static int exynos_ohci_probe(struct platform_device *pdev)
{
- struct exynos4_ohci_platdata *pdata;
+ struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci;
struct usb_hcd *hcd;
struct ohci_hcd *ohci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "No platform data defined\n");
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -108,6 +127,20 @@ static int exynos_ohci_probe(struct platform_device *pdev)
if (!exynos_ohci)
return -ENOMEM;
+ phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ /* Fallback to pdata */
+ if (!pdata) {
+ dev_warn(&pdev->dev, "no platform data or transceiver
defined\n");
+ return -EPROBE_DEFER;
+ } else {
+ exynos_ohci->pdata = pdata;
+ }
+ } else {
+ exynos_ohci->phy = phy;
+ exynos_ohci->otg = phy->otg;
+ }
+
exynos_ohci->dev = &pdev->dev;
hcd = usb_create_hcd(&exynos_ohci_hc_driver, &pdev->dev,
@@ -153,8 +186,11 @@ static int exynos_ohci_probe(struct platform_device *pdev)
goto fail_io;
}
- if (pdata->phy_init)
- pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+ if (exynos_ohci->otg)
+ exynos_ohci->otg->set_host(exynos_ohci->otg,
+ &exynos_ohci->hcd->self);
+
+ exynos_ohci_phy_enable(exynos_ohci);
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
@@ -162,13 +198,15 @@ static int exynos_ohci_probe(struct platform_device *pdev)
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err) {
dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_io;
+ goto fail_add_hcd;
}
platform_set_drvdata(pdev, exynos_ohci);
return 0;
+fail_add_hcd:
+ exynos_ohci_phy_disable(exynos_ohci);
fail_io:
clk_disable_unprepare(exynos_ohci->clk);
fail_clk:
@@ -178,14 +216,16 @@ fail_clk:
static int exynos_ohci_remove(struct platform_device *pdev)
{
- struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = exynos_ohci->hcd;
usb_remove_hcd(hcd);
- if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+ if (exynos_ohci->otg)
+ exynos_ohci->otg->set_host(exynos_ohci->otg,
+ &exynos_ohci->hcd->self)
[PATCH v8 3/4] USB: ehci-s5p: Add phy driver support
Adding the phy driver to ehci-s5p. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Alan Stern
Acked-by: Kukjin Kim
---
drivers/usb/host/ehci-s5p.c | 80 +++---
1 files changed, 59 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 46ca5ef..d603e6e 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
@@ -33,6 +34,9 @@ struct s5p_ehci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct usb_otg *otg;
+ struct s5p_ehci_platdata *pdata;
};
static const struct hc_driver s5p_ehci_hc_driver = {
@@ -66,6 +70,26 @@ static const struct hc_driver s5p_ehci_hc_driver = {
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
};
+static void s5p_ehci_phy_enable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+ if (s5p_ehci->phy)
+ usb_phy_init(s5p_ehci->phy);
+ else if (s5p_ehci->pdata->phy_init)
+ s5p_ehci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+}
+
+static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+ if (s5p_ehci->phy)
+ usb_phy_shutdown(s5p_ehci->phy);
+ else if (s5p_ehci->pdata->phy_exit)
+ s5p_ehci->pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+}
+
static void s5p_setup_vbus_gpio(struct platform_device *pdev)
{
int err;
@@ -88,20 +112,15 @@ static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
static int s5p_ehci_probe(struct platform_device *pdev)
{
- struct s5p_ehci_platdata *pdata;
+ struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci;
struct usb_hcd *hcd;
struct ehci_hcd *ehci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "No platform data defined\n");
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -119,6 +138,20 @@ static int s5p_ehci_probe(struct platform_device *pdev)
if (!s5p_ehci)
return -ENOMEM;
+ phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ /* Fallback to pdata */
+ if (!pdata) {
+ dev_warn(&pdev->dev, "no platform data or transceiver
defined\n");
+ return -EPROBE_DEFER;
+ } else {
+ s5p_ehci->pdata = pdata;
+ }
+ } else {
+ s5p_ehci->phy = phy;
+ s5p_ehci->otg = phy->otg;
+ }
+
s5p_ehci->dev = &pdev->dev;
hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev,
@@ -164,8 +197,10 @@ static int s5p_ehci_probe(struct platform_device *pdev)
goto fail_io;
}
- if (pdata->phy_init)
- pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+ if (s5p_ehci->otg)
+ s5p_ehci->otg->set_host(s5p_ehci->otg, &s5p_ehci->hcd->self);
+
+ s5p_ehci_phy_enable(s5p_ehci);
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -176,13 +211,15 @@ static int s5p_ehci_probe(struct platform_device *pdev)
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err) {
dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_io;
+ goto fail_add_hcd;
}
platform_set_drvdata(pdev, s5p_ehci);
return 0;
+fail_add_hcd:
+ s5p_ehci_phy_disable(s5p_ehci);
fail_io:
clk_disable_unprepare(s5p_ehci->clk);
fail_clk:
@@ -192,14 +229,15 @@ fail_clk:
static int s5p_ehci_remove(struct platform_device *pdev)
{
- struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
usb_remove_hcd(hcd);
- if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+ if (s5p_ehci->otg)
+ s5p_ehci->otg->set_host(s5p_ehci->otg, &s5p_ehci->hcd->self);
+
+ s5p_ehci_phy_disable(s5p_ehci);
clk_disable_unpr
[PATCH v8 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy driver and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri Signed-off-by: Vivek Gautam Acked-by: Kukjin Kim --- .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 513 ++-- 3 files changed, 496 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index 22d06cf..0331949 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,15 +1,23 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be "samsung,exynos4210-usbphy" - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be "samsung,exynos5250-usbphy" +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - #address-cells: should be '1' when usbphy node has a child node with 'reg' property. diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 36a85b6..fae4d08 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -48,7 +48,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool "Samsung USB PHY controller Driver" - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 30aebb5..9e9861c 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,11 +22,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include /* Register definitions */ @@ -57,24 +60,132 @@ #define RSTCON_HLINK_SWRST (0x1 << 1) #define RSTCON_SWRST (0x1 << 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) +#define HOST_CTRL0_FSEL(_x)((_x) << 16) + +#define FSEL_CLKSEL_50M(0x7) +#define FSEL_CLKSEL_24M(0x5) +#define FSEL_CLKSEL_20M(0x4) +#define FSEL_CLKSEL_19200K (0x3) +#define FSEL_CLKSEL_12M(0x2) +#define FSEL_CLKSEL_10M(0x1) +#define FSEL_CLKSEL_9600K (0x0) + +#define HOST_CTRL0_TESTBURNIN (0x1 << 11) +#define HOST_CTRL0_RETENABLE (0x1 << 10) +#define HOST_CTRL0_COMMONON_N (0x1 << 9) +#define HOST_CTRL0_SIDDQ (0x1 << 6) +#define HOST_CTRL0_FORCESLEEP (0x1 << 5) +#define HOST_CTRL0_FORCESUSPEND(0x1 << 4) +#define HOST_CTRL0_WORDINTERFACE (0x1 << 3) +#define HOST_CTRL0_UTMISWRST (0x1 << 2) +#define HOST_CTRL0_LINKSWRST (0x1 << 1) +#define HOST_CTRL0_PHYSWRST(0x1 << 0) + +#define EXYNOS5_PHY_HOST_TUNE0 (0x04) + +#define EXYNOS5_PHY_HSIC_CTRL1 (0x10) + +#define EXYNOS5_PHY_HSIC_TUNE1 (0x14) + +#define EXYNOS5_PHY_HSIC_CTRL2 (0x20) + +#define EXYNOS5_PHY_HSIC_TUNE2
[PATCH v8 1/4] ARM: EXYNOS: Update & move usb-phy types to generic include layer
Updating the names of usb-phy types to more generic names:
USB_PHY_TYPE_DEIVCE & USB_PHY_TYPE_HOST; and further update
its dependencies.
Signed-off-by: Praveen Paneri
Signed-off-by: Vivek Gautam
Acked-by: Kukjin Kim
---
drivers/usb/host/ehci-s5p.c |9 +
drivers/usb/host/ohci-exynos.c |9 +
include/linux/usb/samsung_usb_phy.h | 16
3 files changed, 26 insertions(+), 8 deletions(-)
create mode 100644 include/linux/usb/samsung_usb_phy.h
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 319dcfa..46ca5ef 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#define EHCI_INSNREG00(base) (base + 0x90)
@@ -164,7 +165,7 @@ static int s5p_ehci_probe(struct platform_device *pdev)
}
if (pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -198,7 +199,7 @@ static int s5p_ehci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(s5p_ehci->clk);
@@ -229,7 +230,7 @@ static int s5p_ehci_suspend(struct device *dev)
rc = ehci_suspend(hcd, do_wakeup);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(s5p_ehci->clk);
@@ -246,7 +247,7 @@ static int s5p_ehci_resume(struct device *dev)
clk_prepare_enable(s5p_ehci->clk);
if (pdata && pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
/* DMA burst Enable */
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index aa3b884..804fb62 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
struct exynos_ohci_hcd {
@@ -153,7 +154,7 @@ static int exynos_ohci_probe(struct platform_device *pdev)
}
if (pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
@@ -184,7 +185,7 @@ static int exynos_ohci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(exynos_ohci->clk);
@@ -229,7 +230,7 @@ static int exynos_ohci_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(exynos_ohci->clk);
@@ -249,7 +250,7 @@ static int exynos_ohci_resume(struct device *dev)
clk_prepare_enable(exynos_ohci->clk);
if (pdata && pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ohci_resume(hcd, false);
diff --git a/include/linux/usb/samsung_usb_phy.h
b/include/linux/usb/samsung_usb_phy.h
new file mode 100644
index 000..9167826
--- /dev/null
+++ b/include/linux/usb/samsung_usb_phy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * http://www.samsung.com/
+ *
+ * Defines phy types for samsung usb phy controllers - HOST or DEIVCE.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+enum samsung_usb_phy_type {
+ USB_PHY_TYPE_DEVICE,
+ USB_PHY_TYPE_HOST,
+};
--
1.7.6.5
___
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devicetree-discuss@lists.ozlabs.org
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[PATCH v8 0/4] Adding usb2.0 host-phy support for exynos5250
Changes from v7: - Rebased on 'xceive' of Balbi's usb tree. - Placing proper Acked By's received for each patch. Changes from v6: - Changing macro names from 'HOST_CTRL0_FSEL_CLKSEL_XX' to 'FSEL_CLKSEL_XX' since it's being used by HOST and OTG block to prepare reference clock. - Directly Assigning 'FSEL_CLKSEL_XX' to refclk_freq in samsung_usbphy_get_refclk_freq() instead of ORing them since we are anyways using macros: "HOST_CTRL0_FSEL(_x)((_x) << 16)" "OTG_SYS_FSEL(_x) ((_x) << 4)" Changes from v5: - Adding hostphy enable mask and hostphy register offsets to driver data in order to access the HOSTPHY CONTROL register. - Adding member 'otg' to struct samsung-usbphy so that its consumers can call otg->set_host so as to make 'phy' aware of the consumer type: HOST/DEVICE - Adding 'otg' to 'struct s5p_ehci_hcd' and 'struct exynos_ohci_hcd' which keeps track of 'otg' of the controllers' phy. This then sets the host. - Moved samsung_usbphy_set_type() calls from ehci-s5p and ohci-exynos to phy driver itself where based on phy_type it is called. - Added separate macro definition for USB20PHY_CFG register to select between host/device type usb link. - Removing unnecessary argument 'phy_type' from samsung_usbphy_set_type() and samsung_usbphy_cfg_sel(). - Addressed few nits: -- added macro for 'KHZ' -- removing useless 'if' from samsung_usbphy_cfg_sel() -- keeping the place of clk_get intact and requesting driver data before that. Vivek Gautam (4): ARM: EXYNOS: Update & move usb-phy types to generic include layer usb: phy: samsung: Add host phy support to samsung-phy driver USB: ehci-s5p: Add phy driver support USB: ohci-exynos: Add phy driver support .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- drivers/usb/host/ehci-s5p.c| 81 +++- drivers/usb/host/ohci-exynos.c | 85 +++- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 513 ++-- include/linux/usb/samsung_usb_phy.h| 16 + 6 files changed, 636 insertions(+), 73 deletions(-) create mode 100644 include/linux/usb/samsung_usb_phy.h -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 0/4] Adding usb2.0 host-phy support for exynos5250
Hi Felipe, On Tue, Jan 22, 2013 at 3:02 PM, Felipe Balbi wrote: > HI, > > On Tue, Jan 22, 2013 at 11:29:47AM +0200, Felipe Balbi wrote: >> On Tue, Jan 22, 2013 at 02:45:26PM +0530, Vivek Gautam wrote: >> > Hi Felipe, >> > >> > >> > On Tue, Jan 22, 2013 at 2:20 PM, Felipe Balbi wrote: >> > > HI, >> > > >> > > On Mon, Jan 21, 2013 at 09:23:28PM -0800, Kukjin Kim wrote: >> > >> Vivek Gautam wrote: >> > >> > >> > >> > Changes from v5: >> > >> > - Rebased on top of latest patches: >> > >> > usb: phy: samsung: Introducing usb phy driver for hsotg (v9) >> > >> > usb: phy: samsung: Add support to set pmu isolation (v6) >> > >> >As a result adding hostphy enable mask and hostphy register offsets >> > >> >to driver data in order to access the HOSTPHY CONTROL register. >> > >> > >> > >> > - Adding member 'otg' to struct samsung-usbphy so that its consumers >> > >> >can call otg->set_host so as to make 'phy' aware of the consumer >> > >> > type: >> > >> > HOST/DEVICE >> > >> > >> > >> > - Adding 'otg' to 'struct s5p_ehci_hcd' and 'struct exynos_ohci_hcd' >> > >> >which keeps track of 'otg' of the controllers' phy. This then sets >> > >> >the host. >> > >> > >> > >> > - Moved samsung_usbphy_set_type() calls from ehci-s5p and ohci-exynos >> > >> >to phy driver itself where based on phy_type it is called. >> > >> > >> > >> > - Added separate macro definition for USB20PHY_CFG register to select >> > >> >between host/device type usb link. >> > >> > >> > >> > - Removing unnecessary argument 'phy_type' from >> > >> > samsung_usbphy_set_type() >> > >> >and samsung_usbphy_cfg_sel(). >> > >> > >> > >> > - Addressed few nits: >> > >> > -- added macro for 'KHZ' >> > >> > -- removing useless 'if' from samsung_usbphy_cfg_sel() >> > >> > -- keeping the place of clk_get intact and requesting driver >> > >> >data before that. >> > >> > >> > >> > Vivek Gautam (4): >> > >> > ARM: EXYNOS: Update & move usb-phy types to generic include layer >> > >> > usb: phy: samsung: Add host phy support to samsung-phy driver >> > >> > USB: ehci-s5p: Add phy driver support >> > >> > USB: ohci-exynos: Add phy driver support >> > >> > >> > >> > .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- >> > >> > drivers/usb/host/ehci-s5p.c| 81 +++- >> > >> > drivers/usb/host/ohci-exynos.c | 85 +++- >> > >> > drivers/usb/phy/Kconfig|2 +- >> > >> > drivers/usb/phy/samsung-usbphy.c | 512 >> > >> ++-- >> > >> > include/linux/usb/samsung_usb_phy.h| 16 + >> > >> > 6 files changed, 635 insertions(+), 73 deletions(-) >> > >> > create mode 100644 include/linux/usb/samsung_usb_phy.h >> > >> > >> > >> > -- >> > >> > 1.7.6.5 >> > >> >> > >> Looks good to me, >> > >> >> > >> Felipe and Greg, I don't know who should take this series anyway, feel >> > >> free >> > >> to add my ack: >> > >> >> > >> Acked-by: Kukjin Kim >> > > >> > > I will take care of it. But I need Alan's Acked-by for EHCI and OHCI >> > > parts. >> > > >> > >> > We got Alan's ACK for: >> > USB: ehci-s5p: Add phy driver support >> > USB: ohci-exynos: Add phy driver support >> >> Ok, then as soon as I get back to the office (in a few hours), I'll >> start queueing those. > > Actually, if you want to make my life a little easier today, you could > resend the series with all Acks in place ;-) > Sure, will resend the patches with proper Acks and version :-) > ps: hehe, I'm about to go a little nuts today, too many things happening > at once ;-) > :-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 0/4] Adding usb2.0 host-phy support for exynos5250
Hi Felipe, On Tue, Jan 22, 2013 at 2:20 PM, Felipe Balbi wrote: > HI, > > On Mon, Jan 21, 2013 at 09:23:28PM -0800, Kukjin Kim wrote: >> Vivek Gautam wrote: >> > >> > Changes from v5: >> > - Rebased on top of latest patches: >> > usb: phy: samsung: Introducing usb phy driver for hsotg (v9) >> > usb: phy: samsung: Add support to set pmu isolation (v6) >> >As a result adding hostphy enable mask and hostphy register offsets >> >to driver data in order to access the HOSTPHY CONTROL register. >> > >> > - Adding member 'otg' to struct samsung-usbphy so that its consumers >> >can call otg->set_host so as to make 'phy' aware of the consumer type: >> > HOST/DEVICE >> > >> > - Adding 'otg' to 'struct s5p_ehci_hcd' and 'struct exynos_ohci_hcd' >> >which keeps track of 'otg' of the controllers' phy. This then sets >> >the host. >> > >> > - Moved samsung_usbphy_set_type() calls from ehci-s5p and ohci-exynos >> >to phy driver itself where based on phy_type it is called. >> > >> > - Added separate macro definition for USB20PHY_CFG register to select >> >between host/device type usb link. >> > >> > - Removing unnecessary argument 'phy_type' from >> > samsung_usbphy_set_type() >> >and samsung_usbphy_cfg_sel(). >> > >> > - Addressed few nits: >> > -- added macro for 'KHZ' >> > -- removing useless 'if' from samsung_usbphy_cfg_sel() >> > -- keeping the place of clk_get intact and requesting driver >> >data before that. >> > >> > Vivek Gautam (4): >> > ARM: EXYNOS: Update & move usb-phy types to generic include layer >> > usb: phy: samsung: Add host phy support to samsung-phy driver >> > USB: ehci-s5p: Add phy driver support >> > USB: ohci-exynos: Add phy driver support >> > >> > .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- >> > drivers/usb/host/ehci-s5p.c| 81 +++- >> > drivers/usb/host/ohci-exynos.c | 85 +++- >> > drivers/usb/phy/Kconfig|2 +- >> > drivers/usb/phy/samsung-usbphy.c | 512 >> ++-- >> > include/linux/usb/samsung_usb_phy.h| 16 + >> > 6 files changed, 635 insertions(+), 73 deletions(-) >> > create mode 100644 include/linux/usb/samsung_usb_phy.h >> > >> > -- >> > 1.7.6.5 >> >> Looks good to me, >> >> Felipe and Greg, I don't know who should take this series anyway, feel free >> to add my ack: >> >> Acked-by: Kukjin Kim > > I will take care of it. But I need Alan's Acked-by for EHCI and OHCI > parts. > We got Alan's ACK for: USB: ehci-s5p: Add phy driver support USB: ohci-exynos: Add phy driver support -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 0/2] ARM: Exynos5250: Enabling samsung usb phy
Hi Kukjin, On Tue, Jan 22, 2013 at 10:36 AM, Kukjin Kim wrote: > Felipe Balbi wrote: >> >> On Fri, Jan 18, 2013 at 03:10:13PM +0200, Felipe Balbi wrote: >> > Hi, >> > >> > On Tue, Dec 18, 2012 at 09:09:40PM +0530, Vivek Gautam wrote: >> > > This patch-set enables the samsung-usbphy driver on exynos5250, >> > > which enables the support for USB2 type and USB3 type phys. >> > > The corresponding phy driver patches are available at: >> > > 1) https://lkml.org/lkml/2012/12/18/201 >> > > 2) https://lists.ozlabs.org/pipermail/devicetree-discuss/2012- >> December/024559.html >> > > >> > > Tested this patch-set on exynos5250 with following patch-sets for >> > > USB 2.0 and USB 3.0: >> > > - https://patchwork.kernel.org/patch/1794651/ >> > > - https://lkml.org/lkml/2012/12/18/201 >> > > - https://lists.ozlabs.org/pipermail/devicetree-discuss/2012- >> December/024559.html >> > > - http://comments.gmane.org/gmane.linux.usb.general/76352 >> > > - https://lkml.org/lkml/2012/12/13/492 >> > > >> > > Vivek Gautam (2): >> > > ARM: Exynos5250: Enabling samsung-usbphy driver >> > > ARM: Exynos5250: Enabling USB 3.0 phy for samsung-usbphy driver >> > >> > What should I do with this series ? Is it ready to apply ? If it is, >> > then please resend with Kukjim's Acked-by. >> >> actually, now that I look again, it's all under arch/arm/, so Kukjim can >> take all of those through his tree ;-) >> > Yes, once Vivek addresses comments from Sylwester, let me pick up into > Samsung tree :-) > Sure, i shall update this patch-series based on separate drivers for USB 3.0 PHY controller as posted in following patch series : [PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250 -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 0/2] usb: exynos: Fix compatible strings used for device
Hi Kukjin,
On Tue, Jan 22, 2013 at 11:05 AM, Kukjin Kim wrote:
> Sylwester Nawrocki wrote:
>>
>> On 12/24/2012 09:13 AM, Vivek Gautam wrote:
>> >>>> These two changes look good to me. For both of them:
>> >>>>
>> >>>> Reviewed-by: Doug Anderson
>> >>>
>> >>> Well, I have another idea. Yes, I know, specific chip name should be
> used.
>> >> But
>> >>> you know the specific chip name in compatible can cause another
>> confusion
>> >>> on other SoC which has same IP. So I think, we need to consider to use
>> >>> common name or any specific name not chip in compatible for IP/driver
>> like
>> >>> following?
>> >>>
>> >>> - { .compatible = "samsung,exynos-dwc3" },
>> >>> + { .compatible = "samsung,synopsis-dwc3" },
>> >>>
>> >>> Or if any version or something, how about following?
>> >>>
>> >>> + { .compatible = "samsung,dwc-v3" },
>> >>>
>> > Well, yes the newer SoCs with same IP using the chip name can cause some
>> > confusion, but won't it be fine that -
>> > "Newer parts using the same core can claim compatibility by
>> > including the older string in the compatible list" - as quoted by Grant
> Likely
>> >
>> > Or, can we try another option, using multiple compatible strings for
>> > SoC specific
>> > in of_match_table, so that we don't create any confusion by using same
>> > compatible for newer SoCs also. Like,
>> >
>> > - { .compatible = "samsung,exynos-dwc3" },
>> > + { .compatible = "samsung,exynos5250-dwc3" },
>> > + { .compatible = },
>>
>> Yes, why not just use an SoC name where given IP first appeared ? I
> believe
>> IP revision numbers are not always well documented. Also when an IP is
>> instantiated multiple times in specific SoC, its revision number might not
>> be sufficient to determine the system integration details for each
> instance.
>> I think having version for some devices and SoC name for others just adds
>> to the confusion. Thus using specific chip name in the compatible property
>> seems more clear to me.
>>
> Well, I don't think so. Let's see the DMAC PL330. Its compatible is
> "arm,pl330" and "arm,primecell" not SoC/Chip name. I think DWC is a same
> case or at least similar.
>
> You know, the DWC is a IP from Synopsis and I _Believe_ it has a kind of
> version and it can be used for identify.
>
Right, DWC has version number, but that being the kind of USB controller
(USB 2.0 and USB 3.0)
DWC2: USB High Speed controller (as also indicated in the patch from
Paul: [RFC PATCH 0/6] DWC2 DesignWare HS OTG driver)
DWC3: USB Super Speed controller
Is it fine if we use something like shown below, as suggested by you earlier ?
- { .compatible = "samsung,exynos-dwc3" },
+ { .compatible = "samsung,synopsis-dwc3" }
--
Thanks & Regards
Vivek
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Re: [PATCH v7 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Kukjin, On Fri, Jan 18, 2013 at 8:37 PM, Felipe Balbi wrote: > On Fri, Jan 18, 2013 at 07:59:52PM +0530, Vivek Gautam wrote: >> HI Balbi, >> >> >> On Fri, Jan 18, 2013 at 7:52 PM, Felipe Balbi wrote: >> > On Fri, Jan 18, 2013 at 07:51:08PM +0530, Vivek Gautam wrote: >> >> Hi Felipe, >> >> >> >> >> >> On Fri, Jan 18, 2013 at 6:46 PM, Felipe Balbi wrote: >> >> > Hi, >> >> > >> >> > On Mon, Jan 14, 2013 at 05:52:15PM +0530, Vivek Gautam wrote: >> >> >> This patch adds host phy support to samsung-usbphy driver and >> >> >> further adds support for samsung's exynos5250 usb-phy. >> >> >> >> >> >> Signed-off-by: Praveen Paneri >> >> >> Signed-off-by: Vivek Gautam >> >> > >> >> > Missing Kukjim's Acked-by here >> >> > >> >> >> >> Hope you are fine with the changes happened after discussion in thread: >> >> [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy >> >> driver >> >> >> >> Is it something you want me to modify in this patch ? >> > >> > please send the final patch and we shall see. After quickly browsing >> > that thread, I didn't see anything scary, but I'd like to see your final >> > version before giving my final answer ;-) >> > >> >> this series of patch is the final version from my side unless Doug or >> you have any further comments >> on the thread : >> https://lkml.org/lkml/2013/1/14/481 >> >> Seems like Doug wanted to know your opinion in this regard. ;-) > > only Kukjim's Acked-by missing ;-) > Any comments on this patch-series please ? -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Hi Felipe, On Mon, Jan 14, 2013 at 6:29 PM, Vivek Gautam wrote: > Changes from v2: > - Renaming 'samsung-usbphy.c' driver to 'samsung-usb2.c' indicating >usb 2.0 phy controller's driver for Samsung's SoCs. > - Moving the register definitions and strcuture definitions to >common header file 'samsung-usbphy.h' to be used across >usb 2.0 and usb 3.0 phy. > - Keeping common exported function definitions in samsung-usbphy.c >which can be used across usb 2.0 and usb 3.0 phy. > - Writting separate driver file for Samsung's USB 3.0 phy controller. >and making it dependent on USB_DWC3. > Is the re-organization being done here fine as per requirements for separate drivers for usb 2.0 type PHY and usb 3.0 type PHY ? > Rebased on top of usb-next followed by following patches/patch-threads: > -- [PATCH v9 1/2] usb: phy: samsung: Introducing usb phy driver for > hsotg > -- [PATCH] usb: phy: samsung: Add support to set pmu isolation > (version 6) > -- [PATCH v6 0/4] Adding usb2.0 host-phy support for exynos5250 > > Changes form v1: > - Moved architecture related patch out of this patch-set. > - Replaced unnecessary multi-line macro definitions by >single line definitions. > - Creating new data structure for USB 3.0 phy type and embedding >it in 'samsung_usbphy' structure. > - Adding a flag in 'samsung_usbphy' structure to check if device >has usb 3.0 type phy or not. > - Restructuring probe sequence for USB 3.0 phy, such that we are >initializing only when device has usb3.0 type phy. > > Vivek Gautam (2): > usb: phy: samsung: Common out the generic stuff > usb: phy: samsung: Add PHY support for USB 3.0 controller > > drivers/usb/phy/Kconfig |8 + > drivers/usb/phy/Makefile |3 +- > drivers/usb/phy/samsung-usb2.c | 511 +++ > drivers/usb/phy/samsung-usb3.c | 349 +++ > drivers/usb/phy/samsung-usbphy.c | 713 > +- > drivers/usb/phy/samsung-usbphy.h | 328 + > 6 files changed, 1205 insertions(+), 707 deletions(-) > create mode 100644 drivers/usb/phy/samsung-usb2.c > create mode 100644 drivers/usb/phy/samsung-usb3.c > create mode 100644 drivers/usb/phy/samsung-usbphy.h > -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 3/4] USB: ehci-s5p: Add phy driver support
Hi Alan, On Fri, Jan 18, 2013 at 6:46 PM, Felipe Balbi wrote: > On Fri, Jan 11, 2013 at 08:32:29PM +0530, Vivek Gautam wrote: >> Adding the phy driver to ehci-s5p. Keeping the platform data >> for continuing the smooth operation for boards which still uses it >> >> Signed-off-by: Vivek Gautam >> Acked-by: Jingoo Han > > Missing Alan's Acked-by here. > Any comments on this patch-series ? -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v7 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
HI Balbi, On Fri, Jan 18, 2013 at 7:52 PM, Felipe Balbi wrote: > On Fri, Jan 18, 2013 at 07:51:08PM +0530, Vivek Gautam wrote: >> Hi Felipe, >> >> >> On Fri, Jan 18, 2013 at 6:46 PM, Felipe Balbi wrote: >> > Hi, >> > >> > On Mon, Jan 14, 2013 at 05:52:15PM +0530, Vivek Gautam wrote: >> >> This patch adds host phy support to samsung-usbphy driver and >> >> further adds support for samsung's exynos5250 usb-phy. >> >> >> >> Signed-off-by: Praveen Paneri >> >> Signed-off-by: Vivek Gautam >> > >> > Missing Kukjim's Acked-by here >> > >> >> Hope you are fine with the changes happened after discussion in thread: >> [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver >> >> Is it something you want me to modify in this patch ? > > please send the final patch and we shall see. After quickly browsing > that thread, I didn't see anything scary, but I'd like to see your final > version before giving my final answer ;-) > this series of patch is the final version from my side unless Doug or you have any further comments on the thread : https://lkml.org/lkml/2013/1/14/481 Seems like Doug wanted to know your opinion in this regard. ;-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v7 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Felipe, On Fri, Jan 18, 2013 at 6:46 PM, Felipe Balbi wrote: > Hi, > > On Mon, Jan 14, 2013 at 05:52:15PM +0530, Vivek Gautam wrote: >> This patch adds host phy support to samsung-usbphy driver and >> further adds support for samsung's exynos5250 usb-phy. >> >> Signed-off-by: Praveen Paneri >> Signed-off-by: Vivek Gautam > > Missing Kukjim's Acked-by here > Hope you are fine with the changes happened after discussion in thread: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver Is it something you want me to modify in this patch ? -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v7] usb: phy: samsung: Add support to set pmu isolation
HI Kukjin, On Fri, Jan 18, 2013 at 6:46 AM, Kukjin Kim wrote: > Vivek Gautam wrote: >> >> Adding support to parse device node data in order to get >> required properties to set pmu isolation for usb-phy. >> >> Signed-off-by: Vivek Gautam >> Reviewed-by: Sylwester Nawrocki >> Reviewed-by: Doug Anderson > > This looks good to me, > Acked-by: Kukjin Kim > Thanks > Vivek, could you please re-send following in one series? > - [PATCH v9 1/2] usb: phy: samsung: Introducing usb phy driver for hsotg > - [PATCH v8 2/2] usb: s3c-hsotg: Adding phy driver support > Praveen will re-send this patch-series asap. > As I know, this should be applied on top of above patches. > -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH 2/6] ARM: OMAP: USB: Add phy binding information
Hi Kishon,
Thanks for the explanation.
On Thu, Jan 17, 2013 at 6:01 PM, kishon wrote:
> Hi,
>
>
> On Thursday 17 January 2013 05:41 PM, Vivek Gautam wrote:
>>
>> Hi Kishon,
>>
>>
>> On Wed, Jan 16, 2013 at 8:30 PM, Kishon Vijay Abraham I
>> wrote:
>>>
>>> This is in preparation for the changes in PHY library to support adding
>>> and getting multiple PHYs of the same type. In the new design, the
>>> binding information between the PHY and the USB controller should be
>>> specified in the platform specific initialization code. So it's been
>>> done for OMAP platforms here.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I
>>> ---
>>> This kind-of binding should be done in all the platforms (I've done only
>>> for OMAP platform).
>>> arch/arm/mach-omap2/usb-musb.c |7 ++-
>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/usb-musb.c
>>> b/arch/arm/mach-omap2/usb-musb.c
>>> index 9d27e3f..bbe2fa5 100644
>>> --- a/arch/arm/mach-omap2/usb-musb.c
>>> +++ b/arch/arm/mach-omap2/usb-musb.c
>>> @@ -24,6 +24,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>>
>>> #include "omap_device.h"
>>> #include "soc.h"
>>> @@ -85,8 +86,12 @@ void __init usb_musb_init(struct omap_musb_board_data
>>> *musb_board_data)
>>> musb_plat.mode = board_data->mode;
>>> musb_plat.extvbus = board_data->extvbus;
>>>
>>> - if (cpu_is_omap44xx())
>>> + if (cpu_is_omap44xx()) {
>>> musb_plat.has_mailbox = true;
>>> + usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
>>> + } else if (cpu_is_omap34xx()) {
>>> + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
>>> + }
>>
>>
>> Just trying to understand things here.
>> Is the device name we are using here the platform device name (pdev->name)
>> ?
>
>
> it's pdev->dev.name.
>
>> If i am not wrong then for devices added through device tree
>> the device name would actually include the device address in the string,
>
>
> Ideally for device tree, devm_usb_get_phy_by_phandle() introduced in the 5th
> patch of this series should be used.
Ok.
> usb_bind_phy should be called from platform specific initialization files
> (like your board file), which won't get executed in dt boot.
>
Right.
>> wouldn't that make things somewhat weird, since we will have to add
>> such bindings
>> using this address string.
>>
>> one more doubt please :)
>> is it possible to bind phy in the controllers' driver somehow ?
>
> Thats not going to be good. Why do you need to do that?
>
I was certainly missing something while understanding your patches.
That's why got some doubt on this. :)
> Thanks
> Kishon
--
Thanks & Regards
Vivek
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Re: [RFC PATCH 2/6] ARM: OMAP: USB: Add phy binding information
Hi Kishon,
On Wed, Jan 16, 2013 at 8:30 PM, Kishon Vijay Abraham I wrote:
> This is in preparation for the changes in PHY library to support adding
> and getting multiple PHYs of the same type. In the new design, the
> binding information between the PHY and the USB controller should be
> specified in the platform specific initialization code. So it's been
> done for OMAP platforms here.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> This kind-of binding should be done in all the platforms (I've done only
> for OMAP platform).
> arch/arm/mach-omap2/usb-musb.c |7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
> index 9d27e3f..bbe2fa5 100644
> --- a/arch/arm/mach-omap2/usb-musb.c
> +++ b/arch/arm/mach-omap2/usb-musb.c
> @@ -24,6 +24,7 @@
> #include
> #include
> #include
> +#include
>
> #include "omap_device.h"
> #include "soc.h"
> @@ -85,8 +86,12 @@ void __init usb_musb_init(struct omap_musb_board_data
> *musb_board_data)
> musb_plat.mode = board_data->mode;
> musb_plat.extvbus = board_data->extvbus;
>
> - if (cpu_is_omap44xx())
> + if (cpu_is_omap44xx()) {
> musb_plat.has_mailbox = true;
> + usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
> + } else if (cpu_is_omap34xx()) {
> + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
> + }
Just trying to understand things here.
Is the device name we are using here the platform device name (pdev->name) ?
If i am not wrong then for devices added through device tree
the device name would actually include the device address in the string,
wouldn't that make things somewhat weird, since we will have to add
such bindings
using this address string.
one more doubt please :)
is it possible to bind phy in the controllers' driver somehow ?
>
> if (soc_is_am35xx()) {
> oh_name = "am35x_otg_hs";
> --
> 1.7.9.5
>
> --
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> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH v4 2/4] ARM: Exynos5250: Enabling ohci-exynos driver
Hi Tomasz,
On Wed, Jan 16, 2013 at 1:14 PM, Tomasz Figa wrote:
> Hi Vivek,
>
> On Tuesday 15 of January 2013 19:08:30 Vivek Gautam wrote:
>> Adding OHCI device tree node for Exynos5250 along with
>> the device base address.
>>
>> Signed-off-by: Vivek Gautam
>> Acked-by: Jingoo Han
>> Acked-by: Grant Likely
>> ---
>> .../devicetree/bindings/usb/exynos-usb.txt | 15
>> +++ arch/arm/boot/dts/exynos5250.dtsi |
>> 6 ++ 2 files changed, 21 insertions(+), 0 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> b/Documentation/devicetree/bindings/usb/exynos-usb.txt index
>> e8bbb47..f66fcdd 100644
>> --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
>> @@ -23,3 +23,18 @@ Example:
>> interrupts = <0 71 0>;
>> samsung,vbus-gpio = <&gpx2 6 1 3 3>;
>> };
>> +
>> +OHCI
>> +Required properties:
>> + - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
>> + OHCI companion controller in host mode.
>> + - reg: physical base address of the controller and length of memory
>> mapped + region.
>> + - interrupts: interrupt number to the cpu.
>> +
>> +Example:
>> + usb@1212 {
>> + compatible = "samsung,exynos4210-ohci";
>> + reg = <0x1212 0x100>;
>> + interrupts = <0 71 0>;
>> + };
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi index 2cbe53e..ebb0907 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -281,6 +281,12 @@
>> interrupts = <0 71 0>;
>> };
>>
>> + usb@1212 {
>> + compatible = "samsung,exynos4210-ohci";
>> + reg = <0x1212 0x100>;
>> + interrupts = <0 71 0>;
>
> For Samsung platforms we decided per board enabling of nodes and so this
> node should also contain:
>
> status = "disabled";
>
> while in dts file of board using ohci there would be an overriding entry:
>
> usb@1212 {
> status = "okay";
> };
>
Yes, i could see that for exynos4x dt.
> I know that Exynos5250 has not been yet converted into this convention,
> but using it when adding new devices will simplify the process.
>
Sure, will change this and other patches for usb as suggested.
Thanks for the review. :-)
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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos
Hi Tomasz,
On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa wrote:
> Hi Vivek,
>
> Don't you need also some clkdev lookup entry to make the clock available
> in the driver?
>
This clock source we added with a motive of completion, however it's
not being used as of now.
As far as i could see the lookup structure contains clocks for devices
having multiple instances.
Do you feel that i should be adding an entry in clk_lookup structure ?
May be i am missing here something. Can you please elaborate on the
use-case of clk_lookup
entries.
>
> On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
>> Adding necessary device clock to exynos5 needed for
>> the DWC3 controller.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>> arch/arm/mach-exynos/clock-exynos5.c | 24
>> 1 files changed, 24 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>> b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
>> .enable = exynos5_clk_ip_fsys_ctrl ,
>> .ctrlbit= (1 << 18),
>> }, {
>> + .name = "usbdrd30",
>> + .parent = &exynos5_clk_aclk_200.clk,
>> + .enable = exynos5_clk_ip_fsys_ctrl,
>> + .ctrlbit= (1 << 19),
>> + }, {
>> .name = "usbotg",
>> .enable = exynos5_clk_ip_fsys_ctrl,
>> .ctrlbit= (1 << 7),
>> @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
>> = { .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
>> };
>>
>> +struct clk *exynos5_clkset_usbdrd30_list[] = {
>> + [0] = &exynos5_clk_mout_mpll.clk,
>> + [1] = &exynos5_clk_mout_cpll.clk,
>> +};
>> +
>> +struct clksrc_sources exynos5_clkset_usbdrd30 = {
>> + .sources= exynos5_clkset_usbdrd30_list,
>> + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
>> +};
>> +
>> /* Possible clock sources for aclk_266_gscl_sub Mux */
>> static struct clk *clk_src_gscl_266_list[] = {
>> [0] = &clk_ext_xtal_mux,
>> @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>> .parent = &exynos5_clk_mout_cpll.clk,
>> },
>> .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
> },
>> + }, {
>> + .clk= {
>> + .name = "sclk_usbdrd30",
>> + .enable = exynos5_clksrc_mask_fsys_ctrl,
>> + .ctrlbit= (1 << 28),
>> + },
>> + .sources = &exynos5_clkset_usbdrd30,
>> + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
> 1 },
>> + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
> 4 },
>> },
>> };
--
Thanks & Regards
Vivek
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[PATCH v5 1/4] ARM: Exynos5250: Enabling ehci-s5p driver
Adding EHCI device tree node for Exynos5250 along with
the device base adress and gpio line for vbus.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Grant Likely
---
Changes from v4:
- Added gpio line for VBUS of USB2.0 on snow board.
.../devicetree/bindings/usb/exynos-usb.txt | 25
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250-snow.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi |6
4 files changed, 39 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000..e8bbb47
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,25 @@
+Samsung Exynos SoC USB controller
+
+The USB devices interface with USB controllers on Exynos SOCs.
+The device node has following properties.
+
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
+ EHCI controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO that
+ needs to be pulled up for the bus to be powered.
+
+Example:
+
+ usb@1211 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x1211 0x100>;
+ interrupts = <0 71 0>;
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 942d576..7363e14 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -204,4 +204,8 @@
samsung,mfc-r = <0x4300 0x80>;
samsung,mfc-l = <0x5100 0x80>;
};
+
+ usb@1211 {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951..47b6b84 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,8 @@
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
};
};
+
+ usb@1211 {
+ samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..2cbe53e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -275,6 +275,12 @@
#size-cells = <0>;
};
+ usb@1211 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x1211 0x100>;
+ interrupts = <0 71 0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.7.6.5
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Re: [PATCH v4 1/4] ARM: Exynos5250: Enabling ehci-s5p driver
On Tue, Jan 15, 2013 at 7:08 PM, Vivek Gautam wrote:
> Adding EHCI device tree node for Exynos5250 along with
> the device base adress and gpio line for vbus.
>
> Signed-off-by: Vivek Gautam
> Acked-by: Jingoo Han
> Acked-by: Grant Likely
> ---
> .../devicetree/bindings/usb/exynos-usb.txt | 25
>
> arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
> arch/arm/boot/dts/exynos5250.dtsi |6
> 3 files changed, 35 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
> b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> new file mode 100644
> index 000..e8bbb47
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
> @@ -0,0 +1,25 @@
> +Samsung Exynos SoC USB controller
> +
> +The USB devices interface with USB controllers on Exynos SOCs.
> +The device node has following properties.
> +
> +EHCI
> +Required properties:
> + - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
> + EHCI controller in host mode.
> + - reg: physical base address of the controller and length of memory mapped
> + region.
> + - interrupts: interrupt number to the cpu.
> +
> +Optional properties:
> + - samsung,vbus-gpio: if present, specifies the GPIO that
> + needs to be pulled up for the bus to be powered.
> +
> +Example:
> +
> + usb@1211 {
> + compatible = "samsung,exynos4210-ehci";
> + reg = <0x1211 0x100>;
> + interrupts = <0 71 0>;
> + samsung,vbus-gpio = <&gpx2 6 1 3 3>;
> + };
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 942d576..7363e14 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -204,4 +204,8 @@
> samsung,mfc-r = <0x4300 0x80>;
> samsung,mfc-l = <0x5100 0x80>;
> };
> +
> + usb@1211 {
> + samsung,vbus-gpio = <&gpx2 6 1 3 3>;
> + };
Add required vbus gpio for snow board also here.
> };
--
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Vivek
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[PATCH v4 4/4] ARM: Exynos5250: Enabling dwc3-exynos driver
Adding DWC3 device tree node for Exynos5250 needed to
parse device tree data.
Also enabling XHCI support on exynos5250.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/usb/exynos-usb.txt | 14 ++
arch/arm/boot/dts/exynos5250.dtsi |6 ++
arch/arm/mach-exynos/Kconfig |1 +
3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index f66fcdd..d660410 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -38,3 +38,17 @@ Example:
reg = <0x1212 0x100>;
interrupts = <0 71 0>;
};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+ usb@1200 {
+ compatible = "samsung,exynos5250-dwc3";
+ reg = <0x1200 0x1>;
+ interrupts = <0 72 0>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index ebb0907..a747524 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -275,6 +275,12 @@
#size-cells = <0>;
};
+ usb@1200 {
+ compatible = "samsung,exynos5250-dwc3";
+ reg = <0x1200 0x1>;
+ interrupts = <0 72 0>;
+ };
+
usb@1211 {
compatible = "samsung,exynos4210-ehci";
reg = <0x1211 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d26c9f9..e62fd20 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -428,6 +428,7 @@ config MACH_EXYNOS5_DT
depends on ARCH_EXYNOS5
select ARM_AMBA
select USE_OF
+ select USB_ARCH_HAS_XHCI
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based
board.
--
1.7.6.5
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[PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos
Adding necessary device clock to exynos5 needed for
the DWC3 controller.
Signed-off-by: Vivek Gautam
---
arch/arm/mach-exynos/clock-exynos5.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 0208c3a..13af020 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit= (1 << 18),
}, {
+ .name = "usbdrd30",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 << 19),
+ }, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 7),
@@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+ .sources= exynos5_clkset_usbdrd30_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
@@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ }, {
+ .clk= {
+ .name = "sclk_usbdrd30",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit= (1 << 28),
+ },
+ .sources = &exynos5_clkset_usbdrd30,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1
},
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
4 },
},
};
--
1.7.6.5
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[PATCH v4 2/4] ARM: Exynos5250: Enabling ohci-exynos driver
Adding OHCI device tree node for Exynos5250 along with
the device base address.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Grant Likely
---
.../devicetree/bindings/usb/exynos-usb.txt | 15 +++
arch/arm/boot/dts/exynos5250.dtsi |6 ++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index e8bbb47..f66fcdd 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -23,3 +23,18 @@ Example:
interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
};
+
+OHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
+ OHCI companion controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+ usb@1212 {
+ compatible = "samsung,exynos4210-ohci";
+ reg = <0x1212 0x100>;
+ interrupts = <0 71 0>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 2cbe53e..ebb0907 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -281,6 +281,12 @@
interrupts = <0 71 0>;
};
+ usb@1212 {
+ compatible = "samsung,exynos4210-ohci";
+ reg = <0x1212 0x100>;
+ interrupts = <0 71 0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.7.6.5
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[PATCH v4 1/4] ARM: Exynos5250: Enabling ehci-s5p driver
Adding EHCI device tree node for Exynos5250 along with
the device base adress and gpio line for vbus.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
Acked-by: Grant Likely
---
.../devicetree/bindings/usb/exynos-usb.txt | 25
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi |6
3 files changed, 35 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000..e8bbb47
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,25 @@
+Samsung Exynos SoC USB controller
+
+The USB devices interface with USB controllers on Exynos SOCs.
+The device node has following properties.
+
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
+ EHCI controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Optional properties:
+ - samsung,vbus-gpio: if present, specifies the GPIO that
+ needs to be pulled up for the bus to be powered.
+
+Example:
+
+ usb@1211 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x1211 0x100>;
+ interrupts = <0 71 0>;
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 942d576..7363e14 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -204,4 +204,8 @@
samsung,mfc-r = <0x4300 0x80>;
samsung,mfc-l = <0x5100 0x80>;
};
+
+ usb@1211 {
+ samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..2cbe53e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -275,6 +275,12 @@
#size-cells = <0>;
};
+ usb@1211 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x1211 0x100>;
+ interrupts = <0 71 0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.7.6.5
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[PATCH v4 0/4] Enable ehci, ohci and dwc3 devices on exynos5250
Changes from v3: - Clubbed together arch enable patches for ehci/ohci and dwc3: [PATCH v3 0/2] Enable ehci and ohci devices for exynos5250, and [PATCH v3] ARM: Exynos5250: Enabling dwc3-exynos driver - Dropped OF_DEV_AUXDATA entry in mach-exysno5-dt since we don't need it. - Splitted the patch "ARM: Exynos5250: Enabling dwc3-exynos drive" into clock patch and device enabling patch. - Rebased on top of 'for-next' of linux-samsung tree. Vivek Gautam (4): ARM: Exynos5250: Enabling ehci-s5p driver ARM: Exynos5250: Enabling ohci-exynos driver ARM: Exynos5250: Add clock information for dwc3-exynos ARM: Exynos5250: Enabling dwc3-exynos driver .../devicetree/bindings/usb/exynos-usb.txt | 54 arch/arm/boot/dts/exynos5250-smdk5250.dts |4 ++ arch/arm/boot/dts/exynos5250.dtsi | 18 +++ arch/arm/mach-exynos/Kconfig |1 + arch/arm/mach-exynos/clock-exynos5.c | 24 + 5 files changed, 101 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 0/2] usb: exynos: Fix compatible strings used for device
On Thu, Dec 27, 2012 at 4:28 AM, Sylwester Nawrocki
wrote:
> On 12/24/2012 09:13 AM, Vivek Gautam wrote:
>>>>>
>>>>> These two changes look good to me. For both of them:
>>>>>
>>>>> Reviewed-by: Doug Anderson
>>>>
>>>>
>>>> Well, I have another idea. Yes, I know, specific chip name should be
>>>> used.
>>>
>>> But
>>>>
>>>> you know the specific chip name in compatible can cause another
>>>> confusion
>>>> on other SoC which has same IP. So I think, we need to consider to use
>>>> common name or any specific name not chip in compatible for IP/driver
>>>> like
>>>> following?
>>>>
>>>> - { .compatible = "samsung,exynos-dwc3" },
>>>> + { .compatible = "samsung,synopsis-dwc3" },
>>>>
>>>> Or if any version or something, how about following?
>>>>
>>>> + { .compatible = "samsung,dwc-v3" },
>>>>
>> Well, yes the newer SoCs with same IP using the chip name can cause some
>> confusion, but won't it be fine that -
>> "Newer parts using the same core can claim compatibility by
>> including the older string in the compatible list" - as quoted by Grant
>> Likely
>>
>> Or, can we try another option, using multiple compatible strings for
>> SoC specific
>> in of_match_table, so that we don't create any confusion by using same
>> compatible for newer SoCs also. Like,
>>
>> - { .compatible = "samsung,exynos-dwc3" },
>> + { .compatible = "samsung,exynos5250-dwc3" },
>> + { .compatible = },
>
>
> Yes, why not just use an SoC name where given IP first appeared ? I believe
> IP revision numbers are not always well documented. Also when an IP is
> instantiated multiple times in specific SoC, its revision number might not
> be sufficient to determine the system integration details for each instance.
> I think having version for some devices and SoC name for others just adds
> to the confusion. Thus using specific chip name in the compatible property
> seems more clear to me.
>
Ping !!
--
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[PATCH v7] usb: phy: samsung: Add support to set pmu isolation
Adding support to parse device node data in order to get
required properties to set pmu isolation for usb-phy.
Signed-off-by: Vivek Gautam
Reviewed-by: Sylwester Nawrocki
Reviewed-by: Doug Anderson
---
Changes from v6:
- Returning error code in samsung_usbphy_parse_dt() when
'usbphy-sys' sub-node is not present and thereby putting up
dev_err() instead of dev_warn()
.../devicetree/bindings/usb/samsung-usbphy.txt | 36 +
drivers/usb/phy/samsung-usbphy.c | 163 +---
2 files changed, 177 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 7b26e2d..22d06cf 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -9,3 +9,39 @@ Required properties:
- compatible : should be "samsung,exynos4210-usbphy"
- reg : base physical address of the phy registers and length of memory mapped
region.
+
+Optional properties:
+- #address-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- #size-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- ranges: allows valid translation between child's address space and parent's
+ address space.
+
+- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
+ interface for usb-phy. It should provide the following information required
by
+ usb-phy controller to control phy.
+ - reg : base physical address of PHY_CONTROL registers.
+ The size of this register is the total sum of size of all PHY_CONTROL
+ registers that the SoC has. For example, the size will be
+ '0x4' in case we have only one PHY_CONTROL register (e.g.
+ OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
+ and, '0x8' in case we have two PHY_CONTROL registers (e.g.
+ USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
+ and so on.
+
+Example:
+ - Exynos4210
+
+ usbphy@125B {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "samsung,exynos4210-usbphy";
+ reg = <0x125B 0x100>;
+ ranges;
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = <0x10020704 0x8>;
+ };
+ };
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 5c5e1bb5..30aebb5 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -60,20 +61,46 @@
#define MHZ (1000*1000)
#endif
+#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
+#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
+
enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
};
/*
+ * struct samsung_usbphy_drvdata - driver data for various SoC variants
+ * @cpu_type: machine identifier
+ * @devphy_en_mask: device phy enable mask for PHY CONTROL register
+ * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
+ *mapped address of system controller.
+ *
+ * Here we have a separate mask for device type phy.
+ * Having different masks for host and device type phy helps
+ * in setting independent masks in case of SoCs like S5PV210,
+ * in which PHY0 and PHY1 enable bits belong to same register
+ * placed at position 0 and 1 respectively.
+ * Although for newer SoCs like exynos these bits belong to
+ * different registers altogether placed at position 0.
+ */
+struct samsung_usbphy_drvdata {
+ int cpu_type;
+ int devphy_en_mask;
+ u32 devphy_reg_offset;
+};
+
+/*
* struct samsung_usbphy - transceiver driver state
* @phy: transceiver structure
* @plat: platform data
* @dev: The parent device supplied to the probe function
* @clk: usb phy clock
- * @regs: usb phy register memory base
+ * @regs: usb phy controller registers memory base
+ * @pmuregs: USB device PHY_CONTROL register memory base
* @ref_clk_freq: reference clock frequency selection
- * @cpu_type: machine identifier
+ * @drv_data: driver data available for different SoCs
+ * @lock: lock for phy operations
*/
struct samsung_usbphy {
struct usb_phy phy;
@@ -81,12 +108,66 @@ struct samsung_usbphy {
struct device *dev;
struct clk *clk;
void __iomem*regs;
+ void __iomem*pmuregs;
int ref_clk_freq;
- int cpu_type;
+ const struct samsung_usbphy_drvdata *drv_data;
+
Re: [PATCH] usb: phy: samsung: Add support to set pmu isolation
Hi Doug,
On Tue, Jan 15, 2013 at 3:41 AM, Doug Anderson wrote:
> Vivek,
>
> Sorry for being so absent from these reviews. I'll try to look over a
> few patches today, but please don't hold up anything on account of my
> reviews. I'm definitely a bit of an interested bystander in USB land.
> ;)
>
> In general things look pretty good here. :) One last comment below...
>
> On Fri, Jan 11, 2013 at 12:08 AM, Vivek Gautam
> wrote:> +static int
> samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
>> +{
>> + struct device_node *usbphy_sys;
>> +
>> + /* Getting node for system controller interface for usb-phy */
>> + usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
>> + if (!usbphy_sys)
>> + dev_warn(sphy->dev, "No sys-controller interface for
>> usb-phy\n");
>
> Seems like you ought to return with an error here. Calling of_iomap()
> with a NULL value seems undesirable.
>
Yeah, true. This should have been returning error value alongwith dev_err().
>> +
>> + sphy->pmuregs = of_iomap(usbphy_sys, 0);
>> +
>> + of_node_put(usbphy_sys);
>> +
>> + if (sphy->pmuregs == NULL) {
>> + dev_err(sphy->dev, "Can't get usb-phy pmu control
>> register\n");
>> + return -ENODEV;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Set isolation here for phy.
>> + * Here 'on = true' would mean USB PHY block is isolated, hence
>> + * de-activated and vice-versa.
>> + */
>
> Thank you very much for this comment. :) This explains one of the
> confusions I had earlier...
>
Your welcome :-)
>
> Once you fix the one error condition above you can add my
> "Reviewed-by". Thanks!
>
Sure, thanks !!
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[PATCH v3 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/Kconfig |8 +
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usb3.c | 349 ++
drivers/usb/phy/samsung-usbphy.h | 81 +
4 files changed, 439 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb3.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index fae4d08..a7b0536 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -53,3 +53,11 @@ config SAMSUNG_USBPHY
help
Enable this to support Samsung USB phy controller for samsung
SoCs.
+
+config SAMSUNG_USB3PHY
+ bool "Samsung USB 3.0 PHY controller Driver"
+ depends on USB_DWC3
+ select USB_OTG_UTILS
+ help
+ Enable this to support Samsung USB 3.0 phy controller for samsung
+ SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 0f4fd4f..ed28e89 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o samsung-usb2.o
+obj-$(CONFIG_SAMSUNG_USB3PHY) += samsung-usb3.o
diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
new file mode 100644
index 000..8029c1b
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb3.c
@@ -0,0 +1,349 @@
+/* linux/drivers/usb/phy/samsung-usb3.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Vivek Gautam
+ *
+ * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+/*
+ * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock
core.
+ */
+static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
+{
+ u32 reg;
+ u32 refclk;
+
+ refclk = sphy->ref_clk_freq;
+
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ PHYCLKRST_FSEL(refclk);
+
+ switch (refclk) {
+ case FSEL_CLKSEL_50M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_20M:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case FSEL_CLKSEL_19200K:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ case FSEL_CLKSEL_24M:
+ default:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ }
+
+ return reg;
+}
+
+static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyparam0;
+ u32 phyparam1;
+ u32 linksystem;
+ u32 phybatchg;
+ u32 phytest;
+ u32 phyclkrst;
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
+
+ phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
+ /* Select PHY CLK source */
+ phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+ /* Set Loss-of-Signal Detector sensitivity */
+ phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+ phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
+ writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
+
+ writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
+
+ /*
+* Setting the Frame length Adj value[6:1] to default 0x20
+* See xHCI 1.0 spec, 5.2.4
+*/
+ linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20);
+ writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
+
+ phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
+ /* Set Tx De-Emphasis level */
+ phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
+ phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
+ writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1);
+
+ phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG);
+ phybatchg |= PHYBATCHG_UTMI_CLKSEL;
+ writel(phybatchg, regs + E
[PATCH v3 1/2] usb: phy: samsung: Common out the generic stuff
Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common file "samsung-usbphy.c".
Also renaming the usb 2.0 phy driver to "samsung-usb2.c"
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/Makefile |2 +-
drivers/usb/phy/samsung-usb2.c | 511 +++
drivers/usb/phy/samsung-usbphy.c | 713 +-
drivers/usb/phy/samsung-usbphy.h | 247 +
4 files changed, 766 insertions(+), 707 deletions(-)
create mode 100644 drivers/usb/phy/samsung-usb2.c
create mode 100644 drivers/usb/phy/samsung-usbphy.h
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index ec304f6..0f4fd4f 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -9,4 +9,4 @@ obj-$(CONFIG_USB_ISP1301) += isp1301.o
obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
-obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
+obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o samsung-usb2.o
diff --git a/drivers/usb/phy/samsung-usb2.c b/drivers/usb/phy/samsung-usb2.c
new file mode 100644
index 000..ffde341
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb2.c
@@ -0,0 +1,511 @@
+/* linux/drivers/usb/phy/samsung-usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Praveen Paneri
+ *
+ * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
+ * OHCI-EXYNOS controllers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "samsung-usbphy.h"
+
+int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ if (!otg)
+ return -ENODEV;
+
+ if (!otg->host)
+ otg->host = host;
+
+ return 0;
+}
+
+static bool exynos5_phyhost_is_on(void *regs)
+{
+ u32 reg;
+
+ reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ return !(reg & HOST_CTRL0_SIDDQ);
+}
+
+static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
+{
+ void __iomem *regs = sphy->regs;
+ u32 phyclk = sphy->ref_clk_freq;
+ u32 phyhost;
+ u32 phyotg;
+ u32 phyhsic;
+ u32 ehcictrl;
+ u32 ohcictrl;
+
+ /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+ atomic_inc(&sphy->phy_usage);
+
+ if (exynos5_phyhost_is_on(regs)) {
+ dev_info(sphy->dev, "Already power on PHY\n");
+ return;
+ }
+
+ /* Host configuration */
+ phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ /* phy reference clock configuration */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= HOST_CTRL0_FSEL(phyclk);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHYSWRST |
+ HOST_CTRL0_PHYSWRSTALL |
+ HOST_CTRL0_SIDDQ |
+ /* Enable normal mode of operation */
+ HOST_CTRL0_FORCESUSPEND |
+ HOST_CTRL0_FORCESLEEP);
+
+ /* Link reset */
+ phyhost |= (HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST |
+ /* COMMON Block configuration during suspend */
+ HOST_CTRL0_COMMONON_N);
+ writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
+ udelay(10);
+ phyhost &= ~(HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST);
+ writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
+
+ /* OTG configuration */
+ phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
+
+ /* phy reference clock configuration */
+ phyotg &= ~OTG_SYS_FSEL_MASK;
+ phyotg |= OTG_SYS_FSEL(phyclk);
+
+ /* Enable normal mode of operation */
+ phyotg &= ~(OTG_SYS_FORCESUSPEND |
+ OTG_SYS_SIDDQ_UOTG |
+ OTG_SYS_FORCESLEEP |
+ OTG_SYS_REFCLKSEL_MASK |
+ /* COMMON Block configuration during suspend */
+ OTG_SYS_COMMON_ON);
+
+ /* OTG phy & link reset
[PATCH v3 0/2] Adding USB 3.0 DRD-phy support for exynos5250
Changes from v2: - Renaming 'samsung-usbphy.c' driver to 'samsung-usb2.c' indicating usb 2.0 phy controller's driver for Samsung's SoCs. - Moving the register definitions and strcuture definitions to common header file 'samsung-usbphy.h' to be used across usb 2.0 and usb 3.0 phy. - Keeping common exported function definitions in samsung-usbphy.c which can be used across usb 2.0 and usb 3.0 phy. - Writting separate driver file for Samsung's USB 3.0 phy controller. and making it dependent on USB_DWC3. Rebased on top of usb-next followed by following patches/patch-threads: -- [PATCH v9 1/2] usb: phy: samsung: Introducing usb phy driver for hsotg -- [PATCH] usb: phy: samsung: Add support to set pmu isolation (version 6) -- [PATCH v6 0/4] Adding usb2.0 host-phy support for exynos5250 Changes form v1: - Moved architecture related patch out of this patch-set. - Replaced unnecessary multi-line macro definitions by single line definitions. - Creating new data structure for USB 3.0 phy type and embedding it in 'samsung_usbphy' structure. - Adding a flag in 'samsung_usbphy' structure to check if device has usb 3.0 type phy or not. - Restructuring probe sequence for USB 3.0 phy, such that we are initializing only when device has usb3.0 type phy. Vivek Gautam (2): usb: phy: samsung: Common out the generic stuff usb: phy: samsung: Add PHY support for USB 3.0 controller drivers/usb/phy/Kconfig |8 + drivers/usb/phy/Makefile |3 +- drivers/usb/phy/samsung-usb2.c | 511 +++ drivers/usb/phy/samsung-usb3.c | 349 +++ drivers/usb/phy/samsung-usbphy.c | 713 +- drivers/usb/phy/samsung-usbphy.h | 328 + 6 files changed, 1205 insertions(+), 707 deletions(-) create mode 100644 drivers/usb/phy/samsung-usb2.c create mode 100644 drivers/usb/phy/samsung-usb3.c create mode 100644 drivers/usb/phy/samsung-usbphy.h -- 1.7.6.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v7 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy driver and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri Signed-off-by: Vivek Gautam --- Changes from v6: - Changing macro names from 'HOST_CTRL0_FSEL_CLKSEL_XX' to 'FSEL_CLKSEL_XX' since it's being used by HOST and OTG block to prepare reference clock. - Directly Assigning 'FSEL_CLKSEL_XX' to refclk_freq in samsung_usbphy_get_refclk_freq() instead of ORing them since we are anyways using macros: "HOST_CTRL0_FSEL(_x)((_x) << 16)" "OTG_SYS_FSEL(_x) ((_x) << 4)" .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 513 ++-- 3 files changed, 496 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index 22d06cf..0331949 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,15 +1,23 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be "samsung,exynos4210-usbphy" - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be "samsung,exynos5250-usbphy" +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - #address-cells: should be '1' when usbphy node has a child node with 'reg' property. diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 36a85b6..fae4d08 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -48,7 +48,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool "Samsung USB PHY controller Driver" - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 7eec7c3..355c6b2 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,11 +22,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include /* Register definitions */ @@ -57,24 +60,132 @@ #define RSTCON_HLINK_SWRST (0x1 << 1) #define RSTCON_SWRST (0x1 << 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) +#define HOST_CTRL0_FSEL(_x)((_x) << 16) + +#define FSEL_CLKSEL_50M(0x7) +#define FSEL_CLKSEL_24M(0x5) +#define FSEL_CLKSEL_20M(0x4) +#define FSEL_CLKSEL_19200K (0x3) +#define FSEL_CLKSEL_12M(0x2) +#define FSEL_CLKSEL_10M(0x1) +#define FSEL_CLKSEL_9600K (0x0) + +#define HOST_CTRL0_TESTBURNIN (0x1 << 11) +#define HOST_CTRL0_RETENABLE (0x1 << 10) +#define HOST_CTRL0_COMMONON_N (0x1 << 9) +#define HOST_CTRL0_SIDDQ (0x1 << 6) +#define HOST_CTRL0_FORCESLEEP (0x1 << 5) +#define HOST_CTRL0_FORCESUSPEND(0x1 << 4) +#define HOST_CTRL0_WORDINTERFACE
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Mon, Jan 14, 2013 at 11:15 AM, Vivek Gautam
wrote:
> Hi Doug,
>
>
> On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson wrote:
>> Vivek,
>>
>> On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam
>> wrote:
>>>>> +#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
>>>>> +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
>>>>> +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
>>>>> +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
>>>>> +
>>>>> +#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
>>>>> +#define HOST_CTRL0_FSEL(_x)((_x) << 16)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
>>>>> +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
>>>>
>>>> Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
>>>> makes it match the older phy more closely.
>>>>
>>> Wouldn't it hamper the readability when shifts are used ??
>>> I mean if we have something like this -
>>>
>>> phyhost |= HOST_CTRL0_FSEL(phyclk)
>>>
>>> so, if we are using the shifts then
>>> phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M << HOST_CTRL0_FSEL_SHIFT)
>>
>> I was actually suggesting modifying the #defines like this:
>>
>> #define HOST_CTRL0_FSEL_SHIFT 16
>> #define HOST_CTRL0_FSEL_MASK (0x7 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 << HOST_CTRL0_FSEL_SHIFT)
>> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << HOST_CTRL0_FSEL_SHIFT)
>>
>> ...then the code doesn't need to think about shifts, right?
>>
>
> right right, sorry i din't get your point earlier. :-(
>
> this way things will be similar in samsung_usbphy_get_refclk_freq()
> across exynos 5 and older SoCs.
>
> Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
> Can we just do like this ..
> #define HOST_CTRL0_FSEL_MASK (0x7 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 << 16)
> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << 16)
>
Actually missed one thing here, this "HOST_CTRL0_FSEL_CLKSEL_XX" is
being used by
HOST/OTG blocks to prepare reference clock, that's the reason we kept
#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
and #define OTG_SYS_FSEL(_x) ((_x) << 4)
where (_x) is the reference clock returned from
samsung_usbphy_get_refclk_freq().
So in order to avoid confusion we can change the macro names only and
keep something like
#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
#define FSEL_CLKSEL_50M (0x7)
#define FSEL_CLKSEL_24M (0x5)
#define FSEL_CLKSEL_20M (0x4)
#define FSEL_CLKSEL_19200K (0x3)
#define FSEL_CLKSEL_12M (0x2)
#define FSEL_CLKSEL_10M (0x1)
#define FSEL_CLKSEL_9600K(0x0)
...
#define OTG_SYS_FSEL_MASK (0x7 << 4)
#define OTG_SYS_FSEL(_x) ((_x) << 4)
>>
>>>>> if (IS_ERR(ref_clk)) {
>>>>>
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug,
On Sat, Jan 12, 2013 at 6:20 AM, Doug Anderson wrote:
> Vivek,
>
> On Fri, Jan 11, 2013 at 4:40 AM, Vivek Gautam
> wrote:
>>>> +#define HOST_CTRL0_REFCLKSEL_MASK (0x3)
>>>> +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
>>>> +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
>>>> +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
>>>> +
>>>> +#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
>>>> +#define HOST_CTRL0_FSEL(_x)((_x) << 16)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1)
>>>> +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0)
>>>
>>> Add the shifts to the #defines and remove HOST_CTRL0_FSEL(_x). That
>>> makes it match the older phy more closely.
>>>
>> Wouldn't it hamper the readability when shifts are used ??
>> I mean if we have something like this -
>>
>> phyhost |= HOST_CTRL0_FSEL(phyclk)
>>
>> so, if we are using the shifts then
>> phyhost |= (HOST_CTRL0_FSEL_CLKSEL_24M << HOST_CTRL0_FSEL_SHIFT)
>
> I was actually suggesting modifying the #defines like this:
>
> #define HOST_CTRL0_FSEL_SHIFT 16
> #define HOST_CTRL0_FSEL_MASK (0x7 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_50M (0x7 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_24M (0x5 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_20M (0x4 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_12M (0x2 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_10M (0x1 << HOST_CTRL0_FSEL_SHIFT)
> #define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << HOST_CTRL0_FSEL_SHIFT)
>
> ...then the code doesn't need to think about shifts, right?
>
right right, sorry i din't get your point earlier. :-(
this way things will be similar in samsung_usbphy_get_refclk_freq()
across exynos 5 and older SoCs.
Is it fine if we don't use macro for SHIFT, earlier code also doesn't use it.
Can we just do like this ..
#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_50M(0x7 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_24M(0x5 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_20M(0x4 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_12M(0x2 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_10M(0x1 << 16)
#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0 << 16)
>
>>>> if (IS_ERR(ref_clk)) {
>>>> dev_err(sphy->dev, "Failed to get reference clock\n");
>>>> return PTR_ERR(ref_clk);
>>>> }
>>>>
>>>> - switch (clk_get_rate(ref_clk)) {
>>>> - case 12 * MHZ:
>>>> - refclk_freq = PHYCLK_CLKSEL_12M;
>>>> - break;
>>>> - case 24 * MHZ:
>>>> - refclk_freq = PHYCLK_CLKSEL_24M;
>>>> - break;
>>>> - case 48 * MHZ:
>>>> - refclk_freq = PHYCLK_CLKSEL_48M;
>>>> - break;
>>>> - default:
>>>> - if (sphy->cpu_type == TYPE_S3C64XX)
>>>> - refclk_freq = PHYCLK_CLKSEL_48M;
>>>> - else
>>>> + if (sphy->cpu_type == TYPE_EXYNOS5250) {
>>>> + /* set clock frequency for PLL */
>>>> + switch (clk_get_rate(ref_clk)) {
>>>> + case 96 * 10:
>>>
>>> nit: change to 9600 * KHZ to match; below too.
>>>
>> sure.
>>
>>>> + refclk_freq |= HOST_CTRL0_FSEL_CLKSEL_9600K;
>>>
>>> Why |= with 0?
>>>
>> kept this just to keep things look similar :-). will remove this line,
>
> My comment was about keeping things similar. Right now the 5250 code
> has the |= and t
[PATCH v6 4/4] USB: ohci-exynos: Add phy driver support
Adding the phy-driver to ohci-exynos. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
drivers/usb/host/ohci-exynos.c | 84 ++--
1 files changed, 63 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 804fb62..1b38409 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
@@ -22,8 +23,31 @@ struct exynos_ohci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct usb_otg *otg;
+ struct exynos4_ohci_platdata *pdata;
};
+static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+ if (exynos_ohci->phy)
+ usb_phy_init(exynos_ohci->phy);
+ else if (exynos_ohci->pdata->phy_init)
+ exynos_ohci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+}
+
+static void exynos_ohci_phy_disable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+ if (exynos_ohci->phy)
+ usb_phy_shutdown(exynos_ohci->phy);
+ else if (exynos_ohci->pdata->phy_exit)
+ exynos_ohci->pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+}
+
static int ohci_exynos_reset(struct usb_hcd *hcd)
{
return ohci_init(hcd_to_ohci(hcd));
@@ -79,20 +103,15 @@ static u64 ohci_exynos_dma_mask = DMA_BIT_MASK(32);
static int exynos_ohci_probe(struct platform_device *pdev)
{
- struct exynos4_ohci_platdata *pdata;
+ struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci;
struct usb_hcd *hcd;
struct ohci_hcd *ohci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "No platform data defined\n");
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -108,6 +127,20 @@ static int exynos_ohci_probe(struct platform_device *pdev)
if (!exynos_ohci)
return -ENOMEM;
+ phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ /* Fallback to pdata */
+ if (!pdata) {
+ dev_warn(&pdev->dev, "no platform data or transceiver
defined\n");
+ return -EPROBE_DEFER;
+ } else {
+ exynos_ohci->pdata = pdata;
+ }
+ } else {
+ exynos_ohci->phy = phy;
+ exynos_ohci->otg = phy->otg;
+ }
+
exynos_ohci->dev = &pdev->dev;
hcd = usb_create_hcd(&exynos_ohci_hc_driver, &pdev->dev,
@@ -153,8 +186,11 @@ static int exynos_ohci_probe(struct platform_device *pdev)
goto fail_io;
}
- if (pdata->phy_init)
- pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+ if (exynos_ohci->otg)
+ exynos_ohci->otg->set_host(exynos_ohci->otg,
+ &exynos_ohci->hcd->self);
+
+ exynos_ohci_phy_enable(exynos_ohci);
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
@@ -162,13 +198,15 @@ static int exynos_ohci_probe(struct platform_device *pdev)
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err) {
dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_io;
+ goto fail_add_hcd;
}
platform_set_drvdata(pdev, exynos_ohci);
return 0;
+fail_add_hcd:
+ exynos_ohci_phy_disable(exynos_ohci);
fail_io:
clk_disable_unprepare(exynos_ohci->clk);
fail_clk:
@@ -178,14 +216,16 @@ fail_clk:
static int exynos_ohci_remove(struct platform_device *pdev)
{
- struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = exynos_ohci->hcd;
usb_remove_hcd(hcd);
- if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+ if (exynos_ohci->otg)
+ exynos_ohci->otg->set_host(exynos_ohci->otg,
+ &exynos_ohci->hcd->self);
+
+ exynos_ohci_phy_disable(exynos_ohci);
[PATCH v6 3/4] USB: ehci-s5p: Add phy driver support
Adding the phy driver to ehci-s5p. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
drivers/usb/host/ehci-s5p.c | 80 +++---
1 files changed, 59 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 46ca5ef..d603e6e 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
@@ -33,6 +34,9 @@ struct s5p_ehci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct usb_otg *otg;
+ struct s5p_ehci_platdata *pdata;
};
static const struct hc_driver s5p_ehci_hc_driver = {
@@ -66,6 +70,26 @@ static const struct hc_driver s5p_ehci_hc_driver = {
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
};
+static void s5p_ehci_phy_enable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+ if (s5p_ehci->phy)
+ usb_phy_init(s5p_ehci->phy);
+ else if (s5p_ehci->pdata->phy_init)
+ s5p_ehci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+}
+
+static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+ if (s5p_ehci->phy)
+ usb_phy_shutdown(s5p_ehci->phy);
+ else if (s5p_ehci->pdata->phy_exit)
+ s5p_ehci->pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+}
+
static void s5p_setup_vbus_gpio(struct platform_device *pdev)
{
int err;
@@ -88,20 +112,15 @@ static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
static int s5p_ehci_probe(struct platform_device *pdev)
{
- struct s5p_ehci_platdata *pdata;
+ struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci;
struct usb_hcd *hcd;
struct ehci_hcd *ehci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "No platform data defined\n");
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -119,6 +138,20 @@ static int s5p_ehci_probe(struct platform_device *pdev)
if (!s5p_ehci)
return -ENOMEM;
+ phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ /* Fallback to pdata */
+ if (!pdata) {
+ dev_warn(&pdev->dev, "no platform data or transceiver
defined\n");
+ return -EPROBE_DEFER;
+ } else {
+ s5p_ehci->pdata = pdata;
+ }
+ } else {
+ s5p_ehci->phy = phy;
+ s5p_ehci->otg = phy->otg;
+ }
+
s5p_ehci->dev = &pdev->dev;
hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev,
@@ -164,8 +197,10 @@ static int s5p_ehci_probe(struct platform_device *pdev)
goto fail_io;
}
- if (pdata->phy_init)
- pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
+ if (s5p_ehci->otg)
+ s5p_ehci->otg->set_host(s5p_ehci->otg, &s5p_ehci->hcd->self);
+
+ s5p_ehci_phy_enable(s5p_ehci);
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -176,13 +211,15 @@ static int s5p_ehci_probe(struct platform_device *pdev)
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err) {
dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_io;
+ goto fail_add_hcd;
}
platform_set_drvdata(pdev, s5p_ehci);
return 0;
+fail_add_hcd:
+ s5p_ehci_phy_disable(s5p_ehci);
fail_io:
clk_disable_unprepare(s5p_ehci->clk);
fail_clk:
@@ -192,14 +229,15 @@ fail_clk:
static int s5p_ehci_remove(struct platform_device *pdev)
{
- struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
usb_remove_hcd(hcd);
- if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
+ if (s5p_ehci->otg)
+ s5p_ehci->otg->set_host(s5p_ehci->otg, &s5p_ehci->hcd->self);
+
+ s5p_ehci_phy_disable(s5p_ehci);
clk_disable_unprepare(s5p_ehci->clk);
@@ -223,14 +26
[PATCH v6 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support to samsung-usbphy driver and further adds support for samsung's exynos5250 usb-phy. Signed-off-by: Praveen Paneri Signed-off-by: Vivek Gautam --- .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- drivers/usb/phy/Kconfig|2 +- drivers/usb/phy/samsung-usbphy.c | 512 ++-- 3 files changed, 495 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt index 22d06cf..0331949 100644 --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt @@ -1,15 +1,23 @@ * Samsung's usb phy transceiver -The Samsung's phy transceiver is used for controlling usb otg phy for -s3c-hsotg usb device controller. +The Samsung's phy transceiver is used for controlling usb phy for +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers +across Samsung SOCs. TODO: Adding the PHY binding with controller(s) according to the under developement generic PHY driver. Required properties: + +Exynos4210: - compatible : should be "samsung,exynos4210-usbphy" - reg : base physical address of the phy registers and length of memory mapped region. +Exynos5250: +- compatible : should be "samsung,exynos5250-usbphy" +- reg : base physical address of the phy registers and length of memory mapped + region. + Optional properties: - #address-cells: should be '1' when usbphy node has a child node with 'reg' property. diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 36a85b6..fae4d08 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -48,7 +48,7 @@ config USB_RCAR_PHY config SAMSUNG_USBPHY bool "Samsung USB PHY controller Driver" - depends on USB_S3C_HSOTG + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 7eec7c3..d2b6642 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -5,7 +5,8 @@ * * Author: Praveen Paneri * - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller + * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and + * OHCI-EXYNOS controllers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,11 +22,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include /* Register definitions */ @@ -57,24 +60,131 @@ #define RSTCON_HLINK_SWRST (0x1 << 1) #define RSTCON_SWRST (0x1 << 0) +/* EXYNOS5 */ +#define EXYNOS5_PHY_HOST_CTRL0 (0x00) + +#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) + +#define HOST_CTRL0_REFCLKSEL_MASK (0x3) +#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) +#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) +#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) + +#define HOST_CTRL0_FSEL_MASK (0x7 << 16) +#define HOST_CTRL0_FSEL(_x)((_x) << 16) +#define HOST_CTRL0_FSEL_CLKSEL_50M (0x7) +#define HOST_CTRL0_FSEL_CLKSEL_24M (0x5) +#define HOST_CTRL0_FSEL_CLKSEL_20M (0x4) +#define HOST_CTRL0_FSEL_CLKSEL_19200K (0x3) +#define HOST_CTRL0_FSEL_CLKSEL_12M (0x2) +#define HOST_CTRL0_FSEL_CLKSEL_10M (0x1) +#define HOST_CTRL0_FSEL_CLKSEL_9600K (0x0) + +#define HOST_CTRL0_TESTBURNIN (0x1 << 11) +#define HOST_CTRL0_RETENABLE (0x1 << 10) +#define HOST_CTRL0_COMMONON_N (0x1 << 9) +#define HOST_CTRL0_SIDDQ (0x1 << 6) +#define HOST_CTRL0_FORCESLEEP (0x1 << 5) +#define HOST_CTRL0_FORCESUSPEND(0x1 << 4) +#define HOST_CTRL0_WORDINTERFACE (0x1 << 3) +#define HOST_CTRL0_UTMISWRST (0x1 << 2) +#define HOST_CTRL0_LINKSWRST (0x1 << 1) +#define HOST_CTRL0_PHYSWRST(0x1 << 0) + +#define EXYNOS5_PHY_HOST_TUNE0 (0x04) + +#define EXYNOS5_PHY_HSIC_CTRL1 (0x10) + +#define EXYNOS5_PHY_HSIC_TUNE1 (0x14) + +#define EXYNOS5_PHY_HSIC_CTRL2 (0x20) + +#define EXYNOS5_PHY_HSIC_TUNE2 (0x24) + +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#defi
[PATCH v6 1/4] ARM: EXYNOS: Update & move usb-phy types to generic include layer
Updating the names of usb-phy types to more generic names:
USB_PHY_TYPE_DEIVCE & USB_PHY_TYPE_HOST; and further update
its dependencies.
Signed-off-by: Praveen Paneri
Signed-off-by: Vivek Gautam
---
Changes from v5:
- None
drivers/usb/host/ehci-s5p.c |9 +
drivers/usb/host/ohci-exynos.c |9 +
include/linux/usb/samsung_usb_phy.h | 16
3 files changed, 26 insertions(+), 8 deletions(-)
create mode 100644 include/linux/usb/samsung_usb_phy.h
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 319dcfa..46ca5ef 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#define EHCI_INSNREG00(base) (base + 0x90)
@@ -164,7 +165,7 @@ static int s5p_ehci_probe(struct platform_device *pdev)
}
if (pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -198,7 +199,7 @@ static int s5p_ehci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(s5p_ehci->clk);
@@ -229,7 +230,7 @@ static int s5p_ehci_suspend(struct device *dev)
rc = ehci_suspend(hcd, do_wakeup);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(s5p_ehci->clk);
@@ -246,7 +247,7 @@ static int s5p_ehci_resume(struct device *dev)
clk_prepare_enable(s5p_ehci->clk);
if (pdata && pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
/* DMA burst Enable */
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index aa3b884..804fb62 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
struct exynos_ohci_hcd {
@@ -153,7 +154,7 @@ static int exynos_ohci_probe(struct platform_device *pdev)
}
if (pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
@@ -184,7 +185,7 @@ static int exynos_ohci_remove(struct platform_device *pdev)
usb_remove_hcd(hcd);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(exynos_ohci->clk);
@@ -229,7 +230,7 @@ static int exynos_ohci_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
if (pdata && pdata->phy_exit)
- pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_exit(pdev, USB_PHY_TYPE_HOST);
clk_disable_unprepare(exynos_ohci->clk);
@@ -249,7 +250,7 @@ static int exynos_ohci_resume(struct device *dev)
clk_prepare_enable(exynos_ohci->clk);
if (pdata && pdata->phy_init)
- pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+ pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
ohci_resume(hcd, false);
diff --git a/include/linux/usb/samsung_usb_phy.h
b/include/linux/usb/samsung_usb_phy.h
new file mode 100644
index 000..9167826
--- /dev/null
+++ b/include/linux/usb/samsung_usb_phy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * http://www.samsung.com/
+ *
+ * Defines phy types for samsung usb phy controllers - HOST or DEIVCE.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+enum samsung_usb_phy_type {
+ USB_PHY_TYPE_DEVICE,
+ USB_PHY_TYPE_HOST,
+};
--
1.7.6.5
___
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[PATCH v6 0/4] Adding usb2.0 host-phy support for exynos5250
Changes from v5:
- Rebased on top of latest patches:
usb: phy: samsung: Introducing usb phy driver for hsotg (v9)
usb: phy: samsung: Add support to set pmu isolation (v6)
As a result adding hostphy enable mask and hostphy register offsets
to driver data in order to access the HOSTPHY CONTROL register.
- Adding member 'otg' to struct samsung-usbphy so that its consumers
can call otg->set_host so as to make 'phy' aware of the consumer type:
HOST/DEVICE
- Adding 'otg' to 'struct s5p_ehci_hcd' and 'struct exynos_ohci_hcd'
which keeps track of 'otg' of the controllers' phy. This then sets
the host.
- Moved samsung_usbphy_set_type() calls from ehci-s5p and ohci-exynos
to phy driver itself where based on phy_type it is called.
- Added separate macro definition for USB20PHY_CFG register to select
between host/device type usb link.
- Removing unnecessary argument 'phy_type' from samsung_usbphy_set_type()
and samsung_usbphy_cfg_sel().
- Addressed few nits:
-- added macro for 'KHZ'
-- removing useless 'if' from samsung_usbphy_cfg_sel()
-- keeping the place of clk_get intact and requesting driver
data before that.
Vivek Gautam (4):
ARM: EXYNOS: Update & move usb-phy types to generic include layer
usb: phy: samsung: Add host phy support to samsung-phy driver
USB: ehci-s5p: Add phy driver support
USB: ohci-exynos: Add phy driver support
.../devicetree/bindings/usb/samsung-usbphy.txt | 12 +-
drivers/usb/host/ehci-s5p.c| 81 +++-
drivers/usb/host/ohci-exynos.c | 85 +++-
drivers/usb/phy/Kconfig|2 +-
drivers/usb/phy/samsung-usbphy.c | 512 ++--
include/linux/usb/samsung_usb_phy.h| 16 +
6 files changed, 635 insertions(+), 73 deletions(-)
create mode 100644 include/linux/usb/samsung_usb_phy.h
--
1.7.6.5
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Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Felipe, On Fri, Jan 11, 2013 at 6:28 PM, Felipe Balbi wrote: > Hi, > > On Fri, Jan 11, 2013 at 06:10:48PM +0530, Vivek Gautam wrote: >> Hi Doug, >> >> Sorry!! for the delayed response. >> >> >> On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson wrote: >> > Vivek, >> > >> > I don't really have a good 1 foot view about how all of the USB >> > bits fit together, but a few detail-oriented comments below. >> > >> > >> > On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam >> > wrote: >> >> This patch adds host phy support to samsung-usbphy.c and >> >> further adds support for samsung's exynos5250 usb-phy. >> >> >> >> Signed-off-by: Praveen Paneri >> >> Signed-off-by: Vivek Gautam >> >> --- >> >> .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- >> >> drivers/usb/phy/Kconfig|2 +- >> >> drivers/usb/phy/samsung-usbphy.c | 465 >> >> ++-- >> >> include/linux/usb/samsung_usb_phy.h| 13 + >> >> 4 files changed, 454 insertions(+), 51 deletions(-) >> >> >> >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> index a7b28b2..2ec5400 100644 >> >> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> >> @@ -1,23 +1,38 @@ >> >> * Samsung's usb phy transceiver >> >> >> >> -The Samsung's phy transceiver is used for controlling usb otg phy for >> >> -s3c-hsotg usb device controller. >> >> +The Samsung's phy transceiver is used for controlling usb phy for >> >> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers >> >> +across Samsung SOCs. >> >> TODO: Adding the PHY binding with controller(s) according to the under >> >> developement generic PHY driver. >> >> >> >> Required properties: >> >> + >> >> +Exynos4210: >> >> - compatible : should be "samsung,exynos4210-usbphy" >> >> - reg : base physical address of the phy registers and length of memory >> >> mapped >> >> region. >> >> >> >> +Exynos5250: >> >> +- compatible : should be "samsung,exynos5250-usbphy" >> >> +- reg : base physical address of the phy registers and length of memory >> >> mapped >> >> + region. >> >> + >> >> Optional properties: >> >> - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which >> >> provides >> >> binding data to enable/disable device PHY handled >> >> by >> >> - PMU register. >> >> + PMU register; or to configure usb2.0 phy handled >> >> by >> >> + SYSREG. >> >> >> >> Required properties: >> >> - compatible : should be "samsung,usbdev-phyctrl" >> >> for >> >> - DEVICE type phy. >> >> + DEVICE type phy; or >> >> + should be >> >> "samsung,usbhost-phyctrl" for >> >> + HOST type phy; or >> >> + should be "samsung,usb-phycfg" for >> >> + USB2.0 PHY_CFG. >> >> - samsung,phyhandle-reg: base physical address of >> >> - PHY_CONTROL register in >> >> PMU. >> >> +PHY_CONTROL register in >> >> PMU; >> >> +or USB2.0 PHY_CFG >> >> register >> >> +in SYSREG. >> >> - samsung,enable-mask : should be '1' >> >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> >> index 17ad743..13c0eaf 100644 >> >> --- a/drivers/usb/phy/Kconfig >> >> +++ b/driver
Re: [PATCH v5 2/4] usb: phy: samsung: Add host phy support to samsung-phy driver
Hi Doug, Sorry!! for the delayed response. On Thu, Dec 20, 2012 at 4:31 AM, Doug Anderson wrote: > Vivek, > > I don't really have a good 1 foot view about how all of the USB > bits fit together, but a few detail-oriented comments below. > > > On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam > wrote: >> This patch adds host phy support to samsung-usbphy.c and >> further adds support for samsung's exynos5250 usb-phy. >> >> Signed-off-by: Praveen Paneri >> Signed-off-by: Vivek Gautam >> --- >> .../devicetree/bindings/usb/samsung-usbphy.txt | 25 +- >> drivers/usb/phy/Kconfig|2 +- >> drivers/usb/phy/samsung-usbphy.c | 465 >> ++-- >> include/linux/usb/samsung_usb_phy.h| 13 + >> 4 files changed, 454 insertions(+), 51 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> index a7b28b2..2ec5400 100644 >> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> @@ -1,23 +1,38 @@ >> * Samsung's usb phy transceiver >> >> -The Samsung's phy transceiver is used for controlling usb otg phy for >> -s3c-hsotg usb device controller. >> +The Samsung's phy transceiver is used for controlling usb phy for >> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers >> +across Samsung SOCs. >> TODO: Adding the PHY binding with controller(s) according to the under >> developement generic PHY driver. >> >> Required properties: >> + >> +Exynos4210: >> - compatible : should be "samsung,exynos4210-usbphy" >> - reg : base physical address of the phy registers and length of memory >> mapped >> region. >> >> +Exynos5250: >> +- compatible : should be "samsung,exynos5250-usbphy" >> +- reg : base physical address of the phy registers and length of memory >> mapped >> + region. >> + >> Optional properties: >> - samsung,usb-phyhandle : should point to usb-phyhandle sub-node which >> provides >> binding data to enable/disable device PHY handled by >> - PMU register. >> + PMU register; or to configure usb2.0 phy handled by >> + SYSREG. >> >> Required properties: >> - compatible : should be "samsung,usbdev-phyctrl" for >> - DEVICE type phy. >> + DEVICE type phy; or >> + should be "samsung,usbhost-phyctrl" >> for >> + HOST type phy; or >> + should be "samsung,usb-phycfg" for >> + USB2.0 PHY_CFG. >> - samsung,phyhandle-reg: base physical address of >> - PHY_CONTROL register in PMU. >> +PHY_CONTROL register in PMU; >> +or USB2.0 PHY_CFG register >> +in SYSREG. >> - samsung,enable-mask : should be '1' >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> index 17ad743..13c0eaf 100644 >> --- a/drivers/usb/phy/Kconfig >> +++ b/drivers/usb/phy/Kconfig >> @@ -47,7 +47,7 @@ config USB_RCAR_PHY >> >> config SAMSUNG_USBPHY >> bool "Samsung USB PHY controller Driver" >> - depends on USB_S3C_HSOTG >> + depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS >> select USB_OTG_UTILS >> help >> Enable this to support Samsung USB phy controller for samsung >> diff --git a/drivers/usb/phy/samsung-usbphy.c >> b/drivers/usb/phy/samsung-usbphy.c >> index 4ceabe3..621348a 100644 >> --- a/drivers/usb/phy/samsung-usbphy.c >> +++ b/drivers/usb/phy/samsung-usbphy.c >> @@ -5,7 +5,8 @@ >> * >> * Author: Praveen Paneri >> * >> - * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller >> + * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and >> + * OHCI-EXYNOS controllers. >> * >> * This program is free software; you
Re: [PATCH] usb: phy: samsung: Add support to set pmu isolation
Hi Sylwester, On Fri, Jan 11, 2013 at 2:51 PM, Sylwester Nawrocki wrote: > On 01/11/2013 09:08 AM, Vivek Gautam wrote: >> Adding support to parse device node data in order to get >> required properties to set pmu isolation for usb-phy. >> >> Signed-off-by: Vivek Gautam > > Thanks for addressing my all comments, > > Reviewed-by: Sylwester Nawrocki > Thanks for the review and help. :-) -- Thanks & Regards Vivek ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH] usb: phy: samsung: Add support to set pmu isolation
Adding support to parse device node data in order to get
required properties to set pmu isolation for usb-phy.
Signed-off-by: Vivek Gautam
---
Changes from v5:
- Using a global spin_lock member in 'samsung_usbphy' structure to be
used in samsung_usbphy_init() and samsung_usbphy_shutdown()
to take care of all register initialization sequence.
- Addressing few nits:
- Using devphy_reg_offset instead of 'pmureg_devphy_offset'
- Using if else block instead of ternary conditional statement
in samsung_usbphy_set_isolation()
- Using 'bool' type instead of 'int' for 'on' argument in
samsung_usbphy_set_isolation()
- Amending few comments.
.../devicetree/bindings/usb/samsung-usbphy.txt | 36 +
drivers/usb/phy/samsung-usbphy.c | 161 +---
2 files changed, 175 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 7b26e2d..22d06cf 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -9,3 +9,39 @@ Required properties:
- compatible : should be "samsung,exynos4210-usbphy"
- reg : base physical address of the phy registers and length of memory mapped
region.
+
+Optional properties:
+- #address-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- #size-cells: should be '1' when usbphy node has a child node with 'reg'
+ property.
+- ranges: allows valid translation between child's address space and parent's
+ address space.
+
+- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
+ interface for usb-phy. It should provide the following information required
by
+ usb-phy controller to control phy.
+ - reg : base physical address of PHY_CONTROL registers.
+ The size of this register is the total sum of size of all PHY_CONTROL
+ registers that the SoC has. For example, the size will be
+ '0x4' in case we have only one PHY_CONTROL register (e.g.
+ OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
+ and, '0x8' in case we have two PHY_CONTROL registers (e.g.
+ USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
+ and so on.
+
+Example:
+ - Exynos4210
+
+ usbphy@125B {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "samsung,exynos4210-usbphy";
+ reg = <0x125B 0x100>;
+ ranges;
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = <0x10020704 0x8>;
+ };
+ };
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 5c5e1bb5..7eec7c3 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -60,20 +61,46 @@
#define MHZ (1000*1000)
#endif
+#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
+#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
+
enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
};
/*
+ * struct samsung_usbphy_drvdata - driver data for various SoC variants
+ * @cpu_type: machine identifier
+ * @devphy_en_mask: device phy enable mask for PHY CONTROL register
+ * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
+ *mapped address of system controller.
+ *
+ * Here we have a separate mask for device type phy.
+ * Having different masks for host and device type phy helps
+ * in setting independent masks in case of SoCs like S5PV210,
+ * in which PHY0 and PHY1 enable bits belong to same register
+ * placed at position 0 and 1 respectively.
+ * Although for newer SoCs like exynos these bits belong to
+ * different registers altogether placed at position 0.
+ */
+struct samsung_usbphy_drvdata {
+ int cpu_type;
+ int devphy_en_mask;
+ u32 devphy_reg_offset;
+};
+
+/*
* struct samsung_usbphy - transceiver driver state
* @phy: transceiver structure
* @plat: platform data
* @dev: The parent device supplied to the probe function
* @clk: usb phy clock
- * @regs: usb phy register memory base
+ * @regs: usb phy controller registers memory base
+ * @pmuregs: USB device PHY_CONTROL register memory base
* @ref_clk_freq: reference clock frequency selection
- * @cpu_type: machine identifier
+ * @drv_data: driver data available for different SoCs
+ * @lock: lock for phy operatio
Re: [PATCH v5] usb: phy: samsung: Add support to set pmu isolation
Hi Sylwester,
On Thu, Jan 10, 2013 at 3:12 AM, Sylwester Nawrocki
wrote:
> Hi,
>
>
> On 12/28/2012 10:13 AM, Vivek Gautam wrote:
>>
>> Adding support to parse device node data in order to get
>> required properties to set pmu isolation for usb-phy.
>>
>> Signed-off-by: Vivek Gautam
>
> ...
>
>> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -9,3 +9,38 @@ Required properties:
>> - compatible : should be "samsung,exynos4210-usbphy"
>> - reg : base physical address of the phy registers and length of memory
>> mapped
>> region.
>> +
>> +Optional properties:
>> +- #address-cells: should be '1' when usbphy node has a child node with
>> 'reg'
>> + property.
>> +- #size-cells: should be '1' when usbphy node has a child node with 'reg'
>> + property.
>> +- ranges: allows valid translation between child's address space and
>> parent's
>> + address space.
>> +
>> +- The child node 'usbphy-sys' to the node 'usbphy' is for the system
>> controller
>> + interface for usb-phy. It should provide the following information
>> required by
>> + usb-phy controller to control phy.
>> + - reg : base physical address of PHY control register in PMU which
>> + enables/disables the phy controller.
>
>
> On some SoCs USB_PHY_CONTROL registers don't belong to PMU. So maybe you
> should
> drop references to PMU, or list all SoC entities where USB_PHY_CONTROL
> appears:
> PMU, "MISC REGISTER", etc.
>
On S3C64XX "USB_SIG_MASK" bit is in "OTHERS" register, which is actually part of
system controller register map (clock controller + PM controller), and
then S5P64XX onward
this falls under PM controller's memory map. So, i thought of using
reference to PMU.
May be i am missing something here ?
Will change this if you suggest.
> I would just rephrase this to:
>
> - reg : base physical address of PHY_CONTROL registers
>
> "phy controller" might be confusing, since PHY CONTROLLER is an entity
> separate
> from PHY 0 and PHY 1 ?
>
Ok, will change this as suggested.
>
>> + The size of this register is the total sum of size of all
>> phy-control
>
>
> And what about using PHY_CONTROL name as per the User Manuals ? That would
> perhaps make it a bit easier to follow.
>
Sure this is better. We can use PHY_CONTROL to align with user manuals and avoid
any confusions.
>
>> + registers that the SoC has. For example, the size will be
>> + '0x4' in case we have only one phy-control register (like in
>> S3C64XX) or
>> + '0x8' in case we have two phy-control registers (like in
>> Exynos4210)
>> + and so on.
>> +
>> +Example:
>> + - Exynos4210
>> +
>> + usbphy@125B {
>> + #address-cells =<1>;
>> + #size-cells =<1>;
>> + compatible = "samsung,exynos4210-usbphy";
>> + reg =<0x125B 0x100>;
>> + ranges;
>> +
>> + usbphy-sys {
>> + /* USB device and host PHY_CONTROL registers */
>> + reg =<0x10020704 0x8>;
>> + };
>> + };
>
> ...
>
>> /*
>> + * struct samsung_usbphy_drvdata - driver data for various SoC variants
>> + * @cpu_type: machine identifier
>> + * @devphy_en_mask: device phy enable mask for PHY CONTROL register
>> + * @pmureg_devphy_offset: offset to DEVICE PHY CONTROL register from
>> + * mapped address of system controller.
>> + *
>> + * Here we have a separate mask for device type phy.
>> + * Having different masks for host and device type phy helps
>> + * in setting independent masks in case of SoCs like S5PV210,
>> + * in which PHY0 and PHY1 enable bits belong to same register
>> + * placed at position 0 and 1 respectively.
>> + * Although for newer SoCs like exynos these bits belong to
>> + * different registers altogether placed at position 0.
>> + */
>> +struct samsung_usbphy_drvdata {
>> + int cpu_type;
>> + int devphy_en_mask;
>> + u32 pmureg_devphy_offset;
>
>
> Perhaps just "devphy_reg_offset" would do ?
>
Sure, will amend this as suggested.
>
>> +};
>> +
>> +/*
>>* struct samsung_usbphy - transceiver driver state
>>* @phy: transceiver structure
>>* @plat: platform data
>>* @dev: The parent device supplied to the probe function
>>* @clk: usb phy clock
>
