Re: [STLinux Kernel] [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On 24/06/13 15:12, Mark Brown wrote: On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote: This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. I've got the patch on a topic branch in regmap to allow for this sort of stuff - I can readily provide a signed tag for you to get just that patch if that'd help? Alternatively I'm happy to carry the pinctrl patch in regmap? Thanks Mark, Am Ok with either way, it is required that these 2 patches to go together. Linus W, if you are happy with the patch can Mark take it via regmap repo? Thanks, srini ___ Kernel mailing list ker...@stlinux.com http://www.stlinux.com/mailman/listinfo/kernel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On Mon, Jun 24, 2013 at 4:12 PM, Mark Brown broo...@kernel.org wrote: On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote: This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. I've got the patch on a topic branch in regmap to allow for this sort of stuff - I can readily provide a signed tag for you to get just that patch if that'd help? Alternatively I'm happy to carry the pinctrl patch in regmap? I'm OK that you carry this in the regmap tree. Acked-by: Linus Walleij linus.wall...@linaro.org The clock retime weirdness convinced me that this cannot really use the generic pin config layout... Yours, Linus Walleij ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [STLinux Kernel] [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On 25/06/13 11:58, Linus Walleij wrote: On Mon, Jun 24, 2013 at 4:12 PM, Mark Brown broo...@kernel.org wrote: On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote: This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. I've got the patch on a topic branch in regmap to allow for this sort of stuff - I can readily provide a signed tag for you to get just that patch if that'd help? Alternatively I'm happy to carry the pinctrl patch in regmap? I'm OK that you carry this in the regmap tree. Acked-by: Linus Walleij linus.wall...@linaro.org Thanks Linus W. The clock retime weirdness convinced me that this cannot really use the generic pin config layout... Yours, Linus Walleij ___ Kernel mailing list ker...@stlinux.com http://www.stlinux.com/mailman/listinfo/kernel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On Thu, Jun 20, 2013 at 03:05:38PM +0100, Srinivas KANDAGATLA wrote: This patch add pinctrl support to ST SoCs. About hardware: ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle pin configurations. Applied, thanks. signature.asc Description: Digital signature ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On Fri, Jun 21, 2013 at 3:41 PM, Srinivas KANDAGATLA srinivas.kandaga...@st.com wrote: Hi Linus W, If its not too late can this patch be considered for 3.11 via pinctrl tree? There is a build dependecy with regmap_field apis pulled by Mark Brown in regmap repository. This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. Yours, Linus Walleij ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On 24/06/13 12:57, Linus Walleij wrote: On Fri, Jun 21, 2013 at 3:41 PM, Srinivas KANDAGATLA srinivas.kandaga...@st.com wrote: Hi Linus W, If its not too late can this patch be considered for 3.11 via pinctrl tree? There is a build dependecy with regmap_field apis pulled by Mark Brown in regmap repository. This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. Hmmm.. You mean 3.12* Am not sure, But.. Is it possible to make just regmap field api patch go via pinctrl tree, as Mark Brow has already accepted it. Ideally, It would be nice this patch to be part of 3.11-* as, Arnd already pushed SOC support changes to his next branch. thanks, srini Yours, Linus Walleij ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote: This seems fairly complete, but I cannot have such a basic dependency onto the regmap tree this late in the merge window, i.e. I'm not ready to pull all of regmap into the pinctrl tree. I'd consider this for merging for the next kernel cycle so it's more orthogonal. I've got the patch on a topic branch in regmap to allow for this sort of stuff - I can readily provide a signed tag for you to get just that patch if that'd help? Alternatively I'm happy to carry the pinctrl patch in regmap? signature.asc Description: Digital signature ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
Hi Linus W,
If its not too late can this patch be considered for 3.11 via pinctrl tree?
There is a build dependecy with regmap_field apis pulled by Mark Brown
in regmap repository.
https://git.kernel.org/cgit/linux/kernel/git/broonie/regmap.git/commit/?h=for-nextid=67252287871113deba96adf7e4df1752f3f08688
Thanks,
srini
On 20/06/13 15:05, Srinivas KANDAGATLA wrote:
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus Walleij linus.wall...@linaro.org
---
.../devicetree/bindings/pinctrl/pinctrl-st.txt | 110 ++
drivers/pinctrl/Kconfig|6 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-st.c | 1403
4 files changed, 1520 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
create mode 100644 drivers/pinctrl/pinctrl-st.c
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
new file mode 100644
index 000..05bf82a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -0,0 +1,110 @@
+*ST pin controller.
+
+Each multi-function pin is controlled, driven and routed through the
+PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
+and multiple alternate functions(ALT1 - ALTx) that directly connect
+the pin to different hardware blocks.
+
+When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
+Pull Up (PU) are driven by the related PIO block.
+
+ST pinctrl driver controls PIO multiplexing block and also interacts with
+gpio driver to configure a pin.
+
+Required properties: (PIO multiplexing block)
+- compatible : should be st,SOC-pio-block-pinctrl
+ like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells : Should be one. The first cell is the pin number.
+- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
+ If the property is not present, it is assumed that all the pins in the
+ bank are capable of retiming. Retiming is mainly used to improve the
+ IO timing margins of external synchronous interfaces.
+- st,bank-name : Should be a name string for this bank as
+ specified in datasheet.
+- st,syscfg : Should be a phandle of the syscfg node.
+
+Example:
+ pin-controller-sbc {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = st,stih415-sbc-pinctrl;
+ st,syscfg = syscfg_sbc;
+ ranges = 0 0xfe61 0x5000;
+ PIO0: gpio@fe61 {
+ gpio-controller;
+ #gpio-cells = 1;
+ reg = 0 0x100;
+ st,bank-name= PIO0;
+ };
+ ...
+ pin-functions nodes follow...
+ };
+
+
+Contents of function subnode node:
+--
+Required properties for pin configuration node:
+- st,pins: Child node with list of pins with configuration.
+
+Below is the format of how each pin conf should look like.
+
+bank offset mux mode rt_type rt_delay rt_clk
+
+Every PIO is represented with 4-7 parameters depending on retime
configuration.
+Each parameter is explained as below.
+
+-bank: Should be bank phandle to which this PIO belongs.
+-offset : Offset in the PIO bank.
+-mux : Should be alternate function number associated this pin.
+ Use same numbers from datasheet.
+-mode:pin configuration is selected from one of the below
values.
+ IN
+ IN_PU
+ OUT
+ BIDIR
+ BIDIR_PU
+
+-rt_type Retiming Configuration for the pin.
+ Possible retime
[PATCH v3 03/10] pinctrl:st: Add pinctrl and pinconf support.
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus Walleij linus.wall...@linaro.org
---
.../devicetree/bindings/pinctrl/pinctrl-st.txt | 110 ++
drivers/pinctrl/Kconfig|6 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-st.c | 1403
4 files changed, 1520 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
create mode 100644 drivers/pinctrl/pinctrl-st.c
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
new file mode 100644
index 000..05bf82a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -0,0 +1,110 @@
+*ST pin controller.
+
+Each multi-function pin is controlled, driven and routed through the
+PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
+and multiple alternate functions(ALT1 - ALTx) that directly connect
+the pin to different hardware blocks.
+
+When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
+Pull Up (PU) are driven by the related PIO block.
+
+ST pinctrl driver controls PIO multiplexing block and also interacts with
+gpio driver to configure a pin.
+
+Required properties: (PIO multiplexing block)
+- compatible : should be st,SOC-pio-block-pinctrl
+ like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells: Should be one. The first cell is the pin number.
+- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
+ If the property is not present, it is assumed that all the pins in the
+ bank are capable of retiming. Retiming is mainly used to improve the
+ IO timing margins of external synchronous interfaces.
+- st,bank-name : Should be a name string for this bank as
+ specified in datasheet.
+- st,syscfg: Should be a phandle of the syscfg node.
+
+Example:
+ pin-controller-sbc {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = st,stih415-sbc-pinctrl;
+ st,syscfg = syscfg_sbc;
+ ranges = 0 0xfe61 0x5000;
+ PIO0: gpio@fe61 {
+ gpio-controller;
+ #gpio-cells = 1;
+ reg = 0 0x100;
+ st,bank-name= PIO0;
+ };
+ ...
+ pin-functions nodes follow...
+ };
+
+
+Contents of function subnode node:
+--
+Required properties for pin configuration node:
+- st,pins : Child node with list of pins with configuration.
+
+Below is the format of how each pin conf should look like.
+
+bank offset mux mode rt_type rt_delay rt_clk
+
+Every PIO is represented with 4-7 parameters depending on retime configuration.
+Each parameter is explained as below.
+
+-bank : Should be bank phandle to which this PIO belongs.
+-offset: Offset in the PIO bank.
+-mux : Should be alternate function number associated this pin.
+ Use same numbers from datasheet.
+-mode :pin configuration is selected from one of the below values.
+ IN
+ IN_PU
+ OUT
+ BIDIR
+ BIDIR_PU
+
+-rt_type Retiming Configuration for the pin.
+ Possible retime configuration are:
+
+ --- -
+ value args
+ --- -
+ NICLK delay clk
+ ICLK_IO delay clk
+ BYPASS delay
+ DE_IO delay clk
+ SE_ICLK_IO delay clk
+ SE_NICLK_IO delay clk
+
+- delayis retime delay in pico seconds
