[RESEND PATCH v7 22/22] ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
arch/arm/boot/dts/armada-370-xp.dtsi | 2 +
arch/arm/boot/dts/armada-370.dtsi| 101 +++---
arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 222 ++--
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 261 ---
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 409 ---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
9 files changed, 612 insertions(+), 542 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts
b/arch/arm/boot/dts/armada-370-mirabox.dts
index 19341d2..2471d9d 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -28,6 +28,22 @@
ranges = MBUS_ID(0xf0, 0x01) 0 0xd000 0x10
MBUS_ID(0x01, 0xe0) 0 0xfff0 0x10;
+ pcie-controller {
+ status = okay;
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = okay;
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = okay;
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = 2;
@@ -123,22 +139,6 @@
reg = 0x25;
};
};
-
- pcie-controller {
- status = okay;
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = okay;
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI
controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = okay;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi
b/arch/arm/boot/dts/armada-370-xp.dtsi
index 073dd20..e984ce6 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -44,6 +44,8 @@
#size-cells = 1;
controller = mbusc;
interrupt-parent = mpic;
+ pcie-mem-aperture = 0xe000 0x800;
+ pcie-io-aperture = 0xe800 0x10;
devbus-bootcs {
compatible = marvell,mvebu-devbus;
diff --git a/arch/arm/boot/dts/armada-370.dtsi
b/arch/arm/boot/dts/armada-370.dtsi
index bd21d49..648e530 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -36,6 +36,59 @@
reg = MBUS_ID(0x01, 0xe0) 0 0x10;
};
+ pcie-controller {
+ compatible = marvell,armada-370-pcie;
+ status = disabled;
+ device_type = pci;
+
+ #address-cells = 3;
+ #size-cells = 2;
+
+ bus-range = 0x00 0xff;
+
+ ranges =
+ 0x8200 0 0x4 MBUS_ID(0xf0, 0x01)
0x4 0 0x2000
+ 0x8200 0 0x8 MBUS_ID(0xf0, 0x01)
0x8 0 0x2000
+ 0x8200 0x1 0 MBUS_ID(0x04, 0xe8) 0
1 0 /* Port 0.0 MEM */
+ 0x8100 0x1 0 MBUS_ID(0x04, 0xe0) 0
1 0 /* Port 0.0 IO */
+ 0x8200 0x2 0 MBUS_ID(0x08, 0xe8) 0
1 0 /* Port 1.0 MEM */
+ 0x8100 0x2 0 MBUS_ID(0x08, 0xe0) 0
1 0 /* Port 1.0 IO */;
+
+ pcie@1,0 {
+ device_type = pci;
[PATCH v7 22/22] ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
arch/arm/boot/dts/armada-370-xp.dtsi | 2 +
arch/arm/boot/dts/armada-370.dtsi| 101 +++---
arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 222 ++--
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 261 ---
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 409 ---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
9 files changed, 612 insertions(+), 542 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts
b/arch/arm/boot/dts/armada-370-mirabox.dts
index 19341d2..2471d9d 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -28,6 +28,22 @@
ranges = MBUS_ID(0xf0, 0x01) 0 0xd000 0x10
MBUS_ID(0x01, 0xe0) 0 0xfff0 0x10;
+ pcie-controller {
+ status = okay;
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = okay;
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = okay;
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = 2;
@@ -123,22 +139,6 @@
reg = 0x25;
};
};
-
- pcie-controller {
- status = okay;
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = okay;
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI
controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = okay;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi
b/arch/arm/boot/dts/armada-370-xp.dtsi
index 073dd20..e984ce6 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -44,6 +44,8 @@
#size-cells = 1;
controller = mbusc;
interrupt-parent = mpic;
+ pcie-mem-aperture = 0xe000 0x800;
+ pcie-io-aperture = 0xe800 0x10;
devbus-bootcs {
compatible = marvell,mvebu-devbus;
diff --git a/arch/arm/boot/dts/armada-370.dtsi
b/arch/arm/boot/dts/armada-370.dtsi
index bd21d49..648e530 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -36,6 +36,59 @@
reg = MBUS_ID(0x01, 0xe0) 0 0x10;
};
+ pcie-controller {
+ compatible = marvell,armada-370-pcie;
+ status = disabled;
+ device_type = pci;
+
+ #address-cells = 3;
+ #size-cells = 2;
+
+ bus-range = 0x00 0xff;
+
+ ranges =
+ 0x8200 0 0x4 MBUS_ID(0xf0, 0x01)
0x4 0 0x2000
+ 0x8200 0 0x8 MBUS_ID(0xf0, 0x01)
0x8 0 0x2000
+ 0x8200 0x1 0 MBUS_ID(0x04, 0xe8) 0
1 0 /* Port 0.0 MEM */
+ 0x8100 0x1 0 MBUS_ID(0x04, 0xe0) 0
1 0 /* Port 0.0 IO */
+ 0x8200 0x2 0 MBUS_ID(0x08, 0xe8) 0
1 0 /* Port 1.0 MEM */
+ 0x8100 0x2 0 MBUS_ID(0x08, 0xe0) 0
1 0 /* Port 1.0 IO */;
+
+ pcie@1,0 {
+ device_type = pci;
