[Discuss-gnuradio] Questions about Resampling for MPSK
Ok, I've been banging around on this one for a while, and I'm gonna swallow my pride and ask for input. I have a sample of a CDMA Pilot channel 50, 1.9325G, decimation 16, so 6.5Msps. I want to run that through to extract the QPSK constellation, which I can feed to the short PN to extract the pilot sequence. I figured this was a good place to start since the W0 Walsh code simplifies the math a bit. Using usrp2_fft, there is a noticeable 'bump' at the 1.9325G, which is line with the fact it should be 6-8db 'louder' than the other channels. I captured that to a file, and used the throttle to feed it back at 6.5Msps to a resampler. I've tried the basic Costas loop, using the 2*pi*target/sampling fmin/fmax, with alpha in the range 0.25 through 0.0001 with beta set to a*2/4. I fed the output to a constellation plot, and it looks like teenage acne at its worst. I waned to tackle the MPSK Receiver block, but I'm had a hard time finding enough info on all the parameters. I'm about to go dust off old MATLAB code to run some known data through this, but I'd appreciate any and all insights Thanks, TMB ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Building USRP2 FPGA on ISE 11.4
Nope, Nope, and Nope. I was rather shocked, things never go that well for me :) I pulled the u2_rev3 and just resolved my way through the source tree. I was not expecting it to generate cleanly. I did regenerate two cores as part of the process, dumped a couple of the generated .v files because they refused to resolve properly, but the first time through they regenerated and went right through place and route with no errors, and no timing issues like I had with it earlier (set to the -4 speed grade). I just havent been able to generate the bitstream, and I won't have a chance to do any testing til next week, if I do get it resolved. Tracey On Mon, Feb 15, 2010 at 6:52 PM, Jeff Brower wrote: > Tracey- > > > I was able to place and route the design on ISE 11.4 using a 'high' > effort > > and ensuring that the speed grade selected is -5 (that really made a > > difference of about 20MHz in the speed of the final design). However, > when > > it comes time to generate the bitstream, it complains about the -g > > Match_cycle:Auto and insists on changing it to -g Match_cycle:NoWait, > and > > then throws an error, with no information. > > You didn't have to change any source files or the constraints file? No > coregen errors? > > -Jeff > > -- Tracey Bernath 913-488-6284 ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
[Discuss-gnuradio] Building USRP2 FPGA on ISE 11.4
I was able to place and route the design on ISE 11.4 using a 'high' effort and ensuring that the speed grade selected is -5 (that really made a difference of about 20MHz in the speed of the final design). However, when it comes time to generate the bitstream, it complains about the -g Match_cycle:Auto and insists on changing it to -g Match_cycle:NoWait, and then throws an error, with no information. Does this ring a bell for anyone? I haven't seen it before. Thanks, TMB ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
[Discuss-gnuradio] Rebuilding the USRP2 Firmware in ISE 11.4
Just curious, Has anyone actually been able to rebuild the fpga bitfile using ISE 11.4? I loaded the files from the latest git and the .ucf, and I had 239 timing errors when the process completed. I just thought before I started ripping through it I would ask. Thanks, TMB ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
