[Discuss-gnuradio] benchmark_gmsk_rx.py and Flex 2400 Rx

2006-06-01 Thread amit malani
hi guys!

I am trying to use this sample code, benchmark_gmsk_rx.py. I give frequency option to be 29.32e6 (tried 15e6 too)...
but it gives me assertion error..

File /usr/local/lib/python2.4/site-packages/gnuradio/db_flexrf.py, line 392, in _compute_regs
assert self.B_DIV = self.A_DIV

I dont have Flex 2400 daughterboard on my USRP, still it uses Flex 2400 and then it gives this assertion error.

Which value am i putting wrong?
Where exactly does it check and decide which daughter board to be used and on what basis.
How can i make use of this script to work with basic rx daughter board...


thanks for all ur help..
amit

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[Discuss-gnuradio] FPGA change to completely Shutting off Xmission once done.

2006-05-31 Thread amit malani
hello!
sorry if it has reached previously

in one of the previous
conversation you guys discussed about modifying the FPGA code to shut
off the TX once the packet is sent.
i tried an attempt on it.
In the tx_buffer.v file i set all output to be zero either at reset or tx_empty 
i.e. the rd_empty from fifo_4k.

 // DAC Side of FIFO
 assign rdreq = ((load_next != channels)  !tx_empty);
 
 always @(posedge txclk)
 if(reset | tx_empty) //  if tx_empty then too output be zero

 begin  {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}  = #1 128'h0;  load_next = #1 4'd0; end else if((load_next != channels)  !tx_empty)
 begin  load_next = #1 load_next + 4'd1;  case(load_next)  4'd0 : tx_i_0 = #1 fifodata;  4'd1 : tx_q_0 =...Now with this FPGA design i tried fsk_tx.py and fsk_rx.py.
the problem is, when i try transmission in repeat mode only then i see the channel becoming free once i close the transmission..but if i try just one time transmission, the carrier is still present after the transmission ends..
any idea why this is happening?thanks,amit..---Previous conversation-
What daugherboard(s) are you using?What you're describing is currently tough with the basic tx since it'seffectively always on once you fire it up. If you underrun, the
FPGA will continue transmitting the same value to the DAC (which hasthe upconverter in it), thus even if you're not transmitting, it'shighly likely that you really *are* still transmitting.


There are a couple of ways to solve/work-around this behavior:* use a RFX-foo board with auto transmit switching enabled.* modify the FPGA code such that when the TX fifo is empty, you  ramp the value fed to the DAC down to zero over say 8 clocks.
If this doesn't make sense to you, please attach an oscilloscope tothe DAC output and watch what you're currently getting.
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[Discuss-gnuradio] Readback Registers

2006-05-10 Thread amit malani

Hi!

actually I want to use a readback registers. But i could not find any
example to use it.

I looked into the serial_io.v and the setting_reg.v file. but could
not make out how exactly it could be used.

the serial_io module has a input [31:0] readback. Can that be the
output wires 'out' of the setting_reg module with setting the addr as
the Reg number.

for eg.

setting_reg #(`FR_USER_1) read_back(.clock(clk),
.reset(reset),
.strobe(strobe),
.addr(serial_addr),
.in(serial_data),
.out(read_back));// this read_back is connectedt o read_back_0 of
serial_io module

Please let me know,
thanks in advance,

amit.


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[Discuss-gnuradio] setting a Readback Register in FPGA

2006-05-05 Thread amit malani

Hi!
i could not find an example of setting a readback register in FPGA.
What i understood is that the setting_reg module is used to set a
write register.
Is there a similar way to set a readback reg.

a pointer, where to find it or an example would be of great help!

thanks,

amit


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[Discuss-gnuradio] Carrier sense on USRP

2006-04-21 Thread amit malani
Hello..
i am wondering how carrier sense could be implemented on USRP
can those PLLs on FPGA be brought to some use?

Can I do something on the lines of takeing running average
Will constantly keep a track of the incoming samples of the received signals...
calcuate the running average and
Will decide some noise floor/threshold for decision...

I hve very less knowledge of digital signal processing...
will thisidea work?

thanks,
amit

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[Discuss-gnuradio] selective build of FPGA

2006-04-19 Thread amit malani
i wish to build just one rx_hb and one tx.present usrp_std.vh has 2rx 1tx or 4rxwhat do i need to do to...do i need to modify usrp_std.vh or are the dependancies are deep rooted..thanks

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[Discuss-gnuradio] Re: selective build of FPGA

2006-04-19 Thread amit malani
found how to do it...just wanted to veryfy..created one more fileusrp_std_config_1rxhb_1tx.vh on the line of other files uncommented `define TX_SINGLE and`define RX_SINGLE..so this now includes 1 TX and 1 RX halfband  
On 4/19/06, amit malani [EMAIL PROTECTED] wrote:
i wish to build just one rx_hb and one tx.present usrp_std.vh has 2rx 1tx or 4rxwhat do i need to do to...do i need to modify usrp_std.vh or are the dependancies are deep rooted..
thanks


-- Amit MalaniMaster of Science (Information Networking)Carnegie Mellon Universitymobile: 001 516 209 1358
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[Discuss-gnuradio] registers on FPGA

2006-03-23 Thread amit malani
i hve 2 questions
There some registers 32 of the which are common registers 64 to 79 are for custom use.
whatI understoodall of them are written that is set from the host. none of them is read from host. Isthereany wayby which I could communicate some message to host from FPGA.

If it is, thenwill the host need to pull the message..i mean keep polling or is it pushedfrom the USB controllermay be by raising an interrupt.

also,
I wish to implement 2 buffers for one txpath on theFPGA. this could be done by putting multiplexerand demultiplexer across the buffers andselect the needed one by setting the line select lines.
Am thinking of doing this by configuring the user defined registers to do the line selects.

my qestion is can we access those registers from time to time and set and reset them as and when needed? or is it just at the start only so that once they are set thats the final?
am attaching a rough sketch ofintended design.


buffer.PNG
Description: PNG image
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Re: [Discuss-gnuradio] Queries regarding FPGA

2006-03-10 Thread amit malani
i am sorry for asking it again, but few of my questions got lost with the flow of discussion.how control signaling is done?..whats the protocol for it?actually when i say these lines.
src=usrp.source_c(0,decim)src.set_rx_freq(0,IF_freq)src.set_pga(0,20)how actually it gets translated and conveyed to the master_control(?) module on FPGA to do the needful. am I not he right path?
please let me know,thanks in advanceamitOn 2/27/06, Thomas Schmid [EMAIL PROTECTED]
 wrote:Isn't one of the problems that Linux is not a real time os, i.e.,exact time scheduling is impossible? As far as I know, linux timers
have an accuracy of 1ms (i.e. 1 jiffie in the kernel). If you want tohave shorter delays, you use the udelay function and do a busy wait.Or is there something that I am missing?ThomasOn 2/26/06, Eric Blossom 
[EMAIL PROTECTED] wrote: On Sun, Feb 26, 2006 at 11:16:17AM -0500, Clark Pope wrote:  You'll want to strip out the extra receiver. The default fpga is 2 rx and 1  tx. You probably don't need the second RX for your application. You also
  may not need the halfband filter on your receiver.   In the past I've stripped down to a single RX and got utilization down to  about 30%. You'll probably be at 40% with one RX and one TX.
 The current code is (mostly) conditionally configured for number of Rx and Tx channels.You can select 0, 1, 2 or 4 Rx, but right now, the Tx is either 0 or 2.It's easy to fix.I'd welcome a patch (the Tx
 should be conditionalized in the same style as the Rx). Take a look at usrp/fpga/toplevel/usrp_std/usrp_std.v, usrp_std.vh and usrp_std_config_*.vh  As far as control logic. I've been planning something similar (open 
802.11  mac) and I was thinking I could write a linux device driver to do a lot of  the time critical stuff (agc, CA, etc.). Seems like one can poll some  status lines from the FPGA frequently enough to do a lot of things.
 FYI, It's not clear that going to a driver is going to make too much difference.It might, but I'd start with the user mode code. Measure twice, cut once ;) There is some fairly straight-forward work that can be done to reduce
 the latency of the user mode code, and that's probably a good first step.This would also including enabling real-time scheduling for the signal processing threads (SCHED_FIFO), reducing the amount of user
 space buffering for the USRP (no need to mess with the generic buffering in GNU Radio, it's not the problem), and transfering smaller chunks of data across the user/kernel boundary (that that won't help
 throughput!). Eric ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org
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[Discuss-gnuradio] few more queries on FPGA

2006-03-01 Thread amit malani
Hello!the memory allocated for each of the fifo in tx_buffer and rx_buffer is twice their capacity.i.e 65K 'bits'(8192 bytes)..as seen from the compilation report of Quartus.any specific reason?
also, when i have two Rx..Then how exactly is the rx_buffer used to store and keep seperated the data comming from 2 RX paths?Things which could be controlled from Python on FPGA and AD/DA converters are:
Gains.Decimation Rate.Can bits/sample of AD/DA converters be controlled from Python?  What else is controllable from Python?thanksamit
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