On 05/02/2013 12:06 PM, NaceurElOuni wrote:
Hi all,
* Is it a correct to estimate by an ICMP echo-reply the latency between a
host and the USRP N210 at a giving instant.
That wouldnt work. There is a soft micro in the FPGA fabric for the
purposes of network bring-up and some setup functions. This micro
controller is responsible for implementing ICMP so you can ping the
device. But its not in the fast path for baseband samples or anything
like that.
* To estimate the delay in the Digital portion from the FPGA till the signal
is outputted by the antenna, is it a good way to fed the USRP by a signal
(similar as am going to test) from a signal generator into the Rx input, and
get it re conducted as is from the USRP
(I will have to write a code to read samples from input and write them to
output: will that add extra latency ?)
My purpose is to isolate the latency caused by FPGA to Antenna and get a
rough estimate of it (tens, hundreds of microseconds or what range)
You may find lot of helpful advice, and charts here:
http://code.ettus.com/redmine/ettus/projects/public/wiki/Latency
-josh
Thank you in advance.
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