Re: [Discuss-gnuradio] Filter FIR on FPGA
[EMAIL PROTECTED] wrote: > Hi, > I'm designing a pass band filter FIR on FPGA. This filter has 64MHz of sample > rate and as window type "HAMMING". I'm using "MegaCore® IP Library" for > design > of the filter. > Is correct to use this software for design of the filter? Could you suggest me > other software for design of filter? Design it by hand. I allways do it like that, you have better control of what resources are used for the filter. (Especially when using an FPGA without multipliers like the Cyclone) And you can use the filter on any FPGA and share the code with people who do not have access to MegaCore® IP Library. If you only need the filter-taps, you can use the firdes or optfir (part of gnuradio, see gnuradio-examples on how to use) Greetings, Martin > > Thank you very much. > > > > > > ___ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > http://lists.gnu.org/mailman/listinfo/discuss-gnuradio > ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
[Discuss-gnuradio] Filter FIR on FPGA
Hi, I'm designing a pass band filter FIR on FPGA. This filter has 64MHz of sample rate and as window type "HAMMING". I'm using "MegaCore® IP Library" for design of the filter. Is correct to use this software for design of the filter? Could you suggest me other software for design of filter? Thank you very much. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Filter FIR on FPGA
On Dec 19, 2007 9:22 AM, <[EMAIL PROTECTED]> wrote: > Hello, > I'm working on FPGA and in particulary on side RX. I want to insert a filter > FIR > pass band after the output of ADC and before the input of DDC. The filter is > simulated across MATLAB in particulary across "fdatool" and it is written in > verilog. What's the sampling frequency for this filter FIR? Is correct to > insert this filter? The sample rate of the ADC is 64Msps. The samples then go through the CORDIC to generate complex pairs, then through a CIC with minimum decimation of 4, and then through a halfband 2:1 decimating filter. What symbol rate are you looking at in your simulation and how many samples per symbol are you looking to process? What are the characteristics of your filter (taps, symmetric, etc?) The lack of hardware multipliers inside the FPGA requires you to run a relatively simple filter unless you are running at "low" sample rates which allows you to serialize the data going through one or two multipliers and accumulate the output. Brian ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
[Discuss-gnuradio] Filter FIR on FPGA
Hello, I'm working on FPGA and in particulary on side RX. I want to insert a filter FIR pass band after the output of ADC and before the input of DDC. The filter is simulated across MATLAB in particulary across "fdatool" and it is written in verilog. What's the sampling frequency for this filter FIR? Is correct to insert this filter? Thank you very much. Calogero ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
