[Discuss-gnuradio] Free USRP FPGA Resources

2007-04-22 Thread Eng. Firas

Dear Matt, 
Dear All,


Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify the
CIC + HBF circuit and to build a complete DDC block (CIC + CFIR + PFIR) ?

Thank you in advance.

Firas
-- 
View this message in context: 
http://www.nabble.com/Free-USRP-FPGA-Resources-tf3625577.html#a10123967
Sent from the GnuRadio mailing list archive at Nabble.com.



___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio


Re: [Discuss-gnuradio] Free USRP FPGA Resources

2007-04-22 Thread Eng. Firas



Brian Padalino wrote:
 
 On 4/22/07, Eng. Firas [EMAIL PROTECTED] wrote:

 Dear Matt,
 Dear All,


 Is the DDC decimate by 2 half band filter built inside the FPGA ? If it
 is
 so, then how much the free available FPGA resources left after building
 all
 the present USPR circuits in it? I mean, is there a free space to modify
 the
 CIC + HBF circuit and to build a complete DDC block (CIC + CFIR + PFIR) ?
 
 The standard USRP build has about 95% of the LE's used up, but a
 decent amount of memory free.  If you plan on using only 1 complex RX
 path and 1 complex TX path - you can remove quite a bit of logic and
 build with a single side enabled.
 
 Thank you in advance.

 Firas
 
 Brian
 
 
 ___
 Discuss-gnuradio mailing list
 Discuss-gnuradio@gnu.org
 http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
 
 
Thank you Brian.


Best regards, 
Firas
-- 
View this message in context: 
http://www.nabble.com/Free-USRP-FPGA-Resources-tf3625577.html#a10128203
Sent from the GnuRadio mailing list archive at Nabble.com.



___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio


Re: [Discuss-gnuradio] Free USRP FPGA Resources

2007-04-22 Thread Brian Padalino

On 4/22/07, Eng. Firas [EMAIL PROTECTED] wrote:


Dear Matt,
Dear All,


Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify the
CIC + HBF circuit and to build a complete DDC block (CIC + CFIR + PFIR) ?


The standard USRP build has about 95% of the LE's used up, but a
decent amount of memory free.  If you plan on using only 1 complex RX
path and 1 complex TX path - you can remove quite a bit of logic and
build with a single side enabled.


Thank you in advance.

Firas


Brian


___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio