[Regression] [PATCH] intel_crt_detect_ddc() seems to be broken for DVI-I
Hello
Since Linux 2.6.36 the digital output on my system (855GME + DVI-I) is
not working any longer. The analog output is always activated regardless
of the type of monitor attached.
The culprit seems to be intel_crt_detect_ddc(), which returns true as
soon as an ACK from the EDID device is received. Obviously this approach
does not work with DVI-I where the analog and digital outputs share a
common DDC bus.
The patch below adds an additional check to make sure that there is
really an analog device attached (similar to the "Mac mini hack" in
intel_sdvo.c)
Signed-off-by: David Müller
diff -dpurN a/drivers/gpu/drm/i915/intel_crt.c
b/drivers/gpu/drm/i915/intel_crt.c
--- a/drivers/gpu/drm/i915/intel_crt.c 2011-01-05 10:35:18.44923 +0100
+++ b/drivers/gpu/drm/i915/intel_crt.c 2011-01-06 12:16:47.630998952 +0100
@@ -30,6 +30,7 @@
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
+#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
@@ -287,8 +288,9 @@ static bool intel_crt_ddc_probe(struct d
return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
}
-static bool intel_crt_detect_ddc(struct intel_crt *crt)
+static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
+ struct intel_crt *crt = intel_attached_crt(connector);
struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
/* CRT should always be at 0, but check anyway */
@@ -301,8 +303,26 @@ static bool intel_crt_detect_ddc(struct
}
if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
- DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
- return true;
+ struct edid *edid;
+ bool is_digital = false;
+
+ edid = drm_get_edid(connector,
+ &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
+ /*
+* This may be a DVI-I connector with a shared DDC
+* link between analog and digital outputs, so we
+* have to check the EDID input spec of the attached device.
+*/
+ if (edid != NULL) {
+ is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
+ connector->display_info.raw_edid = NULL;
+ kfree(edid);
+ }
+
+ if (!is_digital) {
+ DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
+ return true;
+ }
}
return false;
@@ -458,7 +478,7 @@ intel_crt_detect(struct drm_connector *c
}
}
- if (intel_crt_detect_ddc(crt))
+ if (intel_crt_detect_ddc(connector))
return connector_status_connected;
if (!force)
@@ -472,7 +492,7 @@ intel_crt_detect(struct drm_connector *c
crtc = intel_get_load_detect_pipe(&crt->base, connector,
NULL, &dpms_mode);
if (crtc) {
- if (intel_crt_detect_ddc(crt))
+ if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
else
status = intel_crt_load_detect(crtc, crt);
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Re: [Regression] [PATCH] intel_crt_detect_ddc() seems to be broken for DVI-I
On Thu, 06 Jan 2011 12:11:38 +0100, "David Müller (ELSOFT AG)" wrote: > The patch below adds an additional check to make sure that there is > really an analog device attached (similar to the "Mac mini hack" in > intel_sdvo.c) Nice patch, thanks. I've applied this to my -fixes queue. -Chris -- Chris Wilson, Intel Open Source Technology Centre -- Learn how Oracle Real Application Clusters (RAC) One Node allows customers to consolidate database storage, standardize their database environment, and, should the need arise, upgrade to a full multi-node Oracle RAC database without downtime or disruption http://p.sf.net/sfu/oracle-sfdevnl-- ___ Dri-devel mailing list dri-de...@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32875] New: KWin 4.5.95 (KDE 4.6) draws blank windows when desktop effects are enabled.
https://bugs.freedesktop.org/show_bug.cgi?id=32875 Summary: KWin 4.5.95 (KDE 4.6) draws blank windows when desktop effects are enabled. Product: Mesa Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/r600 AssignedTo: dri-devel@lists.freedesktop.org ReportedBy: oyvi...@everdot.org All windows appear without any content when desktop effects are enabled. It is possible to resize windows to make the content appear, but that snapshot of content is not updated until the window is resized again. Kwin 4.5.95 is the rc2 of the upcoming KDE 4.6. This new kwin appears to work perfectly (after 10 minutes of testing) with r600 classic, so this does appear to be a r600g bug. Old 4.5.x kwin works fine with both. Please let me know if I can probide any additional information which may help resolve this bug. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Linux 2.6.37
On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote: > > It seems that there is still a regression for intel graphic cards > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. > I can reproduce the problem easily by: > xset dpms force standby; sleep 3s; xset dpms force on > > backlight doesn't get up (there is really dark picture though which > doesn't get brighter by function keys which work normally) after dpms on > until I close and open lid. Hmm. That commit no longer reverts cleanly, so it's not trivial to test whether all those things are exactly the same issue. It's been bisected in the bugzilla entry, but it would be good to verify that yes, reverting it really does fix the issue, and your issue is the exact same one. Chris, any ideas? Linus ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Linux 2.6.37
Hi, On Tue 04-01-11 17:15:45, Linus Torvalds wrote: [...] > We did have another revert to fix hopefullythe last "blank screen" > regression on intel graphics. It seems that there is still a regression for intel graphic cards backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. I can reproduce the problem easily by: xset dpms force standby; sleep 3s; xset dpms force on backlight doesn't get up (there is really dark picture though which doesn't get brighter by function keys which work normally) after dpms on until I close and open lid. The problem wasn't present in 2.6.36 $ lspci -vv [...] 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03) (prog-if 00 [VGA controller]) Subsystem: Fujitsu Limited. Device 137a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: Kernel driver in use: i915 [...] -- Michal Hocko L3 team SUSE LINUX s.r.o. Lihovarska 1060/12 190 00 Praha 9 Czech Republic ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Linux 2.6.37
Just for reference, my initial report was: https://lkml.org/lkml/2010/11/23/146 On Thu 06-01-11 08:29:22, Linus Torvalds wrote: > On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote: > > > > It seems that there is still a regression for intel graphic cards > > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. > > I can reproduce the problem easily by: > > xset dpms force standby; sleep 3s; xset dpms force on > > > > backlight doesn't get up (there is really dark picture though which > > doesn't get brighter by function keys which work normally) after dpms on > > until I close and open lid. > > Hmm. That commit no longer reverts cleanly, so it's not trivial to > test whether all those things are exactly the same issue. It's been > bisected in the bugzilla entry, but it would be good to verify that > yes, reverting it really does fix the issue, and your issue is the > exact same one. > > Chris, any ideas? > >Linus -- Michal Hocko L3 team SUSE LINUX s.r.o. Lihovarska 1060/12 190 00 Praha 9 Czech Republic ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 08/32] drm/nouveau: use system_wq instead of dev_priv->wq
Hello, On Wed, Jan 05, 2011 at 11:16:05AM +1000, Ben Skeggs wrote: > On Wed, 2011-01-05 at 11:07 +1000, Ben Skeggs wrote: > > On Mon, 2011-01-03 at 14:49 +0100, Tejun Heo wrote: > > > With cmwq, there's no reason for nouveau to use a dedicated workqueue. > > > Drop dev_priv->wq and use system_wq instead. > > > > > > Because nouveau_irq_uninstall() may be called from unsleepable > > > context, the work items can't be flushed from there. Instead, init > > > and flush from nouveau_load/unload(). > > Ehh, ok, why not! I'll push this through the nouveau tree, and it'll > > get to Dave from there. > > On second thoughts, this won't apply on top of current nouveau code > that's queued for 2.6.38. Can you rebase on top of Dave's drm-next tree > please. We already missed this merge window, so I'll refresh the patch once the window is closed and resend. Thank you. -- tejun ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Linux 2.6.37
On Thu, 6 Jan 2011 08:29:22 -0800, Linus Torvalds
wrote:
> On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote:
> >
> > It seems that there is still a regression for intel graphic cards
> > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672.
> > I can reproduce the problem easily by:
> > xset dpms force standby; sleep 3s; xset dpms force on
> >
> > backlight doesn't get up (there is really dark picture though which
> > doesn't get brighter by function keys which work normally) after dpms on
> > until I close and open lid.
>
> Hmm. That commit no longer reverts cleanly, so it's not trivial to
> test whether all those things are exactly the same issue. It's been
> bisected in the bugzilla entry, but it would be good to verify that
> yes, reverting it really does fix the issue, and your issue is the
> exact same one.
>
> Chris, any ideas?
My fear is that some machines have a dependency between the backlight
and panel power status. The patch in question changed the timing between
turning on the panel and adjusting the backlight which would be restore
with:
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index aa23070..0b40b4f 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
*intel_lvds)
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
POSTING_READ(lvds_reg);
+ {
+ u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
+ if (wait_for(I915_READ(reg) & PP_ON, 1000))
+ DRM_ERROR("timed out waiting for panel to power up\n");
+ }
+
intel_panel_set_backlight(dev, dev_priv->backlight_level);
}
--
Chris Wilson, Intel Open Source Technology Centre
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[Bug 32634] [r300g, bisected] Massive corruption in Unigine Sanctuary
https://bugs.freedesktop.org/show_bug.cgi?id=32634 Marek Olšák changed: What|Removed |Added Status|NEW |RESOLVED Resolution||FIXED --- Comment #2 from Marek Olšák 2011-01-06 10:10:23 PST --- Fixed with c60f1d8b007625f62a53010bb75e70462eb970ae. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Linux 2.6.37
On Thu, Jan 6, 2011 at 18:49, Chris Wilson wrote:
>
> My fear is that some machines have a dependency between the backlight
> and panel power status. The patch in question changed the timing between
> turning on the panel and adjusting the backlight which would be restore
> with:
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index aa23070..0b40b4f 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
> *intel_lvds)
> I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
> POSTING_READ(lvds_reg);
>
> + {
> + u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
> + if (wait_for(I915_READ(reg) & PP_ON, 1000))
> + DRM_ERROR("timed out waiting for panel to power
> up\n");
> + }
> +
> intel_panel_set_backlight(dev, dev_priv->backlight_level);
> }
FWIW it does not compile:
CC drivers/gpu/drm/i915/intel_lvds.o
drivers/gpu/drm/i915/intel_lvds.c: In function ‘intel_lvds_enable’:
drivers/gpu/drm/i915/intel_lvds.c:110: error: ‘PPS_STATUS’ undeclared
(first use in this function)
drivers/gpu/drm/i915/intel_lvds.c:110: error: (Each undeclared
identifier is reported only once
drivers/gpu/drm/i915/intel_lvds.c:110: error: for each function it appears in.)
make[4]: *** [drivers/gpu/drm/i915/intel_lvds.o] Error 1
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Re: Linux 2.6.37
On Thu, 6 Jan 2011 21:55:23 +0100, Alex Riesen wrote:
> On Thu, Jan 6, 2011 at 18:49, Chris Wilson wrote:
> >
> > My fear is that some machines have a dependency between the backlight
> > and panel power status. The patch in question changed the timing between
> > turning on the panel and adjusting the backlight which would be restore
> > with:
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> > b/drivers/gpu/drm/i915/intel_lvds.c
> > index aa23070..0b40b4f 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
> > *intel_lvds)
> > Â Â Â Â I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
> > Â Â Â Â POSTING_READ(lvds_reg);
> >
> > + Â Â Â {
> > + Â Â Â Â Â Â Â u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS :
> > PPS_STATUS;
> > + Â Â Â Â Â Â Â if (wait_for(I915_READ(reg) & PP_ON, 1000))
> > + Â Â Â Â Â Â Â Â Â Â Â DRM_ERROR("timed out waiting for panel
> > to power up\n");
> > + Â Â Â }
> > +
> > Â Â Â Â intel_panel_set_backlight(dev, dev_priv->backlight_level);
> > Â }
>
> FWIW it does not compile:
> CC drivers/gpu/drm/i915/intel_lvds.o
> drivers/gpu/drm/i915/intel_lvds.c: In function âintel_lvds_enableâ:
> drivers/gpu/drm/i915/intel_lvds.c:110: error: âPPS_STATUSâ undeclared
> (first use in this function)
> drivers/gpu/drm/i915/intel_lvds.c:110: error: (Each undeclared
> identifier is reported only once
> drivers/gpu/drm/i915/intel_lvds.c:110: error: for each function it appears
> in.)
> make[4]: *** [drivers/gpu/drm/i915/intel_lvds.o] Error 1
Daniel quickly pointed out my typo: s/PPS_STATUS/PP_STATUS/
Apologies,
-Chris
--
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Re: Linux 2.6.37
On Thu, Jan 6, 2011 at 21:55, Alex Riesen wrote:
> On Thu, Jan 6, 2011 at 18:49, Chris Wilson wrote:
>>
>> My fear is that some machines have a dependency between the backlight
>> and panel power status. The patch in question changed the timing between
>> turning on the panel and adjusting the backlight which would be restore
>> with:
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
>> b/drivers/gpu/drm/i915/intel_lvds.c
>> index aa23070..0b40b4f 100644
>> --- a/drivers/gpu/drm/i915/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/intel_lvds.c
>> @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
>> *intel_lvds)
>> I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
>> POSTING_READ(lvds_reg);
>>
>> + {
>> + u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
...
> FWIW it does not compile:
> CC drivers/gpu/drm/i915/intel_lvds.o
> drivers/gpu/drm/i915/intel_lvds.c: In function ‘intel_lvds_enable’:
> drivers/gpu/drm/i915/intel_lvds.c:110: error: ‘PPS_STATUS’ undeclared
Ah, I see. Should be PP_STATUS. Whatever. It does not help. The backlight
stays off.
P.S. Probably unrelated, but I just noticed that the backlight never goes
off when closing the lid. Am I supposed to hook up on the corresponding
input event and put the panel in standby? It used to work all by itself,
I think...
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[Bug 32883] New: External LCD monitor slightly wiggles
https://bugs.freedesktop.org/show_bug.cgi?id=32883 Summary: External LCD monitor slightly wiggles Product: DRI Version: XOrg CVS Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/Radeon AssignedTo: dri-devel@lists.freedesktop.org ReportedBy: prijatelj@gmail.com DESCRIPTION: picture on LCD monitor is like if it would shake very fast but very little. It's watchable but I don't think it's not healty for my eyes. This can be noticed already from boot where daemons are being loaded or when the picture comes on external LCD. I've also noticed that from time to time (it happened to me now about 3 times) this slightly wiggling thing becomes very agressive and it's on both screens. Or if I don't have external LCD it's only seen on laptop's screen. It's so agressive I'see parts, many parts of pictures covering between itself and shaking very fast.I'm forced to reboot computer since not even restarting X helps. Maybe this has something to do with slightly wiggles thing on monitor or no, I don't know. SYSTEM: - GPU: Mobility X1400 - distro: Archlinux, - kernel: kernel 2.6.36.2-1 - X.Org: 1.9.2 - xf86-video-ati: 6.13.2-2 - KMS (YES) I've tried to add radeon.disp_priority=2 but the problem is the same. I've tried to add radeon.new_pll=0 but the problem is the same. I've also tried to disable KMS with radeon.nomodeset=0 but after it I'm not able to get into X. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32865] Frogatto (trunk r4089) crashes on startup,
https://bugs.freedesktop.org/show_bug.cgi?id=32865 Ian Romanick changed: What|Removed |Added Keywords||NEEDINFO --- Comment #1 from Ian Romanick 2011-01-06 14:00:51 PST --- The glGenFramebuffers function is part of the GL_ARB_framebuffer_object extension, and I don't think r600c supports that extension. Running 'glxinfo | grep framebuffer' will tell for sure. If this function isn't supported by the driver, it's an application bug. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32865] Frogatto (trunk r4089) crashes on startup,
https://bugs.freedesktop.org/show_bug.cgi?id=32865 --- Comment #2 from Ignacio R. Morelle 2011-01-06 14:25:09 PST --- Indeed it's an application bug and I have now contacted the developers about it. I had originally searched for GL_EXT_framebuffer_object instead, which is supported by this driver. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #6 from Tormod Volden 2011-01-06 15:01:20 PST --- It seems to me that the frame buffer written to is tiled, and that the functions writing into it are unaware of this. I discussed shortly with Alex on IRC, and he said the savages have multiple apertures to the same framebuffer, some providing linear translation. BTW, tiling is a prerequisite for DRI on savage, so I could not check if turning off tiling would fix it. Would be nice if someone could explain how this is meant to work in mesa. I would like to continue debugging this, but I am stuck at this point without knowing how it should work. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #7 from Tormod Volden 2011-01-06 15:15:01 PST --- I googled up a discussion I had 9 months ago and have totally forgotten about (scary), which points to format reworks causing the regression: (dri-devel-2010-04-15.log) 11:50 #dri-devel: < tormod> when a GL-application splats blue spots into other windows (savage, no compiz), is that likely a drm bug? 11:52 #dri-devel: <+ajax> savage! retro. 11:54 #dri-devel: <+ajax> it's likely to be a bug in the dri driver 12:28 #dri-devel: < eosie> how large are these blue spots? 12:29 #dri-devel: < tormod> eosie, I'll try to get a screenshot 12:34 #dri-devel: < tormod> eosie, http://imagebin.ca/view/ZNojCc4.html 12:38 #dri-devel: < eosie> cool 12:40 #dri-devel: < agd5f> tormod: tiling issue 12:41 #dri-devel: < agd5f> I suspect somthing isn't using the right aperture 12:42 #dri-devel: < agd5f> IIRC, savage had several apertures exposed via the PCI BARs 12:42 #dri-devel: < agd5f> the first was the linear view, the others were tiled 12:45 #dri-devel: < tormod> I am not using that savage laptop much any longer, but I think this is new since mesa 7.6 12:45 #dri-devel: < agd5f> tormod: I'd guess a problem is the savage span code 12:46 #dri-devel: < agd5f> *in 12:46 #dri-devel: < tormod> where is the span code? 12:46 #dri-devel: < agd5f> savage_span.c 12:46 #dri-devel: < agd5f> IIRC 12:47 #dri-devel: < agd5f> but it's been ages since I looked at savage 12:47 #dri-devel: < tormod> it's been ages since anyone looked at it :) 12:48 #dri-devel: < agd5f> probably one of the format reworks broke something 12:54 #dri-devel: < tormod> yes I remember format reworks broke some other stuff, that got fixed -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
From: Dave Airlie
This is just an idea that might or might not be a good idea,
it basically adds two ioctls to create a dumb and map a dumb buffer
suitable for scanout. The handle can be passed to the KMS ioctls to create
a framebuffer.
It looks to me like it would be useful in the following cases:
a) in development drivers - we can always provide a shadowfb fallback.
b) libkms users - we can clean up libkms a lot and avoid linking
to libdrm_*.
c) plymouth via libkms is a lot easier.
Userspace bits would be just calls + mmaps. We could probably
mark these handles somehow as not being suitable for acceleartion
so as top stop people who are dumber than dumb.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_crtc.c | 33 +++
drivers/gpu/drm/drm_drv.c|5 +-
drivers/gpu/drm/drm_gem.c|3 +-
drivers/gpu/drm/i915/i915_drv.c |3 +
drivers/gpu/drm/i915/i915_drv.h |7 ++
drivers/gpu/drm/i915/i915_gem.c | 103 --
drivers/gpu/drm/radeon/radeon.h |9 +++
drivers/gpu/drm/radeon/radeon_drv.c | 13
drivers/gpu/drm/radeon/radeon_fb.c |2 +-
drivers/gpu/drm/radeon/radeon_gem.c | 53 --
drivers/gpu/drm/radeon/radeon_mode.h |1 +
include/drm/drm.h|4 +
include/drm/drmP.h | 12
include/drm/drm_crtc.h |7 ++
include/drm/drm_mode.h | 29 ++
15 files changed, 246 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 2baa670..c739170 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2674,3 +2674,36 @@ out:
mutex_unlock(&dev->mode_config.mutex);
return ret;
}
+
+int drm_mode_create_dumb_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *file_priv)
+{
+ struct drm_mode_create_dumb *args = data;
+
+ if (!dev->driver->dumb_create)
+ return -ENOSYS;
+ return dev->driver->dumb_create(file_priv, dev, args);
+}
+
+int drm_mode_mmap_dumb_ioctl(struct drm_device *dev,
+void *data, struct drm_file *file_priv)
+{
+ struct drm_mode_map_dumb *args = data;
+
+ /* call driver ioctl to get mmap offset */
+ if (!dev->driver->dumb_map_offset)
+ return -ENOSYS;
+
+ return dev->driver->dumb_map_offset(file_priv, dev, args->handle,
&args->offset);
+}
+
+int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *file_priv)
+{
+ struct drm_mode_destroy_dumb *args = data;
+
+ if (!dev->driver->dumb_destroy)
+ return -ENOSYS;
+
+ return dev->driver->dumb_destroy(file_priv, dev, args->handle);
+}
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 271835a..3e99198 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -150,7 +150,10 @@ static struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
- DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED)
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED)
};
#define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls )
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index ea1c4b0..aa8df25 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -181,7 +181,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc);
/**
* Removes the mapping from handle to filp for this object.
*/
-static int
+int
drm_gem_handle_delete(struct drm_file *filp, u32 handle)
{
struct drm_device *dev;
@@ -214,6 +214,7 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle)
return 0;
}
+EXPORT_SYMBOL(drm_gem_handle_delete);
/**
* Create a handle for this object. This adds a handle reference
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8724933..ca9434a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -678,6 +678,9 @@ static struct drm_driver driver = {
.gem_init_object = i915_gem_init_object,
.gem_free_objec
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #8 from Tormod Volden 2011-01-06 15:31:26 PST --- Is it possible that the frame buffer address gets wrongly calculated (because of wrong formats or non-initialized stuff) so that it points beyond the linear aperture and reaches inadvertently into a tiled aperture? Can I verify values in gdb against addresses listed in Xorg.0.log? I have tried writing to addresses in gdb to see if I get something on the screen but I got only errors. I don't know if DRI buffers are writable from gdb. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/2] drm/radeon/kms: add pcie get/set lane support for r6xx/r7xx/evergreen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/r300.c|5 +-
drivers/gpu/drm/radeon/r600.c| 118 ++
drivers/gpu/drm/radeon/radeon.h |8 ++
drivers/gpu/drm/radeon/radeon_asic.c | 14 ++--
drivers/gpu/drm/radeon/radeon_asic.h |2 +
drivers/gpu/drm/radeon/radeon_reg.h |9 +++
6 files changed, 145 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 23fee54..fae5e70 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -558,10 +558,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
/* FIXME wait for idle */
- if (rdev->family < CHIP_R600)
- link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
- else
- link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+ link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >>
RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
case RADEON_PCIE_LC_LINK_WIDTH_X0:
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 279794c..60ad8c0 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3531,3 +3531,121 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev,
struct radeon_bo *bo)
} else
WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
}
+
+void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
+{
+ u32 link_width_cntl, mask, target_reg;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return;
+
+ /* FIXME wait for idle */
+
+ switch (lanes) {
+ case 0:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
+ break;
+ case 1:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
+ break;
+ case 2:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
+ break;
+ case 4:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
+ break;
+ case 8:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
+ break;
+ case 12:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
+ break;
+ case 16:
+ default:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
+ break;
+ }
+
+ link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+ if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
+ (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
+ return;
+
+ if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
+ return;
+
+ link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
+RADEON_PCIE_LC_RECONFIG_NOW |
+R600_PCIE_LC_RENEGOTIATE_EN |
+R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
+ link_width_cntl |= mask;
+
+ WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+
+/* some northbridges can renegotiate the link rather than requiring
+ * a complete re-config.
+ * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958,
etc.)
+ */
+if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
+ link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN |
R600_PCIE_LC_UPCONFIGURE_SUPPORT;
+else
+ link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
+
+ WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
+
RADEON_PCIE_LC_RECONFIG_NOW));
+
+if (rdev->family >= CHIP_RV770)
+ target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
+else
+ target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
+
+/* wait for lane set to complete */
+link_width_cntl = RREG32(target_reg);
+while (link_width_cntl == 0x)
+ link_width_cntl = RREG32(target_reg);
+
+}
+
+int r600_get_pcie_lanes(struct radeon_device *rdev)
+{
+ u32 link_width_cntl;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return 0;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return 0;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return 0;
+
+ /* FIXME wait for idle */
+
+ link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+ switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >>
RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
+
[PATCH 2/2] drm/radeon/kms: add support for gen2 pcie link speeds
Supported on rv6xx/r7xx/evergreen. Cards come up in gen1 mode.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c | 53 ++
drivers/gpu/drm/radeon/evergreend.h | 38 +
drivers/gpu/drm/radeon/r600.c | 102 +++
drivers/gpu/drm/radeon/r600d.h | 39 +
drivers/gpu/drm/radeon/radeon.h |2 +
drivers/gpu/drm/radeon/rv770.c | 76 ++
drivers/gpu/drm/radeon/rv770d.h | 38 +
7 files changed, 348 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index eaf4fba..11344c7 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -39,6 +39,7 @@
static void evergreen_gpu_init(struct radeon_device *rdev);
void evergreen_fini(struct radeon_device *rdev);
+static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
{
@@ -2767,6 +2768,9 @@ static int evergreen_startup(struct radeon_device *rdev)
{
int r;
+ /* enable pcie gen2 link */
+ evergreen_pcie_gen2_enable(rdev);
+
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
r = r600_init_microcode(rdev);
if (r) {
@@ -3049,3 +3053,52 @@ void evergreen_fini(struct radeon_device *rdev)
rdev->bios = NULL;
radeon_dummy_page_fini(rdev);
}
+
+static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
+{
+ u32 link_width_cntl, speed_cntl;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return;
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
+ (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
+
+ link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+ link_width_cntl &= ~LC_UPCONFIGURE_DIS;
+ WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl |= LC_GEN2_EN_STRAP;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ } else {
+ link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+ /* XXX: only disable it if gen1 bridge vendor == 0x111d or
0x1106 */
+ if (1)
+ link_width_cntl |= LC_UPCONFIGURE_DIS;
+ else
+ link_width_cntl &= ~LC_UPCONFIGURE_DIS;
+ WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+ }
+}
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 94140e1..b8da323 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -581,6 +581,44 @@
# define DC_HPDx_RX_INT_TIMER(x)((x) << 16)
# define DC_HPDx_EN (1 << 28)
+/* PCIE link stuff */
+#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
+#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
+# define LC_LINK_WIDTH_SHIFT0
+# define LC_LINK_WIDTH_MASK 0x7
+# define LC_LINK_WIDTH_X0 0
+# define LC_LINK_WIDTH_X1 1
+# define LC_LINK_WIDTH_X2 2
+# define LC_LINK_WIDTH_X4 3
+# define LC_LINK_WIDTH_X8 4
+# define LC_LINK_WIDTH_X16 6
+# define LC_LINK_WIDTH_RD_SHIFT 4
+# define LC_LINK_WIDTH_RD_MASK 0x70
+# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
+# define LC_RECONFIG_NOW(1 << 8)
+# define LC_RENEGOTIATION_SUPPORT (1 << 9)
+# define LC_RENEGOTIATE_EN (1 << 10)
+# define LC_SHORT_RECONFIG_EN (1 << 11)
+# define LC_UPCONFIGURE_SUPPORT (1 << 12)
+#
[Bug 29726] New CRTC ID query breaks Radeon DRM in Zaphod mode
https://bugs.freedesktop.org/show_bug.cgi?id=29726 Alex Deucher changed: What|Removed |Added CC||n...@n0nb.us --- Comment #12 from Alex Deucher 2011-01-06 15:54:13 PST --- *** Bug 32885 has been marked as a duplicate of this bug. *** -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
On Fri, 7 Jan 2011 09:16:51 +1000, Dave Airlie wrote:
> +int
> +i915_gem_dumb_create(struct drm_file *file,
> + struct drm_device *dev,
> + struct drm_mode_create_dumb *args)
> +{
> + /* have to work out size/pitch and return them */
> + args->pitch = ALIGN(args->width & ((args->bpp + 1) / 8), 64);
^ oops
I think you meant args->width * ((args->bpp + 7) /8)
> + args->size = args->pitch * args->height;
> + return i915_gem_create(file, dev,
> +args->size, &args->handle);
> +}
The only issue with the dumb libkms fb is the transition to X. Is the
nature of the dumb fb such that we would be prohibited from blitting to
the X fb, or can we use platform specific knowledge to know how we can
abuse it?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
On Thu, Jan 6, 2011 at 3:16 PM, Dave Airlie wrote: > From: Dave Airlie > > This is just an idea that might or might not be a good idea, > it basically adds two ioctls to create a dumb and map a dumb buffer > suitable for scanout. The handle can be passed to the KMS ioctls to create > a framebuffer. > > It looks to me like it would be useful in the following cases: > a) in development drivers - we can always provide a shadowfb fallback. > b) libkms users - we can clean up libkms a lot and avoid linking > to libdrm_*. > c) plymouth via libkms is a lot easier. > > Userspace bits would be just calls + mmaps. We could probably > mark these handles somehow as not being suitable for acceleartion > so as top stop people who are dumber than dumb. > > Signed-off-by: Dave Airlie Looks pretty reasonable. One thing from the IRC conversation on v2 was about cursors -- were they going to be handled through this patch? ~ C. -- When the facts change, I change my mind. What do you do, sir? ~ Keynes Corbin Simpson ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/radeon/kms: set the MSB of the HDP slice size
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 11344c7..b5bc7d0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1147,7 +1147,7 @@ static void evergreen_mc_program(struct radeon_device
*rdev)
tmp |= ((rdev->mc.vram_start >> 24) & 0x);
WREG32(MC_VM_FB_LOCATION, tmp);
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
- WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
WREG32(HDP_NONSURFACE_SIZE, 0x3FFF);
if (rdev->flags & RADEON_IS_AGP) {
WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
--
1.7.1.1
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[PATCH] drm/radeon/kms: fix some typos in evergreen pm4 defines
Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreend.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index b8da323..36d32d8 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -648,7 +648,7 @@ #definePACKET3_NOP 0x10 #definePACKET3_SET_BASE0x11 #definePACKET3_CLEAR_STATE 0x12 -#definePACKET3_INDIRECT_BUFFER_SIZE0x13 +#definePACKET3_INDEX_BUFFER_SIZE 0x13 #definePACKET3_DISPATCH_DIRECT 0x15 #definePACKET3_DISPATCH_INDIRECT 0x16 #definePACKET3_INDIRECT_BUFFER_END 0x17 @@ -689,14 +689,14 @@ # define PACKET3_CB8_DEST_BASE_ENA(1 << 15) # define PACKET3_CB9_DEST_BASE_ENA(1 << 16) # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) -# define PACKET3_CB11_DEST_BASE_ENA (1 << 17) +# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) # define PACKET3_FULL_CACHE_ENA (1 << 20) # define PACKET3_TC_ACTION_ENA(1 << 23) # define PACKET3_VC_ACTION_ENA(1 << 24) # define PACKET3_CB_ACTION_ENA(1 << 25) # define PACKET3_DB_ACTION_ENA(1 << 26) # define PACKET3_SH_ACTION_ENA(1 << 27) -# define PACKET3_SMX_ACTION_ENA (1 << 28) +# define PACKET3_SX_ACTION_ENA(1 << 28) #definePACKET3_ME_INITIALIZE 0x44 #definePACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) #definePACKET3_COND_WRITE 0x45 -- 1.7.1.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
On Fri, 7 Jan 2011 09:16:51 +1000 Dave Airlie wrote: > From: Dave Airlie > > This is just an idea that might or might not be a good idea, > it basically adds two ioctls to create a dumb and map a dumb buffer > suitable for scanout. The handle can be passed to the KMS ioctls to create > a framebuffer. > > It looks to me like it would be useful in the following cases: > a) in development drivers - we can always provide a shadowfb fallback. > b) libkms users - we can clean up libkms a lot and avoid linking > to libdrm_*. > c) plymouth via libkms is a lot easier. > > Userspace bits would be just calls + mmaps. We could probably > mark these handles somehow as not being suitable for acceleartion > so as top stop people who are dumber than dumb. Would extracting libwfb from the server and providing it as a standalone fb access API from the server also fill these needs? It would be a bigger API, but presumably would allow us to share fbs between early boot and subsequent, accelerated usage. We'd still need to settle on the basic allocation API, but we seem to manage that on the server side... -- Jesse Barnes, Intel Open Source Technology Center ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32887] New: [r600g] SIGSEGV src/gallium/drivers/r600/r600_state.c:237
https://bugs.freedesktop.org/show_bug.cgi?id=32887
Summary: [r600g] SIGSEGV
src/gallium/drivers/r600/r600_state.c:237
Product: Mesa
Version: git
Platform: x86 (IA32)
OS/Version: Linux (All)
Status: NEW
Severity: critical
Priority: medium
Component: Drivers/Gallium/r600
AssignedTo: dri-devel@lists.freedesktop.org
ReportedBy: v...@vmware.com
mesa: 6d9ca78ef7bf831b9b63f4bda68623cbae627508 (master)
chipset: RV620
system architecture: i686
libdrm-dev: 2.14.21-1ubuntu2.1
kernel version: 2.6.35-24-generic
Linux distribution: Ubuntu 10.10 i386
Run piglit fbo-generatemipmap-formats test.
$ ./bin/fbo-generatemipmap-formats -auto
Using test set: Core formats
Testing 3
Testing 4
Testing GL_RGB
Testing GL_RGBA
Testing GL_ALPHA
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_LUMINANCE
Probe at (1,1)
Expected: 1.00 1.00 1.00 1.00
Observed: 0.00 0.00 0.00 1.00
Testing GL_LUMINANCE_ALPHA
Testing GL_INTENSITY
Probe at (1,1)
Expected: 1.00 1.00 1.00 1.00
Observed: 0.00 0.00 0.00 0.00
Testing GL_ALPHA4
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_ALPHA8
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_ALPHA12
Segmentation fault (core dumped)
Program terminated with signal 11, Segmentation fault.
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
237if (rctx->vertex_elements->count <
rctx->vs_shader->shader.bc.nresource) {
(gdb) bt
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
#1 0x011087c9 in r600_draw_vbo (ctx=0x8fdad50, info=0xbf953c34) at
src/gallium/drivers/r600/r600_state.c:307
#2 0x0125fbcd in st_draw_vbo (ctx=0x92ec4b0, arrays=0x932e590,
prims=0xbf953cdc, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001', min_index=0,
max_index=3) at src/mesa/state_tracker/st_draw.c:732
#3 0x012e5961 in vbo_draw_arrays (ctx=0x92ec4b0, mode=7, start=0, count=4,
numInstances=1) at src/mesa/vbo/vbo_exec_array.c:588
#4 0x012e5ac8 in vbo_exec_DrawArrays (mode=7, start=0, count=4) at
src/mesa/vbo/vbo_exec_array.c:619
#5 0x0804d636 in piglit_draw_rect_tex ()
#6 0x0804b4e3 in draw_mipmap ()
#7 0x0804bbd9 in test_format ()
#8 0x0804bd02 in piglit_display ()
#9 0x0804de93 in display ()
#10 0x00a8b820 in fghRedrawWindow (window=DWARF-2 expression error: DW_OP_reg
operations must be used either alone or in conjuction with DW_OP_piece or
DW_OP_bit_piece.
) at freeglut_main.c:210
#11 fghcbDisplayWindow (window=DWARF-2 expression error: DW_OP_reg operations
must be used either alone or in conjuction with DW_OP_piece or DW_OP_bit_piece.
) at freeglut_main.c:227
#12 0x00a8f660 in fgEnumWindows (enumCallback=0xa8b790 ,
enumerator=0xbf953f88) at freeglut_structure.c:394
#13 0x00a8bcdb in fghDisplayAll () at freeglut_main.c:249
#14 glutMainLoopEvent () at freeglut_main.c:1450
#15 0x00a8c605 in glutMainLoop () at freeglut_main.c:1498
#16 0x0804e03c in main ()
(gdb) frame 0
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
237if (rctx->vertex_elements->count <
rctx->vs_shader->shader.bc.nresource) {
(gdb) print rctx->vertex_elements
$1 = (struct r600_vertex_element *) 0x0
--
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[Bug 32887] [r600g] SIGSEGV src/gallium/drivers/r600/r600_state.c:237
https://bugs.freedesktop.org/show_bug.cgi?id=32887 --- Comment #1 from Vinson Lee 2011-01-06 18:00:24 PST --- 876effb0e717e8e64050662f6ffa286c22065f5c is the first bad commit commit 876effb0e717e8e64050662f6ffa286c22065f5c Author: Dave Airlie Date: Fri Dec 24 17:33:41 2010 +1000 r600g: hack around property unknown issues. should fix https://bugs.freedesktop.org/show_bug.cgi?id=32619 Need to add proper support for properties later. Signed-off-by: Dave Airlie :04 04 fcc05c38e5c4f2c44622a99f64bc09dd3c6af879 f84be8bf6e3f262d1f5dd2d2445b73f434a2d0b3 Msrc bisect run success -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 0/25] drm/radeon/kms: Add support for NI (Northern Islands)
This patchset adds support for evergreen+ based NI asics (Barts, Turks, and Caicos). It includes full acceleration (2D and 3D) for these asics. Mesa 7.10 or git master and xf86-video-ati from git master are required. There is no support for UMS, KMS is required. The 3D engine on Barts, Turks, and Caicos is based and evergreen and is programmed similarly. The big change is the display block (DCE5) which includes new features such as improved color correction, HDMI 1.4a, and DP 1.2. New ucode is required and is available here: http://people.freedesktop.org/~agd5f/radeon_ucode/ The vbios no longer loads the MC (memory controller) ucode during asic init, so the driver now has to load it. Support for Cayman (Radeon HD 69xx asics) is in progress, but not yet ready for release. Alex ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 01/25] drm/radeon/kms: clean up ASIC_IS_DCE41() macro
only fusion asics are dce4.1
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |3 ++-
drivers/gpu/drm/radeon/radeon_encoders.c |6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3e635c6..396e307 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1335,7 +1335,8 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
-#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM))
+#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
+(rdev->flags & RADEON_IS_IGP))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 55b84b8..c83ad89 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1329,7 +1329,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
switch (mode) {
case DRM_MODE_DPMS_ON:
default:
- if (ASIC_IS_DCE41(rdev) && (rdev->flags &
RADEON_IS_IGP))
+ if (ASIC_IS_DCE41(rdev))
action =
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
else
action = ATOM_ENABLE;
@@ -1337,7 +1337,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- if (ASIC_IS_DCE41(rdev) && (rdev->flags &
RADEON_IS_IGP))
+ if (ASIC_IS_DCE41(rdev))
action =
EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
else
action = ATOM_DISABLE;
@@ -1663,7 +1663,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
}
if (ext_encoder) {
- if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) {
+ if (ASIC_IS_DCE41(rdev)) {
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
atombios_external_encoder_setup(encoder, ext_encoder,
--
1.7.1.1
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[PATCH 02/25] drm/radeon/kms: add NI chip families
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_device.c |3 +++
drivers/gpu/drm/radeon/radeon_family.h |3 +++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 396e307..73730fd 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1337,6 +1337,7 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
(rdev->flags & RADEON_IS_IGP))
+#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 44cf0d7..e353430 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -82,6 +82,9 @@ static const char radeon_family_name[][16] = {
"CYPRESS",
"HEMLOCK",
"PALM",
+ "BARTS",
+ "TURKS",
+ "CAICOS",
"LAST",
};
diff --git a/drivers/gpu/drm/radeon/radeon_family.h
b/drivers/gpu/drm/radeon/radeon_family.h
index 4c222d5..1ca55eb 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -81,6 +81,9 @@ enum radeon_family {
CHIP_CYPRESS,
CHIP_HEMLOCK,
CHIP_PALM,
+ CHIP_BARTS,
+ CHIP_TURKS,
+ CHIP_CAICOS,
CHIP_LAST,
};
--
1.7.1.1
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[PATCH 03/25] drm/radeon/kms: update display watermark calculations for DCE5
Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen.c | 20 1 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index b5bc7d0..9c990c3 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -401,16 +401,28 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, case 0: case 4: default: - return 3840 * 2; + if (ASIC_IS_DCE5(rdev)) + return 4096 * 2; + else + return 3840 * 2; case 1: case 5: - return 5760 * 2; + if (ASIC_IS_DCE5(rdev)) + return 6144 * 2; + else + return 5760 * 2; case 2: case 6: - return 7680 * 2; + if (ASIC_IS_DCE5(rdev)) + return 8192 * 2; + else + return 7680 * 2; case 3: case 7: - return 1920 * 2; + if (ASIC_IS_DCE5(rdev)) + return 2048 * 2; + else + return 1920 * 2; } } -- 1.7.1.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 04/25] drm/radeon/kms: DCE5 supports 16k display surfaces
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_display.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
b/drivers/gpu/drm/radeon/radeon_display.c
index acebbc7..30d867c 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1119,7 +1119,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
- if (ASIC_IS_AVIVO(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ rdev->ddev->mode_config.max_width = 16384;
+ rdev->ddev->mode_config.max_height = 16384;
+ } else if (ASIC_IS_AVIVO(rdev)) {
rdev->ddev->mode_config.max_width = 8192;
rdev->ddev->mode_config.max_height = 8192;
} else {
--
1.7.1.1
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[PATCH 05/25] drm/radeon/kms: DCE5 atom SetPixelClock updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 31 +++--
drivers/gpu/drm/radeon/radeon_atombios.c | 25 ++-
2 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9fbabaa..b3e5e75 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -673,9 +673,14 @@ union set_pixel_clock {
PIXEL_CLOCK_PARAMETERS_V2 v2;
PIXEL_CLOCK_PARAMETERS_V3 v3;
PIXEL_CLOCK_PARAMETERS_V5 v5;
+ PIXEL_CLOCK_PARAMETERS_V6 v6;
};
-static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
+/* on DCE5, make sure the voltage is high enough to support the
+ * required disp clk.
+ */
+static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
+ u32 dispclk)
{
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
@@ -698,9 +703,16 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
* SetPixelClock provides the dividers
*/
args.v5.ucCRTC = ATOM_CRTC_INVALID;
- args.v5.usPixelClock = rdev->clock.default_dispclk;
+ args.v5.usPixelClock = dispclk;
args.v5.ucPpll = ATOM_DCPLL;
break;
+ case 6:
+ /* if the default dcpll clock is specified,
+* SetPixelClock provides the dividers
+*/
+ args.v6.ulDispEngClkFreq = dispclk;
+ args.v6.ucPpll = ATOM_DCPLL;
+ break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
return;
@@ -784,6 +796,18 @@ static void atombios_crtc_program_pll(struct drm_crtc
*crtc,
args.v5.ucEncoderMode = encoder_mode;
args.v5.ucPpll = pll_id;
break;
+ case 6:
+ args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
+ args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock
/ 10);
+ args.v6.ucRefDiv = ref_div;
+ args.v6.usFbDiv = cpu_to_le16(fb_div);
+ args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div *
10);
+ args.v6.ucPostDiv = post_div;
+ args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
+ args.v6.ucTransmitterID = encoder_id;
+ args.v6.ucEncoderMode = encoder_mode;
+ args.v6.ucPpll = pll_id;
+ break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
return;
@@ -1377,7 +1401,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
rdev->clock.default_dispclk);
if (ss_enabled)
atombios_crtc_program_ss(crtc, ATOM_DISABLE,
ATOM_DCPLL, &ss);
- atombios_crtc_set_dcpll(crtc);
+ /* XXX: DCE5, make sure voltage, dispclk is high enough */
+ atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
if (ss_enabled)
atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL,
&ss);
}
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index e4f7e3e..11573d0 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1086,6 +1086,7 @@ union firmware_info {
ATOM_FIRMWARE_INFO_V1_3 info_13;
ATOM_FIRMWARE_INFO_V1_4 info_14;
ATOM_FIRMWARE_INFO_V2_1 info_21;
+ ATOM_FIRMWARE_INFO_V2_2 info_22;
};
bool radeon_atom_get_clock_info(struct drm_device *dev)
@@ -1160,8 +1161,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
*p2pll = *p1pll;
/* system clock */
- spll->reference_freq =
- le16_to_cpu(firmware_info->info.usReferenceClock);
+ if (ASIC_IS_DCE4(rdev))
+ spll->reference_freq =
+
le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
+ else
+ spll->reference_freq =
+
le16_to_cpu(firmware_info->info.usReferenceClock);
spll->reference_div = 0;
spll->pll_out_min =
@@ -1183,8 +1188,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
/* memory clock */
- mpll->refere
[PATCH 06/25] drm/radeon/kms: DCE5 atom spread spectrum updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index b3e5e75..b0ab185 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -403,6 +403,7 @@ union atom_enable_ss {
ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
+ ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
};
static void atombios_crtc_program_ss(struct drm_crtc *crtc,
@@ -417,7 +418,30 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
memset(&args, 0, sizeof(args));
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ args.v3.usSpreadSpectrumAmountFrac = 0;
+ args.v3.ucSpreadSpectrumType = ss->type;
+ switch (pll_id) {
+ case ATOM_PPLL1:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_P1PLL;
+ args.v3.usSpreadSpectrumAmount = ss->amount;
+ args.v3.usSpreadSpectrumStep = ss->step;
+ break;
+ case ATOM_PPLL2:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_P2PLL;
+ args.v3.usSpreadSpectrumAmount = ss->amount;
+ args.v3.usSpreadSpectrumStep = ss->step;
+ break;
+ case ATOM_DCPLL:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_DCPLL;
+ args.v3.usSpreadSpectrumAmount = 0;
+ args.v3.usSpreadSpectrumStep = 0;
+ break;
+ case ATOM_PPLL_INVALID:
+ return;
+ }
+ args.v2.ucEnable = enable;
+ } else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage =
cpu_to_le16(ss->percentage);
args.v2.ucSpreadSpectrumType = ss->type;
switch (pll_id) {
--
1.7.1.1
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[PATCH 07/25] drm/radeon/kms: DCE5 atom transmitter control updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 19 ++-
1 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index c83ad89..76835b0 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -712,7 +712,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
* - 2 DIG encoder blocks.
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
*
- * DCE 4.0
+ * DCE 4.0/5.0
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
* Supports up to 6 digital outputs
* - 6 DIG encoder blocks.
@@ -829,6 +829,7 @@ union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
};
void
@@ -923,10 +924,18 @@ atombios_dig_transmitter_setup(struct drm_encoder
*encoder, int action, uint8_t
struct radeon_crtc *radeon_crtc =
to_radeon_crtc(encoder->crtc);
pll_id = radeon_crtc->pll_id;
}
- if (is_dp && rdev->clock.dp_extclk)
- args.v3.acConfig.ucRefClkSource = 2; /* external src */
- else
- args.v3.acConfig.ucRefClkSource = pll_id;
+
+ if (ASIC_IS_DCE5(rdev)) {
+ if (is_dp && rdev->clock.dp_extclk)
+ args.v4.acConfig.ucRefClkSource = 3; /*
external src */
+ else
+ args.v4.acConfig.ucRefClkSource = pll_id;
+ } else {
+ if (is_dp && rdev->clock.dp_extclk)
+ args.v3.acConfig.ucRefClkSource = 2; /*
external src */
+ else
+ args.v3.acConfig.ucRefClkSource = pll_id;
+ }
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
--
1.7.1.1
___
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[PATCH 08/25] drm/radeon/kms: DCE5 atom dig encoder updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 31 +
1 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 76835b0..989ba26 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -743,6 +743,7 @@ union dig_encoder_control {
DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
+ DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
};
void
@@ -758,6 +759,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int
action)
uint8_t frev, crev;
int dp_clock = 0;
int dp_lane_count = 0;
+ int hpd_id = RADEON_HPD_NONE;
if (connector) {
struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
@@ -766,6 +768,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int
action)
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
+ hpd_id = radeon_connector->hpd.hpd;
}
/* no dig encoder assigned */
@@ -790,19 +793,36 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder,
int action)
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
- if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
- if (dp_clock == 27)
- args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
+ (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
args.v1.ucLaneNum = dp_lane_count;
- } else if (radeon_encoder->pixel_clock > 165000)
+ else if (radeon_encoder->pixel_clock > 165000)
args.v1.ucLaneNum = 8;
else
args.v1.ucLaneNum = 4;
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
+ (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
+ if (dp_clock == 27)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
+ else if (dp_clock == 54)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
+ }
+ args.v4.acConfig.ucDigSel = dig->dig_encoder;
+ args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ if (hpd_id == RADEON_HPD_NONE)
+ args.v4.ucHPD_ID = 0;
+ else
+ args.v4.ucHPD_ID = hpd_id + 1;
+ } else if (ASIC_IS_DCE4(rdev)) {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) &&
(dp_clock == 27))
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
args.v3.acConfig.ucDigSel = dig->dig_encoder;
args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
} else {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) &&
(dp_clock == 27))
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
@@ -1538,6 +1558,7 @@ static int radeon_atom_pick_dig_encoder(struct
drm_encoder *encoder)
struct radeon_encoder_atom_dig *dig;
uint32_t dig_enc_in_use = 0;
+ /* DCE4/5 */
if (ASIC_IS_DCE4(rdev)) {
dig = radeon_encoder->enc_priv;
if (ASIC_IS_DCE41(rdev)) {
--
1.7.1.1
___
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[PATCH 09/25] drm/radeon/kms: dac dpms updates for DCE5
The DAC1OutputControl table was removed for DCE5.
DAC1EncoderControl now handles everything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 28 ++--
1 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 989ba26..2e1d720 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1227,6 +1227,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
int index = 0;
bool is_dig = false;
+ bool is_dce5_dac = false;
memset(&args, 0, sizeof(args));
@@ -1265,12 +1266,16 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
- index = GetIndexIntoMasterTable(COMMAND,
TV1OutputControl);
- else if (radeon_encoder->active_device &
(ATOM_DEVICE_CV_SUPPORT))
- index = GetIndexIntoMasterTable(COMMAND,
CV1OutputControl);
- else
- index = GetIndexIntoMasterTable(COMMAND,
DAC1OutputControl);
+ if (ASIC_IS_DCE5(rdev))
+ is_dce5_dac = true;
+ else {
+ if (radeon_encoder->active_device &
(ATOM_DEVICE_TV_SUPPORT))
+ index = GetIndexIntoMasterTable(COMMAND,
TV1OutputControl);
+ else if (radeon_encoder->active_device &
(ATOM_DEVICE_CV_SUPPORT))
+ index = GetIndexIntoMasterTable(COMMAND,
CV1OutputControl);
+ else
+ index = GetIndexIntoMasterTable(COMMAND,
DAC1OutputControl);
+ }
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
@@ -1329,6 +1334,17 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
atombios_dig_transmitter_setup(encoder,
ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
break;
}
+ } else if (is_dce5_dac) {
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ atombios_dac_setup(encoder, ATOM_ENABLE);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ atombios_dac_setup(encoder, ATOM_DISABLE);
+ break;
+ }
} else {
switch (mode) {
case DRM_MODE_DPMS_ON:
--
1.7.1.1
___
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[PATCH 10/25] drm/radeon/kms: dvo dpms updates for DCE5
The DVOOutputControl table was removed for DCE5.
DVOEncoderControl now handles everything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 2e1d720..3866c64 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1228,6 +1228,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
int index = 0;
bool is_dig = false;
bool is_dce5_dac = false;
+ bool is_dce5_dvo = false;
memset(&args, 0, sizeof(args));
@@ -1250,7 +1251,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
- if (ASIC_IS_DCE3(rdev))
+ if (ASIC_IS_DCE5(rdev))
+ is_dce5_dvo = true;
+ else if (ASIC_IS_DCE3(rdev))
is_dig = true;
else
index = GetIndexIntoMasterTable(COMMAND,
DVOOutputControl);
@@ -1345,6 +1348,17 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
atombios_dac_setup(encoder, ATOM_DISABLE);
break;
}
+ } else if (is_dce5_dvo) {
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ atombios_dvo_setup(encoder, ATOM_ENABLE);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ atombios_dvo_setup(encoder, ATOM_DISABLE);
+ break;
+ }
} else {
switch (mode) {
case DRM_MODE_DPMS_ON:
--
1.7.1.1
___
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[PATCH 11/25] drm/radeon/kms: parse DCE5 encoder caps when setting up encoders
Needed to tell which DIG encoders are HBR2 capable for DP 1.2.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c | 44 +++--
drivers/gpu/drm/radeon/radeon_encoders.c |6 +++-
drivers/gpu/drm/radeon/radeon_mode.h |1 +
3 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 11573d0..a2dfe25 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -37,7 +37,7 @@ radeon_get_encoder_enum(struct drm_device *dev, uint32_t
supported_device,
extern void radeon_link_encoder_connector(struct drm_device *dev);
extern void
radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
- uint32_t supported_device);
+ uint32_t supported_device, u16 caps);
/* from radeon_connector.c */
extern void
@@ -537,6 +537,7 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
u16 size, data_offset;
u8 frev, crev;
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+ ATOM_ENCODER_OBJECT_TABLE *enc_obj;
ATOM_OBJECT_TABLE *router_obj;
ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
ATOM_OBJECT_HEADER *obj_header;
@@ -561,6 +562,9 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
(ctx->bios + data_offset +
le16_to_cpu(obj_header->usConnectorObjectTableOffset));
+ enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
+ (ctx->bios + data_offset +
+le16_to_cpu(obj_header->usEncoderObjectTableOffset));
router_obj = (ATOM_OBJECT_TABLE *)
(ctx->bios + data_offset +
le16_to_cpu(obj_header->usRouterObjectTableOffset));
@@ -666,14 +670,35 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER)
{
- u16 encoder_obj =
le16_to_cpu(path->usGraphicObjIds[j]);
-
- radeon_add_atom_encoder(dev,
- encoder_obj,
- le16_to_cpu
- (path->
-usDeviceTag));
+ for (k = 0; k <
enc_obj->ucNumberOfObjects; k++) {
+ u16 encoder_obj =
le16_to_cpu(enc_obj->asObjects[k].usObjectID);
+ if
(le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
+
ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
+ (ctx->bios +
data_offset +
+
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
+ ATOM_ENCODER_CAP_RECORD
*cap_record;
+ u16 caps = 0;
+ while
(record->ucRecordType > 0 &&
+
record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
+ switch
(record->ucRecordType) {
+ case
ATOM_ENCODER_CAP_RECORD_TYPE:
+
cap_record =(ATOM_ENCODER_CAP_RECORD *)
+
record;
+ caps =
le16_to_cpu(cap_record->usEncoderCap);
+ break;
+ }
+ record =
(ATOM_COMMON_RECORD_HEADER *)
+ ((char
*)record + record->ucRecordSize);
+ }
+
radeon_add_atom_encoder(dev,
+
encoder_obj,
+
le16_to_cpu
+
(path->
+
[PATCH 12/25] drm/radeon/kms: handle NI thermal controller
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_atombios.c |6 ++
drivers/gpu/drm/radeon/radeon_pm.c |1 +
3 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 73730fd..5598f95 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -739,6 +739,7 @@ enum radeon_int_thermal_type {
THERMAL_TYPE_RV770,
THERMAL_TYPE_EVERGREEN,
THERMAL_TYPE_SUMO,
+ THERMAL_TYPE_NI,
};
struct radeon_voltage {
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index a2dfe25..03f1c9a 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1891,6 +1891,7 @@ static const char *pp_lib_thermal_controller_names[] = {
"Evergreen",
"emc2103",
"Sumo",
+ "Northern Islands",
};
union power_info {
@@ -2154,6 +2155,11 @@ static void
radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
+ } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_NISLANDS) {
+ DRM_INFO("Internal thermal controller %s fan control\n",
+(controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
+ rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
} else if ((controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
(controller->ucType ==
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 0afd26c..7ad2e1a 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -440,6 +440,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
temp = rv770_get_temp(rdev);
break;
case THERMAL_TYPE_EVERGREEN:
+ case THERMAL_TYPE_NI:
temp = evergreen_get_temp(rdev);
break;
case THERMAL_TYPE_SUMO:
--
1.7.1.1
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[PATCH 13/25] drm/radeon/kms: add disabled vbios accessor for NI asics
Some systems disable the vbios on secondary cards or cards that
have been posted. This code re-enabled the vbios so the driver
can load it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_bios.c | 41 ++
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c
b/drivers/gpu/drm/radeon/radeon_bios.c
index 8f2c7b5..1aba85c 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -131,6 +131,45 @@ static bool radeon_atrm_get_bios(struct radeon_device
*rdev)
return true;
}
+static bool ni_read_disabled_bios(struct radeon_device *rdev)
+{
+ u32 bus_cntl;
+ u32 d1vga_control;
+ u32 d2vga_control;
+ u32 vga_render_control;
+ u32 rom_cntl;
+ bool r;
+
+ bus_cntl = RREG32(R600_BUS_CNTL);
+ d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
+ d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
+ vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
+ rom_cntl = RREG32(R600_ROM_CNTL);
+
+ /* enable the rom */
+ WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
+ /* Disable VGA mode */
+ WREG32(AVIVO_D1VGA_CONTROL,
+ (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+ AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+ WREG32(AVIVO_D2VGA_CONTROL,
+ (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+ AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+ WREG32(AVIVO_VGA_RENDER_CONTROL,
+ (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+ WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
+
+ r = radeon_read_bios(rdev);
+
+ /* restore regs */
+ WREG32(R600_BUS_CNTL, bus_cntl);
+ WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
+ WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
+ WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+ WREG32(R600_ROM_CNTL, rom_cntl);
+ return r;
+}
+
static bool r700_read_disabled_bios(struct radeon_device *rdev)
{
uint32_t viph_control;
@@ -416,6 +455,8 @@ static bool radeon_read_disabled_bios(struct radeon_device
*rdev)
{
if (rdev->flags & RADEON_IS_IGP)
return igp_read_bios_from_vram(rdev);
+ else if (rdev->family >= CHIP_BARTS)
+ return ni_read_disabled_bios(rdev);
else if (rdev->family >= CHIP_RV770)
return r700_read_disabled_bios(rdev);
else if (rdev->family >= CHIP_R600)
--
1.7.1.1
___
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[PATCH 14/25] drm/radeon/kms: fill gpu init for NI asics
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c | 71
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 9c990c3..6a73867 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1384,11 +1384,14 @@ static u32
evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
case CHIP_CEDAR:
case CHIP_REDWOOD:
case CHIP_PALM:
+ case CHIP_TURKS:
+ case CHIP_CAICOS:
force_no_swizzle = false;
break;
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
case CHIP_JUNIPER:
+ case CHIP_BARTS:
default:
force_no_swizzle = true;
break;
@@ -1502,6 +1505,7 @@ static void evergreen_program_channel_remap(struct
radeon_device *rdev)
switch (rdev->family) {
case CHIP_HEMLOCK:
case CHIP_CYPRESS:
+ case CHIP_BARTS:
tcp_chan_steer_lo = 0x54763210;
tcp_chan_steer_hi = 0xba98;
break;
@@ -1509,6 +1513,8 @@ static void evergreen_program_channel_remap(struct
radeon_device *rdev)
case CHIP_REDWOOD:
case CHIP_CEDAR:
case CHIP_PALM:
+ case CHIP_TURKS:
+ case CHIP_CAICOS:
default:
tcp_chan_steer_lo = 0x76543210;
tcp_chan_steer_hi = 0xba98;
@@ -1652,6 +1658,69 @@ static void evergreen_gpu_init(struct radeon_device
*rdev)
rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
break;
+ case CHIP_BARTS:
+ rdev->config.evergreen.num_ses = 2;
+ rdev->config.evergreen.max_pipes = 4;
+ rdev->config.evergreen.max_tile_pipes = 8;
+ rdev->config.evergreen.max_simds = 7;
+ rdev->config.evergreen.max_backends = 4 *
rdev->config.evergreen.num_ses;
+ rdev->config.evergreen.max_gprs = 256;
+ rdev->config.evergreen.max_threads = 248;
+ rdev->config.evergreen.max_gs_threads = 32;
+ rdev->config.evergreen.max_stack_entries = 512;
+ rdev->config.evergreen.sx_num_of_sets = 4;
+ rdev->config.evergreen.sx_max_export_size = 256;
+ rdev->config.evergreen.sx_max_export_pos_size = 64;
+ rdev->config.evergreen.sx_max_export_smx_size = 192;
+ rdev->config.evergreen.max_hw_contexts = 8;
+ rdev->config.evergreen.sq_num_cf_insts = 2;
+
+ rdev->config.evergreen.sc_prim_fifo_size = 0x100;
+ rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+ break;
+ case CHIP_TURKS:
+ rdev->config.evergreen.num_ses = 1;
+ rdev->config.evergreen.max_pipes = 4;
+ rdev->config.evergreen.max_tile_pipes = 4;
+ rdev->config.evergreen.max_simds = 6;
+ rdev->config.evergreen.max_backends = 2 *
rdev->config.evergreen.num_ses;
+ rdev->config.evergreen.max_gprs = 256;
+ rdev->config.evergreen.max_threads = 248;
+ rdev->config.evergreen.max_gs_threads = 32;
+ rdev->config.evergreen.max_stack_entries = 256;
+ rdev->config.evergreen.sx_num_of_sets = 4;
+ rdev->config.evergreen.sx_max_export_size = 256;
+ rdev->config.evergreen.sx_max_export_pos_size = 64;
+ rdev->config.evergreen.sx_max_export_smx_size = 192;
+ rdev->config.evergreen.max_hw_contexts = 8;
+ rdev->config.evergreen.sq_num_cf_insts = 2;
+
+ rdev->config.evergreen.sc_prim_fifo_size = 0x100;
+ rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+ break;
+ case CHIP_CAICOS:
+ rdev->config.evergreen.num_ses = 1;
+ rdev->config.evergreen.max_pipes = 4;
+ rdev->config.evergreen.max_tile_pipes = 2;
+ rdev->config.evergreen.max_simds = 2;
+ rdev->config.evergreen.max_backends = 1 *
rdev->config.evergreen.num_ses;
+ rdev->config.evergreen.max_gprs = 256;
+ rdev->config.evergreen.max_threads = 192;
+ rdev->config.evergreen.max_gs_threads = 16;
+ rdev->config.evergreen.max_stack_entries = 256;
+ rdev->config.evergreen.sx_num_of_sets = 4;
+ rdev->config.evergreen.sx_max_export_size = 128;
+ rdev->config.evergreen.sx_max_export_pos_size = 32;
+ rdev->config.evergreen.sx_max_export_smx_size = 96;
+ rdev->config.evergreen.ma
[PATCH 15/25] drm/radeon/kms: add backend map workaround for barts
Same as Cypress.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 6a73867..c40e5ad 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1862,6 +1862,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
switch (rdev->family) {
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
+ case CHIP_BARTS:
gb_backend_map = 0x66442200;
break;
case CHIP_JUNIPER:
--
1.7.1.1
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[PATCH 16/25] drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5
NI chips no longer load the MC ucode in the asic_init sequence so
the asic comes up in a basic mode with low engine/memory clocks and
a voltage. Once the MC ucode is loaded by the driver the card
can be programmed to it's proper default clocks and voltage. As such
the default clocks in the firmware info table as the post clocks, not
the default running clocks. Track the default post clocks and default
running clocks separately to handle this.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |3 +++
drivers/gpu/drm/radeon/radeon_atombios.c | 25 -
drivers/gpu/drm/radeon/radeon_pm.c | 18 ++
3 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5598f95..8c62b2f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -823,6 +823,9 @@ struct radeon_pm {
u32 current_sclk;
u32 current_mclk;
u32 current_vddc;
+ u32 default_sclk;
+ u32 default_mclk;
+ u32 default_vddc;
struct radeon_i2c_chan *i2c_bus;
/* selected pm method */
enum radeon_pm_method pm_method;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 03f1c9a..1573202 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2249,15 +2249,22 @@ static void
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
rdev->pm.default_power_state_index = state_index;
rdev->pm.power_state[state_index].default_clock_mode =
&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
- /* patch the table values with the default slck/mclk from
firmware info */
- for (j = 0; j < mode_index; j++) {
- rdev->pm.power_state[state_index].clock_info[j].mclk =
- rdev->clock.default_mclk;
- rdev->pm.power_state[state_index].clock_info[j].sclk =
- rdev->clock.default_sclk;
- if (vddc)
-
rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
- vddc;
+ if (ASIC_IS_DCE5(rdev)) {
+ /* NI chips post without MC ucode, so default clocks
are strobe mode only */
+ rdev->pm.default_sclk =
rdev->pm.power_state[state_index].clock_info[0].sclk;
+ rdev->pm.default_mclk =
rdev->pm.power_state[state_index].clock_info[0].mclk;
+ rdev->pm.default_vddc =
rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
+ } else {
+ /* patch the table values with the default slck/mclk
from firmware info */
+ for (j = 0; j < mode_index; j++) {
+
rdev->pm.power_state[state_index].clock_info[j].mclk =
+ rdev->clock.default_mclk;
+
rdev->pm.power_state[state_index].clock_info[j].sclk =
+ rdev->clock.default_sclk;
+ if (vddc)
+
rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+ vddc;
+ }
}
}
}
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 7ad2e1a..9052d1e 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -167,13 +167,13 @@ static void radeon_set_power_state(struct radeon_device
*rdev)
if (radeon_gui_idle(rdev)) {
sclk =
rdev->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk;
- if (sclk > rdev->clock.default_sclk)
- sclk = rdev->clock.default_sclk;
+ if (sclk > rdev->pm.default_sclk)
+ sclk = rdev->pm.default_sclk;
mclk =
rdev->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk;
- if (mclk > rdev->clock.default_mclk)
- mclk = rdev->clock.default_mclk;
+ if (mclk > rdev->pm.default_mclk)
+ mclk = rdev->pm.default_mclk;
/* upvolt before raising clocks, downvolt after lowering clocks
*/
if (sclk < rdev->pm.current_sclk)
@@ -534,8 +534,8 @@ void radeon_pm_resume(struct radeon_device *rdev)
[PATCH 17/25] drm/radeon/kms: always use writeback/events for fences on NI
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_device.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index e353430..26091d6 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -228,6 +228,11 @@ int radeon_wb_init(struct radeon_device *rdev)
rdev->wb.use_event = true;
}
}
+ /* always use writeback/events on NI */
+ if (ASIC_IS_DCE5(rdev)) {
+ rdev->wb.enabled = true;
+ rdev->wb.use_event = true;
+ }
dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
--
1.7.1.1
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[PATCH 18/25] drm/radeon/kms: add bo blit support for NI
Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen_blit_kms.c | 69 ++- 1 files changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index 2ccd1f0..b758dc7 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c @@ -148,7 +148,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); if ((rdev->family == CHIP_CEDAR) || - (rdev->family == CHIP_PALM)) + (rdev->family == CHIP_PALM) || + (rdev->family == CHIP_CAICOS)) cp_set_surface_sync(rdev, PACKET3_TC_ACTION_ENA, 48, gpu_addr); else @@ -353,10 +354,74 @@ set_default_state(struct radeon_device *rdev) num_hs_stack_entries = 42; num_ls_stack_entries = 42; break; + case CHIP_BARTS: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 85; + num_vs_stack_entries = 85; + num_gs_stack_entries = 85; + num_es_stack_entries = 85; + num_hs_stack_entries = 85; + num_ls_stack_entries = 85; + break; + case CHIP_TURKS: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; + case CHIP_CAICOS: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 10; + num_gs_threads = 10; + num_es_threads = 10; + num_hs_threads = 10; + num_ls_threads = 10; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; } if ((rdev->family == CHIP_CEDAR) || - (rdev->family == CHIP_PALM)) + (rdev->family == CHIP_PALM) || + (rdev->family == CHIP_CAICOS)) sq_config = 0; else sq_config = VC_ENABLE; -- 1.7.1.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 19/25] drm/radeon/kms: add ni_reg.h
This adds some new NI (northern islands) specific display register defines. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni_reg.h | 86 +++ drivers/gpu/drm/radeon/radeon_reg.h |1 + 2 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 drivers/gpu/drm/radeon/ni_reg.h diff --git a/drivers/gpu/drm/radeon/ni_reg.h b/drivers/gpu/drm/radeon/ni_reg.h new file mode 100644 index 000..5db7b7d --- /dev/null +++ b/drivers/gpu/drm/radeon/ni_reg.h @@ -0,0 +1,86 @@ +/* + * Copyright 2010 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef __NI_REG_H__ +#define __NI_REG_H__ + +/* northern islands - DCE5 */ + +#define NI_INPUT_GAMMA_CONTROL 0x6840 +# define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) +# define NI_INPUT_GAMMA_USE_LUT 0 +# define NI_INPUT_GAMMA_BYPASS 1 +# define NI_INPUT_GAMMA_SRGB_24 2 +# define NI_INPUT_GAMMA_XVYCC_2223 +# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) + +#define NI_PRESCALE_GRPH_CONTROL 0x68b4 +# define NI_GRPH_PRESCALE_BYPASS (1 << 4) + +#define NI_PRESCALE_OVL_CONTROL0x68c4 +# define NI_OVL_PRESCALE_BYPASS (1 << 4) + +#define NI_INPUT_CSC_CONTROL 0x68d4 +# define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) +# define NI_INPUT_CSC_BYPASS 0 +# define NI_INPUT_CSC_PROG_COEFF 1 +# define NI_INPUT_CSC_PROG_SHARED_MATRIXA2 +# define NI_INPUT_CSC_OVL_MODE(x)(((x) & 0x3) << 4) + +#define NI_OUTPUT_CSC_CONTROL 0x68f0 +# define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) +# define NI_OUTPUT_CSC_BYPASS0 +# define NI_OUTPUT_CSC_TV_RGB1 +# define NI_OUTPUT_CSC_YCBCR_601 2 +# define NI_OUTPUT_CSC_YCBCR_709 3 +# define NI_OUTPUT_CSC_PROG_COEFF4 +# define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5 +# define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) + +#define NI_DEGAMMA_CONTROL 0x6960 +# define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) +# define NI_DEGAMMA_BYPASS 0 +# define NI_DEGAMMA_SRGB_24 1 +# define NI_DEGAMMA_XVYCC_2222 +# define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) +# define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) +# define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) + +#define NI_GAMUT_REMAP_CONTROL 0x6964 +# define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) +# define NI_GAMUT_REMAP_BYPASS 0 +# define NI_GAMUT_REMAP_PROG_COEFF 1 +# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2 +# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3 +# define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) + +#define NI_REGAMMA_CONTROL 0x6a80 +# define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) +# define NI_REGAMMA_BYPASS 0 +# define NI_REGAMMA_SRGB_24 1 +# define NI_REGAMMA_XVYCC_2222 +# define NI_REGAMMA_PROG_A 3 +# define NI_REGAMMA_PROG_B 4 +# define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) + +#endif diff --git a/drivers/gpu/drm/radeon/radeon_r
[PATCH 20/25] drm/radeon/kms: add support for DCE5 display LUTs
The hardware supports advanced user defined color management
but at the moment, there is no infrastructure in place to take
advantage of it so for now we just support the legacy LUTs.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_display.c | 68 +-
1 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
b/drivers/gpu/drm/radeon/radeon_display.c
index 30d867c..d26dabf 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -68,7 +68,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
radeon_crtc->crtc_id);
}
-static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
+static void dce4_crtc_load_lut(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
@@ -98,6 +98,66 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
}
}
+static void dce5_crtc_load_lut(struct drm_crtc *crtc)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ int i;
+
+ DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
+
+ WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
+ (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
+ NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
+ WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
+ NI_GRPH_PRESCALE_BYPASS);
+ WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
+ NI_OVL_PRESCALE_BYPASS);
+ WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
+ (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
+ NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
+
+ WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
+
+ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset,
0);
+ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset,
0);
+ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset,
0x);
+ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset,
0x);
+ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset,
0x);
+
+ WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
+ WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset,
0x0007);
+
+ WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
+ for (i = 0; i < 256; i++) {
+ WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
+ (radeon_crtc->lut_r[i] << 20) |
+ (radeon_crtc->lut_g[i] << 10) |
+ (radeon_crtc->lut_b[i] << 0));
+ }
+
+ WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
+ (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
+ NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
+ NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
+ NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
+ WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
+ (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
+ NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
+ WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
+ (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
+ NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
+ WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
+ (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
+ NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
+ /* XXX match this to the depth of the crtc fmt block, move to modeset?
*/
+ WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
+
+}
+
static void legacy_crtc_load_lut(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -130,8 +190,10 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
if (!crtc->enabled)
return;
- if (ASIC_IS_DCE4(rdev))
- evergreen_crtc_load_lut(crtc);
+ if (ASIC_IS_DCE5(rdev))
+ dce5_crtc_load_lut(crtc);
+ else if (ASIC_IS_DCE4(rdev))
+ dce4_crtc_load_lut(crtc);
else if (ASIC_IS_AVIVO(rdev))
avivo_crtc_load_lut(crtc);
else
--
1.7.1.1
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[PATCH 21/25] drm/radeon/kms: add ucode loader for NI
The MC ucode is no longer loaded by the vbios
tables as on previous asics. It now must be loaded
by the driver.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile|2 +-
drivers/gpu/drm/radeon/evergreen.c | 21 ++-
drivers/gpu/drm/radeon/ni.c| 316
drivers/gpu/drm/radeon/nid.h | 41 +
drivers/gpu/drm/radeon/radeon.h|4 +
5 files changed, 380 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/ni.c
create mode 100644 drivers/gpu/drm/radeon/nid.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index e97e6f8..e47eecf 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
- radeon_trace_points.o
+ radeon_trace_points.o ni.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index c40e5ad..4fb2101 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2855,12 +2855,27 @@ static int evergreen_startup(struct radeon_device *rdev)
/* enable pcie gen2 link */
evergreen_pcie_gen2_enable(rdev);
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
- r = r600_init_microcode(rdev);
+ if (ASIC_IS_DCE5(rdev)) {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
!rdev->mc_fw) {
+ r = ni_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ r = btc_mc_load_microcode(rdev);
if (r) {
- DRM_ERROR("Failed to load firmware!\n");
+ DRM_ERROR("Failed to load MC firmware!\n");
return r;
}
+ } else {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+ r = r600_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
}
evergreen_mc_program(rdev);
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
new file mode 100644
index 000..5e0bef8
--- /dev/null
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright 2010 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#include
+#include
+#include
+#include "drmP.h"
+#include "radeon.h"
+#include "radeon_asic.h"
+#include "radeon_drm.h"
+#include "nid.h"
+#include "atom.h"
+#include "ni_reg.h"
+
+#define EVERGREEN_PFP_UCODE_SIZE 1120
+#define EVERGREEN_PM4_UCODE_SIZE 1376
+#define EVERGREEN_RLC_UCODE_SIZE 768
+#define BTC_MC_UCODE_SIZE 6024
+
+/* Firmware Names */
+MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
+MODULE_FIRMWARE("radeon/BARTS_me.bin");
+MODULE_FIRMWARE("radeon/BARTS_mc.bin");
+MODULE_FIRMWARE("radeon/BTC_rlc.bin");
+MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
+MODULE_FIRMWARE("radeon/TURKS_me.bin");
+MODULE_FIRMWARE("radeon/TURKS_mc.bin");
+MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
+MODULE_FIRMWARE("radeon/CAICOS_me.bin");
+MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
+
+#define BTC_IO_MC_REGS_SIZE 29
+
+static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
+ {0x0077, 0xff010100},
+ {0x0078, 0x
[PATCH 22/25] drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init
The vbios only partially initializes the memory controller on
NI, so now we need to load the MC ucode in the driver and set
the default clocks once the ucode is loaded.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_pm.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 9052d1e..3b1b2bf 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -530,6 +530,15 @@ void radeon_pm_suspend(struct radeon_device *rdev)
void radeon_pm_resume(struct radeon_device *rdev)
{
+ /* set up the default clocks if the MC ucode is loaded */
+ if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
+ if (rdev->pm.default_vddc)
+ radeon_atom_set_voltage(rdev, rdev->pm.default_vddc);
+ if (rdev->pm.default_sclk)
+ radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
+ if (rdev->pm.default_mclk)
+ radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
+ }
/* asic init will reset the default power state */
mutex_lock(&rdev->pm.mutex);
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
@@ -571,6 +580,15 @@ int radeon_pm_init(struct radeon_device *rdev)
radeon_combios_get_power_modes(rdev);
radeon_pm_print_states(rdev);
radeon_pm_init_profile(rdev);
+ /* set up the default clocks if the MC ucode is loaded */
+ if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
+ if (rdev->pm.default_vddc)
+ radeon_atom_set_voltage(rdev,
rdev->pm.default_vddc);
+ if (rdev->pm.default_sclk)
+ radeon_set_engine_clock(rdev,
rdev->pm.default_sclk);
+ if (rdev->pm.default_mclk)
+ radeon_set_memory_clock(rdev,
rdev->pm.default_mclk);
+ }
}
/* set up the internal thermal sensor if applicable */
--
1.7.1.1
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[PATCH 23/25] drm/radeon/kms: add radeon_asic struct for NI asics
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 51 ++
1 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 53c6240..3a1b161 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -836,6 +836,52 @@ static struct radeon_asic sumo_asic = {
.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
};
+static struct radeon_asic btc_asic = {
+ .init = &evergreen_init,
+ .fini = &evergreen_fini,
+ .suspend = &evergreen_suspend,
+ .resume = &evergreen_resume,
+ .cp_commit = &r600_cp_commit,
+ .gpu_is_lockup = &evergreen_gpu_is_lockup,
+ .asic_reset = &evergreen_asic_reset,
+ .vga_set_state = &r600_vga_set_state,
+ .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
+ .gart_set_page = &rs600_gart_set_page,
+ .ring_test = &r600_ring_test,
+ .ring_ib_execute = &r600_ring_ib_execute,
+ .irq_set = &evergreen_irq_set,
+ .irq_process = &evergreen_irq_process,
+ .get_vblank_counter = &evergreen_get_vblank_counter,
+ .fence_ring_emit = &r600_fence_ring_emit,
+ .cs_parse = &evergreen_cs_parse,
+ .copy_blit = &evergreen_copy_blit,
+ .copy_dma = &evergreen_copy_blit,
+ .copy = &evergreen_copy_blit,
+ .get_engine_clock = &radeon_atom_get_engine_clock,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .get_memory_clock = &radeon_atom_get_memory_clock,
+ .set_memory_clock = &radeon_atom_set_memory_clock,
+ .get_pcie_lanes = NULL,
+ .set_pcie_lanes = NULL,
+ .set_clock_gating = NULL,
+ .set_surface_reg = r600_set_surface_reg,
+ .clear_surface_reg = r600_clear_surface_reg,
+ .bandwidth_update = &evergreen_bandwidth_update,
+ .hpd_init = &evergreen_hpd_init,
+ .hpd_fini = &evergreen_hpd_fini,
+ .hpd_sense = &evergreen_hpd_sense,
+ .hpd_set_polarity = &evergreen_hpd_set_polarity,
+ .gui_idle = &r600_gui_idle,
+ .pm_misc = &evergreen_pm_misc,
+ .pm_prepare = &evergreen_pm_prepare,
+ .pm_finish = &evergreen_pm_finish,
+ .pm_init_profile = &r600_pm_init_profile,
+ .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
+ .pre_page_flip = &evergreen_pre_page_flip,
+ .page_flip = &evergreen_page_flip,
+ .post_page_flip = &evergreen_post_page_flip,
+};
+
int radeon_asic_init(struct radeon_device *rdev)
{
radeon_register_accessor_init(rdev);
@@ -923,6 +969,11 @@ int radeon_asic_init(struct radeon_device *rdev)
case CHIP_PALM:
rdev->asic = &sumo_asic;
break;
+ case CHIP_BARTS:
+ case CHIP_TURKS:
+ case CHIP_CAICOS:
+ rdev->asic = &btc_asic;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
1.7.1.1
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[PATCH 24/25] drm/radeon/kms: don't enable pcie gen2 on NI yet
Still needs to be implemented.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 4fb2101..7fe8ebd 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2853,7 +2853,8 @@ static int evergreen_startup(struct radeon_device *rdev)
int r;
/* enable pcie gen2 link */
- evergreen_pcie_gen2_enable(rdev);
+ if (!ASIC_IS_DCE5(rdev))
+ evergreen_pcie_gen2_enable(rdev);
if (ASIC_IS_DCE5(rdev)) {
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
!rdev->mc_fw) {
--
1.7.1.1
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[PATCH 25/25] drm/radeon/kms: add NI pci ids
Signed-off-by: Alex Deucher
---
include/drm/drm_pciids.h | 36
1 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e6b28a3..fe29ae3 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -142,6 +142,42 @@
{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_RV410|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_RV410|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_RV410|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6723, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6724, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6725, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6726, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6727, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6728, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6729, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6738, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6739, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BARTS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6740, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6741, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6742, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6743, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6744, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6745, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6746, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6747, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6748, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6749, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6759, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6760, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6761, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6762, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6763, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6764, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6765, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6766, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
--
1.7.1.1
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[Bug 32888] New: [r600g] GL_EXT_texture_compression_s3tc support
https://bugs.freedesktop.org/show_bug.cgi?id=32888 Summary: [r600g] GL_EXT_texture_compression_s3tc support Product: Mesa Version: git Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: enhancement Priority: medium Component: Drivers/Gallium/r600 AssignedTo: dri-devel@lists.freedesktop.org ReportedBy: v...@vmware.com mesa: 6d9ca78ef7bf831b9b63f4bda68623cbae627508 (master) r600g currently does not support the OpenGL extension GL_EXT_texture_compression_s3tc, whereas r600 classic does. Gallium drivers softpipe, llvmpipe, and r300g currently also support GL_EXT_texture_compression_s3tc. GL_EXT_texture_compression_s3tc is a necessary extension for VMware Workstation and VMware Player to support hardware graphics acceleration in Windows guest operating systems. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 30754] X server crashes with SEGFAULT when using virtualbox on Evergreen
https://bugs.freedesktop.org/show_bug.cgi?id=30754 --- Comment #5 from Frédéric L. W. Meunier 2011-01-06 18:32:52 PST --- After reading some things, I thought that it could be an issue in the kernel, but moving from 2.6.36 to 2.6.37 didn't improve things. And this time, I was able to reproduce it in VirtualBox 4.0 without starting the VM, just going to the settings and changing something. Anyway, this time I used xorg-server 1.9.3 git (20101231), Mesa 7.9 git (20110105) and xf86-video-ati 6.13.99 git (20101217). -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 32889] New: [i915g] SIGSEGV src/gallium/drivers/i915/i915_state_emit.c:414
https://bugs.freedesktop.org/show_bug.cgi?id=32889 Summary: [i915g] SIGSEGV src/gallium/drivers/i915/i915_state_emit.c:414 Product: Mesa Version: git Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: critical Priority: medium Component: Drivers/Gallium/i915g AssignedTo: dri-devel@lists.freedesktop.org ReportedBy: v...@vmware.com mesa: 6d9ca78ef7bf831b9b63f4bda68623cbae627508 (master) chipset: 945GM (Intel GMA 950) system architecture: i686 xserver-xorg-video-intel: 2:2.12.0-1ubuntu5.1 libdrm-intel1: 2.4.21-1ubuntu2.1 kernel version: 2.6.35-24-generic Linux distribution: Ubuntu 10.10 i386 Run piglit fbo-blit-d24s8 test. $ ./bin/fbo-blit-d24s8 -auto Segmentation fault (core dumped) Program terminated with signal 11, Segmentation fault. #0 0x01102b3b in i915_emit_hardware_state (i915=0x8a6e370) at src/gallium/drivers/i915/i915_state_emit.c:414 414 struct i915_texture *tex = i915_texture(cbuf_surface->texture); (gdb) bt #0 0x01102b3b in i915_emit_hardware_state (i915=0x8a6e370) at src/gallium/drivers/i915/i915_state_emit.c:414 #1 0x010fe0e6 in i915_vbuf_render_draw_arrays (render=0x8a84788, start=0, nr=4) at src/gallium/drivers/i915/i915_prim_vbuf.c:516 #2 0x01194f9d in draw_pt_emit_linear (emit=0x8a6ad30, vert_info=0xbff42328, prim_info=0xbff4239c) at src/gallium/auxiliary/draw/draw_pt_emit.c:265 #3 0x0112fc82 in emit (emit=0x8a6ad30, vert_info=0xbff42328, prim_info=0xbff4239c) at src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c:168 #4 0x01130023 in fetch_pipeline_generic (middle=0x8a6acc8, fetch_info=0x0, prim_info=0xbff4239c) at src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c:286 #5 0x01130144 in fetch_pipeline_linear_run (middle=0x8a6acc8, start=0, count=4, prim_flags=0) at src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c:345 #6 0x01135155 in vsplit_segment_simple_linear (vsplit=0x8a7ee30, flags=0, istart=0, icount=4) at src/gallium/auxiliary/draw/draw_pt_vsplit_tmp.h:229 #7 0x011354ee in vsplit_run_linear (frontend=0x8a7ee30, start=0, count=4) at src/gallium/auxiliary/draw/draw_split_tmp.h:61 #8 0x0112d494 in draw_pt_arrays (draw=0x8a69348, prim=6, start=0, count=4) at src/gallium/auxiliary/draw/draw_pt.c:113 #9 0x0112e049 in draw_vbo (draw=0x8a69348, info=0xbff425a4) at src/gallium/auxiliary/draw/draw_pt.c:481 #10 0x010fc5d3 in i915_draw_vbo (pipe=0x8a6e370, info=0xbff425a4) at src/gallium/drivers/i915/i915_context.c:81 #11 0x019d3690 in util_draw_arrays (pipe=0x8a6e370, mode=6, start=0, count=4) at src/gallium/auxiliary/util/u_draw.h:58 #12 0x019d3757 in util_draw_vertex_buffer (pipe=0x8a6e370, vbuf=0x8b17920, offset=0, prim_type=6, num_verts=4, num_attribs=2) at src/gallium/auxiliary/util/u_draw_quad.c:63 #13 0x01952f15 in draw_quad (st=0x8ad80a0, x0=-1, y0=-1, x1=1, y1=1, z=0.54321003, color=0x8a97324) at src/mesa/state_tracker/st_cb_clear.c:175 #14 0x019535be in clear_with_quad (ctx=0x8a96618, color=0 '\000', depth=2 '\002', stencil=4 '\004') at src/mesa/state_tracker/st_cb_clear.c:299 #15 0x01953cfd in st_Clear (ctx=0x8a96618, mask=48) at src/mesa/state_tracker/st_cb_clear.c:530 #16 0x018ddbb0 in _mesa_Clear (mask=1280) at src/mesa/main/clear.c:242 #17 0x0804b907 in run_test () at piglit/tests/fbo/fbo-blit-d24s8.c:179 #18 0x0804bce9 in piglit_display () at piglit/tests/fbo/fbo-blit-d24s8.c:242 #19 0x0804dce3 in display () at piglit/tests/util/piglit-framework.c:52 #20 0x002d2820 in fghRedrawWindow (window=DWARF-2 expression error: DW_OP_reg operations must be used either alone or in conjuction with DW_OP_piece or DW_OP_bit_piece. ) at freeglut_main.c:210 #21 fghcbDisplayWindow (window=DWARF-2 expression error: DW_OP_reg operations must be used either alone or in conjuction with DW_OP_piece or DW_OP_bit_piece. ) at freeglut_main.c:227 #22 0x002d6660 in fgEnumWindows (enumCallback=0x2d2790 , enumerator=0xbff42948) at freeglut_structure.c:394 #23 0x002d2cdb in fghDisplayAll () at freeglut_main.c:249 #24 glutMainLoopEvent () at freeglut_main.c:1450 #25 0x002d3605 in glutMainLoop () at freeglut_main.c:1498 #26 0x0804de8c in main (argc=1, argv=0xbff42bd4) at piglit/tests/util/piglit-framework.c:118 (gdb) frame 0 #0 0x01102b3b in i915_emit_hardware_state (i915=0x8a6e370) at src/gallium/drivers/i915/i915_state_emit.c:414 414 struct i915_texture *tex = i915_texture(cbuf_surface->texture); (gdb) print cbuf_surface $1 = (struct pipe_surface *) 0x0 -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 30754] X server crashes with SEGFAULT when using virtualbox on Evergreen
https://bugs.freedesktop.org/show_bug.cgi?id=30754 Alex Deucher changed: What|Removed |Added Status|NEW |RESOLVED Resolution||DUPLICATE --- Comment #6 from Alex Deucher 2011-01-06 19:21:11 PST --- *** This bug has been marked as a duplicate of bug 32188 *** -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 09/32] drm/radeon: use system_wq instead of dev_priv->wq
On Tue, 2011-01-04 at 19:21 -0500, Alex Deucher wrote: > On Mon, Jan 3, 2011 at 8:49 AM, Tejun Heo wrote: > > With cmwq, there's no reason for radeon to use a dedicated workqueue. > > Drop dev_priv->wq and use system_wq instead. > > > > Because radeon_driver_irq_uninstall_kms() may be called from > > unsleepable context, the work items can't be flushed from there. > > Instead, init and flush from radeon_irq_kms_init/fini(). > > > > While at it, simplify canceling/flushing of rdev->pm.dynpm_idle_work. > > Always initialize and sync cancel instead of being unnecessarily smart > > about it. > > > > Signed-off-by: Tejun Heo > > Cc: David Airlie > > Cc: dri-devel at lists.freedesktop.org > > --- > > Only compile tested. Please feel free to take it into the subsystem > > tree or simply ack - I'll route it through the wq tree. > > Patch looks good to me. I'm not sure what's the best way to send this > upstream. I'm working on some irq changes in the same area now, so > I'd prefer if we pushed it through Dave's tree, but I can handle it > either way. I'll pull it into my tree for merging to Linus. Dave. > > Acked-by: Alex Deucher >
[Regression] [PATCH] intel_crt_detect_ddc() seems to be broken for DVI-I
Hello Since Linux 2.6.36 the digital output on my system (855GME + DVI-I) is not working any longer. The analog output is always activated regardless of the type of monitor attached. The culprit seems to be intel_crt_detect_ddc(), which returns true as soon as an ACK from the EDID device is received. Obviously this approach does not work with DVI-I where the analog and digital outputs share a common DDC bus. The patch below adds an additional check to make sure that there is really an analog device attached (similar to the "Mac mini hack" in intel_sdvo.c) -- next part -- An embedded and charset-unspecified text was scrubbed... Name: intel_crt.c.patch URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20110106/9929e8da/attachment.asc> -- next part -- -- Learn how Oracle Real Application Clusters (RAC) One Node allows customers to consolidate database storage, standardize their database environment, and, should the need arise, upgrade to a full multi-node Oracle RAC database without downtime or disruption http://p.sf.net/sfu/oracle-sfdevnl -- next part -- -- ___ Dri-devel mailing list Dri-devel at lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
[Regression] [PATCH] intel_crt_detect_ddc() seems to be broken for DVI-I
On Thu, 06 Jan 2011 12:11:38 +0100, "David M??ller (ELSOFT AG)" wrote: > The patch below adds an additional check to make sure that there is > really an analog device attached (similar to the "Mac mini hack" in > intel_sdvo.c) Nice patch, thanks. I've applied this to my -fixes queue. -Chris -- Chris Wilson, Intel Open Source Technology Centre -- next part -- -- Learn how Oracle Real Application Clusters (RAC) One Node allows customers to consolidate database storage, standardize their database environment, and, should the need arise, upgrade to a full multi-node Oracle RAC database without downtime or disruption http://p.sf.net/sfu/oracle-sfdevnl -- next part -- -- ___ Dri-devel mailing list Dri-devel at lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
[Bug 32875] New: KWin 4.5.95 (KDE 4.6) draws blank windows when desktop effects are enabled.
https://bugs.freedesktop.org/show_bug.cgi?id=32875 Summary: KWin 4.5.95 (KDE 4.6) draws blank windows when desktop effects are enabled. Product: Mesa Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/r600 AssignedTo: dri-devel at lists.freedesktop.org ReportedBy: oyvinds at everdot.org All windows appear without any content when desktop effects are enabled. It is possible to resize windows to make the content appear, but that snapshot of content is not updated until the window is resized again. Kwin 4.5.95 is the rc2 of the upcoming KDE 4.6. This new kwin appears to work perfectly (after 10 minutes of testing) with r600 classic, so this does appear to be a r600g bug. Old 4.5.x kwin works fine with both. Please let me know if I can probide any additional information which may help resolve this bug. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
Linux 2.6.37
On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote: > > It seems that there is still a regression for intel graphic cards > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. > I can reproduce the problem easily by: > xset dpms force standby; sleep 3s; xset dpms force on > > backlight doesn't get up (there is really dark picture though which > doesn't get brighter by function keys which work normally) after dpms on > until I close and open lid. Hmm. That commit no longer reverts cleanly, so it's not trivial to test whether all those things are exactly the same issue. It's been bisected in the bugzilla entry, but it would be good to verify that yes, reverting it really does fix the issue, and your issue is the exact same one. Chris, any ideas? Linus
Linux 2.6.37
Hi, On Tue 04-01-11 17:15:45, Linus Torvalds wrote: [...] > We did have another revert to fix hopefullythe last "blank screen" > regression on intel graphics. It seems that there is still a regression for intel graphic cards backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. I can reproduce the problem easily by: xset dpms force standby; sleep 3s; xset dpms force on backlight doesn't get up (there is really dark picture though which doesn't get brighter by function keys which work normally) after dpms on until I close and open lid. The problem wasn't present in 2.6.36 $ lspci -vv [...] 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03) (prog-if 00 [VGA controller]) Subsystem: Fujitsu Limited. Device 137a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: Kernel driver in use: i915 [...] -- Michal Hocko L3 team SUSE LINUX s.r.o. Lihovarska 1060/12 190 00 Praha 9 Czech Republic
Linux 2.6.37
Just for reference, my initial report was: https://lkml.org/lkml/2010/11/23/146 On Thu 06-01-11 08:29:22, Linus Torvalds wrote: > On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote: > > > > It seems that there is still a regression for intel graphic cards > > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672. > > I can reproduce the problem easily by: > > xset dpms force standby; sleep 3s; xset dpms force on > > > > backlight doesn't get up (there is really dark picture though which > > doesn't get brighter by function keys which work normally) after dpms on > > until I close and open lid. > > Hmm. That commit no longer reverts cleanly, so it's not trivial to > test whether all those things are exactly the same issue. It's been > bisected in the bugzilla entry, but it would be good to verify that > yes, reverting it really does fix the issue, and your issue is the > exact same one. > > Chris, any ideas? > >Linus -- Michal Hocko L3 team SUSE LINUX s.r.o. Lihovarska 1060/12 190 00 Praha 9 Czech Republic
[PATCH 08/32] drm/nouveau: use system_wq instead of dev_priv->wq
Hello, On Wed, Jan 05, 2011 at 11:16:05AM +1000, Ben Skeggs wrote: > On Wed, 2011-01-05 at 11:07 +1000, Ben Skeggs wrote: > > On Mon, 2011-01-03 at 14:49 +0100, Tejun Heo wrote: > > > With cmwq, there's no reason for nouveau to use a dedicated workqueue. > > > Drop dev_priv->wq and use system_wq instead. > > > > > > Because nouveau_irq_uninstall() may be called from unsleepable > > > context, the work items can't be flushed from there. Instead, init > > > and flush from nouveau_load/unload(). > > Ehh, ok, why not! I'll push this through the nouveau tree, and it'll > > get to Dave from there. > > On second thoughts, this won't apply on top of current nouveau code > that's queued for 2.6.38. Can you rebase on top of Dave's drm-next tree > please. We already missed this merge window, so I'll refresh the patch once the window is closed and resend. Thank you. -- tejun
Linux 2.6.37
On Thu, 6 Jan 2011 08:29:22 -0800, Linus Torvalds wrote:
> On Thu, Jan 6, 2011 at 2:48 AM, Michal Hocko wrote:
> >
> > It seems that there is still a regression for intel graphic cards
> > backlight. One report is https://bugzilla.kernel.org/show_bug.cgi?id=22672.
> > I can reproduce the problem easily by:
> > xset dpms force standby; sleep 3s; xset dpms force on
> >
> > backlight doesn't get up (there is really dark picture though which
> > doesn't get brighter by function keys which work normally) after dpms on
> > until I close and open lid.
>
> Hmm. That commit no longer reverts cleanly, so it's not trivial to
> test whether all those things are exactly the same issue. It's been
> bisected in the bugzilla entry, but it would be good to verify that
> yes, reverting it really does fix the issue, and your issue is the
> exact same one.
>
> Chris, any ideas?
My fear is that some machines have a dependency between the backlight
and panel power status. The patch in question changed the timing between
turning on the panel and adjusting the backlight which would be restore
with:
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index aa23070..0b40b4f 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
*intel_lvds)
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
POSTING_READ(lvds_reg);
+ {
+ u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
+ if (wait_for(I915_READ(reg) & PP_ON, 1000))
+ DRM_ERROR("timed out waiting for panel to power up\n");
+ }
+
intel_panel_set_backlight(dev, dev_priv->backlight_level);
}
--
Chris Wilson, Intel Open Source Technology Centre
[Bug 32634] [r300g, bisected] Massive corruption in Unigine Sanctuary
https://bugs.freedesktop.org/show_bug.cgi?id=32634 Marek Ol??k changed: What|Removed |Added Status|NEW |RESOLVED Resolution||FIXED --- Comment #2 from Marek Ol??k 2011-01-06 10:10:23 PST --- Fixed with c60f1d8b007625f62a53010bb75e70462eb970ae. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
Linux 2.6.37
On Thu, Jan 6, 2011 at 18:49, Chris Wilson wrote:
>
> My fear is that some machines have a dependency between the backlight
> and panel power status. The patch in question changed the timing between
> turning on the panel and adjusting the backlight which would be restore
> with:
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index aa23070..0b40b4f 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
> *intel_lvds)
> ? ? ? ?I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
> ? ? ? ?POSTING_READ(lvds_reg);
>
> + ? ? ? {
> + ? ? ? ? ? ? ? u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
> + ? ? ? ? ? ? ? if (wait_for(I915_READ(reg) & PP_ON, 1000))
> + ? ? ? ? ? ? ? ? ? ? ? DRM_ERROR("timed out waiting for panel to power
> up\n");
> + ? ? ? }
> +
> ? ? ? ?intel_panel_set_backlight(dev, dev_priv->backlight_level);
> ?}
FWIW it does not compile:
CC drivers/gpu/drm/i915/intel_lvds.o
drivers/gpu/drm/i915/intel_lvds.c: In function ?intel_lvds_enable?:
drivers/gpu/drm/i915/intel_lvds.c:110: error: ?PPS_STATUS? undeclared
(first use in this function)
drivers/gpu/drm/i915/intel_lvds.c:110: error: (Each undeclared
identifier is reported only once
drivers/gpu/drm/i915/intel_lvds.c:110: error: for each function it appears in.)
make[4]: *** [drivers/gpu/drm/i915/intel_lvds.o] Error 1
Linux 2.6.37
On Thu, 6 Jan 2011 21:55:23 +0100, Alex Riesen wrote:
> On Thu, Jan 6, 2011 at 18:49, Chris Wilson
> wrote:
> >
> > My fear is that some machines have a dependency between the backlight
> > and panel power status. The patch in question changed the timing between
> > turning on the panel and adjusting the backlight which would be restore
> > with:
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> > b/drivers/gpu/drm/i915/intel_lvds.c
> > index aa23070..0b40b4f 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
> > *intel_lvds)
> > ?? ?? ?? ??I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
> > ?? ?? ?? ??POSTING_READ(lvds_reg);
> >
> > + ?? ?? ?? {
> > + ?? ?? ?? ?? ?? ?? ?? u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS :
> > PPS_STATUS;
> > + ?? ?? ?? ?? ?? ?? ?? if (wait_for(I915_READ(reg) & PP_ON, 1000))
> > + ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? DRM_ERROR("timed out waiting for panel
> > to power up\n");
> > + ?? ?? ?? }
> > +
> > ?? ?? ?? ??intel_panel_set_backlight(dev, dev_priv->backlight_level);
> > ??}
>
> FWIW it does not compile:
> CC drivers/gpu/drm/i915/intel_lvds.o
> drivers/gpu/drm/i915/intel_lvds.c: In function ???intel_lvds_enable???:
> drivers/gpu/drm/i915/intel_lvds.c:110: error: ???PPS_STATUS??? undeclared
> (first use in this function)
> drivers/gpu/drm/i915/intel_lvds.c:110: error: (Each undeclared
> identifier is reported only once
> drivers/gpu/drm/i915/intel_lvds.c:110: error: for each function it appears
> in.)
> make[4]: *** [drivers/gpu/drm/i915/intel_lvds.o] Error 1
Daniel quickly pointed out my typo: s/PPS_STATUS/PP_STATUS/
Apologies,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
Linux 2.6.37
On Thu, Jan 6, 2011 at 21:55, Alex Riesen wrote:
> On Thu, Jan 6, 2011 at 18:49, Chris Wilson
> wrote:
>>
>> My fear is that some machines have a dependency between the backlight
>> and panel power status. The patch in question changed the timing between
>> turning on the panel and adjusting the backlight which would be restore
>> with:
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
>> b/drivers/gpu/drm/i915/intel_lvds.c
>> index aa23070..0b40b4f 100644
>> --- a/drivers/gpu/drm/i915/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/intel_lvds.c
>> @@ -106,6 +106,12 @@ static void intel_lvds_enable(struct intel_lvds
>> *intel_lvds)
>> ? ? ? ?I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
>> ? ? ? ?POSTING_READ(lvds_reg);
>>
>> + ? ? ? {
>> + ? ? ? ? ? ? ? u32 reg = HAS_PCH_SPLIT(dev) ? PCH_PP_STATUS : PPS_STATUS;
...
> FWIW it does not compile:
> ?CC ? ? ?drivers/gpu/drm/i915/intel_lvds.o
> drivers/gpu/drm/i915/intel_lvds.c: In function ?intel_lvds_enable?:
> drivers/gpu/drm/i915/intel_lvds.c:110: error: ?PPS_STATUS? undeclared
Ah, I see. Should be PP_STATUS. Whatever. It does not help. The backlight
stays off.
P.S. Probably unrelated, but I just noticed that the backlight never goes
off when closing the lid. Am I supposed to hook up on the corresponding
input event and put the panel in standby? It used to work all by itself,
I think...
[Bug 32883] New: External LCD monitor slightly wiggles
https://bugs.freedesktop.org/show_bug.cgi?id=32883 Summary: External LCD monitor slightly wiggles Product: DRI Version: XOrg CVS Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/Radeon AssignedTo: dri-devel at lists.freedesktop.org ReportedBy: prijatelj.mp3 at gmail.com DESCRIPTION: picture on LCD monitor is like if it would shake very fast but very little. It's watchable but I don't think it's not healty for my eyes. This can be noticed already from boot where daemons are being loaded or when the picture comes on external LCD. I've also noticed that from time to time (it happened to me now about 3 times) this slightly wiggling thing becomes very agressive and it's on both screens. Or if I don't have external LCD it's only seen on laptop's screen. It's so agressive I'see parts, many parts of pictures covering between itself and shaking very fast.I'm forced to reboot computer since not even restarting X helps. Maybe this has something to do with slightly wiggles thing on monitor or no, I don't know. SYSTEM: - GPU: Mobility X1400 - distro: Archlinux, - kernel: kernel 2.6.36.2-1 - X.Org: 1.9.2 - xf86-video-ati: 6.13.2-2 - KMS (YES) I've tried to add radeon.disp_priority=2 but the problem is the same. I've tried to add radeon.new_pll=0 but the problem is the same. I've also tried to disable KMS with radeon.nomodeset=0 but after it I'm not able to get into X. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[Bug 32865] Frogatto (trunk r4089) crashes on startup,
https://bugs.freedesktop.org/show_bug.cgi?id=32865 Ian Romanick changed: What|Removed |Added Keywords||NEEDINFO --- Comment #1 from Ian Romanick 2011-01-06 14:00:51 PST --- The glGenFramebuffers function is part of the GL_ARB_framebuffer_object extension, and I don't think r600c supports that extension. Running 'glxinfo | grep framebuffer' will tell for sure. If this function isn't supported by the driver, it's an application bug. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[Bug 32865] Frogatto (trunk r4089) crashes on startup,
https://bugs.freedesktop.org/show_bug.cgi?id=32865 --- Comment #2 from Ignacio R. Morelle 2011-01-06 14:25:09 PST --- Indeed it's an application bug and I have now contacted the developers about it. I had originally searched for GL_EXT_framebuffer_object instead, which is supported by this driver. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #6 from Tormod Volden 2011-01-06 15:01:20 PST --- It seems to me that the frame buffer written to is tiled, and that the functions writing into it are unaware of this. I discussed shortly with Alex on IRC, and he said the savages have multiple apertures to the same framebuffer, some providing linear translation. BTW, tiling is a prerequisite for DRI on savage, so I could not check if turning off tiling would fix it. Would be nice if someone could explain how this is meant to work in mesa. I would like to continue debugging this, but I am stuck at this point without knowing how it should work. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #7 from Tormod Volden 2011-01-06 15:15:01 PST --- I googled up a discussion I had 9 months ago and have totally forgotten about (scary), which points to format reworks causing the regression: (dri-devel-2010-04-15.log) 11:50 #dri-devel: < tormod> when a GL-application splats blue spots into other windows (savage, no compiz), is that likely a drm bug? 11:52 #dri-devel: <+ajax> savage! retro. 11:54 #dri-devel: <+ajax> it's likely to be a bug in the dri driver 12:28 #dri-devel: < eosie> how large are these blue spots? 12:29 #dri-devel: < tormod> eosie, I'll try to get a screenshot 12:34 #dri-devel: < tormod> eosie, http://imagebin.ca/view/ZNojCc4.html 12:38 #dri-devel: < eosie> cool 12:40 #dri-devel: < agd5f> tormod: tiling issue 12:41 #dri-devel: < agd5f> I suspect somthing isn't using the right aperture 12:42 #dri-devel: < agd5f> IIRC, savage had several apertures exposed via the PCI BARs 12:42 #dri-devel: < agd5f> the first was the linear view, the others were tiled 12:45 #dri-devel: < tormod> I am not using that savage laptop much any longer, but I think this is new since mesa 7.6 12:45 #dri-devel: < agd5f> tormod: I'd guess a problem is the savage span code 12:46 #dri-devel: < agd5f> *in 12:46 #dri-devel: < tormod> where is the span code? 12:46 #dri-devel: < agd5f> savage_span.c 12:46 #dri-devel: < agd5f> IIRC 12:47 #dri-devel: < agd5f> but it's been ages since I looked at savage 12:47 #dri-devel: < tormod> it's been ages since anyone looked at it :) 12:48 #dri-devel: < agd5f> probably one of the format reworks broke something 12:54 #dri-devel: < tormod> yes I remember format reworks broke some other stuff, that got fixed -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[Bug 32511] glDrawPixels broken on savage
https://bugs.freedesktop.org/show_bug.cgi?id=32511 --- Comment #8 from Tormod Volden 2011-01-06 15:31:26 PST --- Is it possible that the frame buffer address gets wrongly calculated (because of wrong formats or non-initialized stuff) so that it points beyond the linear aperture and reaches inadvertently into a tiled aperture? Can I verify values in gdb against addresses listed in Xorg.0.log? I have tried writing to addresses in gdb to see if I get something on the screen but I got only errors. I don't know if DRI buffers are writable from gdb. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[PATCH 1/2] drm/radeon/kms: add pcie get/set lane support for r6xx/r7xx/evergreen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/r300.c|5 +-
drivers/gpu/drm/radeon/r600.c| 118 ++
drivers/gpu/drm/radeon/radeon.h |8 ++
drivers/gpu/drm/radeon/radeon_asic.c | 14 ++--
drivers/gpu/drm/radeon/radeon_asic.h |2 +
drivers/gpu/drm/radeon/radeon_reg.h |9 +++
6 files changed, 145 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 23fee54..fae5e70 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -558,10 +558,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
/* FIXME wait for idle */
- if (rdev->family < CHIP_R600)
- link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
- else
- link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+ link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >>
RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
case RADEON_PCIE_LC_LINK_WIDTH_X0:
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 279794c..60ad8c0 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3531,3 +3531,121 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev,
struct radeon_bo *bo)
} else
WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
}
+
+void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
+{
+ u32 link_width_cntl, mask, target_reg;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return;
+
+ /* FIXME wait for idle */
+
+ switch (lanes) {
+ case 0:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
+ break;
+ case 1:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
+ break;
+ case 2:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
+ break;
+ case 4:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
+ break;
+ case 8:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
+ break;
+ case 12:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
+ break;
+ case 16:
+ default:
+ mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
+ break;
+ }
+
+ link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+ if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
+ (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
+ return;
+
+ if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
+ return;
+
+ link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
+RADEON_PCIE_LC_RECONFIG_NOW |
+R600_PCIE_LC_RENEGOTIATE_EN |
+R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
+ link_width_cntl |= mask;
+
+ WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+
+/* some northbridges can renegotiate the link rather than requiring
+ * a complete re-config.
+ * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958,
etc.)
+ */
+if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
+ link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN |
R600_PCIE_LC_UPCONFIGURE_SUPPORT;
+else
+ link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
+
+ WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
+
RADEON_PCIE_LC_RECONFIG_NOW));
+
+if (rdev->family >= CHIP_RV770)
+ target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
+else
+ target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
+
+/* wait for lane set to complete */
+link_width_cntl = RREG32(target_reg);
+while (link_width_cntl == 0x)
+ link_width_cntl = RREG32(target_reg);
+
+}
+
+int r600_get_pcie_lanes(struct radeon_device *rdev)
+{
+ u32 link_width_cntl;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return 0;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return 0;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return 0;
+
+ /* FIXME wait for idle */
+
+ link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+ switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >>
RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
+
[PATCH 2/2] drm/radeon/kms: add support for gen2 pcie link speeds
Supported on rv6xx/r7xx/evergreen. Cards come up in gen1 mode.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c | 53 ++
drivers/gpu/drm/radeon/evergreend.h | 38 +
drivers/gpu/drm/radeon/r600.c | 102 +++
drivers/gpu/drm/radeon/r600d.h | 39 +
drivers/gpu/drm/radeon/radeon.h |2 +
drivers/gpu/drm/radeon/rv770.c | 76 ++
drivers/gpu/drm/radeon/rv770d.h | 38 +
7 files changed, 348 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index eaf4fba..11344c7 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -39,6 +39,7 @@
static void evergreen_gpu_init(struct radeon_device *rdev);
void evergreen_fini(struct radeon_device *rdev);
+static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
{
@@ -2767,6 +2768,9 @@ static int evergreen_startup(struct radeon_device *rdev)
{
int r;
+ /* enable pcie gen2 link */
+ evergreen_pcie_gen2_enable(rdev);
+
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
r = r600_init_microcode(rdev);
if (r) {
@@ -3049,3 +3053,52 @@ void evergreen_fini(struct radeon_device *rdev)
rdev->bios = NULL;
radeon_dummy_page_fini(rdev);
}
+
+static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
+{
+ u32 link_width_cntl, speed_cntl;
+
+ if (rdev->flags & RADEON_IS_IGP)
+ return;
+
+ if (!(rdev->flags & RADEON_IS_PCIE))
+ return;
+
+ /* x2 cards have a special sequence */
+ if (ASIC_IS_X2(rdev))
+ return;
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
+ (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
+
+ link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+ link_width_cntl &= ~LC_UPCONFIGURE_DIS;
+ WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+ speed_cntl |= LC_GEN2_EN_STRAP;
+ WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
+
+ } else {
+ link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
+ /* XXX: only disable it if gen1 bridge vendor == 0x111d or
0x1106 */
+ if (1)
+ link_width_cntl |= LC_UPCONFIGURE_DIS;
+ else
+ link_width_cntl &= ~LC_UPCONFIGURE_DIS;
+ WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+ }
+}
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 94140e1..b8da323 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -581,6 +581,44 @@
# define DC_HPDx_RX_INT_TIMER(x)((x) << 16)
# define DC_HPDx_EN (1 << 28)
+/* PCIE link stuff */
+#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
+#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
+# define LC_LINK_WIDTH_SHIFT0
+# define LC_LINK_WIDTH_MASK 0x7
+# define LC_LINK_WIDTH_X0 0
+# define LC_LINK_WIDTH_X1 1
+# define LC_LINK_WIDTH_X2 2
+# define LC_LINK_WIDTH_X4 3
+# define LC_LINK_WIDTH_X8 4
+# define LC_LINK_WIDTH_X16 6
+# define LC_LINK_WIDTH_RD_SHIFT 4
+# define LC_LINK_WIDTH_RD_MASK 0x70
+# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
+# define LC_RECONFIG_NOW(1 << 8)
+# define LC_RENEGOTIATION_SUPPORT (1 << 9)
+# define LC_RENEGOTIATE_EN (1 << 10)
+# define LC_SHORT_RECONFIG_EN (1 << 11)
+# define LC_UPCONFIGURE_SUPPORT (1 << 12)
+#
[Bug 29726] New CRTC ID query breaks Radeon DRM in Zaphod mode
https://bugs.freedesktop.org/show_bug.cgi?id=29726 Alex Deucher changed: What|Removed |Added CC||n0nb at n0nb.us --- Comment #12 from Alex Deucher 2011-01-06 15:54:13 PST --- *** Bug 32885 has been marked as a duplicate of this bug. *** -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
On Thu, Jan 6, 2011 at 3:16 PM, Dave Airlie wrote: > From: Dave Airlie > > This is just an idea that might or might not be a good idea, > it basically adds two ioctls to create a dumb and map a dumb buffer > suitable for scanout. The handle can be passed to the KMS ioctls to create > a framebuffer. > > It looks to me like it would be useful in the following cases: > a) in development drivers - we can always provide a shadowfb fallback. > b) libkms users - we can clean up libkms a lot and avoid linking > to libdrm_*. > c) plymouth via libkms is a lot easier. > > Userspace bits would be just calls + mmaps. We could probably > mark these handles somehow as not being suitable for acceleartion > so as top stop people who are dumber than dumb. > > Signed-off-by: Dave Airlie Looks pretty reasonable. One thing from the IRC conversation on v2 was about cursors -- were they going to be handled through this patch? ~ C. -- When the facts change, I change my mind. What do you do, sir? ~ Keynes Corbin Simpson
[PATCH] drm/radeon/kms: set the MSB of the HDP slice size
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 11344c7..b5bc7d0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1147,7 +1147,7 @@ static void evergreen_mc_program(struct radeon_device
*rdev)
tmp |= ((rdev->mc.vram_start >> 24) & 0x);
WREG32(MC_VM_FB_LOCATION, tmp);
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
- WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
WREG32(HDP_NONSURFACE_SIZE, 0x3FFF);
if (rdev->flags & RADEON_IS_AGP) {
WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
--
1.7.1.1
[PATCH] drm/radeon/kms: fix some typos in evergreen pm4 defines
Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreend.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index b8da323..36d32d8 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -648,7 +648,7 @@ #definePACKET3_NOP 0x10 #definePACKET3_SET_BASE0x11 #definePACKET3_CLEAR_STATE 0x12 -#definePACKET3_INDIRECT_BUFFER_SIZE0x13 +#definePACKET3_INDEX_BUFFER_SIZE 0x13 #definePACKET3_DISPATCH_DIRECT 0x15 #definePACKET3_DISPATCH_INDIRECT 0x16 #definePACKET3_INDIRECT_BUFFER_END 0x17 @@ -689,14 +689,14 @@ # define PACKET3_CB8_DEST_BASE_ENA(1 << 15) # define PACKET3_CB9_DEST_BASE_ENA(1 << 16) # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) -# define PACKET3_CB11_DEST_BASE_ENA (1 << 17) +# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) # define PACKET3_FULL_CACHE_ENA (1 << 20) # define PACKET3_TC_ACTION_ENA(1 << 23) # define PACKET3_VC_ACTION_ENA(1 << 24) # define PACKET3_CB_ACTION_ENA(1 << 25) # define PACKET3_DB_ACTION_ENA(1 << 26) # define PACKET3_SH_ACTION_ENA(1 << 27) -# define PACKET3_SMX_ACTION_ENA (1 << 28) +# define PACKET3_SX_ACTION_ENA(1 << 28) #definePACKET3_ME_INITIALIZE 0x44 #definePACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) #definePACKET3_COND_WRITE 0x45 -- 1.7.1.1
[PATCH] drm: dumb scanout create/mmap for intel/radeon (v3)
On Fri, 7 Jan 2011 09:16:51 +1000 Dave Airlie wrote: > From: Dave Airlie > > This is just an idea that might or might not be a good idea, > it basically adds two ioctls to create a dumb and map a dumb buffer > suitable for scanout. The handle can be passed to the KMS ioctls to create > a framebuffer. > > It looks to me like it would be useful in the following cases: > a) in development drivers - we can always provide a shadowfb fallback. > b) libkms users - we can clean up libkms a lot and avoid linking > to libdrm_*. > c) plymouth via libkms is a lot easier. > > Userspace bits would be just calls + mmaps. We could probably > mark these handles somehow as not being suitable for acceleartion > so as top stop people who are dumber than dumb. Would extracting libwfb from the server and providing it as a standalone fb access API from the server also fill these needs? It would be a bigger API, but presumably would allow us to share fbs between early boot and subsequent, accelerated usage. We'd still need to settle on the basic allocation API, but we seem to manage that on the server side... -- Jesse Barnes, Intel Open Source Technology Center
[Bug 32887] New: [r600g] SIGSEGV src/gallium/drivers/r600/r600_state.c:237
https://bugs.freedesktop.org/show_bug.cgi?id=32887
Summary: [r600g] SIGSEGV
src/gallium/drivers/r600/r600_state.c:237
Product: Mesa
Version: git
Platform: x86 (IA32)
OS/Version: Linux (All)
Status: NEW
Severity: critical
Priority: medium
Component: Drivers/Gallium/r600
AssignedTo: dri-devel at lists.freedesktop.org
ReportedBy: vlee at vmware.com
mesa: 6d9ca78ef7bf831b9b63f4bda68623cbae627508 (master)
chipset: RV620
system architecture: i686
libdrm-dev: 2.14.21-1ubuntu2.1
kernel version: 2.6.35-24-generic
Linux distribution: Ubuntu 10.10 i386
Run piglit fbo-generatemipmap-formats test.
$ ./bin/fbo-generatemipmap-formats -auto
Using test set: Core formats
Testing 3
Testing 4
Testing GL_RGB
Testing GL_RGBA
Testing GL_ALPHA
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_LUMINANCE
Probe at (1,1)
Expected: 1.00 1.00 1.00 1.00
Observed: 0.00 0.00 0.00 1.00
Testing GL_LUMINANCE_ALPHA
Testing GL_INTENSITY
Probe at (1,1)
Expected: 1.00 1.00 1.00 1.00
Observed: 0.00 0.00 0.00 0.00
Testing GL_ALPHA4
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_ALPHA8
Probe at (129,1)
Expected: 1.00 1.00 1.00 0.25
Observed: 1.00 1.00 1.00 0.00
Testing GL_ALPHA12
Segmentation fault (core dumped)
Program terminated with signal 11, Segmentation fault.
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
237if (rctx->vertex_elements->count <
rctx->vs_shader->shader.bc.nresource) {
(gdb) bt
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
#1 0x011087c9 in r600_draw_vbo (ctx=0x8fdad50, info=0xbf953c34) at
src/gallium/drivers/r600/r600_state.c:307
#2 0x0125fbcd in st_draw_vbo (ctx=0x92ec4b0, arrays=0x932e590,
prims=0xbf953cdc, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001', min_index=0,
max_index=3) at src/mesa/state_tracker/st_draw.c:732
#3 0x012e5961 in vbo_draw_arrays (ctx=0x92ec4b0, mode=7, start=0, count=4,
numInstances=1) at src/mesa/vbo/vbo_exec_array.c:588
#4 0x012e5ac8 in vbo_exec_DrawArrays (mode=7, start=0, count=4) at
src/mesa/vbo/vbo_exec_array.c:619
#5 0x0804d636 in piglit_draw_rect_tex ()
#6 0x0804b4e3 in draw_mipmap ()
#7 0x0804bbd9 in test_format ()
#8 0x0804bd02 in piglit_display ()
#9 0x0804de93 in display ()
#10 0x00a8b820 in fghRedrawWindow (window=DWARF-2 expression error: DW_OP_reg
operations must be used either alone or in conjuction with DW_OP_piece or
DW_OP_bit_piece.
) at freeglut_main.c:210
#11 fghcbDisplayWindow (window=DWARF-2 expression error: DW_OP_reg operations
must be used either alone or in conjuction with DW_OP_piece or DW_OP_bit_piece.
) at freeglut_main.c:227
#12 0x00a8f660 in fgEnumWindows (enumCallback=0xa8b790 ,
enumerator=0xbf953f88) at freeglut_structure.c:394
#13 0x00a8bcdb in fghDisplayAll () at freeglut_main.c:249
#14 glutMainLoopEvent () at freeglut_main.c:1450
#15 0x00a8c605 in glutMainLoop () at freeglut_main.c:1498
#16 0x0804e03c in main ()
(gdb) frame 0
#0 0x01108338 in r600_draw_common (draw=0xbf9537b4) at
src/gallium/drivers/r600/r600_state.c:237
237if (rctx->vertex_elements->count <
rctx->vs_shader->shader.bc.nresource) {
(gdb) print rctx->vertex_elements
$1 = (struct r600_vertex_element *) 0x0
--
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
You are the assignee for the bug.
[Bug 32887] [r600g] SIGSEGV src/gallium/drivers/r600/r600_state.c:237
https://bugs.freedesktop.org/show_bug.cgi?id=32887 --- Comment #1 from Vinson Lee 2011-01-06 18:00:24 PST --- 876effb0e717e8e64050662f6ffa286c22065f5c is the first bad commit commit 876effb0e717e8e64050662f6ffa286c22065f5c Author: Dave Airlie Date: Fri Dec 24 17:33:41 2010 +1000 r600g: hack around property unknown issues. should fix https://bugs.freedesktop.org/show_bug.cgi?id=32619 Need to add proper support for properties later. Signed-off-by: Dave Airlie :04 04 fcc05c38e5c4f2c44622a99f64bc09dd3c6af879 f84be8bf6e3f262d1f5dd2d2445b73f434a2d0b3 Msrc bisect run success -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug.
[PATCH 0/25] drm/radeon/kms: Add support for NI (Northern Islands)
This patchset adds support for evergreen+ based NI asics (Barts, Turks, and Caicos). It includes full acceleration (2D and 3D) for these asics. Mesa 7.10 or git master and xf86-video-ati from git master are required. There is no support for UMS, KMS is required. The 3D engine on Barts, Turks, and Caicos is based and evergreen and is programmed similarly. The big change is the display block (DCE5) which includes new features such as improved color correction, HDMI 1.4a, and DP 1.2. New ucode is required and is available here: http://people.freedesktop.org/~agd5f/radeon_ucode/ The vbios no longer loads the MC (memory controller) ucode during asic init, so the driver now has to load it. Support for Cayman (Radeon HD 69xx asics) is in progress, but not yet ready for release. Alex
[PATCH 01/25] drm/radeon/kms: clean up ASIC_IS_DCE41() macro
only fusion asics are dce4.1
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |3 ++-
drivers/gpu/drm/radeon/radeon_encoders.c |6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3e635c6..396e307 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1335,7 +1335,8 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
-#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM))
+#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
+(rdev->flags & RADEON_IS_IGP))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 55b84b8..c83ad89 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1329,7 +1329,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
switch (mode) {
case DRM_MODE_DPMS_ON:
default:
- if (ASIC_IS_DCE41(rdev) && (rdev->flags &
RADEON_IS_IGP))
+ if (ASIC_IS_DCE41(rdev))
action =
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
else
action = ATOM_ENABLE;
@@ -1337,7 +1337,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- if (ASIC_IS_DCE41(rdev) && (rdev->flags &
RADEON_IS_IGP))
+ if (ASIC_IS_DCE41(rdev))
action =
EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
else
action = ATOM_DISABLE;
@@ -1663,7 +1663,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
}
if (ext_encoder) {
- if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) {
+ if (ASIC_IS_DCE41(rdev)) {
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
atombios_external_encoder_setup(encoder, ext_encoder,
--
1.7.1.1
[PATCH 02/25] drm/radeon/kms: add NI chip families
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_device.c |3 +++
drivers/gpu/drm/radeon/radeon_family.h |3 +++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 396e307..73730fd 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1337,6 +1337,7 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
(rdev->flags & RADEON_IS_IGP))
+#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 44cf0d7..e353430 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -82,6 +82,9 @@ static const char radeon_family_name[][16] = {
"CYPRESS",
"HEMLOCK",
"PALM",
+ "BARTS",
+ "TURKS",
+ "CAICOS",
"LAST",
};
diff --git a/drivers/gpu/drm/radeon/radeon_family.h
b/drivers/gpu/drm/radeon/radeon_family.h
index 4c222d5..1ca55eb 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -81,6 +81,9 @@ enum radeon_family {
CHIP_CYPRESS,
CHIP_HEMLOCK,
CHIP_PALM,
+ CHIP_BARTS,
+ CHIP_TURKS,
+ CHIP_CAICOS,
CHIP_LAST,
};
--
1.7.1.1
[PATCH 03/25] drm/radeon/kms: update display watermark calculations for DCE5
Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen.c | 20 1 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index b5bc7d0..9c990c3 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -401,16 +401,28 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, case 0: case 4: default: - return 3840 * 2; + if (ASIC_IS_DCE5(rdev)) + return 4096 * 2; + else + return 3840 * 2; case 1: case 5: - return 5760 * 2; + if (ASIC_IS_DCE5(rdev)) + return 6144 * 2; + else + return 5760 * 2; case 2: case 6: - return 7680 * 2; + if (ASIC_IS_DCE5(rdev)) + return 8192 * 2; + else + return 7680 * 2; case 3: case 7: - return 1920 * 2; + if (ASIC_IS_DCE5(rdev)) + return 2048 * 2; + else + return 1920 * 2; } } -- 1.7.1.1
[PATCH 04/25] drm/radeon/kms: DCE5 supports 16k display surfaces
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_display.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
b/drivers/gpu/drm/radeon/radeon_display.c
index acebbc7..30d867c 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1119,7 +1119,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
- if (ASIC_IS_AVIVO(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ rdev->ddev->mode_config.max_width = 16384;
+ rdev->ddev->mode_config.max_height = 16384;
+ } else if (ASIC_IS_AVIVO(rdev)) {
rdev->ddev->mode_config.max_width = 8192;
rdev->ddev->mode_config.max_height = 8192;
} else {
--
1.7.1.1
[PATCH 05/25] drm/radeon/kms: DCE5 atom SetPixelClock updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 31 +++--
drivers/gpu/drm/radeon/radeon_atombios.c | 25 ++-
2 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9fbabaa..b3e5e75 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -673,9 +673,14 @@ union set_pixel_clock {
PIXEL_CLOCK_PARAMETERS_V2 v2;
PIXEL_CLOCK_PARAMETERS_V3 v3;
PIXEL_CLOCK_PARAMETERS_V5 v5;
+ PIXEL_CLOCK_PARAMETERS_V6 v6;
};
-static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
+/* on DCE5, make sure the voltage is high enough to support the
+ * required disp clk.
+ */
+static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
+ u32 dispclk)
{
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
@@ -698,9 +703,16 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
* SetPixelClock provides the dividers
*/
args.v5.ucCRTC = ATOM_CRTC_INVALID;
- args.v5.usPixelClock = rdev->clock.default_dispclk;
+ args.v5.usPixelClock = dispclk;
args.v5.ucPpll = ATOM_DCPLL;
break;
+ case 6:
+ /* if the default dcpll clock is specified,
+* SetPixelClock provides the dividers
+*/
+ args.v6.ulDispEngClkFreq = dispclk;
+ args.v6.ucPpll = ATOM_DCPLL;
+ break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
return;
@@ -784,6 +796,18 @@ static void atombios_crtc_program_pll(struct drm_crtc
*crtc,
args.v5.ucEncoderMode = encoder_mode;
args.v5.ucPpll = pll_id;
break;
+ case 6:
+ args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
+ args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock
/ 10);
+ args.v6.ucRefDiv = ref_div;
+ args.v6.usFbDiv = cpu_to_le16(fb_div);
+ args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div *
10);
+ args.v6.ucPostDiv = post_div;
+ args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
+ args.v6.ucTransmitterID = encoder_id;
+ args.v6.ucEncoderMode = encoder_mode;
+ args.v6.ucPpll = pll_id;
+ break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
return;
@@ -1377,7 +1401,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
rdev->clock.default_dispclk);
if (ss_enabled)
atombios_crtc_program_ss(crtc, ATOM_DISABLE,
ATOM_DCPLL, &ss);
- atombios_crtc_set_dcpll(crtc);
+ /* XXX: DCE5, make sure voltage, dispclk is high enough */
+ atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
if (ss_enabled)
atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL,
&ss);
}
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index e4f7e3e..11573d0 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1086,6 +1086,7 @@ union firmware_info {
ATOM_FIRMWARE_INFO_V1_3 info_13;
ATOM_FIRMWARE_INFO_V1_4 info_14;
ATOM_FIRMWARE_INFO_V2_1 info_21;
+ ATOM_FIRMWARE_INFO_V2_2 info_22;
};
bool radeon_atom_get_clock_info(struct drm_device *dev)
@@ -1160,8 +1161,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
*p2pll = *p1pll;
/* system clock */
- spll->reference_freq =
- le16_to_cpu(firmware_info->info.usReferenceClock);
+ if (ASIC_IS_DCE4(rdev))
+ spll->reference_freq =
+
le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
+ else
+ spll->reference_freq =
+
le16_to_cpu(firmware_info->info.usReferenceClock);
spll->reference_div = 0;
spll->pll_out_min =
@@ -1183,8 +1188,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
/* memory clock */
- mpll->reference_f
[PATCH 06/25] drm/radeon/kms: DCE5 atom spread spectrum updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index b3e5e75..b0ab185 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -403,6 +403,7 @@ union atom_enable_ss {
ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
+ ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
};
static void atombios_crtc_program_ss(struct drm_crtc *crtc,
@@ -417,7 +418,30 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
memset(&args, 0, sizeof(args));
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ args.v3.usSpreadSpectrumAmountFrac = 0;
+ args.v3.ucSpreadSpectrumType = ss->type;
+ switch (pll_id) {
+ case ATOM_PPLL1:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_P1PLL;
+ args.v3.usSpreadSpectrumAmount = ss->amount;
+ args.v3.usSpreadSpectrumStep = ss->step;
+ break;
+ case ATOM_PPLL2:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_P2PLL;
+ args.v3.usSpreadSpectrumAmount = ss->amount;
+ args.v3.usSpreadSpectrumStep = ss->step;
+ break;
+ case ATOM_DCPLL:
+ args.v3.ucSpreadSpectrumType |=
ATOM_PPLL_SS_TYPE_V3_DCPLL;
+ args.v3.usSpreadSpectrumAmount = 0;
+ args.v3.usSpreadSpectrumStep = 0;
+ break;
+ case ATOM_PPLL_INVALID:
+ return;
+ }
+ args.v2.ucEnable = enable;
+ } else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage =
cpu_to_le16(ss->percentage);
args.v2.ucSpreadSpectrumType = ss->type;
switch (pll_id) {
--
1.7.1.1
[PATCH 07/25] drm/radeon/kms: DCE5 atom transmitter control updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 19 ++-
1 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index c83ad89..76835b0 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -712,7 +712,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
* - 2 DIG encoder blocks.
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
*
- * DCE 4.0
+ * DCE 4.0/5.0
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
* Supports up to 6 digital outputs
* - 6 DIG encoder blocks.
@@ -829,6 +829,7 @@ union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
};
void
@@ -923,10 +924,18 @@ atombios_dig_transmitter_setup(struct drm_encoder
*encoder, int action, uint8_t
struct radeon_crtc *radeon_crtc =
to_radeon_crtc(encoder->crtc);
pll_id = radeon_crtc->pll_id;
}
- if (is_dp && rdev->clock.dp_extclk)
- args.v3.acConfig.ucRefClkSource = 2; /* external src */
- else
- args.v3.acConfig.ucRefClkSource = pll_id;
+
+ if (ASIC_IS_DCE5(rdev)) {
+ if (is_dp && rdev->clock.dp_extclk)
+ args.v4.acConfig.ucRefClkSource = 3; /*
external src */
+ else
+ args.v4.acConfig.ucRefClkSource = pll_id;
+ } else {
+ if (is_dp && rdev->clock.dp_extclk)
+ args.v3.acConfig.ucRefClkSource = 2; /*
external src */
+ else
+ args.v3.acConfig.ucRefClkSource = pll_id;
+ }
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
--
1.7.1.1
[PATCH 08/25] drm/radeon/kms: DCE5 atom dig encoder updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 31 +
1 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 76835b0..989ba26 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -743,6 +743,7 @@ union dig_encoder_control {
DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
+ DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
};
void
@@ -758,6 +759,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int
action)
uint8_t frev, crev;
int dp_clock = 0;
int dp_lane_count = 0;
+ int hpd_id = RADEON_HPD_NONE;
if (connector) {
struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
@@ -766,6 +768,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int
action)
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
+ hpd_id = radeon_connector->hpd.hpd;
}
/* no dig encoder assigned */
@@ -790,19 +793,36 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder,
int action)
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
- if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
- if (dp_clock == 27)
- args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
+ (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
args.v1.ucLaneNum = dp_lane_count;
- } else if (radeon_encoder->pixel_clock > 165000)
+ else if (radeon_encoder->pixel_clock > 165000)
args.v1.ucLaneNum = 8;
else
args.v1.ucLaneNum = 4;
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE5(rdev)) {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
+ (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
+ if (dp_clock == 27)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
+ else if (dp_clock == 54)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
+ }
+ args.v4.acConfig.ucDigSel = dig->dig_encoder;
+ args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ if (hpd_id == RADEON_HPD_NONE)
+ args.v4.ucHPD_ID = 0;
+ else
+ args.v4.ucHPD_ID = hpd_id + 1;
+ } else if (ASIC_IS_DCE4(rdev)) {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) &&
(dp_clock == 27))
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
args.v3.acConfig.ucDigSel = dig->dig_encoder;
args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
} else {
+ if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) &&
(dp_clock == 27))
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
@@ -1538,6 +1558,7 @@ static int radeon_atom_pick_dig_encoder(struct
drm_encoder *encoder)
struct radeon_encoder_atom_dig *dig;
uint32_t dig_enc_in_use = 0;
+ /* DCE4/5 */
if (ASIC_IS_DCE4(rdev)) {
dig = radeon_encoder->enc_priv;
if (ASIC_IS_DCE41(rdev)) {
--
1.7.1.1
[PATCH 09/25] drm/radeon/kms: dac dpms updates for DCE5
The DAC1OutputControl table was removed for DCE5.
DAC1EncoderControl now handles everything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 28 ++--
1 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 989ba26..2e1d720 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1227,6 +1227,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
int index = 0;
bool is_dig = false;
+ bool is_dce5_dac = false;
memset(&args, 0, sizeof(args));
@@ -1265,12 +1266,16 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
- index = GetIndexIntoMasterTable(COMMAND,
TV1OutputControl);
- else if (radeon_encoder->active_device &
(ATOM_DEVICE_CV_SUPPORT))
- index = GetIndexIntoMasterTable(COMMAND,
CV1OutputControl);
- else
- index = GetIndexIntoMasterTable(COMMAND,
DAC1OutputControl);
+ if (ASIC_IS_DCE5(rdev))
+ is_dce5_dac = true;
+ else {
+ if (radeon_encoder->active_device &
(ATOM_DEVICE_TV_SUPPORT))
+ index = GetIndexIntoMasterTable(COMMAND,
TV1OutputControl);
+ else if (radeon_encoder->active_device &
(ATOM_DEVICE_CV_SUPPORT))
+ index = GetIndexIntoMasterTable(COMMAND,
CV1OutputControl);
+ else
+ index = GetIndexIntoMasterTable(COMMAND,
DAC1OutputControl);
+ }
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
@@ -1329,6 +1334,17 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
atombios_dig_transmitter_setup(encoder,
ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
break;
}
+ } else if (is_dce5_dac) {
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ atombios_dac_setup(encoder, ATOM_ENABLE);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ atombios_dac_setup(encoder, ATOM_DISABLE);
+ break;
+ }
} else {
switch (mode) {
case DRM_MODE_DPMS_ON:
--
1.7.1.1
[PATCH 10/25] drm/radeon/kms: dvo dpms updates for DCE5
The DVOOutputControl table was removed for DCE5.
DVOEncoderControl now handles everything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_encoders.c | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 2e1d720..3866c64 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1228,6 +1228,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
int index = 0;
bool is_dig = false;
bool is_dce5_dac = false;
+ bool is_dce5_dvo = false;
memset(&args, 0, sizeof(args));
@@ -1250,7 +1251,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
- if (ASIC_IS_DCE3(rdev))
+ if (ASIC_IS_DCE5(rdev))
+ is_dce5_dvo = true;
+ else if (ASIC_IS_DCE3(rdev))
is_dig = true;
else
index = GetIndexIntoMasterTable(COMMAND,
DVOOutputControl);
@@ -1345,6 +1348,17 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder,
int mode)
atombios_dac_setup(encoder, ATOM_DISABLE);
break;
}
+ } else if (is_dce5_dvo) {
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ atombios_dvo_setup(encoder, ATOM_ENABLE);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ atombios_dvo_setup(encoder, ATOM_DISABLE);
+ break;
+ }
} else {
switch (mode) {
case DRM_MODE_DPMS_ON:
--
1.7.1.1
[PATCH 11/25] drm/radeon/kms: parse DCE5 encoder caps when setting up encoders
Needed to tell which DIG encoders are HBR2 capable for DP 1.2.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c | 44 +++--
drivers/gpu/drm/radeon/radeon_encoders.c |6 +++-
drivers/gpu/drm/radeon/radeon_mode.h |1 +
3 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 11573d0..a2dfe25 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -37,7 +37,7 @@ radeon_get_encoder_enum(struct drm_device *dev, uint32_t
supported_device,
extern void radeon_link_encoder_connector(struct drm_device *dev);
extern void
radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
- uint32_t supported_device);
+ uint32_t supported_device, u16 caps);
/* from radeon_connector.c */
extern void
@@ -537,6 +537,7 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
u16 size, data_offset;
u8 frev, crev;
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+ ATOM_ENCODER_OBJECT_TABLE *enc_obj;
ATOM_OBJECT_TABLE *router_obj;
ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
ATOM_OBJECT_HEADER *obj_header;
@@ -561,6 +562,9 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
(ctx->bios + data_offset +
le16_to_cpu(obj_header->usConnectorObjectTableOffset));
+ enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
+ (ctx->bios + data_offset +
+le16_to_cpu(obj_header->usEncoderObjectTableOffset));
router_obj = (ATOM_OBJECT_TABLE *)
(ctx->bios + data_offset +
le16_to_cpu(obj_header->usRouterObjectTableOffset));
@@ -666,14 +670,35 @@ bool
radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER)
{
- u16 encoder_obj =
le16_to_cpu(path->usGraphicObjIds[j]);
-
- radeon_add_atom_encoder(dev,
- encoder_obj,
- le16_to_cpu
- (path->
-usDeviceTag));
+ for (k = 0; k <
enc_obj->ucNumberOfObjects; k++) {
+ u16 encoder_obj =
le16_to_cpu(enc_obj->asObjects[k].usObjectID);
+ if
(le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
+
ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
+ (ctx->bios +
data_offset +
+
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
+ ATOM_ENCODER_CAP_RECORD
*cap_record;
+ u16 caps = 0;
+ while
(record->ucRecordType > 0 &&
+
record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
+ switch
(record->ucRecordType) {
+ case
ATOM_ENCODER_CAP_RECORD_TYPE:
+
cap_record =(ATOM_ENCODER_CAP_RECORD *)
+
record;
+ caps =
le16_to_cpu(cap_record->usEncoderCap);
+ break;
+ }
+ record =
(ATOM_COMMON_RECORD_HEADER *)
+ ((char
*)record + record->ucRecordSize);
+ }
+
radeon_add_atom_encoder(dev,
+
encoder_obj,
+
le16_to_cpu
+
(path->
+
[PATCH 12/25] drm/radeon/kms: handle NI thermal controller
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_atombios.c |6 ++
drivers/gpu/drm/radeon/radeon_pm.c |1 +
3 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 73730fd..5598f95 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -739,6 +739,7 @@ enum radeon_int_thermal_type {
THERMAL_TYPE_RV770,
THERMAL_TYPE_EVERGREEN,
THERMAL_TYPE_SUMO,
+ THERMAL_TYPE_NI,
};
struct radeon_voltage {
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index a2dfe25..03f1c9a 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1891,6 +1891,7 @@ static const char *pp_lib_thermal_controller_names[] = {
"Evergreen",
"emc2103",
"Sumo",
+ "Northern Islands",
};
union power_info {
@@ -2154,6 +2155,11 @@ static void
radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
+ } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_NISLANDS) {
+ DRM_INFO("Internal thermal controller %s fan control\n",
+(controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
+ rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
} else if ((controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
(controller->ucType ==
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 0afd26c..7ad2e1a 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -440,6 +440,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
temp = rv770_get_temp(rdev);
break;
case THERMAL_TYPE_EVERGREEN:
+ case THERMAL_TYPE_NI:
temp = evergreen_get_temp(rdev);
break;
case THERMAL_TYPE_SUMO:
--
1.7.1.1
